From 28b551bfe3cff583615f677a6498b3f2ba94b159 Mon Sep 17 00:00:00 2001 From: Jamie <48308473+JamieTx@users.noreply.github.com> Date: Fri, 6 May 2022 09:28:21 +0800 Subject: Add the BSP of HC32 series. (#5905) * Add the BSP of HC32 series. --- bsp/hc32/README.md | 22 + ...210\266\344\275\234\346\225\231\347\250\213.md" | 2 + ...275\277\347\224\250\346\225\231\347\250\213.md" | 1 + ...251\261\345\212\250\344\273\213\347\273\215.md" | 2 + bsp/hc32/ev_hc32f4a0_lqfp176/.config | 702 + bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore | 42 + bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig | 21 + bsp/hc32/ev_hc32f4a0_lqfp176/README.md | 116 + bsp/hc32/ev_hc32f4a0_lqfp176/SConscript | 15 + bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct | 60 + .../ev_hc32f4a0_lqfp176/applications/SConscript | 11 + bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c | 33 + bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig | 372 + bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript | 36 + bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c | 160 + bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h | 42 + bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c | 279 + bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h | 110 + .../ev_hc32f4a0_lqfp176/board/config/adc_config.h | 90 + .../ev_hc32f4a0_lqfp176/board/config/can_config.h | 42 + .../ev_hc32f4a0_lqfp176/board/config/dma_config.h | 202 + .../ev_hc32f4a0_lqfp176/board/config/eth_config.h | 39 + .../ev_hc32f4a0_lqfp176/board/config/gpio_config.h | 174 + .../ev_hc32f4a0_lqfp176/board/config/spi_config.h | 321 + .../ev_hc32f4a0_lqfp176/board/config/tim_config.h | 80 + .../ev_hc32f4a0_lqfp176/board/config/uart_config.h | 579 + bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h | 34 + bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h | 210 + .../board/linker_scripts/link.icf | 51 + .../board/linker_scripts/link.ld | 267 + .../board/linker_scripts/link.sct | 15 + .../ev_hc32f4a0_lqfp176/board/ports/spi_flash.c | 46 + bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c | 319 + bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h | 135 + bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg | Bin 0 -> 492661 bytes bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd | 2966 + bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp | 2187 + bsp/hc32/ev_hc32f4a0_lqfp176/project.eww | 10 + bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx | 189 + bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx | 817 + bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h | 202 + bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py | 150 + bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp | 1925 + bsp/hc32/ev_hc32f4a0_lqfp176/template.eww | 10 + bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx | 189 + bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx | 390 + bsp/hc32/libraries/.ignore_format.yml | 6 + bsp/hc32/libraries/Kconfig | 22 + bsp/hc32/libraries/hc32_drivers/Kconfig | 26 + bsp/hc32/libraries/hc32_drivers/SConscript | 74 + bsp/hc32/libraries/hc32_drivers/drv_adc.c | 217 + bsp/hc32/libraries/hc32_drivers/drv_adc.h | 77 + bsp/hc32/libraries/hc32_drivers/drv_can.c | 614 + bsp/hc32/libraries/hc32_drivers/drv_can.h | 38 + bsp/hc32/libraries/hc32_drivers/drv_dma.h | 40 + bsp/hc32/libraries/hc32_drivers/drv_eth.c | 642 + bsp/hc32/libraries/hc32_drivers/drv_eth.h | 82 + bsp/hc32/libraries/hc32_drivers/drv_gpio.c | 505 + bsp/hc32/libraries/hc32_drivers/drv_gpio.h | 31 + bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c | 551 + bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h | 145 + bsp/hc32/libraries/hc32_drivers/drv_irq.c | 73 + bsp/hc32/libraries/hc32_drivers/drv_irq.h | 59 + bsp/hc32/libraries/hc32_drivers/drv_log.h | 27 + .../libraries/hc32_drivers/drv_pulse_encoder.c | 472 + .../libraries/hc32_drivers/drv_pulse_encoder.h | 241 + bsp/hc32/libraries/hc32_drivers/drv_pwm.c | 525 + bsp/hc32/libraries/hc32_drivers/drv_rtc.c | 195 + bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c | 252 + bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h | 104 + bsp/hc32/libraries/hc32_drivers/drv_spi.c | 877 + bsp/hc32/libraries/hc32_drivers/drv_spi.h | 60 + bsp/hc32/libraries/hc32_drivers/drv_usart.c | 1345 + bsp/hc32/libraries/hc32_drivers/drv_usart.h | 96 + bsp/hc32/libraries/hc32f4a0_ddl/LICENSE | 29 + bsp/hc32/libraries/hc32f4a0_ddl/README.txt | 4 + bsp/hc32/libraries/hc32f4a0_ddl/SConscript | 74 + .../config/flashloader/FlashHC32F4A0.mac | 16 + .../config/flashloader/FlashHC32F4A0.out | Bin 0 -> 47100 bytes .../config/flashloader/FlashHC32F4A0_otp.flash | 10 + .../config/flashloader/FlashHC32F4A0_otp.out | Bin 0 -> 47280 bytes .../config/flashloader/FlashHC32F4A0_qspi.flash | 9 + .../config/flashloader/FlashHC32F4A0_qspi.out | Bin 0 -> 49892 bytes .../config/flashloader/FlashHC32F4A0xG.flash | 10 + .../config/flashloader/FlashHC32F4A0xI.flash | 10 + .../config/flashloader/HC32F4A0xG.board | 18 + .../config/flashloader/HC32F4A0xI.board | 18 + .../hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf | 51 + .../hc32f4a0_ddl/config/linker/HC32F4A0xG.icf | 53 + .../hc32f4a0_ddl/config/linker/HC32F4A0xI.icf | 53 + .../cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h | 23785 ++++ .../cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h | 66 + .../Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h | 142 + .../Source/ARM/flashloader/HC32F4A0_1M.FLM | Bin 0 -> 25216 bytes .../Source/ARM/flashloader/HC32F4A0_2M.FLM | Bin 0 -> 30276 bytes .../Source/ARM/flashloader/HC32F4A0_RAM.FLM | Bin 0 -> 13664 bytes .../Source/ARM/flashloader/HC32F4A0_otp.FLM | Bin 0 -> 29692 bytes .../HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini | 16 + .../HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR | Bin 0 -> 3121534 bytes .../HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s | 594 + .../HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xG.ld | 208 + .../HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xI.ld | 208 + .../HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S | 529 + .../HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F4A0.svd | 102653 ++++++++++++++++++ .../Source/IAR/flashloader/FlashHC32F4A0.mac | 16 + .../Source/IAR/flashloader/FlashHC32F4A0.out | Bin 0 -> 47100 bytes .../Source/IAR/flashloader/FlashHC32F4A0_otp.out | Bin 0 -> 47280 bytes .../hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf | 51 + .../HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf | 51 + .../HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf | 51 + .../HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s | 970 + .../HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F4A0.svd | 102653 ++++++++++++++++++ .../Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c | 241 + .../drivers/cmsis/Include/arm_common_tables.h | 517 + .../drivers/cmsis/Include/arm_const_structs.h | 76 + .../drivers/cmsis/Include/arm_helium_utils.h | 348 + .../hc32f4a0_ddl/drivers/cmsis/Include/arm_math.h | 8970 ++ .../drivers/cmsis/Include/arm_mve_tables.h | 235 + .../drivers/cmsis/Include/arm_vec_math.h | 372 + .../drivers/cmsis/Include/cachel1_armv7.h | 411 + .../drivers/cmsis/Include/cmsis_armcc.h | 885 + .../drivers/cmsis/Include/cmsis_armclang.h | 1467 + .../drivers/cmsis/Include/cmsis_armclang_ltm.h | 1893 + .../drivers/cmsis/Include/cmsis_compiler.h | 283 + .../hc32f4a0_ddl/drivers/cmsis/Include/cmsis_gcc.h | 2177 + .../drivers/cmsis/Include/cmsis_iccarm.h | 968 + .../drivers/cmsis/Include/cmsis_version.h | 39 + .../drivers/cmsis/Include/core_armv81mml.h | 4191 + .../drivers/cmsis/Include/core_armv8mbl.h | 2222 + .../drivers/cmsis/Include/core_armv8mml.h | 3196 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm0.h | 952 + .../drivers/cmsis/Include/core_cm0plus.h | 1087 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm1.h | 979 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm23.h | 2297 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm3.h | 1943 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm33.h | 3264 + .../drivers/cmsis/Include/core_cm35p.h | 3264 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm4.h | 2129 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm55.h | 4215 + .../hc32f4a0_ddl/drivers/cmsis/Include/core_cm7.h | 2362 + .../drivers/cmsis/Include/core_sc000.h | 1030 + .../drivers/cmsis/Include/core_sc300.h | 1917 + .../hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv7.h | 275 + .../hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv8.h | 352 + .../hc32f4a0_ddl/drivers/cmsis/Include/pmu_armv8.h | 337 + .../drivers/cmsis/Include/tz_context.h | 70 + .../drivers/hc32_ll_driver/inc/hc32_ll.h | 369 + .../drivers/hc32_ll_driver/inc/hc32_ll_adc.h | 518 + .../drivers/hc32_ll_driver/inc/hc32_ll_aes.h | 115 + .../drivers/hc32_ll_driver/inc/hc32_ll_aos.h | 187 + .../drivers/hc32_ll_driver/inc/hc32_ll_can.h | 717 + .../drivers/hc32_ll_driver/inc/hc32_ll_clk.h | 779 + .../drivers/hc32_ll_driver/inc/hc32_ll_cmp.h | 435 + .../drivers/hc32_ll_driver/inc/hc32_ll_crc.h | 161 + .../drivers/hc32_ll_driver/inc/hc32_ll_ctc.h | 198 + .../drivers/hc32_ll_driver/inc/hc32_ll_dac.h | 191 + .../drivers/hc32_ll_driver/inc/hc32_ll_dcu.h | 297 + .../drivers/hc32_ll_driver/inc/hc32_ll_def.h | 378 + .../drivers/hc32_ll_driver/inc/hc32_ll_dma.h | 620 + .../drivers/hc32_ll_driver/inc/hc32_ll_dmc.h | 416 + .../drivers/hc32_ll_driver/inc/hc32_ll_dvp.h | 296 + .../drivers/hc32_ll_driver/inc/hc32_ll_efm.h | 680 + .../drivers/hc32_ll_driver/inc/hc32_ll_emb.h | 509 + .../drivers/hc32_ll_driver/inc/hc32_ll_eth.h | 2459 + .../hc32_ll_driver/inc/hc32_ll_event_port.h | 233 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcg.h | 254 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcm.h | 294 + .../drivers/hc32_ll_driver/inc/hc32_ll_fmac.h | 203 + .../drivers/hc32_ll_driver/inc/hc32_ll_gpio.h | 485 + .../drivers/hc32_ll_driver/inc/hc32_ll_hash.h | 214 + .../drivers/hc32_ll_driver/inc/hc32_ll_hrpwm.h | 139 + .../drivers/hc32_ll_driver/inc/hc32_ll_i2c.h | 319 + .../drivers/hc32_ll_driver/inc/hc32_ll_i2s.h | 347 + .../drivers/hc32_ll_driver/inc/hc32_ll_icg.h | 465 + .../hc32_ll_driver/inc/hc32_ll_interrupts.h | 591 + .../drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h | 239 + .../drivers/hc32_ll_driver/inc/hc32_ll_mau.h | 120 + .../drivers/hc32_ll_driver/inc/hc32_ll_mpu.h | 394 + .../drivers/hc32_ll_driver/inc/hc32_ll_nfc.h | 591 + .../drivers/hc32_ll_driver/inc/hc32_ll_ots.h | 202 + .../drivers/hc32_ll_driver/inc/hc32_ll_pwc.h | 693 + .../drivers/hc32_ll_driver/inc/hc32_ll_qspi.h | 445 + .../drivers/hc32_ll_driver/inc/hc32_ll_rmu.h | 130 + .../drivers/hc32_ll_driver/inc/hc32_ll_rtc.h | 459 + .../drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h | 763 + .../drivers/hc32_ll_driver/inc/hc32_ll_smc.h | 396 + .../drivers/hc32_ll_driver/inc/hc32_ll_spi.h | 432 + .../drivers/hc32_ll_driver/inc/hc32_ll_sram.h | 235 + .../drivers/hc32_ll_driver/inc/hc32_ll_swdt.h | 226 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h | 227 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr2.h | 352 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h | 801 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h | 917 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmra.h | 556 + .../drivers/hc32_ll_driver/inc/hc32_ll_trng.h | 130 + .../drivers/hc32_ll_driver/inc/hc32_ll_usart.h | 540 + .../drivers/hc32_ll_driver/inc/hc32_ll_usb.h | 671 + .../drivers/hc32_ll_driver/inc/hc32_ll_utility.h | 131 + .../drivers/hc32_ll_driver/inc/hc32_ll_wdt.h | 227 + .../inc/hc32f4a0_ll_interrupts_share.h | 583 + .../drivers/hc32_ll_driver/src/hc32_ll.c | 170 + .../drivers/hc32_ll_driver/src/hc32_ll_adc.c | 1174 + .../drivers/hc32_ll_driver/src/hc32_ll_aes.c | 287 + .../drivers/hc32_ll_driver/src/hc32_ll_aos.c | 194 + .../drivers/hc32_ll_driver/src/hc32_ll_can.c | 1497 + .../drivers/hc32_ll_driver/src/hc32_ll_clk.c | 1776 + .../drivers/hc32_ll_driver/src/hc32_ll_cmp.c | 716 + .../drivers/hc32_ll_driver/src/hc32_ll_crc.c | 584 + .../drivers/hc32_ll_driver/src/hc32_ll_ctc.c | 384 + .../drivers/hc32_ll_driver/src/hc32_ll_dac.c | 529 + .../drivers/hc32_ll_driver/src/hc32_ll_dcu.c | 605 + .../drivers/hc32_ll_driver/src/hc32_ll_dma.c | 1196 + .../drivers/hc32_ll_driver/src/hc32_ll_dmc.c | 565 + .../drivers/hc32_ll_driver/src/hc32_ll_dvp.c | 426 + .../drivers/hc32_ll_driver/src/hc32_ll_efm.c | 1450 + .../drivers/hc32_ll_driver/src/hc32_ll_emb.c | 718 + .../drivers/hc32_ll_driver/src/hc32_ll_eth.c | 4200 + .../hc32_ll_driver/src/hc32_ll_event_port.c | 442 + .../drivers/hc32_ll_driver/src/hc32_ll_fcg.c | 194 + .../drivers/hc32_ll_driver/src/hc32_ll_fcm.c | 385 + .../drivers/hc32_ll_driver/src/hc32_ll_fmac.c | 350 + .../drivers/hc32_ll_driver/src/hc32_ll_gpio.c | 650 + .../drivers/hc32_ll_driver/src/hc32_ll_hash.c | 593 + .../drivers/hc32_ll_driver/src/hc32_ll_hrpwm.c | 381 + .../drivers/hc32_ll_driver/src/hc32_ll_i2c.c | 1200 + .../drivers/hc32_ll_driver/src/hc32_ll_i2s.c | 1027 + .../drivers/hc32_ll_driver/src/hc32_ll_icg.c | 138 + .../hc32_ll_driver/src/hc32_ll_interrupts.c | 1821 + .../drivers/hc32_ll_driver/src/hc32_ll_keyscan.c | 227 + .../drivers/hc32_ll_driver/src/hc32_ll_mau.c | 278 + .../drivers/hc32_ll_driver/src/hc32_ll_mpu.c | 950 + .../drivers/hc32_ll_driver/src/hc32_ll_nfc.c | 1821 + .../drivers/hc32_ll_driver/src/hc32_ll_ots.c | 405 + .../drivers/hc32_ll_driver/src/hc32_ll_pwc.c | 1289 + .../drivers/hc32_ll_driver/src/hc32_ll_qspi.c | 471 + .../drivers/hc32_ll_driver/src/hc32_ll_rmu.c | 152 + .../drivers/hc32_ll_driver/src/hc32_ll_rtc.c | 1139 + .../drivers/hc32_ll_driver/src/hc32_ll_sdioc.c | 2676 + .../drivers/hc32_ll_driver/src/hc32_ll_smc.c | 549 + .../drivers/hc32_ll_driver/src/hc32_ll_spi.c | 884 + .../drivers/hc32_ll_driver/src/hc32_ll_sram.c | 307 + .../drivers/hc32_ll_driver/src/hc32_ll_swdt.c | 256 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr0.c | 626 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr2.c | 810 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr4.c | 2306 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr6.c | 1935 + .../drivers/hc32_ll_driver/src/hc32_ll_tmra.c | 1178 + .../drivers/hc32_ll_driver/src/hc32_ll_trng.c | 216 + .../drivers/hc32_ll_driver/src/hc32_ll_usart.c | 2359 + .../drivers/hc32_ll_driver/src/hc32_ll_usb.c | 1362 + .../drivers/hc32_ll_driver/src/hc32_ll_utility.c | 396 + .../drivers/hc32_ll_driver/src/hc32_ll_wdt.c | 256 + .../src/hc32f4a0_ll_interrupts_share.c | 4719 + .../hc32/iec60730_class_b_stl/stl_common.h | 145 + .../midwares/hc32/iec60730_class_b_stl/stl_conf.h | 106 + .../stl_test_item/inc/stl_sw_crc32.h | 95 + .../stl_test_item/inc/stl_test_cpu.h | 86 + .../stl_test_item/inc/stl_test_flash.h | 87 + .../stl_test_item/inc/stl_test_interrupt.h | 100 + .../stl_test_item/inc/stl_test_pc.h | 85 + .../stl_test_item/inc/stl_test_ram.h | 89 + .../stl_test_item/src/EWARM/stl_test_cpu_runtime.s | 245 + .../stl_test_item/src/EWARM/stl_test_cpu_startup.s | 357 + .../src/EWARM/stl_test_full_ram_startup.s | 186 + .../stl_test_item/src/EWARM/stl_test_pc.s | 147 + .../stl_test_item/src/MDK/stl_test_cpu_runtime.s | 251 + .../stl_test_item/src/MDK/stl_test_cpu_startup.s | 363 + .../src/MDK/stl_test_full_ram_startup.s | 191 + .../stl_test_item/src/MDK/stl_test_pc.s | 146 + .../stl_test_item/src/stl_sw_crc32.c | 156 + .../stl_test_item/src/stl_test_flash.c | 164 + .../stl_test_item/src/stl_test_interrupt.c | 169 + .../stl_test_item/src/stl_test_ram_runtime.c | 268 + .../hc32/iec60730_class_b_stl/stl_test_runtime.c | 138 + .../hc32/iec60730_class_b_stl/stl_test_runtime.h | 116 + .../hc32/iec60730_class_b_stl/stl_test_startup.c | 120 + .../hc32/iec60730_class_b_stl/stl_test_startup.h | 111 + .../hc32/iec60730_class_b_stl/stl_utility.c | 234 + .../hc32/iec60730_class_b_stl/stl_utility.h | 107 + .../cdc_msc_composite/usb_dev_cdc_msc_wrapper.c | 334 + .../cdc_msc_composite/usb_dev_cdc_msc_wrapper.h | 79 + .../custom_hid/usb_dev_custom_hid_class.c | 381 + .../custom_hid/usb_dev_custom_hid_class.h | 130 + .../hid_cdc_composite/usb_dev_hid_cdc_wrapper.c | 364 + .../hid_cdc_composite/usb_dev_hid_cdc_wrapper.h | 74 + .../hid_keyboard/usb_dev_keyboard_class.c | 330 + .../hid_keyboard/usb_dev_keyboard_class.h | 101 + .../device_class/hid_mouse/usb_dev_mouse_class.c | 345 + .../device_class/hid_mouse/usb_dev_mouse_class.h | 101 + .../hid_msc_composite/usb_dev_hid_msc_wrapper.c | 273 + .../hid_msc_composite/usb_dev_hid_msc_wrapper.h | 80 + .../device_class/msc/usb_dev_msc_bot.c | 267 + .../device_class/msc/usb_dev_msc_bot.h | 137 + .../device_class/msc/usb_dev_msc_class.c | 264 + .../device_class/msc/usb_dev_msc_class.h | 94 + .../device_class/msc/usb_dev_msc_data.c | 111 + .../device_class/msc/usb_dev_msc_data.h | 92 + .../device_class/msc/usb_dev_msc_mem.h | 90 + .../device_class/msc/usb_dev_msc_scsi.c | 553 + .../device_class/msc/usb_dev_msc_scsi.h | 167 + .../device_class/single_cdc/usb_dev_cdc_class.c | 427 + .../device_class/single_cdc/usb_dev_cdc_class.h | 121 + .../usb/usb_device_lib/device_core/usb_dev_core.c | 339 + .../usb/usb_device_lib/device_core/usb_dev_core.h | 82 + .../device_core/usb_dev_ctrleptrans.c | 159 + .../device_core/usb_dev_ctrleptrans.h | 83 + .../usb/usb_device_lib/device_core/usb_dev_def.h | 155 + .../usb_device_lib/device_core/usb_dev_driver.c | 400 + .../usb_device_lib/device_core/usb_dev_driver.h | 89 + .../usb/usb_device_lib/device_core/usb_dev_int.c | 456 + .../usb/usb_device_lib/device_core/usb_dev_int.h | 136 + .../usb_device_lib/device_core/usb_dev_stdreq.c | 606 + .../usb_device_lib/device_core/usb_dev_stdreq.h | 82 + .../host_class/cdc/usb_host_cdc_class.c | 693 + .../host_class/cdc/usb_host_cdc_class.h | 169 + .../host_class/cdc/usb_host_cdc_ctrl.c | 175 + .../host_class/cdc/usb_host_cdc_ctrl.h | 221 + .../host_class/hid/usb_host_hid_class.c | 443 + .../host_class/hid/usb_host_hid_class.h | 167 + .../host_class/hid/usb_host_hid_keyboardapp.c | 277 + .../host_class/hid/usb_host_hid_keyboardapp.h | 99 + .../host_class/hid/usb_host_hid_mouseapp.c | 122 + .../host_class/hid/usb_host_hid_mouseapp.h | 92 + .../usb_host_lib/host_class/msc/usb_host_msc_bot.c | 449 + .../usb_host_lib/host_class/msc/usb_host_msc_bot.h | 162 + .../host_class/msc/usb_host_msc_class.c | 395 + .../host_class/msc/usb_host_msc_class.h | 113 + .../host_class/msc/usb_host_msc_fatfs.c | 241 + .../host_class/msc/usb_host_msc_scsi.c | 528 + .../host_class/msc/usb_host_msc_scsi.h | 136 + .../usb/usb_host_lib/host_core/usb_host_cfgch.c | 202 + .../usb/usb_host_lib/host_core/usb_host_cfgch.h | 103 + .../usb/usb_host_lib/host_core/usb_host_core.c | 537 + .../usb/usb_host_lib/host_core/usb_host_core.h | 95 + .../usb_host_lib/host_core/usb_host_ctrltrans.c | 320 + .../usb_host_lib/host_core/usb_host_ctrltrans.h | 86 + .../hc32/usb/usb_host_lib/host_core/usb_host_def.h | 430 + .../usb/usb_host_lib/host_core/usb_host_driver.c | 231 + .../usb/usb_host_lib/host_core/usb_host_driver.h | 90 + .../hc32/usb/usb_host_lib/host_core/usb_host_int.c | 575 + .../hc32/usb/usb_host_lib/host_core/usb_host_int.h | 128 + .../usb/usb_host_lib/host_core/usb_host_stdreq.c | 482 + .../usb/usb_host_lib/host_core/usb_host_stdreq.h | 107 + .../hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h | 199 + bsp/hc32/tools/sdk_dist.py | 21 + 345 files changed, 402773 insertions(+) create mode 100644 bsp/hc32/README.md create mode 100644 "bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" create mode 100644 "bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\244\226\350\256\276\351\251\261\345\212\250\344\275\277\347\224\250\346\225\231\347\250\213.md" create mode 100644 "bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/.config create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/README.md create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/SConscript create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript create 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bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_irq.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_irq.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_log.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_pwm.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_rtc.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_spi.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_spi.h create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_usart.c create mode 100644 bsp/hc32/libraries/hc32_drivers/drv_usart.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/LICENSE create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/README.txt create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/SConscript create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.mac create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.out create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.flash create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.out create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.flash create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.out create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xG.flash create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xI.flash create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xG.board create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xI.board create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_1M.FLM create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_2M.FLM create mode 100644 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bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_compiler.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_gcc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_iccarm.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_version.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv81mml.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mbl.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mml.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0plus.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm1.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm23.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm3.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm33.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm35p.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm4.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm55.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm7.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc000.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc300.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv7.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv8.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/pmu_armv8.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/tz_context.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dmc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dvp.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_eth.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fmac.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hrpwm.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mau.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_nfc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr2.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32f4a0_ll_interrupts_share.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dmc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dvp.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_eth.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fmac.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hrpwm.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mau.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_nfc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr2.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h create mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h create mode 100644 bsp/hc32/tools/sdk_dist.py (limited to 'bsp') diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md new file mode 100644 index 0000000000..ab297d37e5 --- /dev/null +++ b/bsp/hc32/README.md @@ -0,0 +1,22 @@ + +# HC32 BSP 说明 + +HC32 系列 BSP 目前支持情况如下表所示： + +| **BSP 文件夹名称** | **开发板名称** | +|:------------------------- |:------------------------- | +| **F1 系列** | | +| **F4 系列** | | +| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | +| **M1 系列** | | +| **M4 系列** | | + +可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： + +| **BSP 使用教程** | **简介** | +|:-------------------- |:------------------------------------------------- | +| [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 | +| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 | +| **BSP 制作与提交** | **简介** | +| [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 | + diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" new file mode 100644 index 0000000000..f6ea04998b --- /dev/null +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" @@ -0,0 +1,2 @@ +# HC32 系列 BSP 制作教程 + diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\244\226\350\256\276\351\251\261\345\212\250\344\275\277\347\224\250\346\225\231\347\250\213.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\244\226\350\256\276\351\251\261\345\212\250\344\275\277\347\224\250\346\225\231\347\250\213.md" new file mode 100644 index 0000000000..7a6e5bc255 --- /dev/null +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\244\226\350\256\276\351\251\261\345\212\250\344\275\277\347\224\250\346\225\231\347\250\213.md" @@ -0,0 +1 @@ +# HC32系列BSP外设驱动使用教程 diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" new file mode 100644 index 0000000000..43f9faa055 --- /dev/null +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" @@ -0,0 +1,2 @@ +# HC32系列驱动介绍 + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.config b/bsp/hc32/ev_hc32f4a0_lqfp176/.config new file mode 100644 index 0000000000..5df70f1e7b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.config @@ -0,0 +1,702 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40100 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +CONFIG_RT_USING_PULSE_ENCODER=y +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F4A0SI=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_TCA9539 is not set +# CONFIG_BSP_USING_SPI_FLASH is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_TIMER is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CAN is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore b/bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md new file mode 100644 index 0000000000..e914a61988 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md @@ -0,0 +1,116 @@ +# XHSC EV_F4A0_LQ176 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F4A0_LQ176 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F4A0_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A0SITB 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F4A0_LQ176 开发板常用 **板载资源** 如下： + +- MCU：HC32F4A0SITB，主频240MHz，2048KB FLASH，512KB RAM +- 外部RAM：IS62WV51216(SRAM, 1MB) IS42S16400J(SDRAM, 8MB) +- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 64MB) +- 常用外设 + - LED：3 个， user LED(LED0,LED1,LED2)。 + - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。 +- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口 +- 调试接口：板载DAP调试器、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F4A0_LQ176](http://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART1 | +| SPI Flash | 支持 | 使用 SPI1 | +| LED | 支持 | LED | +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 | +| UART | 支持 | UART1~10 | +| SPI | 支持 | SPI1~6 | +| I2C | 支持 | 软件 I2C | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| PWM | 支持 | | +| HWTIMER | 支持 | | +| LED | 支持 | LED11 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。 + +USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Apr 24 2022 13:32:39 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +## 联系人信息 + +维护人: + +- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/SConscript b/bsp/hc32/ev_hc32f4a0_lqfp176/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct b/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct new file mode 100644 index 0000000000..b255bbb97a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hc32_library = 'hc32f4a0_ddl' +rtconfig.BSP_LIBRARY_TYPE = hc32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c new file mode 100644 index 0000000000..360d45e00a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include + + +/* defined the LED_GREEN pin: PC9 */ +#define LED_GREEN_PIN GET_PIN(C, 9) + + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig new file mode 100644 index 0000000000..890ca05996 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -0,0 +1,372 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F4A0SI + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config PHY_USING_RTL8201F + bool + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select BSP_USING_I2C1 + select RT_USING_LWIP + select PHY_USING_RTL8201F + select RT_LWIP_USING_HW_CHECKSUM + select BSP_USING_TCA9539 + if BSP_USING_ETH + config ETH_USING_INTERFACE_RMII + bool "select RMII interface" + default n + + config PHY_USING_INTERRUPT_MODE + bool "enable phy interrupt mode" + select ETH_PHY_INT_PIN + default n + + config ETH_PHY_INT_PIN + int + default 16 + endif + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C1 + default n + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + default n + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_USING_UART6 + bool "Enable UART6" + default n + + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART7 + bool "Enable UART7" + default n + + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART8 + bool "Enable UART8" + default n + + config BSP_USING_UART9 + bool "Enable UART9" + default n + + config BSP_USING_UART10 + bool "Enable UART10" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + + config BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + depends on BSP_USING_SPI4 + default n + + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + depends on BSP_USING_SPI4 + select BSP_SPI4_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LRC + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output PWM" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH1 + bool "Enable PWM1 channel1" + default n + + config BSP_USING_PWM1_CH2 + bool "Enable PWM1 channel2" + default n + + config BSP_USING_PWM1_CH3 + bool "Enable PWM1 channel3" + default n + + config BSP_USING_PWM1_CH4 + bool "Enable PWM1 channel4" + default n + endif + + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output PWM" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH1 + bool "Enable PWM2 channel1" + default n + + config BSP_USING_PWM2_CH2 + bool "Enable PWM2 channel2" + default n + + config BSP_USING_PWM2_CH3 + bool "Enable PWM2 channel3" + default n + + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + endif + + menuconfig BSP_USING_TIMER + bool "Enable TIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_TIMER + config BSP_USING_TIMER5 + bool "Enable TIMER5" + default n + + config BSP_USING_TIMER6 + bool "Enable TIMER6" + default n + + config BSP_USING_TIMER7 + bool "Enable TIMER7" + default n + + config BSP_USING_TIMER8 + bool "Enable TIMER8" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER9 + bool "Enable Pulse Encoder9" + default n + + config BSP_USING_PULSE_ENCODER10 + bool "Enable Pulse Encoder10" + default n + + config BSP_USING_PULSE_ENCODER11 + bool "Enable Pulse Encoder11" + default n + + config BSP_USING_PULSE_ENCODER12 + bool "Enable Pulse Encoder12" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "using adc1" + default n + config BSP_USING_ADC2 + bool "using adc2" + default n + config BSP_USING_ADC3 + bool "using adc3" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript new file mode 100644 index 0000000000..abc21f957a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript @@ -0,0 +1,36 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +if GetDepend(['BSP_USING_TCA9539']): + src += Glob('ports/tca9539.c') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/spi_flash.c') + +path = [cwd] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s'] + +CPPDEFINES = ['HC32F4A0'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c new file mode 100644 index 0000000000..b3c27756d9 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include "board.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_HCLK_DIV1)); + + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + stc_clock_freq_t stcClkFreq; + rt_uint32_t cnts; + + CLK_GetClockFreq(&stcClkFreq); + + cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND; + + SysTick_Config(cnts); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* Peripheral registers write unprotected */ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); + + SystemClock_Config(); + /* Configure the SysTick */ + SysTick_Configuration(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h new file mode 100644 index 0000000000..92b2e7b994 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c new file mode 100644 index 0000000000..6029bbb25c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, GPIO_FUNC_37); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, GPIO_FUNC_36); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM1) + case (rt_uint32_t)CM_TMRA_1: +#if defined(BSP_USING_PWM1_CH1) + GPIO_SetFunc(PWM1_CH1_PORT, PWM1_CH1_PIN, PWM1_CH1_FUNC); +#endif +#if defined(BSP_USING_PWM1_CH2) + GPIO_SetFunc(PWM1_CH2_PORT, PWM1_CH2_PIN, PWM1_CH2_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PULSE_ENCODER9) + case (rt_uint32_t)CM_TMRA_9: + GPIO_SetFunc(PULSE_ENCODER9_CLKA_PORT, PULSE_ENCODER9_CLKA_PIN, PULSE_ENCODER9_CLKA_FUNC); + GPIO_SetFunc(PULSE_ENCODER9_CLKB_PORT, PULSE_ENCODER9_CLKB_PIN, PULSE_ENCODER9_CLKB_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_ADC) +void rt_hw_board_adc_clock_init(void) +{ + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); + + /* 1. Enable ADC peripheral clock. */ +#if defined(BSP_USING_ADC1) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE); +#endif +#if defined(BSP_USING_ADC2) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE); +#endif +#if defined(BSP_USING_ADC3) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE); +#endif +} + +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_SetFunc(GPIO_PORT_C, GPIO_PIN_06, GPIO_FUNC_40); /* SCK */ + GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_13, GPIO_FUNC_41); /* MOSI */ + GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_12, GPIO_FUNC_42); /* MISO */ + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ +#if defined(ETH_USING_INTERFACE_RMII) + /* + ETH_SMI_MDIO ----------------> PA2 + ETH_SMI_MDC -----------------> PC1 + ETH_RMII_TX_EN --------------> PG11 + ETH_RMII_TXD0 ---------------> PG13 + ETH_RMII_TXD1 ---------------> PG14 + ETH_RMII_REF_CLK ------------> PA1 + ETH_RMII_CRS_DV -------------> PA7 + ETH_RMII_RXD0 ---------------> PC4 + ETH_RMII_RXD1 ---------------> PC5 + ETH_RMII_RX_ER --------------> PI10 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11); + /* Configure PC1, PC4 and PC5 */ + GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11); + /* Configure PG11, PG13 and PG14 */ + GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11); + /* Configure PI10 */ + GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11); +#else + /* + ETH_SMI_MDIO ----------------> PA2 + ETH_SMI_MDC -----------------> PC1 + ETH_MII_TX_CLK --------------> PB6 + ETH_MII_TX_EN ---------------> PG11 + ETH_MII_TXD0 ----------------> PG13 + ETH_MII_TXD1 ----------------> PG14 + ETH_MII_TXD2 ----------------> PB9 + ETH_MII_TXD3 ----------------> PB8 + ETH_MII_RX_CLK --------------> PA1 + ETH_MII_RX_DV ---------------> PA7 + ETH_MII_RXD0 ----------------> PC4 + ETH_MII_RXD1 ----------------> PC5 + ETH_MII_RXD2 ----------------> PB0 + ETH_MII_RXD3 ----------------> PB1 + ETH_MII_RX_ER ---------------> PI10 + ETH_MII_CRS -----------------> PH2 + ETH_MII_COL -----------------> PH3 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11); + /* Configure PB0, PB1, PB6, PB8 and PB9 */ + GPIO_SetFunc(GPIO_PORT_B, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_06 | GPIO_PIN_08 | GPIO_PIN_09), GPIO_FUNC_11); + /* Configure PC1, PC4 and PC5 */ + GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11); + /* Configure PG11, PG13 and PG14 */ + GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11); + /* Configure PH2, PH3 */ + GPIO_SetFunc(GPIO_PORT_H, (GPIO_PIN_02 | GPIO_PIN_03), GPIO_FUNC_11); + /* Configure PI10 */ + GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11); +#endif + return RT_EOK; +} +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h new file mode 100644 index 0000000000..c419c67054 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" + + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_H) + #define USART1_RX_PIN (GPIO_PIN_13) + + #define USART1_TX_PORT (GPIO_PORT_H) + #define USART1_TX_PIN (GPIO_PIN_15) +#endif + +#if defined(BSP_USING_UART6) + #define USART6_RX_PORT (GPIO_PORT_H) + #define USART6_RX_PIN (GPIO_PIN_06) + + #define USART6_TX_PORT (GPIO_PORT_E) + #define USART6_TX_PIN (GPIO_PIN_06) +#endif + +/*********************** PWM port *************************/ +#if defined(BSP_USING_PWM1) + + #if defined(BSP_USING_PWM1_CH1) + #define PWM1_CH1_PORT (GPIO_PORT_A) + #define PWM1_CH1_PIN (GPIO_PIN_08) + #define PWM1_CH1_FUNC (GPIO_FUNC_4) + #endif + + #if defined(BSP_USING_PWM1_CH2) + #define PWM1_CH2_PORT (GPIO_PORT_A) + #define PWM1_CH2_PIN (GPIO_PIN_09) + #define PWM1_CH2_FUNC (GPIO_FUNC_4) + #endif + +#endif + +/****************** Pulse encoder port ********************/ +#if defined(BSP_USING_PULSE_ENCODER9) + #define PULSE_ENCODER9_CLKA_PORT (GPIO_PORT_G) + #define PULSE_ENCODER9_CLKA_PIN (GPIO_PIN_04) + #define PULSE_ENCODER9_CLKA_FUNC (GPIO_FUNC_4) + + #define PULSE_ENCODER9_CLKB_PORT (GPIO_PORT_G) + #define PULSE_ENCODER9_CLKB_PIN (GPIO_PIN_05) + #define PULSE_ENCODER9_CLKB_FUNC (GPIO_FUNC_4) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_C) + #define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_C) + #define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) + #define CAN1_TX_PORT (GPIO_PORT_D) + #define CAN1_TX_PIN (GPIO_PIN_05) + #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + + #define CAN1_RX_PORT (GPIO_PORT_D) + #define CAN1_RX_PIN (GPIO_PIN_04) + #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) + + #define CAN1_INT_PRIO (DDL_IRQ_PRIO_03) + #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) + #define CAN1_INT_IRQn (INT004_IRQn) +#endif + +#if defined(BSP_USING_CAN2) + #define CAN2_TX_PORT (GPIO_PORT_D) + #define CAN2_TX_PIN (GPIO_PIN_07) + #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + + #define CAN2_RX_PORT (GPIO_PORT_D) + #define CAN2_RX_PIN (GPIO_PIN_06) + #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) + + #define CAN2_INT_PRIO (DDL_IRQ_PRIO_03) + #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) + #define CAN2_INT_IRQn (INT005_IRQn) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h new file mode 100644 index 0000000000..abca2da019 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .name = "adc1", \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .name = "adc2", \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_CONFIG */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .name = "adc3", \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_CONFIG */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h new file mode 100644 index 0000000000..54bbe8129f --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#ifndef CAN1_CONFIG +#define CAN1_CONFIG \ + { \ + .name = "can1", \ + } +#endif /* CAN1_CONFIG */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#ifndef CAN2_CONFIG +#define CAN2_CONFIG \ + { \ + .name = "can2", \ + } +#endif /* CAN2_CONFIG */ +#endif /* BSP_USING_CAN2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h new file mode 100644 index 0000000000..612db91b47 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_IRQn INT038_IRQn +#define SPI1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_IRQn INT039_IRQn +#define SPI1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_IRQn INT040_IRQn +#define SPI2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_IRQn INT041_IRQn +#define SPI2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_IRQn INT042_IRQn +#define SPI3_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_IRQn INT043_IRQn +#define SPI3_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_IRQn INT018_IRQn +#define SPI4_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_IRQn INT019_IRQn +#define SPI4_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_IRQn INT044_IRQn +#define UART1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_IRQn INT045_IRQn +#define UART1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_IRQn INT046_IRQn +#define UART2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_IRQn INT047_IRQn +#define UART2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_IRQn INT048_IRQn +#define UART6_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_IRQn INT049_IRQn +#define UART6_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_IRQn INT020_IRQn +#define UART7_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_IRQn INT021_IRQn +#define UART7_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h new file mode 100644 index 0000000000..aad1868525 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = INT104_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h new file mode 100644 index 0000000000..066d20bc5c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = INT022_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = INT023_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = INT024_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = INT025_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = INT026_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = INT027_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = INT028_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = INT029_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = INT030_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = INT031_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = INT032_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = INT033_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = INT034_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = INT035_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = INT036_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = INT037_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h new file mode 100644 index 0000000000..da93ebdff8 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .irq_config = \ + { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .irq_config = \ + { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h new file mode 100644 index 0000000000..3ed0a17f50 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM11 +#ifndef TIM11_CONFIG +#define TIM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ + .name = "timer11", \ + } +#endif /* TIM11_CONFIG */ +#endif /* BSP_USING_TIM11 */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h new file mode 100644 index 0000000000..dba447e691 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h @@ -0,0 +1,579 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT010_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT089_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT088_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = INT006_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = INT086_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif /* UART1_TX_CPLT_CONFIG */ + +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT011_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT091_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT090_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = INT007_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = INT087_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif /* UART2_TX_CPLT_CONFIG */ + +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT012_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT095_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT094_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT013_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT097_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT096_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT014_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT101_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT100_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT015_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT103_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT102_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .irq_config = \ + { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = INT008_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = INT099_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif /* UART6_TX_CPLT_CONFIG */ + +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .irq_config = \ + { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT016_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT107_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT106_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .irq_config = \ + { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = INT009_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = INT105_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif /* UART7_TX_CPLT_CONFIG */ + +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .irq_config = \ + { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT017_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT109_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT108_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ + } +#endif /* UART8_CONFIG */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT112_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT110_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT111_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ + } +#endif /* UART9_CONFIG */ +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = INT115_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = INT114_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = INT113_IRQn, \ + .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h new file mode 100644 index 0000000000..4c72df565b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/gpio_config.h" +#include "config/eth_config.h" +#include "config/can_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h new file mode 100644 index 0000000000..5ac85f3cd6 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h @@ -0,0 +1,210 @@ +/** + ******************************************************************************* + * @file template/source/hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2022-04-28 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MDIO_ENABLE (DDL_OFF) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PLA_ENABLE (DDL_OFF) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_OFF) +#define LL_VREF_ENABLE (DDL_OFF) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A0_LQFP176 (1U) +#define BSP_EV_HC32F4A0_LQFP176_MEM (2U) +#define BSP_EV_HC32F460_LQFP100_V1 (3U) +#define BSP_EV_HC32F460_LQFP100_V2 (4U) +#define BSP_EV_HC32F451_LQFP100 (5U) +#define BSP_EV_HC32F452_LQFP100 (6U) +#define BSP_EV_HC32F472_LQFP100 (7U) +#define BSP_SK_HC32F4A0_LQFP100 (8U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_CY62167EV30LL_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_S29GL064N90TFI03_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/** + * @brief Ethernet and PHY Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x00U) + +/* PHY Configuration delay(ms) */ +#define ETH_PHY_RST_DELAY (0x0080UL) +#define ETH_PHY_CONFIG_DELAY (0x0040UL) +#define ETH_PHY_RD_TIMEOUT (0x0005UL) +#define ETH_PHY_WR_TIMEOUT (0x0005UL) + +/* Common PHY Registers */ +#define PHY_BCR (0x00U) /*!< Basic Control Register */ +#define PHY_BSR (0x01U) /*!< Basic Status Register */ + +#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ +#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M (0x2100U) /*!< SET the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M (0x2000U) /*!< SET the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M (0x0100U) /*!< SET the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M (0x0000U) /*!< SET the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ +#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ + +#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ +#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ +#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ +#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ +#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ + +/** + * @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0). + * @note Set value to non-zero if re-define main function. + */ +#define RE_DEFINE_MAIN (0) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf new file mode 100644 index 0000000000..f653427843 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld new file mode 100644 index 0000000000..15541a04e2 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld @@ -0,0 +1,267 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A0xI.ld */ +/* Abstract Linker script for HC32F4A0 Device with */ +/* 2MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2022-04-28 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000000; +__OTP_DATA_SIZE = 2048; +__OTP_LOCK_START = 0x03001840; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct new file mode 100644 index 0000000000..a1e04b14b5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00200000 { ; load region size_region + ER_IROM1 0x00000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 0x00080000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c new file mode 100644 index 0000000000..9934418c3d --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include "drv_spi.h" + +#if defined(BSP_USING_SPI_FLASH) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static int rt_hw_spi_flash_init(void) +{ + rt_hw_spi_device_attach("spi1", "spi10", GPIO_PORT_C, GPIO_PIN_07); + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c new file mode 100644 index 0000000000..bda2ad7df5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include + +#ifdef BSP_USING_TCA9539 + +#include "tca9539.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Define for TCA9539 */ +#define BSP_TCA9539_I2C_BUS_NAME "i2c1" +#define BSP_TCA9539_DEV_ADDR (0x74U) + +#define TCA9539_RST_PIN (45) /* PC13 */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief BSP TCA9539 write data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be written. + * @param [in] data: The pointer to the buffer contains the data to be written. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + rt_uint8_t buf[6]; + + buf[0] = reg; + if (len > 0) + { + if (len < 6) + { + rt_memcpy(buf + 1, data, len); + } + else + { + return -RT_ERROR; + } + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = len + 1; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +/** + * @brief BSP TCA9539 Read data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be read. + * @param [out] data: The pointer to the buffer contains the data to be read. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + + if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0)) + { + return -RT_ERROR; + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_RD; + msgs.buf = data; + msgs.len = len; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + + +/** + * @brief Reset TCA9539. + * @param [in] None + * @retval None + */ +static void TCA9539_Reset(void) +{ + rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT); + /* Reset the device */ + rt_pin_write(TCA9539_RST_PIN, PIN_LOW); + rt_thread_mdelay(3U); + rt_pin_write(TCA9539_RST_PIN, PIN_HIGH); +} + +/** + * @brief Write TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + if (0U == u8PinState) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Read TCA9539 pin input value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + if (0U != (u8TempData[1] & u8Pin)) + { + *pu8PinState = TCA9539_PIN_SET; + } + else + { + *pu8PinState = TCA9539_PIN_RESET; + } + + return RT_EOK; +} + +/** + * @brief Toggle TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + u8TempData[1] ^= u8Pin; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Configuration TCA9539 pin. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8Dir Pin output direction. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Direction_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + if (TCA9539_DIR_OUT == u8Dir) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Initialize TCA9539. + * @param [in] None + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +int TCA9539_Init(void) +{ + char name[RT_NAME_MAX]; + uint8_t u8TempData[2]; + + TCA9539_Reset(); + rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX); + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); + if (i2c_bus == RT_NULL) + { + rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME); + return RT_ERROR; + } + /* All Pins are input as default */ + u8TempData[0] = TCA9539_REG_CONFIG_PORT0; + u8TempData[1] = 0xFFU; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + u8TempData[0] = TCA9539_REG_CONFIG_PORT1; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_PREV_EXPORT(TCA9539_Init); + +#endif /* BSP_USING_TCA9539 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h new file mode 100644 index 0000000000..cbe44c5fed --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __TCA9539_H__ +#define __TCA9539_H__ + +#include + +/** + * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition + * @{ + */ +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Port_Definition TCA9539 Port Definition + * @{ + */ +#define TCA9539_IO_PORT0 (0x00U) +#define TCA9539_IO_PORT1 (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition + * @{ + */ +#define TCA9539_IO_PIN0 (0x01U) +#define TCA9539_IO_PIN1 (0x02U) +#define TCA9539_IO_PIN2 (0x04U) +#define TCA9539_IO_PIN3 (0x08U) +#define TCA9539_IO_PIN4 (0x10U) +#define TCA9539_IO_PIN5 (0x20U) +#define TCA9539_IO_PIN6 (0x40U) +#define TCA9539_IO_PIN7 (0x80U) +#define TCA9539_IO_PIN_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition + * @{ + */ +#define TCA9539_DIR_OUT (0x00U) +#define TCA9539_DIR_IN (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition + * @{ + */ +#define TCA9539_PIN_RESET (0x00U) +#define TCA9539_PIN_SET (0x01U) +/** + * @} + */ + +/** + * @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ + +int TCA9539_Init(void); +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState); +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState); +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin); +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir); + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg b/bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg new file mode 100644 index 0000000000..f579fdb570 Binary files /dev/null and b/bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg differ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd new file mode 100644 index 0000000000..3b371ed831 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd @@ -0,0 +1,2966 @@ + + + 3 + + Debug + + ARM + + 0 + + C-SPY + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp new file mode 100644 index 0000000000..ab6696c72d --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp @@ -0,0 +1,2187 @@ + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + Compiler + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + + Drivers + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f4a0.s + + + $PROJ_DIR$\board\board_config.c + + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_usart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\clock.c + + + + Libraries + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32f4a0_ll_interrupts_share.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f4a0.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c + + + + POSIX + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.eww b/bsp/hc32/ev_hc32f4a0_lqfp176/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx new file mode 100644 index 0000000000..023d2c5a89 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx new file mode 100644 index 0000000000..ccdb2c7cb5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx @@ -0,0 +1,817 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F4A0SITB + HDSC + HDSC.HC32F4A0.1.0.6 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + 0 + $$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h + + + + + + + + + + ../libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x3000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_DDL_DRIVER, __RTTHREAD__, HC32F4A0, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\ports;..\libraries\hc32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\libraries\hc32f4a0_ddl\drivers\cmsis\Include;..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\inc;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + stdlib.c + 1 + ..\..\..\components\libc\compilers\common\stdlib.c + + + + + CPU + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + startup_hc32f4a0.s + 2 + ..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f4a0.s + + + + + board_config.c + 1 + board\board_config.c + + + + + board.c + 1 + board\board.c + + + + + drv_gpio.c + 1 + ..\libraries\hc32_drivers\drv_gpio.c + + + + + drv_irq.c + 1 + ..\libraries\hc32_drivers\drv_irq.c + + + + + drv_usart.c + 1 + ..\libraries\hc32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + Libraries + + + hc32_ll_clk.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c + + + + + hc32_ll_icg.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c + + + + + hc32_ll_utility.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c + + + + + hc32_ll_fcg.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c + + + + + hc32_ll_interrupts.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c + + + + + hc32_ll_pwc.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + + + hc32_ll_aos.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c + + + + + hc32_ll_sram.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + + + hc32_ll.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + + + hc32_ll_efm.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c + + + + + hc32f4a0_ll_interrupts_share.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32f4a0_ll_interrupts_share.c + + + + + hc32_ll_gpio.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c + + + + + hc32_ll_usart.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c + + + + + hc32_ll_rmu.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + + + system_hc32f4a0.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f4a0.c + + + + + hc32_ll_tmr0.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c + + + + + hc32_ll_dma.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h new file mode 100644 index 0000000000..8bbe89eb5e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h @@ -0,0 +1,202 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40100 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* POSIX extension functions */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F4A0SI + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py new file mode 100644 index 0000000000..b0b7b6a25e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp b/bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp new file mode 100644 index 0000000000..79e93411c7 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp @@ -0,0 +1,1925 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/template.eww b/bsp/hc32/ev_hc32f4a0_lqfp176/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx new file mode 100644 index 0000000000..023d2c5a89 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx new file mode 100644 index 0000000000..aebcb8f949 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F4A0SITB + HDSC + HDSC.HC32F4A0.1.0.6 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + 0 + $$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h + + + + + + + + + + ../libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x3000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/libraries/.ignore_format.yml b/bsp/hc32/libraries/.ignore_format.yml new file mode 100644 index 0000000000..21e74c0292 --- /dev/null +++ b/bsp/hc32/libraries/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- hc32f4a0_ddl diff --git a/bsp/hc32/libraries/Kconfig b/bsp/hc32/libraries/Kconfig new file mode 100644 index 0000000000..a73bfb6c25 --- /dev/null +++ b/bsp/hc32/libraries/Kconfig @@ -0,0 +1,22 @@ +config SOC_FAMILY_HC32 + bool + +config SOC_SERIES_HC32F1 + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_HC32 + +config SOC_SERIES_HC32F4 + bool + select ARCH_ARM_CORTEX_M4 + select SOC_FAMILY_HC32 + +config SOC_SERIES_HC32M1 + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_HC32 + +config SOC_SERIES_HC32M4 + bool + select ARCH_ARM_CORTEX_M4 + select SOC_FAMILY_HC32 diff --git a/bsp/hc32/libraries/hc32_drivers/Kconfig b/bsp/hc32/libraries/hc32_drivers/Kconfig new file mode 100644 index 0000000000..93e9ecd88f --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/Kconfig @@ -0,0 +1,26 @@ +if BSP_USING_USBD + config BSP_USBD_TYPE_FS + bool + # "USB Full Speed (FS) Core" + config BSP_USBD_TYPE_HS + bool + # "USB High Speed (HS) Core" + + config BSP_USBD_SPEED_HS + bool + # "USB High Speed (HS) Mode" + config BSP_USBD_SPEED_HSINFS + bool + # "USB High Speed (HS) Core in FS mode" + + config BSP_USBD_PHY_EMBEDDED + bool + # "Using Embedded phy interface" + config BSP_USBD_PHY_UTMI + bool + # "UTMI: USB 2.0 Transceiver Macrocell Interace" + config BSP_USBD_PHY_ULPI + bool + # "ULPI: UTMI+ Low Pin Interface" +endif + diff --git a/bsp/hc32/libraries/hc32_drivers/SConscript b/bsp/hc32/libraries/hc32_drivers/SConscript new file mode 100644 index 0000000000..7af8a35308 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/SConscript @@ -0,0 +1,74 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +drv_irq.c +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_PULSE_ENCODER']): + src += ['drv_pulse_encoder.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_QSPI']): + src += ['drv_qspi.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_soft_i2c.c'] + +if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']): + src += ['drv_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['drv_dac.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['RT_USING_PM']): + src += ['drv_pm.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['drv_rtc.c'] + +if GetDepend(['RT_USING_ON_CHIP_FLASH']): + src += ['drv_flash.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['RT_USING_USBD']): + src += ['drv_usbd.c'] + +if GetDepend(['RT_USING_USBH']): + src += ['drv_usbh.c'] + + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c new file mode 100644 index 0000000000..d5bef0396f --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include +#include + +#define DBG_TAG "drv.adc" +#define DBG_LVL DBG_INFO + +#include +#ifdef RT_USING_ADC +typedef struct +{ + struct rt_adc_device adc_dev; + CM_ADC_TypeDef *hc32_adc_instance; + struct hc32_adc_init_type init; +} hc32_adc_device; + +#if !defined(BSP_USING_ADC1) && !defined(BSP_USING_ADC2) && !defined(BSP_USING_ADC3) + #error "Please define at least one BSP_USING_ADCx" +#endif + +static hc32_adc_device g_hc32_devs[] = +{ +#ifdef BSP_USING_ADC1 + { + {0}, + CM_ADC1, + ADC1_CONFIG, + }, +#endif +#ifdef BSP_USING_ADC2 + { + {0}, + CM_ADC2, + ADC2_CONFIG, + }, +#endif +#ifdef BSP_USING_ADC3 + { + {0}, + CM_ADC3, + ADC3_CONFIG, + }, +#endif +}; + +static void internal_trigger0_set(hc32_adc_device *dev) +{ + uint32_t u32TriggerSel; + rt_bool_t is_internal_trig0_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); + + if (is_internal_trig0_enabled == RT_FALSE) + { + return; + } + +#if defined(HC32F4A0) + switch ((rt_uint32_t)dev->hc32_adc_instance) + { + case (rt_uint32_t)CM_ADC1: + u32TriggerSel = AOS_ADC1_0; + break; + case (rt_uint32_t)CM_ADC2: + u32TriggerSel = AOS_ADC2_0; + break; + case (rt_uint32_t)CM_ADC3: + u32TriggerSel = AOS_ADC3_0; + break; + default: + break; + } + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable); +#endif + AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig0_sel); +} + +static void internal_trigger1_set(hc32_adc_device *dev) +{ + uint32_t u32TriggerSel; + rt_bool_t is_internal_trig1_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); + + if (is_internal_trig1_enabled == RT_FALSE) + { + return; + } + +#if defined(HC32F4A0) + switch ((rt_uint32_t)dev->hc32_adc_instance) + { + case (rt_uint32_t)CM_ADC1: + u32TriggerSel = AOS_ADC1_1; + break; + case (rt_uint32_t)CM_ADC2: + u32TriggerSel = AOS_ADC2_1; + break; + case (rt_uint32_t)CM_ADC3: + u32TriggerSel = AOS_ADC3_1; + break; + default: + break; + } + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable); +#endif + AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig1_sel); +} + +static rt_err_t hc32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + hc32_adc_device *adc; + + adc = rt_container_of(device, hc32_adc_device, adc_dev); + ADC_ChCmd(adc->hc32_adc_instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled); + return 0; +} + +static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + rt_err_t rt_ret = RT_ERROR; + + if (!value) + { + return -RT_EINVAL; + } + + hc32_adc_device *adc; + adc = rt_container_of(device, hc32_adc_device, adc_dev); + + if (adc->init.hard_trig_enable == RT_FALSE && adc->hc32_adc_instance->STR == 0) + { + ADC_Start(adc->hc32_adc_instance); + } + + uint32_t start_time = rt_tick_get(); + do + { + if (ADC_GetStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA) == SET) + { + ADC_ClearStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA); + rt_ret = LL_OK; + break; + } + } + while ((rt_tick_get() - start_time) < adc->init.eoc_poll_time_max); + + if (rt_ret == LL_OK) + { + /* Get any ADC value of sequence A channel that needed. */ + *value = ADC_GetValue(adc->hc32_adc_instance, channel); + } + + return rt_ret; +} + +static struct rt_adc_ops g_hc32_adc_ops = +{ + hc32_adc_enabled, + hc32_adc_convert, +}; + +extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx); +extern void rt_hw_board_adc_clock_init(void); +static int rt_hw_adc_init(void) +{ + int ret, i = 0; + stc_adc_init_t stcAdcInit = {0}; + int32_t ll_ret = 0; + + rt_hw_board_adc_clock_init(); + uint32_t dev_cnt = sizeof(g_hc32_devs) / sizeof(g_hc32_devs[0]); + for (; i < dev_cnt; i++) + { + ADC_DeInit(g_hc32_devs[i].hc32_adc_instance); + /* Initializes ADC. */ + stcAdcInit.u16Resolution = g_hc32_devs[i].init.resolution; + stcAdcInit.u16DataAlign = g_hc32_devs[i].init.data_align; + stcAdcInit.u16ScanMode = (g_hc32_devs[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT; + ll_ret = ADC_Init((void *)g_hc32_devs[i].hc32_adc_instance, &stcAdcInit); + if (ll_ret != LL_OK) + { + ret = -RT_ERROR; + break; + } + + ADC_TriggerCmd(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, (en_functional_state_t)g_hc32_devs[i].init.hard_trig_enable); + ADC_TriggerConfig(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, g_hc32_devs[i].init.hard_trig_src); + if (g_hc32_devs[i].init.hard_trig_enable && g_hc32_devs[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) + { + internal_trigger0_set(&g_hc32_devs[i]); + internal_trigger1_set(&g_hc32_devs[i]); + } + + rt_hw_board_adc_init((void *)g_hc32_devs[i].hc32_adc_instance); + ret = rt_hw_adc_register(&g_hc32_devs[i].adc_dev, \ + (const char *)g_hc32_devs[i].init.name, \ + &g_hc32_adc_ops, (void *)g_hc32_devs[i].hc32_adc_instance); + if (ret != RT_EOK) + { + /* TODO err handler */ + // LOG_E("failed register %s, err=%d", g_hc32_devs[i].name, ret); + } + } + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_adc_init); +#endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.h b/bsp/hc32/libraries/hc32_drivers/drv_adc.h new file mode 100644 index 0000000000..c6e956382d --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" + +#include "hc32_ll.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_adc_init_type +{ + char name[8]; + uint16_t resolution; /*!< Specifies the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t data_align; /*!< Specifies ADC data alignment. + This parameter can be a value of @ref ADC_Data_Align */ + rt_bool_t hard_trig_enable; + + uint32_t hard_trig_src; /*a value of @ref ADC_Hard_Trigger_Sel */ + rt_bool_t internal_trig0_comtrg0_enable; + rt_bool_t internal_trig0_comtrg1_enable; + en_event_src_t internal_trig0_sel; /*@ref en_event_src_t in details */ + rt_bool_t internal_trig1_comtrg0_enable; + rt_bool_t internal_trig1_comtrg1_enable; + en_event_src_t internal_trig1_sel; /*@ref en_event_src_t in details */ + + rt_bool_t continue_conv_mode_enable; + rt_bool_t data_reg_auto_clear; + uint32_t eoc_poll_time_max; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +int rt_hw_uart_init(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.c b/bsp/hc32/libraries/hc32_drivers/drv_can.c new file mode 100644 index 0000000000..56d603ba0c --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.c @@ -0,0 +1,614 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include "drv_can.h" +#include +#include + +#ifdef BSP_USING_CAN +#define LOG_TAG "drv_can" + +#if !defined(BSP_USING_CAN1) && !defined(BSP_USING_CAN2) + #error "Please define at least one BSP_USING_CANx" +#endif + +#if defined (HC32F4A0) + #define FILTER_COUNT (16) +#endif + +enum +{ +#ifdef BSP_USING_CAN1 + CAN1_INDEX, +#endif +#ifdef BSP_USING_CAN2 + CAN2_INDEX, +#endif + CAN_INDEX_MAX, +}; + +struct hc32_baud_rate_tab +{ + rt_uint32_t baud_rate; + stc_can_bit_time_config_t ll_sbt; +}; + +#if defined (HC32F4A0) +static const struct hc32_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, {2, 16, 4, 4}}, + {CAN800kBaud, {2, 20, 5, 4}}, + {CAN500kBaud, {4, 16, 4, 4}}, + {CAN250kBaud, {8, 16, 4, 4}}, + {CAN125kBaud, {16, 16, 4, 4}}, + {CAN100kBaud, {20, 16, 4, 4}}, + {CAN50kBaud, {40, 16, 4, 4}}, + {CAN20kBaud, {100, 16, 4, 4}}, + {CAN10kBaud, {200, 16, 4, 4}}, +}; +#endif + +typedef struct +{ + struct rt_can_device rt_can; + struct hc32_can_init_type init; + CM_CAN_TypeDef *instance; + stc_can_init_t ll_init; + stc_can_filter_config_t *p_ll_can_filter_cfg; +} hc32_drv_can; + +static hc32_drv_can drv_can[] = +{ +#ifdef BSP_USING_CAN1 + { + {0}, + CAN1_CONFIG, + .instance = CM_CAN1, + }, +#endif +#ifdef BSP_USING_CAN2 + { + {0}, + CAN2_CONFIG, + .instance = CM_CAN2, + }, +#endif +}; + +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].baud_rate == baud) + return index; + } + + return 0; /* default baud is CAN1MBaud */ +} + +static rt_uint32_t get_can_work_mode(rt_uint32_t mode) +{ + rt_uint32_t work_mode; + switch (mode) + { + case RT_CAN_MODE_NORMAL: + work_mode = CAN_WORK_MD_NORMAL; + break; + case RT_CAN_MODE_LISEN: + work_mode = CAN_WORK_MD_SILENT; + break; + case RT_CAN_MODE_LOOPBACK: + work_mode = CAN_WORK_MD_ELB; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + work_mode = CAN_WORK_MD_ELB_SILENT; + break; + default: + work_mode = CAN_WORK_MD_NORMAL; + break; + } + + return work_mode; +} + +static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg) +{ + rt_uint32_t baud_index; + hc32_drv_can *hc32_can; + rt_err_t rt_ret = RT_EOK; + + RT_ASSERT(can); + RT_ASSERT(cfg); + hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); + RT_ASSERT(hc32_can); + + hc32_can->ll_init.u8WorkMode = get_can_work_mode(cfg->mode); + baud_index = get_can_baud_index(cfg->baud_rate); + hc32_can->ll_init.stcBitCfg = can_baud_rate_tab[baud_index].ll_sbt; + + /* init can */ + int32_t ret = CAN_Init(hc32_can->instance, &hc32_can->ll_init); + if (ret != LL_OK) + { + rt_ret = RT_EINVAL; + } + + return rt_ret; +} + +static uint16_t get_filter_idx(struct rt_can_filter_config *filter_cfg) +{ + uint16_t u16FilterSelected = 0; + + for (int i = 0; i < filter_cfg->count; i++) + { + if (filter_cfg->items[i].hdr != -1) + { + u16FilterSelected |= 1 << filter_cfg->items[i].hdr; + } + } + + for (int i = 0; i < filter_cfg->count; i++) + { + if (filter_cfg->items[i].hdr == -1) + { + for (int j = 0; j < FILTER_COUNT; j++) + { + if ((u16FilterSelected & 1 << j) == 0) + { + filter_cfg->items[i].hdr = j; + u16FilterSelected |= 1 << filter_cfg->items[i].hdr; + break; + } + } + } + } + + return u16FilterSelected; +} + +static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) +{ + hc32_drv_can *hc32_can; + rt_uint32_t argval; + struct rt_can_filter_config *filter_cfg; + + RT_ASSERT(can != RT_NULL); + hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); + RT_ASSERT(hc32_can); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + switch (argval) + { + case RT_DEVICE_FLAG_INT_RX: + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, DISABLE); + break; + case RT_DEVICE_FLAG_INT_TX: + CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, DISABLE); + break; + case RT_DEVICE_CAN_INT_ERR: + CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, DISABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, DISABLE); + break; + default: + break; + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + switch (argval) + { + case RT_DEVICE_FLAG_INT_RX: + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, ENABLE); + break; + case RT_DEVICE_FLAG_INT_TX: + CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, ENABLE); + break; + case RT_DEVICE_CAN_INT_ERR: + CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, ENABLE); + CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, ENABLE); + break; + default: + break; + } + break; + case RT_CAN_CMD_SET_FILTER: + if (RT_NULL != arg) + { + filter_cfg = (struct rt_can_filter_config *)arg; + + if (filter_cfg->count == 0) + { + return -RT_EINVAL; + } + RT_ASSERT(filter_cfg->count <= FILTER_COUNT); + + /* get default filter */ + if (hc32_can->p_ll_can_filter_cfg) + { + hc32_can->ll_init.u16FilterSelect = get_filter_idx(filter_cfg); + for (int i = 0; i < filter_cfg->count; i++) + { + hc32_can->p_ll_can_filter_cfg[i].u32ID = filter_cfg->items[i].id; + hc32_can->p_ll_can_filter_cfg[i].u32IDMask = filter_cfg->items[i].mask; + hc32_can->p_ll_can_filter_cfg[i].u32IDType = filter_cfg->items[i].ide; + } + } + (void)CAN_Init(hc32_can->instance, &hc32_can->ll_init); + break; + } + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISEN) + { + return -RT_ERROR; + } + if (argval != hc32_can->rt_can.config.mode) + { + hc32_can->rt_can.config.mode = argval; + _can_config(can, &hc32_can->rt_can.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != hc32_can->rt_can.config.baud_rate) + { + hc32_can->rt_can.config.baud_rate = argval; + _can_config(can, &hc32_can->rt_can.config); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -RT_ERROR; + } + if (argval != hc32_can->rt_can.config.privmode) + { + hc32_can->rt_can.config.privmode = argval; + return _can_config(can, &hc32_can->rt_can.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + struct rt_can_status *rt_can_stat = (struct rt_can_status *)arg; + stc_can_error_info_t stcErr = {0}; + CAN_GetErrorInfo(hc32_can->instance, &stcErr); + rt_can_stat->rcverrcnt = stcErr.u8RxErrorCount; + rt_can_stat->snderrcnt = stcErr.u8TxErrorCount; + rt_can_stat->lasterrtype = stcErr.u8ErrorType; + rt_can_stat->errcode = CAN_GetStatusValue(hc32_can->instance); + + } + break; + default: + break; + + } + return RT_EOK; +} + +static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + stc_can_tx_frame_t stc_tx_frame = {0}; + int32_t ll_ret; + + RT_ASSERT(can != RT_NULL); + hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); + RT_ASSERT(hc32_can); + + /*check select mailbox is empty */ + stc_tx_frame.u32ID = pmsg->id; + if (RT_CAN_DTR == pmsg->rtr) + { + stc_tx_frame.RTR = 0; + } + else + { + stc_tx_frame.RTR = 1; + } + /* Set up the DLC */ + stc_tx_frame.DLC = pmsg->len & 0x0FU; + /* Set up the data field */ + rt_memcpy(&stc_tx_frame.au8Data, pmsg->data, sizeof(stc_tx_frame.au8Data)); + + ll_ret = CAN_FillTxFrame(hc32_can->instance, CAN_TX_BUF_PTB, &stc_tx_frame); + if (ll_ret != LL_OK) + { + return RT_ERROR; + } + /* Request transmission */ + CAN_StartTx(hc32_can->instance, CAN_TX_REQ_PTB); + return RT_EOK; +} + +static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + int32_t ll_ret; + struct rt_can_msg *pmsg; + stc_can_rx_frame_t ll_rx_frame; + + RT_ASSERT(can != RT_NULL); + hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); + RT_ASSERT(hc32_can); + + pmsg = (struct rt_can_msg *) buf; + + /* get data */ + ll_ret = CAN_GetRxFrame(hc32_can->instance, &ll_rx_frame); + if (ll_ret != LL_OK) + return -RT_ERROR; + /* get id */ + if (CAN_ID_STD == ll_rx_frame.IDE) + { + pmsg->ide = RT_CAN_STDID; + } + else + { + pmsg->ide = RT_CAN_EXTID; + } + pmsg->id = ll_rx_frame.u32ID; + /* get type */ + if (0 == ll_rx_frame.RTR) + { + pmsg->rtr = RT_CAN_DTR; + } + else + { + pmsg->rtr = RT_CAN_RTR; + } + /* get len */ + pmsg->len = ll_rx_frame.DLC; + /* get hdr */ + pmsg->hdr = 0; + rt_memcpy(pmsg->data, &ll_rx_frame.au8Data, ll_rx_frame.DLC); + + return RT_EOK; +} + +static const struct rt_can_ops _can_ops = +{ + _can_config, + _can_control, + _can_sendmsg, + _can_recvmsg, +}; + +static void can_isr(hc32_drv_can *hc32_can) +{ + stc_can_error_info_t stcErr; + + (void)CAN_GetErrorInfo(hc32_can->instance, &stcErr); + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_BUS_OFF) == SET) + { + DDL_Printf("BUS OFF.\r\n"); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF) == SET) + { + DDL_Printf("RX overflow.\r\n"); + rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RXOF_IND); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_BUF_FULL) == SET) + { + DDL_Printf("TX buffer full.\r\n"); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED) == SET) + { + DDL_Printf("TX aborted.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST) == SET) + { + rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_FAIL); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_STB_TX) == SET) + { + DDL_Printf("STB transmitted.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_STB_TX); + rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_PTB_TX) == SET) + { + DDL_Printf("PTB transmitted.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_PTB_TX); + rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX) == SET) + { + /* Received frame can be read here. */ + DDL_Printf("Received a frame.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX); + rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RX_IND); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN) == SET) + { + /* Received frames can be read here. */ + DDL_Printf("RX buffer warning.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL) == SET) + { + /* Received frames can be read here. */ + DDL_Printf("RX buffer full.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN) == SET) + { + DDL_Printf("RX buffer overrun.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN); + } + + if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN) == SET) + { + DDL_Printf("TEC or REC reached warning limit.\r\n"); + CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN); + } + + if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG) == SET) + { + DDL_Printf("Time trigger interrupt.\r\n"); + CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG); + } + + if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TRIG_ERR) == SET) + { + DDL_Printf("Trigger error interrupt.\r\n"); + } + + if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG) == SET) + { + DDL_Printf("Watch trigger interrupt.\r\n"); + CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG); + } +} +#if defined(BSP_USING_CAN1) +static void can1_irq_handler(void) +{ + rt_interrupt_enter(); + can_isr(&drv_can[CAN1_INDEX]); + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_CAN2) +static void can2_irq_handler(void) +{ + rt_interrupt_enter(); + can_isr(&drv_can[CAN2_INDEX]); + rt_interrupt_leave(); +} +#endif + +extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx); +extern void CanPhyEnable(void); +int rt_hw_can_init(void) +{ + struct can_configure rt_can_config = CANDEFAULTCONFIG; + rt_can_config.privmode = RT_CAN_MODE_NOPRIV; + rt_can_config.ticks = 50; +#ifdef RT_CAN_USING_HDR + rt_can_config.maxhdr = FILTER_COUNT; +#endif + + struct hc32_irq_config irq_config; +#if defined(BSP_USING_CAN1) + irq_config.irq_num = CAN1_INT_IRQn; + irq_config.int_src = CAN1_INT_SRC; + irq_config.irq_prio = CAN1_INT_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + can1_irq_handler, + RT_TRUE); +#endif +#if defined(BSP_USING_CAN2) + irq_config.irq_num = CAN2_INT_IRQn; + irq_config.int_src = CAN2_INT_SRC; + irq_config.irq_prio = CAN2_INT_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + can2_irq_handler, + RT_TRUE); +#endif + +#if defined(HC32F4A0) +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN2, ENABLE); +#endif +#endif + + CanPhyEnable(); + int result = RT_EOK; + uint32_t i = 0; + for (; i < CAN_INDEX_MAX; i++) + { + if (drv_can[i].p_ll_can_filter_cfg == RT_NULL) + { + drv_can[i].p_ll_can_filter_cfg = (stc_can_filter_config_t *)rt_malloc(sizeof(stc_can_filter_config_t) * FILTER_COUNT); + } + RT_ASSERT((drv_can[i].p_ll_can_filter_cfg != RT_NULL)); + + rt_memset(drv_can[i].p_ll_can_filter_cfg, 0, sizeof(stc_can_filter_config_t) * FILTER_COUNT); + drv_can[i].p_ll_can_filter_cfg[0].u32ID = 0U; + drv_can[i].p_ll_can_filter_cfg[0].u32IDMask = 0x1FFFFFFF; + drv_can[i].p_ll_can_filter_cfg[0].u32IDType = CAN_ID_STD; + CAN_StructInit(&drv_can[i].ll_init); + drv_can[i].ll_init.pstcFilter = &drv_can[i].p_ll_can_filter_cfg[0]; + drv_can[i].ll_init.u16FilterSelect = CAN_FILTER1; + drv_can[i].rt_can.config = rt_can_config; + + /* register CAN1 device */ + rt_hw_board_can_init(drv_can[i].instance); + rt_hw_can_register(&drv_can[i].rt_can, + drv_can[i].init.name, + &_can_ops, + &drv_can[i]); + } + + return result; +} + +INIT_DEVICE_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_CAN */ + +/************************** end of file ******************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.h b/bsp/hc32/libraries/hc32_drivers/drv_can.h new file mode 100644 index 0000000000..2a9f461c3d --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_CAN_H__ +#define __DRV_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + + + +/* stm32 can device */ +struct hc32_can_init_type +{ + char *name; +}; + +int rt_hw_can_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_CAN_H__ */ + +/************************** end of file ******************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dma.h b/bsp/hc32/libraries/hc32_drivers/drv_dma.h new file mode 100644 index 0000000000..e130ee6f6c --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_dma.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_DMA_H__ +#define __DRV_DMA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "drv_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct dma_config +{ + CM_DMA_TypeDef *Instance; + rt_uint32_t channel; + rt_uint32_t clock; + rt_uint32_t trigger_select; + en_event_src_t trigger_event; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_DMA_H__ */ + diff --git a/bsp/hc32/libraries/hc32_drivers/drv_eth.c b/bsp/hc32/libraries/hc32_drivers/drv_eth.c new file mode 100644 index 0000000000..f4bbcfd6e3 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_eth.c @@ -0,0 +1,642 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "drv_eth.h" + +#if defined(BSP_USING_ETH) + +#include +#include +#include "drv_irq.h" +#include "board_config.h" + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define DRV_DEBUG +#define LOG_TAG "drv.eth" +#include + +#define MAX_ADDR_LEN 6 + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +struct hc32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; +#if !(defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII)) + rt_timer_t poll_link_timer; +#endif + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* ETH_Speed */ + rt_uint32_t eth_speed; + /* ETH_Duplex_Mode */ + rt_uint32_t eth_mode; + /* eth irq */ + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +/* eth phy status */ +enum +{ + ETH_PHY_LINK = 0x01U, + ETH_PHY_100M = 0x02U, + ETH_PHY_FULL_DUPLEX = 0x04U, +}; + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx); +extern rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx); + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void eth_global_irq_handle(void); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static stc_eth_handle_t EthHandle; +/* Ethernet Tx,Rx DMA Descriptor */ +static stc_eth_dma_desc_t *EthDmaTxDscrTab, *EthDmaRxDscrTab; +/* Ethernet Transmit,Receive Buffer */ +static rt_uint8_t *EthTxBuff, *EthRxBuff; +static struct hc32_eth hc32_eth_device = +{ + .irq_config = ETH_IRQ_CONFIG, + .irq_callback = eth_global_irq_handle, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static rt_err_t rt_hc32_eth_init(rt_device_t dev) +{ + stc_eth_init_t stcEthInit; + uint16_t u16RegVal; + + /* Enable ETH clock */ + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_ETHMAC, ENABLE); + /* Init Ethernet GPIO */ + rt_hw_eth_phy_reset(CM_ETH); + rt_hw_eth_board_init(CM_ETH); + /* Reset ETHERNET */ + (void)ETH_DeInit(); + /* Configure structure initialization */ + (void)ETH_CommStructInit(&EthHandle.stcCommInit); + (void)ETH_StructInit(&stcEthInit); + EthHandle.stcCommInit.u16AutoNego = ETH_AUTO_NEGO_DISABLE; + EthHandle.stcCommInit.au8MacAddr[0] = hc32_eth_device.dev_addr[0]; + EthHandle.stcCommInit.au8MacAddr[1] = hc32_eth_device.dev_addr[1]; + EthHandle.stcCommInit.au8MacAddr[2] = hc32_eth_device.dev_addr[2]; + EthHandle.stcCommInit.au8MacAddr[3] = hc32_eth_device.dev_addr[3]; + EthHandle.stcCommInit.au8MacAddr[4] = hc32_eth_device.dev_addr[4]; + EthHandle.stcCommInit.au8MacAddr[5] = hc32_eth_device.dev_addr[5]; +#ifdef ETH_USING_INTERFACE_RMII + EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_RMII; +#else + EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_MII; +#endif + EthHandle.stcCommInit.u32ReceiveMode = ETH_RX_MD_INT; +#ifdef RT_LWIP_USING_HW_CHECKSUM + EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_HW; +#else + EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_SW; +#endif + /* Configure ethernet peripheral */ + if (LL_OK != ETH_Init(&EthHandle, &stcEthInit)) + { + LOG_E("eth hardware init failed"); + } + else + { + LOG_D("eth hardware init success"); + } + + /* Initialize Tx Descriptors list: Chain Mode */ + (void)ETH_DMA_TxDescListInit(&EthHandle, EthDmaTxDscrTab, EthTxBuff, ETH_TX_BUF_NUM); + /* Initialize Rx Descriptors list: Chain Mode */ + (void)ETH_DMA_RxDescListInit(&EthHandle, EthDmaRxDscrTab, EthRxBuff, ETH_RX_BUF_NUM); + /* Enable ETH interrupt */ + NVIC_EnableIRQ(hc32_eth_device.irq_config.irq_num); + + /* Enable MAC and DMA transmission and reception */ + if (LL_OK == ETH_Start()) + { + LOG_D("eth hardware start"); + } + else + { + LOG_E("eth hardware start faild"); + return -RT_ERROR; + } + + /* Configure PHY LED mode */ + u16RegVal = PHY_PAGE_ADDR_7; + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal); + (void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal); + MODIFY_REG16(u16RegVal, PHY_LED_SELECT, PHY_LED_SELECT_10); + (void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal); + u16RegVal = PHY_PAGE_ADDR_0; + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal); +#ifdef ETH_USING_INTERFACE_RMII + /* Disable Power Saving Mode */ + (void)ETH_PHY_ReadReg(&EthHandle, PHY_PSMR, &u16RegVal); + CLR_REG16_BIT(u16RegVal, PHY_EN_PWR_SAVE); + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSMR, u16RegVal); +#endif + + return RT_EOK; +} + +static rt_err_t rt_hc32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("eth open"); + return RT_EOK; +} + +static rt_err_t rt_hc32_eth_close(rt_device_t dev) +{ + LOG_D("eth close"); + return RT_EOK; +} + +static rt_size_t rt_hc32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("eth read"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_hc32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("eth write"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_hc32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) + { + SMEMCPY(args, hc32_eth_device.dev_addr, 6); + } + else + { + return -RT_ERROR; + } + break; + + default : + break; + } + + return RT_EOK; +} + +/* ethernet device interface */ +/* transmit data*/ +rt_err_t rt_hc32_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t errval = RT_ERROR; + struct pbuf *q; + uint8_t *txBuffer; + __IO stc_eth_dma_desc_t *DmaTxDesc; + uint32_t byteCnt; + uint32_t frameLength = 0UL; + uint32_t bufferOffset; + uint32_t payloadOffset; + + DmaTxDesc = EthHandle.stcTxDesc; + txBuffer = (uint8_t *)((EthHandle.stcTxDesc)->u32Buf1Addr); + bufferOffset = 0UL; + /* Copy frame from pbufs to driver buffers */ + for (q = p; q != NULL; q = q->next) + { + /* If this buffer isn't available, goto error */ + if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN)) + { + LOG_D("buffer not valid"); + errval = (err_t)ERR_USE; + goto error; + } + + /* Get bytes in current lwIP buffer */ + byteCnt = q->len; + payloadOffset = 0UL; + /* Check if the length of data to copy is bigger than Tx buffer size */ + while ((byteCnt + bufferOffset) > ETH_TX_BUF_SIZE) + { + /* Copy data to Tx buffer*/ + SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (ETH_TX_BUF_SIZE - bufferOffset)); + /* Point to next descriptor */ + DmaTxDesc = (stc_eth_dma_desc_t *)(DmaTxDesc->u32Buf2NextDescAddr); + /* Check if the buffer is available */ + if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN)) + { + errval = (err_t)ERR_USE; + goto error; + } + + txBuffer = (uint8_t *)(DmaTxDesc->u32Buf1Addr); + byteCnt = byteCnt - (ETH_TX_BUF_SIZE - bufferOffset); + payloadOffset = payloadOffset + (ETH_TX_BUF_SIZE - bufferOffset); + frameLength = frameLength + (ETH_TX_BUF_SIZE - bufferOffset); + bufferOffset = 0UL; + } + /* Copy the remaining bytes */ + SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), byteCnt); + bufferOffset = bufferOffset + byteCnt; + frameLength = frameLength + byteCnt; + } + LOG_D("transmit frame length :%d", framelength); + /* Prepare transmit descriptors to give to DMA */ + (void)ETH_DMA_SetTransFrame(&EthHandle, frameLength); + errval = (err_t)ERR_OK; + +error: + /* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */ + if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_UNS)) + { + /* Clear DMA UNS flag */ + ETH_DMA_ClearStatus(ETH_DMA_FLAG_UNS); + /* Resume DMA transmission */ + WRITE_REG32(CM_ETH->DMA_TXPOLLR, 0UL); + } + + return errval; +} + +/* receive data*/ +struct pbuf *rt_hc32_eth_rx(rt_device_t dev) +{ + struct pbuf *p = NULL; + struct pbuf *q; + uint32_t len; + uint8_t *rxBuffer; + __IO stc_eth_dma_desc_t *DmaRxDesc; + uint32_t byteCnt; + uint32_t bufferOffset; + uint32_t payloadOffset; + uint32_t i; + + /* Get received frame */ + if (LL_OK != ETH_DMA_GetReceiveFrame_Int(&EthHandle)) + { + LOG_D("receive frame faild"); + return NULL; + } + + /* Obtain the size of the packet */ + len = (EthHandle.stcRxFrame).u32Len; + rxBuffer = (uint8_t *)(EthHandle.stcRxFrame).u32Buf; + LOG_D("receive frame len : %d", len); + if (len > 0UL) + { + /* Allocate a pbuf chain of pbufs from the Lwip buffer pool */ + p = pbuf_alloc(PBUF_RAW, (uint16_t)len, PBUF_POOL); + } + if (p != NULL) + { + DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc; + bufferOffset = 0UL; + for (q = p; q != NULL; q = q->next) + { + byteCnt = q->len; + payloadOffset = 0UL; + /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size */ + while ((byteCnt + bufferOffset) > ETH_RX_BUF_SIZE) + { + /* Copy data to pbuf */ + SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), (ETH_RX_BUF_SIZE - bufferOffset)); + /* Point to next descriptor */ + DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr); + rxBuffer = (uint8_t *)(DmaRxDesc->u32Buf1Addr); + byteCnt = byteCnt - (ETH_RX_BUF_SIZE - bufferOffset); + payloadOffset = payloadOffset + (ETH_RX_BUF_SIZE - bufferOffset); + bufferOffset = 0UL; + } + /* Copy remaining data in pbuf */ + SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), byteCnt); + bufferOffset = bufferOffset + byteCnt; + } + } + /* Release descriptors to DMA */ + DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc; + for (i = 0UL; i < (EthHandle.stcRxFrame).u32SegCount; i++) + { + DmaRxDesc->u32ControlStatus |= ETH_DMA_RXDESC_OWN; + DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr); + } + /* Clear Segment_Count */ + (EthHandle.stcRxFrame).u32SegCount = 0UL; + + /* When Rx Buffer unavailable flag is set, clear it and resume reception */ + if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RUS)) + { + /* Clear DMA RUS flag */ + ETH_DMA_ClearStatus(ETH_DMA_FLAG_RUS); + /* Resume DMA reception */ + WRITE_REG32(CM_ETH->DMA_RXPOLLR, 0UL); + } + + return p; +} + +static void hc32_eth_irq_handle(stc_eth_handle_t *eth_handle) +{ + rt_err_t result; + + (void)eth_handle; + /* Frame received */ + if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RIS)) + { + result = eth_device_ready(&(hc32_eth_device.parent)); + if (result != RT_EOK) + { + LOG_I("eth rx complete callback err = %d", result); + } + /* Clear the Eth DMA Rx IT pending bits */ + ETH_DMA_ClearStatus(ETH_DMA_FLAG_RIS | ETH_DMA_FLAG_NIS); + } +} + +/* interrupt service routine */ +static void eth_global_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_eth_irq_handle(&EthHandle); + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_phy_link_change(void) +{ + static rt_uint8_t phy_status = 0; + rt_uint8_t phy_status_new = 0; + uint16_t u16RegVal = 0U; + uint16_t u16Page = 0U; + + /* Switch page */ + (void)ETH_PHY_ReadReg(&EthHandle, PHY_PSR, &u16Page); + if (u16Page != PHY_PAGE_ADDR_0) + { + u16RegVal = PHY_PAGE_ADDR_0; + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal); + } + /* Read PHY_BSR */ + (void)ETH_PHY_ReadReg(&EthHandle, PHY_BASIC_STATUS_REG, &u16RegVal); + LOG_D("phy basic status reg is 0x%X", u16RegVal); + if ((0x0000U != u16RegVal) && (0xFFFFU != u16RegVal)) + { + if (u16RegVal & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK)) + { + phy_status_new |= ETH_PHY_LINK; + if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_10BASE_T_FD))) + { + phy_status_new |= ETH_PHY_FULL_DUPLEX; + } + if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_100BASE_TX_HD))) + { + phy_status_new |= ETH_PHY_100M; + } + } + } + /* Restore page */ + if (u16Page != PHY_PAGE_ADDR_0) + { + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16Page); + } + + if (phy_status != phy_status_new) + { + phy_status = phy_status_new; + if (phy_status & ETH_PHY_LINK) + { + if (phy_status & ETH_PHY_FULL_DUPLEX) + { + hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL; + } + else + { + hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_HALF; + } + if (phy_status & ETH_PHY_100M) + { + hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M; + } + else + { + hc32_eth_device.eth_speed = ETH_MAC_SPEED_10M; + } + LOG_D("link up"); + eth_device_linkchange(&hc32_eth_device.parent, RT_TRUE); + } + else + { + LOG_I("link down"); + eth_device_linkchange(&hc32_eth_device.parent, RT_FALSE); + } + } +} + +#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII) +static void eth_phy_irq_handler(void *args) +{ + rt_uint16_t status = 0; + + ETH_PHY_ReadReg(&EthHandle, PHY_IISDR, &status); + LOG_D("phy interrupt status reg is 0x%X", status); + hc32_phy_link_change(); +} +#endif + +static void hc32_phy_monitor_thread(void *parameter) +{ + uint8_t phy_addr = 0xFF; + uint8_t detected_count = 0; + + /* phy search */ + while (phy_addr == 0xFF) + { + rt_uint16_t i, temp; + + for (i = 0; i <= 0x1F; i++) + { + EthHandle.stcCommInit.u16PhyAddr = i; + ETH_PHY_ReadReg(&EthHandle, PHY_ID1_REG, &temp); + if (temp != 0xFFFF && temp != 0x00) + { + phy_addr = i; + break; + } + } + detected_count++; + rt_thread_mdelay(1000); + if (detected_count > 10) + { + LOG_E("No PHY device was detected!"); + } + } + LOG_D("Found a phy, address:0x%02X", phy_addr); + + /* Reset PHY */ + ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); + rt_thread_mdelay(2000); + ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK); + hc32_phy_link_change(); +#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII) + /* configuration intterrupt pin */ + rt_pin_mode(ETH_PHY_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(ETH_PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_irq_handler, (void *)"callbackargs"); + rt_pin_irq_enable(ETH_PHY_INT_PIN, PIN_IRQ_ENABLE); + + uint16_t u16RegVal; + /* Configure PHY to generate an interrupt when Eth Link state changes */ + u16RegVal = PHY_PAGE_ADDR_7; + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal); + /* Enable Interrupt on change of link status */ + (void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal); + SET_REG16_BIT(u16RegVal, PHY_INT_LINK_CHANGE); + (void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal); + u16RegVal = PHY_PAGE_ADDR_0; + (void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal); +#else + hc32_eth_device.poll_link_timer = rt_timer_create("eth_phy_link", (void (*)(void *))hc32_phy_link_change, + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + if (!hc32_eth_device.poll_link_timer || rt_timer_start(hc32_eth_device.poll_link_timer) != RT_EOK) + { + LOG_E("Start eth phy link change detection timer failed"); + } +#endif +} + +/* Register the eth device */ +static int rt_hw_hc32_eth_init(void) +{ + rt_err_t state = RT_EOK; + + /* register eth handler */ + hc32_install_irq_handler(&hc32_eth_device.irq_config, hc32_eth_device.irq_callback, RT_FALSE); + /* Prepare receive and send buffers */ + EthRxBuff = (rt_uint8_t *)rt_calloc(ETH_RX_BUF_NUM, ETH_MAX_PACKET_SIZE); + if (EthRxBuff == RT_NULL) + { + LOG_E("No memory"); + state = -RT_ENOMEM; + goto __exit; + } + EthTxBuff = (rt_uint8_t *)rt_calloc(ETH_TX_BUF_NUM, ETH_MAX_PACKET_SIZE); + if (EthTxBuff == RT_NULL) + { + LOG_E("No memory"); + state = -RT_ENOMEM; + goto __exit; + } + EthDmaRxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_RX_BUF_NUM, sizeof(stc_eth_dma_desc_t)); + if (EthDmaRxDscrTab == RT_NULL) + { + LOG_E("No memory"); + state = -RT_ENOMEM; + goto __exit; + } + EthDmaTxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_TX_BUF_NUM, sizeof(stc_eth_dma_desc_t)); + if (EthDmaTxDscrTab == RT_NULL) + { + LOG_E("No memory"); + state = -RT_ENOMEM; + goto __exit; + } + + hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M; + hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL; + /* 00-80 uid */ + hc32_eth_device.dev_addr[0] = 0x02; + hc32_eth_device.dev_addr[1] = 0x80; + hc32_eth_device.dev_addr[2] = 0x00; + /* generate MAC addr from unique ID */ + hc32_eth_device.dev_addr[3] = (rt_uint8_t)READ_REG32(CM_EFM->UQID0); + hc32_eth_device.dev_addr[4] = (rt_uint8_t)READ_REG32(CM_EFM->UQID1); + hc32_eth_device.dev_addr[5] = (rt_uint8_t)READ_REG32(CM_EFM->UQID2); + + hc32_eth_device.parent.parent.init = rt_hc32_eth_init; + hc32_eth_device.parent.parent.open = rt_hc32_eth_open; + hc32_eth_device.parent.parent.close = rt_hc32_eth_close; + hc32_eth_device.parent.parent.read = rt_hc32_eth_read; + hc32_eth_device.parent.parent.write = rt_hc32_eth_write; + hc32_eth_device.parent.parent.control = rt_hc32_eth_control; + hc32_eth_device.parent.parent.user_data = RT_NULL; + hc32_eth_device.parent.eth_rx = rt_hc32_eth_rx; + hc32_eth_device.parent.eth_tx = rt_hc32_eth_tx; + /* register eth device */ + state = eth_device_init(&(hc32_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("eth device init success"); + } + else + { + LOG_E("eth device init faild: %d", state); + state = -RT_ERROR; + goto __exit; + } + + /* start phy monitor */ + rt_thread_t tid; + tid = rt_thread_create("phy_monitor", hc32_phy_monitor_thread, RT_NULL, 1024, 12, 5); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + state = -RT_ERROR; + } + +__exit: + if (state != RT_EOK) + { + if (EthRxBuff) + { + rt_free(EthRxBuff); + } + if (EthTxBuff) + { + rt_free(EthTxBuff); + } + if (EthDmaRxDscrTab) + { + rt_free(EthDmaRxDscrTab); + } + if (EthDmaTxDscrTab) + { + rt_free(EthDmaTxDscrTab); + } + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_hc32_eth_init); + +#endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_eth.h b/bsp/hc32/libraries/hc32_drivers/drv_eth.h new file mode 100644 index 0000000000..d23cd0c32b --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_eth.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* The PHY basic control register */ +#define PHY_BASIC_CONTROL_REG 0x00U +#define PHY_RESET_MASK (1<<15) +#define PHY_AUTO_NEGOTIATION_MASK (1<<12) + +/* The PHY basic status register */ +#define PHY_BASIC_STATUS_REG 0x01U +#define PHY_LINKED_STATUS_MASK (1<<2) +#define PHY_AUTONEGO_COMPLETE_MASK (1<<5) + +/* The PHY ID one register */ +#define PHY_ID1_REG 0x02U + + +#ifdef PHY_USING_RTL8201F +/* Extended PHY Registers */ +#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */ +#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */ +#define PHY_PSR (0x1FU) /*!< Page Select Register */ +#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */ +#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */ + +/* The following parameters will return to default values after a software reset */ +#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */ + +#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */ +#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */ +#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */ +#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */ + +#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */ +#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */ + +#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */ +#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */ +#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */ + +#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */ +#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */ +#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */ +#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */ +#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */ +#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */ +#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_ETH_H__ */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c new file mode 100644 index 0000000000..ed848782fa --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -0,0 +1,505 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include "drv_gpio.h" +#include "board_config.h" + +#ifdef RT_USING_PIN + +#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) +#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) +#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F)) +#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin))) + +#if defined (HC32F4A0) + #define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) +#endif + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +#ifndef HC32_PIN_CONFIG +#define HC32_PIN_CONFIG(pin, callback, config) \ + { \ + .pinbit = pin, \ + .irq_callback = callback, \ + .irq_config = config, \ + } +#endif /* HC32_PIN_CONFIG */ + +static void extint0_irq_handler(void); +static void extint1_irq_handler(void); +static void extint2_irq_handler(void); +static void extint3_irq_handler(void); +static void extint4_irq_handler(void); +static void extint5_irq_handler(void); +static void extint6_irq_handler(void); +static void extint7_irq_handler(void); +static void extint8_irq_handler(void); +static void extint9_irq_handler(void); +static void extint10_irq_handler(void); +static void extint11_irq_handler(void); +static void extint12_irq_handler(void); +static void extint13_irq_handler(void); +static void extint14_irq_handler(void); +static void extint15_irq_handler(void); + +static struct hc32_pin_irq_map pin_irq_map[] = +{ + HC32_PIN_CONFIG(GPIO_PIN_00, extint0_irq_handler, EXTINT0_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_01, extint1_irq_handler, EXTINT1_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_02, extint2_irq_handler, EXTINT2_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_03, extint3_irq_handler, EXTINT3_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_04, extint4_irq_handler, EXTINT4_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_05, extint5_irq_handler, EXTINT5_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_06, extint6_irq_handler, EXTINT6_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_07, extint7_irq_handler, EXTINT7_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_08, extint8_irq_handler, EXTINT8_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_09, extint9_irq_handler, EXTINT9_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_10, extint10_irq_handler, EXTINT10_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_11, extint11_irq_handler, EXTINT11_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_12, extint12_irq_handler, EXTINT12_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_13, extint13_irq_handler, EXTINT13_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_14, extint14_irq_handler, EXTINT14_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_15, extint15_irq_handler, EXTINT15_IRQ_CONFIG), +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void pin_irq_handler(rt_uint16_t pinbit) +{ + rt_int32_t irqindex = -1; + + if (SET == EXTINT_GetExtIntStatus(pinbit)) + { + EXTINT_ClearExtIntStatus(pinbit); + irqindex = __CLZ(__RBIT(pinbit)); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } +} + +static void extint0_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[0].pinbit); + rt_interrupt_leave(); +} + +static void extint1_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[1].pinbit); + rt_interrupt_leave(); +} + +static void extint2_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[2].pinbit); + rt_interrupt_leave(); +} + +static void extint3_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[3].pinbit); + rt_interrupt_leave(); +} + +static void extint4_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[4].pinbit); + rt_interrupt_leave(); +} + +static void extint5_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[5].pinbit); + rt_interrupt_leave(); +} + +static void extint6_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[6].pinbit); + rt_interrupt_leave(); +} + +static void extint7_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[7].pinbit); + rt_interrupt_leave(); +} + +static void extint8_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[8].pinbit); + rt_interrupt_leave(); +} + +static void extint9_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[9].pinbit); + rt_interrupt_leave(); +} + +static void extint10_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[10].pinbit); + rt_interrupt_leave(); +} + +static void extint11_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[11].pinbit); + rt_interrupt_leave(); +} + +static void extint12_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[12].pinbit); + rt_interrupt_leave(); +} + +static void extint13_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[13].pinbit); + rt_interrupt_leave(); +} + +static void extint14_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[14].pinbit); + rt_interrupt_leave(); +} + +static void extint15_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[15].pinbit); + rt_interrupt_leave(); +} + +static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + stc_gpio_init_t stcGpioInit; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + GPIO_StructInit(&stcGpioInit); + switch (mode) + { + case PIN_MODE_OUTPUT: + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_CMOS; + break; + case PIN_MODE_INPUT: + stcGpioInit.u16PinDir = PIN_DIR_IN; + break; + case PIN_MODE_INPUT_PULLUP: + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_ON; + break; + case PIN_MODE_INPUT_PULLDOWN: + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_OFF; + break; + case PIN_MODE_OUTPUT_OD: + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_NMOS; + break; + default: + break; + } + GPIO_Init(GPIO_PORT(pin), GPIO_PIN(pin), &stcGpioInit); +} + +static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + GPIO_ResetPins(gpio_port, gpio_pin); + } + else + { + GPIO_SetPins(gpio_port, gpio_pin); + } + } +} + +static int hc32_pin_read(struct rt_device *device, rt_base_t pin) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_RESET == GPIO_ReadInputPins(gpio_port, gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt) +{ + __IO uint16_t *PCRx; + uint16_t pin_num; + + pin_num = __CLZ(__RBIT(u16Pin)); + PCRx = (__IO uint16_t *)((uint32_t)(&CM_GPIO->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL)); + MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt); +} + +static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + struct hc32_pin_irq_map *irq_map; + rt_base_t level; + rt_int32_t irqindex = -1; + stc_extint_init_t stcExtIntInit; + uint8_t gpio_port; + uint16_t gpio_pin; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + irq_map = &pin_irq_map[irqindex]; + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + EXTINT_StructInit(&stcExtIntInit); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + stcExtIntInit.u32Edge = EXTINT_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + stcExtIntInit.u32Edge = EXTINT_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + stcExtIntInit.u32Edge = EXTINT_TRIG_BOTH; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + stcExtIntInit.u32Edge = EXTINT_TRIG_LOW; + break; + } + EXTINT_Init(gpio_pin, &stcExtIntInit); + NVIC_EnableIRQ(irq_map->irq_config.irq_num); + gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_ON); + } + else + { + level = rt_hw_interrupt_disable(); + gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_OFF); + NVIC_DisableIRQ(irq_map->irq_config.irq_num); + } + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_base_t hc32_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + if ((name_len < 4) || (name_len >= 6)) + { + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} + +static const struct rt_pin_ops hc32_pin_ops = +{ + hc32_pin_mode, + hc32_pin_write, + hc32_pin_read, + hc32_pin_attach_irq, + hc32_pin_detach_irq, + hc32_pin_irq_enable, + hc32_pin_get, +}; + +int rt_hw_pin_init(void) +{ + uint8_t u32MaxExtInt; + + /* register extint */ + u32MaxExtInt = ITEM_NUM(pin_irq_map); + for (uint8_t i = 0; i < u32MaxExtInt; i++) + { + hc32_install_irq_handler(&pin_irq_map[i].irq_config, pin_irq_map[i].irq_callback, RT_FALSE); + } + + return rt_device_pin_register("pin", &hc32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.h b/bsp/hc32/libraries/hc32_drivers/drv_gpio.h new file mode 100644 index 0000000000..92e796cf40 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include "drv_irq.h" + +#if defined(RT_USING_PIN) + +#define __HC_PORT(port) GPIO_PORT_##port +#define GET_PIN(PORT, PIN) (rt_base_t)(((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) + +struct hc32_pin_irq_map +{ + rt_uint16_t pinbit; + func_ptr_t irq_callback; + struct hc32_irq_config irq_config; +}; + +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c new file mode 100644 index 0000000000..6b0ad6b303 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c @@ -0,0 +1,551 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include + +#if defined(RT_USING_HWTIMER) + +#if defined(BSP_USING_TIMER1) || defined(BSP_USING_TIMER2) || defined(BSP_USING_TIMER3) || \ + defined(BSP_USING_TIMER4) || defined(BSP_USING_TIMER5) || defined(BSP_USING_TIMER6) || \ + defined(BSP_USING_TIMER7) || defined(BSP_USING_TIMER8) || defined(BSP_USING_TIMER9) || \ + defined(BSP_USING_TIMER10) || defined(BSP_USING_TIMER11) || defined(BSP_USING_TIMER12) + + +#include "drv_hwtimer.h" +#include "drv_irq.h" + +enum +{ +#ifdef BSP_USING_TIMER1 + TIMER1_INDEX, +#endif +#ifdef BSP_USING_TIMER2 + TIMER2_INDEX, +#endif +#ifdef BSP_USING_TIMER3 + TIMER3_INDEX, +#endif +#ifdef BSP_USING_TIMER4 + TIMER4_INDEX, +#endif +#ifdef BSP_USING_TIMER5 + TIMER5_INDEX, +#endif +#ifdef BSP_USING_TIMER6 + TIMER6_INDEX, +#endif +#ifdef BSP_USING_TIMER7 + TIMER7_INDEX, +#endif +#ifdef BSP_USING_TIMER8 + TIMER8_INDEX, +#endif +#ifdef BSP_USING_TIMER9 + TIMER9_INDEX, +#endif +#ifdef BSP_USING_TIMER10 + TIMER10_INDEX, +#endif +#ifdef BSP_USING_TIMER11 + TIMER11_INDEX, +#endif +#ifdef BSP_USING_TIMER12 + TIMER12_INDEX, +#endif +}; + +#ifdef BSP_USING_TIMER1 + static void timer1_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER2 + static void timer2_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER3 + static void timer3_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER4 + static void timer4_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER5 + static void timer5_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER6 + static void timer6_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER7 + static void timer7_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER8 + static void timer8_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER9 + static void timer9_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER10 + static void timer10_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER11 + static void timer11_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER12 + static void timer12_irq_handler(void); +#endif + +struct hc32_hwtimer_config +{ + rt_hwtimer_t time_device; + CM_TMRA_TypeDef *timer_periph; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; + uint32_t extend_div; + uint32_t extend_cnt; + char *name; +}; + +#ifndef HC32_TIMER_CONFIG +#define HC32_TIMER_CONFIG(periph, irq, label, src, irq_info) \ + { \ + .timer_periph = periph, \ + .irq_callback = irq, \ + .name = label, \ + .irq_config = irq_info, \ + .irq_config.int_src = src, \ + } +#endif /* HC32_TIMER_CONFIG */ + +static struct hc32_hwtimer_config hwtimer_obj[] = +{ +#ifdef BSP_USING_TIMER1 + HC32_TIMER_CONFIG(CM_TMRA_1, timer1_irq_handler, "timer1", INT_SRC_TMRA_1_OVF, TIMER1_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER2 + HC32_TIMER_CONFIG(CM_TMRA_2, timer2_irq_handler, "timer2", INT_SRC_TMRA_2_OVF, TIMER2_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER3 + HC32_TIMER_CONFIG(CM_TMRA_3, timer3_irq_handler, "timer3", INT_SRC_TMRA_3_OVF, TIMER3_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER4 + HC32_TIMER_CONFIG(CM_TMRA_4, timer4_irq_handler, "timer4", INT_SRC_TMRA_4_OVF, TIMER4_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER5 + HC32_TIMER_CONFIG(CM_TMRA_5, timer5_irq_handler, "timer5", INT_SRC_TMRA_5_OVF, TIMER5_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER6 + HC32_TIMER_CONFIG(CM_TMRA_6, timer6_irq_handler, "timer6", INT_SRC_TMRA_6_OVF, TIMER6_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER7 + HC32_TIMER_CONFIG(CM_TMRA_7, timer7_irq_handler, "timer7", INT_SRC_TMRA_7_OVF, TIMER7_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER8 + HC32_TIMER_CONFIG(CM_TMRA_8, timer8_irq_handler, "timer8", INT_SRC_TMRA_8_OVF, TIMER8_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER9 + HC32_TIMER_CONFIG(CM_TMRA_9, timer9_irq_handler, "timer9", INT_SRC_TMRA_9_OVF, TIMER9_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER10 + HC32_TIMER_CONFIG(CM_TMRA_10, timer10_irq_handler, "timer10", INT_SRC_TMRA_10_OVF, TIMER10_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER11 + HC32_TIMER_CONFIG(CM_TMRA_11, timer11_irq_handler, "timer11", INT_SRC_TMRA_11_OVF, TIMER11_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER12 + HC32_TIMER_CONFIG(CM_TMRA_12, timer12_irq_handler, "timer12", INT_SRC_TMRA_12_OVF, TIMER12_IRQ_CONFIG), +#endif +}; + +static void hc32_timer_irq_handler(struct hc32_hwtimer_config *timer_config) +{ + if ((++timer_config->extend_cnt) >= timer_config->extend_div) + { + timer_config->extend_cnt = 0; + rt_device_hwtimer_isr(&timer_config->time_device); + } + TMRA_ClearStatus(timer_config->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF)); +} + +#ifdef BSP_USING_TIMER1 +static void timer1_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER1_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER2 +static void timer2_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER2_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER3 +static void timer3_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER3_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER4 +static void timer4_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER4_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER5 +static void timer5_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER5_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER6 +static void timer6_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER6_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER7 +static void timer7_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER7_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER8 +static void timer8_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER8_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER9 +static void timer9_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER9_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER10 +static void timer10_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER10_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER11 +static void timer11_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER11_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER12 +static void timer12_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER12_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static rt_uint16_t hc32_timer_get_unit_number(CM_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_timer_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_timer_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + FCG_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +static void hc32_timer_get_div_value(CM_TMRA_TypeDef *TMRAx, uint32_t freq, uint16_t *div, uint32_t *extend_div) +{ + stc_clock_freq_t stcClkFreq; + rt_uint32_t divisor, remainder; + rt_uint16_t div_val; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_timer_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.u32Pclk1Freq; + } + else + { + clk_freq = stcClkFreq.u32Pclk0Freq; + } + divisor = clk_freq / freq; + remainder = clk_freq % freq; + for (div_val = 1; div_val <= 1024; div_val <<= 1) + { + if (((divisor % 2) == 0) && (remainder == 0)) + { + remainder = divisor % 2; + divisor = divisor / 2; + } + else + { + break; + } + } + *extend_div = divisor; + *div = (__CLZ(__RBIT(div_val))) << TMRA_BCSTR_CKDIV_POS; +} + +static void hc32_timer_interrupt_config(struct rt_hwtimer_device *timer, en_functional_state_t enNewState) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + + timer_config = (struct hc32_hwtimer_config *)timer; + if (INT_SRC_MAX == timer_config->irq_config.int_src) + { + LOG_D("%s interrupt init failed", timer_config->name); + return; + } + + if (ENABLE == enNewState) + { + /* Enable the specified interrupts of Timer */ + hc32_install_irq_handler(&timer_config->irq_config, timer_config->irq_callback, RT_FALSE); + NVIC_EnableIRQ(timer_config->irq_config.irq_num); + TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, ENABLE); + } + else + { + /* Disable the specified interrupts of Timer */ + TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, DISABLE); + NVIC_DisableIRQ(timer_config->irq_config.irq_num); + } +} + +static void hc32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + stc_tmra_init_t stcTmraInit; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + if (state) + { + /* Enable Timer peripheral clock. */ + hc32_timer_clock_config(timer_config->timer_periph, ENABLE); + TMRA_DeInit(timer_config->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.sw_count.u16CountDir = TMRA_DIR_UP; + TMRA_Init(timer_config->timer_periph, &stcTmraInit); + LOG_D("%s init success", timer_config->name); + } + else + { + TMRA_DeInit(timer_config->timer_periph); + hc32_timer_interrupt_config(timer, DISABLE); + /* Disable Timer peripheral clock. */ + hc32_timer_clock_config(timer_config->timer_periph, DISABLE); + } +} + +static rt_err_t hc32_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + rt_err_t result = RT_EOK; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + if (mode == HWTIMER_MODE_ONESHOT) + { + TMRA_CountReloadCmd(timer_config->timer_periph, DISABLE); + } + else + { + TMRA_CountReloadCmd(timer_config->timer_periph, ENABLE); + } + timer_config->extend_cnt = 0; + TMRA_SetCountValue(timer_config->timer_periph, 0); + TMRA_SetPeriodValue(timer_config->timer_periph, cnt - 1); + hc32_timer_interrupt_config(timer, ENABLE); + TMRA_Start(timer_config->timer_periph); + + return result; +} + +static void hc32_timer_stop(struct rt_hwtimer_device *timer) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + /* stop timer */ + TMRA_Stop(timer_config->timer_periph); + hc32_timer_interrupt_config(timer, DISABLE); + TMRA_SetCountValue(timer_config->timer_periph, 0); +} + +static rt_uint32_t hc32_timer_get_counter(struct rt_hwtimer_device *timer) +{ + rt_uint32_t count_val; + rt_uint32_t period_val; + float temp; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + period_val = TMRA_GetPeriodValue(timer_config->timer_periph); + count_val = TMRA_GetCountValue(timer_config->timer_periph); + temp = (timer_config->extend_cnt * period_val + count_val); + temp = temp / (timer_config->extend_div * period_val) * period_val; + count_val = (rt_uint32_t)temp; + + return count_val; +} + +static rt_err_t hc32_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(args != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t div_val; + rt_uint32_t extend_div_val; + + /* set timer frequency */ + freq = *((rt_uint32_t *)args); + hc32_timer_get_div_value(timer_config->timer_periph, freq, &div_val, &extend_div_val); + TMRA_SetClockDiv(timer_config->timer_periph, div_val); + timer_config->extend_div = extend_div_val; + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static const struct rt_hwtimer_ops hwtimer_ops = +{ + .init = hc32_timer_init, + .start = hc32_timer_start, + .stop = hc32_timer_stop, + .count_get = hc32_timer_get_counter, + .control = hc32_timer_ctrl, +}; + +static const struct rt_hwtimer_info hwtimer_info = +{ + .maxfreq = 30000000, + .minfreq = 1000, + .maxcnt = 0xFFFF, + .cntmode = HWTIMER_CNTMODE_UP, +}; + +static int rt_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(hwtimer_obj) / sizeof(hwtimer_obj[0]); i++) + { + hwtimer_obj[i].time_device.info = &hwtimer_info; + hwtimer_obj[i].time_device.ops = &hwtimer_ops; + if (rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].name, hwtimer_obj[i].timer_periph) == RT_EOK) + { + LOG_D("%s register success", hwtimer_obj[i].name); + } + else + { + LOG_E("%s register failed", hwtimer_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hwtimer_init); + +#endif + +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h new file mode 100644 index 0000000000..090cbdfdf8 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TIMER1 +#ifndef TIMER1_IRQ_CONFIG +#define TIMER1_IRQ_CONFIG \ + { \ + .irq_num = TIMER1_CNT_INT_IRQn, \ + .irq_prio = TIMER1_CNT_INT_PRIO, \ + } +#endif /* TIMER1_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER1 */ + +#ifdef BSP_USING_TIMER2 +#ifndef TIMER2_IRQ_CONFIG +#define TIMER2_IRQ_CONFIG \ + { \ + .irq_num = TIMER2_CNT_INT_IRQn, \ + .irq_prio = TIMER2_CNT_INT_PRIO, \ + } +#endif /* TIMER2_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER2 */ + +#ifdef BSP_USING_TIMER3 +#ifndef TIMER3_IRQ_CONFIG +#define TIMER3_IRQ_CONFIG \ + { \ + .irq_num = TIMER3_CNT_INT_IRQn, \ + .irq_prio = TIMER3_CNT_INT_PRIO, \ + } +#endif /* TIMER3_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER3 */ + +#ifdef BSP_USING_TIMER4 +#ifndef TIMER4_IRQ_CONFIG +#define TIMER4_IRQ_CONFIG \ + { \ + .irq_num = TIMER4_CNT_INT_IRQn, \ + .irq_prio = TIMER4_CNT_INT_PRIO, \ + } +#endif /* TIMER4_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER4 */ + +#ifdef BSP_USING_TIMER5 +#ifndef TIMER5_IRQ_CONFIG +#define TIMER5_IRQ_CONFIG \ + { \ + .irq_num = TIMER5_CNT_INT_IRQn, \ + .irq_prio = TIMER5_CNT_INT_PRIO, \ + } +#endif /* TIMER5_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER5 */ + +#ifdef BSP_USING_TIMER6 +#ifndef TIMER6_IRQ_CONFIG +#define TIMER6_IRQ_CONFIG \ + { \ + .irq_num = TIMER6_CNT_INT_IRQn, \ + .irq_prio = TIMER6_CNT_INT_PRIO, \ + } +#endif /* TIMER6_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER6 */ + +#ifdef BSP_USING_TIMER7 +#ifndef TIMER7_IRQ_CONFIG +#define TIMER7_IRQ_CONFIG \ + { \ + .irq_num = TIMER7_CNT_INT_IRQn, \ + .irq_prio = TIMER7_CNT_INT_PRIO, \ + } +#endif /* TIMER7_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER7 */ + +#ifdef BSP_USING_TIMER8 +#ifndef TIMER8_IRQ_CONFIG +#define TIMER8_IRQ_CONFIG \ + { \ + .irq_num = TIMER8_CNT_INT_IRQn, \ + .irq_prio = TIMER8_CNT_INT_PRIO, \ + } +#endif /* TIMER8_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER8 */ + +#ifdef BSP_USING_TIMER9 +#ifndef TIMER9_IRQ_CONFIG +#define TIMER9_IRQ_CONFIG \ + { \ + .irq_num = TIMER9_CNT_INT_IRQn, \ + .irq_prio = TIMER9_CNT_INT_PRIO, \ + } +#endif /* TIMER9_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER9 */ + +#ifdef BSP_USING_TIMER10 +#ifndef TIMER10_IRQ_CONFIG +#define TIMER10_IRQ_CONFIG \ + { \ + .irq_num = TIMER10_CNT_INT_IRQn, \ + .irq_prio = TIMER10_CNT_INT_PRIO, \ + } +#endif /* TIMER10_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER10 */ + +#ifdef BSP_USING_TIMER11 +#ifndef TIMER11_IRQ_CONFIG +#define TIMER11_IRQ_CONFIG \ + { \ + .irq_num = TIMER11_CNT_INT_IRQn, \ + .irq_prio = TIMER11_CNT_INT_PRIO, \ + } +#endif /* TIMER11_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER11 */ + +#ifdef BSP_USING_TIMER12 +#ifndef TIMER12_IRQ_CONFIG +#define TIMER12_IRQ_CONFIG \ + { \ + .irq_num = TIMER12_CNT_INT_IRQn, \ + .irq_prio = TIMER12_CNT_INT_PRIO, \ + } +#endif /* TIMER12_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER12 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.c b/bsp/hc32/libraries/hc32_drivers/drv_irq.c new file mode 100644 index 0000000000..3f8f44b7bb --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "drv_irq.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable) +{ + rt_err_t result = -RT_ERROR; + stc_irq_signin_config_t stcIrqSignConfig; + + RT_ASSERT(RT_NULL != irq_config); + RT_ASSERT(RT_NULL != irq_hdr); + + stcIrqSignConfig.enIRQn = irq_config->irq_num; + stcIrqSignConfig.enIntSrc = irq_config->int_src; + stcIrqSignConfig.pfnCallback = irq_hdr; + if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) + { + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, irq_config->irq_prio); + if (RT_TRUE == irq_enable) + { + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); + } + else + { + NVIC_DisableIRQ(stcIrqSignConfig.enIRQn); + } + result = RT_EOK; + } + return result; +} + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.h b/bsp/hc32/libraries/hc32_drivers/drv_irq.h new file mode 100644 index 0000000000..add06cd842 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_IRQ_H__ +#define __DRV_IRQ_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ll.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_irq_config +{ + IRQn_Type irq_num; + uint32_t irq_prio; + en_int_src_t int_src; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_IRQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_log.h b/bsp/hc32/libraries/hc32_drivers/drv_log.h new file mode 100644 index 0000000000..044fff46dc --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG + #define DBG_TAG "drv" +#else + #define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c new file mode 100644 index 0000000000..e2011befe3 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c @@ -0,0 +1,472 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include + +#ifdef RT_USING_PULSE_ENCODER + +#if defined(BSP_USING_PULSE_ENCODER1) || defined(BSP_USING_PULSE_ENCODER2) || defined(BSP_USING_PULSE_ENCODER3) || \ + defined(BSP_USING_PULSE_ENCODER4) || defined(BSP_USING_PULSE_ENCODER5) || defined(BSP_USING_PULSE_ENCODER6) || \ + defined(BSP_USING_PULSE_ENCODER7) || defined(BSP_USING_PULSE_ENCODER8) || defined(BSP_USING_PULSE_ENCODER9) || \ + defined(BSP_USING_PULSE_ENCODER10) || defined(BSP_USING_PULSE_ENCODER11) || defined(BSP_USING_PULSE_ENCODER12) + +#include "drv_pulse_encoder.h" +#include "drv_irq.h" + +#define TIMER_AUTO_RELOAD_VALUE (0xFFFFU) + +enum +{ +#ifdef BSP_USING_PULSE_ENCODER1 + PULSE_ENCODER1_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER2 + PULSE_ENCODER2_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER3 + PULSE_ENCODER3_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER4 + PULSE_ENCODER4_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER5 + PULSE_ENCODER5_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER6 + PULSE_ENCODER6_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER7 + PULSE_ENCODER7_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER8 + PULSE_ENCODER8_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER9 + PULSE_ENCODER9_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER10 + PULSE_ENCODER10_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER11 + PULSE_ENCODER11_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER12 + PULSE_ENCODER12_INDEX, +#endif +}; + +#ifdef BSP_USING_PULSE_ENCODER1 + static void pulse_encoder1_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER2 + static void pulse_encoder2_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER3 + static void pulse_encoder3_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER4 + static void pulse_encoder4_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER5 + static void pulse_encoder5_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER6 + static void pulse_encoder6_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER7 + static void pulse_encoder7_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER8 + static void pulse_encoder8_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER9 + static void pulse_encoder9_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER10 + static void pulse_encoder10_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER11 + static void pulse_encoder11_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER12 + static void pulse_encoder12_irq_handler(void); +#endif + +struct hc32_pulse_encoder_config +{ + struct rt_pulse_encoder_device pulse_encoder; + CM_TMRA_TypeDef *timer_periph; + struct hc32_irq_config ovf_irq_config; + struct hc32_irq_config udf_irq_config; + func_ptr_t irq_callback; + rt_int32_t ovf_udf_count; + char *name; +}; + +#ifndef HC32_PULSE_ENCODER_CONFIG +#define HC32_PULSE_ENCODER_CONFIG(periph, irq, label, ovf_src, udf_src, \ + ovf_irq_info, udf_irq_info) \ + { \ + .timer_periph = periph, \ + .irq_callback = irq, \ + .name = label, \ + .ovf_irq_config = ovf_irq_info, \ + .udf_irq_config = udf_irq_info, \ + .ovf_irq_config.int_src = ovf_src, \ + .udf_irq_config.int_src = udf_src, \ + } +#endif /* HC32_PULSE_ENCODER_CONFIG */ + +static struct hc32_pulse_encoder_config pulse_encoder_obj[] = +{ +#ifdef BSP_USING_PULSE_ENCODER1 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_1, pulse_encoder1_irq_handler, "pulse1", INT_SRC_TMRA_1_OVF, INT_SRC_TMRA_1_UDF, + PULSE_ENCODER1_OVF_IRQ_CONFIG, PULSE_ENCODER1_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER2 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_2, pulse_encoder2_irq_handler, "pulse2", INT_SRC_TMRA_2_OVF, INT_SRC_TMRA_2_UDF, + PULSE_ENCODER2_OVF_IRQ_CONFIG, PULSE_ENCODER2_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER3 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_3, pulse_encoder3_irq_handler, "pulse3", INT_SRC_TMRA_3_OVF, INT_SRC_TMRA_3_UDF, + PULSE_ENCODER3_OVF_IRQ_CONFIG, PULSE_ENCODER3_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER4 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_4, pulse_encoder4_irq_handler, "pulse4", INT_SRC_TMRA_4_OVF, INT_SRC_TMRA_4_UDF, + PULSE_ENCODER4_OVF_IRQ_CONFIG, PULSE_ENCODER4_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER5 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_5, pulse_encoder5_irq_handler, "pulse5", INT_SRC_TMRA_5_OVF, INT_SRC_TMRA_5_UDF, + PULSE_ENCODER5_OVF_IRQ_CONFIG, PULSE_ENCODER5_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER6 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_6, pulse_encoder6_irq_handler, "pulse6", INT_SRC_TMRA_6_OVF, INT_SRC_TMRA_6_UDF, + PULSE_ENCODER6_OVF_IRQ_CONFIG, PULSE_ENCODER6_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER7 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_7, pulse_encoder7_irq_handler, "pulse7", INT_SRC_TMRA_7_OVF, INT_SRC_TMRA_7_UDF, + PULSE_ENCODER7_OVF_IRQ_CONFIG, PULSE_ENCODER7_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER8 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_8, pulse_encoder8_irq_handler, "pulse8", INT_SRC_TMRA_8_OVF, INT_SRC_TMRA_8_UDF, + PULSE_ENCODER8_OVF_IRQ_CONFIG, PULSE_ENCODER8_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER9 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_9, pulse_encoder9_irq_handler, "pulse9", INT_SRC_TMRA_9_OVF, INT_SRC_TMRA_9_UDF, + PULSE_ENCODER9_OVF_IRQ_CONFIG, PULSE_ENCODER9_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER10 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_10, pulse_encoder10_irq_handler, "pulse10", INT_SRC_TMRA_10_OVF, INT_SRC_TMRA_10_UDF, + PULSE_ENCODER10_OVF_IRQ_CONFIG, PULSE_ENCODER10_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER11 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_11, pulse_encoder11_irq_handler, "pulse11", INT_SRC_TMRA_11_OVF, INT_SRC_TMRA_11_UDF, + PULSE_ENCODER11_OVF_IRQ_CONFIG, PULSE_ENCODER11_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER12 + HC32_PULSE_ENCODER_CONFIG(CM_TMRA_12, pulse_encoder12_irq_handler, "pulse12", INT_SRC_TMRA_12_OVF, INT_SRC_TMRA_12_UDF, + PULSE_ENCODER12_OVF_IRQ_CONFIG, PULSE_ENCODER12_UDF_IRQ_CONFIG), +#endif +}; + +static void hc32_pulse_encoder_irq_handler(struct hc32_pulse_encoder_config *pulse_encoder_config) +{ + if (SET == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF)) + { + pulse_encoder_config->ovf_udf_count++; + TMRA_ClearStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF); + } + if (SET == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UDF)) + { + pulse_encoder_config->ovf_udf_count--; + TMRA_ClearStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UDF); + } +} + +#ifdef BSP_USING_PULSE_ENCODER1 +static void pulse_encoder1_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER1_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER2 +static void pulse_encoder2_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER2_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER3 +static void pulse_encoder3_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER3_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER4 +static void pulse_encoder4_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER4_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER5 +static void pulse_encoder5_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER5_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER6 +static void pulse_encoder6_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER6_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER7 +static void pulse_encoder7_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER7_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER8 +static void pulse_encoder8_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER8_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER9 +static void pulse_encoder9_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER9_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER10 +static void pulse_encoder10_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER10_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER11 +static void pulse_encoder11_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER11_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER12 +static void pulse_encoder12_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER12_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static rt_uint16_t hc32_timer_get_unit_number(CM_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_timer_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_timer_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + FCG_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +extern rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx); + +rt_err_t hc32_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + stc_tmra_init_t stcTmraInit; + rt_err_t result; + + RT_ASSERT(pulse_encoder != RT_NULL); + pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder; + /* Enable Timer peripheral clock. */ + hc32_timer_clock_config(pulse_encoder_device->timer_periph, ENABLE); + /* pwm pin configuration */ + result = rt_hw_board_pulse_encoder_init(pulse_encoder_device->timer_periph); + if (RT_EOK == result) + { + TMRA_DeInit(pulse_encoder_device->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.u32PeriodValue = TIMER_AUTO_RELOAD_VALUE; + stcTmraInit.u8CountSrc = TMRA_CNT_SRC_HW; + stcTmraInit.hw_count.u16CountUpCond = TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING; + stcTmraInit.hw_count.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING; + TMRA_Init(pulse_encoder_device->timer_periph, &stcTmraInit); + LOG_D("%s init success", pulse_encoder_device->name); + + hc32_install_irq_handler(&pulse_encoder_device->ovf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE); + NVIC_EnableIRQ(pulse_encoder_device->ovf_irq_config.irq); + hc32_install_irq_handler(&pulse_encoder_device->udf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE); + NVIC_EnableIRQ(pulse_encoder_device->udf_irq_config.irq); + /* clear update flag */ + TMRA_ClearStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF)); + } + + return result; +} + +rt_err_t hc32_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + + pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder; + pulse_encoder_device->ovf_udf_count = 0; + TMRA_Stop(pulse_encoder_device->timer_periph); + TMRA_SetCountValue(pulse_encoder_device->timer_periph, 0); + TMRA_ClearStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF)); + TMRA_Start(pulse_encoder_device->timer_periph); + + return RT_EOK; +} + +rt_int32_t hc32_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + rt_int32_t period_val; + rt_int32_t count_val; + + pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder; + period_val = TMRA_GetCountValue(pulse_encoder_device->timer_periph); + count_val = period_val + pulse_encoder_device->ovf_udf_count * TIMER_AUTO_RELOAD_VALUE; + + return count_val; +} + +rt_err_t hc32_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) +{ + rt_err_t result = RT_EOK; + struct hc32_pulse_encoder_config *pulse_encoder_device; + pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder; + + switch (cmd) + { + case PULSE_ENCODER_CMD_ENABLE: + TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UDF), ENABLE); + TMRA_Start(pulse_encoder_device->timer_periph); + break; + case PULSE_ENCODER_CMD_DISABLE: + TMRA_Stop(pulse_encoder_device->timer_periph); + TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UDF), DISABLE); + break; + default: + result = -RT_ENOSYS; + break; + } + + return result; +} + +static const struct rt_pulse_encoder_ops pulse_encoder_ops = +{ + .init = hc32_pulse_encoder_init, + .get_count = hc32_pulse_encoder_get_count, + .clear_count = hc32_pulse_encoder_clear_count, + .control = hc32_pulse_encoder_control, +}; + +int hw_pulse_encoder_init(void) +{ + int i; + int result; + + result = RT_EOK; + for (i = 0; i < sizeof(pulse_encoder_obj) / sizeof(pulse_encoder_obj[0]); i++) + { + pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER; + pulse_encoder_obj[i].pulse_encoder.ops = &pulse_encoder_ops; + + if (rt_device_pulse_encoder_register(&pulse_encoder_obj[i].pulse_encoder, pulse_encoder_obj[i].name, pulse_encoder_obj[i].timer_periph) != RT_EOK) + { + LOG_E("%s register failed", pulse_encoder_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(hw_pulse_encoder_init); + +#endif + +#endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.h b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.h new file mode 100644 index 0000000000..e8267ab5d6 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_PULSE_ENCODER_H__ +#define __DRV_PULSE_ENCODER_H__ + +#include +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PULSE_ENCODER1 +#ifndef PULSE_ENCODER1_OVF_IRQ_CONFIG +#define PULSE_ENCODER1_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER1_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER1_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER1_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER1_UDF_IRQ_CONFIG +#define PULSE_ENCODER1_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER1_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER1_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER1_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER1 */ + +#ifdef BSP_USING_PULSE_ENCODER2 +#ifndef PULSE_ENCODER2_OVF_IRQ_CONFIG +#define PULSE_ENCODER2_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER2_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER2_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER2_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER2_UDF_IRQ_CONFIG +#define PULSE_ENCODER2_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER2_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER2_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER2_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER2 */ + +#ifdef BSP_USING_PULSE_ENCODER3 +#ifndef PULSE_ENCODER3_OVF_IRQ_CONFIG +#define PULSE_ENCODER3_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER3_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER3_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER3_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER3_UDF_IRQ_CONFIG +#define PULSE_ENCODER3_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER3_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER3_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER3_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER3 */ + +#ifdef BSP_USING_PULSE_ENCODER4 +#ifndef PULSE_ENCODER4_OVF_IRQ_CONFIG +#define PULSE_ENCODER4_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER4_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER4_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER4_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER4_UDF_IRQ_CONFIG +#define PULSE_ENCODER4_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER4_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER4_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER4_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER4 */ + +#ifdef BSP_USING_PULSE_ENCODER5 +#ifndef PULSE_ENCODER5_OVF_IRQ_CONFIG +#define PULSE_ENCODER5_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER5_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER5_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER5_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER5_UDF_IRQ_CONFIG +#define PULSE_ENCODER5_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER5_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER5_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER5_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER5 */ + +#ifdef BSP_USING_PULSE_ENCODER6 +#ifndef PULSE_ENCODER6_OVF_IRQ_CONFIG +#define PULSE_ENCODER6_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER6_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER6_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER6_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER6_UDF_IRQ_CONFIG +#define PULSE_ENCODER6_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER6_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER6_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER6_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER6 */ + +#ifdef BSP_USING_PULSE_ENCODER7 +#ifndef PULSE_ENCODER7_OVF_IRQ_CONFIG +#define PULSE_ENCODER7_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER7_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER7_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER7_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER7_UDF_IRQ_CONFIG +#define PULSE_ENCODER7_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER7_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER7_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER7_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER7 */ + +#ifdef BSP_USING_PULSE_ENCODER8 +#ifndef PULSE_ENCODER8_OVF_IRQ_CONFIG +#define PULSE_ENCODER8_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER8_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER8_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER8_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER8_UDF_IRQ_CONFIG +#define PULSE_ENCODER8_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER8_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER8_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER8_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER8 */ + +#ifdef BSP_USING_PULSE_ENCODER9 +#ifndef PULSE_ENCODER9_OVF_IRQ_CONFIG +#define PULSE_ENCODER9_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER9_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER9_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER9_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER9_UDF_IRQ_CONFIG +#define PULSE_ENCODER9_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER9_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER9_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER9_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER9 */ + +#ifdef BSP_USING_PULSE_ENCODER10 +#ifndef PULSE_ENCODER10_OVF_IRQ_CONFIG +#define PULSE_ENCODER10_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER10_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER10_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER10_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER10_UDF_IRQ_CONFIG +#define PULSE_ENCODER10_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER10_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER10_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER10_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER10 */ + +#ifdef BSP_USING_PULSE_ENCODER11 +#ifndef PULSE_ENCODER11_OVF_IRQ_CONFIG +#define PULSE_ENCODER11_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER11_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER11_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER11_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER11_UDF_IRQ_CONFIG +#define PULSE_ENCODER11_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER11_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER11_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER11_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER11 */ + +#ifdef BSP_USING_PULSE_ENCODER12 +#ifndef PULSE_ENCODER12_OVF_IRQ_CONFIG +#define PULSE_ENCODER12_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER12_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER12_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER12_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER12_UDF_IRQ_CONFIG +#define PULSE_ENCODER12_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER12_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER12_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER12_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER12 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_PULSE_ENCODER_H__ */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c new file mode 100644 index 0000000000..761b5f79f3 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c @@ -0,0 +1,525 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include + +#if defined(RT_USING_PWM) + +#if defined(BSP_USING_PWM1) || defined(BSP_USING_PWM2) || defined(BSP_USING_PWM3) || \ + defined(BSP_USING_PWM4) || defined(BSP_USING_PWM5) || defined(BSP_USING_PWM6) || \ + defined(BSP_USING_PWM7) || defined(BSP_USING_PWM8) || defined(BSP_USING_PWM9) || \ + defined(BSP_USING_PWM10) || defined(BSP_USING_PWM11) || defined(BSP_USING_PWM12) +#define PWM_MAX_PERIOD (65535U) +#define PWM_MIN_PERIOD (1U) +#define PWM_MIN_PULSE (1U) + +#define PWM_MAX_CHANNEL (TMRA_CH4) + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWCM_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + PWM9_INDEX, +#endif +#ifdef BSP_USING_PWM10 + PWM10_INDEX, +#endif +#ifdef BSP_USING_PWM11 + PWM11_INDEX, +#endif +#ifdef BSP_USING_PWM12 + PWM12_INDEX, +#endif +}; + +struct hc32_pwm_config +{ + struct rt_device_pwm pwm_device; + CM_TMRA_TypeDef *timer_periph; + rt_uint8_t channel; + char *name; +}; + +#ifndef HC32_PWM_CONFIG +#define HC32_PWM_CONFIG(periph, ch, label) \ + { \ + .timer_periph = periph, \ + .channel = ch, \ + .name = label \ + } +#endif /* HC32_PWM_CONFIG */ + +static struct hc32_pwm_config pwm_obj[] = +{ +#ifdef BSP_USING_PWM1 + HC32_PWM_CONFIG(CM_TMRA_1, 0, "pwm1"), +#endif +#ifdef BSP_USING_PWM2 + HC32_PWM_CONFIG(CM_TMRA_2, 0, "pwm2"), +#endif +#ifdef BSP_USING_PWM3 + HC32_PWM_CONFIG(CM_TMRA_3, 0, "pwm3"), +#endif +#ifdef BSP_USING_PWM4 + HC32_PWM_CONFIG(CM_TMRA_4, 0, "pwm4"), +#endif +#ifdef BSP_USING_PWM5 + HC32_PWM_CONFIG(CM_TMRA_5, 0, "pwm5"), +#endif +#ifdef BSP_USING_PWM6 + HC32_PWM_CONFIG(CM_TMRA_6, 0, "pwm6"), +#endif +#ifdef BSP_USING_PWM7 + HC32_PWM_CONFIG(CM_TMRA_7, 0, "pwm7"), +#endif +#ifdef BSP_USING_PWM8 + HC32_PWM_CONFIG(CM_TMRA_8, 0, "pwm8"), +#endif +#ifdef BSP_USING_PWM9 + HC32_PWM_CONFIG(CM_TMRA_9, 0, "pwm9"), +#endif +#ifdef BSP_USING_PWM10 + HC32_PWM_CONFIG(CM_TMRA_10, 0, "pwm10"), +#endif +#ifdef BSP_USING_PWM11 + HC32_PWM_CONFIG(CM_TMRA_11, 0, "pwm11"), +#endif +#ifdef BSP_USING_PWM12 + HC32_PWM_CONFIG(CM_TMRA_12, 0, "pwm12"), +#endif +}; + +static rt_uint16_t hc32_pwm_get_unit_number(CM_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_pwm_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_pwm_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + FCG_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +static rt_err_t hc32_pwm_enable(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + if (configuration->channel > PWM_MAX_CHANNEL) + { + return RT_EINVAL; + } + + if (!enable) + { + TMRA_PWM_OutputCmd(TMRAx, configuration->channel, DISABLE); + } + else + { + TMRA_PWM_OutputCmd(TMRAx, configuration->channel, ENABLE); + } + + return RT_EOK; +} + +static rt_err_t hc32_pwm_get(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration) +{ + stc_clock_freq_t stcClkFreq; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + rt_uint16_t div_val; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_pwm_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.u32Pclk1Freq; + } + else + { + clk_freq = stcClkFreq.u32Pclk0Freq; + } + + /* Convert nanosecond to frequency and duty cycle */ + div_val = 0x01 << (READ_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_CKDIV) >> TMRA_BCSTR_CKDIV_POS); + clk_freq /= 1000000UL; + configuration->period = (TMRA_GetPeriodValue(TMRAx) + 1) * div_val * 1000UL / clk_freq; + configuration->pulse = (TMRA_GetCompareValue(TMRAx, configuration->channel) + 1) * div_val * 1000UL / clk_freq; + + return RT_EOK; +} + +static rt_err_t hc32_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t clk_div; + stc_clock_freq_t stcClkFreq; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + rt_uint16_t div_val; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_pwm_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.u32Pclk1Freq; + } + else + { + clk_freq = stcClkFreq.u32Pclk0Freq; + } + /* Convert nanosecond to frequency and duty cycle */ + clk_freq /= 1000000UL; + period = (unsigned long long)configuration->period * clk_freq / 1000UL; + clk_div = period / PWM_MAX_PERIOD + 1; + + if (clk_div > 1024) + { + return RT_EINVAL; + } + else if (clk_div != 1) + { + for (div_val = 512; div_val > 1; div_val >>= 1) + { + if (clk_div > div_val) + { + clk_div = div_val << 1; + break; + } + } + } + period = period / clk_div; + TMRA_SetClockDiv(TMRAx, ((__CLZ(__RBIT(clk_div))) << TMRA_BCSTR_CKDIV_POS)); + + if (period < PWM_MIN_PERIOD) + { + period = PWM_MIN_PERIOD; + } + TMRA_SetPeriodValue(TMRAx, period - 1); + + pulse = (unsigned long long)configuration->pulse * clk_freq / clk_div / 1000UL; + if (pulse < PWM_MIN_PULSE) + { + pulse = PWM_MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + TMRA_SetCompareValue(TMRAx, configuration->channel, pulse - 1); + TMRA_SetCountValue(TMRAx, 0); + + return RT_EOK; +} + +static rt_err_t hc32_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + CM_TMRA_TypeDef *timer_periph = (CM_TMRA_TypeDef *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return hc32_pwm_enable(timer_periph, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return hc32_pwm_enable(timer_periph, configuration, RT_FALSE); + case PWM_CMD_SET: + return hc32_pwm_set(timer_periph, configuration); + case PWM_CMD_GET: + return hc32_pwm_get(timer_periph, configuration); + default: + return RT_EINVAL; + } +} + +extern rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx); + +static rt_err_t hc32_pwm_init(struct hc32_pwm_config *device) +{ + rt_err_t result = RT_EOK; + stc_tmra_init_t stcTmraInit; + stc_tmra_pwm_init_t stcPwmCfg; + + RT_ASSERT(device != RT_NULL); + + /* ENABLE Timer peripheral clock. */ + hc32_pwm_clock_config(device->timer_periph, ENABLE); + /* pwm pin configuration */ + result = rt_hw_board_pwm_init(device->timer_periph); + if (RT_EOK == result) + { + TMRA_DeInit(device->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.sw_count.u16ClockDiv = TMRA_CLK_DIV1; + stcTmraInit.u16CountReload = TMRA_CNT_RELOAD_ENABLE; + stcTmraInit.u32PeriodValue = 0xFFFF; + TMRA_Init(device->timer_periph, &stcTmraInit); + + /* Set the comparison reference value */ + TMRA_PWM_StructInit(&stcPwmCfg); + stcPwmCfg.u16StartPolarity = TMRA_PWM_HIGH; + stcPwmCfg.u16StopPolarity = TMRA_PWM_LOW; + stcPwmCfg.u16CompareMatchPolarity = TMRA_PWM_LOW; + stcPwmCfg.u16PeriodMatchPolarity = TMRA_PWM_HIGH; + + /* config pwm channel */ + if (0 != (device->channel & 0x01)) + { + TMRA_PWM_Init(device->timer_periph, TMRA_CH1, &stcPwmCfg); + TMRA_SetCompareValue(device->timer_periph, TMRA_CH1, 0x7FFF); + } + if (0 != (device->channel & 0x02)) + { + TMRA_PWM_Init(device->timer_periph, TMRA_CH2, &stcPwmCfg); + TMRA_SetCompareValue(device->timer_periph, TMRA_CH2, 0x7FFF); + } + if (0 != (device->channel & 0x04)) + { + TMRA_PWM_Init(device->timer_periph, TMRA_CH3, &stcPwmCfg); + TMRA_SetCompareValue(device->timer_periph, TMRA_CH3, 0x7FFF); + } + if (0 != (device->channel & 0x08)) + { + TMRA_PWM_Init(device->timer_periph, TMRA_CH4, &stcPwmCfg); + TMRA_SetCompareValue(device->timer_periph, TMRA_CH4, 0x7FFF); + } + /* start timer */ + TMRA_Start(device->timer_periph); + } + + return result; +} + +static void hc32_pwm_get_channel(void) +{ +#ifdef BSP_USING_PWM1_CH1 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM1_CH2 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM1_CH3 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM1_CH4 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM2_CH1 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM2_CH2 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM2_CH3 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM2_CH4 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM3_CH1 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM3_CH2 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM3_CH3 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM3_CH4 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWCM_CH1 + pwm_obj[PWCM_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWCM_CH2 + pwm_obj[PWCM_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWCM_CH3 + pwm_obj[PWCM_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWCM_CH4 + pwm_obj[PWCM_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM5_CH1 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM5_CH2 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM5_CH3 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM5_CH4 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM6_CH1 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM6_CH2 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM6_CH3 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM6_CH4 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM7_CH1 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM7_CH2 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM7_CH3 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM7_CH4 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM8_CH1 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM8_CH2 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM8_CH3 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM8_CH4 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM9_CH1 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM9_CH2 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM9_CH3 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM9_CH4 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM10_CH1 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM10_CH2 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM10_CH3 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM10_CH4 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM11_CH1 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM11_CH2 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM11_CH3 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM11_CH4 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM12_CH1 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM12_CH2 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM12_CH3 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM12_CH4 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 3); +#endif +} + +static struct rt_pwm_ops pwm_ops = +{ + .control = hc32_pwm_control +}; + +static int rt_hw_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + hc32_pwm_get_channel(); + for (i = 0; i < sizeof(pwm_obj) / sizeof(pwm_obj[0]); i++) + { + if (hc32_pwm_init(&pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", pwm_obj[i].name); + result = -RT_ERROR; + } + else + { + LOG_D("%s init success", pwm_obj[i].name); + /* register pwm device */ + if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].name, &pwm_ops, pwm_obj[i].timer_periph) == RT_EOK) + { + LOG_D("%s register success", pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif + +#endif /* RT_USING_PWM */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c new file mode 100644 index 0000000000..08d1ae27f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_RTC + +static struct rt_device rtc; + +static time_t hc32_rtc_get_time_stamp(void) +{ + stc_rtc_time_t stcRtcTime = {0}; + stc_rtc_date_t stcRtcDate = {0}; + struct tm tm_new = {0}; + + RTC_GetTime(RTC_DATA_FMT_DEC, &stcRtcTime); + RTC_GetDate(RTC_DATA_FMT_DEC, &stcRtcDate); + + tm_new.tm_sec = stcRtcTime.u8Second; + tm_new.tm_min = stcRtcTime.u8Minute; + tm_new.tm_hour = stcRtcTime.u8Hour; + tm_new.tm_mday = stcRtcDate.u8Day; + tm_new.tm_mon = stcRtcDate.u8Month - 1; + tm_new.tm_year = stcRtcDate.u8Year + 100; + tm_new.tm_wday = stcRtcDate.u8Weekday; + + LOG_D("get rtc time."); + return timegm(&tm_new); +} + +static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) +{ + stc_rtc_time_t stcRtcTime = {0}; + stc_rtc_date_t stcRtcDate = {0}; + struct tm *p_tm; + + p_tm = gmtime(&time_stamp); + if (p_tm->tm_year < 100) + { + return -RT_ERROR; + } + + stcRtcTime.u8Second = p_tm->tm_sec ; + stcRtcTime.u8Minute = p_tm->tm_min ; + stcRtcTime.u8Hour = p_tm->tm_hour; + stcRtcDate.u8Day = p_tm->tm_mday; + stcRtcDate.u8Month = p_tm->tm_mon + 1 ; + stcRtcDate.u8Year = p_tm->tm_year - 100; + stcRtcDate.u8Weekday = p_tm->tm_wday; + + if (LL_OK != RTC_SetTime(RTC_DATA_FMT_DEC, &stcRtcTime)) + { + return -RT_ERROR; + } + if (LL_OK != RTC_SetDate(RTC_DATA_FMT_DEC, &stcRtcDate)) + { + return -RT_ERROR; + } + + LOG_D("set rtc time."); + return RT_EOK; +} + +static rt_err_t hc32_rtc_init(struct rt_device *dev) +{ + stc_rtc_init_t stcRtcInit; + +#ifdef BSP_RTC_USING_XTAL32 + stc_clk_xtal32_init_t stcXtal32Init; + + /* Xtal32 config */ + stcXtal32Init.u8Xtal32State = CLK_XTAL32_ON; + stcXtal32Init.u8Xtal32Drv = CLK_XTAL32DRV_HIGH; + stcXtal32Init.u8Xtal32NF = CLK_XTAL32NF_PART; + (void)CLK_Xtal32Init(&stcXtal32Init); + /* Waiting for XTAL32 stabilization */ + rt_thread_delay(1000); +#endif + + /* Reset RTC counter */ + if (LL_ERR_TIMEOUT == RTC_DeInit()) + { + return -RT_ERROR; + } + else + { + /* Configure structure initialization */ + (void)RTC_StructInit(&stcRtcInit); + /* Configuration RTC structure */ +#ifdef BSP_RTC_USING_XTAL32 + stcRtcInit.u8ClockSrc = RTC_CLK_SRC_XTAL32; +#else + stcRtcInit.u8ClockSrc = RTC_CLK_SRC_LRC; +#endif + stcRtcInit.u8HourFormat = RTC_HOUR_FMT_24H; + (void)RTC_Init(&stcRtcInit); + /* Startup RTC count */ + RTC_Cmd(ENABLE); + } + + return RT_EOK; +} + +static rt_err_t hc32_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(dev != RT_NULL); + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = hc32_rtc_get_time_stamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (hc32_rtc_set_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + break; + default: + return RT_EINVAL; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + hc32_rtc_control +}; +#endif + +//static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) +//{ +// RT_ASSERT(device != RT_NULL); + +// if (hc32_rtc_init(device) != RT_EOK) +// { +// return -RT_ERROR; +// } +//#ifdef RT_USING_DEVICE_OPS +// device->ops = &rtc_ops; +//#else +// device->init = RT_NULL; +// device->open = RT_NULL; +// device->close = RT_NULL; +// device->read = RT_NULL; +// device->write = RT_NULL; +// device->control = hc32_rtc_control; +//#endif +// device->type = RT_Device_Class_RTC; +// device->rx_indicate = RT_NULL; +// device->tx_complete = RT_NULL; +// device->user_data = RT_NULL; + +// /* register a character device */ +// return rt_device_register(device, name, flag); +//} + +int rt_hw_rtc_init(void) +{ +// rt_err_t result; + +// result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); +// if (result != RT_EOK) +// { +// LOG_E("rtc register err code: %d", result); +// return result; +// } +// LOG_D("rtc init success"); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..f73e4c8b8e --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "drv_soft_i2c.h" +#include "board_config.h" + +#if defined(RT_USING_I2C) + +#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || \ + defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +static const struct hc32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C5 + I2C5_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C6 + I2C6_BUS_CONFIG, +#endif +}; + +static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * This function initializes the i2c pin. + * + * @param Hc32 i2c dirver class. + */ +static void hc32_i2c_gpio_init(struct hc32_i2c *i2c) +{ + struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)i2c->ops.data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD); + rt_pin_write(cfg->scl_pin, PIN_HIGH); + rt_pin_write(cfg->sda_pin, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param Hc32 config class. + * @param The sda pin state. + */ +static void hc32_set_sda(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data; + + if (state) + { + rt_pin_write(cfg->sda_pin, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda_pin, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param Hc32 config class. + * @param The scl pin state. + */ +static void hc32_set_scl(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data; + + if (state) + { + rt_pin_write(cfg->scl_pin, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl_pin, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t hc32_get_sda(void *data) +{ + struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data; + return rt_pin_read(cfg->sda_pin); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t hc32_get_scl(void *data) +{ + struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data; + return rt_pin_read(cfg->scl_pin); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void hc32_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops hc32_bit_ops_default = +{ + .data = RT_NULL, + .set_sda = hc32_set_sda, + .set_scl = hc32_set_scl, + .get_sda = hc32_get_sda, + .get_scl = hc32_get_scl, + .udelay = hc32_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/** + * if i2c is locked, this function will unlock it + * + * @param hc32 config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t hc32_i2c_bus_unlock(const struct hc32_soft_i2c_config *cfg) +{ + rt_uint32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl_pin, PIN_HIGH); + hc32_udelay(100); + rt_pin_write(cfg->scl_pin, PIN_LOW); + hc32_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int hc32_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct hc32_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = hc32_bit_ops_default; + i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; + i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; + hc32_i2c_gpio_init(&i2c_obj[i]); + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + hc32_i2c_bus_unlock(&soft_i2c_config[i]); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(hc32_hw_i2c_init); + +#endif + +#endif /* RT_USING_I2C */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..1e2e731c62 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_soft_i2c_config +{ + rt_uint16_t scl_pin; + rt_uint16_t sda_pin; + const char *bus_name; +}; + +struct hc32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c_bus; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C1_SCL_PIN, \ + .sda_pin = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif + +#ifdef BSP_USING_I2C5 +#define I2C5_BUS_CONFIG \ + { \ + .scl = BSP_I2C5_SCL_PIN, \ + .sda = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5", \ + } +#endif + +#ifdef BSP_USING_I2C6 +#define I2C6_BUS_CONFIG \ + { \ + .scl = BSP_I2C6_SCL_PIN, \ + .sda = BSP_I2C6_SDA_PIN, \ + .bus_name = "i2c6", \ + } +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.c b/bsp/hc32/libraries/hc32_drivers/drv_spi.c new file mode 100644 index 0000000000..d7680476b7 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.c @@ -0,0 +1,877 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +#if defined(RT_USING_SPI) + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || \ + defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) + +#include "drv_spi.h" +#include "board_config.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx); + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#if defined(BSP_USING_SPI1) + static void spi1_rx_dma_irq_handle(void); + static void spi1_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI1 */ + +#if defined(BSP_USING_SPI2) + static void spi2_rx_dma_irq_handle(void); + static void spi2_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI2 */ + +#if defined(BSP_USING_SPI3) + static void spi3_rx_dma_irq_handle(void); + static void spi3_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI3 */ + +#if defined(BSP_USING_SPI4) + static void spi4_rx_dma_irq_handle(void); + static void spi4_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI4 */ + +#if defined(BSP_USING_SPI5) + static void spi5_rx_dma_irq_handle(void); + static void spi5_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI5 */ + +#if defined(BSP_USING_SPI6) + static void spi6_rx_dma_irq_handle(void); + static void spi6_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI6 */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +#ifdef BSP_USING_SPI2 + SPI2_INDEX, +#endif +#ifdef BSP_USING_SPI3 + SPI3_INDEX, +#endif +#ifdef BSP_USING_SPI4 + SPI4_INDEX, +#endif +#ifdef BSP_USING_SPI5 + SPI5_INDEX, +#endif +#ifdef BSP_USING_SPI6 + SPI6_INDEX, +#endif +}; + +static struct hc32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI4 + SPI4_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI5 + SPI5_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI6 + SPI6_BUS_CONFIG, +#endif +}; + +static struct hc32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + stc_spi_init_t stcSpiInit; + stc_clock_freq_t stcClkFreq; + CM_SPI_TypeDef *spi_instance = spi_drv->config->Instance; + + /* Enable spi clock */ + FCG_Fcg1PeriphClockCmd(spi_drv->config->clock, ENABLE); + /* Init spi struct as default value */ + SPI_StructInit(&stcSpiInit); + + /* Slave or master mode */ + if (cfg->mode & RT_SPI_SLAVE) + { + stcSpiInit.u32MasterSlave = SPI_SLAVE; + } + else + { + stcSpiInit.u32MasterSlave = SPI_MASTER; + } + /* SI/SO pin shared */ + if (cfg->mode & RT_SPI_3WIRE) + { + return RT_EINVAL; + } + else + { + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; + } + /* clock phase & polarity */ + if (RT_SPI_MODE_3 == (cfg->mode & RT_SPI_MODE_3)) + { + stcSpiInit.u32SpiMode = SPI_MD_3; + } + else if (RT_SPI_MODE_2 == (cfg->mode & RT_SPI_MODE_3)) + { + stcSpiInit.u32SpiMode = SPI_MD_2; + } + else if (RT_SPI_MODE_1 == (cfg->mode & RT_SPI_MODE_3)) + { + stcSpiInit.u32SpiMode = SPI_MD_1; + } + else + { + stcSpiInit.u32SpiMode = SPI_MD_0; + } + /* No chipselect */ + if (cfg->mode & RT_SPI_NO_CS) + { + stcSpiInit.u32WireMode = SPI_4_WIRE; + } + else + { + stcSpiInit.u32WireMode = SPI_3_WIRE; + } + /* LSB or MSB */ + if (cfg->mode & RT_SPI_MSB) + { + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; + } + else + { + stcSpiInit.u32FirstBit = SPI_FIRST_LSB; + } + /* config data width 8,16,32 */ + if (8 == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; + } + else if (16 == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_16BIT; + } + else if (32 == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_32BIT; + } + else + { + return RT_EIO; + } + /* Get BUS clock */ + CLK_GetClockFreq(&stcClkFreq); + if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 2) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV2; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 4) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV4; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 8) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 16) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV16; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 32) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV32; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 64) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; + } + else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 128) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV128; + } + else + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV256; + } + if ((cfg->mode & RT_SPI_SLAVE) && (stcSpiInit.u32BaudRatePrescaler < SPI_BR_CLK_DIV8)) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + } + LOG_D("sys freq: %d, SPI freq: %d, BaudRatePrescaler: %d", stcClkFreq.u32HclkFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler); + + /* spi port init */ + rt_hw_spi_board_init(spi_instance); + if (LL_OK != SPI_Init(spi_instance, &stcSpiInit)) + { + return RT_EIO; + } + + /* DMA configuration */ + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + struct dma_config *spi_dma; + stc_dma_init_t stcDmaInit; + + /* Get spi dma_rx */ + spi_dma = spi_drv->config->dma_rx; + /* Enable Dma clock */ + FCG_Fcg0PeriphClockCmd(spi_dma->clock, ENABLE); + AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event); + /* Config Dma */ + DMA_StructInit(&stcDmaInit); + stcDmaInit.u32IntEn = DMA_INT_ENABLE; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCount = 0; + stcDmaInit.u32DestAddr = 0; + stcDmaInit.u32SrcAddr = (uint32_t)(&spi_instance->DR); + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; + if (8 == cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + } + else if (16 == cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + } + else + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT; + } + /* Init Dma */ + if (LL_OK != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit)) + { + return RT_EIO; + } + NVIC_EnableIRQ(spi_dma->irq_config.irq_num); + /* Enable Dma */ + DMA_Cmd(spi_dma->Instance, ENABLE); + } + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + struct dma_config *spi_dma; + stc_dma_init_t stcDmaInit; + + /* Get spi dma_tx */ + spi_dma = spi_drv->config->dma_tx; + FCG_Fcg0PeriphClockCmd(spi_dma->clock, ENABLE); + AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event); + /* Config Dma */ + DMA_StructInit(&stcDmaInit); + stcDmaInit.u32IntEn = DMA_INT_ENABLE; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCount = 0; + stcDmaInit.u32DestAddr = (uint32_t)(&spi_instance->DR);; + stcDmaInit.u32SrcAddr = 0; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; + if (8 == cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + } + else if (16 == cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + } + else + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT; + } + /* Init Dma */ + if (LL_OK != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit)) + { + return RT_EIO; + } + NVIC_EnableIRQ(spi_dma->irq_config.irq_num); + /* Enable Dma */ + DMA_Cmd(spi_dma->Instance, ENABLE); + } + + LOG_D("%s init done", spi_drv->config->bus_name); + return RT_EOK; +} + +static rt_err_t hc32_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + spi_drv->cfg = configuration; + + return hc32_spi_init(spi_drv, configuration); +} + +static int32_t hc32_spi_dma_trans(struct hc32_spi_config *spi_config, const uint8_t *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + if ((spi_config == RT_NULL) || (pvTxBuf == RT_NULL) || (pvRxBuf == RT_NULL)) + { + return LL_ERR; + } + + SPI_Cmd(spi_config->Instance, DISABLE); + if (RT_NULL == pvTxBuf) + { + DMA_SetSrcAddr(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, (uint32_t)pvTxBuf); + DMA_SetTransCount(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, u32Length); + DMA_ChCmd(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, ENABLE); + } + if (RT_NULL == pvRxBuf) + { + DMA_SetDestAddr(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, (uint32_t)pvRxBuf); + DMA_SetTransCount(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, u32Length); + DMA_ChCmd(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, ENABLE); + } + SPI_Cmd(spi_config->Instance, ENABLE); + + return LL_OK; +} + +static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) +{ + /* Check if the SPI is already enabled */ + if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SPI_Cmd(SPIx, ENABLE); + } +} + +static rt_uint32_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + int32_t state; + rt_size_t message_length, already_send_length; + rt_uint16_t send_length; + rt_uint8_t *recv_buf; + const rt_uint8_t *send_buf; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + CM_SPI_TypeDef *spi_instance = spi_drv->config->Instance; + struct hc32_hw_spi_cs *cs = device->parent.user_data; + + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS)) + { + if (device->config.mode & RT_SPI_CS_HIGH) + { + GPIO_SetPins(cs->port, cs->pin); + } + else + { + GPIO_ResetPins(cs->port, cs->pin); + } + } + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", spi_drv->config->bus_name, + (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); + + message_length = message->length; + recv_buf = message->recv_buf; + send_buf = message->send_buf; + while (message_length) + { + if (message_length > 65535) + { + send_length = 65535; + message_length = message_length - 65535; + } + else + { + send_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = message->length - send_length - message_length; + send_buf = (rt_uint8_t *)message->send_buf + already_send_length; + recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length; + if (message->send_buf && message->recv_buf) + { + if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX)) + { + state = hc32_spi_dma_trans(spi_drv->config, send_buf, recv_buf, send_length); + } + else + { + hc32_spi_enable(spi_instance); + state = SPI_TransReceive(spi_instance, send_buf, recv_buf, send_length, 1000); + } + } + else if (message->send_buf) + { + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + /* Maybe need to switch to send only mode */ + state = hc32_spi_dma_trans(spi_drv->config, send_buf, RT_NULL, send_length); + } + else + { + hc32_spi_enable(spi_instance); + state = SPI_Trans(spi_instance, send_buf, send_length, 1000); + } + } + else + { + rt_memset((uint8_t *)recv_buf, 0xFF, send_length); + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + state = hc32_spi_dma_trans(spi_drv->config, recv_buf, recv_buf, send_length); + } + else + { + hc32_spi_enable(spi_instance); + state = SPI_Receive(spi_instance, recv_buf, send_length, 1000); + } + } + if (state != LL_OK) + { + LOG_I("spi transfer error : %d", state); + message->length = 0; + } + /* Wait for the spi transfer complete */ + while (RESET != SPI_GetStatus(spi_instance, SPI_FLAG_IDLE)); + } + /* clear error flag */ + SPI_ClearStatus(spi_instance, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL); + + if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS)) + { + if (device->config.mode & RT_SPI_CS_HIGH) + { + GPIO_ResetPins(cs->port, cs->pin); + } + else + { + GPIO_SetPins(cs->port, cs->pin); + } + } + + return message->length; +} + +static const struct rt_spi_ops hc32_spi_ops = +{ + .configure = hc32_spi_configure, + .xfer = hc32_spi_xfer, +}; + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint8_t cs_gpio_port, uint16_t cs_gpio_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct hc32_hw_spi_cs *cs_pin; + stc_gpio_init_t stcGpioInit; + + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PullUp = PIN_PU_ON; + GPIO_Init(cs_gpio_port, cs_gpio_pin, &stcGpioInit); + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct hc32_hw_spi_cs *)rt_malloc(sizeof(struct hc32_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->port = cs_gpio_port; + cs_pin->pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + return result; +} + +/** + * @brief Clear DMA transfer complete flag. + * @param dma specific dam witch spi used. + * @retval None + */ +static void hc32_dma_irq_handle(struct dma_config *dma) +{ + DMA_ClearTransCompleteStatus(dma->Instance, (1U << dma->channel)); +} + +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi1_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi1_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi2_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi2_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi3_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi3_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi4_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi4_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi5_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi5_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi6_rx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_rx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi6_tx_dma_irq_handle(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_tx); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +/** + * @brief This function gets dma witch spi used infomation include unit, + * channel, interrupt etc. + * @param None + * @retval None + */ +static void hc32_get_dma_info(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi1_dma_rx.irq_callback = spi1_rx_dma_irq_handle; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi1_dma_tx.irq_callback = spi1_tx_dma_irq_handle; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi2_dma_rx.irq_callback = spi2_rx_dma_irq_handle; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi2_dma_tx.irq_callback = spi2_tx_dma_irq_handle; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif + +#ifdef BSP_SPI3_RX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + spi3_dma_rx.irq_callback = spi3_rx_dma_irq_handle; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; +#endif +#ifdef BSP_SPI3_TX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + spi3_dma_tx.irq_callback = spi3_tx_dma_irq_handle; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; +#endif + +#ifdef BSP_SPI4_RX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + spi4_dma_rx.irq_callback = spi4_rx_dma_irq_handle; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; +#endif +#ifdef BSP_SPI4_TX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + spi4_dma_tx.irq_callback = spi4_tx_dma_irq_handle; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; +#endif + +#ifdef BSP_SPI5_RX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + spi5_dma_rx.irq_callback = spi5_rx_dma_irq_handle; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; +#endif +#ifdef BSP_SPI5_TX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + spi5_dma_tx.irq_callback = spi5_tx_dma_irq_handle; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; +#endif + +#ifdef BSP_SPI6_RX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + spi6_dma_rx.irq_callback = spi6_rx_dma_irq_handle; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; +#endif +#ifdef BSP_SPI6_TX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + spi6_dma_tx.irq_callback = spi6_tx_dma_irq_handle; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; +#endif +} + +static int hc32_hw_spi_bus_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; + + if (spi_bus_obj[i].spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + /* Configure the DMA handler */ + hc32_install_irq_handler(&spi_config[i].dma_rx->irq_config, spi_config[i].dma_rx->irq_callback, RT_FALSE); + } + if (spi_bus_obj[i].spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + /* Configure the DMA handler */ + hc32_install_irq_handler(&spi_config[i].dma_tx->irq_config, spi_config[i].dma_tx->irq_callback, RT_FALSE); + } + + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &hc32_spi_ops); + LOG_D("%s bus init done", spi_config[i].bus_name); + } + + return result; +} + +int hc32_hw_spi_init(void) +{ + hc32_get_dma_info(); + return hc32_hw_spi_bus_init(); +} + +INIT_BOARD_EXPORT(hc32_hw_spi_init); + +#endif + +#endif /* BSP_USING_SPI */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.h b/bsp/hc32/libraries/hc32_drivers/drv_spi.h new file mode 100644 index 0000000000..7fc1c00bb1 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" +#include "drv_dma.h" +#include "drv_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +struct hc32_hw_spi_cs +{ + rt_uint8_t port; + rt_uint16_t pin; +}; + +struct hc32_spi_config +{ + CM_SPI_TypeDef *Instance; + char *bus_name; + rt_uint32_t clock; + // struct hc32_irq_config irq_config; + struct dma_config *dma_rx; + struct dma_config *dma_tx; +}; + +struct hc32_spi +{ + struct hc32_spi_config *config; + struct rt_spi_configuration *cfg; + struct rt_spi_bus spi_bus; + rt_uint8_t spi_dma_flag; +}; + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint8_t cs_gpio_port, uint16_t cs_gpio_pin); + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SPI_H__ */ + diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.c b/bsp/hc32/libraries/hc32_drivers/drv_usart.c new file mode 100644 index 0000000000..a313c94455 --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.c @@ -0,0 +1,1345 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + + +#ifdef RT_USING_SERIAL + +#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \ + defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \ + defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \ + defined(BSP_USING_UART10) + +#include "drv_usart.h" +#include "board_config.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DMA_CH_REG(reg_base, ch) \ + (*(uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +#define DMA_TRANS_CNT(unit, ch) \ + (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) + +#define USART_TCI_ENABLE(unit) \ + SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT) + + +#define UART_BAUDRATE_ERR_MAX (0.025F) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx); + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#ifdef RT_SERIAL_USING_DMA + static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif +#ifdef BSP_USING_UART9 + UART9_INDEX, +#endif +#ifdef BSP_USING_UART10 + UART10_INDEX, +#endif +}; + +static struct hc32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif +#ifdef BSP_USING_UART6 + UART6_CONFIG, +#endif +#ifdef BSP_USING_UART7 + UART7_CONFIG, +#endif +#ifdef BSP_USING_UART8 + UART8_CONFIG, +#endif +#ifdef BSP_USING_UART9 + UART9_CONFIG, +#endif +#ifdef BSP_USING_UART10 + UART10_CONFIG, +#endif +}; + +static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hc32_uart *uart; + stc_usart_uart_init_t uart_init; + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + USART_UART_StructInit(&uart_init); + uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + uart_init.u32Baudrate = cfg->baud_rate; + uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK; + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ + (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) + { + uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + uart_init.u32DataWidth = USART_DATA_WIDTH_8BIT; + break; + case DATA_BITS_9: + uart_init.u32DataWidth = USART_DATA_WIDTH_9BIT; + break; + default: + uart_init.u32DataWidth = USART_DATA_WIDTH_8BIT; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_init.u32StopBit = USART_STOPBIT_1BIT; + break; + case STOP_BITS_2: + uart_init.u32StopBit = USART_STOPBIT_2BIT; + break; + default: + uart_init.u32StopBit = USART_STOPBIT_1BIT; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart_init.u32Parity = USART_PARITY_NONE; + break; + case PARITY_EVEN: + uart_init.u32Parity = USART_PARITY_EVEN; + break; + case PARITY_ODD: + uart_init.u32Parity = USART_PARITY_ODD; + break; + default: + uart_init.u32Parity = USART_PARITY_NONE; + break; + } + + if (BIT_ORDER_LSB == cfg->bit_order) + { + uart_init.u32FirstBit = USART_FIRST_BIT_LSB; + } + else + { + uart_init.u32FirstBit = USART_FIRST_BIT_MSB; + } + + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_RTS_CTS; + break; + default: + uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_NONE; + break; + } + +#ifdef RT_SERIAL_USING_DMA + uart->dma_rx_last_index = 0; +#endif + /* Enable USART clock */ + FCG_Fcg3PeriphClockCmd(uart->config->clock, ENABLE); + if (RT_EOK != rt_hw_board_uart_init(uart->config->Instance)) + { + return -RT_ERROR; + } + /* Configure UART */ + uint32_t u32Div; + float32_t f32Error; + int32_t i32Ret = LL_ERR; + USART_DeInit(uart->config->Instance); + USART_UART_Init(uart->config->Instance, &uart_init, NULL); + for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) + { + USART_SetClockDiv(uart->config->Instance, u32Div); + if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) && + ((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX))) + { + i32Ret = LL_OK; + break; + } + } + if (i32Ret != LL_OK) + { + return -RT_ERROR; + } + + /* Enable error interrupt */ + NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); + USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX, ENABLE); + + return RT_EOK; +} + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(RT_NULL != serial); + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->config->Instance); + + switch (cmd) + { + /* Disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); + USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE); + INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); + } + else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) + { + NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); + USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); + INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); + } +#ifdef RT_SERIAL_USING_DMA + else if (RT_DEVICE_FLAG_DMA_RX == ctrl_arg) + { + NVIC_DisableIRQ(uart->config->dma_rx->irq_config.irq_num); + } + else if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg) + { + NVIC_DisableIRQ(uart->config->dma_tx->irq_config.irq_num); + } +#endif + break; + /* Enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE); + hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE); + } + else + { + USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, ENABLE); + hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE); + } + break; +#ifdef RT_SERIAL_USING_DMA + case RT_DEVICE_CTRL_CONFIG: + hc32_dma_config(serial, ctrl_arg); + break; +#endif + case RT_DEVICE_CTRL_CLOSE: + USART_DeInit(uart->config->Instance); + break; + } + + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->config->Instance); + + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + if (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET) + { + return -1; + } + } + else + { + /* Polling mode. */ + while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET); + } + USART_WriteData(uart->config->Instance, c); + + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->config->Instance); + if (SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) + { + ch = (rt_uint8_t)USART_ReadData(uart->config->Instance); + } + + return ch; +} + +static rt_size_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ +#ifdef RT_SERIAL_USING_DMA + struct hc32_uart *uart; + struct dma_config *uart_dma; + + RT_ASSERT(RT_NULL != serial); + RT_ASSERT(RT_NULL != buf); + + if (size == 0) + { + return 0; + } + + uart = rt_container_of(serial, struct hc32_uart, serial); + if (RT_SERIAL_DMA_TX == direction) + { + uart_dma = uart->config->dma_tx; + if (RESET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT)) + { + RT_ASSERT(0); + } + DMA_SetSrcAddr(uart_dma->Instance, uart_dma->channel, (uint32_t)buf); + DMA_SetTransCount(uart_dma->Instance, uart_dma->channel, size); + DMA_ChCmd(uart_dma->Instance, uart_dma->channel, ENABLE); + USART_FuncCmd(uart->config->Instance, USART_TX, ENABLE); + USART_FuncCmd(uart->config->Instance, USART_INT_TX_CPLT, ENABLE); + return size; + } +#endif + + return 0; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_tx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->config->Instance); + + if (SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR))) + { + USART_ReadData(uart->config->Instance); + } + USART_ClearStatus(uart->config->Instance, (USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR | USART_FLAG_OVERRUN)); +} + +#ifdef RT_SERIAL_USING_DMA +static void hc32_uart_rx_timeout(struct rt_serial_device *serial) +{ + struct hc32_uart *uart; + uint32_t cmp_val; + CM_TMR0_TypeDef *TMR0_Instance; + uint8_t ch; + uint32_t timeout_bits; + stc_tmr0_init_t stcTmr0Init; + + RT_ASSERT(RT_NULL != serial); + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->config->Instance); + + TMR0_Instance = uart->config->rx_timeout->TMR0_Instance; + ch = uart->config->rx_timeout->channel; + timeout_bits = uart->config->rx_timeout->timeout_bits; + + if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_A == ch); + } + else if ((CM_USART2 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_B == ch); + } + FCG_Fcg2PeriphClockCmd(uart->config->rx_timeout->clock, ENABLE); + + /* TIMER0 basetimer function initialize */ + TMR0_DeInit(TMR0_Instance); + TMR0_SetCountValue(TMR0_Instance, ch, 0U); + TMR0_StructInit(&stcTmr0Init); + stcTmr0Init.u32ClockDiv = TMR0_CLK_DIV1; + stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32; + if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv) + { + cmp_val = (timeout_bits - 4UL); + } + else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv) + { + cmp_val = (timeout_bits / 2UL - 2UL); + } + else + { + cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL); + } + DDL_ASSERT(cmp_val <= 0xFFFFUL); + stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val); + TMR0_Init(TMR0_Instance, ch, &stcTmr0Init); + TMR0_HWStartCondCmd(TMR0_Instance, ch, ENABLE); + TMR0_HWClearCondCmd(TMR0_Instance, ch, ENABLE); + /* Clear compare flag */ + TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << ch)); + + NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num); + USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); + USART_FuncCmd(uart->config->Instance, (USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT), ENABLE); +} + +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct hc32_uart *uart; + stc_dma_init_t dma_init; + struct dma_config *uart_dma; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->config->Instance); + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + stc_dma_llp_init_t llp_init; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance); + RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance); + + uart_dma = uart->config->dma_rx; + /* Initialization uart rx timeout for DMA */ + hc32_uart_rx_timeout(serial); + /* Enable DMA clock */ + FCG_Fcg0PeriphClockCmd(uart_dma->clock, ENABLE); + DMA_ChCmd(uart_dma->Instance, uart_dma->channel, DISABLE); + + /* Initialize DMA */ + DMA_StructInit(&dma_init); + dma_init.u32IntEn = DMA_INT_ENABLE; + dma_init.u32SrcAddr = ((uint32_t)(&uart->config->Instance->DR) + 2UL); + dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer; + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = serial->config.bufsz; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC; + DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); + + /* Initialize LLP */ + static stc_dma_llp_descriptor_t llp_desc; + llp_init.u32State = DMA_LLP_ENABLE; + llp_init.u32Mode = DMA_LLP_WAIT; + llp_init.u32Addr = (uint32_t)&llp_desc; + DMA_LlpInit(uart_dma->Instance, uart_dma->channel, &llp_init); + + /* Configure LLP descriptor */ + llp_desc.SARx = dma_init.u32SrcAddr; + llp_desc.DARx = dma_init.u32DestAddr; + llp_desc.DTCTLx = (dma_init.u32TransCount << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); + llp_desc.LLPx = (uint32_t)&llp_desc; + llp_desc.CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \ + llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); + + /* Enable DMA interrupt */ + NVIC_EnableIRQ(uart->config->dma_rx->irq_config.irq_num); + /* Enable DMA module */ + DMA_Cmd(uart_dma->Instance, ENABLE); + AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event); + DMA_ChCmd(uart_dma->Instance, uart_dma->channel, ENABLE); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + RT_ASSERT(RT_NULL != uart->config->dma_tx->Instance); + + uart_dma = uart->config->dma_tx; + /* Enable DMA clock */ + FCG_Fcg0PeriphClockCmd(uart_dma->clock, ENABLE); + DMA_ChCmd(uart_dma->Instance, uart_dma->channel, DISABLE); + + /* Initialize DMA */ + DMA_StructInit(&dma_init); + dma_init.u32IntEn = DMA_INT_DISABLE; + dma_init.u32SrcAddr = 0UL; + dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->DR); + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = 0UL; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC; + dma_init.u32DestAddrInc = DMA_DEST_ADDR_FIX; + DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); + + /* Enable DMA module */ + DMA_Cmd(uart_dma->Instance, ENABLE); + AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event); + USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE); + NVIC_EnableIRQ(uart->config->tc_irq->irq_config.irq_num); + } +} + +static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) +{ + struct rt_serial_device *serial; + rt_size_t recv_len; + rt_base_t level; + + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->config->Instance); + + serial = &uart->serial; + level = rt_hw_interrupt_disable(); + recv_len = serial->config.bufsz - uart->dma_rx_last_index; + uart->dma_rx_last_index = 0UL; + rt_hw_interrupt_enable(level); + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) +{ + rt_base_t level; + rt_size_t cnt; + rt_size_t recv_len; + rt_size_t recv_total_index; + + cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); + recv_total_index = uart->serial.config.bufsz - cnt; + if (0UL != recv_total_index) + { + level = rt_hw_interrupt_disable(); + recv_len = recv_total_index - uart->dma_rx_last_index; + uart->dma_rx_last_index = recv_total_index; + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + } + TMR0_Stop(uart->config->rx_timeout->TMR0_Instance, uart->config->rx_timeout->channel); + USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); +} + +static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); + + DMA_ClearTransCompleteStatus(uart->config->dma_tx->Instance, (DMA_FLAG_TC_CH0 | DMA_FLAG_BTC_CH0) << uart->config->dma_tx->channel); + USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE); + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_DMA_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); + } +} +#endif + +#if defined(BSP_USING_UART1) +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +static void hc32_uart1_rxto_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +static void hc32_uart1_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART1_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +static void hc32_uart2_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart2_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart2_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_TX_USING_DMA) +static void hc32_uart2_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART2_TX_USING_DMA */ + +#if defined(BSP_UART2_RX_USING_DMA) +static void hc32_uart2_rxto_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart2_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); + +} +#endif /* BSP_UART2_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +static void hc32_uart3_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +static void hc32_uart4_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart4_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart4_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +static void hc32_uart5_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart5_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart5_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +static void hc32_uart6_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart6_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart6_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART6_TX_USING_DMA) +static void hc32_uart6_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART6_TX_USING_DMA */ + +#if defined(BSP_UART6_RX_USING_DMA) +static void hc32_uart6_rxto_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart6_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART6_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +static void hc32_uart7_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart7_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart7_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART7_TX_USING_DMA) +static void hc32_uart7_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART7_TX_USING_DMA */ + +#if defined(BSP_UART7_RX_USING_DMA) +static void hc32_uart7_rxto_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart7_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART7_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +static void hc32_uart8_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart8_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart8_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +static void hc32_uart9_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart9_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart9_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +static void hc32_uart10_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart10_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart10_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART10 */ + +/** + * @brief This function gets dma witch uart used infomation include unit, + * channel, interrupt etc. + * @param None + * @retval None + */ +static void hc32_uart_get_dma_info(void) +{ +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; + uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; + uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; + uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; + static struct hc32_uart_irq_config uart1_tc_irq = UART1_TX_CPLT_CONFIG; + uart1_tc_irq.irq_callback = hc32_uart1_tc_irq_handler; + uart_config[UART1_INDEX].tc_irq = &uart1_tc_irq; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG; + uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler; + uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler; + uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; + static struct hc32_uart_irq_config uart2_tc_irq = UART2_TX_CPLT_CONFIG; + uart2_tc_irq.irq_callback = hc32_uart2_tc_irq_handler; + uart_config[UART2_INDEX].tc_irq = &uart2_tc_irq; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart6_rx_timeout = UART6_RXTO_CONFIG; + uart6_dma_rx.irq_callback = hc32_uart6_dma_rx_irq_handler; + uart6_rx_timeout.irq_callback = hc32_uart6_rxto_irq_handler; + uart_config[UART6_INDEX].rx_timeout = &uart6_rx_timeout; + uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; +#endif +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; + static struct hc32_uart_irq_config uart6_tc_irq = UART6_TX_CPLT_CONFIG; + uart6_tc_irq.irq_callback = hc32_uart6_tc_irq_handler; + uart_config[UART6_INDEX].tc_irq = &uart6_tc_irq; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart7_rx_timeout = UART7_RXTO_CONFIG; + uart7_dma_rx.irq_callback = hc32_uart7_dma_rx_irq_handler; + uart7_rx_timeout.irq_callback = hc32_uart7_rxto_irq_handler; + uart_config[UART7_INDEX].rx_timeout = &uart7_rx_timeout; + uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; +#endif +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; + static struct hc32_uart_irq_config uart7_tc_irq = UART7_TX_CPLT_CONFIG; + uart7_tc_irq.irq_callback = hc32_uart7_tc_irq_handler; + uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq; +#endif +#endif +} + +/** + * @brief This function gets uart irq handle. + * @param None + * @retval None + */ +static void hc32_get_uart_callback(void) +{ +#ifdef BSP_USING_UART1 + uart_config[UART1_INDEX].rxerr_irq.irq_callback = hc32_uart1_rxerr_irq_handler; + uart_config[UART1_INDEX].rx_irq.irq_callback = hc32_uart1_rx_irq_handler; + uart_config[UART1_INDEX].tx_irq.irq_callback = hc32_uart1_tx_irq_handler; +#endif +#ifdef BSP_USING_UART2 + uart_config[UART2_INDEX].rxerr_irq.irq_callback = hc32_uart2_rxerr_irq_handler; + uart_config[UART2_INDEX].rx_irq.irq_callback = hc32_uart2_rx_irq_handler; + uart_config[UART2_INDEX].tx_irq.irq_callback = hc32_uart2_tx_irq_handler; +#endif +#ifdef BSP_USING_UART3 + uart_config[UART3_INDEX].rxerr_irq.irq_callback = hc32_uart3_rxerr_irq_handler; + uart_config[UART3_INDEX].rx_irq.irq_callback = hc32_uart3_rx_irq_handler; + uart_config[UART3_INDEX].tx_irq.irq_callback = hc32_uart3_tx_irq_handler; +#endif +#ifdef BSP_USING_UART4 + uart_config[UART4_INDEX].rxerr_irq.irq_callback = hc32_uart4_rxerr_irq_handler; + uart_config[UART4_INDEX].rx_irq.irq_callback = hc32_uart4_rx_irq_handler; + uart_config[UART4_INDEX].tx_irq.irq_callback = hc32_uart4_tx_irq_handler; +#endif +#ifdef BSP_USING_UART5 + uart_config[UART5_INDEX].rxerr_irq.irq_callback = hc32_uart5_rxerr_irq_handler; + uart_config[UART5_INDEX].rx_irq.irq_callback = hc32_uart5_rx_irq_handler; + uart_config[UART5_INDEX].tx_irq.irq_callback = hc32_uart5_tx_irq_handler; +#endif +#ifdef BSP_USING_UART6 + uart_config[UART6_INDEX].rxerr_irq.irq_callback = hc32_uart6_rxerr_irq_handler; + uart_config[UART6_INDEX].rx_irq.irq_callback = hc32_uart6_rx_irq_handler; + uart_config[UART6_INDEX].tx_irq.irq_callback = hc32_uart6_tx_irq_handler; +#endif +#ifdef BSP_USING_UART7 + uart_config[UART7_INDEX].rxerr_irq.irq_callback = hc32_uart7_rxerr_irq_handler; + uart_config[UART7_INDEX].rx_irq.irq_callback = hc32_uart7_rx_irq_handler; + uart_config[UART7_INDEX].tx_irq.irq_callback = hc32_uart7_tx_irq_handler; +#endif +#ifdef BSP_USING_UART8 + uart_config[UART8_INDEX].rxerr_irq.irq_callback = hc32_uart8_rxerr_irq_handler; + uart_config[UART8_INDEX].rx_irq.irq_callback = hc32_uart8_rx_irq_handler; + uart_config[UART8_INDEX].tx_irq.irq_callback = hc32_uart8_tx_irq_handler; +#endif +#ifdef BSP_USING_UART9 + uart_config[UART9_INDEX].rxerr_irq.irq_callback = hc32_uart9_rxerr_irq_handler; + uart_config[UART9_INDEX].rx_irq.irq_callback = hc32_uart9_rx_irq_handler; + uart_config[UART9_INDEX].tx_irq.irq_callback = hc32_uart9_tx_irq_handler; +#endif +#ifdef BSP_USING_UART10 + uart_config[UART10_INDEX].rxerr_irq.irq_callback = hc32_uart10_rxerr_irq_handler; + uart_config[UART10_INDEX].rx_irq.irq_callback = hc32_uart10_rx_irq_handler; + uart_config[UART10_INDEX].tx_irq.irq_callback = hc32_uart10_tx_irq_handler; +#endif +} + +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, + .dma_transmit = hc32_dma_transmit +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + hc32_uart_get_dma_info(); + hc32_get_uart_callback(); + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + uart_obj[i].config = &uart_config[i]; + /* register the handle */ + hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE); +#ifdef RT_SERIAL_USING_DMA + if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE); + hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE); + } + if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + hc32_install_irq_handler(&uart_config[i].tc_irq->irq_config, uart_config[i].tc_irq->irq_callback, RT_FALSE); + } +#endif + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | + uart_obj[i].uart_dma_flag), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif + +#endif /* RT_USING_SERIAL */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.h b/bsp/hc32/libraries/hc32_drivers/drv_usart.h new file mode 100644 index 0000000000..c8da34460c --- /dev/null +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" +#include "drv_irq.h" +#include "drv_dma.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_uart_irq_config +{ + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +/* HC32 config Rx timeout */ +struct hc32_uart_rxto +{ + CM_TMR0_TypeDef *TMR0_Instance; + rt_uint32_t channel; + rt_uint32_t clock; + rt_size_t timeout_bits; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +/* HC32 config uart class */ +struct hc32_uart_config +{ + const char *name; + CM_USART_TypeDef *Instance; + rt_uint32_t clock; + struct hc32_uart_irq_config rxerr_irq; + struct hc32_uart_irq_config rx_irq; + struct hc32_uart_irq_config tx_irq; +#ifdef RT_SERIAL_USING_DMA + struct hc32_uart_rxto *rx_timeout; + struct dma_config *dma_rx; + struct hc32_uart_irq_config *tc_irq; + struct dma_config *dma_tx; +#endif +}; + +/* HC32 uart dirver class */ +struct hc32_uart +{ + struct hc32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + rt_size_t dma_rx_last_index; +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/LICENSE b/bsp/hc32/libraries/hc32f4a0_ddl/LICENSE new file mode 100644 index 0000000000..304f0058f1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. ("XHSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/README.txt b/bsp/hc32/libraries/hc32f4a0_ddl/README.txt new file mode 100644 index 0000000000..3fd6873191 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/README.txt @@ -0,0 +1,4 @@ +version date comment + 2.0.0 + Mar 31, 2022 Initial release. +EOF diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/SConscript b/bsp/hc32/libraries/hc32f4a0_ddl/SConscript new file mode 100644 index 0000000000..ffdd53ba8a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/SConscript @@ -0,0 +1,74 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Split(''' +drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c +drivers/hc32_ll_driver/src/hc32_ll.c +drivers/hc32_ll_driver/src/hc32_ll_aos.c +drivers/hc32_ll_driver/src/hc32_ll_clk.c +drivers/hc32_ll_driver/src/hc32_ll_dma.c +drivers/hc32_ll_driver/src/hc32_ll_efm.c +drivers/hc32_ll_driver/src/hc32_ll_fcg.c +drivers/hc32_ll_driver/src/hc32_ll_gpio.c +drivers/hc32_ll_driver/src/hc32_ll_icg.c +drivers/hc32_ll_driver/src/hc32_ll_interrupts.c +drivers/hc32_ll_driver/src/hc32_ll_pwc.c +drivers/hc32_ll_driver/src/hc32_ll_rmu.c +drivers/hc32_ll_driver/src/hc32_ll_sram.c +drivers/hc32_ll_driver/src/hc32_ll_utility.c +drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c +''') + +if GetDepend(['RT_USING_SERIAL']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_usart.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr0.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_spi.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_can.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_dac.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_rtc.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_swdt.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_wdt.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_sdioc.c'] + +if GetDepend(['RT_USING_ON_CHIP_FLASH']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_efm.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])): + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c'] + +path = [ + cwd + '/drivers/cmsis/Device/HDSC/hc32f4xx/Include', + cwd + '/drivers/cmsis/Include', + cwd + '/drivers/hc32_ll_driver/inc',] + +CPPDEFINES = ['USE_DDL_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.mac b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.mac new file mode 100644 index 0000000000..e30bd40aa2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.out b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.out new file mode 100644 index 0000000000..f4a726caf9 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.out differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.flash b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.flash new file mode 100644 index 0000000000..a6694b3d9f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.out + 4 + 1 0x1800 + 0x03000000 + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac + 0 + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.out b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.out new file mode 100644 index 0000000000..47da8bd591 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.out differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.flash b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.flash new file mode 100644 index 0000000000..300fef50bd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.flash @@ -0,0 +1,9 @@ + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.out + 256 + 2048 0x1000 + 0x98000000 + 0 + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.out b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.out new file mode 100644 index 0000000000..605536a84d Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.out differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xG.flash b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xG.flash new file mode 100644 index 0000000000..e75b34f207 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xG.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out + 4 + 128 0x2000 + 0x00000000 + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac + 0 + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xI.flash b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xI.flash new file mode 100644 index 0000000000..29129c6ae9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xI.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out + 4 + 256 0x2000 + 0x00000000 + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac + 0 + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xG.board b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xG.board new file mode 100644 index 0000000000..35e75b17da --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xG.board @@ -0,0 +1,18 @@ + + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xG.flash + CODE 0x0 0xFFFFF + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash + CODE 0x03000000 0x030017FF + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash + CODE 0x98000000 0x987FFFFF + + + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xI.board b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xI.board new file mode 100644 index 0000000000..975988a469 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xI.board @@ -0,0 +1,18 @@ + + + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xI.flash + CODE 0x0 0x1FFFFF + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash + CODE 0x03000000 0x030017FF + + + $PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash + CODE 0x98000000 0x987FFFFF + + + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf new file mode 100644 index 0000000000..73c070bfb5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1FFE0000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf new file mode 100644 index 0000000000..159df7daa4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in QSPI_region { readonly section .ex_rom }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf new file mode 100644 index 0000000000..82734efbd6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in QSPI_region { readonly section .ex_rom }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h new file mode 100644 index 0000000000..2c2ff1591a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h @@ -0,0 +1,23785 @@ +/** + ******************************************************************************* + * @file HC32F4A0.h + * @brief Headerfile for HC32F4A0 series MCU + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + **/ + +#ifndef __HC32F4A0_H__ +#define __HC32F4A0_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F4A0 provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F4A0 supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F4A0 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum { + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SVCall */ + DebugMonitor_IRQn = -4, /* 12 DebugMonitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + INT000_IRQn = 0, + INT001_IRQn = 1, + INT002_IRQn = 2, + INT003_IRQn = 3, + INT004_IRQn = 4, + INT005_IRQn = 5, + INT006_IRQn = 6, + INT007_IRQn = 7, + INT008_IRQn = 8, + INT009_IRQn = 9, + INT010_IRQn = 10, + INT011_IRQn = 11, + INT012_IRQn = 12, + INT013_IRQn = 13, + INT014_IRQn = 14, + INT015_IRQn = 15, + INT016_IRQn = 16, + INT017_IRQn = 17, + INT018_IRQn = 18, + INT019_IRQn = 19, + INT020_IRQn = 20, + INT021_IRQn = 21, + INT022_IRQn = 22, + INT023_IRQn = 23, + INT024_IRQn = 24, + INT025_IRQn = 25, + INT026_IRQn = 26, + INT027_IRQn = 27, + INT028_IRQn = 28, + INT029_IRQn = 29, + INT030_IRQn = 30, + INT031_IRQn = 31, + INT032_IRQn = 32, + INT033_IRQn = 33, + INT034_IRQn = 34, + INT035_IRQn = 35, + INT036_IRQn = 36, + INT037_IRQn = 37, + INT038_IRQn = 38, + INT039_IRQn = 39, + INT040_IRQn = 40, + INT041_IRQn = 41, + INT042_IRQn = 42, + INT043_IRQn = 43, + INT044_IRQn = 44, + INT045_IRQn = 45, + INT046_IRQn = 46, + INT047_IRQn = 47, + INT048_IRQn = 48, + INT049_IRQn = 49, + INT050_IRQn = 50, + INT051_IRQn = 51, + INT052_IRQn = 52, + INT053_IRQn = 53, + INT054_IRQn = 54, + INT055_IRQn = 55, + INT056_IRQn = 56, + INT057_IRQn = 57, + INT058_IRQn = 58, + INT059_IRQn = 59, + INT060_IRQn = 60, + INT061_IRQn = 61, + INT062_IRQn = 62, + INT063_IRQn = 63, + INT064_IRQn = 64, + INT065_IRQn = 65, + INT066_IRQn = 66, + INT067_IRQn = 67, + INT068_IRQn = 68, + INT069_IRQn = 69, + INT070_IRQn = 70, + INT071_IRQn = 71, + INT072_IRQn = 72, + INT073_IRQn = 73, + INT074_IRQn = 74, + INT075_IRQn = 75, + INT076_IRQn = 76, + INT077_IRQn = 77, + INT078_IRQn = 78, + INT079_IRQn = 79, + INT080_IRQn = 80, + INT081_IRQn = 81, + INT082_IRQn = 82, + INT083_IRQn = 83, + INT084_IRQn = 84, + INT085_IRQn = 85, + INT086_IRQn = 86, + INT087_IRQn = 87, + INT088_IRQn = 88, + INT089_IRQn = 89, + INT090_IRQn = 90, + INT091_IRQn = 91, + INT092_IRQn = 92, + INT093_IRQn = 93, + INT094_IRQn = 94, + INT095_IRQn = 95, + INT096_IRQn = 96, + INT097_IRQn = 97, + INT098_IRQn = 98, + INT099_IRQn = 99, + INT100_IRQn = 100, + INT101_IRQn = 101, + INT102_IRQn = 102, + INT103_IRQn = 103, + INT104_IRQn = 104, + INT105_IRQn = 105, + INT106_IRQn = 106, + INT107_IRQn = 107, + INT108_IRQn = 108, + INT109_IRQn = 109, + INT110_IRQn = 110, + INT111_IRQn = 111, + INT112_IRQn = 112, + INT113_IRQn = 113, + INT114_IRQn = 114, + INT115_IRQn = 115, + INT116_IRQn = 116, + INT117_IRQn = 117, + INT118_IRQn = 118, + INT119_IRQn = 119, + INT120_IRQn = 120, + INT121_IRQn = 121, + INT122_IRQn = 122, + INT123_IRQn = 123, + INT124_IRQn = 124, + INT125_IRQn = 125, + INT126_IRQn = 126, + INT127_IRQn = 127, + INT128_IRQn = 128, + INT129_IRQn = 129, + INT130_IRQn = 130, + INT131_IRQn = 131, + INT132_IRQn = 132, + INT133_IRQn = 133, + INT134_IRQn = 134, + INT135_IRQn = 135, + INT136_IRQn = 136, + INT137_IRQn = 137, + INT138_IRQn = 138, + INT139_IRQn = 139, + INT140_IRQn = 140, + INT141_IRQn = 141, + INT142_IRQn = 142, + INT143_IRQn = 143, + +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum { + EVT_SRC_SWI_IRQ0 = 0U, + EVT_SRC_SWI_IRQ1 = 1U, + EVT_SRC_SWI_IRQ2 = 2U, + EVT_SRC_SWI_IRQ3 = 3U, + EVT_SRC_SWI_IRQ4 = 4U, + EVT_SRC_SWI_IRQ5 = 5U, + EVT_SRC_SWI_IRQ6 = 6U, + EVT_SRC_SWI_IRQ7 = 7U, + EVT_SRC_SWI_IRQ8 = 8U, + EVT_SRC_SWI_IRQ9 = 9U, + EVT_SRC_SWI_IRQ10 = 10U, + EVT_SRC_SWI_IRQ11 = 11U, + EVT_SRC_SWI_IRQ12 = 12U, + EVT_SRC_SWI_IRQ13 = 13U, + EVT_SRC_SWI_IRQ14 = 14U, + EVT_SRC_SWI_IRQ15 = 15U, + EVT_SRC_SWI_IRQ16 = 16U, + EVT_SRC_SWI_IRQ17 = 17U, + EVT_SRC_SWI_IRQ18 = 18U, + EVT_SRC_SWI_IRQ19 = 19U, + EVT_SRC_SWI_IRQ20 = 20U, + EVT_SRC_SWI_IRQ21 = 21U, + EVT_SRC_SWI_IRQ22 = 22U, + EVT_SRC_SWI_IRQ23 = 23U, + EVT_SRC_SWI_IRQ24 = 24U, + EVT_SRC_SWI_IRQ25 = 25U, + EVT_SRC_SWI_IRQ26 = 26U, + EVT_SRC_SWI_IRQ27 = 27U, + EVT_SRC_SWI_IRQ28 = 28U, + EVT_SRC_SWI_IRQ29 = 29U, + EVT_SRC_SWI_IRQ30 = 30U, + EVT_SRC_SWI_IRQ31 = 31U, + /* External Interrupt */ + EVT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + EVT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + EVT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + EVT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + EVT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + EVT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + EVT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + EVT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + EVT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + EVT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + EVT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + EVT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + EVT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + EVT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + EVT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + EVT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + /* DMA_1 */ + EVT_SRC_DMA1_TC0 = 32U, /* DMA_1_TC0 */ + EVT_SRC_DMA1_TC1 = 33U, /* DMA_1_TC1 */ + EVT_SRC_DMA1_TC2 = 34U, /* DMA_1_TC2 */ + EVT_SRC_DMA1_TC3 = 35U, /* DMA_1_TC3 */ + EVT_SRC_DMA1_TC4 = 36U, /* DMA_1_TC4 */ + EVT_SRC_DMA1_TC5 = 37U, /* DMA_1_TC5 */ + EVT_SRC_DMA1_TC6 = 38U, /* DMA_1_TC6 */ + EVT_SRC_DMA1_TC7 = 39U, /* DMA_1_TC7 */ + EVT_SRC_DMA1_BTC0 = 40U, /* DMA_1_BTC0 */ + EVT_SRC_DMA1_BTC1 = 41U, /* DMA_1_BTC1 */ + EVT_SRC_DMA1_BTC2 = 42U, /* DMA_1_BTC2 */ + EVT_SRC_DMA1_BTC3 = 43U, /* DMA_1_BTC3 */ + EVT_SRC_DMA1_BTC4 = 44U, /* DMA_1_BTC4 */ + EVT_SRC_DMA1_BTC5 = 45U, /* DMA_1_BTC5 */ + EVT_SRC_DMA1_BTC6 = 46U, /* DMA_1_BTC6 */ + EVT_SRC_DMA1_BTC7 = 47U, /* DMA_1_BTC7 */ + /* EFM */ + EVT_SRC_EFM_OPTEND = 51U, /* EFM_OPTEND */ + /* USBFS */ + EVT_SRC_USBFS_SOF = 52U, /* USBFS_SOF */ + /* USBHS */ + EVT_SRC_USBHS_SOF = 53U, /* USBHS_SOF */ + /* DCU */ + EVT_SRC_DCU1 = 55U, /* DCU1 */ + EVT_SRC_DCU2 = 56U, /* DCU2 */ + EVT_SRC_DCU3 = 57U, /* DCU3 */ + EVT_SRC_DCU4 = 58U, /* DCU4 */ + EVT_SRC_DCU5 = 59U, /* DCU5 */ + EVT_SRC_DCU6 = 60U, /* DCU6 */ + EVT_SRC_DCU7 = 61U, /* DCU7 */ + EVT_SRC_DCU8 = 62U, /* DCU8 */ + /* DMA_2 */ + EVT_SRC_DMA2_TC0 = 64U, /* DMA_2_TC0 */ + EVT_SRC_DMA2_TC1 = 65U, /* DMA_2_TC1 */ + EVT_SRC_DMA2_TC2 = 66U, /* DMA_2_TC2 */ + EVT_SRC_DMA2_TC3 = 67U, /* DMA_2_TC3 */ + EVT_SRC_DMA2_TC4 = 68U, /* DMA_2_TC4 */ + EVT_SRC_DMA2_TC5 = 69U, /* DMA_2_TC5 */ + EVT_SRC_DMA2_TC6 = 70U, /* DMA_2_TC6 */ + EVT_SRC_DMA2_TC7 = 71U, /* DMA_2_TC7 */ + EVT_SRC_DMA2_BTC0 = 72U, /* DMA_2_BTC0 */ + EVT_SRC_DMA2_BTC1 = 73U, /* DMA_2_BTC1 */ + EVT_SRC_DMA2_BTC2 = 74U, /* DMA_2_BTC2 */ + EVT_SRC_DMA2_BTC3 = 75U, /* DMA_2_BTC3 */ + EVT_SRC_DMA2_BTC4 = 76U, /* DMA_2_BTC4 */ + EVT_SRC_DMA2_BTC5 = 77U, /* DMA_2_BTC5 */ + EVT_SRC_DMA2_BTC6 = 78U, /* DMA_2_BTC6 */ + EVT_SRC_DMA2_BTC7 = 79U, /* DMA_2_BTC7 */ + /* MAU */ + EVT_SRC_MAU_SQRT = 83U, /* MAU_SQRT */ + /* DVP */ + EVT_SRC_DVP_FRAMSTA = 84U, /* DVP_FRAMSTA */ + EVT_SRC_DVP_LINESTA = 85U, /* DVP_LINESTA */ + EVT_SRC_DVP_LINEEND = 86U, /* DVP_LINEEND */ + EVT_SRC_DVP_FRAMEND = 87U, /* DVP_FRAMEND */ + EVT_SRC_DVP_SQUERR = 88U, /* DVP_SQUERR */ + EVT_SRC_DVP_FIFOERR = 89U, /* DVP_FIFOERR */ + EVT_SRC_DVP_DMAREQ = 90U, /* DVP_DMAREQ */ + /* FMAC */ + EVT_SRC_FMAC_1 = 91U, /* FMAC_1_FIR */ + EVT_SRC_FMAC_2 = 92U, /* FMAC_2_FIR */ + EVT_SRC_FMAC_3 = 93U, /* FMAC_3_FIR */ + EVT_SRC_FMAC_4 = 94U, /* FMAC_4_FIR */ + /* TIMER0 */ + EVT_SRC_TMR0_1_CMP_A = 96U, /* TMR0_1_CMPA */ + EVT_SRC_TMR0_1_CMP_B = 97U, /* TMR0_1_CMPB */ + EVT_SRC_TMR0_2_CMP_A = 98U, /* TMR0_2_CMPA */ + EVT_SRC_TMR0_2_CMP_B = 99U, /* TMR0_2_CMPB */ + /* TIMER2 */ + EVT_SRC_TMR2_1_CMP_A = 100U, /* TMR2_1_CMPA */ + EVT_SRC_TMR2_1_CMP_B = 101U, /* TMR2_1_CMPB */ + EVT_SRC_TMR2_1_OVF_A = 102U, /* TMR2_1_OVFA */ + EVT_SRC_TMR2_1_OVF_B = 103U, /* TMR2_1_OVFB */ + EVT_SRC_TMR2_2_CMP_A = 104U, /* TMR2_2_CMPA */ + EVT_SRC_TMR2_2_CMP_B = 105U, /* TMR2_2_CMPB */ + EVT_SRC_TMR2_2_OVF_A = 106U, /* TMR2_2_OVFA */ + EVT_SRC_TMR2_2_OVF_B = 107U, /* TMR2_2_OVFB */ + EVT_SRC_TMR2_3_CMP_A = 108U, /* TMR2_3_CMPA */ + EVT_SRC_TMR2_3_CMP_B = 109U, /* TMR2_3_CMPB */ + EVT_SRC_TMR2_3_OVF_A = 110U, /* TMR2_3_OVFA */ + EVT_SRC_TMR2_3_OVF_B = 111U, /* TMR2_3_OVFB */ + EVT_SRC_TMR2_4_CMP_A = 112U, /* TMR2_4_CMPA */ + EVT_SRC_TMR2_4_CMP_B = 113U, /* TMR2_4_CMPB */ + EVT_SRC_TMR2_4_OVF_A = 114U, /* TMR2_4_OVFA */ + EVT_SRC_TMR2_4_OVF_B = 115U, /* TMR2_4_OVFB */ + /* RTC */ + EVT_SRC_RTC_ALM = 121U, /* RTC_ALM */ + EVT_SRC_RTC_PRD = 122U, /* RTC_PRD */ + /* TIMER6_1 */ + EVT_SRC_TMR6_1_GCMP_A = 128U, /* TMR6_1_GCMA */ + EVT_SRC_TMR6_1_GCMP_B = 129U, /* TMR6_1_GCMB */ + EVT_SRC_TMR6_1_GCMP_C = 130U, /* TMR6_1_GCMC */ + EVT_SRC_TMR6_1_GCMP_D = 131U, /* TMR6_1_GCMD */ + EVT_SRC_TMR6_1_GCMP_E = 132U, /* TMR6_1_GCME */ + EVT_SRC_TMR6_1_GCMP_F = 133U, /* TMR6_1_GCMF */ + EVT_SRC_TMR6_1_OVF = 134U, /* TMR6_1_GOVF */ + EVT_SRC_TMR6_1_UDF = 135U, /* TMR6_1_GUDF */ + /* TIMER4_1 */ + EVT_SRC_TMR4_1_SCMP_UH = 136U, /* TMR4_1_SCMUH */ + EVT_SRC_TMR4_1_SCMP_UL = 137U, /* TMR4_1_SCMUL */ + EVT_SRC_TMR4_1_SCMP_VH = 138U, /* TMR4_1_SCMVH */ + EVT_SRC_TMR4_1_SCMP_VL = 139U, /* TMR4_1_SCMVL */ + EVT_SRC_TMR4_1_SCMP_WH = 140U, /* TMR4_1_SCMWH */ + EVT_SRC_TMR4_1_SCMP_WL = 141U, /* TMR4_1_SCMWL */ + /* TIMER6_2 */ + EVT_SRC_TMR6_2_GCMP_A = 144U, /* TMR6_2_GCMA */ + EVT_SRC_TMR6_2_GCMP_B = 145U, /* TMR6_2_GCMB */ + EVT_SRC_TMR6_2_GCMP_C = 146U, /* TMR6_2_GCMC */ + EVT_SRC_TMR6_2_GCMP_D = 147U, /* TMR6_2_GCMD */ + EVT_SRC_TMR6_2_GCMP_E = 148U, /* TMR6_2_GCME */ + EVT_SRC_TMR6_2_GCMP_F = 149U, /* TMR6_2_GCMF */ + EVT_SRC_TMR6_2_OVF = 150U, /* TMR6_2_GOVF */ + EVT_SRC_TMR6_2_UDF = 151U, /* TMR6_2_GUDF */ + /* TIMER4_2 */ + EVT_SRC_TMR4_2_SCMP_UH = 152U, /* TMR4_2_SCMUH */ + EVT_SRC_TMR4_2_SCMP_UL = 153U, /* TMR4_2_SCMUL */ + EVT_SRC_TMR4_2_SCMP_VH = 154U, /* TMR4_2_SCMVH */ + EVT_SRC_TMR4_2_SCMP_VL = 155U, /* TMR4_2_SCMVL */ + EVT_SRC_TMR4_2_SCMP_WH = 156U, /* TMR4_2_SCMWH */ + EVT_SRC_TMR4_2_SCMP_WL = 157U, /* TMR4_2_SCMWL */ + /* TIMER6_3 */ + EVT_SRC_TMR6_3_GCMP_A = 160U, /* TMR6_3_GCMA */ + EVT_SRC_TMR6_3_GCMP_B = 161U, /* TMR6_3_GCMB */ + EVT_SRC_TMR6_3_GCMP_C = 162U, /* TMR6_3_GCMC */ + EVT_SRC_TMR6_3_GCMP_D = 163U, /* TMR6_3_GCMD */ + EVT_SRC_TMR6_3_GCMP_E = 164U, /* TMR6_3_GCME */ + EVT_SRC_TMR6_3_GCMP_F = 165U, /* TMR6_3_GCMF */ + EVT_SRC_TMR6_3_OVF = 166U, /* TMR6_3_GOVF */ + EVT_SRC_TMR6_3_UDF = 167U, /* TMR6_3_GUDF */ + /* TIMER4_3 */ + EVT_SRC_TMR4_3_SCMP_UH = 168U, /* TMR4_3_SCMUH */ + EVT_SRC_TMR4_3_SCMP_UL = 169U, /* TMR4_3_SCMUL */ + EVT_SRC_TMR4_3_SCMP_VH = 170U, /* TMR4_3_SCMVH */ + EVT_SRC_TMR4_3_SCMP_VL = 171U, /* TMR4_3_SCMVL */ + EVT_SRC_TMR4_3_SCMP_WH = 172U, /* TMR4_3_SCMWH */ + EVT_SRC_TMR4_3_SCMP_WL = 173U, /* TMR4_3_SCMWL */ + /* TIMER6 */ + EVT_SRC_TMR6_1_SCMP_A = 179U, /* TMR6_1_SCMA */ + EVT_SRC_TMR6_1_SCMP_B = 180U, /* TMR6_1_SCMB */ + EVT_SRC_TMR6_2_SCMP_A = 187U, /* TMR6_2_SCMA */ + EVT_SRC_TMR6_2_SCMP_B = 188U, /* TMR6_2_SCMB */ + EVT_SRC_TMR6_3_SCMP_A = 195U, /* TMR6_3_SCMA */ + EVT_SRC_TMR6_3_SCMP_B = 196U, /* TMR6_3_SCMB */ + EVT_SRC_TMR6_4_GCMP_A = 208U, /* TMR6_4_GCMA */ + EVT_SRC_TMR6_4_GCMP_B = 209U, /* TMR6_4_GCMB */ + EVT_SRC_TMR6_4_GCMP_C = 210U, /* TMR6_4_GCMC */ + EVT_SRC_TMR6_4_GCMP_D = 211U, /* TMR6_4_GCMD */ + EVT_SRC_TMR6_4_GCMP_E = 212U, /* TMR6_4_GCME */ + EVT_SRC_TMR6_4_GCMP_F = 213U, /* TMR6_4_GCMF */ + EVT_SRC_TMR6_4_OVF = 214U, /* TMR6_4_GOVF */ + EVT_SRC_TMR6_4_UDF = 215U, /* TMR6_4_GUDF */ + EVT_SRC_TMR6_4_SCMP_A = 219U, /* TMR6_4_SCMA */ + EVT_SRC_TMR6_4_SCMP_B = 220U, /* TMR6_4_SCMB */ + EVT_SRC_TMR6_5_GCMP_A = 224U, /* TMR6_5_GCMA */ + EVT_SRC_TMR6_5_GCMP_B = 225U, /* TMR6_5_GCMB */ + EVT_SRC_TMR6_5_GCMP_C = 226U, /* TMR6_5_GCMC */ + EVT_SRC_TMR6_5_GCMP_D = 227U, /* TMR6_5_GCMD */ + EVT_SRC_TMR6_5_GCMP_E = 228U, /* TMR6_5_GCME */ + EVT_SRC_TMR6_5_GCMP_F = 229U, /* TMR6_5_GCMF */ + EVT_SRC_TMR6_5_OVF = 230U, /* TMR6_5_GOVF */ + EVT_SRC_TMR6_5_UDF = 231U, /* TMR6_5_GUDF */ + EVT_SRC_TMR6_5_SCMP_A = 235U, /* TMR6_5_SCMA */ + EVT_SRC_TMR6_5_SCMP_B = 236U, /* TMR6_5_SCMB */ + /* TIMERA_1 */ + EVT_SRC_TMRA_1_OVF = 237U, /* TMRA_1_OVF */ + EVT_SRC_TMRA_1_UDF = 238U, /* TMRA_1_UDF */ + EVT_SRC_TMRA_1_CMP = 239U, /* TMRA_1_CMP */ + /* TIMER6_6 */ + EVT_SRC_TMR6_6_GCMP_A = 240U, /* TMR6_6_GCMA */ + EVT_SRC_TMR6_6_GCMP_B = 241U, /* TMR6_6_GCMB */ + EVT_SRC_TMR6_6_GCMP_C = 242U, /* TMR6_6_GCMC */ + EVT_SRC_TMR6_6_GCMP_D = 243U, /* TMR6_6_GCMD */ + EVT_SRC_TMR6_6_GCMP_E = 244U, /* TMR6_6_GCME */ + EVT_SRC_TMR6_6_GCMP_F = 245U, /* TMR6_6_GCMF */ + EVT_SRC_TMR6_6_OVF = 246U, /* TMR6_6_GOVF */ + EVT_SRC_TMR6_6_UDF = 247U, /* TMR6_6_GUDF */ + EVT_SRC_TMR6_6_SCMP_A = 251U, /* TMR6_6_SCMA */ + EVT_SRC_TMR6_6_SCMP_B = 252U, /* TMR6_6_SCMB */ + /* TIMERA_2 */ + EVT_SRC_TMRA_2_OVF = 253U, /* TMRA_2_OVF */ + EVT_SRC_TMRA_2_UDF = 254U, /* TMRA_2_UDF */ + EVT_SRC_TMRA_2_CMP = 255U, /* TMRA_2_CMP */ + /* TIMER6_7 */ + EVT_SRC_TMR6_7_GCMP_A = 256U, /* TMR6_7_GCMA */ + EVT_SRC_TMR6_7_GCMP_B = 257U, /* TMR6_7_GCMB */ + EVT_SRC_TMR6_7_GCMP_C = 258U, /* TMR6_7_GCMC */ + EVT_SRC_TMR6_7_GCMP_D = 259U, /* TMR6_7_GCMD */ + EVT_SRC_TMR6_7_GCMP_E = 260U, /* TMR6_7_GCME */ + EVT_SRC_TMR6_7_GCMP_F = 261U, /* TMR6_7_GCMF */ + EVT_SRC_TMR6_7_OVF = 262U, /* TMR6_7_GOVF */ + EVT_SRC_TMR6_7_UDF = 263U, /* TMR6_7_GUDF */ + EVT_SRC_TMR6_7_SCMP_A = 267U, /* TMR6_7_SCMA */ + EVT_SRC_TMR6_7_SCMP_B = 268U, /* TMR6_7_SCMB */ + /* TIMERA_3 */ + EVT_SRC_TMRA_3_OVF = 269U, /* TMRA_3_OVF */ + EVT_SRC_TMRA_3_UDF = 270U, /* TMRA_3_UDF */ + EVT_SRC_TMRA_3_CMP = 271U, /* TMRA_3_CMP */ + /* TIMER6_8 */ + EVT_SRC_TMR6_8_GCMP_A = 272U, /* TMR6_8_GCMA */ + EVT_SRC_TMR6_8_GCMP_B = 273U, /* TMR6_8_GCMB */ + EVT_SRC_TMR6_8_GCMP_C = 274U, /* TMR6_8_GCMC */ + EVT_SRC_TMR6_8_GCMP_D = 275U, /* TMR6_8_GCMD */ + EVT_SRC_TMR6_8_GCMP_E = 276U, /* TMR6_8_GCME */ + EVT_SRC_TMR6_8_GCMP_F = 277U, /* TMR6_8_GCMF */ + EVT_SRC_TMR6_8_OVF = 278U, /* TMR6_8_GOVF */ + EVT_SRC_TMR6_8_UDF = 279U, /* TMR6_8_GUDF */ + EVT_SRC_TMR6_8_SCMP_A = 283U, /* TMR6_8_SCMA */ + EVT_SRC_TMR6_8_SCMP_B = 284U, /* TMR6_8_SCMB */ + /* TIMERA_4 */ + EVT_SRC_TMRA_4_OVF = 285U, /* TMRA_4_OVF */ + EVT_SRC_TMRA_4_UDF = 286U, /* TMRA_4_UDF */ + EVT_SRC_TMRA_4_CMP = 287U, /* TMRA_4_CMP */ + /* AOS_STRG */ + EVT_SRC_AOS_STRG = 299U, /* AOS_STRG */ + /* USART1 USART2 */ + EVT_SRC_USART1_EI = 300U, /* USART_1_EI */ + EVT_SRC_USART1_RI = 301U, /* USART_1_RI */ + EVT_SRC_USART1_TI = 302U, /* USART_1_TI */ + EVT_SRC_USART1_TCI = 303U, /* USART_1_TCI */ + EVT_SRC_USART1_RTO = 304U, /* USART_1_RTO */ + EVT_SRC_USART2_EI = 305U, /* USART_2_EI */ + EVT_SRC_USART2_RI = 306U, /* USART_2_RI */ + EVT_SRC_USART2_TI = 307U, /* USART_2_TI */ + EVT_SRC_USART2_TCI = 308U, /* USART_2_TCI */ + EVT_SRC_USART2_RTO = 309U, /* USART_2_RTO */ + /* SPI1 SPI2 */ + EVT_SRC_SPI1_SPRI = 310U, /* SPI_1_SPRI */ + EVT_SRC_SPI1_SPTI = 311U, /* SPI_1_SPTI */ + EVT_SRC_SPI1_SPII = 312U, /* SPI_1_SPII */ + EVT_SRC_SPI1_SPEI = 313U, /* SPI_1_SPEI */ + EVT_SRC_SPI1_SPEND = 314U, /* SPI_1_SPEND */ + EVT_SRC_SPI2_SPRI = 315U, /* SPI_2_SPRI */ + EVT_SRC_SPI2_SPTI = 316U, /* SPI_2_SPTI */ + EVT_SRC_SPI2_SPII = 317U, /* SPI_2_SPII */ + EVT_SRC_SPI2_SPEI = 318U, /* SPI_2_SPEI */ + EVT_SRC_SPI2_SPEND = 319U, /* SPI_2_STEND */ + /* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */ + EVT_SRC_TMRA_5_OVF = 320U, /* TMRA_5_OVF */ + EVT_SRC_TMRA_5_UDF = 321U, /* TMRA_5_UDF */ + EVT_SRC_TMRA_5_CMP = 322U, /* TMRA_5_CMP */ + EVT_SRC_TMRA_6_OVF = 323U, /* TMRA_6_OVF */ + EVT_SRC_TMRA_6_UDF = 324U, /* TMRA_6_UDF */ + EVT_SRC_TMRA_6_CMP = 325U, /* TMRA_6_CMP */ + EVT_SRC_TMRA_7_OVF = 326U, /* TMRA_7_OVF */ + EVT_SRC_TMRA_7_UDF = 327U, /* TMRA_7_UDF */ + EVT_SRC_TMRA_7_CMP = 328U, /* TMRA_7_CMP */ + EVT_SRC_TMRA_8_OVF = 329U, /* TMRA_8_OVF */ + EVT_SRC_TMRA_8_UDF = 330U, /* TMRA_8_UDF */ + EVT_SRC_TMRA_8_CMP = 331U, /* TMRA_8_CMP */ + /* USART3 USART4 */ + EVT_SRC_USART3_EI = 332U, /* USART_3_EI */ + EVT_SRC_USART3_RI = 333U, /* USART_3_RI */ + EVT_SRC_USART3_TI = 334U, /* USART_3_TI */ + EVT_SRC_USART3_TCI = 335U, /* USART_3_TCI */ + EVT_SRC_USART4_EI = 336U, /* USART_4_EI */ + EVT_SRC_USART4_RI = 337U, /* USART_4_RI */ + EVT_SRC_USART4_TI = 338U, /* USART_4_TI */ + EVT_SRC_USART4_TCI = 339U, /* USART_4_TCI */ + /* SPI3 SPI4 */ + EVT_SRC_SPI3_SPRI = 342U, /* SPI_3_SPRI */ + EVT_SRC_SPI3_SPTI = 343U, /* SPI_3_SPTI */ + EVT_SRC_SPI3_SPII = 344U, /* SPI_3_SPII */ + EVT_SRC_SPI3_SPEI = 345U, /* SPI_3_SPEI */ + EVT_SRC_SPI3_SPEND = 346U, /* SPI_3_SPEND */ + EVT_SRC_SPI4_SPRI = 347U, /* SPI_4_SPRI */ + EVT_SRC_SPI4_SPTI = 348U, /* SPI_4_SPTI */ + EVT_SRC_SPI4_SPII = 349U, /* SPI_4_SPII */ + EVT_SRC_SPI4_SPEI = 350U, /* SPI_4_SPEI */ + EVT_SRC_SPI4_SPEND = 351U, /* SPI_4_SPEND */ + /* TIMERA_9 TIMERA_10 TIMERA_11 TIMERA_12 */ + EVT_SRC_TMRA_9_OVF = 352U, /* TMRA_9_OVF */ + EVT_SRC_TMRA_9_UDF = 353U, /* TMRA_9_UDF */ + EVT_SRC_TMRA_9_CMP = 354U, /* TMRA_9_CMP */ + EVT_SRC_TMRA_10_OVF = 355U, /* TMRA_10_OVF */ + EVT_SRC_TMRA_10_UDF = 356U, /* TMRA_10_UDF */ + EVT_SRC_TMRA_10_CMP = 357U, /* TMRA_10_CMP */ + EVT_SRC_TMRA_11_OVF = 358U, /* TMRA_11_OVF */ + EVT_SRC_TMRA_11_UDF = 359U, /* TMRA_11_UDF */ + EVT_SRC_TMRA_11_CMP = 360U, /* TMRA_11_CMP */ + EVT_SRC_TMRA_12_OVF = 361U, /* TMRA_12_OVF */ + EVT_SRC_TMRA_12_UDF = 362U, /* TMRA_12_UDF */ + EVT_SRC_TMRA_12_CMP = 363U, /* TMRA_12_CMP */ + /* USART5 USART6 */ + EVT_SRC_USART5_BRKWKPI = 364U, /* USART_5_BRKWKPI */ + EVT_SRC_USART5_EI = 365U, /* USART_5_EI */ + EVT_SRC_USART5_RI = 366U, /* USART_5_RI */ + EVT_SRC_USART5_TI = 367U, /* USART_5_TI */ + EVT_SRC_USART5_TCI = 368U, /* USART_5_TCI */ + EVT_SRC_USART6_EI = 369U, /* USART_6_EI */ + EVT_SRC_USART6_RI = 370U, /* USART_6_RI */ + EVT_SRC_USART6_TI = 371U, /* USART_6_TI */ + EVT_SRC_USART6_TCI = 372U, /* USART_6_TCI */ + EVT_SRC_USART6_RTO = 373U, /* USART_6_RTO */ + /* SPI5 SPI6 */ + EVT_SRC_SPI5_SPRI = 374U, /* SPI_5_SPRI */ + EVT_SRC_SPI5_SPTI = 375U, /* SPI_5_SPTI */ + EVT_SRC_SPI5_SPII = 376U, /* SPI_5_SPII */ + EVT_SRC_SPI5_SPEI = 377U, /* SPI_5_SPEI */ + EVT_SRC_SPI5_SPEND = 378U, /* SPI_5_SPEND */ + EVT_SRC_SPI6_SPRI = 379U, /* SPI_6_SPRI */ + EVT_SRC_SPI6_SPTI = 380U, /* SPI_6_SPTI */ + EVT_SRC_SPI6_SPII = 381U, /* SPI_6_SPII */ + EVT_SRC_SPI6_SPEI = 382U, /* SPI_6_SPEI */ + EVT_SRC_SPI6_SPEND = 383U, /* SPI_6_SPEND */ + /* I2S1 I2S2 */ + EVT_SRC_I2S1_TXIRQOUT = 384U, /* I2S_1_TXIRQOUT */ + EVT_SRC_I2S1_RXIRQOUT = 385U, /* I2S_1_RXIRQOUT */ + EVT_SRC_I2S2_TXIRQOUT = 387U, /* I2S_2_TXIRQOUT */ + EVT_SRC_I2S2_RXIRQOUT = 388U, /* I2S_2_RXIRQOUT */ + /* USART7 USART8 */ + EVT_SRC_USART7_EI = 390U, /* USART_7_EI */ + EVT_SRC_USART7_RI = 391U, /* USART_7_RI */ + EVT_SRC_USART7_TI = 392U, /* USART_7_TI */ + EVT_SRC_USART7_TCI = 393U, /* USART_7_TCI */ + EVT_SRC_USART7_RTO = 394U, /* USART_7_RTO */ + EVT_SRC_USART8_EI = 395U, /* USART_8_EI */ + EVT_SRC_USART8_RI = 396U, /* USART_8_RI */ + EVT_SRC_USART8_TI = 397U, /* USART_8_TI */ + EVT_SRC_USART8_TCI = 398U, /* USART_8_TCI */ + /* HASH */ + EVT_SRC_HASH = 401U, /* HASH_INT */ + /* SDIOC */ + EVT_SRC_SDIOC1_DMAR = 402U, /* SDIOC_1_DMAR */ + EVT_SRC_SDIOC1_DMAW = 403U, /* SDIOC_1_DMAW */ + EVT_SRC_SDIOC2_DMAR = 405U, /* SDIOC_2_DMAR */ + EVT_SRC_SDIOC2_DMAW = 406U, /* SDIOC_2_DMAW */ + /* EVENT PORT */ + EVT_SRC_EVENT_PORT1 = 408U, /* EVENT_PORT1 */ + EVT_SRC_EVENT_PORT2 = 409U, /* EVENT_PORT2 */ + EVT_SRC_EVENT_PORT3 = 410U, /* EVENT_PORT3 */ + EVT_SRC_EVENT_PORT4 = 411U, /* EVENT_PORT4 */ + /* ETHER */ + EVT_SRC_ETH_PPS_OUT_0 = 414U, /* ETH_PPS_OUT_0 */ + EVT_SRC_ETH_PPS_OUT_1 = 415U, /* ETH_PPS_OUT_1 */ + /* I2S3 I2S4 */ + EVT_SRC_I2S3_TXIRQOUT = 416U, /* I2S_3_TXIRQOUT */ + EVT_SRC_I2S3_RXIRQOUT = 417U, /* I2S_3_RXIRQOUT */ + EVT_SRC_I2S4_TXIRQOUT = 419U, /* I2S_4_TXIRQOUT */ + EVT_SRC_I2S4_RXIRQOUT = 420U, /* I2S_4_RXIRQOUT */ + /* USART9 USART10 */ + EVT_SRC_USART9_EI = 422U, /* USART_9_EI */ + EVT_SRC_USART9_RI = 423U, /* USART_9_RI */ + EVT_SRC_USART9_TI = 424U, /* USART_9_TI */ + EVT_SRC_USART9_TCI = 425U, /* USART_9_TCI */ + EVT_SRC_USART10_BRKWKPI = 426U, /* USART_10_BRKWKPI */ + EVT_SRC_USART10_EI = 427U, /* USART_10_EI */ + EVT_SRC_USART10_RI = 428U, /* USART_10_RI */ + EVT_SRC_USART10_TI = 429U, /* USART_10_TI */ + EVT_SRC_USART10_TCI = 430U, /* USART_10_TCI */ + /* I2C1 I2C2 I2C3 */ + EVT_SRC_I2C1_RXI = 432U, /* I2C_1_RXI */ + EVT_SRC_I2C1_TXI = 433U, /* I2C_1_TXI */ + EVT_SRC_I2C1_TEI = 434U, /* I2C_1_TEI */ + EVT_SRC_I2C1_EEI = 435U, /* I2C_1_EEI */ + EVT_SRC_I2C2_RXI = 436U, /* I2C_2_RXI */ + EVT_SRC_I2C2_TXI = 437U, /* I2C_2_TXI */ + EVT_SRC_I2C2_TEI = 438U, /* I2C_2_TEI */ + EVT_SRC_I2C2_EEI = 439U, /* I2C_2_EEI */ + EVT_SRC_I2C3_RXI = 440U, /* I2C_3_RXI */ + EVT_SRC_I2C3_TXI = 441U, /* I2C_3_TXI */ + EVT_SRC_I2C3_TEI = 442U, /* I2C_3_TEI */ + EVT_SRC_I2C3_EEI = 443U, /* I2C_3_EEI */ + /* ACMP */ + EVT_SRC_CMP1 = 444U, /* CMP1 */ + EVT_SRC_CMP2 = 445U, /* CMP2 */ + EVT_SRC_CMP3 = 446U, /* CMP3 */ + EVT_SRC_CMP4 = 447U, /* CMP4 */ + /* I2C4 I2C5 I2C6 */ + EVT_SRC_I2C4_RXI = 448U, /* I2C_4_RXI */ + EVT_SRC_I2C4_TXI = 449U, /* I2C_4_TXI */ + EVT_SRC_I2C4_TEI = 450U, /* I2C_4_TEI */ + EVT_SRC_I2C4_EEI = 451U, /* I2C_4_EEI */ + EVT_SRC_I2C5_RXI = 452U, /* I2C_5_RXI */ + EVT_SRC_I2C5_TXI = 453U, /* I2C_5_TXI */ + EVT_SRC_I2C5_TEI = 454U, /* I2C_5_TEI */ + EVT_SRC_I2C5_EEI = 455U, /* I2C_5_EEI */ + EVT_SRC_I2C6_RXI = 456U, /* I2C_6_RXI */ + EVT_SRC_I2C6_TXI = 457U, /* I2C_6_TXI */ + EVT_SRC_I2C6_TEI = 458U, /* I2C_6_TEI */ + EVT_SRC_I2C6_EEI = 459U, /* I2C_6_EEI */ + /* LVD */ + EVT_SRC_LVD1 = 461U, /* LVD1 */ + EVT_SRC_LVD2 = 462U, /* LVD2 */ + /* OTS */ + EVT_SRC_OTS = 463U, /* OTS */ + /* WDT */ + EVT_SRC_WDT_REFUDF = 467U, /* WDT_REFUDF */ + /* ADC */ + EVT_SRC_ADC1_EOCA = 480U, /* ADC_1_EOCA */ + EVT_SRC_ADC1_EOCB = 481U, /* ADC_1_EOCB */ + EVT_SRC_ADC1_CMP0 = 482U, /* ADC_1_CMP0 */ + EVT_SRC_ADC1_CMP1 = 483U, /* ADC_1_CMP1 */ + EVT_SRC_ADC2_EOCA = 484U, /* ADC_2_EOCA */ + EVT_SRC_ADC2_EOCB = 485U, /* ADC_2_EOCB */ + EVT_SRC_ADC2_CMP0 = 486U, /* ADC_2_CMP0 */ + EVT_SRC_ADC2_CMP1 = 487U, /* ADC_2_CMP1 */ + EVT_SRC_ADC3_EOCA = 488U, /* ADC_3_EOCA */ + EVT_SRC_ADC3_EOCB = 489U, /* ADC_3_EOCB */ + EVT_SRC_ADC3_CMP0 = 490U, /* ADC_3_CMP0 */ + EVT_SRC_ADC3_CMP1 = 491U, /* ADC_3_CMP1 */ + /* TRNG */ + EVT_SRC_TRNG_END = 492U, /* TRNG_END */ + EVT_SRC_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum { + INT_SRC_SWI_IRQ0 = 0U, + INT_SRC_SWI_IRQ1 = 1U, + INT_SRC_SWI_IRQ2 = 2U, + INT_SRC_SWI_IRQ3 = 3U, + INT_SRC_SWI_IRQ4 = 4U, + INT_SRC_SWI_IRQ5 = 5U, + INT_SRC_SWI_IRQ6 = 6U, + INT_SRC_SWI_IRQ7 = 7U, + INT_SRC_SWI_IRQ8 = 8U, + INT_SRC_SWI_IRQ9 = 9U, + INT_SRC_SWI_IRQ10 = 10U, + INT_SRC_SWI_IRQ11 = 11U, + INT_SRC_SWI_IRQ12 = 12U, + INT_SRC_SWI_IRQ13 = 13U, + INT_SRC_SWI_IRQ14 = 14U, + INT_SRC_SWI_IRQ15 = 15U, + INT_SRC_SWI_IRQ16 = 16U, + INT_SRC_SWI_IRQ17 = 17U, + INT_SRC_SWI_IRQ18 = 18U, + INT_SRC_SWI_IRQ19 = 19U, + INT_SRC_SWI_IRQ20 = 20U, + INT_SRC_SWI_IRQ21 = 21U, + INT_SRC_SWI_IRQ22 = 22U, + INT_SRC_SWI_IRQ23 = 23U, + INT_SRC_SWI_IRQ24 = 24U, + INT_SRC_SWI_IRQ25 = 25U, + INT_SRC_SWI_IRQ26 = 26U, + INT_SRC_SWI_IRQ27 = 27U, + INT_SRC_SWI_IRQ28 = 28U, + INT_SRC_SWI_IRQ29 = 29U, + INT_SRC_SWI_IRQ30 = 30U, + INT_SRC_SWI_IRQ31 = 31U, + /* External Interrupt */ + INT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + INT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + INT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + INT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + INT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + INT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + INT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + INT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + INT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + INT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + INT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + INT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + INT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + INT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + INT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + INT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + /* DMA_1 */ + INT_SRC_DMA1_TC0 = 32U, /* DMA_1_TC0 */ + INT_SRC_DMA1_TC1 = 33U, /* DMA_1_TC1 */ + INT_SRC_DMA1_TC2 = 34U, /* DMA_1_TC2 */ + INT_SRC_DMA1_TC3 = 35U, /* DMA_1_TC3 */ + INT_SRC_DMA1_TC4 = 36U, /* DMA_1_TC4 */ + INT_SRC_DMA1_TC5 = 37U, /* DMA_1_TC5 */ + INT_SRC_DMA1_TC6 = 38U, /* DMA_1_TC6 */ + INT_SRC_DMA1_TC7 = 39U, /* DMA_1_TC7 */ + INT_SRC_DMA1_BTC0 = 40U, /* DMA_1_BTC0 */ + INT_SRC_DMA1_BTC1 = 41U, /* DMA_1_BTC1 */ + INT_SRC_DMA1_BTC2 = 42U, /* DMA_1_BTC2 */ + INT_SRC_DMA1_BTC3 = 43U, /* DMA_1_BTC3 */ + INT_SRC_DMA1_BTC4 = 44U, /* DMA_1_BTC4 */ + INT_SRC_DMA1_BTC5 = 45U, /* DMA_1_BTC5 */ + INT_SRC_DMA1_BTC6 = 46U, /* DMA_1_BTC6 */ + INT_SRC_DMA1_BTC7 = 47U, /* DMA_1_BTC7 */ + INT_SRC_DMA1_ERR = 48U, /* DMA_1_ERR */ + /* EFM */ + INT_SRC_EFM_PEERR = 49U, /* EFM_PEERR */ + INT_SRC_EFM_RDCOL = 50U, /* EFM_RDCOL */ + INT_SRC_EFM_OPTEND = 51U, /* EFM_OPTEND */ + /* QSPI */ + INT_SRC_QSPI_INTR = 54U, /* QSPI_INTR */ + /* DCU */ + INT_SRC_DCU1 = 55U, /* DCU1 */ + INT_SRC_DCU2 = 56U, /* DCU2 */ + INT_SRC_DCU3 = 57U, /* DCU3 */ + INT_SRC_DCU4 = 58U, /* DCU4 */ + INT_SRC_DCU5 = 59U, /* DCU5 */ + INT_SRC_DCU6 = 60U, /* DCU6 */ + INT_SRC_DCU7 = 61U, /* DCU7 */ + INT_SRC_DCU8 = 62U, /* DCU8 */ + /* DMA2 */ + INT_SRC_DMA2_TC0 = 64U, /* DMA_2_TC0 */ + INT_SRC_DMA2_TC1 = 65U, /* DMA_2_TC1 */ + INT_SRC_DMA2_TC2 = 66U, /* DMA_2_TC2 */ + INT_SRC_DMA2_TC3 = 67U, /* DMA_2_TC3 */ + INT_SRC_DMA2_TC4 = 68U, /* DMA_2_TC4 */ + INT_SRC_DMA2_TC5 = 69U, /* DMA_2_TC5 */ + INT_SRC_DMA2_TC6 = 70U, /* DMA_2_TC6 */ + INT_SRC_DMA2_TC7 = 71U, /* DMA_2_TC7 */ + INT_SRC_DMA2_BTC0 = 72U, /* DMA_2_BTC0 */ + INT_SRC_DMA2_BTC1 = 73U, /* DMA_2_BTC1 */ + INT_SRC_DMA2_BTC2 = 74U, /* DMA_2_BTC2 */ + INT_SRC_DMA2_BTC3 = 75U, /* DMA_2_BTC3 */ + INT_SRC_DMA2_BTC4 = 76U, /* DMA_2_BTC4 */ + INT_SRC_DMA2_BTC5 = 77U, /* DMA_2_BTC5 */ + INT_SRC_DMA2_BTC6 = 78U, /* DMA_2_BTC6 */ + INT_SRC_DMA2_BTC7 = 79U, /* DMA_2_BTC7 */ + INT_SRC_DMA2_ERR = 80U, /* DMA_2_ERR */ + /* MAU */ + INT_SRC_MAU_SQRT = 83U, /* MAU_SQRT */ + /* DVP */ + INT_SRC_DVP_FRAMSTA = 84U, /* DVP_FRAMSTA */ + INT_SRC_DVP_LINESTA = 85U, /* DVP_LINESTA */ + INT_SRC_DVP_LINEEND = 86U, /* DVP_LINEEND */ + INT_SRC_DVP_FRAMEND = 87U, /* DVP_FRAMEND */ + INT_SRC_DVP_SQUERR = 88U, /* DVP_SQUERR */ + INT_SRC_DVP_FIFOERR = 89U, /* DVP_FIFOERR */ + /* FMAC */ + INT_SRC_FMAC_1 = 91U, /* FMAC_1_FIR */ + INT_SRC_FMAC_2 = 92U, /* FMAC_2_FIR */ + INT_SRC_FMAC_3 = 93U, /* FMAC_3_FIR */ + INT_SRC_FMAC_4 = 94U, /* FMAC_4_FIR */ + /* TIMER0 */ + INT_SRC_TMR0_1_CMP_A = 96U, /* TMR0_1_CMPA */ + INT_SRC_TMR0_1_CMP_B = 97U, /* TMR0_1_CMPB */ + INT_SRC_TMR0_2_CMP_A = 98U, /* TMR0_2_CMPA */ + INT_SRC_TMR0_2_CMP_B = 99U, /* TMR0_2_CMPB */ + /* TIMER2 */ + INT_SRC_TMR2_1_CMP_A = 100U, /* TMR2_1_CMPA */ + INT_SRC_TMR2_1_CMP_B = 101U, /* TMR2_1_CMPB */ + INT_SRC_TMR2_1_OVF_A = 102U, /* TMR2_1_OVFA */ + INT_SRC_TMR2_1_OVF_B = 103U, /* TMR2_1_OVFB */ + INT_SRC_TMR2_2_CMP_A = 104U, /* TMR2_2_CMPA */ + INT_SRC_TMR2_2_CMP_B = 105U, /* TMR2_2_CMPB */ + INT_SRC_TMR2_2_OVF_A = 106U, /* TMR2_2_OVFA */ + INT_SRC_TMR2_2_OVF_B = 107U, /* TMR2_2_OVFB */ + INT_SRC_TMR2_3_CMP_A = 108U, /* TMR2_3_CMPA */ + INT_SRC_TMR2_3_CMP_B = 109U, /* TMR2_3_CMPB */ + INT_SRC_TMR2_3_OVF_A = 110U, /* TMR2_3_OVFA */ + INT_SRC_TMR2_3_OVF_B = 111U, /* TMR2_3_OVFB */ + INT_SRC_TMR2_4_CMP_A = 112U, /* TMR2_4_CMPA */ + INT_SRC_TMR2_4_CMP_B = 113U, /* TMR2_4_CMPB */ + INT_SRC_TMR2_4_OVF_A = 114U, /* TMR2_4_OVFA */ + INT_SRC_TMR2_4_OVF_B = 115U, /* TMR2_4_OVFB */ + /* RTC */ + INT_SRC_RTC_TP = 120U, /* RTC_TP */ + INT_SRC_RTC_ALM = 121U, /* RTC_ALM */ + INT_SRC_RTC_PRD = 122U, /* RTC_PRD */ + /* XTAL */ + INT_SRC_XTAL_STOP = 125U, /* XTAL_STOP */ + /* WKTM */ + INT_SRC_WKTM_PRD = 126U, /* WKTM_PRD */ + /* SWDT */ + INT_SRC_SWDT_REFUDF = 127U, /* SWDT_REFUDF */ + /* TIMER6_1 */ + INT_SRC_TMR6_1_GCMP_A = 128U, /* TMR6_1_GCMA */ + INT_SRC_TMR6_1_GCMP_B = 129U, /* TMR6_1_GCMB */ + INT_SRC_TMR6_1_GCMP_C = 130U, /* TMR6_1_GCMC */ + INT_SRC_TMR6_1_GCMP_D = 131U, /* TMR6_1_GCMD */ + INT_SRC_TMR6_1_GCMP_E = 132U, /* TMR6_1_GCME */ + INT_SRC_TMR6_1_GCMP_F = 133U, /* TMR6_1_GCMF */ + INT_SRC_TMR6_1_OVF = 134U, /* TMR6_1_GOVF */ + INT_SRC_TMR6_1_UDF = 135U, /* TMR6_1_GUDF */ + /* TIMER4_1 */ + INT_SRC_TMR4_1_GCMP_UH = 136U, /* TMR4_1_GCMUH */ + INT_SRC_TMR4_1_GCMP_UL = 137U, /* TMR4_1_GCMUL */ + INT_SRC_TMR4_1_GCMP_VH = 138U, /* TMR4_1_GCMVH */ + INT_SRC_TMR4_1_GCMP_VL = 139U, /* TMR4_1_GCMVL */ + INT_SRC_TMR4_1_GCMP_WH = 140U, /* TMR4_1_GCMWH */ + INT_SRC_TMR4_1_GCMP_WL = 141U, /* TMR4_1_GCMWL */ + INT_SRC_TMR4_1_OVF = 142U, /* TMR4_1_GOVF */ + INT_SRC_TMR4_1_UDF = 143U, /* TMR4_1_GUDF */ + /* TIMER6_2 */ + INT_SRC_TMR6_2_GCMP_A = 144U, /* TMR6_2_GCMA */ + INT_SRC_TMR6_2_GCMP_B = 145U, /* TMR6_2_GCMB */ + INT_SRC_TMR6_2_GCMP_C = 146U, /* TMR6_2_GCMC */ + INT_SRC_TMR6_2_GCMP_D = 147U, /* TMR6_2_GCMD */ + INT_SRC_TMR6_2_GCMP_E = 148U, /* TMR6_2_GCME */ + INT_SRC_TMR6_2_GCMP_F = 149U, /* TMR6_2_GCMF */ + INT_SRC_TMR6_2_OVF = 150U, /* TMR6_2_GOVF */ + INT_SRC_TMR6_2_UDF = 151U, /* TMR6_2_GUDF */ + /* TIMER4_2 */ + INT_SRC_TMR4_2_GCMP_UH = 152U, /* TMR4_2_GCMUH */ + INT_SRC_TMR4_2_GCMP_UL = 153U, /* TMR4_2_GCMUL */ + INT_SRC_TMR4_2_GCMP_VH = 154U, /* TMR4_2_GCMVH */ + INT_SRC_TMR4_2_GCMP_VL = 155U, /* TMR4_2_GCMVL */ + INT_SRC_TMR4_2_GCMP_WH = 156U, /* TMR4_2_GCMWH */ + INT_SRC_TMR4_2_GCMP_WL = 157U, /* TMR4_2_GCMWL */ + INT_SRC_TMR4_2_OVF = 158U, /* TMR4_2_GOVF */ + INT_SRC_TMR4_2_UDF = 159U, /* TMR4_2_GUDF */ + /* TIMER6_3 */ + INT_SRC_TMR6_3_GCMP_A = 160U, /* TMR6_3_GCMA */ + INT_SRC_TMR6_3_GCMP_B = 161U, /* TMR6_3_GCMB */ + INT_SRC_TMR6_3_GCMP_C = 162U, /* TMR6_3_GCMC */ + INT_SRC_TMR6_3_GCMP_D = 163U, /* TMR6_3_GCMD */ + INT_SRC_TMR6_3_GCMP_E = 164U, /* TMR6_3_GCME */ + INT_SRC_TMR6_3_GCMP_F = 165U, /* TMR6_3_GCMF */ + INT_SRC_TMR6_3_OVF = 166U, /* TMR6_3_GOVF */ + INT_SRC_TMR6_3_UDF = 167U, /* TMR6_3_GUDF */ + /* TIMER4_3 */ + INT_SRC_TMR4_3_GCMP_UH = 168U, /* TMR4_3_GCMUH */ + INT_SRC_TMR4_3_GCMP_UL = 169U, /* TMR4_3_GCMUL */ + INT_SRC_TMR4_3_GCMP_VH = 170U, /* TMR4_3_GCMVH */ + INT_SRC_TMR4_3_GCMP_VL = 171U, /* TMR4_3_GCMVL */ + INT_SRC_TMR4_3_GCMP_WH = 172U, /* TMR4_3_GCMWH */ + INT_SRC_TMR4_3_GCMP_WL = 173U, /* TMR4_3_GCMWL */ + INT_SRC_TMR4_3_OVF = 174U, /* TMR4_3_GOVF */ + INT_SRC_TMR4_3_UDF = 175U, /* TMR4_3_GUDF */ + /* TIMER6_1 */ + INT_SRC_TMR6_1_DTE = 176U, /* TMR6_1_GDTE */ + INT_SRC_TMR6_1_SCMP_A = 179U, /* TMR6_1_SCMA */ + INT_SRC_TMR6_1_SCMP_B = 180U, /* TMR6_1_SCMB */ + /* TIMER4_1 */ + INT_SRC_TMR4_1_RELOAD_U = 181U, /* TMR4_1_RLOU */ + INT_SRC_TMR4_1_RELOAD_V = 182U, /* TMR4_1_RLOV */ + INT_SRC_TMR4_1_RELOAD_W = 183U, /* TMR4_1_RLOW */ + /* TIMER6_2 */ + INT_SRC_TMR6_2_DTE = 184U, /* TMR6_2_GDTE */ + INT_SRC_TMR6_2_SCMP_A = 187U, /* TMR6_2_SCMA */ + INT_SRC_TMR6_2_SCMP_B = 188U, /* TMR6_2_SCMB */ + /* TIMER4_2 */ + INT_SRC_TMR4_2_RELOAD_U = 189U, /* TMR4_2_RLOU */ + INT_SRC_TMR4_2_RELOAD_V = 190U, /* TMR4_2_RLOV */ + INT_SRC_TMR4_2_RELOAD_W = 191U, /* TMR4_2_RLOW */ + /* TIMER6_3 */ + INT_SRC_TMR6_3_DTE = 192U, /* TMR6_3_GDTE */ + INT_SRC_TMR6_3_SCMP_A = 195U, /* TMR6_3_SCMA */ + INT_SRC_TMR6_3_SCMP_B = 196U, /* TMR6_3_SCMB */ + /* TIMER4_3 */ + INT_SRC_TMR4_3_RELOAD_U = 197U, /* TMR4_3_RLOU */ + INT_SRC_TMR4_3_RELOAD_V = 198U, /* TMR4_3_RLOV */ + INT_SRC_TMR4_3_RELOAD_W = 199U, /* TMR4_3_RLOW */ + /* TIMER6_4 TIMER6_5 */ + INT_SRC_TMR6_4_GCMP_A = 208U, /* TMR6_4_GCMA */ + INT_SRC_TMR6_4_GCMP_B = 209U, /* TMR6_4_GCMB */ + INT_SRC_TMR6_4_GCMP_C = 210U, /* TMR6_4_GCMC */ + INT_SRC_TMR6_4_GCMP_D = 211U, /* TMR6_4_GCMD */ + INT_SRC_TMR6_4_GCMP_E = 212U, /* TMR6_4_GCME */ + INT_SRC_TMR6_4_GCMP_F = 213U, /* TMR6_4_GCMF */ + INT_SRC_TMR6_4_OVF = 214U, /* TMR6_4_GOVF */ + INT_SRC_TMR6_4_UDF = 215U, /* TMR6_4_GUDF */ + INT_SRC_TMR6_4_DTE = 216U, /* TMR6_4_GDTE */ + INT_SRC_TMR6_4_SCMP_A = 219U, /* TMR6_4_SCMA */ + INT_SRC_TMR6_4_SCMP_B = 220U, /* TMR6_4_SCMB */ + INT_SRC_TMR6_5_GCMP_A = 224U, /* TMR6_5_GCMA */ + INT_SRC_TMR6_5_GCMP_B = 225U, /* TMR6_5_GCMB */ + INT_SRC_TMR6_5_GCMP_C = 226U, /* TMR6_5_GCMC */ + INT_SRC_TMR6_5_GCMP_D = 227U, /* TMR6_5_GCMD */ + INT_SRC_TMR6_5_GCMP_E = 228U, /* TMR6_5_GCME */ + INT_SRC_TMR6_5_GCMP_F = 229U, /* TMR6_5_GCMF */ + INT_SRC_TMR6_5_OVF = 230U, /* TMR6_5_GOVF */ + INT_SRC_TMR6_5_UDF = 231U, /* TMR6_5_GUDF */ + INT_SRC_TMR6_5_DTE = 232U, /* TMR6_5_GDTE */ + INT_SRC_TMR6_5_SCMP_A = 235U, /* TMR6_5_SCMA */ + INT_SRC_TMR6_5_SCMP_B = 236U, /* TMR6_5_SCMB */ + /* TIMERA_1 */ + INT_SRC_TMRA_1_OVF = 237U, /* TMRA_1_OVF */ + INT_SRC_TMRA_1_UDF = 238U, /* TMRA_1_UDF */ + INT_SRC_TMRA_1_CMP = 239U, /* TMRA_1_CMP */ + /* TIMER6_6 */ + INT_SRC_TMR6_6_GCMP_A = 240U, /* TMR6_6_GCMA */ + INT_SRC_TMR6_6_GCMP_B = 241U, /* TMR6_6_GCMB */ + INT_SRC_TMR6_6_GCMP_C = 242U, /* TMR6_6_GCMC */ + INT_SRC_TMR6_6_GCMP_D = 243U, /* TMR6_6_GCMD */ + INT_SRC_TMR6_6_GCMP_E = 244U, /* TMR6_6_GCME */ + INT_SRC_TMR6_6_GCMP_F = 245U, /* TMR6_6_GCMF */ + INT_SRC_TMR6_6_OVF = 246U, /* TMR6_6_GOVF */ + INT_SRC_TMR6_6_UDF = 247U, /* TMR6_6_GUDF */ + INT_SRC_TMR6_6_DTE = 248U, /* TMR6_6_GDTE */ + INT_SRC_TMR6_6_SCMP_A = 251U, /* TMR6_6_SCMA */ + INT_SRC_TMR6_6_SCMP_B = 252U, /* TMR6_6_SCMB */ + /* TIMERA_2 */ + INT_SRC_TMRA_2_OVF = 253U, /* TMRA_2_OVF */ + INT_SRC_TMRA_2_UDF = 254U, /* TMRA_2_UDF */ + INT_SRC_TMRA_2_CMP = 255U, /* TMRA_2_CMP */ + /* TIMER6_7 */ + INT_SRC_TMR6_7_GCMP_A = 256U, /* TMR6_7_GCMA */ + INT_SRC_TMR6_7_GCMP_B = 257U, /* TMR6_7_GCMB */ + INT_SRC_TMR6_7_GCMP_C = 258U, /* TMR6_7_GCMC */ + INT_SRC_TMR6_7_GCMP_D = 259U, /* TMR6_7_GCMD */ + INT_SRC_TMR6_7_GCMP_E = 260U, /* TMR6_7_GCME */ + INT_SRC_TMR6_7_GCMP_F = 261U, /* TMR6_7_GCMF */ + INT_SRC_TMR6_7_OVF = 262U, /* TMR6_7_GOVF */ + INT_SRC_TMR6_7_UDF = 263U, /* TMR6_7_GUDF */ + INT_SRC_TMR6_7_DTE = 264U, /* TMR6_7_GDTE */ + INT_SRC_TMR6_7_SCMP_A = 267U, /* TMR6_7_SCMA */ + INT_SRC_TMR6_7_SCMP_B = 268U, /* TMR6_7_SCMB */ + /* TIMERA_3 */ + INT_SRC_TMRA_3_OVF = 269U, /* TMRA_3_OVF */ + INT_SRC_TMRA_3_UDF = 270U, /* TMRA_3_UDF */ + INT_SRC_TMRA_3_CMP = 271U, /* TMRA_3_CMP */ + /* TIMER6_8 */ + INT_SRC_TMR6_8_GCMP_A = 272U, /* TMR6_8_GCMA */ + INT_SRC_TMR6_8_GCMP_B = 273U, /* TMR6_8_GCMB */ + INT_SRC_TMR6_8_GCMP_C = 274U, /* TMR6_8_GCMC */ + INT_SRC_TMR6_8_GCMP_D = 275U, /* TMR6_8_GCMD */ + INT_SRC_TMR6_8_GCMP_E = 276U, /* TMR6_8_GCME */ + INT_SRC_TMR6_8_GCMP_F = 277U, /* TMR6_8_GCMF */ + INT_SRC_TMR6_8_OVF = 278U, /* TMR6_8_GOVF */ + INT_SRC_TMR6_8_UDF = 279U, /* TMR6_8_GUDF */ + INT_SRC_TMR6_8_DTE = 280U, /* TMR6_8_GDTE */ + INT_SRC_TMR6_8_SCMP_A = 283U, /* TMR6_8_SCMA */ + INT_SRC_TMR6_8_SCMP_B = 284U, /* TMR6_8_SCMB */ + /* TIMERA_4 */ + INT_SRC_TMRA_4_OVF = 285U, /* TMRA_4_OVF */ + INT_SRC_TMRA_4_UDF = 286U, /* TMRA_4_UDF */ + INT_SRC_TMRA_4_CMP = 287U, /* TMRA_4_CMP */ + /* EMB */ + INT_SRC_EMB_GR0 = 288U, /* EMB_GR0 */ + INT_SRC_EMB_GR1 = 289U, /* EMB_GR1 */ + INT_SRC_EMB_GR2 = 290U, /* EMB_GR2 */ + INT_SRC_EMB_GR3 = 291U, /* EMB_GR3 */ + INT_SRC_EMB_GR4 = 292U, /* EMB_GR4 */ + INT_SRC_EMB_GR5 = 293U, /* EMB_GR5 */ + INT_SRC_EMB_GR6 = 294U, /* EMB_GR6 */ + /* USBHS */ + INT_SRC_USBHS_EP1_OUT = 295U, /* USBHS_EP1_OUT */ + INT_SRC_USBHS_EP1_IN = 296U, /* USBHS_EP1_IN */ + INT_SRC_USBHS_GLB = 297U, /* USBHS_GLB */ + INT_SRC_USBHS_WKUP = 298U, /* USBHS_WKUP */ + /* USART1 USART2 */ + INT_SRC_USART1_EI = 300U, /* USART_1_EI */ + INT_SRC_USART1_RI = 301U, /* USART_1_RI */ + INT_SRC_USART1_TI = 302U, /* USART_1_TI */ + INT_SRC_USART1_TCI = 303U, /* USART_1_TCI */ + INT_SRC_USART1_RTO = 304U, /* USART_1_RTO */ + INT_SRC_USART2_EI = 305U, /* USART_2_EI */ + INT_SRC_USART2_RI = 306U, /* USART_2_RI */ + INT_SRC_USART2_TI = 307U, /* USART_2_TI */ + INT_SRC_USART2_TCI = 308U, /* USART_2_TCI */ + INT_SRC_USART2_RTO = 309U, /* USART_2_RTO */ + /* SPI1 SPI2 */ + INT_SRC_SPI1_SPRI = 310U, /* SPI_1_SPRI */ + INT_SRC_SPI1_SPTI = 311U, /* SPI_1_SPTI */ + INT_SRC_SPI1_SPII = 312U, /* SPI_1_SPII */ + INT_SRC_SPI1_SPEI = 313U, /* SPI_1_SPEI */ + INT_SRC_SPI2_SPRI = 315U, /* SPI_2_SPRI */ + INT_SRC_SPI2_SPTI = 316U, /* SPI_2_SPTI */ + INT_SRC_SPI2_SPII = 317U, /* SPI_2_SPII */ + INT_SRC_SPI2_SPEI = 318U, /* SPI_2_SPEI */ + /* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */ + INT_SRC_TMRA_5_OVF = 320U, /* TMRA_5_OVF */ + INT_SRC_TMRA_5_UDF = 321U, /* TMRA_5_UDF */ + INT_SRC_TMRA_5_CMP = 322U, /* TMRA_5_CMP */ + INT_SRC_TMRA_6_OVF = 323U, /* TMRA_6_OVF */ + INT_SRC_TMRA_6_UDF = 324U, /* TMRA_6_UDF */ + INT_SRC_TMRA_6_CMP = 325U, /* TMRA_6_CMP */ + INT_SRC_TMRA_7_OVF = 326U, /* TMRA_7_OVF */ + INT_SRC_TMRA_7_UDF = 327U, /* TMRA_7_UDF */ + INT_SRC_TMRA_7_CMP = 328U, /* TMRA_7_CMP */ + INT_SRC_TMRA_8_OVF = 329U, /* TMRA_8_OVF */ + INT_SRC_TMRA_8_UDF = 330U, /* TMRA_8_UDF */ + INT_SRC_TMRA_8_CMP = 331U, /* TMRA_8_CMP */ + /* USART3 USART4 */ + INT_SRC_USART3_EI = 332U, /* USART_3_EI */ + INT_SRC_USART3_RI = 333U, /* USART_3_RI */ + INT_SRC_USART3_TI = 334U, /* USART_3_TI */ + INT_SRC_USART3_TCI = 335U, /* USART_3_TCI */ + INT_SRC_USART4_EI = 336U, /* USART_4_EI */ + INT_SRC_USART4_RI = 337U, /* USART_4_RI */ + INT_SRC_USART4_TI = 338U, /* USART_4_TI */ + INT_SRC_USART4_TCI = 339U, /* USART_4_TCI */ + /* CAN1 CAN2 */ + INT_SRC_CAN1_HOST = 340U, /* CAN_1_HOST */ + INT_SRC_CAN2_HOST = 341U, /* CAN_2_HOST */ + /* SPI3 SPI4 */ + INT_SRC_SPI3_SPRI = 342U, /* SPI_3_SPRI */ + INT_SRC_SPI3_SPTI = 343U, /* SPI_3_SPTI */ + INT_SRC_SPI3_SPII = 344U, /* SPI_3_SPII */ + INT_SRC_SPI3_SPEI = 345U, /* SPI_3_SPEI */ + INT_SRC_SPI4_SPRI = 347U, /* SPI_4_SPRI */ + INT_SRC_SPI4_SPTI = 348U, /* SPI_4_SPTI */ + INT_SRC_SPI4_SPII = 349U, /* SPI_4_SPII */ + INT_SRC_SPI4_SPEI = 350U, /* SPI_4_SPEI */ + /* TIMERA_9 TIMERA_10 TIMER_11 TIMER_12 */ + INT_SRC_TMRA_9_OVF = 352U, /* TMRA_9_OVF */ + INT_SRC_TMRA_9_UDF = 353U, /* TMRA_9_UDF */ + INT_SRC_TMRA_9_CMP = 354U, /* TMRA_9_CMP */ + INT_SRC_TMRA_10_OVF = 355U, /* TMRA_10_OVF */ + INT_SRC_TMRA_10_UDF = 356U, /* TMRA_10_UDF */ + INT_SRC_TMRA_10_CMP = 357U, /* TMRA_10_CMP */ + INT_SRC_TMRA_11_OVF = 358U, /* TMRA_11_OVF */ + INT_SRC_TMRA_11_UDF = 359U, /* TMRA_11_UDF */ + INT_SRC_TMRA_11_CMP = 360U, /* TMRA_11_CMP */ + INT_SRC_TMRA_12_OVF = 361U, /* TMRA_12_OVF */ + INT_SRC_TMRA_12_UDF = 362U, /* TMRA_12_UDF */ + INT_SRC_TMRA_12_CMP = 363U, /* TMRA_12_CMP */ + /* USART5 USART6 */ + INT_SRC_USART5_BRKWKPI = 364U, /* USART_5_BRKWKPI */ + INT_SRC_USART5_EI = 365U, /* USART_5_EI */ + INT_SRC_USART5_RI = 366U, /* USART_5_RI */ + INT_SRC_USART5_TI = 367U, /* USART_5_TI */ + INT_SRC_USART5_TCI = 368U, /* USART_5_TCI */ + INT_SRC_USART6_EI = 369U, /* USART_6_EI */ + INT_SRC_USART6_RI = 370U, /* USART_6_RI */ + INT_SRC_USART6_TI = 371U, /* USART_6_TI */ + INT_SRC_USART6_TCI = 372U, /* USART_6_TCI */ + INT_SRC_USART6_RTO = 373U, /* USART_6_RTO */ + /* SPI5 SPI6 */ + INT_SRC_SPI5_SPRI = 374U, /* SPI_5_SPRI */ + INT_SRC_SPI5_SPTI = 375U, /* SPI_5_SPTI */ + INT_SRC_SPI5_SPII = 376U, /* SPI_5_SPII */ + INT_SRC_SPI5_SPEI = 377U, /* SPI_5_SPEI */ + INT_SRC_SPI6_SPRI = 379U, /* SPI_6_SPRI */ + INT_SRC_SPI6_SPTI = 380U, /* SPI_6_SPTI */ + INT_SRC_SPI6_SPII = 381U, /* SPI_6_SPII */ + INT_SRC_SPI6_SPEI = 382U, /* SPI_6_SPEI */ + /* I2S1 I2S2 */ + INT_SRC_I2S1_TXIRQOUT = 384U, /* I2S_1_TXIRQOUT */ + INT_SRC_I2S1_RXIRQOUT = 385U, /* I2S_1_RXIRQOUT */ + INT_SRC_I2S1_ERRIRQOUT = 386U, /* I2S_1_ERRIRQOUT */ + INT_SRC_I2S2_TXIRQOUT = 387U, /* I2S_2_TXIRQOUT */ + INT_SRC_I2S2_RXIRQOUT = 388U, /* I2S_2_RXIRQOUT */ + INT_SRC_I2S2_ERRIRQOUT = 389U, /* I2S_2_ERRIRQOUT */ + /* USART7 USART8 */ + INT_SRC_USART7_EI = 390U, /* USART_7_EI */ + INT_SRC_USART7_RI = 391U, /* USART_7_RI */ + INT_SRC_USART7_TI = 392U, /* USART_7_TI */ + INT_SRC_USART7_TCI = 393U, /* USART_7_TCI */ + INT_SRC_USART7_RTO = 394U, /* USART_7_RTO */ + INT_SRC_USART8_EI = 395U, /* USART_8_EI */ + INT_SRC_USART8_RI = 396U, /* USART_8_RI */ + INT_SRC_USART8_TI = 397U, /* USART_8_TI */ + INT_SRC_USART8_TCI = 398U, /* USART_8_TCI */ + /* USBFS */ + INT_SRC_USBFS_GLB = 399U, /* USBFS_GLB */ + INT_SRC_USBFS_WKUP = 400U, /* USBFS_WKUP */ + /* HASH */ + INT_SRC_HASH = 401U, /* HASH_INT */ + /* SDIOC */ + INT_SRC_SDIOC1_SD = 404U, /* SDIOC_1_SD */ + INT_SRC_SDIOC2_SD = 407U, /* SDIOC_2_SD */ + /* EVENT PORT */ + INT_SRC_EVENT_PORT1 = 408U, /* EVENT_PORT1 */ + INT_SRC_EVENT_PORT2 = 409U, /* EVENT_PORT2 */ + INT_SRC_EVENT_PORT3 = 410U, /* EVENT_PORT3 */ + INT_SRC_EVENT_PORT4 = 411U, /* EVENT_PORT4 */ + /* ETHER */ + INT_SRC_ETH_GLB_INT = 412U, /* ETH_GLB_INT */ + INT_SRC_ETH_WKP_INT = 413U, /* ETH_WKP_INT */ + /* I2S3 I2S4 */ + INT_SRC_I2S3_TXIRQOUT = 416U, /* I2S_3_TXIRQOUT */ + INT_SRC_I2S3_RXIRQOUT = 417U, /* I2S_3_RXIRQOUT */ + INT_SRC_I2S3_ERRIRQOUT = 418U, /* I2S_3_ERRIRQOUT */ + INT_SRC_I2S4_TXIRQOUT = 419U, /* I2S_4_TXIRQOUT */ + INT_SRC_I2S4_RXIRQOUT = 420U, /* I2S_4_RXIRQOUT */ + INT_SRC_I2S4_ERRIRQOUT = 421U, /* I2S_4_ERRIRQOUT */ + /* USART9 USART10 */ + INT_SRC_USART9_EI = 422U, /* USART_9_EI */ + INT_SRC_USART9_RI = 423U, /* USART_9_RI */ + INT_SRC_USART9_TI = 424U, /* USART_9_TI */ + INT_SRC_USART9_TCI = 425U, /* USART_9_TCI */ + INT_SRC_USART10_BRKWKPI = 426U, /* USART_10_BRKWKPI */ + INT_SRC_USART10_EI = 427U, /* USART_10_EI */ + INT_SRC_USART10_RI = 428U, /* USART_10_RI */ + INT_SRC_USART10_TI = 429U, /* USART_10_TI */ + INT_SRC_USART10_TCI = 430U, /* USART_10_TCI */ + /* I2C1 I2C2 I2C3 */ + INT_SRC_I2C1_RXI = 432U, /* I2C_1_RXI */ + INT_SRC_I2C1_TXI = 433U, /* I2C_1_TXI */ + INT_SRC_I2C1_TEI = 434U, /* I2C_1_TEI */ + INT_SRC_I2C1_EEI = 435U, /* I2C_1_EEI */ + INT_SRC_I2C2_RXI = 436U, /* I2C_2_RXI */ + INT_SRC_I2C2_TXI = 437U, /* I2C_2_TXI */ + INT_SRC_I2C2_TEI = 438U, /* I2C_2_TEI */ + INT_SRC_I2C2_EEI = 439U, /* I2C_2_EEI */ + INT_SRC_I2C3_RXI = 440U, /* I2C_3_RXI */ + INT_SRC_I2C3_TXI = 441U, /* I2C_3_TXI */ + INT_SRC_I2C3_TEI = 442U, /* I2C_3_TEI */ + INT_SRC_I2C3_EEI = 443U, /* I2C_3_EEI */ + /* ACMP */ + INT_SRC_CMP1 = 444U, /* CMP1 */ + INT_SRC_CMP2 = 445U, /* CMP2 */ + INT_SRC_CMP3 = 446U, /* CMP3 */ + INT_SRC_CMP4 = 447U, /* CMP4 */ + /* I2C4 I2C5 I2C6 */ + INT_SRC_I2C4_RXI = 448U, /* I2C_4_RXI */ + INT_SRC_I2C4_TXI = 449U, /* I2C_4_TXI */ + INT_SRC_I2C4_TEI = 450U, /* I2C_4_TEI */ + INT_SRC_I2C4_EEI = 451U, /* I2C_4_EEI */ + INT_SRC_I2C5_RXI = 452U, /* I2C_5_RXI */ + INT_SRC_I2C5_TXI = 453U, /* I2C_5_TXI */ + INT_SRC_I2C5_TEI = 454U, /* I2C_5_TEI */ + INT_SRC_I2C5_EEI = 455U, /* I2C_5_EEI */ + INT_SRC_I2C6_RXI = 456U, /* I2C_6_RXI */ + INT_SRC_I2C6_TXI = 457U, /* I2C_6_TXI */ + INT_SRC_I2C6_TEI = 458U, /* I2C_6_TEI */ + INT_SRC_I2C6_EEI = 459U, /* I2C_6_EEI */ + /* USART1 */ + INT_SRC_USART1_WUPI = 460U, /* USART_1_WUPI */ + /* LVD */ + INT_SRC_LVD1 = 461U, /* LVD1 */ + INT_SRC_LVD2 = 462U, /* LVD2 */ + /* OTS */ + INT_SRC_OTS = 463U, /* OTS */ + /* FCM */ + INT_SRC_FCMFERRI = 464U, /* FCMFERRI */ + INT_SRC_FCMMENDI = 465U, /* FCMMENDI */ + INT_SRC_FCMCOVFI = 466U, /* FCMCOVFI */ + /* WDT */ + INT_SRC_WDT_REFUDF = 467U, /* WDT_REFUDF */ + /* CTC */ + INT_SRC_CTC_ERR = 468U, /* CTC_ERR */ + /* ADC */ + INT_SRC_ADC1_EOCA = 480U, /* ADC_1_EOCA */ + INT_SRC_ADC1_EOCB = 481U, /* ADC_1_EOCB */ + INT_SRC_ADC1_CMP0 = 482U, /* ADC_1_CMP0 */ + INT_SRC_ADC1_CMP1 = 483U, /* ADC_1_CMP1 */ + INT_SRC_ADC2_EOCA = 484U, /* ADC_2_EOCA */ + INT_SRC_ADC2_EOCB = 485U, /* ADC_2_EOCB */ + INT_SRC_ADC2_CMP0 = 486U, /* ADC_2_CMP0 */ + INT_SRC_ADC2_CMP1 = 487U, /* ADC_2_CMP1 */ + INT_SRC_ADC3_EOCA = 488U, /* ADC_3_EOCA */ + INT_SRC_ADC3_EOCB = 489U, /* ADC_3_EOCB */ + INT_SRC_ADC3_CMP0 = 490U, /* ADC_3_CMP0 */ + INT_SRC_ADC3_CMP1 = 491U, /* ADC_3_CMP1 */ + /* TRNG */ + INT_SRC_TRNG_END = 492U, /* TRNG_END */ + /* NFC */ + INT_SRC_NFC_INT = 496U, /* NFC_INT */ + INT_SRC_MAX = 511U, +} en_int_src_t; + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +/** + * @brief ADC + */ +typedef struct { + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + uint8_t RESERVED1[4]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + __IO uint8_t EXCHSELR; + uint8_t RESERVED2[1]; + __IO uint16_t SHCR; + uint8_t RESERVED3[4]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED4[7]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED5[4]; + __I uint8_t ISR; + __IO uint8_t ICR; + __IO uint8_t ISCLRR; + uint8_t RESERVED6[5]; + __IO uint16_t SYNCCR; + uint8_t RESERVED7[2]; + __I uint16_t DR0; + __I uint16_t DR1; + __I uint16_t DR2; + __I uint16_t DR3; + __I uint16_t DR4; + __I uint16_t DR5; + __I uint16_t DR6; + __I uint16_t DR7; + __I uint16_t DR8; + __I uint16_t DR9; + __I uint16_t DR10; + __I uint16_t DR11; + __I uint16_t DR12; + __I uint16_t DR13; + __I uint16_t DR14; + __I uint16_t DR15; + __I uint16_t DR16; + __I uint16_t DR17; + __I uint16_t DR18; + __I uint16_t DR19; + uint8_t RESERVED8[40]; + __IO uint16_t AWDCR; + __I uint8_t AWDSR; + __IO uint8_t AWDSCLRR; + __IO uint16_t AWD0DR0; + __IO uint16_t AWD0DR1; + __IO uint8_t AWD0CHSR; + uint8_t RESERVED9[3]; + __IO uint16_t AWD1DR0; + __IO uint16_t AWD1DR1; + __IO uint8_t AWD1CHSR; + uint8_t RESERVED10[15]; + __IO uint8_t PGACR1; + __IO uint8_t PGACR2; + __IO uint8_t PGACR3; + uint8_t RESERVED11[1]; + __IO uint8_t PGAVSSENR; +} CM_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; + __IO uint32_t KR4; + __IO uint32_t KR5; + __IO uint32_t KR6; + __IO uint32_t KR7; +} CM_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct { + __O uint32_t INTSFTTRG; + __IO uint32_t DCU_TRGSEL1; + __IO uint32_t DCU_TRGSEL2; + __IO uint32_t DCU_TRGSEL3; + __IO uint32_t DCU_TRGSEL4; + __IO uint32_t DMA1_TRGSEL0; + __IO uint32_t DMA1_TRGSEL1; + __IO uint32_t DMA1_TRGSEL2; + __IO uint32_t DMA1_TRGSEL3; + __IO uint32_t DMA1_TRGSEL4; + __IO uint32_t DMA1_TRGSEL5; + __IO uint32_t DMA1_TRGSEL6; + __IO uint32_t DMA1_TRGSEL7; + __IO uint32_t DMA2_TRGSEL0; + __IO uint32_t DMA2_TRGSEL1; + __IO uint32_t DMA2_TRGSEL2; + __IO uint32_t DMA2_TRGSEL3; + __IO uint32_t DMA2_TRGSEL4; + __IO uint32_t DMA2_TRGSEL5; + __IO uint32_t DMA2_TRGSEL6; + __IO uint32_t DMA2_TRGSEL7; + __IO uint32_t DMA_TRGSELRC; + __IO uint32_t TMR6_HTSSR0; + __IO uint32_t TMR6_HTSSR1; + __IO uint32_t TMR6_HTSSR2; + __IO uint32_t TMR6_HTSSR3; + __IO uint32_t PEVNTTRGSR12; + __IO uint32_t PEVNTTRGSR34; + __IO uint32_t TMR0_HTSSR; + __IO uint32_t TMR2_HTSSR; + __IO uint32_t HASH_ITRGSELA; + __IO uint32_t HASH_ITRGSELB; + __IO uint32_t TMRA_HTSSR0; + __IO uint32_t TMRA_HTSSR1; + __IO uint32_t TMRA_HTSSR2; + __IO uint32_t TMRA_HTSSR3; + __IO uint32_t OTS_TRG; + __IO uint32_t ADC1_ITRGSELR0; + __IO uint32_t ADC1_ITRGSELR1; + __IO uint32_t ADC2_ITRGSELR0; + __IO uint32_t ADC2_ITRGSELR1; + __IO uint32_t ADC3_ITRGSELR0; + __IO uint32_t ADC3_ITRGSELR1; + __IO uint32_t COMTRG1; + __IO uint32_t COMTRG2; + uint8_t RESERVED0[76]; + __IO uint32_t PEVNTDIRR1; + __I uint32_t PEVNTIDR1; + __IO uint32_t PEVNTODR1; + __IO uint32_t PEVNTORR1; + __IO uint32_t PEVNTOSR1; + __IO uint32_t PEVNTRISR1; + __IO uint32_t PEVNTFAL1; + __IO uint32_t PEVNTDIRR2; + __I uint32_t PEVNTIDR2; + __IO uint32_t PEVNTODR2; + __IO uint32_t PEVNTORR2; + __IO uint32_t PEVNTOSR2; + __IO uint32_t PEVNTRISR2; + __IO uint32_t PEVNTFAL2; + __IO uint32_t PEVNTDIRR3; + __I uint32_t PEVNTIDR3; + __IO uint32_t PEVNTODR3; + __IO uint32_t PEVNTORR3; + __IO uint32_t PEVNTOSR3; + __IO uint32_t PEVNTRISR3; + __IO uint32_t PEVNTFAL3; + __IO uint32_t PEVNTDIRR4; + __I uint32_t PEVNTIDR4; + __IO uint32_t PEVNTODR4; + __IO uint32_t PEVNTORR4; + __IO uint32_t PEVNTOSR4; + __IO uint32_t PEVNTRISR4; + __IO uint32_t PEVNTFAL4; + __IO uint32_t PEVNTNFCR; +} CM_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct { + __I uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + __IO uint8_t CFG_STAT; + __IO uint8_t TCMD; + __IO uint8_t TCTRL; + __IO uint8_t RCTRL; + __IO uint8_t RTIE; + __IO uint8_t RTIF; + __IO uint8_t ERRINT; + __IO uint8_t LIMIT; + __IO uint32_t SBT; + __IO uint32_t FBT; + __I uint8_t EALCAP; + __IO uint8_t TDC; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + __IO uint8_t ACFCTRL; + uint8_t RESERVED2[1]; + __IO uint16_t ACFEN; + __IO uint32_t ACF; + uint8_t RESERVED3[2]; + __IO uint8_t TBSLOT; + __IO uint8_t TTCFG; + __IO uint32_t REF_MSG; + __IO uint16_t TRG_CFG; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} CM_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct { + __IO uint8_t MDR; + __IO uint8_t FIR; + __IO uint8_t OCR; + __IO uint8_t PMSR; + __IO uint16_t TWSR; + __IO uint16_t TWPR; + __IO uint16_t VISR; +} CM_CMP_TypeDef; + +/** + * @brief CMU + */ +typedef struct { + __IO uint8_t XTAL32CR; + uint8_t RESERVED0[3]; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED1[15]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED2[7]; + __IO uint8_t LRCCR; + uint8_t RESERVED3[3]; + __IO uint8_t RTCLRCCR; + uint8_t RESERVED4[3]; + __IO uint8_t LRCTRM; + uint8_t RESERVED5[7]; + __IO uint8_t RTCLRCTRM; + uint8_t RESERVED6[2123]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED7[29591]; + __IO uint16_t PERICKSEL; + __IO uint16_t I2SCKSEL; + uint8_t RESERVED8[4]; + __IO uint8_t CANCKCFGR; + uint8_t RESERVED9[7]; + __IO uint32_t SCFGR; + __IO uint8_t USBCKCFGR; + uint8_t RESERVED10[1]; + __IO uint8_t CKSWR; + uint8_t RESERVED11[3]; + __IO uint8_t PLLHCR; + uint8_t RESERVED12[3]; + __IO uint8_t PLLACR; + uint8_t RESERVED13[3]; + __IO uint8_t XTALCR; + uint8_t RESERVED14[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED15[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED16[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCOCFGR1; + __IO uint8_t MCOCFGR2; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED17[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED18[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED19[93]; + __IO uint32_t PLLHCFGR; + __IO uint32_t PLLACFGR; +} CM_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[120]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +} CM_CRC_TypeDef; + +/** + * @brief CTC + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __I uint32_t STR; +} CM_CTC_TypeDef; + +/** + * @brief DAC + */ +typedef struct { + __IO uint16_t DADR1; + __IO uint16_t DADR2; + __IO uint16_t DACR; + __IO uint16_t DAADPCR; + uint8_t RESERVED0[20]; + __IO uint16_t DAOCR; +} CM_DAC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct { + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + __IO uint32_t MCUSTAT; + __IO uint32_t MCUCTL; + __IO uint32_t FMCCTL; + __IO uint32_t MCUDBGCSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; + __IO uint32_t MCUSTPCTL2; +} CM_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct { + __IO uint32_t CTL; + __I uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __O uint32_t FLAGCLR; + __IO uint32_t INTSEL; +} CM_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct { + __IO uint32_t EN; + __I uint32_t INTSTAT0; + __I uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __IO uint32_t INTCLR0; + __IO uint32_t INTCLR1; + __IO uint32_t CHEN; + __I uint32_t REQSTAT; + __I uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + uint8_t RESERVED1[4]; + __IO uint32_t CHENCLR; + uint8_t RESERVED2[8]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __I uint32_t MONSAR0; + __I uint32_t MONDAR0; + __I uint32_t MONDTCTL0; + __I uint32_t MONRPT0; + __I uint32_t MONSNSEQCTL0; + __I uint32_t MONDNSEQCTL0; + uint8_t RESERVED3[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __I uint32_t MONSAR1; + __I uint32_t MONDAR1; + __I uint32_t MONDTCTL1; + __I uint32_t MONRPT1; + __I uint32_t MONSNSEQCTL1; + __I uint32_t MONDNSEQCTL1; + uint8_t RESERVED4[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __I uint32_t MONSAR2; + __I uint32_t MONDAR2; + __I uint32_t MONDTCTL2; + __I uint32_t MONRPT2; + __I uint32_t MONSNSEQCTL2; + __I uint32_t MONDNSEQCTL2; + uint8_t RESERVED5[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __I uint32_t MONSAR3; + __I uint32_t MONDAR3; + __I uint32_t MONDTCTL3; + __I uint32_t MONRPT3; + __I uint32_t MONSNSEQCTL3; + __I uint32_t MONDNSEQCTL3; + uint8_t RESERVED6[8]; + __IO uint32_t SAR4; + __IO uint32_t DAR4; + __IO uint32_t DTCTL4; + union { + __IO uint32_t RPT4; + __IO uint32_t RPTB4; + }; + union { + __IO uint32_t SNSEQCTL4; + __IO uint32_t SNSEQCTLB4; + }; + union { + __IO uint32_t DNSEQCTL4; + __IO uint32_t DNSEQCTLB4; + }; + __IO uint32_t LLP4; + __IO uint32_t CHCTL4; + __I uint32_t MONSAR4; + __I uint32_t MONDAR4; + __I uint32_t MONDTCTL4; + __I uint32_t MONRPT4; + __I uint32_t MONSNSEQCTL4; + __I uint32_t MONDNSEQCTL4; + uint8_t RESERVED7[8]; + __IO uint32_t SAR5; + __IO uint32_t DAR5; + __IO uint32_t DTCTL5; + union { + __IO uint32_t RPT5; + __IO uint32_t RPTB5; + }; + union { + __IO uint32_t SNSEQCTL5; + __IO uint32_t SNSEQCTLB5; + }; + union { + __IO uint32_t DNSEQCTL5; + __IO uint32_t DNSEQCTLB5; + }; + __IO uint32_t LLP5; + __IO uint32_t CHCTL5; + __I uint32_t MONSAR5; + __I uint32_t MONDAR5; + __I uint32_t MONDTCTL5; + __I uint32_t MONRPT5; + __I uint32_t MONSNSEQCTL5; + __I uint32_t MONDNSEQCTL5; + uint8_t RESERVED8[8]; + __IO uint32_t SAR6; + __IO uint32_t DAR6; + __IO uint32_t DTCTL6; + union { + __IO uint32_t RPT6; + __IO uint32_t RPTB6; + }; + union { + __IO uint32_t SNSEQCTL6; + __IO uint32_t SNSEQCTLB6; + }; + union { + __IO uint32_t DNSEQCTL6; + __IO uint32_t DNSEQCTLB6; + }; + __IO uint32_t LLP6; + __IO uint32_t CHCTL6; + __I uint32_t MONSAR6; + __I uint32_t MONDAR6; + __I uint32_t MONDTCTL6; + __I uint32_t MONRPT6; + __I uint32_t MONSNSEQCTL6; + __I uint32_t MONDNSEQCTL6; + uint8_t RESERVED9[8]; + __IO uint32_t SAR7; + __IO uint32_t DAR7; + __IO uint32_t DTCTL7; + union { + __IO uint32_t RPT7; + __IO uint32_t RPTB7; + }; + union { + __IO uint32_t SNSEQCTL7; + __IO uint32_t SNSEQCTLB7; + }; + union { + __IO uint32_t DNSEQCTL7; + __IO uint32_t DNSEQCTLB7; + }; + __IO uint32_t LLP7; + __IO uint32_t CHCTL7; + __I uint32_t MONSAR7; + __I uint32_t MONDAR7; + __I uint32_t MONDTCTL7; + __I uint32_t MONRPT7; + __I uint32_t MONSNSEQCTL7; + __I uint32_t MONDNSEQCTL7; +} CM_DMA_TypeDef; + +/** + * @brief DMC + */ +typedef struct { + __I uint32_t STSR; + __O uint32_t STCR; + __O uint32_t CMDR; + __IO uint32_t CPCR; + __IO uint32_t RFTR; + __IO uint32_t TMCR_T_CASL; + __IO uint32_t TMCR_T_DQSS; + __IO uint32_t TMCR_T_MRD; + __IO uint32_t TMCR_T_RAS; + __IO uint32_t TMCR_T_RC; + __IO uint32_t TMCR_T_RCD; + __IO uint32_t TMCR_T_RFC; + __IO uint32_t TMCR_T_RP; + __IO uint32_t TMCR_T_RRD; + __IO uint32_t TMCR_T_WR; + __IO uint32_t TMCR_T_WTR; + __IO uint32_t TMCR_T_XP; + __IO uint32_t TMCR_T_XSR; + __IO uint32_t TMCR_T_ESR; + uint8_t RESERVED0[436]; + __IO uint32_t CSCR0; + __IO uint32_t CSCR1; + __IO uint32_t CSCR2; + __IO uint32_t CSCR3; + uint8_t RESERVED1[240]; + __IO uint32_t BACR; +} CM_DMC_TypeDef; + +/** + * @brief DVP + */ +typedef struct { + __IO uint32_t CTR; + __I uint32_t DTR; + __IO uint32_t STR; + __IO uint32_t IER; + __I uint32_t DMR; + uint8_t RESERVED0[12]; + __IO uint32_t SSYNDR; + __IO uint32_t SSYNMR; + __IO uint32_t CPSFTR; + __IO uint32_t CPSZER; +} CM_DVP_TypeDef; + +/** + * @brief EFM + */ +typedef struct { + __IO uint32_t FAPRT; + __IO uint32_t KEY1; + __IO uint32_t KEY2; + uint8_t RESERVED0[8]; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __I uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __I uint32_t FSWP; + uint8_t RESERVED1[16]; + __I uint32_t CHIPID; + uint8_t RESERVED2[12]; + __I uint32_t UQID0; + __I uint32_t UQID1; + __I uint32_t UQID2; + uint8_t RESERVED3[164]; + __IO uint32_t MMF_REMPRT; + __IO uint32_t MMF_REMCR0; + __IO uint32_t MMF_REMCR1; + uint8_t RESERVED4[116]; + __IO uint32_t WLOCK; + uint8_t RESERVED5[12]; + __IO uint32_t F0NWPRT0; + __IO uint32_t F0NWPRT1; + __IO uint32_t F0NWPRT2; + __IO uint32_t F0NWPRT3; + __IO uint32_t F1NWPRT0; + __IO uint32_t F1NWPRT1; + __IO uint32_t F1NWPRT2; + __IO uint32_t F1NWPRT3; +} CM_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct { + __IO uint32_t CTL1; + __IO uint32_t CTL2; + __IO uint32_t SOE; + __I uint32_t STAT; + __O uint32_t STATCLR; + __IO uint32_t INTEN; + __IO uint32_t RLSSEL; +} CM_EMB_TypeDef; + +/** + * @brief ETH + */ +typedef struct { + uint8_t RESERVED0[21520]; + __IO uint32_t MAC_IFCONFR; + uint8_t RESERVED1[44012]; + __IO uint32_t MAC_CONFIGR; + __IO uint32_t MAC_FLTCTLR; + __IO uint32_t MAC_HASHTHR; + __IO uint32_t MAC_HASHTLR; + __IO uint32_t MAC_SMIADDR; + __IO uint32_t MAC_SMIDATR; + __IO uint32_t MAC_FLOCTLR; + __IO uint32_t MAC_VTAFLTR; + uint8_t RESERVED2[4]; + __I uint32_t MAC_MACSTSR; + __IO uint32_t MAC_RTWKFFR; + __IO uint32_t MAC_PMTCTLR; + uint8_t RESERVED3[8]; + __I uint32_t MAC_INTSTSR; + __IO uint32_t MAC_INTMSKR; + __IO uint32_t MAC_MACADHR0; + __IO uint32_t MAC_MACADLR0; + __IO uint32_t MAC_MACADHR1; + __IO uint32_t MAC_MACADLR1; + __IO uint32_t MAC_MACADHR2; + __IO uint32_t MAC_MACADLR2; + __IO uint32_t MAC_MACADHR3; + __IO uint32_t MAC_MACADLR3; + __IO uint32_t MAC_MACADHR4; + __IO uint32_t MAC_MACADLR4; + uint8_t RESERVED4[152]; + __IO uint32_t MMC_MMCCTLR; + __I uint32_t MMC_REVSTSR; + __I uint32_t MMC_TRSSTSR; + __IO uint32_t MMC_RITCTLR; + __IO uint32_t MMC_TITCTLR; + uint8_t RESERVED5[8]; + __I uint32_t MMC_TXBRGFR; + __I uint32_t MMC_TXMUGFR; + uint8_t RESERVED6[48]; + __I uint32_t MMC_TXDEEFR; + __I uint32_t MMC_TXLCEFR; + __I uint32_t MMC_TXECEFR; + __I uint32_t MMC_TXCAEFR; + uint8_t RESERVED7[4]; + __I uint32_t MMC_TXUNGFR; + __I uint32_t MMC_TXEDEFR; + uint8_t RESERVED8[28]; + __I uint32_t MMC_RXBRGFR; + __I uint32_t MMC_RXMUGFR; + __I uint32_t MMC_RXCREFR; + __I uint32_t MMC_RXALEFR; + __I uint32_t MMC_RXRUEFR; + uint8_t RESERVED9[36]; + __I uint32_t MMC_RXUNGFR; + __I uint32_t MMC_RXLEEFR; + __I uint32_t MMC_RXOREFR; + uint8_t RESERVED10[560]; + __IO uint32_t MAC_L34CTLR; + __IO uint32_t MAC_L4PORTR; + uint8_t RESERVED11[8]; + __IO uint32_t MAC_L3ADDRR0; + __IO uint32_t MAC_L3ADDRR1; + __IO uint32_t MAC_L3ADDRR2; + __IO uint32_t MAC_L3ADDRR3; + uint8_t RESERVED12[356]; + __IO uint32_t MAC_VTACTLR; + __IO uint32_t MAC_VLAHTBR; + uint8_t RESERVED13[372]; + __IO uint32_t PTP_TSPCTLR; + __IO uint32_t PTP_TSPNSAR; + __I uint32_t PTP_TMSSECR; + __I uint32_t PTP_TMSNSER; + __IO uint32_t PTP_TMUSECR; + __IO uint32_t PTP_TMUNSER; + __IO uint32_t PTP_TSPADDR; + __IO uint32_t PTP_TMTSECR0; + __IO uint32_t PTP_TMTNSER0; + uint8_t RESERVED14[4]; + __I uint32_t PTP_TSPSTSR; + __IO uint32_t PTP_PPSCTLR; + uint8_t RESERVED15[80]; + __IO uint32_t PTP_TMTSECR1; + __IO uint32_t PTP_TMTNSER1; + uint8_t RESERVED16[2168]; + __IO uint32_t DMA_BUSMODR; + __IO uint32_t DMA_TXPOLLR; + __IO uint32_t DMA_RXPOLLR; + __IO uint32_t DMA_RXDLADR; + __IO uint32_t DMA_TXDLADR; + __IO uint32_t DMA_DMASTSR; + __IO uint32_t DMA_OPRMODR; + __IO uint32_t DMA_INTENAR; + __I uint32_t DMA_RFRCNTR; + __IO uint32_t DMA_REVWDTR; + uint8_t RESERVED17[32]; + __I uint32_t DMA_CHTXDER; + __I uint32_t DMA_CHRXDER; + __I uint32_t DMA_CHTXBFR; + __I uint32_t DMA_CHRXBFR; +} CM_ETH_TypeDef; + +/** + * @brief FCM + */ +typedef struct { + __IO uint32_t LVR; + __IO uint32_t UVR; + __I uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __I uint32_t SR; + __O uint32_t CLR; +} CM_FCM_TypeDef; + +/** + * @brief FMAC + */ +typedef struct { + __IO uint32_t ENR; + __IO uint32_t CTR; + __IO uint32_t IER; + __IO uint32_t DTR; + __IO uint32_t RTR0; + __IO uint32_t RTR1; + __IO uint32_t STR; + uint8_t RESERVED0[4]; + __IO uint32_t COR0; + __IO uint32_t COR1; + __IO uint32_t COR2; + __IO uint32_t COR3; + __IO uint32_t COR4; + __IO uint32_t COR5; + __IO uint32_t COR6; + __IO uint32_t COR7; + __IO uint32_t COR8; + __IO uint32_t COR9; + __IO uint32_t COR10; + __IO uint32_t COR11; + __IO uint32_t COR12; + __IO uint32_t COR13; + __IO uint32_t COR14; + __IO uint32_t COR15; + __IO uint32_t COR16; +} CM_FMAC_TypeDef; + +/** + * @brief GPIO + */ +typedef struct { + __I uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __O uint16_t POSRA; + __O uint16_t PORRA; + __O uint16_t POTRA; + uint8_t RESERVED1[2]; + __I uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __O uint16_t POSRB; + __O uint16_t PORRB; + __O uint16_t POTRB; + uint8_t RESERVED3[2]; + __I uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __O uint16_t POSRC; + __O uint16_t PORRC; + __O uint16_t POTRC; + uint8_t RESERVED5[2]; + __I uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __O uint16_t POSRD; + __O uint16_t PORRD; + __O uint16_t POTRD; + uint8_t RESERVED7[2]; + __I uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __O uint16_t POSRE; + __O uint16_t PORRE; + __O uint16_t POTRE; + uint8_t RESERVED9[2]; + __I uint16_t PIDRF; + uint8_t RESERVED10[2]; + __IO uint16_t PODRF; + __IO uint16_t POERF; + __O uint16_t POSRF; + __O uint16_t PORRF; + __O uint16_t POTRF; + uint8_t RESERVED11[2]; + __I uint16_t PIDRG; + uint8_t RESERVED12[2]; + __IO uint16_t PODRG; + __IO uint16_t POERG; + __O uint16_t POSRG; + __O uint16_t PORRG; + __O uint16_t POTRG; + uint8_t RESERVED13[2]; + __I uint16_t PIDRH; + uint8_t RESERVED14[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __O uint16_t POSRH; + __O uint16_t PORRH; + __O uint16_t POTRH; + uint8_t RESERVED15[2]; + __I uint16_t PIDRI; + uint8_t RESERVED16[2]; + __IO uint16_t PODRI; + __IO uint16_t POERI; + __O uint16_t POSRI; + __O uint16_t PORRI; + __O uint16_t POTRI; + uint8_t RESERVED17[870]; + __IO uint16_t PSPCR; + uint8_t RESERVED18[2]; + __IO uint16_t PCCR; + __IO uint16_t PINAER; + __IO uint16_t PWPR; + uint8_t RESERVED19[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + __IO uint16_t PCRD3; + __IO uint16_t PFSRD3; + __IO uint16_t PCRD4; + __IO uint16_t PFSRD4; + __IO uint16_t PCRD5; + __IO uint16_t PFSRD5; + __IO uint16_t PCRD6; + __IO uint16_t PFSRD6; + __IO uint16_t PCRD7; + __IO uint16_t PFSRD7; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + __IO uint16_t PCRD12; + __IO uint16_t PFSRD12; + __IO uint16_t PCRD13; + __IO uint16_t PFSRD13; + __IO uint16_t PCRD14; + __IO uint16_t PFSRD14; + __IO uint16_t PCRD15; + __IO uint16_t PFSRD15; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + __IO uint16_t PCRE5; + __IO uint16_t PFSRE5; + __IO uint16_t PCRE6; + __IO uint16_t PFSRE6; + __IO uint16_t PCRE7; + __IO uint16_t PFSRE7; + __IO uint16_t PCRE8; + __IO uint16_t PFSRE8; + __IO uint16_t PCRE9; + __IO uint16_t PFSRE9; + __IO uint16_t PCRE10; + __IO uint16_t PFSRE10; + __IO uint16_t PCRE11; + __IO uint16_t PFSRE11; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRF0; + __IO uint16_t PFSRF0; + __IO uint16_t PCRF1; + __IO uint16_t PFSRF1; + __IO uint16_t PCRF2; + __IO uint16_t PFSRF2; + __IO uint16_t PCRF3; + __IO uint16_t PFSRF3; + __IO uint16_t PCRF4; + __IO uint16_t PFSRF4; + __IO uint16_t PCRF5; + __IO uint16_t PFSRF5; + __IO uint16_t PCRF6; + __IO uint16_t PFSRF6; + __IO uint16_t PCRF7; + __IO uint16_t PFSRF7; + __IO uint16_t PCRF8; + __IO uint16_t PFSRF8; + __IO uint16_t PCRF9; + __IO uint16_t PFSRF9; + __IO uint16_t PCRF10; + __IO uint16_t PFSRF10; + __IO uint16_t PCRF11; + __IO uint16_t PFSRF11; + __IO uint16_t PCRF12; + __IO uint16_t PFSRF12; + __IO uint16_t PCRF13; + __IO uint16_t PFSRF13; + __IO uint16_t PCRF14; + __IO uint16_t PFSRF14; + __IO uint16_t PCRF15; + __IO uint16_t PFSRF15; + __IO uint16_t PCRG0; + __IO uint16_t PFSRG0; + __IO uint16_t PCRG1; + __IO uint16_t PFSRG1; + __IO uint16_t PCRG2; + __IO uint16_t PFSRG2; + __IO uint16_t PCRG3; + __IO uint16_t PFSRG3; + __IO uint16_t PCRG4; + __IO uint16_t PFSRG4; + __IO uint16_t PCRG5; + __IO uint16_t PFSRG5; + __IO uint16_t PCRG6; + __IO uint16_t PFSRG6; + __IO uint16_t PCRG7; + __IO uint16_t PFSRG7; + __IO uint16_t PCRG8; + __IO uint16_t PFSRG8; + __IO uint16_t PCRG9; + __IO uint16_t PFSRG9; + __IO uint16_t PCRG10; + __IO uint16_t PFSRG10; + __IO uint16_t PCRG11; + __IO uint16_t PFSRG11; + __IO uint16_t PCRG12; + __IO uint16_t PFSRG12; + __IO uint16_t PCRG13; + __IO uint16_t PFSRG13; + __IO uint16_t PCRG14; + __IO uint16_t PFSRG14; + __IO uint16_t PCRG15; + __IO uint16_t PFSRG15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; + __IO uint16_t PCRH3; + __IO uint16_t PFSRH3; + __IO uint16_t PCRH4; + __IO uint16_t PFSRH4; + __IO uint16_t PCRH5; + __IO uint16_t PFSRH5; + __IO uint16_t PCRH6; + __IO uint16_t PFSRH6; + __IO uint16_t PCRH7; + __IO uint16_t PFSRH7; + __IO uint16_t PCRH8; + __IO uint16_t PFSRH8; + __IO uint16_t PCRH9; + __IO uint16_t PFSRH9; + __IO uint16_t PCRH10; + __IO uint16_t PFSRH10; + __IO uint16_t PCRH11; + __IO uint16_t PFSRH11; + __IO uint16_t PCRH12; + __IO uint16_t PFSRH12; + __IO uint16_t PCRH13; + __IO uint16_t PFSRH13; + __IO uint16_t PCRH14; + __IO uint16_t PFSRH14; + __IO uint16_t PCRH15; + __IO uint16_t PFSRH15; + __IO uint16_t PCRI0; + __IO uint16_t PFSRI0; + __IO uint16_t PCRI1; + __IO uint16_t PFSRI1; + __IO uint16_t PCRI2; + __IO uint16_t PFSRI2; + __IO uint16_t PCRI3; + __IO uint16_t PFSRI3; + __IO uint16_t PCRI4; + __IO uint16_t PFSRI4; + __IO uint16_t PCRI5; + __IO uint16_t PFSRI5; + __IO uint16_t PCRI6; + __IO uint16_t PFSRI6; + __IO uint16_t PCRI7; + __IO uint16_t PFSRI7; + __IO uint16_t PCRI8; + __IO uint16_t PFSRI8; + __IO uint16_t PCRI9; + __IO uint16_t PFSRI9; + __IO uint16_t PCRI10; + __IO uint16_t PFSRI10; + __IO uint16_t PCRI11; + __IO uint16_t PFSRI11; + __IO uint16_t PCRI12; + __IO uint16_t PFSRI12; + __IO uint16_t PCRI13; + __IO uint16_t PFSRI13; +} CM_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} CM_HASH_TypeDef; + +/** + * @brief HRPWM + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t CR5; + __IO uint32_t CR6; + __IO uint32_t CR7; + __IO uint32_t CR8; + __IO uint32_t CR9; + __IO uint32_t CR10; + __IO uint32_t CR11; + __IO uint32_t CR12; + __IO uint32_t CR13; + __IO uint32_t CR14; + __IO uint32_t CR15; + __IO uint32_t CR16; + uint8_t RESERVED0[16]; + __IO uint32_t CALCR0; + __IO uint32_t CALCR1; +} CM_HRPWM_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __O uint32_t CLR; + __O uint8_t DTR; + uint8_t RESERVED0[3]; + __I uint8_t DRR; + uint8_t RESERVED1[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; +} CM_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct { + __IO uint32_t CTRL; + __I uint32_t SR; + __IO uint32_t ER; + __IO uint32_t CFGR; + __O uint32_t TXBUF; + __I uint32_t RXBUF; + __IO uint32_t PR; +} CM_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct { + __I uint32_t ICG0; + __I uint32_t ICG1; + __I uint32_t ICG2; + __I uint32_t ICG3; +} CM_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct { + __IO uint32_t NOCCR; + __IO uint32_t NMIENR; + __IO uint32_t NMIFR; + __IO uint32_t NMICFR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WUPEN; + __IO uint32_t EIRQFR; + __IO uint32_t EIRQCFR; + __IO uint32_t SEL0; + __IO uint32_t SEL1; + __IO uint32_t SEL2; + __IO uint32_t SEL3; + __IO uint32_t SEL4; + __IO uint32_t SEL5; + __IO uint32_t SEL6; + __IO uint32_t SEL7; + __IO uint32_t SEL8; + __IO uint32_t SEL9; + __IO uint32_t SEL10; + __IO uint32_t SEL11; + __IO uint32_t SEL12; + __IO uint32_t SEL13; + __IO uint32_t SEL14; + __IO uint32_t SEL15; + __IO uint32_t SEL16; + __IO uint32_t SEL17; + __IO uint32_t SEL18; + __IO uint32_t SEL19; + __IO uint32_t SEL20; + __IO uint32_t SEL21; + __IO uint32_t SEL22; + __IO uint32_t SEL23; + __IO uint32_t SEL24; + __IO uint32_t SEL25; + __IO uint32_t SEL26; + __IO uint32_t SEL27; + __IO uint32_t SEL28; + __IO uint32_t SEL29; + __IO uint32_t SEL30; + __IO uint32_t SEL31; + __IO uint32_t SEL32; + __IO uint32_t SEL33; + __IO uint32_t SEL34; + __IO uint32_t SEL35; + __IO uint32_t SEL36; + __IO uint32_t SEL37; + __IO uint32_t SEL38; + __IO uint32_t SEL39; + __IO uint32_t SEL40; + __IO uint32_t SEL41; + __IO uint32_t SEL42; + __IO uint32_t SEL43; + __IO uint32_t SEL44; + __IO uint32_t SEL45; + __IO uint32_t SEL46; + __IO uint32_t SEL47; + __IO uint32_t SEL48; + __IO uint32_t SEL49; + __IO uint32_t SEL50; + __IO uint32_t SEL51; + __IO uint32_t SEL52; + __IO uint32_t SEL53; + __IO uint32_t SEL54; + __IO uint32_t SEL55; + __IO uint32_t SEL56; + __IO uint32_t SEL57; + __IO uint32_t SEL58; + __IO uint32_t SEL59; + __IO uint32_t SEL60; + __IO uint32_t SEL61; + __IO uint32_t SEL62; + __IO uint32_t SEL63; + __IO uint32_t SEL64; + __IO uint32_t SEL65; + __IO uint32_t SEL66; + __IO uint32_t SEL67; + __IO uint32_t SEL68; + __IO uint32_t SEL69; + __IO uint32_t SEL70; + __IO uint32_t SEL71; + __IO uint32_t SEL72; + __IO uint32_t SEL73; + __IO uint32_t SEL74; + __IO uint32_t SEL75; + __IO uint32_t SEL76; + __IO uint32_t SEL77; + __IO uint32_t SEL78; + __IO uint32_t SEL79; + __IO uint32_t SEL80; + __IO uint32_t SEL81; + __IO uint32_t SEL82; + __IO uint32_t SEL83; + __IO uint32_t SEL84; + __IO uint32_t SEL85; + __IO uint32_t SEL86; + __IO uint32_t SEL87; + __IO uint32_t SEL88; + __IO uint32_t SEL89; + __IO uint32_t SEL90; + __IO uint32_t SEL91; + __IO uint32_t SEL92; + __IO uint32_t SEL93; + __IO uint32_t SEL94; + __IO uint32_t SEL95; + __IO uint32_t SEL96; + __IO uint32_t SEL97; + __IO uint32_t SEL98; + __IO uint32_t SEL99; + __IO uint32_t SEL100; + __IO uint32_t SEL101; + __IO uint32_t SEL102; + __IO uint32_t SEL103; + __IO uint32_t SEL104; + __IO uint32_t SEL105; + __IO uint32_t SEL106; + __IO uint32_t SEL107; + __IO uint32_t SEL108; + __IO uint32_t SEL109; + __IO uint32_t SEL110; + __IO uint32_t SEL111; + __IO uint32_t SEL112; + __IO uint32_t SEL113; + __IO uint32_t SEL114; + __IO uint32_t SEL115; + __IO uint32_t SEL116; + __IO uint32_t SEL117; + __IO uint32_t SEL118; + __IO uint32_t SEL119; + __IO uint32_t SEL120; + __IO uint32_t SEL121; + __IO uint32_t SEL122; + __IO uint32_t SEL123; + __IO uint32_t SEL124; + __IO uint32_t SEL125; + __IO uint32_t SEL126; + __IO uint32_t SEL127; + __IO uint32_t VSSEL128; + __IO uint32_t VSSEL129; + __IO uint32_t VSSEL130; + __IO uint32_t VSSEL131; + __IO uint32_t VSSEL132; + __IO uint32_t VSSEL133; + __IO uint32_t VSSEL134; + __IO uint32_t VSSEL135; + __IO uint32_t VSSEL136; + __IO uint32_t VSSEL137; + __IO uint32_t VSSEL138; + __IO uint32_t VSSEL139; + __IO uint32_t VSSEL140; + __IO uint32_t VSSEL141; + __IO uint32_t VSSEL142; + __IO uint32_t VSSEL143; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} CM_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct { + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} CM_KEYSCAN_TypeDef; + +/** + * @brief MAU + */ +typedef struct { + __IO uint32_t CSR; + __IO uint32_t DTR0; + uint8_t RESERVED0[4]; + __IO uint32_t RTR0; + __IO uint32_t DTR1; + __IO uint32_t RTR1; +} CM_MAU_TypeDef; + +/** + * @brief MPU + */ +typedef struct { + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __I uint32_t SR; + __O uint32_t ECLR; + __IO uint32_t WP; + __IO uint32_t IPPR; + __IO uint32_t S1RGE; + __IO uint32_t S1RGWP; + __IO uint32_t S1RGRP; + __IO uint32_t S1CR; + __IO uint32_t S2RGE; + __IO uint32_t S2RGWP; + __IO uint32_t S2RGRP; + __IO uint32_t S2CR; + __IO uint32_t FRGE; + __IO uint32_t FRGWP; + __IO uint32_t FRGRP; + __IO uint32_t FCR; + __IO uint32_t HRGE; + __IO uint32_t HRGWP; + __IO uint32_t HRGRP; + __IO uint32_t HCR; + __IO uint32_t ERGE; + __IO uint32_t ERGWP; + __IO uint32_t ERGRP; + __IO uint32_t ECR; +} CM_MPU_TypeDef; + +/** + * @brief NFC + */ +typedef struct { + __IO uint32_t DATR_BASE; + uint8_t RESERVED0[32764]; + __IO uint32_t CMDR; + __IO uint32_t IDXR0; + uint8_t RESERVED1[40]; + __IO uint32_t IENR; + __IO uint32_t ISTR; + __IO uint32_t IRSR; + uint8_t RESERVED2[12]; + __IO uint32_t IDXR1; + __IO uint32_t TMCR0; + __IO uint32_t TMCR1; + __IO uint32_t BACR; + uint8_t RESERVED3[4]; + __IO uint32_t TMCR2; + __I uint32_t ECCR0; + __I uint32_t ECCR1; + __I uint32_t ECCR2; + __I uint32_t ECCR3; + __I uint32_t ECCR4; + __I uint32_t ECCR5; + __I uint32_t ECCR6; + __I uint32_t ECC_STAT; + __I uint32_t ECC_SYND0_0; + __I uint32_t ECC_SYND0_1; + __I uint32_t ECC_SYND0_2; + __I uint32_t ECC_SYND0_3; + __I uint32_t ECC_SYND1_0; + __I uint32_t ECC_SYND1_1; + __I uint32_t ECC_SYND1_2; + __I uint32_t ECC_SYND1_3; + __I uint32_t ECC_SYND2_0; + __I uint32_t ECC_SYND2_1; + __I uint32_t ECC_SYND2_2; + __I uint32_t ECC_SYND2_3; + __I uint32_t ECC_SYND3_0; + __I uint32_t ECC_SYND3_1; + __I uint32_t ECC_SYND3_2; + __I uint32_t ECC_SYND3_3; + __I uint32_t ECC_SYND4_0; + __I uint32_t ECC_SYND4_1; + __I uint32_t ECC_SYND4_2; + __I uint32_t ECC_SYND4_3; + __I uint32_t ECC_SYND5_0; + __I uint32_t ECC_SYND5_1; + __I uint32_t ECC_SYND5_2; + __I uint32_t ECC_SYND5_3; + __I uint32_t ECC_SYND6_0; + __I uint32_t ECC_SYND6_1; + __I uint32_t ECC_SYND6_2; + __I uint32_t ECC_SYND6_3; + __I uint32_t ECC_SYND7_0; + __I uint32_t ECC_SYND7_1; + __I uint32_t ECC_SYND7_2; + __I uint32_t ECC_SYND7_3; + __I uint32_t ECC_SYND8_0; + __I uint32_t ECC_SYND8_1; + __I uint32_t ECC_SYND8_2; + __I uint32_t ECC_SYND8_3; + __I uint32_t ECC_SYND9_0; + __I uint32_t ECC_SYND9_1; + __I uint32_t ECC_SYND9_2; + __I uint32_t ECC_SYND9_3; + __I uint32_t ECC_SYND10_0; + __I uint32_t ECC_SYND10_1; + __I uint32_t ECC_SYND10_2; + __I uint32_t ECC_SYND10_3; + __I uint32_t ECC_SYND11_0; + __I uint32_t ECC_SYND11_1; + __I uint32_t ECC_SYND11_2; + __I uint32_t ECC_SYND11_3; + __I uint32_t ECC_SYND12_0; + __I uint32_t ECC_SYND12_1; + __I uint32_t ECC_SYND12_2; + __I uint32_t ECC_SYND12_3; + __I uint32_t ECC_SYND13_0; + __I uint32_t ECC_SYND13_1; + __I uint32_t ECC_SYND13_2; + __I uint32_t ECC_SYND13_3; + __I uint32_t ECC_SYND14_0; + __I uint32_t ECC_SYND14_1; + __I uint32_t ECC_SYND14_2; + __I uint32_t ECC_SYND14_3; + __I uint32_t ECC_SYND15_0; + __I uint32_t ECC_SYND15_1; + __I uint32_t ECC_SYND15_2; + __I uint32_t ECC_SYND15_3; +} CM_NFC_TypeDef; + +/** + * @brief OTS + */ +typedef struct { + uint8_t RESERVED0[224]; + __IO uint32_t PDR1; + uint8_t RESERVED1[16]; + __IO uint32_t PDR2; + __IO uint32_t PDR3; + uint8_t RESERVED2[237828]; + __IO uint16_t CTL; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + __I uint32_t LPR; +} CM_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct { + __IO uint32_t USB_SYCTLREG; + __IO uint32_t SDIOC_SYCTLREG; + __IO uint32_t NFC_STCR; + union { + __IO uint32_t NFC_ENAR; + __IO uint32_t SMC_ENAR; + __IO uint32_t DMC_ENAR; + }; + uint8_t RESERVED0[12]; + __IO uint32_t USART1_NFC; + uint8_t RESERVED1[8]; + __I uint32_t NFC_STSR; +} CM_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct { + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17436]; + __IO uint8_t VBATRSTR; + uint8_t RESERVED1[15]; + __IO uint8_t VBATCR; + uint8_t RESERVED2[15]; + __IO uint8_t WKTC0; + uint8_t RESERVED3[3]; + __IO uint8_t WKTC1; + uint8_t RESERVED4[3]; + __IO uint8_t WKTC2; + uint8_t RESERVED5[423]; + __IO uint8_t BKR0; + uint8_t RESERVED6[3]; + __IO uint8_t BKR1; + uint8_t RESERVED7[3]; + __IO uint8_t BKR2; + uint8_t RESERVED8[3]; + __IO uint8_t BKR3; + uint8_t RESERVED9[3]; + __IO uint8_t BKR4; + uint8_t RESERVED10[3]; + __IO uint8_t BKR5; + uint8_t RESERVED11[3]; + __IO uint8_t BKR6; + uint8_t RESERVED12[3]; + __IO uint8_t BKR7; + uint8_t RESERVED13[3]; + __IO uint8_t BKR8; + uint8_t RESERVED14[3]; + __IO uint8_t BKR9; + uint8_t RESERVED15[3]; + __IO uint8_t BKR10; + uint8_t RESERVED16[3]; + __IO uint8_t BKR11; + uint8_t RESERVED17[3]; + __IO uint8_t BKR12; + uint8_t RESERVED18[3]; + __IO uint8_t BKR13; + uint8_t RESERVED19[3]; + __IO uint8_t BKR14; + uint8_t RESERVED20[3]; + __IO uint8_t BKR15; + uint8_t RESERVED21[3]; + __IO uint8_t BKR16; + uint8_t RESERVED22[3]; + __IO uint8_t BKR17; + uint8_t RESERVED23[3]; + __IO uint8_t BKR18; + uint8_t RESERVED24[3]; + __IO uint8_t BKR19; + uint8_t RESERVED25[3]; + __IO uint8_t BKR20; + uint8_t RESERVED26[3]; + __IO uint8_t BKR21; + uint8_t RESERVED27[3]; + __IO uint8_t BKR22; + uint8_t RESERVED28[3]; + __IO uint8_t BKR23; + uint8_t RESERVED29[3]; + __IO uint8_t BKR24; + uint8_t RESERVED30[3]; + __IO uint8_t BKR25; + uint8_t RESERVED31[3]; + __IO uint8_t BKR26; + uint8_t RESERVED32[3]; + __IO uint8_t BKR27; + uint8_t RESERVED33[3]; + __IO uint8_t BKR28; + uint8_t RESERVED34[3]; + __IO uint8_t BKR29; + uint8_t RESERVED35[3]; + __IO uint8_t BKR30; + uint8_t RESERVED36[3]; + __IO uint8_t BKR31; + uint8_t RESERVED37[3]; + __IO uint8_t BKR32; + uint8_t RESERVED38[3]; + __IO uint8_t BKR33; + uint8_t RESERVED39[3]; + __IO uint8_t BKR34; + uint8_t RESERVED40[3]; + __IO uint8_t BKR35; + uint8_t RESERVED41[3]; + __IO uint8_t BKR36; + uint8_t RESERVED42[3]; + __IO uint8_t BKR37; + uint8_t RESERVED43[3]; + __IO uint8_t BKR38; + uint8_t RESERVED44[3]; + __IO uint8_t BKR39; + uint8_t RESERVED45[3]; + __IO uint8_t BKR40; + uint8_t RESERVED46[3]; + __IO uint8_t BKR41; + uint8_t RESERVED47[3]; + __IO uint8_t BKR42; + uint8_t RESERVED48[3]; + __IO uint8_t BKR43; + uint8_t RESERVED49[3]; + __IO uint8_t BKR44; + uint8_t RESERVED50[3]; + __IO uint8_t BKR45; + uint8_t RESERVED51[3]; + __IO uint8_t BKR46; + uint8_t RESERVED52[3]; + __IO uint8_t BKR47; + uint8_t RESERVED53[3]; + __IO uint8_t BKR48; + uint8_t RESERVED54[3]; + __IO uint8_t BKR49; + uint8_t RESERVED55[3]; + __IO uint8_t BKR50; + uint8_t RESERVED56[3]; + __IO uint8_t BKR51; + uint8_t RESERVED57[3]; + __IO uint8_t BKR52; + uint8_t RESERVED58[3]; + __IO uint8_t BKR53; + uint8_t RESERVED59[3]; + __IO uint8_t BKR54; + uint8_t RESERVED60[3]; + __IO uint8_t BKR55; + uint8_t RESERVED61[3]; + __IO uint8_t BKR56; + uint8_t RESERVED62[3]; + __IO uint8_t BKR57; + uint8_t RESERVED63[3]; + __IO uint8_t BKR58; + uint8_t RESERVED64[3]; + __IO uint8_t BKR59; + uint8_t RESERVED65[3]; + __IO uint8_t BKR60; + uint8_t RESERVED66[3]; + __IO uint8_t BKR61; + uint8_t RESERVED67[3]; + __IO uint8_t BKR62; + uint8_t RESERVED68[3]; + __IO uint8_t BKR63; + uint8_t RESERVED69[3]; + __IO uint8_t BKR64; + uint8_t RESERVED70[3]; + __IO uint8_t BKR65; + uint8_t RESERVED71[3]; + __IO uint8_t BKR66; + uint8_t RESERVED72[3]; + __IO uint8_t BKR67; + uint8_t RESERVED73[3]; + __IO uint8_t BKR68; + uint8_t RESERVED74[3]; + __IO uint8_t BKR69; + uint8_t RESERVED75[3]; + __IO uint8_t BKR70; + uint8_t RESERVED76[3]; + __IO uint8_t BKR71; + uint8_t RESERVED77[3]; + __IO uint8_t BKR72; + uint8_t RESERVED78[3]; + __IO uint8_t BKR73; + uint8_t RESERVED79[3]; + __IO uint8_t BKR74; + uint8_t RESERVED80[3]; + __IO uint8_t BKR75; + uint8_t RESERVED81[3]; + __IO uint8_t BKR76; + uint8_t RESERVED82[3]; + __IO uint8_t BKR77; + uint8_t RESERVED83[3]; + __IO uint8_t BKR78; + uint8_t RESERVED84[3]; + __IO uint8_t BKR79; + uint8_t RESERVED85[3]; + __IO uint8_t BKR80; + uint8_t RESERVED86[3]; + __IO uint8_t BKR81; + uint8_t RESERVED87[3]; + __IO uint8_t BKR82; + uint8_t RESERVED88[3]; + __IO uint8_t BKR83; + uint8_t RESERVED89[3]; + __IO uint8_t BKR84; + uint8_t RESERVED90[3]; + __IO uint8_t BKR85; + uint8_t RESERVED91[3]; + __IO uint8_t BKR86; + uint8_t RESERVED92[3]; + __IO uint8_t BKR87; + uint8_t RESERVED93[3]; + __IO uint8_t BKR88; + uint8_t RESERVED94[3]; + __IO uint8_t BKR89; + uint8_t RESERVED95[3]; + __IO uint8_t BKR90; + uint8_t RESERVED96[3]; + __IO uint8_t BKR91; + uint8_t RESERVED97[3]; + __IO uint8_t BKR92; + uint8_t RESERVED98[3]; + __IO uint8_t BKR93; + uint8_t RESERVED99[3]; + __IO uint8_t BKR94; + uint8_t RESERVED100[3]; + __IO uint8_t BKR95; + uint8_t RESERVED101[3]; + __IO uint8_t BKR96; + uint8_t RESERVED102[3]; + __IO uint8_t BKR97; + uint8_t RESERVED103[3]; + __IO uint8_t BKR98; + uint8_t RESERVED104[3]; + __IO uint8_t BKR99; + uint8_t RESERVED105[3]; + __IO uint8_t BKR100; + uint8_t RESERVED106[3]; + __IO uint8_t BKR101; + uint8_t RESERVED107[3]; + __IO uint8_t BKR102; + uint8_t RESERVED108[3]; + __IO uint8_t BKR103; + uint8_t RESERVED109[3]; + __IO uint8_t BKR104; + uint8_t RESERVED110[3]; + __IO uint8_t BKR105; + uint8_t RESERVED111[3]; + __IO uint8_t BKR106; + uint8_t RESERVED112[3]; + __IO uint8_t BKR107; + uint8_t RESERVED113[3]; + __IO uint8_t BKR108; + uint8_t RESERVED114[3]; + __IO uint8_t BKR109; + uint8_t RESERVED115[3]; + __IO uint8_t BKR110; + uint8_t RESERVED116[3]; + __IO uint8_t BKR111; + uint8_t RESERVED117[3]; + __IO uint8_t BKR112; + uint8_t RESERVED118[3]; + __IO uint8_t BKR113; + uint8_t RESERVED119[3]; + __IO uint8_t BKR114; + uint8_t RESERVED120[3]; + __IO uint8_t BKR115; + uint8_t RESERVED121[3]; + __IO uint8_t BKR116; + uint8_t RESERVED122[3]; + __IO uint8_t BKR117; + uint8_t RESERVED123[3]; + __IO uint8_t BKR118; + uint8_t RESERVED124[3]; + __IO uint8_t BKR119; + uint8_t RESERVED125[3]; + __IO uint8_t BKR120; + uint8_t RESERVED126[3]; + __IO uint8_t BKR121; + uint8_t RESERVED127[3]; + __IO uint8_t BKR122; + uint8_t RESERVED128[3]; + __IO uint8_t BKR123; + uint8_t RESERVED129[3]; + __IO uint8_t BKR124; + uint8_t RESERVED130[3]; + __IO uint8_t BKR125; + uint8_t RESERVED131[3]; + __IO uint8_t BKR126; + uint8_t RESERVED132[3]; + __IO uint8_t BKR127; + uint8_t RESERVED133[1027]; + __IO uint8_t PWRC0; + uint8_t RESERVED134[3]; + __IO uint8_t PWRC1; + uint8_t RESERVED135[3]; + __IO uint8_t PWRC2; + uint8_t RESERVED136[3]; + __IO uint8_t PWRC3; + uint8_t RESERVED137[3]; + __IO uint8_t PWRC4; + uint8_t RESERVED138[3]; + __IO uint8_t PVDCR0; + uint8_t RESERVED139[3]; + __IO uint8_t PVDCR1; + uint8_t RESERVED140[3]; + __IO uint8_t PVDFCR; + uint8_t RESERVED141[3]; + __IO uint8_t PVDLCR; + uint8_t RESERVED142[7]; + __IO uint8_t PDWKE0; + uint8_t RESERVED143[3]; + __IO uint8_t PDWKE1; + uint8_t RESERVED144[3]; + __IO uint8_t PDWKE2; + uint8_t RESERVED145[3]; + __IO uint8_t PDWKES; + uint8_t RESERVED146[3]; + __IO uint8_t PDWKF0; + uint8_t RESERVED147[3]; + __IO uint8_t PDWKF1; + uint8_t RESERVED148[163]; + __IO uint32_t RAMPC0; + __IO uint16_t RAMOPM; + uint8_t RESERVED149[2]; + __IO uint32_t PRAMLPC; + uint8_t RESERVED150[4]; + __IO uint8_t PVDICR; + uint8_t RESERVED151[3]; + __IO uint8_t PVDDSR; + uint8_t RESERVED152[29463]; + __IO uint16_t STPMCR; + uint8_t RESERVED153[1008]; + __IO uint16_t FPRC; +} CM_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __O uint32_t SR2; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} CM_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct { + uint8_t RESERVED0[248]; + __IO uint8_t PRSTCR0; + uint8_t RESERVED1[3]; + __IO uint32_t RSTF0; +} CM_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct { + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; + uint8_t RESERVED15[3]; + __IO uint8_t TPCR0; + uint8_t RESERVED16[3]; + __IO uint8_t TPCR1; + uint8_t RESERVED17[3]; + __IO uint8_t TPSR; + uint8_t RESERVED18[3]; + __IO uint8_t SECTP; + uint8_t RESERVED19[3]; + __IO uint8_t MINTP; + uint8_t RESERVED20[3]; + __IO uint8_t HOURTP; + uint8_t RESERVED21[3]; + __IO uint8_t DAYTP; + uint8_t RESERVED22[3]; + __IO uint8_t MONTP; +} CM_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint16_t BLKSIZE; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + __IO uint16_t TRANSMODE; + __IO uint16_t CMD; + __I uint16_t RESP0; + __I uint16_t RESP1; + __I uint16_t RESP2; + __I uint16_t RESP3; + __I uint16_t RESP4; + __I uint16_t RESP5; + __I uint16_t RESP6; + __I uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + __I uint32_t PSTAT; + __IO uint8_t HOSTCON; + __IO uint8_t PWRCON; + __IO uint8_t BLKGPCON; + uint8_t RESERVED1[1]; + __IO uint16_t CLKCON; + __IO uint8_t TOUTCON; + __IO uint8_t SFTRST; + __IO uint16_t NORINTST; + __IO uint16_t ERRINTST; + __IO uint16_t NORINTSTEN; + __IO uint16_t ERRINTSTEN; + __IO uint16_t NORINTSGEN; + __IO uint16_t ERRINTSGEN; + __I uint16_t ATCERRST; + uint8_t RESERVED2[18]; + __O uint16_t FEA; + __O uint16_t FEE; +} CM_SDIOC_TypeDef; + +/** + * @brief SMC + */ +typedef struct { + __I uint32_t STSR; + uint8_t RESERVED0[4]; + __O uint32_t STCR0; + __O uint32_t STCR1; + __O uint32_t CMDR; + __O uint32_t TMCR; + __O uint32_t CPCR; + uint8_t RESERVED1[4]; + __IO uint32_t RFTR; + uint8_t RESERVED2[220]; + __I uint32_t TMSR0; + __I uint32_t CPSR0; + uint8_t RESERVED3[24]; + __I uint32_t TMSR1; + __I uint32_t CPSR1; + uint8_t RESERVED4[24]; + __I uint32_t TMSR2; + __I uint32_t CPSR2; + uint8_t RESERVED5[24]; + __I uint32_t TMSR3; + __I uint32_t CPSR3; + uint8_t RESERVED6[152]; + __IO uint32_t BACR; + uint8_t RESERVED7[4]; + __IO uint32_t CSCR0; + __IO uint32_t CSCR1; +} CM_SMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct { + __IO uint32_t DR; + __IO uint32_t CR1; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} CM_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct { + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; +} CM_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} CM_TMR0_TypeDef; + +/** + * @brief TMR2 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t ICONR; + __IO uint32_t PCONR; + __IO uint32_t HCONR; + __IO uint32_t STFLR; +} CM_TMR2_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCMRHUH; + uint8_t RESERVED6[2]; + __IO uint32_t OCMRLUL; + __IO uint16_t OCMRHVH; + uint8_t RESERVED7[2]; + __IO uint32_t OCMRLVL; + __IO uint16_t OCMRHWH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRLWL; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + __IO uint16_t POCRU; + uint8_t RESERVED14[2]; + __IO uint16_t POCRV; + uint8_t RESERVED15[2]; + __IO uint16_t POCRW; + uint8_t RESERVED16[2]; + __IO uint16_t RCSR; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + __IO uint32_t PSCR; + __IO uint16_t SCER; +} CM_TMR4_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t UPDAR; + uint8_t RESERVED0[56]; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + uint8_t RESERVED1[52]; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + uint8_t RESERVED2[40]; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + uint8_t RESERVED3[40]; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + uint8_t RESERVED4[48]; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED5[4]; + __IO uint32_t PCNAR; + __IO uint32_t PCNBR; + __IO uint32_t FCNGR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + uint8_t RESERVED6[24]; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HUPDR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; +} CM_TMR6_TypeDef; + +/** + * @brief TMR6CR + */ +typedef struct { + uint8_t RESERVED0[1004]; + __IO uint32_t FCNTR; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; + __IO uint32_t SUPDR; +} CM_TMR6CR_TypeDef; + +/** + * @brief TMRA + */ +typedef struct { + __IO uint16_t CNTER; + uint8_t RESERVED0[2]; + __IO uint16_t PERAR; + uint8_t RESERVED1[58]; + __IO uint16_t CMPAR1; + uint8_t RESERVED2[2]; + __IO uint16_t CMPAR2; + uint8_t RESERVED3[2]; + __IO uint16_t CMPAR3; + uint8_t RESERVED4[2]; + __IO uint16_t CMPAR4; + uint8_t RESERVED5[50]; + __IO uint16_t BCSTR; + uint8_t RESERVED6[2]; + __IO uint16_t HCONR; + uint8_t RESERVED7[2]; + __IO uint16_t HCUPR; + uint8_t RESERVED8[2]; + __IO uint16_t HCDOR; + uint8_t RESERVED9[2]; + __IO uint16_t ICONR; + uint8_t RESERVED10[2]; + __IO uint16_t ECONR; + uint8_t RESERVED11[2]; + __IO uint16_t FCONR; + uint8_t RESERVED12[2]; + __IO uint16_t STFLR; + uint8_t RESERVED13[34]; + __IO uint16_t BCONR1; + uint8_t RESERVED14[6]; + __IO uint16_t BCONR2; + uint8_t RESERVED15[54]; + __IO uint16_t CCONR1; + uint8_t RESERVED16[2]; + __IO uint16_t CCONR2; + uint8_t RESERVED17[2]; + __IO uint16_t CCONR3; + uint8_t RESERVED18[2]; + __IO uint16_t CCONR4; + uint8_t RESERVED19[50]; + __IO uint16_t PCONR1; + uint8_t RESERVED20[2]; + __IO uint16_t PCONR2; + uint8_t RESERVED21[2]; + __IO uint16_t PCONR3; + uint8_t RESERVED22[2]; + __IO uint16_t PCONR4; +} CM_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __I uint32_t DR0; + __I uint32_t DR1; +} CM_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct { + __I uint32_t SR; + __IO uint32_t DR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; + __I uint32_t LBMC; +} CM_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct { + __IO uint32_t GVBUSCFG; + uint8_t RESERVED0[4]; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __I uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __I uint32_t GRXSTSR; + __I uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t HNPTXFSIZ; + __I uint32_t HNPTXSTS; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[20]; + __IO uint32_t GLPMCFG; + uint8_t RESERVED3[168]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + __IO uint32_t DIEPTXF6; + __IO uint32_t DIEPTXF7; + __IO uint32_t DIEPTXF8; + __IO uint32_t DIEPTXF9; + __IO uint32_t DIEPTXF10; + __IO uint32_t DIEPTXF11; + __IO uint32_t DIEPTXF12; + __IO uint32_t DIEPTXF13; + __IO uint32_t DIEPTXF14; + __IO uint32_t DIEPTXF15; + uint8_t RESERVED4[704]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __I uint32_t HFNUM; + uint8_t RESERVED5[4]; + __I uint32_t HPTXSTS; + __I uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED6[36]; + __I uint32_t HPRT; + uint8_t RESERVED7[188]; + __IO uint32_t HCCHAR0; + uint8_t RESERVED8[4]; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED9[8]; + __IO uint32_t HCCHAR1; + uint8_t RESERVED10[4]; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED11[8]; + __IO uint32_t HCCHAR2; + uint8_t RESERVED12[4]; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED13[8]; + __IO uint32_t HCCHAR3; + uint8_t RESERVED14[4]; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED15[8]; + __IO uint32_t HCCHAR4; + uint8_t RESERVED16[4]; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED17[8]; + __IO uint32_t HCCHAR5; + uint8_t RESERVED18[4]; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED19[8]; + __IO uint32_t HCCHAR6; + uint8_t RESERVED20[4]; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED21[8]; + __IO uint32_t HCCHAR7; + uint8_t RESERVED22[4]; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED23[8]; + __IO uint32_t HCCHAR8; + uint8_t RESERVED24[4]; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED25[8]; + __IO uint32_t HCCHAR9; + uint8_t RESERVED26[4]; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED27[8]; + __IO uint32_t HCCHAR10; + uint8_t RESERVED28[4]; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED29[8]; + __IO uint32_t HCCHAR11; + uint8_t RESERVED30[4]; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED31[8]; + __IO uint32_t HCCHAR12; + uint8_t RESERVED32[4]; + __IO uint32_t HCINT12; + __IO uint32_t HCINTMSK12; + __IO uint32_t HCTSIZ12; + __IO uint32_t HCDMA12; + uint8_t RESERVED33[8]; + __IO uint32_t HCCHAR13; + uint8_t RESERVED34[4]; + __IO uint32_t HCINT13; + __IO uint32_t HCINTMSK13; + __IO uint32_t HCTSIZ13; + __IO uint32_t HCDMA13; + uint8_t RESERVED35[8]; + __IO uint32_t HCCHAR14; + uint8_t RESERVED36[4]; + __IO uint32_t HCINT14; + __IO uint32_t HCINTMSK14; + __IO uint32_t HCTSIZ14; + __IO uint32_t HCDMA14; + uint8_t RESERVED37[8]; + __IO uint32_t HCCHAR15; + uint8_t RESERVED38[4]; + __IO uint32_t HCINT15; + __IO uint32_t HCINTMSK15; + __IO uint32_t HCTSIZ15; + __IO uint32_t HCDMA15; + uint8_t RESERVED39[264]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __I uint32_t DSTS; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED41[20]; + __IO uint32_t DIEPEMPMSK; + uint8_t RESERVED42[200]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __I uint32_t DTXFSTS0; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __I uint32_t DTXFSTS1; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __I uint32_t DTXFSTS2; + uint8_t RESERVED51[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED52[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED53[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __I uint32_t DTXFSTS3; + uint8_t RESERVED54[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED55[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED56[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __I uint32_t DTXFSTS4; + uint8_t RESERVED57[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED58[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED59[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __I uint32_t DTXFSTS5; + uint8_t RESERVED60[4]; + __IO uint32_t DIEPCTL6; + uint8_t RESERVED61[4]; + __IO uint32_t DIEPINT6; + uint8_t RESERVED62[4]; + __IO uint32_t DIEPTSIZ6; + __IO uint32_t DIEPDMA6; + __I uint32_t DTXFSTS6; + uint8_t RESERVED63[4]; + __IO uint32_t DIEPCTL7; + uint8_t RESERVED64[4]; + __IO uint32_t DIEPINT7; + uint8_t RESERVED65[4]; + __IO uint32_t DIEPTSIZ7; + __IO uint32_t DIEPDMA7; + __I uint32_t DTXFSTS7; + uint8_t RESERVED66[4]; + __IO uint32_t DIEPCTL8; + uint8_t RESERVED67[4]; + __IO uint32_t DIEPINT8; + uint8_t RESERVED68[4]; + __IO uint32_t DIEPTSIZ8; + __IO uint32_t DIEPDMA8; + __I uint32_t DTXFSTS8; + uint8_t RESERVED69[4]; + __IO uint32_t DIEPCTL9; + uint8_t RESERVED70[4]; + __IO uint32_t DIEPINT9; + uint8_t RESERVED71[4]; + __IO uint32_t DIEPTSIZ9; + __IO uint32_t DIEPDMA9; + __I uint32_t DTXFSTS9; + uint8_t RESERVED72[4]; + __IO uint32_t DIEPCTL10; + uint8_t RESERVED73[4]; + __IO uint32_t DIEPINT10; + uint8_t RESERVED74[4]; + __IO uint32_t DIEPTSIZ10; + __IO uint32_t DIEPDMA10; + __I uint32_t DTXFSTS10; + uint8_t RESERVED75[4]; + __IO uint32_t DIEPCTL11; + uint8_t RESERVED76[4]; + __IO uint32_t DIEPINT11; + uint8_t RESERVED77[4]; + __IO uint32_t DIEPTSIZ11; + __IO uint32_t DIEPDMA11; + __I uint32_t DTXFSTS11; + uint8_t RESERVED78[4]; + __IO uint32_t DIEPCTL12; + uint8_t RESERVED79[4]; + __IO uint32_t DIEPINT12; + uint8_t RESERVED80[4]; + __IO uint32_t DIEPTSIZ12; + __IO uint32_t DIEPDMA12; + __I uint32_t DTXFSTS12; + uint8_t RESERVED81[4]; + __IO uint32_t DIEPCTL13; + uint8_t RESERVED82[4]; + __IO uint32_t DIEPINT13; + uint8_t RESERVED83[4]; + __IO uint32_t DIEPTSIZ13; + __IO uint32_t DIEPDMA13; + __I uint32_t DTXFSTS13; + uint8_t RESERVED84[4]; + __IO uint32_t DIEPCTL14; + uint8_t RESERVED85[4]; + __IO uint32_t DIEPINT14; + uint8_t RESERVED86[4]; + __IO uint32_t DIEPTSIZ14; + __IO uint32_t DIEPDMA14; + __I uint32_t DTXFSTS14; + uint8_t RESERVED87[4]; + __IO uint32_t DIEPCTL15; + uint8_t RESERVED88[4]; + __IO uint32_t DIEPINT15; + uint8_t RESERVED89[4]; + __IO uint32_t DIEPTSIZ15; + __IO uint32_t DIEPDMA15; + __I uint32_t DTXFSTS15; + uint8_t RESERVED90[4]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED91[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED92[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED93[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED94[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED95[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED96[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED97[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED98[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED99[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED100[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED101[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED102[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED103[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED104[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED105[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED106[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED107[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED108[8]; + __IO uint32_t DOEPCTL6; + uint8_t RESERVED109[4]; + __IO uint32_t DOEPINT6; + uint8_t RESERVED110[4]; + __IO uint32_t DOEPTSIZ6; + __IO uint32_t DOEPDMA6; + uint8_t RESERVED111[8]; + __IO uint32_t DOEPCTL7; + uint8_t RESERVED112[4]; + __IO uint32_t DOEPINT7; + uint8_t RESERVED113[4]; + __IO uint32_t DOEPTSIZ7; + __IO uint32_t DOEPDMA7; + uint8_t RESERVED114[8]; + __IO uint32_t DOEPCTL8; + uint8_t RESERVED115[4]; + __IO uint32_t DOEPINT8; + uint8_t RESERVED116[4]; + __IO uint32_t DOEPTSIZ8; + __IO uint32_t DOEPDMA8; + uint8_t RESERVED117[8]; + __IO uint32_t DOEPCTL9; + uint8_t RESERVED118[4]; + __IO uint32_t DOEPINT9; + uint8_t RESERVED119[4]; + __IO uint32_t DOEPTSIZ9; + __IO uint32_t DOEPDMA9; + uint8_t RESERVED120[8]; + __IO uint32_t DOEPCTL10; + uint8_t RESERVED121[4]; + __IO uint32_t DOEPINT10; + uint8_t RESERVED122[4]; + __IO uint32_t DOEPTSIZ10; + __IO uint32_t DOEPDMA10; + uint8_t RESERVED123[8]; + __IO uint32_t DOEPCTL11; + uint8_t RESERVED124[4]; + __IO uint32_t DOEPINT11; + uint8_t RESERVED125[4]; + __IO uint32_t DOEPTSIZ11; + __IO uint32_t DOEPDMA11; + uint8_t RESERVED126[8]; + __IO uint32_t DOEPCTL12; + uint8_t RESERVED127[4]; + __IO uint32_t DOEPINT12; + uint8_t RESERVED128[4]; + __IO uint32_t DOEPTSIZ12; + __IO uint32_t DOEPDMA12; + uint8_t RESERVED129[8]; + __IO uint32_t DOEPCTL13; + uint8_t RESERVED130[4]; + __IO uint32_t DOEPINT13; + uint8_t RESERVED131[4]; + __IO uint32_t DOEPTSIZ13; + __IO uint32_t DOEPDMA13; + uint8_t RESERVED132[8]; + __IO uint32_t DOEPCTL14; + uint8_t RESERVED133[4]; + __IO uint32_t DOEPINT14; + uint8_t RESERVED134[4]; + __IO uint32_t DOEPTSIZ14; + __IO uint32_t DOEPDMA14; + uint8_t RESERVED135[8]; + __IO uint32_t DOEPCTL15; + uint8_t RESERVED136[4]; + __IO uint32_t DOEPINT15; + uint8_t RESERVED137[4]; + __IO uint32_t DOEPTSIZ15; + __IO uint32_t DOEPDMA15; + uint8_t RESERVED138[264]; + __IO uint32_t GCCTL; +} CM_USBFS_TypeDef; + +/** + * @brief USBHS + */ +typedef struct { + __IO uint32_t GVBUSCFG; + uint8_t RESERVED0[4]; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __I uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __I uint32_t GRXSTSR; + __I uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t HNPTXFSIZ; + __I uint32_t HNPTXSTS; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[20]; + __IO uint32_t GLPMCFG; + uint8_t RESERVED3[168]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + __IO uint32_t DIEPTXF6; + __IO uint32_t DIEPTXF7; + __IO uint32_t DIEPTXF8; + __IO uint32_t DIEPTXF9; + __IO uint32_t DIEPTXF10; + __IO uint32_t DIEPTXF11; + __IO uint32_t DIEPTXF12; + __IO uint32_t DIEPTXF13; + __IO uint32_t DIEPTXF14; + __IO uint32_t DIEPTXF15; + uint8_t RESERVED4[704]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __I uint32_t HFNUM; + uint8_t RESERVED5[4]; + __I uint32_t HPTXSTS; + __I uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED6[36]; + __I uint32_t HPRT; + uint8_t RESERVED7[188]; + __IO uint32_t HCCHAR0; + __IO uint32_t HCSPLT0; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + __IO uint32_t HCCHAR1; + __IO uint32_t HCSPLT1; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED9[8]; + __IO uint32_t HCCHAR2; + __IO uint32_t HCSPLT2; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR3; + __IO uint32_t HCSPLT3; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED11[8]; + __IO uint32_t HCCHAR4; + __IO uint32_t HCSPLT4; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR5; + __IO uint32_t HCSPLT5; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED13[8]; + __IO uint32_t HCCHAR6; + __IO uint32_t HCSPLT6; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR7; + __IO uint32_t HCSPLT7; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED15[8]; + __IO uint32_t HCCHAR8; + __IO uint32_t HCSPLT8; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR9; + __IO uint32_t HCSPLT9; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED17[8]; + __IO uint32_t HCCHAR10; + __IO uint32_t HCSPLT10; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR11; + __IO uint32_t HCSPLT11; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED19[8]; + __IO uint32_t HCCHAR12; + __IO uint32_t HCSPLT12; + __IO uint32_t HCINT12; + __IO uint32_t HCINTMSK12; + __IO uint32_t HCTSIZ12; + __IO uint32_t HCDMA12; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR13; + __IO uint32_t HCSPLT13; + __IO uint32_t HCINT13; + __IO uint32_t HCINTMSK13; + __IO uint32_t HCTSIZ13; + __IO uint32_t HCDMA13; + uint8_t RESERVED21[8]; + __IO uint32_t HCCHAR14; + __IO uint32_t HCSPLT14; + __IO uint32_t HCINT14; + __IO uint32_t HCINTMSK14; + __IO uint32_t HCTSIZ14; + __IO uint32_t HCDMA14; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR15; + __IO uint32_t HCSPLT15; + __IO uint32_t HCINT15; + __IO uint32_t HCINTMSK15; + __IO uint32_t HCTSIZ15; + __IO uint32_t HCDMA15; + uint8_t RESERVED23[264]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __I uint32_t DSTS; + uint8_t RESERVED24[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED25[16]; + __IO uint32_t DTHRCTL; + __IO uint32_t DIEPEMPMSK; + __IO uint32_t DEACHINT; + __IO uint32_t DEACHINTMSK; + uint8_t RESERVED26[4]; + __IO uint32_t DIEPEACHMSK1; + uint8_t RESERVED27[60]; + __IO uint32_t DOEPEACHMSK1; + uint8_t RESERVED28[120]; + __I uint32_t DIEPCTL0; + uint8_t RESERVED29[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED30[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __I uint32_t DTXFSTS0; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED32[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED33[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __I uint32_t DTXFSTS1; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __I uint32_t DTXFSTS2; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __I uint32_t DTXFSTS3; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __I uint32_t DTXFSTS4; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __I uint32_t DTXFSTS5; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPCTL6; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPINT6; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPTSIZ6; + __IO uint32_t DIEPDMA6; + __I uint32_t DTXFSTS6; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPCTL7; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPINT7; + uint8_t RESERVED51[4]; + __IO uint32_t DIEPTSIZ7; + __IO uint32_t DIEPDMA7; + __I uint32_t DTXFSTS7; + uint8_t RESERVED52[4]; + __IO uint32_t DIEPCTL8; + uint8_t RESERVED53[4]; + __IO uint32_t DIEPINT8; + uint8_t RESERVED54[4]; + __IO uint32_t DIEPTSIZ8; + __IO uint32_t DIEPDMA8; + __I uint32_t DTXFSTS8; + uint8_t RESERVED55[4]; + __IO uint32_t DIEPCTL9; + uint8_t RESERVED56[4]; + __IO uint32_t DIEPINT9; + uint8_t RESERVED57[4]; + __IO uint32_t DIEPTSIZ9; + __IO uint32_t DIEPDMA9; + __I uint32_t DTXFSTS9; + uint8_t RESERVED58[4]; + __IO uint32_t DIEPCTL10; + uint8_t RESERVED59[4]; + __IO uint32_t DIEPINT10; + uint8_t RESERVED60[4]; + __IO uint32_t DIEPTSIZ10; + __IO uint32_t DIEPDMA10; + __I uint32_t DTXFSTS10; + uint8_t RESERVED61[4]; + __IO uint32_t DIEPCTL11; + uint8_t RESERVED62[4]; + __IO uint32_t DIEPINT11; + uint8_t RESERVED63[4]; + __IO uint32_t DIEPTSIZ11; + __IO uint32_t DIEPDMA11; + __I uint32_t DTXFSTS11; + uint8_t RESERVED64[4]; + __IO uint32_t DIEPCTL12; + uint8_t RESERVED65[4]; + __IO uint32_t DIEPINT12; + uint8_t RESERVED66[4]; + __IO uint32_t DIEPTSIZ12; + __IO uint32_t DIEPDMA12; + __I uint32_t DTXFSTS12; + uint8_t RESERVED67[4]; + __IO uint32_t DIEPCTL13; + uint8_t RESERVED68[4]; + __IO uint32_t DIEPINT13; + uint8_t RESERVED69[4]; + __IO uint32_t DIEPTSIZ13; + __IO uint32_t DIEPDMA13; + __I uint32_t DTXFSTS13; + uint8_t RESERVED70[4]; + __IO uint32_t DIEPCTL14; + uint8_t RESERVED71[4]; + __IO uint32_t DIEPINT14; + uint8_t RESERVED72[4]; + __IO uint32_t DIEPTSIZ14; + __IO uint32_t DIEPDMA14; + __I uint32_t DTXFSTS14; + uint8_t RESERVED73[4]; + __IO uint32_t DIEPCTL15; + uint8_t RESERVED74[4]; + __IO uint32_t DIEPINT15; + uint8_t RESERVED75[4]; + __IO uint32_t DIEPTSIZ15; + __IO uint32_t DIEPDMA15; + __I uint32_t DTXFSTS15; + uint8_t RESERVED76[4]; + __I uint32_t DOEPCTL0; + uint8_t RESERVED77[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED78[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED79[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED80[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED81[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED82[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED83[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED84[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED85[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED86[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED87[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED88[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED89[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED90[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED91[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED92[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED93[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED94[8]; + __IO uint32_t DOEPCTL6; + uint8_t RESERVED95[4]; + __IO uint32_t DOEPINT6; + uint8_t RESERVED96[4]; + __IO uint32_t DOEPTSIZ6; + __IO uint32_t DOEPDMA6; + uint8_t RESERVED97[8]; + __IO uint32_t DOEPCTL7; + uint8_t RESERVED98[4]; + __IO uint32_t DOEPINT7; + uint8_t RESERVED99[4]; + __IO uint32_t DOEPTSIZ7; + __IO uint32_t DOEPDMA7; + uint8_t RESERVED100[8]; + __IO uint32_t DOEPCTL8; + uint8_t RESERVED101[4]; + __IO uint32_t DOEPINT8; + uint8_t RESERVED102[4]; + __IO uint32_t DOEPTSIZ8; + __IO uint32_t DOEPDMA8; + uint8_t RESERVED103[8]; + __IO uint32_t DOEPCTL9; + uint8_t RESERVED104[4]; + __IO uint32_t DOEPINT9; + uint8_t RESERVED105[4]; + __IO uint32_t DOEPTSIZ9; + __IO uint32_t DOEPDMA9; + uint8_t RESERVED106[8]; + __IO uint32_t DOEPCTL10; + uint8_t RESERVED107[4]; + __IO uint32_t DOEPINT10; + uint8_t RESERVED108[4]; + __IO uint32_t DOEPTSIZ10; + __IO uint32_t DOEPDMA10; + uint8_t RESERVED109[8]; + __IO uint32_t DOEPCTL11; + uint8_t RESERVED110[4]; + __IO uint32_t DOEPINT11; + uint8_t RESERVED111[4]; + __IO uint32_t DOEPTSIZ11; + __IO uint32_t DOEPDMA11; + uint8_t RESERVED112[8]; + __IO uint32_t DOEPCTL12; + uint8_t RESERVED113[4]; + __IO uint32_t DOEPINT12; + uint8_t RESERVED114[4]; + __IO uint32_t DOEPTSIZ12; + __IO uint32_t DOEPDMA12; + uint8_t RESERVED115[8]; + __IO uint32_t DOEPCTL13; + uint8_t RESERVED116[4]; + __IO uint32_t DOEPINT13; + uint8_t RESERVED117[4]; + __IO uint32_t DOEPTSIZ13; + __IO uint32_t DOEPDMA13; + uint8_t RESERVED118[8]; + __IO uint32_t DOEPCTL14; + uint8_t RESERVED119[4]; + __IO uint32_t DOEPINT14; + uint8_t RESERVED120[4]; + __IO uint32_t DOEPTSIZ14; + __IO uint32_t DOEPDMA14; + uint8_t RESERVED121[8]; + __IO uint32_t DOEPCTL15; + uint8_t RESERVED122[4]; + __IO uint32_t DOEPINT15; + uint8_t RESERVED123[4]; + __IO uint32_t DOEPTSIZ15; + __IO uint32_t DOEPDMA15; + uint8_t RESERVED124[264]; + __IO uint32_t GCCTL; +} CM_USBHS_TypeDef; + +/** + * @brief WDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_WDT_TypeDef; + +/******************************************************************************/ +/* Memory Base Address */ +/******************************************************************************/ +#define EFM_BASE (0x00000000UL) /*!< EFM base address in the alias region */ +#define SRAM_BASE (0x1FFE0000UL) /*!< SRAM base address in the alias region */ +#define SMC_BASE (0x60000000UL) /*!< SMC base address in the alias region */ +#define DMC_BASE (0x80000000UL) /*!< DMC base address in the alias region */ +#define QSPI_BASE (0x98000000UL) /*!< QSPI base address in the alias region */ + +/******************************************************************************/ +/* Device Specific Peripheral Base Address */ +/******************************************************************************/ +#define CM_ADC1_BASE (0x40040000UL) +#define CM_ADC2_BASE (0x40040400UL) +#define CM_ADC3_BASE (0x40040800UL) +#define CM_AES_BASE (0x40008000UL) +#define CM_AOS_BASE (0x40010800UL) +#define CM_CAN1_BASE (0x40009000UL) +#define CM_CAN2_BASE (0x40078000UL) +#define CM_CMP1_BASE (0x4004A000UL) +#define CM_CMP2_BASE (0x4004A010UL) +#define CM_CMP3_BASE (0x4004A400UL) +#define CM_CMP4_BASE (0x4004A410UL) +#define CM_CMU_BASE (0x4004C400UL) +#define CM_CRC_BASE (0x40008C00UL) +#define CM_CTC_BASE (0x40049C00UL) +#define CM_DAC1_BASE (0x40041000UL) +#define CM_DAC2_BASE (0x40041400UL) +#define CM_DBGC_BASE (0xE0042000UL) +#define CM_DCU1_BASE (0x40056000UL) +#define CM_DCU2_BASE (0x40056400UL) +#define CM_DCU3_BASE (0x40056800UL) +#define CM_DCU4_BASE (0x40056C00UL) +#define CM_DCU5_BASE (0x40057000UL) +#define CM_DCU6_BASE (0x40057400UL) +#define CM_DCU7_BASE (0x40057800UL) +#define CM_DCU8_BASE (0x40057C00UL) +#define CM_DMA1_BASE (0x40053000UL) +#define CM_DMA2_BASE (0x40053400UL) +#define CM_DMC_BASE (0x88000400UL) +#define CM_DVP_BASE (0x40055800UL) +#define CM_EFM_BASE (0x40010400UL) +#define CM_EMB0_BASE (0x40017C00UL) +#define CM_EMB1_BASE (0x40017C20UL) +#define CM_EMB2_BASE (0x40017C40UL) +#define CM_EMB3_BASE (0x40017C60UL) +#define CM_EMB4_BASE (0x40017C80UL) +#define CM_EMB5_BASE (0x40017CA0UL) +#define CM_EMB6_BASE (0x40017CC0UL) +#define CM_ETH_BASE (0x40050000UL) +#define CM_FCM_BASE (0x40048400UL) +#define CM_FMAC1_BASE (0x40058000UL) +#define CM_FMAC2_BASE (0x40058400UL) +#define CM_FMAC3_BASE (0x40058800UL) +#define CM_FMAC4_BASE (0x40058C00UL) +#define CM_GPIO_BASE (0x40053800UL) +#define CM_HASH_BASE (0x40008400UL) +#define CM_HRPWM_BASE (0x4003C000UL) +#define CM_I2C1_BASE (0x4004E000UL) +#define CM_I2C2_BASE (0x4004E400UL) +#define CM_I2C3_BASE (0x4004E800UL) +#define CM_I2C4_BASE (0x4004EC00UL) +#define CM_I2C5_BASE (0x4004F000UL) +#define CM_I2C6_BASE (0x4004F400UL) +#define CM_I2S1_BASE (0x4001E000UL) +#define CM_I2S2_BASE (0x4001E400UL) +#define CM_I2S3_BASE (0x40022000UL) +#define CM_I2S4_BASE (0x40022400UL) +#define CM_ICG_BASE (0x00000400UL) +#define CM_INTC_BASE (0x40051000UL) +#define CM_KEYSCAN_BASE (0x40050C00UL) +#define CM_MAU_BASE (0x40055000UL) +#define CM_MPU_BASE (0x40050000UL) +#define CM_NFC_BASE (0x88100000UL) +#define CM_OTS_BASE (0x40010600UL) +#define CM_PERIC_BASE (0x40055400UL) +#define CM_PWC_BASE (0x40048000UL) +#define CM_QSPI_BASE (0x9C000000UL) +#define CM_RMU_BASE (0x4004CC00UL) +#define CM_RTC_BASE (0x4004C000UL) +#define CM_SDIOC1_BASE (0x40070000UL) +#define CM_SDIOC2_BASE (0x40078400UL) +#define CM_SMC_BASE (0x88000000UL) +#define CM_SPI1_BASE (0x4001C000UL) +#define CM_SPI2_BASE (0x4001C400UL) +#define CM_SPI3_BASE (0x4001C800UL) +#define CM_SPI4_BASE (0x40020000UL) +#define CM_SPI5_BASE (0x40020400UL) +#define CM_SPI6_BASE (0x40020800UL) +#define CM_SRAMC_BASE (0x40050800UL) +#define CM_SWDT_BASE (0x40049400UL) +#define CM_TMR0_1_BASE (0x40024000UL) +#define CM_TMR0_2_BASE (0x40024400UL) +#define CM_TMR2_1_BASE (0x40024800UL) +#define CM_TMR2_2_BASE (0x40024C00UL) +#define CM_TMR2_3_BASE (0x40025000UL) +#define CM_TMR2_4_BASE (0x40025400UL) +#define CM_TMR4_1_BASE (0x40038000UL) +#define CM_TMR4_2_BASE (0x40038400UL) +#define CM_TMR4_3_BASE (0x40038800UL) +#define CM_TMR6_1_BASE (0x40018000UL) +#define CM_TMR6_2_BASE (0x40018400UL) +#define CM_TMR6_3_BASE (0x40018800UL) +#define CM_TMR6_4_BASE (0x40018C00UL) +#define CM_TMR6_5_BASE (0x40019000UL) +#define CM_TMR6_6_BASE (0x40019400UL) +#define CM_TMR6_7_BASE (0x40019800UL) +#define CM_TMR6_8_BASE (0x40019C00UL) +#define CM_TMR6CR_BASE (0x40018000UL) +#define CM_TMRA_1_BASE (0x4003A000UL) +#define CM_TMRA_10_BASE (0x40027400UL) +#define CM_TMRA_11_BASE (0x40027800UL) +#define CM_TMRA_12_BASE (0x40027C00UL) +#define CM_TMRA_2_BASE (0x4003A400UL) +#define CM_TMRA_3_BASE (0x4003A800UL) +#define CM_TMRA_4_BASE (0x4003AC00UL) +#define CM_TMRA_5_BASE (0x40026000UL) +#define CM_TMRA_6_BASE (0x40026400UL) +#define CM_TMRA_7_BASE (0x40026800UL) +#define CM_TMRA_8_BASE (0x40026C00UL) +#define CM_TMRA_9_BASE (0x40027000UL) +#define CM_TRNG_BASE (0x40042000UL) +#define CM_USART1_BASE (0x4001CC00UL) +#define CM_USART10_BASE (0x40021C00UL) +#define CM_USART2_BASE (0x4001D000UL) +#define CM_USART3_BASE (0x4001D400UL) +#define CM_USART4_BASE (0x4001D800UL) +#define CM_USART5_BASE (0x4001DC00UL) +#define CM_USART6_BASE (0x40020C00UL) +#define CM_USART7_BASE (0x40021000UL) +#define CM_USART8_BASE (0x40021400UL) +#define CM_USART9_BASE (0x40021800UL) +#define CM_USBFS_BASE (0x40080000UL) +#define CM_USBHS_BASE (0x400C0000UL) +#define CM_WDT_BASE (0x40049000UL) + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ +#define CM_ADC1 ((CM_ADC_TypeDef *)CM_ADC1_BASE) +#define CM_ADC2 ((CM_ADC_TypeDef *)CM_ADC2_BASE) +#define CM_ADC3 ((CM_ADC_TypeDef *)CM_ADC3_BASE) +#define CM_AES ((CM_AES_TypeDef *)CM_AES_BASE) +#define CM_AOS ((CM_AOS_TypeDef *)CM_AOS_BASE) +#define CM_CAN1 ((CM_CAN_TypeDef *)CM_CAN1_BASE) +#define CM_CAN2 ((CM_CAN_TypeDef *)CM_CAN2_BASE) +#define CM_CMP1 ((CM_CMP_TypeDef *)CM_CMP1_BASE) +#define CM_CMP2 ((CM_CMP_TypeDef *)CM_CMP2_BASE) +#define CM_CMP3 ((CM_CMP_TypeDef *)CM_CMP3_BASE) +#define CM_CMP4 ((CM_CMP_TypeDef *)CM_CMP4_BASE) +#define CM_CMU ((CM_CMU_TypeDef *)CM_CMU_BASE) +#define CM_CRC ((CM_CRC_TypeDef *)CM_CRC_BASE) +#define CM_CTC ((CM_CTC_TypeDef *)CM_CTC_BASE) +#define CM_DAC1 ((CM_DAC_TypeDef *)CM_DAC1_BASE) +#define CM_DAC2 ((CM_DAC_TypeDef *)CM_DAC2_BASE) +#define CM_DBGC ((CM_DBGC_TypeDef *)CM_DBGC_BASE) +#define CM_DCU1 ((CM_DCU_TypeDef *)CM_DCU1_BASE) +#define CM_DCU2 ((CM_DCU_TypeDef *)CM_DCU2_BASE) +#define CM_DCU3 ((CM_DCU_TypeDef *)CM_DCU3_BASE) +#define CM_DCU4 ((CM_DCU_TypeDef *)CM_DCU4_BASE) +#define CM_DCU5 ((CM_DCU_TypeDef *)CM_DCU5_BASE) +#define CM_DCU6 ((CM_DCU_TypeDef *)CM_DCU6_BASE) +#define CM_DCU7 ((CM_DCU_TypeDef *)CM_DCU7_BASE) +#define CM_DCU8 ((CM_DCU_TypeDef *)CM_DCU8_BASE) +#define CM_DMA1 ((CM_DMA_TypeDef *)CM_DMA1_BASE) +#define CM_DMA2 ((CM_DMA_TypeDef *)CM_DMA2_BASE) +#define CM_DMC ((CM_DMC_TypeDef *)CM_DMC_BASE) +#define CM_DVP ((CM_DVP_TypeDef *)CM_DVP_BASE) +#define CM_EFM ((CM_EFM_TypeDef *)CM_EFM_BASE) +#define CM_EMB0 ((CM_EMB_TypeDef *)CM_EMB0_BASE) +#define CM_EMB1 ((CM_EMB_TypeDef *)CM_EMB1_BASE) +#define CM_EMB2 ((CM_EMB_TypeDef *)CM_EMB2_BASE) +#define CM_EMB3 ((CM_EMB_TypeDef *)CM_EMB3_BASE) +#define CM_EMB4 ((CM_EMB_TypeDef *)CM_EMB4_BASE) +#define CM_EMB5 ((CM_EMB_TypeDef *)CM_EMB5_BASE) +#define CM_EMB6 ((CM_EMB_TypeDef *)CM_EMB6_BASE) +#define CM_ETH ((CM_ETH_TypeDef *)CM_ETH_BASE) +#define CM_FCM ((CM_FCM_TypeDef *)CM_FCM_BASE) +#define CM_FMAC1 ((CM_FMAC_TypeDef *)CM_FMAC1_BASE) +#define CM_FMAC2 ((CM_FMAC_TypeDef *)CM_FMAC2_BASE) +#define CM_FMAC3 ((CM_FMAC_TypeDef *)CM_FMAC3_BASE) +#define CM_FMAC4 ((CM_FMAC_TypeDef *)CM_FMAC4_BASE) +#define CM_GPIO ((CM_GPIO_TypeDef *)CM_GPIO_BASE) +#define CM_HASH ((CM_HASH_TypeDef *)CM_HASH_BASE) +#define CM_HRPWM ((CM_HRPWM_TypeDef *)CM_HRPWM_BASE) +#define CM_I2C1 ((CM_I2C_TypeDef *)CM_I2C1_BASE) +#define CM_I2C2 ((CM_I2C_TypeDef *)CM_I2C2_BASE) +#define CM_I2C3 ((CM_I2C_TypeDef *)CM_I2C3_BASE) +#define CM_I2C4 ((CM_I2C_TypeDef *)CM_I2C4_BASE) +#define CM_I2C5 ((CM_I2C_TypeDef *)CM_I2C5_BASE) +#define CM_I2C6 ((CM_I2C_TypeDef *)CM_I2C6_BASE) +#define CM_I2S1 ((CM_I2S_TypeDef *)CM_I2S1_BASE) +#define CM_I2S2 ((CM_I2S_TypeDef *)CM_I2S2_BASE) +#define CM_I2S3 ((CM_I2S_TypeDef *)CM_I2S3_BASE) +#define CM_I2S4 ((CM_I2S_TypeDef *)CM_I2S4_BASE) +#define CM_ICG ((CM_ICG_TypeDef *)CM_ICG_BASE) +#define CM_INTC ((CM_INTC_TypeDef *)CM_INTC_BASE) +#define CM_KEYSCAN ((CM_KEYSCAN_TypeDef *)CM_KEYSCAN_BASE) +#define CM_MAU ((CM_MAU_TypeDef *)CM_MAU_BASE) +#define CM_MPU ((CM_MPU_TypeDef *)CM_MPU_BASE) +#define CM_NFC ((CM_NFC_TypeDef *)CM_NFC_BASE) +#define CM_OTS ((CM_OTS_TypeDef *)CM_OTS_BASE) +#define CM_PERIC ((CM_PERIC_TypeDef *)CM_PERIC_BASE) +#define CM_PWC ((CM_PWC_TypeDef *)CM_PWC_BASE) +#define CM_QSPI ((CM_QSPI_TypeDef *)CM_QSPI_BASE) +#define CM_RMU ((CM_RMU_TypeDef *)CM_RMU_BASE) +#define CM_RTC ((CM_RTC_TypeDef *)CM_RTC_BASE) +#define CM_SDIOC1 ((CM_SDIOC_TypeDef *)CM_SDIOC1_BASE) +#define CM_SDIOC2 ((CM_SDIOC_TypeDef *)CM_SDIOC2_BASE) +#define CM_SMC ((CM_SMC_TypeDef *)CM_SMC_BASE) +#define CM_SPI1 ((CM_SPI_TypeDef *)CM_SPI1_BASE) +#define CM_SPI2 ((CM_SPI_TypeDef *)CM_SPI2_BASE) +#define CM_SPI3 ((CM_SPI_TypeDef *)CM_SPI3_BASE) +#define CM_SPI4 ((CM_SPI_TypeDef *)CM_SPI4_BASE) +#define CM_SPI5 ((CM_SPI_TypeDef *)CM_SPI5_BASE) +#define CM_SPI6 ((CM_SPI_TypeDef *)CM_SPI6_BASE) +#define CM_SRAMC ((CM_SRAMC_TypeDef *)CM_SRAMC_BASE) +#define CM_SWDT ((CM_SWDT_TypeDef *)CM_SWDT_BASE) +#define CM_TMR0_1 ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE) +#define CM_TMR0_2 ((CM_TMR0_TypeDef *)CM_TMR0_2_BASE) +#define CM_TMR2_1 ((CM_TMR2_TypeDef *)CM_TMR2_1_BASE) +#define CM_TMR2_2 ((CM_TMR2_TypeDef *)CM_TMR2_2_BASE) +#define CM_TMR2_3 ((CM_TMR2_TypeDef *)CM_TMR2_3_BASE) +#define CM_TMR2_4 ((CM_TMR2_TypeDef *)CM_TMR2_4_BASE) +#define CM_TMR4_1 ((CM_TMR4_TypeDef *)CM_TMR4_1_BASE) +#define CM_TMR4_2 ((CM_TMR4_TypeDef *)CM_TMR4_2_BASE) +#define CM_TMR4_3 ((CM_TMR4_TypeDef *)CM_TMR4_3_BASE) +#define CM_TMR6_1 ((CM_TMR6_TypeDef *)CM_TMR6_1_BASE) +#define CM_TMR6_2 ((CM_TMR6_TypeDef *)CM_TMR6_2_BASE) +#define CM_TMR6_3 ((CM_TMR6_TypeDef *)CM_TMR6_3_BASE) +#define CM_TMR6_4 ((CM_TMR6_TypeDef *)CM_TMR6_4_BASE) +#define CM_TMR6_5 ((CM_TMR6_TypeDef *)CM_TMR6_5_BASE) +#define CM_TMR6_6 ((CM_TMR6_TypeDef *)CM_TMR6_6_BASE) +#define CM_TMR6_7 ((CM_TMR6_TypeDef *)CM_TMR6_7_BASE) +#define CM_TMR6_8 ((CM_TMR6_TypeDef *)CM_TMR6_8_BASE) +#define CM_TMR6CR ((CM_TMR6CR_TypeDef *)CM_TMR6CR_BASE) +#define CM_TMRA_1 ((CM_TMRA_TypeDef *)CM_TMRA_1_BASE) +#define CM_TMRA_10 ((CM_TMRA_TypeDef *)CM_TMRA_10_BASE) +#define CM_TMRA_11 ((CM_TMRA_TypeDef *)CM_TMRA_11_BASE) +#define CM_TMRA_12 ((CM_TMRA_TypeDef *)CM_TMRA_12_BASE) +#define CM_TMRA_2 ((CM_TMRA_TypeDef *)CM_TMRA_2_BASE) +#define CM_TMRA_3 ((CM_TMRA_TypeDef *)CM_TMRA_3_BASE) +#define CM_TMRA_4 ((CM_TMRA_TypeDef *)CM_TMRA_4_BASE) +#define CM_TMRA_5 ((CM_TMRA_TypeDef *)CM_TMRA_5_BASE) +#define CM_TMRA_6 ((CM_TMRA_TypeDef *)CM_TMRA_6_BASE) +#define CM_TMRA_7 ((CM_TMRA_TypeDef *)CM_TMRA_7_BASE) +#define CM_TMRA_8 ((CM_TMRA_TypeDef *)CM_TMRA_8_BASE) +#define CM_TMRA_9 ((CM_TMRA_TypeDef *)CM_TMRA_9_BASE) +#define CM_TRNG ((CM_TRNG_TypeDef *)CM_TRNG_BASE) +#define CM_USART1 ((CM_USART_TypeDef *)CM_USART1_BASE) +#define CM_USART10 ((CM_USART_TypeDef *)CM_USART10_BASE) +#define CM_USART2 ((CM_USART_TypeDef *)CM_USART2_BASE) +#define CM_USART3 ((CM_USART_TypeDef *)CM_USART3_BASE) +#define CM_USART4 ((CM_USART_TypeDef *)CM_USART4_BASE) +#define CM_USART5 ((CM_USART_TypeDef *)CM_USART5_BASE) +#define CM_USART6 ((CM_USART_TypeDef *)CM_USART6_BASE) +#define CM_USART7 ((CM_USART_TypeDef *)CM_USART7_BASE) +#define CM_USART8 ((CM_USART_TypeDef *)CM_USART8_BASE) +#define CM_USART9 ((CM_USART_TypeDef *)CM_USART9_BASE) +#define CM_USBFS ((CM_USBFS_TypeDef *)CM_USBFS_BASE) +#define CM_USBHS ((CM_USBHS_TypeDef *)CM_USBHS_BASE) +#define CM_WDT ((CM_WDT_TypeDef *)CM_WDT_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0003U) +#define ADC_CR0_MS_0 (0x0001U) +#define ADC_CR0_MS_1 (0x0002U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x000FFFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x000FFFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x000FFFFFUL) + +/* Bit definition for ADC_EXCHSELR register */ +#define ADC_EXCHSELR_EXCHSEL (0x01U) + +/* Bit definition for ADC_SHCR register */ +#define ADC_SHCR_SHSST_POS (0U) +#define ADC_SHCR_SHSST (0x00FFU) +#define ADC_SHCR_SHSEL_POS (8U) +#define ADC_SHCR_SHSEL (0x0700U) + +/* Bit definition for ADC_SSTR register */ +#define ADC_SSTR (0xFFU) + +/* Bit definition for ADC_SSTRL register */ +#define ADC_SSTRL (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) +#define ADC_ISR_SASTPDF_POS (4U) +#define ADC_ISR_SASTPDF (0x10U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_ISCLRR register */ +#define ADC_ISCLRR_CLREOCAF_POS (0U) +#define ADC_ISCLRR_CLREOCAF (0x01U) +#define ADC_ISCLRR_CLREOCBF_POS (1U) +#define ADC_ISCLRR_CLREOCBF (0x02U) +#define ADC_ISCLRR_CLRSASTPDF_POS (4U) +#define ADC_ISCLRR_CLRSASTPDF (0x10U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCMD_0 (0x0010U) +#define ADC_SYNCCR_SYNCMD_1 (0x0020U) +#define ADC_SYNCCR_SYNCMD_2 (0x0040U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) + +/* Bit definition for ADC_DR register */ +#define ADC_DR (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWD0EN_POS (0U) +#define ADC_AWDCR_AWD0EN (0x0001U) +#define ADC_AWDCR_AWD0IEN_POS (1U) +#define ADC_AWDCR_AWD0IEN (0x0002U) +#define ADC_AWDCR_AWD0MD_POS (2U) +#define ADC_AWDCR_AWD0MD (0x0004U) +#define ADC_AWDCR_AWD1EN_POS (4U) +#define ADC_AWDCR_AWD1EN (0x0010U) +#define ADC_AWDCR_AWD1IEN_POS (5U) +#define ADC_AWDCR_AWD1IEN (0x0020U) +#define ADC_AWDCR_AWD1MD_POS (6U) +#define ADC_AWDCR_AWD1MD (0x0040U) +#define ADC_AWDCR_AWDCM_POS (8U) +#define ADC_AWDCR_AWDCM (0x0300U) +#define ADC_AWDCR_AWDCM_0 (0x0100U) +#define ADC_AWDCR_AWDCM_1 (0x0200U) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWD0F_POS (0U) +#define ADC_AWDSR_AWD0F (0x01U) +#define ADC_AWDSR_AWD1F_POS (1U) +#define ADC_AWDSR_AWD1F (0x02U) +#define ADC_AWDSR_AWDCMF_POS (4U) +#define ADC_AWDSR_AWDCMF (0x10U) + +/* Bit definition for ADC_AWDSCLRR register */ +#define ADC_AWDSCLRR_CLRAWD0F_POS (0U) +#define ADC_AWDSCLRR_CLRAWD0F (0x01U) +#define ADC_AWDSCLRR_CLRAWD1F_POS (1U) +#define ADC_AWDSCLRR_CLRAWD1F (0x02U) +#define ADC_AWDSCLRR_CLRAWDCMF_POS (4U) +#define ADC_AWDSCLRR_CLRAWDCMF (0x10U) + +/* Bit definition for ADC_AWD0DR0 register */ +#define ADC_AWD0DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD0DR1 register */ +#define ADC_AWD0DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD0CHSR register */ +#define ADC_AWD0CHSR_AWDCH (0x1FU) +#define ADC_AWD0CHSR_AWDCH_0 (0x01U) +#define ADC_AWD0CHSR_AWDCH_1 (0x02U) +#define ADC_AWD0CHSR_AWDCH_2 (0x04U) +#define ADC_AWD0CHSR_AWDCH_3 (0x08U) +#define ADC_AWD0CHSR_AWDCH_4 (0x10U) + +/* Bit definition for ADC_AWD1DR0 register */ +#define ADC_AWD1DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD1DR1 register */ +#define ADC_AWD1DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD1CHSR register */ +#define ADC_AWD1CHSR_AWDCH (0x1FU) + +/* Bit definition for ADC_PGACR register */ +#define ADC_PGACR_PGACTL_POS (0U) +#define ADC_PGACR_PGACTL (0x0FU) +#define ADC_PGACR_PGAGAIN_POS (4U) +#define ADC_PGACR_PGAGAIN (0xF0U) + +/* Bit definition for ADC_PGAVSSENR register */ +#define ADC_PGAVSSENR_PGAVSSEN (0x07U) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) +#define AES_CR_KEYSIZE_POS (3U) +#define AES_CR_KEYSIZE (0x00000018UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR4 register */ +#define AES_KR4 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR5 register */ +#define AES_KR5 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR6 register */ +#define AES_KR6 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR7 register */ +#define AES_KR7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INTSFTTRG register */ +#define AOS_INTSFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_TRGSEL register */ +#define AOS_DCU_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DCU_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DCU_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DCU_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA1_TRGSEL register */ +#define AOS_DMA1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA1_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DMA1_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DMA1_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA1_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA2_TRGSEL register */ +#define AOS_DMA2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA2_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DMA2_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DMA2_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA2_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_TRGSELRC register */ +#define AOS_DMA_TRGSELRC_TRGSEL_POS (0U) +#define AOS_DMA_TRGSELRC_TRGSEL (0x000001FFUL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_POS (30U) +#define AOS_DMA_TRGSELRC_COMTRG_EN (0xC0000000UL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_HTSSR register */ +#define AOS_TMR6_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR6_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR6_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR6_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR6_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR6_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNTTRGSR register */ +#define AOS_PEVNTTRGSR_TRGSEL_POS (0U) +#define AOS_PEVNTTRGSR_TRGSEL (0x000001FFUL) +#define AOS_PEVNTTRGSR_COMTRG_EN_POS (30U) +#define AOS_PEVNTTRGSR_COMTRG_EN (0xC0000000UL) +#define AOS_PEVNTTRGSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_PEVNTTRGSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_HTSSR register */ +#define AOS_TMR0_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR0_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR0_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR0_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR0_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR0_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR2_HTSSR register */ +#define AOS_TMR2_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR2_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR2_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR2_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR2_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR2_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_HASH_ITRGSELA register */ +#define AOS_HASH_ITRGSELA_TRGSEL_POS (0U) +#define AOS_HASH_ITRGSELA_TRGSEL (0x000001FFUL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_POS (30U) +#define AOS_HASH_ITRGSELA_COMTRG_EN (0xC0000000UL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_0 (0x40000000UL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_HASH_ITRGSELB register */ +#define AOS_HASH_ITRGSELB_TRGSEL_POS (0U) +#define AOS_HASH_ITRGSELB_TRGSEL (0x000001FFUL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_POS (30U) +#define AOS_HASH_ITRGSELB_COMTRG_EN (0xC0000000UL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_0 (0x40000000UL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_HTSSR register */ +#define AOS_TMRA_HTSSR_TRGSEL_POS (0U) +#define AOS_TMRA_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMRA_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMRA_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMRA_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMRA_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_OTS_TRG register */ +#define AOS_OTS_TRG_TRGSEL_POS (0U) +#define AOS_OTS_TRG_TRGSEL (0x000001FFUL) +#define AOS_OTS_TRG_COMTRG_EN_POS (30U) +#define AOS_OTS_TRG_COMTRG_EN (0xC0000000UL) +#define AOS_OTS_TRG_COMTRG_EN_0 (0x40000000UL) +#define AOS_OTS_TRG_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC1_ITRGSELR register */ +#define AOS_ADC1_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC1_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC1_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC1_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC1_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC1_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC2_ITRGSELR register */ +#define AOS_ADC2_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC2_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC2_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC2_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC2_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC2_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC3_ITRGSELR register */ +#define AOS_ADC3_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC3_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC3_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC3_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC3_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC3_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRG1 register */ +#define AOS_COMTRG1_TRGSEL (0x000001FFUL) + +/* Bit definition for AOS_COMTRG2 register */ +#define AOS_COMTRG2_TRGSEL (0x000001FFUL) + +/* Bit definition for AOS_PEVNTDIRR register */ +#define AOS_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTIDR register */ +#define AOS_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTODR register */ +#define AOS_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTORR register */ +#define AOS_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTOSR register */ +#define AOS_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTRISR register */ +#define AOS_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTFAL register */ +#define AOS_PEVNTFAL_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTNFCR register */ +#define AOS_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_PEVNTNFCR_DIVS4 (0x06000000UL) + +/******************************************************************************* + Bit definition for Peripheral CAN +*******************************************************************************/ +/* Bit definition for CAN_RBUF register */ +#define CAN_RBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_TBUF register */ +#define CAN_TBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_CFG_STAT register */ +#define CAN_CFG_STAT_BUSOFF_POS (0U) +#define CAN_CFG_STAT_BUSOFF (0x01U) +#define CAN_CFG_STAT_TACTIVE_POS (1U) +#define CAN_CFG_STAT_TACTIVE (0x02U) +#define CAN_CFG_STAT_RACTIVE_POS (2U) +#define CAN_CFG_STAT_RACTIVE (0x04U) +#define CAN_CFG_STAT_TSSS_POS (3U) +#define CAN_CFG_STAT_TSSS (0x08U) +#define CAN_CFG_STAT_TPSS_POS (4U) +#define CAN_CFG_STAT_TPSS (0x10U) +#define CAN_CFG_STAT_LBMI_POS (5U) +#define CAN_CFG_STAT_LBMI (0x20U) +#define CAN_CFG_STAT_LBME_POS (6U) +#define CAN_CFG_STAT_LBME (0x40U) +#define CAN_CFG_STAT_RESET_POS (7U) +#define CAN_CFG_STAT_RESET (0x80U) + +/* Bit definition for CAN_TCMD register */ +#define CAN_TCMD_TSA_POS (0U) +#define CAN_TCMD_TSA (0x01U) +#define CAN_TCMD_TSALL_POS (1U) +#define CAN_TCMD_TSALL (0x02U) +#define CAN_TCMD_TSONE_POS (2U) +#define CAN_TCMD_TSONE (0x04U) +#define CAN_TCMD_TPA_POS (3U) +#define CAN_TCMD_TPA (0x08U) +#define CAN_TCMD_TPE_POS (4U) +#define CAN_TCMD_TPE (0x10U) +#define CAN_TCMD_LOM_POS (6U) +#define CAN_TCMD_LOM (0x40U) +#define CAN_TCMD_TBSEL_POS (7U) +#define CAN_TCMD_TBSEL (0x80U) + +/* Bit definition for CAN_TCTRL register */ +#define CAN_TCTRL_TSSTAT_POS (0U) +#define CAN_TCTRL_TSSTAT (0x03U) +#define CAN_TCTRL_TSSTAT_0 (0x01U) +#define CAN_TCTRL_TSSTAT_1 (0x02U) +#define CAN_TCTRL_TTTBM_POS (4U) +#define CAN_TCTRL_TTTBM (0x10U) +#define CAN_TCTRL_TSMODE_POS (5U) +#define CAN_TCTRL_TSMODE (0x20U) +#define CAN_TCTRL_TSNEXT_POS (6U) +#define CAN_TCTRL_TSNEXT (0x40U) +#define CAN_TCTRL_FD_ISO_POS (7U) +#define CAN_TCTRL_FD_ISO (0x80U) + +/* Bit definition for CAN_RCTRL register */ +#define CAN_RCTRL_RSTAT_POS (0U) +#define CAN_RCTRL_RSTAT (0x03U) +#define CAN_RCTRL_RSTAT_0 (0x01U) +#define CAN_RCTRL_RSTAT_1 (0x02U) +#define CAN_RCTRL_RBALL_POS (3U) +#define CAN_RCTRL_RBALL (0x08U) +#define CAN_RCTRL_RREL_POS (4U) +#define CAN_RCTRL_RREL (0x10U) +#define CAN_RCTRL_ROV_POS (5U) +#define CAN_RCTRL_ROV (0x20U) +#define CAN_RCTRL_ROM_POS (6U) +#define CAN_RCTRL_ROM (0x40U) +#define CAN_RCTRL_SACK_POS (7U) +#define CAN_RCTRL_SACK (0x80U) + +/* Bit definition for CAN_RTIE register */ +#define CAN_RTIE_TSFF_POS (0U) +#define CAN_RTIE_TSFF (0x01U) +#define CAN_RTIE_EIE_POS (1U) +#define CAN_RTIE_EIE (0x02U) +#define CAN_RTIE_TSIE_POS (2U) +#define CAN_RTIE_TSIE (0x04U) +#define CAN_RTIE_TPIE_POS (3U) +#define CAN_RTIE_TPIE (0x08U) +#define CAN_RTIE_RAFIE_POS (4U) +#define CAN_RTIE_RAFIE (0x10U) +#define CAN_RTIE_RFIE_POS (5U) +#define CAN_RTIE_RFIE (0x20U) +#define CAN_RTIE_ROIE_POS (6U) +#define CAN_RTIE_ROIE (0x40U) +#define CAN_RTIE_RIE_POS (7U) +#define CAN_RTIE_RIE (0x80U) + +/* Bit definition for CAN_RTIF register */ +#define CAN_RTIF_AIF_POS (0U) +#define CAN_RTIF_AIF (0x01U) +#define CAN_RTIF_EIF_POS (1U) +#define CAN_RTIF_EIF (0x02U) +#define CAN_RTIF_TSIF_POS (2U) +#define CAN_RTIF_TSIF (0x04U) +#define CAN_RTIF_TPIF_POS (3U) +#define CAN_RTIF_TPIF (0x08U) +#define CAN_RTIF_RAFIF_POS (4U) +#define CAN_RTIF_RAFIF (0x10U) +#define CAN_RTIF_RFIF_POS (5U) +#define CAN_RTIF_RFIF (0x20U) +#define CAN_RTIF_ROIF_POS (6U) +#define CAN_RTIF_ROIF (0x40U) +#define CAN_RTIF_RIF_POS (7U) +#define CAN_RTIF_RIF (0x80U) + +/* Bit definition for CAN_ERRINT register */ +#define CAN_ERRINT_BEIF_POS (0U) +#define CAN_ERRINT_BEIF (0x01U) +#define CAN_ERRINT_BEIE_POS (1U) +#define CAN_ERRINT_BEIE (0x02U) +#define CAN_ERRINT_ALIF_POS (2U) +#define CAN_ERRINT_ALIF (0x04U) +#define CAN_ERRINT_ALIE_POS (3U) +#define CAN_ERRINT_ALIE (0x08U) +#define CAN_ERRINT_EPIF_POS (4U) +#define CAN_ERRINT_EPIF (0x10U) +#define CAN_ERRINT_EPIE_POS (5U) +#define CAN_ERRINT_EPIE (0x20U) +#define CAN_ERRINT_EPASS_POS (6U) +#define CAN_ERRINT_EPASS (0x40U) +#define CAN_ERRINT_EWARN_POS (7U) +#define CAN_ERRINT_EWARN (0x80U) + +/* Bit definition for CAN_LIMIT register */ +#define CAN_LIMIT_EWL_POS (0U) +#define CAN_LIMIT_EWL (0x0FU) +#define CAN_LIMIT_AFWL_POS (4U) +#define CAN_LIMIT_AFWL (0xF0U) + +/* Bit definition for CAN_SBT register */ +#define CAN_SBT_S_SEG_1_POS (0U) +#define CAN_SBT_S_SEG_1 (0x000000FFUL) +#define CAN_SBT_S_SEG_2_POS (8U) +#define CAN_SBT_S_SEG_2 (0x00007F00UL) +#define CAN_SBT_S_SJW_POS (16U) +#define CAN_SBT_S_SJW (0x007F0000UL) +#define CAN_SBT_S_PRESC_POS (24U) +#define CAN_SBT_S_PRESC (0xFF000000UL) + +/* Bit definition for CAN_FBT register */ +#define CAN_FBT_F_SEG_1_POS (0U) +#define CAN_FBT_F_SEG_1 (0x0000001FUL) +#define CAN_FBT_F_SEG_2_POS (8U) +#define CAN_FBT_F_SEG_2 (0x00000F00UL) +#define CAN_FBT_F_SJW_POS (16U) +#define CAN_FBT_F_SJW (0x000F0000UL) +#define CAN_FBT_F_PRESC_POS (24U) +#define CAN_FBT_F_PRESC (0xFF000000UL) + +/* Bit definition for CAN_EALCAP register */ +#define CAN_EALCAP_ALC_POS (0U) +#define CAN_EALCAP_ALC (0x1FU) +#define CAN_EALCAP_KOER_POS (5U) +#define CAN_EALCAP_KOER (0xE0U) + +/* Bit definition for CAN_TDC register */ +#define CAN_TDC_SSPOFF_POS (0U) +#define CAN_TDC_SSPOFF (0x7FU) +#define CAN_TDC_TDCEN_POS (7U) +#define CAN_TDC_TDCEN (0x80U) + +/* Bit definition for CAN_RECNT register */ +#define CAN_RECNT (0xFFU) + +/* Bit definition for CAN_TECNT register */ +#define CAN_TECNT (0xFFU) + +/* Bit definition for CAN_ACFCTRL register */ +#define CAN_ACFCTRL_ACFADR_POS (0U) +#define CAN_ACFCTRL_ACFADR (0x0FU) +#define CAN_ACFCTRL_SELMASK_POS (5U) +#define CAN_ACFCTRL_SELMASK (0x20U) + +/* Bit definition for CAN_ACFEN register */ +#define CAN_ACFEN_AE_1_POS (0U) +#define CAN_ACFEN_AE_1 (0x0001U) +#define CAN_ACFEN_AE_2_POS (1U) +#define CAN_ACFEN_AE_2 (0x0002U) +#define CAN_ACFEN_AE_3_POS (2U) +#define CAN_ACFEN_AE_3 (0x0004U) +#define CAN_ACFEN_AE_4_POS (3U) +#define CAN_ACFEN_AE_4 (0x0008U) +#define CAN_ACFEN_AE_5_POS (4U) +#define CAN_ACFEN_AE_5 (0x0010U) +#define CAN_ACFEN_AE_6_POS (5U) +#define CAN_ACFEN_AE_6 (0x0020U) +#define CAN_ACFEN_AE_7_POS (6U) +#define CAN_ACFEN_AE_7 (0x0040U) +#define CAN_ACFEN_AE_8_POS (7U) +#define CAN_ACFEN_AE_8 (0x0080U) +#define CAN_ACFEN_AE_9_POS (8U) +#define CAN_ACFEN_AE_9 (0x0100U) +#define CAN_ACFEN_AE_10_POS (9U) +#define CAN_ACFEN_AE_10 (0x0200U) +#define CAN_ACFEN_AE_11_POS (10U) +#define CAN_ACFEN_AE_11 (0x0400U) +#define CAN_ACFEN_AE_12_POS (11U) +#define CAN_ACFEN_AE_12 (0x0800U) +#define CAN_ACFEN_AE_13_POS (12U) +#define CAN_ACFEN_AE_13 (0x1000U) +#define CAN_ACFEN_AE_14_POS (13U) +#define CAN_ACFEN_AE_14 (0x2000U) +#define CAN_ACFEN_AE_15_POS (14U) +#define CAN_ACFEN_AE_15 (0x4000U) +#define CAN_ACFEN_AE_16_POS (15U) +#define CAN_ACFEN_AE_16 (0x8000U) + +/* Bit definition for CAN_ACF register */ +#define CAN_ACF_ACODEORAMASK_POS (0U) +#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL) +#define CAN_ACF_AIDE_POS (29U) +#define CAN_ACF_AIDE (0x20000000UL) +#define CAN_ACF_AIDEE_POS (30U) +#define CAN_ACF_AIDEE (0x40000000UL) + +/* Bit definition for CAN_TBSLOT register */ +#define CAN_TBSLOT_TBPTR_POS (0U) +#define CAN_TBSLOT_TBPTR (0x3FU) +#define CAN_TBSLOT_TBF_POS (6U) +#define CAN_TBSLOT_TBF (0x40U) +#define CAN_TBSLOT_TBE_POS (7U) +#define CAN_TBSLOT_TBE (0x80U) + +/* Bit definition for CAN_TTCFG register */ +#define CAN_TTCFG_TTEN_POS (0U) +#define CAN_TTCFG_TTEN (0x01U) +#define CAN_TTCFG_T_PRESC_POS (1U) +#define CAN_TTCFG_T_PRESC (0x06U) +#define CAN_TTCFG_T_PRESC_0 (0x02U) +#define CAN_TTCFG_T_PRESC_1 (0x04U) +#define CAN_TTCFG_TTIF_POS (3U) +#define CAN_TTCFG_TTIF (0x08U) +#define CAN_TTCFG_TTIE_POS (4U) +#define CAN_TTCFG_TTIE (0x10U) +#define CAN_TTCFG_TEIF_POS (5U) +#define CAN_TTCFG_TEIF (0x20U) +#define CAN_TTCFG_WTIF_POS (6U) +#define CAN_TTCFG_WTIF (0x40U) +#define CAN_TTCFG_WTIE_POS (7U) +#define CAN_TTCFG_WTIE (0x80U) + +/* Bit definition for CAN_REF_MSG register */ +#define CAN_REF_MSG_REF_ID_POS (0U) +#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_IDE_POS (31U) +#define CAN_REF_MSG_REF_IDE (0x80000000UL) + +/* Bit definition for CAN_TRG_CFG register */ +#define CAN_TRG_CFG_TTPTR_POS (0U) +#define CAN_TRG_CFG_TTPTR (0x003FU) +#define CAN_TRG_CFG_TTYPE_POS (8U) +#define CAN_TRG_CFG_TTYPE (0x0700U) +#define CAN_TRG_CFG_TTYPE_0 (0x0100U) +#define CAN_TRG_CFG_TTYPE_1 (0x0200U) +#define CAN_TRG_CFG_TTYPE_2 (0x0400U) +#define CAN_TRG_CFG_TEW_POS (12U) +#define CAN_TRG_CFG_TEW (0xF000U) + +/* Bit definition for CAN_TT_TRIG register */ +#define CAN_TT_TRIG (0xFFFFU) + +/* Bit definition for CAN_TT_WTRIG register */ +#define CAN_TT_WTRIG (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_MDR register */ +#define CMP_MDR_CENB_POS (0U) +#define CMP_MDR_CENB (0x01U) +#define CMP_MDR_CWDE_POS (1U) +#define CMP_MDR_CWDE (0x02U) +#define CMP_MDR_CMON_POS (7U) +#define CMP_MDR_CMON (0x80U) + +/* Bit definition for CMP_FIR register */ +#define CMP_FIR_FCKS_POS (0U) +#define CMP_FIR_FCKS (0x03U) +#define CMP_FIR_FCKS_0 (0x01U) +#define CMP_FIR_FCKS_1 (0x02U) +#define CMP_FIR_EDGS_POS (4U) +#define CMP_FIR_EDGS (0x30U) +#define CMP_FIR_EDGS_0 (0x10U) +#define CMP_FIR_EDGS_1 (0x20U) +#define CMP_FIR_CIEN_POS (6U) +#define CMP_FIR_CIEN (0x40U) + +/* Bit definition for CMP_OCR register */ +#define CMP_OCR_COEN_POS (0U) +#define CMP_OCR_COEN (0x01U) +#define CMP_OCR_COPS_POS (1U) +#define CMP_OCR_COPS (0x02U) +#define CMP_OCR_CPOE_POS (2U) +#define CMP_OCR_CPOE (0x04U) +#define CMP_OCR_TWOE_POS (3U) +#define CMP_OCR_TWOE (0x08U) +#define CMP_OCR_TWOL_POS (4U) +#define CMP_OCR_TWOL (0x10U) + +/* Bit definition for CMP_PMSR register */ +#define CMP_PMSR_RVSL_POS (0U) +#define CMP_PMSR_RVSL (0x0FU) +#define CMP_PMSR_RVSL_0 (0x01U) +#define CMP_PMSR_RVSL_1 (0x02U) +#define CMP_PMSR_RVSL_2 (0x04U) +#define CMP_PMSR_RVSL_3 (0x08U) +#define CMP_PMSR_CVSL_POS (4U) +#define CMP_PMSR_CVSL (0xF0U) +#define CMP_PMSR_CVSL_0 (0x10U) +#define CMP_PMSR_CVSL_1 (0x20U) +#define CMP_PMSR_CVSL_2 (0x40U) +#define CMP_PMSR_CVSL_3 (0x80U) + +/* Bit definition for CMP_TWSR register */ +#define CMP_TWSR_CTWS0_POS (0U) +#define CMP_TWSR_CTWS0 (0x0001U) +#define CMP_TWSR_CTWS1_POS (1U) +#define CMP_TWSR_CTWS1 (0x0002U) +#define CMP_TWSR_CTWS2_POS (2U) +#define CMP_TWSR_CTWS2 (0x0004U) +#define CMP_TWSR_CTWS3_POS (3U) +#define CMP_TWSR_CTWS3 (0x0008U) +#define CMP_TWSR_CTWS4_POS (4U) +#define CMP_TWSR_CTWS4 (0x0010U) +#define CMP_TWSR_CTWS5_POS (5U) +#define CMP_TWSR_CTWS5 (0x0020U) +#define CMP_TWSR_CTWS6_POS (6U) +#define CMP_TWSR_CTWS6 (0x0040U) +#define CMP_TWSR_CTWS7_POS (7U) +#define CMP_TWSR_CTWS7 (0x0080U) +#define CMP_TWSR_CTWS8_POS (8U) +#define CMP_TWSR_CTWS8 (0x0100U) +#define CMP_TWSR_CTWS9_POS (9U) +#define CMP_TWSR_CTWS9 (0x0200U) +#define CMP_TWSR_CTWS10_POS (10U) +#define CMP_TWSR_CTWS10 (0x0400U) +#define CMP_TWSR_CTWS11_POS (11U) +#define CMP_TWSR_CTWS11 (0x0800U) +#define CMP_TWSR_CTWS12_POS (12U) +#define CMP_TWSR_CTWS12 (0x1000U) +#define CMP_TWSR_CTWS13_POS (13U) +#define CMP_TWSR_CTWS13 (0x2000U) +#define CMP_TWSR_CTWS14_POS (14U) +#define CMP_TWSR_CTWS14 (0x4000U) +#define CMP_TWSR_CTWS15_POS (15U) +#define CMP_TWSR_CTWS15 (0x8000U) + +/* Bit definition for CMP_TWPR register */ +#define CMP_TWPR_CTWP0_POS (0U) +#define CMP_TWPR_CTWP0 (0x0001U) +#define CMP_TWPR_CTWP1_POS (1U) +#define CMP_TWPR_CTWP1 (0x0002U) +#define CMP_TWPR_CTWP2_POS (2U) +#define CMP_TWPR_CTWP2 (0x0004U) +#define CMP_TWPR_CTWP3_POS (3U) +#define CMP_TWPR_CTWP3 (0x0008U) +#define CMP_TWPR_CTWP4_POS (4U) +#define CMP_TWPR_CTWP4 (0x0010U) +#define CMP_TWPR_CTWP5_POS (5U) +#define CMP_TWPR_CTWP5 (0x0020U) +#define CMP_TWPR_CTWP6_POS (6U) +#define CMP_TWPR_CTWP6 (0x0040U) +#define CMP_TWPR_CTWP7_POS (7U) +#define CMP_TWPR_CTWP7 (0x0080U) +#define CMP_TWPR_CTWP8_POS (8U) +#define CMP_TWPR_CTWP8 (0x0100U) +#define CMP_TWPR_CTWP9_POS (9U) +#define CMP_TWPR_CTWP9 (0x0200U) +#define CMP_TWPR_CTWP10_POS (10U) +#define CMP_TWPR_CTWP10 (0x0400U) +#define CMP_TWPR_CTWP11_POS (11U) +#define CMP_TWPR_CTWP11 (0x0800U) +#define CMP_TWPR_CTWP12_POS (12U) +#define CMP_TWPR_CTWP12 (0x1000U) +#define CMP_TWPR_CTWP13_POS (13U) +#define CMP_TWPR_CTWP13 (0x2000U) +#define CMP_TWPR_CTWP14_POS (14U) +#define CMP_TWPR_CTWP14 (0x4000U) +#define CMP_TWPR_CTWP15_POS (15U) +#define CMP_TWPR_CTWP15 (0x8000U) + +/* Bit definition for CMP_VISR register */ +#define CMP_VISR_P2SL_POS (0U) +#define CMP_VISR_P2SL (0x0007U) +#define CMP_VISR_P2SL_0 (0x0001U) +#define CMP_VISR_P2SL_1 (0x0002U) +#define CMP_VISR_P2SL_2 (0x0004U) +#define CMP_VISR_P3SL_POS (4U) +#define CMP_VISR_P3SL (0x0030U) +#define CMP_VISR_P3SL_0 (0x0010U) +#define CMP_VISR_P3SL_1 (0x0020U) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV_POS (0U) +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) +#define CMU_XTAL32CFGR_XTAL32IE_POS (3U) +#define CMU_XTAL32CFGR_XTAL32IE (0x08U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_RTCLRCCR register */ +#define CMU_RTCLRCCR_RTCLRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/* Bit definition for CMU_RTCLRCTRM register */ +#define CMU_RTCLRCTRM (0xFFU) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) + +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_I2SCKSEL register */ +#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U) +#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU) +#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U) +#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U) +#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U) +#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U) +#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U) +#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U) + +/* Bit definition for CMU_CANCKCFGR register */ +#define CMU_CANCKCFGR_CAN1CKS_POS (0U) +#define CMU_CANCKCFGR_CAN1CKS (0x0FU) +#define CMU_CANCKCFGR_CAN2CKS_POS (4U) +#define CMU_CANCKCFGR_CAN2CKS (0xF0U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_USBCKCFGR register */ +#define CMU_USBCKCFGR_USBCKS_POS (4U) +#define CMU_USBCKCFGR_USBCKS (0xF0U) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLHCR register */ +#define CMU_PLLHCR_PLLHOFF (0x01U) + +/* Bit definition for CMU_PLLACR register */ +#define CMU_PLLACR_PLLAOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_PLLHSTBF_POS (5U) +#define CMU_OSCSTBSR_PLLHSTBF (0x20U) +#define CMU_OSCSTBSR_PLLASTBF_POS (6U) +#define CMU_OSCSTBSR_PLLASTBF (0x40U) + +/* Bit definition for CMU_MCOCFGR register */ +#define CMU_MCOCFGR_MCOSEL_POS (0U) +#define CMU_MCOCFGR_MCOSEL (0x0FU) +#define CMU_MCOCFGR_MCODIV_POS (4U) +#define CMU_MCOCFGR_MCODIV (0x70U) +#define CMU_MCOCFGR_MCOEN_POS (7U) +#define CMU_MCOCFGR_MCOEN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) + +/* Bit definition for CMU_PLLHCFGR register */ +#define CMU_PLLHCFGR_PLLHM_POS (0U) +#define CMU_PLLHCFGR_PLLHM (0x00000003UL) +#define CMU_PLLHCFGR_PLLSRC_POS (7U) +#define CMU_PLLHCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLHCFGR_PLLHN_POS (8U) +#define CMU_PLLHCFGR_PLLHN (0x0000FF00UL) +#define CMU_PLLHCFGR_PLLHR_POS (20U) +#define CMU_PLLHCFGR_PLLHR (0x00F00000UL) +#define CMU_PLLHCFGR_PLLHQ_POS (24U) +#define CMU_PLLHCFGR_PLLHQ (0x0F000000UL) +#define CMU_PLLHCFGR_PLLHP_POS (28U) +#define CMU_PLLHCFGR_PLLHP (0xF0000000UL) + +/* Bit definition for CMU_PLLACFGR register */ +#define CMU_PLLACFGR_PLLAM_POS (0U) +#define CMU_PLLACFGR_PLLAM (0x0000001FUL) +#define CMU_PLLACFGR_PLLAN_POS (8U) +#define CMU_PLLACFGR_PLLAN (0x0001FF00UL) +#define CMU_PLLACFGR_PLLAR_POS (20U) +#define CMU_PLLACFGR_PLLAR (0x00F00000UL) +#define CMU_PLLACFGR_PLLAQ_POS (24U) +#define CMU_PLLACFGR_PLLAQ (0x0F000000UL) +#define CMU_PLLACFGR_PLLAP_POS (28U) +#define CMU_PLLACFGR_PLLAP (0xF0000000UL) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (0U) +#define CRC_CR_CR (0x00000001UL) +#define CRC_CR_FLAG_POS (1U) +#define CRC_CR_FLAG (0x00000002UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral CTC +*******************************************************************************/ +/* Bit definition for CTC_CR1 register */ +#define CTC_CR1_REFPSC_POS (0U) +#define CTC_CR1_REFPSC (0x00000007UL) +#define CTC_CR1_REFPSC_0 (0x00000001UL) +#define CTC_CR1_REFPSC_1 (0x00000002UL) +#define CTC_CR1_REFPSC_2 (0x00000004UL) +#define CTC_CR1_REFCKS_POS (4U) +#define CTC_CR1_REFCKS (0x00000030UL) +#define CTC_CR1_REFCKS_0 (0x00000010UL) +#define CTC_CR1_REFCKS_1 (0x00000020UL) +#define CTC_CR1_ERRIE_POS (6U) +#define CTC_CR1_ERRIE (0x00000040UL) +#define CTC_CR1_CTCEN_POS (7U) +#define CTC_CR1_CTCEN (0x00000080UL) +#define CTC_CR1_TRMVAL_POS (16U) +#define CTC_CR1_TRMVAL (0x003F0000UL) + +/* Bit definition for CTC_CR2 register */ +#define CTC_CR2_OFSVAL_POS (0U) +#define CTC_CR2_OFSVAL (0x000000FFUL) +#define CTC_CR2_RLDVAL_POS (16U) +#define CTC_CR2_RLDVAL (0xFFFF0000UL) + +/* Bit definition for CTC_STR register */ +#define CTC_STR_TRIMOK_POS (0U) +#define CTC_STR_TRIMOK (0x00000001UL) +#define CTC_STR_TRMOVF_POS (1U) +#define CTC_STR_TRMOVF (0x00000002UL) +#define CTC_STR_TRMUDF_POS (2U) +#define CTC_STR_TRMUDF (0x00000004UL) +#define CTC_STR_CTCBSY_POS (3U) +#define CTC_STR_CTCBSY (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral DAC +*******************************************************************************/ +/* Bit definition for DAC_DADR1 register */ +#define DAC_DADR1 (0xFFFFU) + +/* Bit definition for DAC_DADR2 register */ +#define DAC_DADR2 (0xFFFFU) + +/* Bit definition for DAC_DACR register */ +#define DAC_DACR_DAEN_POS (0U) +#define DAC_DACR_DAEN (0x0001U) +#define DAC_DACR_DA1EN_POS (1U) +#define DAC_DACR_DA1EN (0x0002U) +#define DAC_DACR_DA2EN_POS (2U) +#define DAC_DACR_DA2EN (0x0004U) +#define DAC_DACR_ALIGN_POS (8U) +#define DAC_DACR_ALIGN (0x0100U) +#define DAC_DACR_DAAMP1_POS (9U) +#define DAC_DACR_DAAMP1 (0x0200U) +#define DAC_DACR_DAAMP2_POS (10U) +#define DAC_DACR_DAAMP2 (0x0400U) +#define DAC_DACR_EXTDSL1_POS (11U) +#define DAC_DACR_EXTDSL1 (0x0800U) +#define DAC_DACR_EXTDSL2_POS (12U) +#define DAC_DACR_EXTDSL2 (0x1000U) + +/* Bit definition for DAC_DAADPCR register */ +#define DAC_DAADPCR_ADPSL1_POS (0U) +#define DAC_DAADPCR_ADPSL1 (0x0001U) +#define DAC_DAADPCR_ADPSL2_POS (1U) +#define DAC_DAADPCR_ADPSL2 (0x0002U) +#define DAC_DAADPCR_ADPSL3_POS (2U) +#define DAC_DAADPCR_ADPSL3 (0x0004U) +#define DAC_DAADPCR_DA1SF_POS (8U) +#define DAC_DAADPCR_DA1SF (0x0100U) +#define DAC_DAADPCR_DA2SF_POS (9U) +#define DAC_DAADPCR_DA2SF (0x0200U) +#define DAC_DAADPCR_ADPEN_POS (15U) +#define DAC_DAADPCR_ADPEN (0x8000U) + +/* Bit definition for DAC_DAOCR register */ +#define DAC_DAOCR_DAODIS1_POS (14U) +#define DAC_DAOCR_DAODIS1 (0x4000U) +#define DAC_DAOCR_DAODIS2_POS (15U) +#define DAC_DAOCR_DAODIS2 (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_AUTHID0 register */ +#define DBGC_AUTHID0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID1 register */ +#define DBGC_AUTHID1 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID2 register */ +#define DBGC_AUTHID2 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_RESV0 register */ +#define DBGC_RESV0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_MCUSTAT register */ +#define DBGC_MCUSTAT_AUTH_POS (0U) +#define DBGC_MCUSTAT_AUTH (0x00000001UL) +#define DBGC_MCUSTAT_REMVLOCK_POS (1U) +#define DBGC_MCUSTAT_REMVLOCK (0x00000002UL) +#define DBGC_MCUSTAT_SAFTYLOCK1_POS (2U) +#define DBGC_MCUSTAT_SAFTYLOCK1 (0x00000004UL) +#define DBGC_MCUSTAT_SAFTYLOCK2_POS (3U) +#define DBGC_MCUSTAT_SAFTYLOCK2 (0x00000008UL) +#define DBGC_MCUSTAT_CPUSTOP_POS (8U) +#define DBGC_MCUSTAT_CPUSTOP (0x00000100UL) +#define DBGC_MCUSTAT_CPUSLEEP_POS (9U) +#define DBGC_MCUSTAT_CPUSLEEP (0x00000200UL) + +/* Bit definition for DBGC_MCUCTL register */ +#define DBGC_MCUCTL_EDBGRQ_POS (0U) +#define DBGC_MCUCTL_EDBGRQ (0x00000001UL) +#define DBGC_MCUCTL_RESTART_POS (1U) +#define DBGC_MCUCTL_RESTART (0x00000002UL) +#define DBGC_MCUCTL_DIRQ_POS (8U) +#define DBGC_MCUCTL_DIRQ (0x00000100UL) + +/* Bit definition for DBGC_FMCCTL register */ +#define DBGC_FMCCTL_ERASEREQ_POS (0U) +#define DBGC_FMCCTL_ERASEREQ (0x00000001UL) +#define DBGC_FMCCTL_ERASEACK_POS (1U) +#define DBGC_FMCCTL_ERASEACK (0x00000002UL) +#define DBGC_FMCCTL_ERASEERR_POS (2U) +#define DBGC_FMCCTL_ERASEERR (0x00000004UL) + +/* Bit definition for DBGC_MCUDBGCSTAT register */ +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_PVD0STP_POS (3U) +#define DBGC_MCUSTPCTL_PVD0STP (0x00000008UL) +#define DBGC_MCUSTPCTL_PVD1STP_POS (4U) +#define DBGC_MCUSTPCTL_PVD1STP (0x00000010UL) +#define DBGC_MCUSTPCTL_PVD2STP_POS (5U) +#define DBGC_MCUSTPCTL_PVD2STP (0x00000020UL) +#define DBGC_MCUSTPCTL_M06STP_POS (6U) +#define DBGC_MCUSTPCTL_M06STP (0x00000040UL) +#define DBGC_MCUSTPCTL_M07STP_POS (7U) +#define DBGC_MCUSTPCTL_M07STP (0x00000080UL) +#define DBGC_MCUSTPCTL_M08STP_POS (8U) +#define DBGC_MCUSTPCTL_M08STP (0x00000100UL) +#define DBGC_MCUSTPCTL_M09STP_POS (9U) +#define DBGC_MCUSTPCTL_M09STP (0x00000200UL) +#define DBGC_MCUSTPCTL_M10STP_POS (10U) +#define DBGC_MCUSTPCTL_M10STP (0x00000400UL) +#define DBGC_MCUSTPCTL_M11STP_POS (11U) +#define DBGC_MCUSTPCTL_M11STP (0x00000800UL) +#define DBGC_MCUSTPCTL_M12STP_POS (12U) +#define DBGC_MCUSTPCTL_M12STP (0x00001000UL) +#define DBGC_MCUSTPCTL_M13STP_POS (13U) +#define DBGC_MCUSTPCTL_M13STP (0x00002000UL) +#define DBGC_MCUSTPCTL_M14STP_POS (14U) +#define DBGC_MCUSTPCTL_M14STP (0x00004000UL) +#define DBGC_MCUSTPCTL_M15STP_POS (15U) +#define DBGC_MCUSTPCTL_M15STP (0x00008000UL) +#define DBGC_MCUSTPCTL_M16STP_POS (16U) +#define DBGC_MCUSTPCTL_M16STP (0x00010000UL) +#define DBGC_MCUSTPCTL_M17STP_POS (17U) +#define DBGC_MCUSTPCTL_M17STP (0x00020000UL) +#define DBGC_MCUSTPCTL_M18STP_POS (18U) +#define DBGC_MCUSTPCTL_M18STP (0x00040000UL) +#define DBGC_MCUSTPCTL_M19STP_POS (19U) +#define DBGC_MCUSTPCTL_M19STP (0x00080000UL) +#define DBGC_MCUSTPCTL_M20STP_POS (20U) +#define DBGC_MCUSTPCTL_M20STP (0x00100000UL) +#define DBGC_MCUSTPCTL_M21STP_POS (21U) +#define DBGC_MCUSTPCTL_M21STP (0x00200000UL) +#define DBGC_MCUSTPCTL_M22STP_POS (22U) +#define DBGC_MCUSTPCTL_M22STP (0x00400000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/* Bit definition for DBGC_MCUSTPCTL2 register */ +#define DBGC_MCUSTPCTL2_M32STP_POS (0U) +#define DBGC_MCUSTPCTL2_M32STP (0x00000001UL) +#define DBGC_MCUSTPCTL2_M33STP_POS (1U) +#define DBGC_MCUSTPCTL2_M33STP (0x00000002UL) +#define DBGC_MCUSTPCTL2_M34STP_POS (2U) +#define DBGC_MCUSTPCTL2_M34STP (0x00000004UL) +#define DBGC_MCUSTPCTL2_M35STP_POS (3U) +#define DBGC_MCUSTPCTL2_M35STP (0x00000008UL) +#define DBGC_MCUSTPCTL2_M36STP_POS (4U) +#define DBGC_MCUSTPCTL2_M36STP (0x00000010UL) +#define DBGC_MCUSTPCTL2_M37STP_POS (5U) +#define DBGC_MCUSTPCTL2_M37STP (0x00000020UL) +#define DBGC_MCUSTPCTL2_M38STP_POS (6U) +#define DBGC_MCUSTPCTL2_M38STP (0x00000040UL) +#define DBGC_MCUSTPCTL2_M39STP_POS (7U) +#define DBGC_MCUSTPCTL2_M39STP (0x00000080UL) +#define DBGC_MCUSTPCTL2_M40STP_POS (8U) +#define DBGC_MCUSTPCTL2_M40STP (0x00000100UL) +#define DBGC_MCUSTPCTL2_M41STP_POS (9U) +#define DBGC_MCUSTPCTL2_M41STP (0x00000200UL) +#define DBGC_MCUSTPCTL2_M42STP_POS (10U) +#define DBGC_MCUSTPCTL2_M42STP (0x00000400UL) +#define DBGC_MCUSTPCTL2_M43STP_POS (11U) +#define DBGC_MCUSTPCTL2_M43STP (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x0000000FUL) +#define DCU_CTL_MODE_0 (0x00000001UL) +#define DCU_CTL_MODE_1 (0x00000002UL) +#define DCU_CTL_MODE_2 (0x00000004UL) +#define DCU_CTL_MODE_3 (0x00000008UL) +#define DCU_CTL_DATASIZE_POS (4U) +#define DCU_CTL_DATASIZE (0x00000030UL) +#define DCU_CTL_DATASIZE_0 (0x00000010UL) +#define DCU_CTL_DATASIZE_1 (0x00000020UL) +#define DCU_CTL_COMP_TRG_POS (8U) +#define DCU_CTL_COMP_TRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) +#define DCU_FLAG_FLAG_RLD_POS (9U) +#define DCU_FLAG_FLAG_RLD (0x00000200UL) +#define DCU_FLAG_FLAG_BTM_POS (10U) +#define DCU_FLAG_FLAG_BTM (0x00000400UL) +#define DCU_FLAG_FLAG_TOP_POS (11U) +#define DCU_FLAG_FLAG_TOP (0x00000800UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) +#define DCU_FLAGCLR_CLR_RLD_POS (9U) +#define DCU_FLAGCLR_CLR_RLD (0x00000200UL) +#define DCU_FLAGCLR_CLR_BTM_POS (10U) +#define DCU_FLAGCLR_CLR_BTM (0x00000400UL) +#define DCU_FLAGCLR_CLR_TOP_POS (11U) +#define DCU_FLAGCLR_CLR_TOP (0x00000800UL) + +/* Bit definition for DCU_INTSEL register */ +#define DCU_INTSEL_INT_OP_POS (0U) +#define DCU_INTSEL_INT_OP (0x00000001UL) +#define DCU_INTSEL_INT_LS2_POS (1U) +#define DCU_INTSEL_INT_LS2 (0x00000002UL) +#define DCU_INTSEL_INT_EQ2_POS (2U) +#define DCU_INTSEL_INT_EQ2 (0x00000004UL) +#define DCU_INTSEL_INT_GT2_POS (3U) +#define DCU_INTSEL_INT_GT2 (0x00000008UL) +#define DCU_INTSEL_INT_LS1_POS (4U) +#define DCU_INTSEL_INT_LS1 (0x00000010UL) +#define DCU_INTSEL_INT_EQ1_POS (5U) +#define DCU_INTSEL_INT_EQ1 (0x00000020UL) +#define DCU_INTSEL_INT_GT1_POS (6U) +#define DCU_INTSEL_INT_GT1 (0x00000040UL) +#define DCU_INTSEL_INT_WIN_POS (7U) +#define DCU_INTSEL_INT_WIN (0x00000180UL) +#define DCU_INTSEL_INT_WIN_0 (0x00000080UL) +#define DCU_INTSEL_INT_WIN_1 (0x00000100UL) +#define DCU_INTSEL_INT_RLD_POS (9U) +#define DCU_INTSEL_INT_RLD (0x00000200UL) +#define DCU_INTSEL_INT_BTM_POS (10U) +#define DCU_INTSEL_INT_BTM (0x00000400UL) +#define DCU_INTSEL_INT_TOP_POS (11U) +#define DCU_INTSEL_INT_TOP (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x000000FFUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_TRNERR_4 (0x00000010UL) +#define DMA_INTSTAT0_TRNERR_5 (0x00000020UL) +#define DMA_INTSTAT0_TRNERR_6 (0x00000040UL) +#define DMA_INTSTAT0_TRNERR_7 (0x00000080UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x00FF0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) +#define DMA_INTSTAT0_REQERR_4 (0x00100000UL) +#define DMA_INTSTAT0_REQERR_5 (0x00200000UL) +#define DMA_INTSTAT0_REQERR_6 (0x00400000UL) +#define DMA_INTSTAT0_REQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x000000FFUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_TC_4 (0x00000010UL) +#define DMA_INTSTAT1_TC_5 (0x00000020UL) +#define DMA_INTSTAT1_TC_6 (0x00000040UL) +#define DMA_INTSTAT1_TC_7 (0x00000080UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x00FF0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) +#define DMA_INTSTAT1_BTC_4 (0x00100000UL) +#define DMA_INTSTAT1_BTC_5 (0x00200000UL) +#define DMA_INTSTAT1_BTC_6 (0x00400000UL) +#define DMA_INTSTAT1_BTC_7 (0x00800000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x000000FFUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKTRNERR_4 (0x00000010UL) +#define DMA_INTMASK0_MSKTRNERR_5 (0x00000020UL) +#define DMA_INTMASK0_MSKTRNERR_6 (0x00000040UL) +#define DMA_INTMASK0_MSKTRNERR_7 (0x00000080UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x00FF0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) +#define DMA_INTMASK0_MSKREQERR_4 (0x00100000UL) +#define DMA_INTMASK0_MSKREQERR_5 (0x00200000UL) +#define DMA_INTMASK0_MSKREQERR_6 (0x00400000UL) +#define DMA_INTMASK0_MSKREQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x000000FFUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKTC_4 (0x00000010UL) +#define DMA_INTMASK1_MSKTC_5 (0x00000020UL) +#define DMA_INTMASK1_MSKTC_6 (0x00000040UL) +#define DMA_INTMASK1_MSKTC_7 (0x00000080UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x00FF0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) +#define DMA_INTMASK1_MSKBTC_4 (0x00100000UL) +#define DMA_INTMASK1_MSKBTC_5 (0x00200000UL) +#define DMA_INTMASK1_MSKBTC_6 (0x00400000UL) +#define DMA_INTMASK1_MSKBTC_7 (0x00800000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x000000FFUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRTRNERR_4 (0x00000010UL) +#define DMA_INTCLR0_CLRTRNERR_5 (0x00000020UL) +#define DMA_INTCLR0_CLRTRNERR_6 (0x00000040UL) +#define DMA_INTCLR0_CLRTRNERR_7 (0x00000080UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x00FF0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) +#define DMA_INTCLR0_CLRREQERR_4 (0x00100000UL) +#define DMA_INTCLR0_CLRREQERR_5 (0x00200000UL) +#define DMA_INTCLR0_CLRREQERR_6 (0x00400000UL) +#define DMA_INTCLR0_CLRREQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x000000FFUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRTC_4 (0x00000010UL) +#define DMA_INTCLR1_CLRTC_5 (0x00000020UL) +#define DMA_INTCLR1_CLRTC_6 (0x00000040UL) +#define DMA_INTCLR1_CLRTC_7 (0x00000080UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x00FF0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) +#define DMA_INTCLR1_CLRBTC_4 (0x00100000UL) +#define DMA_INTCLR1_CLRBTC_5 (0x00200000UL) +#define DMA_INTCLR1_CLRBTC_6 (0x00400000UL) +#define DMA_INTCLR1_CLRBTC_7 (0x00800000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x000000FFUL) +#define DMA_CHEN_CHEN_0 (0x00000001UL) +#define DMA_CHEN_CHEN_1 (0x00000002UL) +#define DMA_CHEN_CHEN_2 (0x00000004UL) +#define DMA_CHEN_CHEN_3 (0x00000008UL) +#define DMA_CHEN_CHEN_4 (0x00000010UL) +#define DMA_CHEN_CHEN_5 (0x00000020UL) +#define DMA_CHEN_CHEN_6 (0x00000040UL) +#define DMA_CHEN_CHEN_7 (0x00000080UL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x000000FFUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_CHREQ_4 (0x00000010UL) +#define DMA_REQSTAT_CHREQ_5 (0x00000020UL) +#define DMA_REQSTAT_CHREQ_6 (0x00000040UL) +#define DMA_REQSTAT_CHREQ_7 (0x00000080UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x00FF0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) +#define DMA_CHSTAT_CHACT_4 (0x00100000UL) +#define DMA_CHSTAT_CHACT_5 (0x00200000UL) +#define DMA_CHSTAT_CHACT_6 (0x00400000UL) +#define DMA_CHSTAT_CHACT_7 (0x00800000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_CHENCLR register */ +#define DMA_CHENCLR_CHENCLR (0x000000FFUL) +#define DMA_CHENCLR_CHENCLR_0 (0x00000001UL) +#define DMA_CHENCLR_CHENCLR_1 (0x00000002UL) +#define DMA_CHENCLR_CHENCLR_2 (0x00000004UL) +#define DMA_CHENCLR_CHENCLR_3 (0x00000008UL) +#define DMA_CHENCLR_CHENCLR_4 (0x00000010UL) +#define DMA_CHENCLR_CHENCLR_5 (0x00000020UL) +#define DMA_CHENCLR_CHENCLR_6 (0x00000040UL) +#define DMA_CHENCLR_CHENCLR_7 (0x00000080UL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRPTEN_POS (4U) +#define DMA_CHCTL_SRPTEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral DMC +*******************************************************************************/ +/* Bit definition for DMC_STSR register */ +#define DMC_STSR_STATUS_POS (0U) +#define DMC_STSR_STATUS (0x00000003UL) +#define DMC_STSR_STATUS_0 (0x00000001UL) +#define DMC_STSR_STATUS_1 (0x00000002UL) +#define DMC_STSR_MEMW_POS (2U) +#define DMC_STSR_MEMW (0x0000000CUL) +#define DMC_STSR_MEMW_0 (0x00000004UL) +#define DMC_STSR_MEMW_1 (0x00000008UL) + +/* Bit definition for DMC_STCR register */ +#define DMC_STCR_STCTL (0x00000007UL) +#define DMC_STCR_STCTL_0 (0x00000001UL) +#define DMC_STCR_STCTL_1 (0x00000002UL) +#define DMC_STCR_STCTL_2 (0x00000004UL) + +/* Bit definition for DMC_CMDR register */ +#define DMC_CMDR_CMDADD_POS (0U) +#define DMC_CMDR_CMDADD (0x00003FFFUL) +#define DMC_CMDR_CMDBA_POS (16U) +#define DMC_CMDR_CMDBA (0x00030000UL) +#define DMC_CMDR_CMDBA_0 (0x00010000UL) +#define DMC_CMDR_CMDBA_1 (0x00020000UL) +#define DMC_CMDR_CMD_POS (18U) +#define DMC_CMDR_CMD (0x000C0000UL) +#define DMC_CMDR_CMD_0 (0x00040000UL) +#define DMC_CMDR_CMD_1 (0x00080000UL) +#define DMC_CMDR_CMDCHIP_POS (20U) +#define DMC_CMDR_CMDCHIP (0x00300000UL) +#define DMC_CMDR_CMDCHIP_0 (0x00100000UL) +#define DMC_CMDR_CMDCHIP_1 (0x00200000UL) + +/* Bit definition for DMC_CPCR register */ +#define DMC_CPCR_COLBS_POS (0U) +#define DMC_CPCR_COLBS (0x00000007UL) +#define DMC_CPCR_ROWBS_POS (4U) +#define DMC_CPCR_ROWBS (0x00000070UL) +#define DMC_CPCR_APBS_POS (7U) +#define DMC_CPCR_APBS (0x00000080UL) +#define DMC_CPCR_CKEDIS_POS (8U) +#define DMC_CPCR_CKEDIS (0x00000100UL) +#define DMC_CPCR_CKSTOP_POS (9U) +#define DMC_CPCR_CKSTOP (0x00000200UL) +#define DMC_CPCR_CKEDISPRD_POS (10U) +#define DMC_CPCR_CKEDISPRD (0x0000FC00UL) +#define DMC_CPCR_BURST_POS (16U) +#define DMC_CPCR_BURST (0x00070000UL) +#define DMC_CPCR_ACTCP_POS (24U) +#define DMC_CPCR_ACTCP (0x03000000UL) +#define DMC_CPCR_ACTCP_0 (0x01000000UL) +#define DMC_CPCR_ACTCP_1 (0x02000000UL) + +/* Bit definition for DMC_RFTR register */ +#define DMC_RFTR_REFPRD (0x00007FFFUL) + +/* Bit definition for DMC_TMCR_T_CASL register */ +#define DMC_TMCR_T_CASL_T_CASL (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_DQSS register */ +#define DMC_TMCR_T_DQSS_T_DQSS (0x00000003UL) + +/* Bit definition for DMC_TMCR_T_MRD register */ +#define DMC_TMCR_T_MRD_T_MRD (0x0000007FUL) + +/* Bit definition for DMC_TMCR_T_RAS register */ +#define DMC_TMCR_T_RAS_T_RAS (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_RC register */ +#define DMC_TMCR_T_RC_T_RC (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_RCD register */ +#define DMC_TMCR_T_RCD_T_RCD_B_POS (0U) +#define DMC_TMCR_T_RCD_T_RCD_B (0x00000007UL) +#define DMC_TMCR_T_RCD_T_RCD_P_POS (4U) +#define DMC_TMCR_T_RCD_T_RCD_P (0x00000070UL) + +/* Bit definition for DMC_TMCR_T_RFC register */ +#define DMC_TMCR_T_RFC_T_RFC_B_POS (0U) +#define DMC_TMCR_T_RFC_T_RFC_B (0x0000001FUL) +#define DMC_TMCR_T_RFC_T_RFC_P_POS (8U) +#define DMC_TMCR_T_RFC_T_RFC_P (0x00001F00UL) + +/* Bit definition for DMC_TMCR_T_RP register */ +#define DMC_TMCR_T_RP_T_RP_B_POS (0U) +#define DMC_TMCR_T_RP_T_RP_B (0x00000007UL) +#define DMC_TMCR_T_RP_T_RP_P_POS (4U) +#define DMC_TMCR_T_RP_T_RP_P (0x00000070UL) + +/* Bit definition for DMC_TMCR_T_RRD register */ +#define DMC_TMCR_T_RRD_T_RRD (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_WR register */ +#define DMC_TMCR_T_WR_T_WR (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_WTR register */ +#define DMC_TMCR_T_WTR_T_WTR (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_XP register */ +#define DMC_TMCR_T_XP_T_XP (0x000000FFUL) + +/* Bit definition for DMC_TMCR_T_XSR register */ +#define DMC_TMCR_T_XSR_T_XSR (0x000000FFUL) + +/* Bit definition for DMC_TMCR_T_ESR register */ +#define DMC_TMCR_T_ESR_T_ESR (0x000000FFUL) + +/* Bit definition for DMC_CSCR register */ +#define DMC_CSCR_ADDMSK_POS (0U) +#define DMC_CSCR_ADDMSK (0x000000FFUL) +#define DMC_CSCR_ADDMAT_POS (8U) +#define DMC_CSCR_ADDMAT (0x0000FF00UL) +#define DMC_CSCR_BRC_POS (16U) +#define DMC_CSCR_BRC (0x00010000UL) + +/* Bit definition for DMC_BACR register */ +#define DMC_BACR_DMCMW_POS (0U) +#define DMC_BACR_DMCMW (0x00000003UL) +#define DMC_BACR_DMCMW_0 (0x00000001UL) +#define DMC_BACR_DMCMW_1 (0x00000002UL) +#define DMC_BACR_CKSEL_POS (14U) +#define DMC_BACR_CKSEL (0x0000C000UL) +#define DMC_BACR_CKSEL_0 (0x00004000UL) +#define DMC_BACR_CKSEL_1 (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral DVP +*******************************************************************************/ +/* Bit definition for DVP_CTR register */ +#define DVP_CTR_CAPEN_POS (0U) +#define DVP_CTR_CAPEN (0x00000001UL) +#define DVP_CTR_CAPMD_POS (1U) +#define DVP_CTR_CAPMD (0x00000002UL) +#define DVP_CTR_CROPEN_POS (2U) +#define DVP_CTR_CROPEN (0x00000004UL) +#define DVP_CTR_JPEGEN_POS (3U) +#define DVP_CTR_JPEGEN (0x00000008UL) +#define DVP_CTR_SWSYNC_POS (4U) +#define DVP_CTR_SWSYNC (0x00000010UL) +#define DVP_CTR_PIXCKSEL_POS (5U) +#define DVP_CTR_PIXCKSEL (0x00000020UL) +#define DVP_CTR_HSYNCSEL_POS (6U) +#define DVP_CTR_HSYNCSEL (0x00000040UL) +#define DVP_CTR_VSYNCSEL_POS (7U) +#define DVP_CTR_VSYNCSEL (0x00000080UL) +#define DVP_CTR_CAPFRC_POS (8U) +#define DVP_CTR_CAPFRC (0x00000300UL) +#define DVP_CTR_CAPFRC_0 (0x00000100UL) +#define DVP_CTR_CAPFRC_1 (0x00000200UL) +#define DVP_CTR_BITSEL_POS (10U) +#define DVP_CTR_BITSEL (0x00000C00UL) +#define DVP_CTR_BITSEL_0 (0x00000400UL) +#define DVP_CTR_BITSEL_1 (0x00000800UL) +#define DVP_CTR_DVPEN_POS (14U) +#define DVP_CTR_DVPEN (0x00004000UL) + +/* Bit definition for DVP_DTR register */ +#define DVP_DTR (0xFFFFFFFFUL) + +/* Bit definition for DVP_STR register */ +#define DVP_STR_FSF_POS (0U) +#define DVP_STR_FSF (0x00000001UL) +#define DVP_STR_LSF_POS (1U) +#define DVP_STR_LSF (0x00000002UL) +#define DVP_STR_LEF_POS (2U) +#define DVP_STR_LEF (0x00000004UL) +#define DVP_STR_FEF_POS (3U) +#define DVP_STR_FEF (0x00000008UL) +#define DVP_STR_SQUERF_POS (4U) +#define DVP_STR_SQUERF (0x00000010UL) +#define DVP_STR_FIFOERF_POS (5U) +#define DVP_STR_FIFOERF (0x00000020UL) + +/* Bit definition for DVP_IER register */ +#define DVP_IER_FSIEN_POS (0U) +#define DVP_IER_FSIEN (0x00000001UL) +#define DVP_IER_LSIEN_POS (1U) +#define DVP_IER_LSIEN (0x00000002UL) +#define DVP_IER_LEIEN_POS (2U) +#define DVP_IER_LEIEN (0x00000004UL) +#define DVP_IER_FEIEN_POS (3U) +#define DVP_IER_FEIEN (0x00000008UL) +#define DVP_IER_SQUERIEN_POS (4U) +#define DVP_IER_SQUERIEN (0x00000010UL) +#define DVP_IER_FIFOERIEN_POS (5U) +#define DVP_IER_FIFOERIEN (0x00000020UL) + +/* Bit definition for DVP_DMR register */ +#define DVP_DMR (0xFFFFFFFFUL) + +/* Bit definition for DVP_SSYNDR register */ +#define DVP_SSYNDR_FSDAT_POS (0U) +#define DVP_SSYNDR_FSDAT (0x000000FFUL) +#define DVP_SSYNDR_LSDAT_POS (8U) +#define DVP_SSYNDR_LSDAT (0x0000FF00UL) +#define DVP_SSYNDR_LEDAT_POS (16U) +#define DVP_SSYNDR_LEDAT (0x00FF0000UL) +#define DVP_SSYNDR_FEDAT_POS (24U) +#define DVP_SSYNDR_FEDAT (0xFF000000UL) + +/* Bit definition for DVP_SSYNMR register */ +#define DVP_SSYNMR_FSMSK_POS (0U) +#define DVP_SSYNMR_FSMSK (0x000000FFUL) +#define DVP_SSYNMR_LSMSK_POS (8U) +#define DVP_SSYNMR_LSMSK (0x0000FF00UL) +#define DVP_SSYNMR_LEMSK_POS (16U) +#define DVP_SSYNMR_LEMSK (0x00FF0000UL) +#define DVP_SSYNMR_FEMSK_POS (24U) +#define DVP_SSYNMR_FEMSK (0xFF000000UL) + +/* Bit definition for DVP_CPSFTR register */ +#define DVP_CPSFTR_RSHIFT_POS (0U) +#define DVP_CPSFTR_RSHIFT (0x00003FFFUL) +#define DVP_CPSFTR_CSHIFT_POS (16U) +#define DVP_CPSFTR_CSHIFT (0x3FFF0000UL) + +/* Bit definition for DVP_CPSZER register */ +#define DVP_CPSZER_RSIZE_POS (0U) +#define DVP_CPSZER_RSIZE (0x00003FFFUL) +#define DVP_CPSZER_CSIZE_POS (16U) +#define DVP_CPSZER_CSIZE (0x3FFF0000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_KEY1 register */ +#define EFM_KEY1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_KEY2 register */ +#define EFM_KEY2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_F0STP_POS (0U) +#define EFM_FSTP_F0STP (0x00000001UL) +#define EFM_FSTP_F1STP_POS (1U) +#define EFM_FSTP_F1STP (0x00000002UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_FLWT_POS (0U) +#define EFM_FRMC_FLWT (0x0000000FUL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_ICACHE_POS (16U) +#define EFM_FRMC_ICACHE (0x00010000UL) +#define EFM_FRMC_DCACHE_POS (17U) +#define EFM_FRMC_DCACHE (0x00020000UL) +#define EFM_FRMC_PREFETE_POS (18U) +#define EFM_FRMC_PREFETE (0x00040000UL) +#define EFM_FRMC_CRST_POS (19U) +#define EFM_FRMC_CRST (0x00080000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMOD_POS (0U) +#define EFM_FWMC_PEMOD (0x00000007UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) +#define EFM_FWMC_KEY1LOCK_POS (16U) +#define EFM_FWMC_KEY1LOCK (0x00010000UL) +#define EFM_FWMC_KEY2LOCK_POS (17U) +#define EFM_FWMC_KEY2LOCK (0x00020000UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_OTPWERR0_POS (0U) +#define EFM_FSR_OTPWERR0 (0x00000001UL) +#define EFM_FSR_PRTWERR0_POS (1U) +#define EFM_FSR_PRTWERR0 (0x00000002UL) +#define EFM_FSR_PGSZERR0_POS (2U) +#define EFM_FSR_PGSZERR0 (0x00000004UL) +#define EFM_FSR_MISMTCH0_POS (3U) +#define EFM_FSR_MISMTCH0 (0x00000008UL) +#define EFM_FSR_OPTEND0_POS (4U) +#define EFM_FSR_OPTEND0 (0x00000010UL) +#define EFM_FSR_COLERR0_POS (5U) +#define EFM_FSR_COLERR0 (0x00000020UL) +#define EFM_FSR_RDY0_POS (8U) +#define EFM_FSR_RDY0 (0x00000100UL) +#define EFM_FSR_PRTWERR1_POS (17U) +#define EFM_FSR_PRTWERR1 (0x00020000UL) +#define EFM_FSR_PGSZERR1_POS (18U) +#define EFM_FSR_PGSZERR1 (0x00040000UL) +#define EFM_FSR_MISMTCH1_POS (19U) +#define EFM_FSR_MISMTCH1 (0x00080000UL) +#define EFM_FSR_OPTEND1_POS (20U) +#define EFM_FSR_OPTEND1 (0x00100000UL) +#define EFM_FSR_COLERR1_POS (21U) +#define EFM_FSR_COLERR1 (0x00200000UL) +#define EFM_FSR_RDY1_POS (24U) +#define EFM_FSR_RDY1 (0x01000000UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_OTPWERRCLR0_POS (0U) +#define EFM_FSCLR_OTPWERRCLR0 (0x00000001UL) +#define EFM_FSCLR_PRTWERRCLR0_POS (1U) +#define EFM_FSCLR_PRTWERRCLR0 (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR0_POS (2U) +#define EFM_FSCLR_PGSZERRCLR0 (0x00000004UL) +#define EFM_FSCLR_MISMTCHCLR0_POS (3U) +#define EFM_FSCLR_MISMTCHCLR0 (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR0_POS (4U) +#define EFM_FSCLR_OPTENDCLR0 (0x00000010UL) +#define EFM_FSCLR_COLERRCLR0_POS (5U) +#define EFM_FSCLR_COLERRCLR0 (0x00000020UL) +#define EFM_FSCLR_PRTWERRCLR1_POS (17U) +#define EFM_FSCLR_PRTWERRCLR1 (0x00020000UL) +#define EFM_FSCLR_PGSZERRCLR1_POS (18U) +#define EFM_FSCLR_PGSZERRCLR1 (0x00040000UL) +#define EFM_FSCLR_MISMTCHCLR1_POS (19U) +#define EFM_FSCLR_MISMTCHCLR1 (0x00080000UL) +#define EFM_FSCLR_OPTENDCLR1_POS (20U) +#define EFM_FSCLR_OPTENDCLR1 (0x00100000UL) +#define EFM_FSCLR_COLERRCLR1_POS (21U) +#define EFM_FSCLR_COLERRCLR1 (0x00200000UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_CHIPID register */ +#define EFM_CHIPID (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_MMF_REMPRT register */ +#define EFM_MMF_REMPRT_MMF_REMPRT (0x0000FFFFUL) + +/* Bit definition for EFM_MMF_REMCR register */ +#define EFM_MMF_REMCR_RMSIZE_POS (0U) +#define EFM_MMF_REMCR_RMSIZE (0x0000001FUL) +#define EFM_MMF_REMCR_RMTADDR_POS (12U) +#define EFM_MMF_REMCR_RMTADDR (0x1FFFF000UL) +#define EFM_MMF_REMCR_EN_POS (31U) +#define EFM_MMF_REMCR_EN (0x80000000UL) + +/* Bit definition for EFM_WLOCK register */ +#define EFM_WLOCK_WLOCK (0x000000FFUL) +#define EFM_WLOCK_WLOCK_0 (0x00000001UL) +#define EFM_WLOCK_WLOCK_1 (0x00000002UL) +#define EFM_WLOCK_WLOCK_2 (0x00000004UL) +#define EFM_WLOCK_WLOCK_3 (0x00000008UL) +#define EFM_WLOCK_WLOCK_4 (0x00000010UL) +#define EFM_WLOCK_WLOCK_5 (0x00000020UL) +#define EFM_WLOCK_WLOCK_6 (0x00000040UL) +#define EFM_WLOCK_WLOCK_7 (0x00000080UL) + +/* Bit definition for EFM_F0NWPRT0 register */ +#define EFM_F0NWPRT0_F0NWPRT0_POS (0U) +#define EFM_F0NWPRT0_F0NWPRT0 (0x00000001UL) +#define EFM_F0NWPRT0_F0NWPRT1_POS (1U) +#define EFM_F0NWPRT0_F0NWPRT1 (0x00000002UL) +#define EFM_F0NWPRT0_F0NWPRT2_POS (2U) +#define EFM_F0NWPRT0_F0NWPRT2 (0x00000004UL) +#define EFM_F0NWPRT0_F0NWPRT3_POS (3U) +#define EFM_F0NWPRT0_F0NWPRT3 (0x00000008UL) +#define EFM_F0NWPRT0_F0NWPRT4_POS (4U) +#define EFM_F0NWPRT0_F0NWPRT4 (0x00000010UL) +#define EFM_F0NWPRT0_F0NWPRT5_POS (5U) +#define EFM_F0NWPRT0_F0NWPRT5 (0x00000020UL) +#define EFM_F0NWPRT0_F0NWPRT6_POS (6U) +#define EFM_F0NWPRT0_F0NWPRT6 (0x00000040UL) +#define EFM_F0NWPRT0_F0NWPRT7_POS (7U) +#define EFM_F0NWPRT0_F0NWPRT7 (0x00000080UL) +#define EFM_F0NWPRT0_F0NWPRT8_POS (8U) +#define EFM_F0NWPRT0_F0NWPRT8 (0x00000100UL) +#define EFM_F0NWPRT0_F0NWPRT9_POS (9U) +#define EFM_F0NWPRT0_F0NWPRT9 (0x00000200UL) +#define EFM_F0NWPRT0_F0NWPRT10_POS (10U) +#define EFM_F0NWPRT0_F0NWPRT10 (0x00000400UL) +#define EFM_F0NWPRT0_F0NWPRT11_POS (11U) +#define EFM_F0NWPRT0_F0NWPRT11 (0x00000800UL) +#define EFM_F0NWPRT0_F0NWPRT12_POS (12U) +#define EFM_F0NWPRT0_F0NWPRT12 (0x00001000UL) +#define EFM_F0NWPRT0_F0NWPRT13_POS (13U) +#define EFM_F0NWPRT0_F0NWPRT13 (0x00002000UL) +#define EFM_F0NWPRT0_F0NWPRT14_POS (14U) +#define EFM_F0NWPRT0_F0NWPRT14 (0x00004000UL) +#define EFM_F0NWPRT0_F0NWPRT15_POS (15U) +#define EFM_F0NWPRT0_F0NWPRT15 (0x00008000UL) +#define EFM_F0NWPRT0_F0NWPRT16_POS (16U) +#define EFM_F0NWPRT0_F0NWPRT16 (0x00010000UL) +#define EFM_F0NWPRT0_F0NWPRT17_POS (17U) +#define EFM_F0NWPRT0_F0NWPRT17 (0x00020000UL) +#define EFM_F0NWPRT0_F0NWPRT18_POS (18U) +#define EFM_F0NWPRT0_F0NWPRT18 (0x00040000UL) +#define EFM_F0NWPRT0_F0NWPRT19_POS (19U) +#define EFM_F0NWPRT0_F0NWPRT19 (0x00080000UL) +#define EFM_F0NWPRT0_F0NWPRT20_POS (20U) +#define EFM_F0NWPRT0_F0NWPRT20 (0x00100000UL) +#define EFM_F0NWPRT0_F0NWPRT21_POS (21U) +#define EFM_F0NWPRT0_F0NWPRT21 (0x00200000UL) +#define EFM_F0NWPRT0_F0NWPRT22_POS (22U) +#define EFM_F0NWPRT0_F0NWPRT22 (0x00400000UL) +#define EFM_F0NWPRT0_F0NWPRT23_POS (23U) +#define EFM_F0NWPRT0_F0NWPRT23 (0x00800000UL) +#define EFM_F0NWPRT0_F0NWPRT24_POS (24U) +#define EFM_F0NWPRT0_F0NWPRT24 (0x01000000UL) +#define EFM_F0NWPRT0_F0NWPRT25_POS (25U) +#define EFM_F0NWPRT0_F0NWPRT25 (0x02000000UL) +#define EFM_F0NWPRT0_F0NWPRT26_POS (26U) +#define EFM_F0NWPRT0_F0NWPRT26 (0x04000000UL) +#define EFM_F0NWPRT0_F0NWPRT27_POS (27U) +#define EFM_F0NWPRT0_F0NWPRT27 (0x08000000UL) +#define EFM_F0NWPRT0_F0NWPRT28_POS (28U) +#define EFM_F0NWPRT0_F0NWPRT28 (0x10000000UL) +#define EFM_F0NWPRT0_F0NWPRT29_POS (29U) +#define EFM_F0NWPRT0_F0NWPRT29 (0x20000000UL) +#define EFM_F0NWPRT0_F0NWPRT30_POS (30U) +#define EFM_F0NWPRT0_F0NWPRT30 (0x40000000UL) +#define EFM_F0NWPRT0_F0NWPRT31_POS (31U) +#define EFM_F0NWPRT0_F0NWPRT31 (0x80000000UL) + +/* Bit definition for EFM_F0NWPRT1 register */ +#define EFM_F0NWPRT1_F0NWPRT32_POS (0U) +#define EFM_F0NWPRT1_F0NWPRT32 (0x00000001UL) +#define EFM_F0NWPRT1_F0NWPRT33_POS (1U) +#define EFM_F0NWPRT1_F0NWPRT33 (0x00000002UL) +#define EFM_F0NWPRT1_F0NWPRT34_POS (2U) +#define EFM_F0NWPRT1_F0NWPRT34 (0x00000004UL) +#define EFM_F0NWPRT1_F0NWPRT35_POS (3U) +#define EFM_F0NWPRT1_F0NWPRT35 (0x00000008UL) +#define EFM_F0NWPRT1_F0NWPRT36_POS (4U) +#define EFM_F0NWPRT1_F0NWPRT36 (0x00000010UL) +#define EFM_F0NWPRT1_F0NWPRT37_POS (5U) +#define EFM_F0NWPRT1_F0NWPRT37 (0x00000020UL) +#define EFM_F0NWPRT1_F0NWPRT38_POS (6U) +#define EFM_F0NWPRT1_F0NWPRT38 (0x00000040UL) +#define EFM_F0NWPRT1_F0NWPRT39_POS (7U) +#define EFM_F0NWPRT1_F0NWPRT39 (0x00000080UL) +#define EFM_F0NWPRT1_F0NWPRT40_POS (8U) +#define EFM_F0NWPRT1_F0NWPRT40 (0x00000100UL) +#define EFM_F0NWPRT1_F0NWPRT41_POS (9U) +#define EFM_F0NWPRT1_F0NWPRT41 (0x00000200UL) +#define EFM_F0NWPRT1_F0NWPRT42_POS (10U) +#define EFM_F0NWPRT1_F0NWPRT42 (0x00000400UL) +#define EFM_F0NWPRT1_F0NWPRT43_POS (11U) +#define EFM_F0NWPRT1_F0NWPRT43 (0x00000800UL) +#define EFM_F0NWPRT1_F0NWPRT44_POS (12U) +#define EFM_F0NWPRT1_F0NWPRT44 (0x00001000UL) +#define EFM_F0NWPRT1_F0NWPRT45_POS (13U) +#define EFM_F0NWPRT1_F0NWPRT45 (0x00002000UL) +#define EFM_F0NWPRT1_F0NWPRT46_POS (14U) +#define EFM_F0NWPRT1_F0NWPRT46 (0x00004000UL) +#define EFM_F0NWPRT1_F0NWPRT47_POS (15U) +#define EFM_F0NWPRT1_F0NWPRT47 (0x00008000UL) +#define EFM_F0NWPRT1_F0NWPRT48_POS (16U) +#define EFM_F0NWPRT1_F0NWPRT48 (0x00010000UL) +#define EFM_F0NWPRT1_F0NWPRT49_POS (17U) +#define EFM_F0NWPRT1_F0NWPRT49 (0x00020000UL) +#define EFM_F0NWPRT1_F0NWPRT50_POS (18U) +#define EFM_F0NWPRT1_F0NWPRT50 (0x00040000UL) +#define EFM_F0NWPRT1_F0NWPRT51_POS (19U) +#define EFM_F0NWPRT1_F0NWPRT51 (0x00080000UL) +#define EFM_F0NWPRT1_F0NWPRT52_POS (20U) +#define EFM_F0NWPRT1_F0NWPRT52 (0x00100000UL) +#define EFM_F0NWPRT1_F0NWPRT53_POS (21U) +#define EFM_F0NWPRT1_F0NWPRT53 (0x00200000UL) +#define EFM_F0NWPRT1_F0NWPRT54_POS (22U) +#define EFM_F0NWPRT1_F0NWPRT54 (0x00400000UL) +#define EFM_F0NWPRT1_F0NWPRT55_POS (23U) +#define EFM_F0NWPRT1_F0NWPRT55 (0x00800000UL) +#define EFM_F0NWPRT1_F0NWPRT56_POS (24U) +#define EFM_F0NWPRT1_F0NWPRT56 (0x01000000UL) +#define EFM_F0NWPRT1_F0NWPRT57_POS (25U) +#define EFM_F0NWPRT1_F0NWPRT57 (0x02000000UL) +#define EFM_F0NWPRT1_F0NWPRT58_POS (26U) +#define EFM_F0NWPRT1_F0NWPRT58 (0x04000000UL) +#define EFM_F0NWPRT1_F0NWPRT59_POS (27U) +#define EFM_F0NWPRT1_F0NWPRT59 (0x08000000UL) +#define EFM_F0NWPRT1_F0NWPRT60_POS (28U) +#define EFM_F0NWPRT1_F0NWPRT60 (0x10000000UL) +#define EFM_F0NWPRT1_F0NWPRT61_POS (29U) +#define EFM_F0NWPRT1_F0NWPRT61 (0x20000000UL) +#define EFM_F0NWPRT1_F0NWPRT62_POS (30U) +#define EFM_F0NWPRT1_F0NWPRT62 (0x40000000UL) +#define EFM_F0NWPRT1_F0NWPRT63_POS (31U) +#define EFM_F0NWPRT1_F0NWPRT63 (0x80000000UL) + +/* Bit definition for EFM_F0NWPRT2 register */ +#define EFM_F0NWPRT2_F0NWPRT64_POS (0U) +#define EFM_F0NWPRT2_F0NWPRT64 (0x00000001UL) +#define EFM_F0NWPRT2_F0NWPRT65_POS (1U) +#define EFM_F0NWPRT2_F0NWPRT65 (0x00000002UL) +#define EFM_F0NWPRT2_F0NWPRT66_POS (2U) +#define EFM_F0NWPRT2_F0NWPRT66 (0x00000004UL) +#define EFM_F0NWPRT2_F0NWPRT67_POS (3U) +#define EFM_F0NWPRT2_F0NWPRT67 (0x00000008UL) +#define EFM_F0NWPRT2_F0NWPRT68_POS (4U) +#define EFM_F0NWPRT2_F0NWPRT68 (0x00000010UL) +#define EFM_F0NWPRT2_F0NWPRT69_POS (5U) +#define EFM_F0NWPRT2_F0NWPRT69 (0x00000020UL) +#define EFM_F0NWPRT2_F0NWPRT70_POS (6U) +#define EFM_F0NWPRT2_F0NWPRT70 (0x00000040UL) +#define EFM_F0NWPRT2_F0NWPRT71_POS (7U) +#define EFM_F0NWPRT2_F0NWPRT71 (0x00000080UL) +#define EFM_F0NWPRT2_F0NWPRT72_POS (8U) +#define EFM_F0NWPRT2_F0NWPRT72 (0x00000100UL) +#define EFM_F0NWPRT2_F0NWPRT73_POS (9U) +#define EFM_F0NWPRT2_F0NWPRT73 (0x00000200UL) +#define EFM_F0NWPRT2_F0NWPRT74_POS (10U) +#define EFM_F0NWPRT2_F0NWPRT74 (0x00000400UL) +#define EFM_F0NWPRT2_F0NWPRT75_POS (11U) +#define EFM_F0NWPRT2_F0NWPRT75 (0x00000800UL) +#define EFM_F0NWPRT2_F0NWPRT76_POS (12U) +#define EFM_F0NWPRT2_F0NWPRT76 (0x00001000UL) +#define EFM_F0NWPRT2_F0NWPRT77_POS (13U) +#define EFM_F0NWPRT2_F0NWPRT77 (0x00002000UL) +#define EFM_F0NWPRT2_F0NWPRT78_POS (14U) +#define EFM_F0NWPRT2_F0NWPRT78 (0x00004000UL) +#define EFM_F0NWPRT2_F0NWPRT79_POS (15U) +#define EFM_F0NWPRT2_F0NWPRT79 (0x00008000UL) +#define EFM_F0NWPRT2_F0NWPRT80_POS (16U) +#define EFM_F0NWPRT2_F0NWPRT80 (0x00010000UL) +#define EFM_F0NWPRT2_F0NWPRT81_POS (17U) +#define EFM_F0NWPRT2_F0NWPRT81 (0x00020000UL) +#define EFM_F0NWPRT2_F0NWPRT82_POS (18U) +#define EFM_F0NWPRT2_F0NWPRT82 (0x00040000UL) +#define EFM_F0NWPRT2_F0NWPRT83_POS (19U) +#define EFM_F0NWPRT2_F0NWPRT83 (0x00080000UL) +#define EFM_F0NWPRT2_F0NWPRT84_POS (20U) +#define EFM_F0NWPRT2_F0NWPRT84 (0x00100000UL) +#define EFM_F0NWPRT2_F0NWPRT85_POS (21U) +#define EFM_F0NWPRT2_F0NWPRT85 (0x00200000UL) +#define EFM_F0NWPRT2_F0NWPRT86_POS (22U) +#define EFM_F0NWPRT2_F0NWPRT86 (0x00400000UL) +#define EFM_F0NWPRT2_F0NWPRT87_POS (23U) +#define EFM_F0NWPRT2_F0NWPRT87 (0x00800000UL) +#define EFM_F0NWPRT2_F0NWPRT88_POS (24U) +#define EFM_F0NWPRT2_F0NWPRT88 (0x01000000UL) +#define EFM_F0NWPRT2_F0NWPRT89_POS (25U) +#define EFM_F0NWPRT2_F0NWPRT89 (0x02000000UL) +#define EFM_F0NWPRT2_F0NWPRT90_POS (26U) +#define EFM_F0NWPRT2_F0NWPRT90 (0x04000000UL) +#define EFM_F0NWPRT2_F0NWPRT91_POS (27U) +#define EFM_F0NWPRT2_F0NWPRT91 (0x08000000UL) +#define EFM_F0NWPRT2_F0NWPRT92_POS (28U) +#define EFM_F0NWPRT2_F0NWPRT92 (0x10000000UL) +#define EFM_F0NWPRT2_F0NWPRT93_POS (29U) +#define EFM_F0NWPRT2_F0NWPRT93 (0x20000000UL) +#define EFM_F0NWPRT2_F0NWPRT94_POS (30U) +#define EFM_F0NWPRT2_F0NWPRT94 (0x40000000UL) +#define EFM_F0NWPRT2_F0NWPRT95_POS (31U) +#define EFM_F0NWPRT2_F0NWPRT95 (0x80000000UL) + +/* Bit definition for EFM_F0NWPRT3 register */ +#define EFM_F0NWPRT3_F0NWPRT96_POS (0U) +#define EFM_F0NWPRT3_F0NWPRT96 (0x00000001UL) +#define EFM_F0NWPRT3_F0NWPRT97_POS (1U) +#define EFM_F0NWPRT3_F0NWPRT97 (0x00000002UL) +#define EFM_F0NWPRT3_F0NWPRT98_POS (2U) +#define EFM_F0NWPRT3_F0NWPRT98 (0x00000004UL) +#define EFM_F0NWPRT3_F0NWPRT99_POS (3U) +#define EFM_F0NWPRT3_F0NWPRT99 (0x00000008UL) +#define EFM_F0NWPRT3_F0NWPRT100_POS (4U) +#define EFM_F0NWPRT3_F0NWPRT100 (0x00000010UL) +#define EFM_F0NWPRT3_F0NWPRT101_POS (5U) +#define EFM_F0NWPRT3_F0NWPRT101 (0x00000020UL) +#define EFM_F0NWPRT3_F0NWPRT102_POS (6U) +#define EFM_F0NWPRT3_F0NWPRT102 (0x00000040UL) +#define EFM_F0NWPRT3_F0NWPRT103_POS (7U) +#define EFM_F0NWPRT3_F0NWPRT103 (0x00000080UL) +#define EFM_F0NWPRT3_F0NWPRT104_POS (8U) +#define EFM_F0NWPRT3_F0NWPRT104 (0x00000100UL) +#define EFM_F0NWPRT3_F0NWPRT105_POS (9U) +#define EFM_F0NWPRT3_F0NWPRT105 (0x00000200UL) +#define EFM_F0NWPRT3_F0NWPRT106_POS (10U) +#define EFM_F0NWPRT3_F0NWPRT106 (0x00000400UL) +#define EFM_F0NWPRT3_F0NWPRT107_POS (11U) +#define EFM_F0NWPRT3_F0NWPRT107 (0x00000800UL) +#define EFM_F0NWPRT3_F0NWPRT108_POS (12U) +#define EFM_F0NWPRT3_F0NWPRT108 (0x00001000UL) +#define EFM_F0NWPRT3_F0NWPRT109_POS (13U) +#define EFM_F0NWPRT3_F0NWPRT109 (0x00002000UL) +#define EFM_F0NWPRT3_F0NWPRT110_POS (14U) +#define EFM_F0NWPRT3_F0NWPRT110 (0x00004000UL) +#define EFM_F0NWPRT3_F0NWPRT111_POS (15U) +#define EFM_F0NWPRT3_F0NWPRT111 (0x00008000UL) +#define EFM_F0NWPRT3_F0NWPRT112_POS (16U) +#define EFM_F0NWPRT3_F0NWPRT112 (0x00010000UL) +#define EFM_F0NWPRT3_F0NWPRT113_POS (17U) +#define EFM_F0NWPRT3_F0NWPRT113 (0x00020000UL) +#define EFM_F0NWPRT3_F0NWPRT114_POS (18U) +#define EFM_F0NWPRT3_F0NWPRT114 (0x00040000UL) +#define EFM_F0NWPRT3_F0NWPRT115_POS (19U) +#define EFM_F0NWPRT3_F0NWPRT115 (0x00080000UL) +#define EFM_F0NWPRT3_F0NWPRT116_POS (20U) +#define EFM_F0NWPRT3_F0NWPRT116 (0x00100000UL) +#define EFM_F0NWPRT3_F0NWPRT117_POS (21U) +#define EFM_F0NWPRT3_F0NWPRT117 (0x00200000UL) +#define EFM_F0NWPRT3_F0NWPRT118_POS (22U) +#define EFM_F0NWPRT3_F0NWPRT118 (0x00400000UL) +#define EFM_F0NWPRT3_F0NWPRT119_POS (23U) +#define EFM_F0NWPRT3_F0NWPRT119 (0x00800000UL) +#define EFM_F0NWPRT3_F0NWPRT120_POS (24U) +#define EFM_F0NWPRT3_F0NWPRT120 (0x01000000UL) +#define EFM_F0NWPRT3_F0NWPRT121_POS (25U) +#define EFM_F0NWPRT3_F0NWPRT121 (0x02000000UL) +#define EFM_F0NWPRT3_F0NWPRT122_POS (26U) +#define EFM_F0NWPRT3_F0NWPRT122 (0x04000000UL) +#define EFM_F0NWPRT3_F0NWPRT123_POS (27U) +#define EFM_F0NWPRT3_F0NWPRT123 (0x08000000UL) +#define EFM_F0NWPRT3_F0NWPRT124_POS (28U) +#define EFM_F0NWPRT3_F0NWPRT124 (0x10000000UL) +#define EFM_F0NWPRT3_F0NWPRT125_POS (29U) +#define EFM_F0NWPRT3_F0NWPRT125 (0x20000000UL) +#define EFM_F0NWPRT3_F0NWPRT126_POS (30U) +#define EFM_F0NWPRT3_F0NWPRT126 (0x40000000UL) +#define EFM_F0NWPRT3_F0NWPRT127_POS (31U) +#define EFM_F0NWPRT3_F0NWPRT127 (0x80000000UL) + +/* Bit definition for EFM_F1NWPRT0 register */ +#define EFM_F1NWPRT0_F1NWPRT0_POS (0U) +#define EFM_F1NWPRT0_F1NWPRT0 (0x00000001UL) +#define EFM_F1NWPRT0_F1NWPRT1_POS (1U) +#define EFM_F1NWPRT0_F1NWPRT1 (0x00000002UL) +#define EFM_F1NWPRT0_F1NWPRT2_POS (2U) +#define EFM_F1NWPRT0_F1NWPRT2 (0x00000004UL) +#define EFM_F1NWPRT0_F1NWPRT3_POS (3U) +#define EFM_F1NWPRT0_F1NWPRT3 (0x00000008UL) +#define EFM_F1NWPRT0_F1NWPRT4_POS (4U) +#define EFM_F1NWPRT0_F1NWPRT4 (0x00000010UL) +#define EFM_F1NWPRT0_F1NWPRT5_POS (5U) +#define EFM_F1NWPRT0_F1NWPRT5 (0x00000020UL) +#define EFM_F1NWPRT0_F1NWPRT6_POS (6U) +#define EFM_F1NWPRT0_F1NWPRT6 (0x00000040UL) +#define EFM_F1NWPRT0_F1NWPRT7_POS (7U) +#define EFM_F1NWPRT0_F1NWPRT7 (0x00000080UL) +#define EFM_F1NWPRT0_F1NWPRT8_POS (8U) +#define EFM_F1NWPRT0_F1NWPRT8 (0x00000100UL) +#define EFM_F1NWPRT0_F1NWPRT9_POS (9U) +#define EFM_F1NWPRT0_F1NWPRT9 (0x00000200UL) +#define EFM_F1NWPRT0_F1NWPRT10_POS (10U) +#define EFM_F1NWPRT0_F1NWPRT10 (0x00000400UL) +#define EFM_F1NWPRT0_F1NWPRT11_POS (11U) +#define EFM_F1NWPRT0_F1NWPRT11 (0x00000800UL) +#define EFM_F1NWPRT0_F1NWPRT12_POS (12U) +#define EFM_F1NWPRT0_F1NWPRT12 (0x00001000UL) +#define EFM_F1NWPRT0_F1NWPRT13_POS (13U) +#define EFM_F1NWPRT0_F1NWPRT13 (0x00002000UL) +#define EFM_F1NWPRT0_F1NWPRT14_POS (14U) +#define EFM_F1NWPRT0_F1NWPRT14 (0x00004000UL) +#define EFM_F1NWPRT0_F1NWPRT15_POS (15U) +#define EFM_F1NWPRT0_F1NWPRT15 (0x00008000UL) +#define EFM_F1NWPRT0_F1NWPRT16_POS (16U) +#define EFM_F1NWPRT0_F1NWPRT16 (0x00010000UL) +#define EFM_F1NWPRT0_F1NWPRT17_POS (17U) +#define EFM_F1NWPRT0_F1NWPRT17 (0x00020000UL) +#define EFM_F1NWPRT0_F1NWPRT18_POS (18U) +#define EFM_F1NWPRT0_F1NWPRT18 (0x00040000UL) +#define EFM_F1NWPRT0_F1NWPRT19_POS (19U) +#define EFM_F1NWPRT0_F1NWPRT19 (0x00080000UL) +#define EFM_F1NWPRT0_F1NWPRT20_POS (20U) +#define EFM_F1NWPRT0_F1NWPRT20 (0x00100000UL) +#define EFM_F1NWPRT0_F1NWPRT21_POS (21U) +#define EFM_F1NWPRT0_F1NWPRT21 (0x00200000UL) +#define EFM_F1NWPRT0_F1NWPRT22_POS (22U) +#define EFM_F1NWPRT0_F1NWPRT22 (0x00400000UL) +#define EFM_F1NWPRT0_F1NWPRT23_POS (23U) +#define EFM_F1NWPRT0_F1NWPRT23 (0x00800000UL) +#define EFM_F1NWPRT0_F1NWPRT24_POS (24U) +#define EFM_F1NWPRT0_F1NWPRT24 (0x01000000UL) +#define EFM_F1NWPRT0_F1NWPRT25_POS (25U) +#define EFM_F1NWPRT0_F1NWPRT25 (0x02000000UL) +#define EFM_F1NWPRT0_F1NWPRT26_POS (26U) +#define EFM_F1NWPRT0_F1NWPRT26 (0x04000000UL) +#define EFM_F1NWPRT0_F1NWPRT27_POS (27U) +#define EFM_F1NWPRT0_F1NWPRT27 (0x08000000UL) +#define EFM_F1NWPRT0_F1NWPRT28_POS (28U) +#define EFM_F1NWPRT0_F1NWPRT28 (0x10000000UL) +#define EFM_F1NWPRT0_F1NWPRT29_POS (29U) +#define EFM_F1NWPRT0_F1NWPRT29 (0x20000000UL) +#define EFM_F1NWPRT0_F1NWPRT30_POS (30U) +#define EFM_F1NWPRT0_F1NWPRT30 (0x40000000UL) +#define EFM_F1NWPRT0_F1NWPRT31_POS (31U) +#define EFM_F1NWPRT0_F1NWPRT31 (0x80000000UL) + +/* Bit definition for EFM_F1NWPRT1 register */ +#define EFM_F1NWPRT1_F1NWPRT32_POS (0U) +#define EFM_F1NWPRT1_F1NWPRT32 (0x00000001UL) +#define EFM_F1NWPRT1_F1NWPRT33_POS (1U) +#define EFM_F1NWPRT1_F1NWPRT33 (0x00000002UL) +#define EFM_F1NWPRT1_F1NWPRT34_POS (2U) +#define EFM_F1NWPRT1_F1NWPRT34 (0x00000004UL) +#define EFM_F1NWPRT1_F1NWPRT35_POS (3U) +#define EFM_F1NWPRT1_F1NWPRT35 (0x00000008UL) +#define EFM_F1NWPRT1_F1NWPRT36_POS (4U) +#define EFM_F1NWPRT1_F1NWPRT36 (0x00000010UL) +#define EFM_F1NWPRT1_F1NWPRT37_POS (5U) +#define EFM_F1NWPRT1_F1NWPRT37 (0x00000020UL) +#define EFM_F1NWPRT1_F1NWPRT38_POS (6U) +#define EFM_F1NWPRT1_F1NWPRT38 (0x00000040UL) +#define EFM_F1NWPRT1_F1NWPRT39_POS (7U) +#define EFM_F1NWPRT1_F1NWPRT39 (0x00000080UL) +#define EFM_F1NWPRT1_F1NWPRT40_POS (8U) +#define EFM_F1NWPRT1_F1NWPRT40 (0x00000100UL) +#define EFM_F1NWPRT1_F1NWPRT41_POS (9U) +#define EFM_F1NWPRT1_F1NWPRT41 (0x00000200UL) +#define EFM_F1NWPRT1_F1NWPRT42_POS (10U) +#define EFM_F1NWPRT1_F1NWPRT42 (0x00000400UL) +#define EFM_F1NWPRT1_F1NWPRT43_POS (11U) +#define EFM_F1NWPRT1_F1NWPRT43 (0x00000800UL) +#define EFM_F1NWPRT1_F1NWPRT44_POS (12U) +#define EFM_F1NWPRT1_F1NWPRT44 (0x00001000UL) +#define EFM_F1NWPRT1_F1NWPRT45_POS (13U) +#define EFM_F1NWPRT1_F1NWPRT45 (0x00002000UL) +#define EFM_F1NWPRT1_F1NWPRT46_POS (14U) +#define EFM_F1NWPRT1_F1NWPRT46 (0x00004000UL) +#define EFM_F1NWPRT1_F1NWPRT47_POS (15U) +#define EFM_F1NWPRT1_F1NWPRT47 (0x00008000UL) +#define EFM_F1NWPRT1_F1NWPRT48_POS (16U) +#define EFM_F1NWPRT1_F1NWPRT48 (0x00010000UL) +#define EFM_F1NWPRT1_F1NWPRT49_POS (17U) +#define EFM_F1NWPRT1_F1NWPRT49 (0x00020000UL) +#define EFM_F1NWPRT1_F1NWPRT50_POS (18U) +#define EFM_F1NWPRT1_F1NWPRT50 (0x00040000UL) +#define EFM_F1NWPRT1_F1NWPRT51_POS (19U) +#define EFM_F1NWPRT1_F1NWPRT51 (0x00080000UL) +#define EFM_F1NWPRT1_F1NWPRT52_POS (20U) +#define EFM_F1NWPRT1_F1NWPRT52 (0x00100000UL) +#define EFM_F1NWPRT1_F1NWPRT53_POS (21U) +#define EFM_F1NWPRT1_F1NWPRT53 (0x00200000UL) +#define EFM_F1NWPRT1_F1NWPRT54_POS (22U) +#define EFM_F1NWPRT1_F1NWPRT54 (0x00400000UL) +#define EFM_F1NWPRT1_F1NWPRT55_POS (23U) +#define EFM_F1NWPRT1_F1NWPRT55 (0x00800000UL) +#define EFM_F1NWPRT1_F1NWPRT56_POS (24U) +#define EFM_F1NWPRT1_F1NWPRT56 (0x01000000UL) +#define EFM_F1NWPRT1_F1NWPRT57_POS (25U) +#define EFM_F1NWPRT1_F1NWPRT57 (0x02000000UL) +#define EFM_F1NWPRT1_F1NWPRT58_POS (26U) +#define EFM_F1NWPRT1_F1NWPRT58 (0x04000000UL) +#define EFM_F1NWPRT1_F1NWPRT59_POS (27U) +#define EFM_F1NWPRT1_F1NWPRT59 (0x08000000UL) +#define EFM_F1NWPRT1_F1NWPRT60_POS (28U) +#define EFM_F1NWPRT1_F1NWPRT60 (0x10000000UL) +#define EFM_F1NWPRT1_F1NWPRT61_POS (29U) +#define EFM_F1NWPRT1_F1NWPRT61 (0x20000000UL) +#define EFM_F1NWPRT1_F1NWPRT62_POS (30U) +#define EFM_F1NWPRT1_F1NWPRT62 (0x40000000UL) +#define EFM_F1NWPRT1_F1NWPRT63_POS (31U) +#define EFM_F1NWPRT1_F1NWPRT63 (0x80000000UL) + +/* Bit definition for EFM_F1NWPRT2 register */ +#define EFM_F1NWPRT2_F1NWPRT64_POS (0U) +#define EFM_F1NWPRT2_F1NWPRT64 (0x00000001UL) +#define EFM_F1NWPRT2_F1NWPRT65_POS (1U) +#define EFM_F1NWPRT2_F1NWPRT65 (0x00000002UL) +#define EFM_F1NWPRT2_F1NWPRT66_POS (2U) +#define EFM_F1NWPRT2_F1NWPRT66 (0x00000004UL) +#define EFM_F1NWPRT2_F1NWPRT67_POS (3U) +#define EFM_F1NWPRT2_F1NWPRT67 (0x00000008UL) +#define EFM_F1NWPRT2_F1NWPRT68_POS (4U) +#define EFM_F1NWPRT2_F1NWPRT68 (0x00000010UL) +#define EFM_F1NWPRT2_F1NWPRT69_POS (5U) +#define EFM_F1NWPRT2_F1NWPRT69 (0x00000020UL) +#define EFM_F1NWPRT2_F1NWPRT70_POS (6U) +#define EFM_F1NWPRT2_F1NWPRT70 (0x00000040UL) +#define EFM_F1NWPRT2_F1NWPRT71_POS (7U) +#define EFM_F1NWPRT2_F1NWPRT71 (0x00000080UL) +#define EFM_F1NWPRT2_F1NWPRT72_POS (8U) +#define EFM_F1NWPRT2_F1NWPRT72 (0x00000100UL) +#define EFM_F1NWPRT2_F1NWPRT73_POS (9U) +#define EFM_F1NWPRT2_F1NWPRT73 (0x00000200UL) +#define EFM_F1NWPRT2_F1NWPRT74_POS (10U) +#define EFM_F1NWPRT2_F1NWPRT74 (0x00000400UL) +#define EFM_F1NWPRT2_F1NWPRT75_POS (11U) +#define EFM_F1NWPRT2_F1NWPRT75 (0x00000800UL) +#define EFM_F1NWPRT2_F1NWPRT76_POS (12U) +#define EFM_F1NWPRT2_F1NWPRT76 (0x00001000UL) +#define EFM_F1NWPRT2_F1NWPRT77_POS (13U) +#define EFM_F1NWPRT2_F1NWPRT77 (0x00002000UL) +#define EFM_F1NWPRT2_F1NWPRT78_POS (14U) +#define EFM_F1NWPRT2_F1NWPRT78 (0x00004000UL) +#define EFM_F1NWPRT2_F1NWPRT79_POS (15U) +#define EFM_F1NWPRT2_F1NWPRT79 (0x00008000UL) +#define EFM_F1NWPRT2_F1NWPRT80_POS (16U) +#define EFM_F1NWPRT2_F1NWPRT80 (0x00010000UL) +#define EFM_F1NWPRT2_F1NWPRT81_POS (17U) +#define EFM_F1NWPRT2_F1NWPRT81 (0x00020000UL) +#define EFM_F1NWPRT2_F1NWPRT82_POS (18U) +#define EFM_F1NWPRT2_F1NWPRT82 (0x00040000UL) +#define EFM_F1NWPRT2_F1NWPRT83_POS (19U) +#define EFM_F1NWPRT2_F1NWPRT83 (0x00080000UL) +#define EFM_F1NWPRT2_F1NWPRT84_POS (20U) +#define EFM_F1NWPRT2_F1NWPRT84 (0x00100000UL) +#define EFM_F1NWPRT2_F1NWPRT85_POS (21U) +#define EFM_F1NWPRT2_F1NWPRT85 (0x00200000UL) +#define EFM_F1NWPRT2_F1NWPRT86_POS (22U) +#define EFM_F1NWPRT2_F1NWPRT86 (0x00400000UL) +#define EFM_F1NWPRT2_F1NWPRT87_POS (23U) +#define EFM_F1NWPRT2_F1NWPRT87 (0x00800000UL) +#define EFM_F1NWPRT2_F1NWPRT88_POS (24U) +#define EFM_F1NWPRT2_F1NWPRT88 (0x01000000UL) +#define EFM_F1NWPRT2_F1NWPRT89_POS (25U) +#define EFM_F1NWPRT2_F1NWPRT89 (0x02000000UL) +#define EFM_F1NWPRT2_F1NWPRT90_POS (26U) +#define EFM_F1NWPRT2_F1NWPRT90 (0x04000000UL) +#define EFM_F1NWPRT2_F1NWPRT91_POS (27U) +#define EFM_F1NWPRT2_F1NWPRT91 (0x08000000UL) +#define EFM_F1NWPRT2_F1NWPRT92_POS (28U) +#define EFM_F1NWPRT2_F1NWPRT92 (0x10000000UL) +#define EFM_F1NWPRT2_F1NWPRT93_POS (29U) +#define EFM_F1NWPRT2_F1NWPRT93 (0x20000000UL) +#define EFM_F1NWPRT2_F1NWPRT94_POS (30U) +#define EFM_F1NWPRT2_F1NWPRT94 (0x40000000UL) +#define EFM_F1NWPRT2_F1NWPRT95_POS (31U) +#define EFM_F1NWPRT2_F1NWPRT95 (0x80000000UL) + +/* Bit definition for EFM_F1NWPRT3 register */ +#define EFM_F1NWPRT3_F1NWPRT96_POS (0U) +#define EFM_F1NWPRT3_F1NWPRT96 (0x00000001UL) +#define EFM_F1NWPRT3_F1NWPRT97_POS (1U) +#define EFM_F1NWPRT3_F1NWPRT97 (0x00000002UL) +#define EFM_F1NWPRT3_F1NWPRT98_POS (2U) +#define EFM_F1NWPRT3_F1NWPRT98 (0x00000004UL) +#define EFM_F1NWPRT3_F1NWPRT99_POS (3U) +#define EFM_F1NWPRT3_F1NWPRT99 (0x00000008UL) +#define EFM_F1NWPRT3_F1NWPRT100_POS (4U) +#define EFM_F1NWPRT3_F1NWPRT100 (0x00000010UL) +#define EFM_F1NWPRT3_F1NWPRT101_POS (5U) +#define EFM_F1NWPRT3_F1NWPRT101 (0x00000020UL) +#define EFM_F1NWPRT3_F1NWPRT102_POS (6U) +#define EFM_F1NWPRT3_F1NWPRT102 (0x00000040UL) +#define EFM_F1NWPRT3_F1NWPRT103_POS (7U) +#define EFM_F1NWPRT3_F1NWPRT103 (0x00000080UL) +#define EFM_F1NWPRT3_F1NWPRT104_POS (8U) +#define EFM_F1NWPRT3_F1NWPRT104 (0x00000100UL) +#define EFM_F1NWPRT3_F1NWPRT105_POS (9U) +#define EFM_F1NWPRT3_F1NWPRT105 (0x00000200UL) +#define EFM_F1NWPRT3_F1NWPRT106_POS (10U) +#define EFM_F1NWPRT3_F1NWPRT106 (0x00000400UL) +#define EFM_F1NWPRT3_F1NWPRT107_POS (11U) +#define EFM_F1NWPRT3_F1NWPRT107 (0x00000800UL) +#define EFM_F1NWPRT3_F1NWPRT108_POS (12U) +#define EFM_F1NWPRT3_F1NWPRT108 (0x00001000UL) +#define EFM_F1NWPRT3_F1NWPRT109_POS (13U) +#define EFM_F1NWPRT3_F1NWPRT109 (0x00002000UL) +#define EFM_F1NWPRT3_F1NWPRT110_POS (14U) +#define EFM_F1NWPRT3_F1NWPRT110 (0x00004000UL) +#define EFM_F1NWPRT3_F1NWPRT111_POS (15U) +#define EFM_F1NWPRT3_F1NWPRT111 (0x00008000UL) +#define EFM_F1NWPRT3_F1NWPRT112_POS (16U) +#define EFM_F1NWPRT3_F1NWPRT112 (0x00010000UL) +#define EFM_F1NWPRT3_F1NWPRT113_POS (17U) +#define EFM_F1NWPRT3_F1NWPRT113 (0x00020000UL) +#define EFM_F1NWPRT3_F1NWPRT114_POS (18U) +#define EFM_F1NWPRT3_F1NWPRT114 (0x00040000UL) +#define EFM_F1NWPRT3_F1NWPRT115_POS (19U) +#define EFM_F1NWPRT3_F1NWPRT115 (0x00080000UL) +#define EFM_F1NWPRT3_F1NWPRT116_POS (20U) +#define EFM_F1NWPRT3_F1NWPRT116 (0x00100000UL) +#define EFM_F1NWPRT3_F1NWPRT117_POS (21U) +#define EFM_F1NWPRT3_F1NWPRT117 (0x00200000UL) +#define EFM_F1NWPRT3_F1NWPRT118_POS (22U) +#define EFM_F1NWPRT3_F1NWPRT118 (0x00400000UL) +#define EFM_F1NWPRT3_F1NWPRT119_POS (23U) +#define EFM_F1NWPRT3_F1NWPRT119 (0x00800000UL) +#define EFM_F1NWPRT3_F1NWPRT120_POS (24U) +#define EFM_F1NWPRT3_F1NWPRT120 (0x01000000UL) +#define EFM_F1NWPRT3_F1NWPRT121_POS (25U) +#define EFM_F1NWPRT3_F1NWPRT121 (0x02000000UL) +#define EFM_F1NWPRT3_F1NWPRT122_POS (26U) +#define EFM_F1NWPRT3_F1NWPRT122 (0x04000000UL) +#define EFM_F1NWPRT3_F1NWPRT123_POS (27U) +#define EFM_F1NWPRT3_F1NWPRT123 (0x08000000UL) +#define EFM_F1NWPRT3_F1NWPRT124_POS (28U) +#define EFM_F1NWPRT3_F1NWPRT124 (0x10000000UL) +#define EFM_F1NWPRT3_F1NWPRT125_POS (29U) +#define EFM_F1NWPRT3_F1NWPRT125 (0x20000000UL) +#define EFM_F1NWPRT3_F1NWPRT126_POS (30U) +#define EFM_F1NWPRT3_F1NWPRT126 (0x40000000UL) +#define EFM_F1NWPRT3_F1NWPRT127_POS (31U) +#define EFM_F1NWPRT3_F1NWPRT127 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL1 register */ +#define EMB_CTL1_CMPEN0_POS (0U) +#define EMB_CTL1_CMPEN0 (0x00000001UL) +#define EMB_CTL1_CMPEN1_POS (1U) +#define EMB_CTL1_CMPEN1 (0x00000002UL) +#define EMB_CTL1_CMPEN2_POS (2U) +#define EMB_CTL1_CMPEN2 (0x00000004UL) +#define EMB_CTL1_CMPEN3_POS (3U) +#define EMB_CTL1_CMPEN3 (0x00000008UL) +#define EMB_CTL1_OSCSTPEN_POS (4U) +#define EMB_CTL1_OSCSTPEN (0x00000010UL) +#define EMB_CTL1_PWMSEN0_POS (5U) +#define EMB_CTL1_PWMSEN0 (0x00000020UL) +#define EMB_CTL1_PWMSEN1_POS (6U) +#define EMB_CTL1_PWMSEN1 (0x00000040UL) +#define EMB_CTL1_PWMSEN2_POS (7U) +#define EMB_CTL1_PWMSEN2 (0x00000080UL) +#define EMB_CTL1_PWMSEN3_POS (8U) +#define EMB_CTL1_PWMSEN3 (0x00000100UL) +#define EMB_CTL1_PWMSEN4_POS (9U) +#define EMB_CTL1_PWMSEN4 (0x00000200UL) +#define EMB_CTL1_PWMSEN5_POS (10U) +#define EMB_CTL1_PWMSEN5 (0x00000400UL) +#define EMB_CTL1_PWMSEN6_POS (11U) +#define EMB_CTL1_PWMSEN6 (0x00000800UL) +#define EMB_CTL1_PWMSEN7_POS (12U) +#define EMB_CTL1_PWMSEN7 (0x00001000UL) +#define EMB_CTL1_PORTINEN1_POS (16U) +#define EMB_CTL1_PORTINEN1 (0x00010000UL) +#define EMB_CTL1_PORTINEN2_POS (17U) +#define EMB_CTL1_PORTINEN2 (0x00020000UL) +#define EMB_CTL1_PORTINEN3_POS (18U) +#define EMB_CTL1_PORTINEN3 (0x00040000UL) +#define EMB_CTL1_PORTINEN4_POS (19U) +#define EMB_CTL1_PORTINEN4 (0x00080000UL) +#define EMB_CTL1_INVSEL1_POS (22U) +#define EMB_CTL1_INVSEL1 (0x00400000UL) +#define EMB_CTL1_INVSEL2_POS (23U) +#define EMB_CTL1_INVSEL2 (0x00800000UL) +#define EMB_CTL1_INVSEL3_POS (24U) +#define EMB_CTL1_INVSEL3 (0x01000000UL) +#define EMB_CTL1_INVSEL4_POS (25U) +#define EMB_CTL1_INVSEL4 (0x02000000UL) + +/* Bit definition for EMB_CTL2 register */ +#define EMB_CTL2_PWMLV0_POS (0U) +#define EMB_CTL2_PWMLV0 (0x00000001UL) +#define EMB_CTL2_PWMLV1_POS (1U) +#define EMB_CTL2_PWMLV1 (0x00000002UL) +#define EMB_CTL2_PWMLV2_POS (2U) +#define EMB_CTL2_PWMLV2 (0x00000004UL) +#define EMB_CTL2_PWMLV3_POS (3U) +#define EMB_CTL2_PWMLV3 (0x00000008UL) +#define EMB_CTL2_PWMLV4_POS (4U) +#define EMB_CTL2_PWMLV4 (0x00000010UL) +#define EMB_CTL2_PWMLV5_POS (5U) +#define EMB_CTL2_PWMLV5 (0x00000020UL) +#define EMB_CTL2_PWMLV6_POS (6U) +#define EMB_CTL2_PWMLV6 (0x00000040UL) +#define EMB_CTL2_PWMLV7_POS (7U) +#define EMB_CTL2_PWMLV7 (0x00000080UL) +#define EMB_CTL2_NFSEL1_POS (16U) +#define EMB_CTL2_NFSEL1 (0x00030000UL) +#define EMB_CTL2_NFEN1_POS (18U) +#define EMB_CTL2_NFEN1 (0x00040000UL) +#define EMB_CTL2_NFSEL2_POS (19U) +#define EMB_CTL2_NFSEL2 (0x00180000UL) +#define EMB_CTL2_NFEN2_POS (21U) +#define EMB_CTL2_NFEN2 (0x00200000UL) +#define EMB_CTL2_NFSEL3_POS (22U) +#define EMB_CTL2_NFSEL3 (0x00C00000UL) +#define EMB_CTL2_NFEN3_POS (24U) +#define EMB_CTL2_NFEN3 (0x01000000UL) +#define EMB_CTL2_NFSEL4_POS (25U) +#define EMB_CTL2_NFSEL4 (0x06000000UL) +#define EMB_CTL2_NFEN4_POS (27U) +#define EMB_CTL2_NFEN4 (0x08000000UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_OSF_POS (3U) +#define EMB_STAT_OSF (0x00000008UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) +#define EMB_STAT_CMPST_POS (6U) +#define EMB_STAT_CMPST (0x00000040UL) +#define EMB_STAT_OSST_POS (7U) +#define EMB_STAT_OSST (0x00000080UL) +#define EMB_STAT_PORTINF1_POS (8U) +#define EMB_STAT_PORTINF1 (0x00000100UL) +#define EMB_STAT_PORTINF2_POS (9U) +#define EMB_STAT_PORTINF2 (0x00000200UL) +#define EMB_STAT_PORTINF3_POS (10U) +#define EMB_STAT_PORTINF3 (0x00000400UL) +#define EMB_STAT_PORTINF4_POS (11U) +#define EMB_STAT_PORTINF4 (0x00000800UL) +#define EMB_STAT_PORTINST1_POS (14U) +#define EMB_STAT_PORTINST1 (0x00004000UL) +#define EMB_STAT_PORTINST2_POS (15U) +#define EMB_STAT_PORTINST2 (0x00008000UL) +#define EMB_STAT_PORTINST3_POS (16U) +#define EMB_STAT_PORTINST3 (0x00010000UL) +#define EMB_STAT_PORTINST4_POS (17U) +#define EMB_STAT_PORTINST4 (0x00020000UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_OSFCLR_POS (3U) +#define EMB_STATCLR_OSFCLR (0x00000008UL) +#define EMB_STATCLR_PORTINFCLR1_POS (8U) +#define EMB_STATCLR_PORTINFCLR1 (0x00000100UL) +#define EMB_STATCLR_PORTINFCLR2_POS (9U) +#define EMB_STATCLR_PORTINFCLR2 (0x00000200UL) +#define EMB_STATCLR_PORTINFCLR3_POS (10U) +#define EMB_STATCLR_PORTINFCLR3 (0x00000400UL) +#define EMB_STATCLR_PORTINFCLR4_POS (11U) +#define EMB_STATCLR_PORTINFCLR4 (0x00000800UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_OSINTEN_POS (3U) +#define EMB_INTEN_OSINTEN (0x00000008UL) +#define EMB_INTEN_PORTINTEN1_POS (8U) +#define EMB_INTEN_PORTINTEN1 (0x00000100UL) +#define EMB_INTEN_PORTINTEN2_POS (9U) +#define EMB_INTEN_PORTINTEN2 (0x00000200UL) +#define EMB_INTEN_PORTINTEN3_POS (10U) +#define EMB_INTEN_PORTINTEN3 (0x00000400UL) +#define EMB_INTEN_PORTINTEN4_POS (11U) +#define EMB_INTEN_PORTINTEN4 (0x00000800UL) + +/* Bit definition for EMB_RLSSEL register */ +#define EMB_RLSSEL_PWMRSEL_POS (1U) +#define EMB_RLSSEL_PWMRSEL (0x00000002UL) +#define EMB_RLSSEL_CMPRSEL_POS (2U) +#define EMB_RLSSEL_CMPRSEL (0x00000004UL) +#define EMB_RLSSEL_OSRSEL_POS (3U) +#define EMB_RLSSEL_OSRSEL (0x00000008UL) +#define EMB_RLSSEL_PORTINRSEL1_POS (8U) +#define EMB_RLSSEL_PORTINRSEL1 (0x00000100UL) +#define EMB_RLSSEL_PORTINRSEL2_POS (9U) +#define EMB_RLSSEL_PORTINRSEL2 (0x00000200UL) +#define EMB_RLSSEL_PORTINRSEL3_POS (10U) +#define EMB_RLSSEL_PORTINRSEL3 (0x00000400UL) +#define EMB_RLSSEL_PORTINRSEL4_POS (11U) +#define EMB_RLSSEL_PORTINRSEL4 (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral ETH +*******************************************************************************/ +/* Bit definition for ETH_MAC_IFCONFR register */ +#define ETH_MAC_IFCONFR_IFSEL_POS (0U) +#define ETH_MAC_IFCONFR_IFSEL (0x00000001UL) +#define ETH_MAC_IFCONFR_RCKINV_POS (4U) +#define ETH_MAC_IFCONFR_RCKINV (0x00000010UL) +#define ETH_MAC_IFCONFR_TCKINV_POS (5U) +#define ETH_MAC_IFCONFR_TCKINV (0x00000020UL) + +/* Bit definition for ETH_MAC_CONFIGR register */ +#define ETH_MAC_CONFIGR_RE_POS (2U) +#define ETH_MAC_CONFIGR_RE (0x00000004UL) +#define ETH_MAC_CONFIGR_TE_POS (3U) +#define ETH_MAC_CONFIGR_TE (0x00000008UL) +#define ETH_MAC_CONFIGR_DC_POS (4U) +#define ETH_MAC_CONFIGR_DC (0x00000010UL) +#define ETH_MAC_CONFIGR_BL_POS (5U) +#define ETH_MAC_CONFIGR_BL (0x00000060UL) +#define ETH_MAC_CONFIGR_BL_0 (0x00000020UL) +#define ETH_MAC_CONFIGR_BL_1 (0x00000040UL) +#define ETH_MAC_CONFIGR_ACS_POS (7U) +#define ETH_MAC_CONFIGR_ACS (0x00000080UL) +#define ETH_MAC_CONFIGR_DRTY_POS (9U) +#define ETH_MAC_CONFIGR_DRTY (0x00000200UL) +#define ETH_MAC_CONFIGR_IPCO_POS (10U) +#define ETH_MAC_CONFIGR_IPCO (0x00000400UL) +#define ETH_MAC_CONFIGR_DM_POS (11U) +#define ETH_MAC_CONFIGR_DM (0x00000800UL) +#define ETH_MAC_CONFIGR_LM_POS (12U) +#define ETH_MAC_CONFIGR_LM (0x00001000UL) +#define ETH_MAC_CONFIGR_DO_POS (13U) +#define ETH_MAC_CONFIGR_DO (0x00002000UL) +#define ETH_MAC_CONFIGR_FES_POS (14U) +#define ETH_MAC_CONFIGR_FES (0x00004000UL) +#define ETH_MAC_CONFIGR_DCRS_POS (16U) +#define ETH_MAC_CONFIGR_DCRS (0x00010000UL) +#define ETH_MAC_CONFIGR_IFG_POS (17U) +#define ETH_MAC_CONFIGR_IFG (0x000E0000UL) +#define ETH_MAC_CONFIGR_IFG_0 (0x00020000UL) +#define ETH_MAC_CONFIGR_IFG_1 (0x00040000UL) +#define ETH_MAC_CONFIGR_IFG_2 (0x00080000UL) +#define ETH_MAC_CONFIGR_MJB_POS (22U) +#define ETH_MAC_CONFIGR_MJB (0x00400000UL) +#define ETH_MAC_CONFIGR_MWD_POS (23U) +#define ETH_MAC_CONFIGR_MWD (0x00800000UL) +#define ETH_MAC_CONFIGR_CST_POS (25U) +#define ETH_MAC_CONFIGR_CST (0x02000000UL) +#define ETH_MAC_CONFIGR_SAIRC_POS (28U) +#define ETH_MAC_CONFIGR_SAIRC (0x70000000UL) +#define ETH_MAC_CONFIGR_SAIRC_0 (0x10000000UL) +#define ETH_MAC_CONFIGR_SAIRC_1 (0x20000000UL) +#define ETH_MAC_CONFIGR_SAIRC_2 (0x40000000UL) + +/* Bit definition for ETH_MAC_FLTCTLR register */ +#define ETH_MAC_FLTCTLR_PR_POS (0U) +#define ETH_MAC_FLTCTLR_PR (0x00000001UL) +#define ETH_MAC_FLTCTLR_HUC_POS (1U) +#define ETH_MAC_FLTCTLR_HUC (0x00000002UL) +#define ETH_MAC_FLTCTLR_HMC_POS (2U) +#define ETH_MAC_FLTCTLR_HMC (0x00000004UL) +#define ETH_MAC_FLTCTLR_DAIF_POS (3U) +#define ETH_MAC_FLTCTLR_DAIF (0x00000008UL) +#define ETH_MAC_FLTCTLR_PMF_POS (4U) +#define ETH_MAC_FLTCTLR_PMF (0x00000010UL) +#define ETH_MAC_FLTCTLR_DBF_POS (5U) +#define ETH_MAC_FLTCTLR_DBF (0x00000020UL) +#define ETH_MAC_FLTCTLR_PCF_POS (6U) +#define ETH_MAC_FLTCTLR_PCF (0x000000C0UL) +#define ETH_MAC_FLTCTLR_PCF_0 (0x00000040UL) +#define ETH_MAC_FLTCTLR_PCF_1 (0x00000080UL) +#define ETH_MAC_FLTCTLR_SAIF_POS (8U) +#define ETH_MAC_FLTCTLR_SAIF (0x00000100UL) +#define ETH_MAC_FLTCTLR_SAF_POS (9U) +#define ETH_MAC_FLTCTLR_SAF (0x00000200UL) +#define ETH_MAC_FLTCTLR_HPF_POS (10U) +#define ETH_MAC_FLTCTLR_HPF (0x00000400UL) +#define ETH_MAC_FLTCTLR_VTFE_POS (16U) +#define ETH_MAC_FLTCTLR_VTFE (0x00010000UL) +#define ETH_MAC_FLTCTLR_IPFE_POS (20U) +#define ETH_MAC_FLTCTLR_IPFE (0x00100000UL) +#define ETH_MAC_FLTCTLR_DNTU_POS (21U) +#define ETH_MAC_FLTCTLR_DNTU (0x00200000UL) +#define ETH_MAC_FLTCTLR_RA_POS (31U) +#define ETH_MAC_FLTCTLR_RA (0x80000000UL) + +/* Bit definition for ETH_MAC_HASHTHR register */ +#define ETH_MAC_HASHTHR_HTH (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_HASHTLR register */ +#define ETH_MAC_HASHTLR_HTL (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_SMIADDR register */ +#define ETH_MAC_SMIADDR_SMIB_POS (0U) +#define ETH_MAC_SMIADDR_SMIB (0x00000001UL) +#define ETH_MAC_SMIADDR_SMIW_POS (1U) +#define ETH_MAC_SMIADDR_SMIW (0x00000002UL) +#define ETH_MAC_SMIADDR_SMIC_POS (2U) +#define ETH_MAC_SMIADDR_SMIC (0x0000003CUL) +#define ETH_MAC_SMIADDR_SMIC_0 (0x00000004UL) +#define ETH_MAC_SMIADDR_SMIC_1 (0x00000008UL) +#define ETH_MAC_SMIADDR_SMIC_2 (0x00000010UL) +#define ETH_MAC_SMIADDR_SMIC_3 (0x00000020UL) +#define ETH_MAC_SMIADDR_SMIR_POS (6U) +#define ETH_MAC_SMIADDR_SMIR (0x000007C0UL) +#define ETH_MAC_SMIADDR_SMIR_0 (0x00000040UL) +#define ETH_MAC_SMIADDR_SMIR_1 (0x00000080UL) +#define ETH_MAC_SMIADDR_SMIR_2 (0x00000100UL) +#define ETH_MAC_SMIADDR_SMIR_3 (0x00000200UL) +#define ETH_MAC_SMIADDR_SMIR_4 (0x00000400UL) +#define ETH_MAC_SMIADDR_SMIA_POS (11U) +#define ETH_MAC_SMIADDR_SMIA (0x0000F800UL) +#define ETH_MAC_SMIADDR_SMIA_0 (0x00000800UL) +#define ETH_MAC_SMIADDR_SMIA_1 (0x00001000UL) +#define ETH_MAC_SMIADDR_SMIA_2 (0x00002000UL) +#define ETH_MAC_SMIADDR_SMIA_3 (0x00004000UL) +#define ETH_MAC_SMIADDR_SMIA_4 (0x00008000UL) + +/* Bit definition for ETH_MAC_SMIDATR register */ +#define ETH_MAC_SMIDATR_SMID (0x0000FFFFUL) + +/* Bit definition for ETH_MAC_FLOCTLR register */ +#define ETH_MAC_FLOCTLR_FCA_BPA_POS (0U) +#define ETH_MAC_FLOCTLR_FCA_BPA (0x00000001UL) +#define ETH_MAC_FLOCTLR_TFE_POS (1U) +#define ETH_MAC_FLOCTLR_TFE (0x00000002UL) +#define ETH_MAC_FLOCTLR_RFE_POS (2U) +#define ETH_MAC_FLOCTLR_RFE (0x00000004UL) +#define ETH_MAC_FLOCTLR_UNP_POS (3U) +#define ETH_MAC_FLOCTLR_UNP (0x00000008UL) +#define ETH_MAC_FLOCTLR_PLT_POS (4U) +#define ETH_MAC_FLOCTLR_PLT (0x00000030UL) +#define ETH_MAC_FLOCTLR_PLT_0 (0x00000010UL) +#define ETH_MAC_FLOCTLR_PLT_1 (0x00000020UL) +#define ETH_MAC_FLOCTLR_DZPQ_POS (7U) +#define ETH_MAC_FLOCTLR_DZPQ (0x00000080UL) +#define ETH_MAC_FLOCTLR_PAUSET_POS (16U) +#define ETH_MAC_FLOCTLR_PAUSET (0xFFFF0000UL) + +/* Bit definition for ETH_MAC_VTAFLTR register */ +#define ETH_MAC_VTAFLTR_VLFLT_POS (0U) +#define ETH_MAC_VTAFLTR_VLFLT (0x0000FFFFUL) +#define ETH_MAC_VTAFLTR_VTAL_POS (16U) +#define ETH_MAC_VTAFLTR_VTAL (0x00010000UL) +#define ETH_MAC_VTAFLTR_VTIM_POS (17U) +#define ETH_MAC_VTAFLTR_VTIM (0x00020000UL) +#define ETH_MAC_VTAFLTR_VTHM_POS (19U) +#define ETH_MAC_VTAFLTR_VTHM (0x00080000UL) + +/* Bit definition for ETH_MAC_MACSTSR register */ +#define ETH_MAC_MACSTSR_MREA_POS (0U) +#define ETH_MAC_MACSTSR_MREA (0x00000001UL) +#define ETH_MAC_MACSTSR_MRS_POS (1U) +#define ETH_MAC_MACSTSR_MRS (0x00000006UL) +#define ETH_MAC_MACSTSR_MRS_0 (0x00000002UL) +#define ETH_MAC_MACSTSR_MRS_1 (0x00000004UL) +#define ETH_MAC_MACSTSR_RFWA_POS (4U) +#define ETH_MAC_MACSTSR_RFWA (0x00000010UL) +#define ETH_MAC_MACSTSR_RFRS_POS (5U) +#define ETH_MAC_MACSTSR_RFRS (0x00000060UL) +#define ETH_MAC_MACSTSR_RFRS_0 (0x00000020UL) +#define ETH_MAC_MACSTSR_RFRS_1 (0x00000040UL) +#define ETH_MAC_MACSTSR_RFFL_POS (8U) +#define ETH_MAC_MACSTSR_RFFL (0x00000300UL) +#define ETH_MAC_MACSTSR_RFFL_0 (0x00000100UL) +#define ETH_MAC_MACSTSR_RFFL_1 (0x00000200UL) +#define ETH_MAC_MACSTSR_MTEA_POS (16U) +#define ETH_MAC_MACSTSR_MTEA (0x00010000UL) +#define ETH_MAC_MACSTSR_MTS_POS (17U) +#define ETH_MAC_MACSTSR_MTS (0x00060000UL) +#define ETH_MAC_MACSTSR_MTS_0 (0x00020000UL) +#define ETH_MAC_MACSTSR_MTS_1 (0x00040000UL) +#define ETH_MAC_MACSTSR_MTP_POS (19U) +#define ETH_MAC_MACSTSR_MTP (0x00080000UL) +#define ETH_MAC_MACSTSR_TFRS_POS (20U) +#define ETH_MAC_MACSTSR_TFRS (0x00300000UL) +#define ETH_MAC_MACSTSR_TFRS_0 (0x00100000UL) +#define ETH_MAC_MACSTSR_TFRS_1 (0x00200000UL) +#define ETH_MAC_MACSTSR_TFWA_POS (22U) +#define ETH_MAC_MACSTSR_TFWA (0x00400000UL) +#define ETH_MAC_MACSTSR_TFNE_POS (24U) +#define ETH_MAC_MACSTSR_TFNE (0x01000000UL) +#define ETH_MAC_MACSTSR_TFF_POS (25U) +#define ETH_MAC_MACSTSR_TFF (0x02000000UL) + +/* Bit definition for ETH_MAC_RTWKFFR register */ +#define ETH_MAC_RTWKFFR_WKUPFRMFT (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_PMTCTLR register */ +#define ETH_MAC_PMTCTLR_PWDN_POS (0U) +#define ETH_MAC_PMTCTLR_PWDN (0x00000001UL) +#define ETH_MAC_PMTCTLR_MPEN_POS (1U) +#define ETH_MAC_PMTCTLR_MPEN (0x00000002UL) +#define ETH_MAC_PMTCTLR_WKEN_POS (2U) +#define ETH_MAC_PMTCTLR_WKEN (0x00000004UL) +#define ETH_MAC_PMTCTLR_MPFR_POS (5U) +#define ETH_MAC_PMTCTLR_MPFR (0x00000020UL) +#define ETH_MAC_PMTCTLR_WKFR_POS (6U) +#define ETH_MAC_PMTCTLR_WKFR (0x00000040UL) +#define ETH_MAC_PMTCTLR_GLUB_POS (9U) +#define ETH_MAC_PMTCTLR_GLUB (0x00000200UL) +#define ETH_MAC_PMTCTLR_RTWKTR_POS (10U) +#define ETH_MAC_PMTCTLR_RTWKTR (0x00000400UL) +#define ETH_MAC_PMTCTLR_RTWKPT_POS (24U) +#define ETH_MAC_PMTCTLR_RTWKPT (0x07000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_0 (0x01000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_1 (0x02000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_2 (0x04000000UL) +#define ETH_MAC_PMTCTLR_RTWKFR_POS (31U) +#define ETH_MAC_PMTCTLR_RTWKFR (0x80000000UL) + +/* Bit definition for ETH_MAC_INTSTSR register */ +#define ETH_MAC_INTSTSR_PMTIS_POS (3U) +#define ETH_MAC_INTSTSR_PMTIS (0x00000008UL) +#define ETH_MAC_INTSTSR_MMCIS_POS (4U) +#define ETH_MAC_INTSTSR_MMCIS (0x00000010UL) +#define ETH_MAC_INTSTSR_MMCRXIS_POS (5U) +#define ETH_MAC_INTSTSR_MMCRXIS (0x00000020UL) +#define ETH_MAC_INTSTSR_MMCTXIS_POS (6U) +#define ETH_MAC_INTSTSR_MMCTXIS (0x00000040UL) +#define ETH_MAC_INTSTSR_TSPIS_POS (9U) +#define ETH_MAC_INTSTSR_TSPIS (0x00000200UL) + +/* Bit definition for ETH_MAC_INTMSKR register */ +#define ETH_MAC_INTMSKR_PMTIM_POS (3U) +#define ETH_MAC_INTMSKR_PMTIM (0x00000008UL) +#define ETH_MAC_INTMSKR_TSPIM_POS (9U) +#define ETH_MAC_INTMSKR_TSPIM (0x00000200UL) + +/* Bit definition for ETH_MAC_MACADHR0 register */ +#define ETH_MAC_MACADHR0_ADDRH0_POS (0U) +#define ETH_MAC_MACADHR0_ADDRH0 (0x0000FFFFUL) +#define ETH_MAC_MACADHR0_AE0_POS (31U) +#define ETH_MAC_MACADHR0_AE0 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR0 register */ +#define ETH_MAC_MACADLR0_ADDRL0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR1 register */ +#define ETH_MAC_MACADHR1_ADDRH1_POS (0U) +#define ETH_MAC_MACADHR1_ADDRH1 (0x0000FFFFUL) +#define ETH_MAC_MACADHR1_MBC1_POS (24U) +#define ETH_MAC_MACADHR1_MBC1 (0x3F000000UL) +#define ETH_MAC_MACADHR1_MBC1_0 (0x01000000UL) +#define ETH_MAC_MACADHR1_MBC1_1 (0x02000000UL) +#define ETH_MAC_MACADHR1_MBC1_2 (0x04000000UL) +#define ETH_MAC_MACADHR1_MBC1_3 (0x08000000UL) +#define ETH_MAC_MACADHR1_MBC1_4 (0x10000000UL) +#define ETH_MAC_MACADHR1_MBC1_5 (0x20000000UL) +#define ETH_MAC_MACADHR1_SA1_POS (30U) +#define ETH_MAC_MACADHR1_SA1 (0x40000000UL) +#define ETH_MAC_MACADHR1_AE1_POS (31U) +#define ETH_MAC_MACADHR1_AE1 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR1 register */ +#define ETH_MAC_MACADLR1_ADDRL1 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR2 register */ +#define ETH_MAC_MACADHR2_ADDRH2_POS (0U) +#define ETH_MAC_MACADHR2_ADDRH2 (0x0000FFFFUL) +#define ETH_MAC_MACADHR2_MBC2_POS (24U) +#define ETH_MAC_MACADHR2_MBC2 (0x3F000000UL) +#define ETH_MAC_MACADHR2_MBC2_0 (0x01000000UL) +#define ETH_MAC_MACADHR2_MBC2_1 (0x02000000UL) +#define ETH_MAC_MACADHR2_MBC2_2 (0x04000000UL) +#define ETH_MAC_MACADHR2_MBC2_3 (0x08000000UL) +#define ETH_MAC_MACADHR2_MBC2_4 (0x10000000UL) +#define ETH_MAC_MACADHR2_MBC2_5 (0x20000000UL) +#define ETH_MAC_MACADHR2_SA2_POS (30U) +#define ETH_MAC_MACADHR2_SA2 (0x40000000UL) +#define ETH_MAC_MACADHR2_AE2_POS (31U) +#define ETH_MAC_MACADHR2_AE2 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR2 register */ +#define ETH_MAC_MACADLR2_ADDRL2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR3 register */ +#define ETH_MAC_MACADHR3_ADDRH3_POS (0U) +#define ETH_MAC_MACADHR3_ADDRH3 (0x0000FFFFUL) +#define ETH_MAC_MACADHR3_MBC3_POS (24U) +#define ETH_MAC_MACADHR3_MBC3 (0x3F000000UL) +#define ETH_MAC_MACADHR3_MBC3_0 (0x01000000UL) +#define ETH_MAC_MACADHR3_MBC3_1 (0x02000000UL) +#define ETH_MAC_MACADHR3_MBC3_2 (0x04000000UL) +#define ETH_MAC_MACADHR3_MBC3_3 (0x08000000UL) +#define ETH_MAC_MACADHR3_MBC3_4 (0x10000000UL) +#define ETH_MAC_MACADHR3_MBC3_5 (0x20000000UL) +#define ETH_MAC_MACADHR3_SA3_POS (30U) +#define ETH_MAC_MACADHR3_SA3 (0x40000000UL) +#define ETH_MAC_MACADHR3_AE3_POS (31U) +#define ETH_MAC_MACADHR3_AE3 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR3 register */ +#define ETH_MAC_MACADLR3_ADDRL3 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR4 register */ +#define ETH_MAC_MACADHR4_ADDRH4_POS (0U) +#define ETH_MAC_MACADHR4_ADDRH4 (0x0000FFFFUL) +#define ETH_MAC_MACADHR4_MBC4_POS (24U) +#define ETH_MAC_MACADHR4_MBC4 (0x3F000000UL) +#define ETH_MAC_MACADHR4_MBC4_0 (0x01000000UL) +#define ETH_MAC_MACADHR4_MBC4_1 (0x02000000UL) +#define ETH_MAC_MACADHR4_MBC4_2 (0x04000000UL) +#define ETH_MAC_MACADHR4_MBC4_3 (0x08000000UL) +#define ETH_MAC_MACADHR4_MBC4_4 (0x10000000UL) +#define ETH_MAC_MACADHR4_MBC4_5 (0x20000000UL) +#define ETH_MAC_MACADHR4_SA4_POS (30U) +#define ETH_MAC_MACADHR4_SA4 (0x40000000UL) +#define ETH_MAC_MACADHR4_AE4_POS (31U) +#define ETH_MAC_MACADHR4_AE4 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR4 register */ +#define ETH_MAC_MACADLR4_ADDRL4 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MMC_MMCCTLR register */ +#define ETH_MMC_MMCCTLR_CRST_POS (0U) +#define ETH_MMC_MMCCTLR_CRST (0x00000001UL) +#define ETH_MMC_MMCCTLR_COS_POS (1U) +#define ETH_MMC_MMCCTLR_COS (0x00000002UL) +#define ETH_MMC_MMCCTLR_ROR_POS (2U) +#define ETH_MMC_MMCCTLR_ROR (0x00000004UL) +#define ETH_MMC_MMCCTLR_MCF_POS (3U) +#define ETH_MMC_MMCCTLR_MCF (0x00000008UL) +#define ETH_MMC_MMCCTLR_MCPSET_POS (4U) +#define ETH_MMC_MMCCTLR_MCPSET (0x00000010UL) +#define ETH_MMC_MMCCTLR_MCPSEL_POS (5U) +#define ETH_MMC_MMCCTLR_MCPSEL (0x00000020UL) + +/* Bit definition for ETH_MMC_REVSTSR register */ +#define ETH_MMC_REVSTSR_RXBGIS_POS (3U) +#define ETH_MMC_REVSTSR_RXBGIS (0x00000008UL) +#define ETH_MMC_REVSTSR_RXMGIS_POS (4U) +#define ETH_MMC_REVSTSR_RXMGIS (0x00000010UL) +#define ETH_MMC_REVSTSR_RXCEIS_POS (5U) +#define ETH_MMC_REVSTSR_RXCEIS (0x00000020UL) +#define ETH_MMC_REVSTSR_RXAEIS_POS (6U) +#define ETH_MMC_REVSTSR_RXAEIS (0x00000040UL) +#define ETH_MMC_REVSTSR_RXREIS_POS (7U) +#define ETH_MMC_REVSTSR_RXREIS (0x00000080UL) +#define ETH_MMC_REVSTSR_RXUGIS_POS (17U) +#define ETH_MMC_REVSTSR_RXUGIS (0x00020000UL) +#define ETH_MMC_REVSTSR_RXLEIS_POS (18U) +#define ETH_MMC_REVSTSR_RXLEIS (0x00040000UL) +#define ETH_MMC_REVSTSR_RXOEIS_POS (19U) +#define ETH_MMC_REVSTSR_RXOEIS (0x00080000UL) + +/* Bit definition for ETH_MMC_TRSSTSR register */ +#define ETH_MMC_TRSSTSR_TXBGIS_POS (2U) +#define ETH_MMC_TRSSTSR_TXBGIS (0x00000004UL) +#define ETH_MMC_TRSSTSR_TXMGIS_POS (3U) +#define ETH_MMC_TRSSTSR_TXMGIS (0x00000008UL) +#define ETH_MMC_TRSSTSR_TXDEEIS_POS (16U) +#define ETH_MMC_TRSSTSR_TXDEEIS (0x00010000UL) +#define ETH_MMC_TRSSTSR_TXLCEIS_POS (17U) +#define ETH_MMC_TRSSTSR_TXLCEIS (0x00020000UL) +#define ETH_MMC_TRSSTSR_TXECEIS_POS (18U) +#define ETH_MMC_TRSSTSR_TXECEIS (0x00040000UL) +#define ETH_MMC_TRSSTSR_TXCAEIS_POS (19U) +#define ETH_MMC_TRSSTSR_TXCAEIS (0x00080000UL) +#define ETH_MMC_TRSSTSR_TXUGIS_POS (21U) +#define ETH_MMC_TRSSTSR_TXUGIS (0x00200000UL) +#define ETH_MMC_TRSSTSR_TXEDEIS_POS (22U) +#define ETH_MMC_TRSSTSR_TXEDEIS (0x00400000UL) + +/* Bit definition for ETH_MMC_RITCTLR register */ +#define ETH_MMC_RITCTLR_RXBGIM_POS (3U) +#define ETH_MMC_RITCTLR_RXBGIM (0x00000008UL) +#define ETH_MMC_RITCTLR_RXMGIM_POS (4U) +#define ETH_MMC_RITCTLR_RXMGIM (0x00000010UL) +#define ETH_MMC_RITCTLR_RXCEIM_POS (5U) +#define ETH_MMC_RITCTLR_RXCEIM (0x00000020UL) +#define ETH_MMC_RITCTLR_RXAEIM_POS (6U) +#define ETH_MMC_RITCTLR_RXAEIM (0x00000040UL) +#define ETH_MMC_RITCTLR_RXREIM_POS (7U) +#define ETH_MMC_RITCTLR_RXREIM (0x00000080UL) +#define ETH_MMC_RITCTLR_RXUGIM_POS (17U) +#define ETH_MMC_RITCTLR_RXUGIM (0x00020000UL) +#define ETH_MMC_RITCTLR_RXLEIM_POS (18U) +#define ETH_MMC_RITCTLR_RXLEIM (0x00040000UL) +#define ETH_MMC_RITCTLR_RXOEIM_POS (19U) +#define ETH_MMC_RITCTLR_RXOEIM (0x00080000UL) + +/* Bit definition for ETH_MMC_TITCTLR register */ +#define ETH_MMC_TITCTLR_TXBGIM_POS (2U) +#define ETH_MMC_TITCTLR_TXBGIM (0x00000004UL) +#define ETH_MMC_TITCTLR_TXMGIM_POS (3U) +#define ETH_MMC_TITCTLR_TXMGIM (0x00000008UL) +#define ETH_MMC_TITCTLR_TXDEEIM_POS (16U) +#define ETH_MMC_TITCTLR_TXDEEIM (0x00010000UL) +#define ETH_MMC_TITCTLR_TXLCEIM_POS (17U) +#define ETH_MMC_TITCTLR_TXLCEIM (0x00020000UL) +#define ETH_MMC_TITCTLR_TXECEIM_POS (18U) +#define ETH_MMC_TITCTLR_TXECEIM (0x00040000UL) +#define ETH_MMC_TITCTLR_TXCAEIM_POS (19U) +#define ETH_MMC_TITCTLR_TXCAEIM (0x00080000UL) +#define ETH_MMC_TITCTLR_TXUGIM_POS (21U) +#define ETH_MMC_TITCTLR_TXUGIM (0x00200000UL) +#define ETH_MMC_TITCTLR_TXEDEIM_POS (22U) +#define ETH_MMC_TITCTLR_TXEDEIM (0x00400000UL) + +/* Bit definition for ETH_MMC_TXBRGFR register */ +#define ETH_MMC_TXBRGFR_TXBRGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXMUGFR register */ +#define ETH_MMC_TXMUGFR_TXMUGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXDEEFR register */ +#define ETH_MMC_TXDEEFR_TXDEECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXLCEFR register */ +#define ETH_MMC_TXLCEFR_TXLCECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXECEFR register */ +#define ETH_MMC_TXECEFR_TXECECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXCAEFR register */ +#define ETH_MMC_TXCAEFR_TXCAECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXUNGFR register */ +#define ETH_MMC_TXUNGFR_TXUNGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXEDEFR register */ +#define ETH_MMC_TXEDEFR_TXEDECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXBRGFR register */ +#define ETH_MMC_RXBRGFR_RXBRGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXMUGFR register */ +#define ETH_MMC_RXMUGFR_RXMUGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXCREFR register */ +#define ETH_MMC_RXCREFR_RXCRECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXALEFR register */ +#define ETH_MMC_RXALEFR_RXALECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXRUEFR register */ +#define ETH_MMC_RXRUEFR_RXRUECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXUNGFR register */ +#define ETH_MMC_RXUNGFR_RXUNGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXLEEFR register */ +#define ETH_MMC_RXLEEFR_RXLEECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXOREFR register */ +#define ETH_MMC_RXOREFR_RXORECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MAC_L34CTLR register */ +#define ETH_MAC_L34CTLR_L3PEN_POS (0U) +#define ETH_MAC_L34CTLR_L3PEN (0x00000001UL) +#define ETH_MAC_L34CTLR_L3SAM_POS (2U) +#define ETH_MAC_L34CTLR_L3SAM (0x00000004UL) +#define ETH_MAC_L34CTLR_L3SAIM_POS (3U) +#define ETH_MAC_L34CTLR_L3SAIM (0x00000008UL) +#define ETH_MAC_L34CTLR_L3DAM_POS (4U) +#define ETH_MAC_L34CTLR_L3DAM (0x00000010UL) +#define ETH_MAC_L34CTLR_L3DAIM_POS (5U) +#define ETH_MAC_L34CTLR_L3DAIM (0x00000020UL) +#define ETH_MAC_L34CTLR_L3HSBM_POS (6U) +#define ETH_MAC_L34CTLR_L3HSBM (0x000007C0UL) +#define ETH_MAC_L34CTLR_L3HSBM_0 (0x00000040UL) +#define ETH_MAC_L34CTLR_L3HSBM_1 (0x00000080UL) +#define ETH_MAC_L34CTLR_L3HSBM_2 (0x00000100UL) +#define ETH_MAC_L34CTLR_L3HSBM_3 (0x00000200UL) +#define ETH_MAC_L34CTLR_L3HSBM_4 (0x00000400UL) +#define ETH_MAC_L34CTLR_L3HDBM_POS (11U) +#define ETH_MAC_L34CTLR_L3HDBM (0x0000F800UL) +#define ETH_MAC_L34CTLR_L3HDBM_0 (0x00000800UL) +#define ETH_MAC_L34CTLR_L3HDBM_1 (0x00001000UL) +#define ETH_MAC_L34CTLR_L3HDBM_2 (0x00002000UL) +#define ETH_MAC_L34CTLR_L3HDBM_3 (0x00004000UL) +#define ETH_MAC_L34CTLR_L3HDBM_4 (0x00008000UL) +#define ETH_MAC_L34CTLR_L4PEN_POS (16U) +#define ETH_MAC_L34CTLR_L4PEN (0x00010000UL) +#define ETH_MAC_L34CTLR_L4SPM_POS (18U) +#define ETH_MAC_L34CTLR_L4SPM (0x00040000UL) +#define ETH_MAC_L34CTLR_L4SPIM_POS (19U) +#define ETH_MAC_L34CTLR_L4SPIM (0x00080000UL) +#define ETH_MAC_L34CTLR_L4DPM_POS (20U) +#define ETH_MAC_L34CTLR_L4DPM (0x00100000UL) +#define ETH_MAC_L34CTLR_L4DPIM_POS (21U) +#define ETH_MAC_L34CTLR_L4DPIM (0x00200000UL) + +/* Bit definition for ETH_MAC_L4PORTR register */ +#define ETH_MAC_L4PORTR_L4SPVAL_POS (0U) +#define ETH_MAC_L4PORTR_L4SPVAL (0x0000FFFFUL) +#define ETH_MAC_L4PORTR_L4DPVAL_POS (16U) +#define ETH_MAC_L4PORTR_L4DPVAL (0xFFFF0000UL) + +/* Bit definition for ETH_MAC_L3ADDRR0 register */ +#define ETH_MAC_L3ADDRR0_L3ADDR0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR1 register */ +#define ETH_MAC_L3ADDRR1_L3ADDR2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR2 register */ +#define ETH_MAC_L3ADDRR2_L3ADDR2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR3 register */ +#define ETH_MAC_L3ADDRR3_L3ADDR3 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_VTACTLR register */ +#define ETH_MAC_VTACTLR_VLANV_POS (0U) +#define ETH_MAC_VTACTLR_VLANV (0x0000FFFFUL) +#define ETH_MAC_VTACTLR_VLANC_POS (16U) +#define ETH_MAC_VTACTLR_VLANC (0x00030000UL) +#define ETH_MAC_VTACTLR_VLANC_0 (0x00010000UL) +#define ETH_MAC_VTACTLR_VLANC_1 (0x00020000UL) +#define ETH_MAC_VTACTLR_VLANS_POS (18U) +#define ETH_MAC_VTACTLR_VLANS (0x00040000UL) + +/* Bit definition for ETH_MAC_VLAHTBR register */ +#define ETH_MAC_VLAHTBR_VLHT (0x0000FFFFUL) + +/* Bit definition for ETH_PTP_TSPCTLR register */ +#define ETH_PTP_TSPCTLR_TSPEN_POS (0U) +#define ETH_PTP_TSPCTLR_TSPEN (0x00000001UL) +#define ETH_PTP_TSPCTLR_TSPUPSEL_POS (1U) +#define ETH_PTP_TSPCTLR_TSPUPSEL (0x00000002UL) +#define ETH_PTP_TSPCTLR_TSPINI_POS (2U) +#define ETH_PTP_TSPCTLR_TSPINI (0x00000004UL) +#define ETH_PTP_TSPCTLR_TSPUP_POS (3U) +#define ETH_PTP_TSPCTLR_TSPUP (0x00000008UL) +#define ETH_PTP_TSPCTLR_TSPINT_POS (4U) +#define ETH_PTP_TSPCTLR_TSPINT (0x00000010UL) +#define ETH_PTP_TSPCTLR_TSPADUP_POS (5U) +#define ETH_PTP_TSPCTLR_TSPADUP (0x00000020UL) +#define ETH_PTP_TSPCTLR_TSPEALL_POS (8U) +#define ETH_PTP_TSPCTLR_TSPEALL (0x00000100UL) +#define ETH_PTP_TSPCTLR_TSPSSR_POS (9U) +#define ETH_PTP_TSPCTLR_TSPSSR (0x00000200UL) +#define ETH_PTP_TSPCTLR_TSPVER_POS (10U) +#define ETH_PTP_TSPCTLR_TSPVER (0x00000400UL) +#define ETH_PTP_TSPCTLR_TSPOVETH_POS (11U) +#define ETH_PTP_TSPCTLR_TSPOVETH (0x00000800UL) +#define ETH_PTP_TSPCTLR_TSPOVIPV6_POS (12U) +#define ETH_PTP_TSPCTLR_TSPOVIPV6 (0x00001000UL) +#define ETH_PTP_TSPCTLR_TSPOVIPV4_POS (13U) +#define ETH_PTP_TSPCTLR_TSPOVIPV4 (0x00002000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_POS (14U) +#define ETH_PTP_TSPCTLR_TSPMTSEL (0x0003C000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_0 (0x00004000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_1 (0x00008000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_2 (0x00010000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_3 (0x00020000UL) +#define ETH_PTP_TSPCTLR_TSPADF_POS (18U) +#define ETH_PTP_TSPCTLR_TSPADF (0x00040000UL) + +/* Bit definition for ETH_PTP_TSPNSAR register */ +#define ETH_PTP_TSPNSAR_TSPNSEADD (0x000000FFUL) + +/* Bit definition for ETH_PTP_TMSSECR register */ +#define ETH_PTP_TMSSECR_TSPSYSSEC (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMSNSER register */ +#define ETH_PTP_TMSNSER_TSPSYSNSEC (0x7FFFFFFFUL) + +/* Bit definition for ETH_PTP_TMUSECR register */ +#define ETH_PTP_TMUSECR_TSPUPSEC (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMUNSER register */ +#define ETH_PTP_TMUNSER_TSPUPNSEC_POS (0U) +#define ETH_PTP_TMUNSER_TSPUPNSEC (0x7FFFFFFFUL) +#define ETH_PTP_TMUNSER_TSPUPNS_POS (31U) +#define ETH_PTP_TMUNSER_TSPUPNS (0x80000000UL) + +/* Bit definition for ETH_PTP_TSPADDR register */ +#define ETH_PTP_TSPADDR_TSPADD (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTSECR0 register */ +#define ETH_PTP_TMTSECR0_TSPTAGSEC0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTNSER0 register */ +#define ETH_PTP_TMTNSER0_TSPTAGNSEC0 (0x7FFFFFFFUL) + +/* Bit definition for ETH_PTP_TSPSTSR register */ +#define ETH_PTP_TSPSTSR_TSOVF_POS (0U) +#define ETH_PTP_TSPSTSR_TSOVF (0x00000001UL) +#define ETH_PTP_TSPSTSR_TSTAR0_POS (1U) +#define ETH_PTP_TSPSTSR_TSTAR0 (0x00000002UL) +#define ETH_PTP_TSPSTSR_TSERR0_POS (3U) +#define ETH_PTP_TSPSTSR_TSERR0 (0x00000008UL) +#define ETH_PTP_TSPSTSR_TSTAR1_POS (4U) +#define ETH_PTP_TSPSTSR_TSTAR1 (0x00000010UL) +#define ETH_PTP_TSPSTSR_TSERR1_POS (5U) +#define ETH_PTP_TSPSTSR_TSERR1 (0x00000020UL) + +/* Bit definition for ETH_PTP_PPSCTLR register */ +#define ETH_PTP_PPSCTLR_PPSFRE0_POS (0U) +#define ETH_PTP_PPSCTLR_PPSFRE0 (0x0000000FUL) +#define ETH_PTP_PPSCTLR_PPSFRE0_0 (0x00000001UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_1 (0x00000002UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_2 (0x00000004UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_3 (0x00000008UL) +#define ETH_PTP_PPSCTLR_PPSOMD_POS (4U) +#define ETH_PTP_PPSCTLR_PPSOMD (0x00000010UL) +#define ETH_PTP_PPSCTLR_TT0SEL_POS (5U) +#define ETH_PTP_PPSCTLR_TT0SEL (0x00000060UL) +#define ETH_PTP_PPSCTLR_TT0SEL_0 (0x00000020UL) +#define ETH_PTP_PPSCTLR_TT0SEL_1 (0x00000040UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_POS (8U) +#define ETH_PTP_PPSCTLR_PPSFRE1 (0x00000700UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_0 (0x00000100UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_1 (0x00000200UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_2 (0x00000400UL) +#define ETH_PTP_PPSCTLR_TT1SEL_POS (13U) +#define ETH_PTP_PPSCTLR_TT1SEL (0x00006000UL) +#define ETH_PTP_PPSCTLR_TT1SEL_0 (0x00002000UL) +#define ETH_PTP_PPSCTLR_TT1SEL_1 (0x00004000UL) + +/* Bit definition for ETH_PTP_TMTSECR1 register */ +#define ETH_PTP_TMTSECR1_TSPTAGSEC1 (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTNSER1 register */ +#define ETH_PTP_TMTNSER1_TSPTAGNSEC1 (0x7FFFFFFFUL) + +/* Bit definition for ETH_DMA_BUSMODR register */ +#define ETH_DMA_BUSMODR_SWR_POS (0U) +#define ETH_DMA_BUSMODR_SWR (0x00000001UL) +#define ETH_DMA_BUSMODR_DMAA_POS (1U) +#define ETH_DMA_BUSMODR_DMAA (0x00000002UL) +#define ETH_DMA_BUSMODR_DSL_POS (2U) +#define ETH_DMA_BUSMODR_DSL (0x0000007CUL) +#define ETH_DMA_BUSMODR_DSL_0 (0x00000004UL) +#define ETH_DMA_BUSMODR_DSL_1 (0x00000008UL) +#define ETH_DMA_BUSMODR_DSL_2 (0x00000010UL) +#define ETH_DMA_BUSMODR_DSL_3 (0x00000020UL) +#define ETH_DMA_BUSMODR_DSL_4 (0x00000040UL) +#define ETH_DMA_BUSMODR_DSEN_POS (7U) +#define ETH_DMA_BUSMODR_DSEN (0x00000080UL) +#define ETH_DMA_BUSMODR_TPBL_POS (8U) +#define ETH_DMA_BUSMODR_TPBL (0x00003F00UL) +#define ETH_DMA_BUSMODR_TPBL_0 (0x00000100UL) +#define ETH_DMA_BUSMODR_TPBL_1 (0x00000200UL) +#define ETH_DMA_BUSMODR_TPBL_2 (0x00000400UL) +#define ETH_DMA_BUSMODR_TPBL_3 (0x00000800UL) +#define ETH_DMA_BUSMODR_TPBL_4 (0x00001000UL) +#define ETH_DMA_BUSMODR_TPBL_5 (0x00002000UL) +#define ETH_DMA_BUSMODR_PRAT_POS (14U) +#define ETH_DMA_BUSMODR_PRAT (0x0000C000UL) +#define ETH_DMA_BUSMODR_PRAT_0 (0x00004000UL) +#define ETH_DMA_BUSMODR_PRAT_1 (0x00008000UL) +#define ETH_DMA_BUSMODR_FBST_POS (16U) +#define ETH_DMA_BUSMODR_FBST (0x00010000UL) +#define ETH_DMA_BUSMODR_RPBL_POS (17U) +#define ETH_DMA_BUSMODR_RPBL (0x007E0000UL) +#define ETH_DMA_BUSMODR_RPBL_0 (0x00020000UL) +#define ETH_DMA_BUSMODR_RPBL_1 (0x00040000UL) +#define ETH_DMA_BUSMODR_RPBL_2 (0x00080000UL) +#define ETH_DMA_BUSMODR_RPBL_3 (0x00100000UL) +#define ETH_DMA_BUSMODR_RPBL_4 (0x00200000UL) +#define ETH_DMA_BUSMODR_RPBL_5 (0x00400000UL) +#define ETH_DMA_BUSMODR_SPBL_POS (23U) +#define ETH_DMA_BUSMODR_SPBL (0x00800000UL) +#define ETH_DMA_BUSMODR_M8PBL_POS (24U) +#define ETH_DMA_BUSMODR_M8PBL (0x01000000UL) +#define ETH_DMA_BUSMODR_AAL_POS (25U) +#define ETH_DMA_BUSMODR_AAL (0x02000000UL) +#define ETH_DMA_BUSMODR_MBST_POS (26U) +#define ETH_DMA_BUSMODR_MBST (0x04000000UL) +#define ETH_DMA_BUSMODR_TXPR_POS (27U) +#define ETH_DMA_BUSMODR_TXPR (0x08000000UL) + +/* Bit definition for ETH_DMA_TXPOLLR register */ +#define ETH_DMA_TXPOLLR_TXPOLL (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_RXPOLLR register */ +#define ETH_DMA_RXPOLLR_RXPOLL (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_RXDLADR register */ +#define ETH_DMA_RXDLADR_RXDLAD (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_TXDLADR register */ +#define ETH_DMA_TXDLADR_TXDLAD (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_DMASTSR register */ +#define ETH_DMA_DMASTSR_TIS_POS (0U) +#define ETH_DMA_DMASTSR_TIS (0x00000001UL) +#define ETH_DMA_DMASTSR_TSS_POS (1U) +#define ETH_DMA_DMASTSR_TSS (0x00000002UL) +#define ETH_DMA_DMASTSR_TUS_POS (2U) +#define ETH_DMA_DMASTSR_TUS (0x00000004UL) +#define ETH_DMA_DMASTSR_TJS_POS (3U) +#define ETH_DMA_DMASTSR_TJS (0x00000008UL) +#define ETH_DMA_DMASTSR_OVS_POS (4U) +#define ETH_DMA_DMASTSR_OVS (0x00000010UL) +#define ETH_DMA_DMASTSR_UNS_POS (5U) +#define ETH_DMA_DMASTSR_UNS (0x00000020UL) +#define ETH_DMA_DMASTSR_RIS_POS (6U) +#define ETH_DMA_DMASTSR_RIS (0x00000040UL) +#define ETH_DMA_DMASTSR_RUS_POS (7U) +#define ETH_DMA_DMASTSR_RUS (0x00000080UL) +#define ETH_DMA_DMASTSR_RSS_POS (8U) +#define ETH_DMA_DMASTSR_RSS (0x00000100UL) +#define ETH_DMA_DMASTSR_RWS_POS (9U) +#define ETH_DMA_DMASTSR_RWS (0x00000200UL) +#define ETH_DMA_DMASTSR_ETS_POS (10U) +#define ETH_DMA_DMASTSR_ETS (0x00000400UL) +#define ETH_DMA_DMASTSR_FBS_POS (13U) +#define ETH_DMA_DMASTSR_FBS (0x00002000UL) +#define ETH_DMA_DMASTSR_ERS_POS (14U) +#define ETH_DMA_DMASTSR_ERS (0x00004000UL) +#define ETH_DMA_DMASTSR_AIS_POS (15U) +#define ETH_DMA_DMASTSR_AIS (0x00008000UL) +#define ETH_DMA_DMASTSR_NIS_POS (16U) +#define ETH_DMA_DMASTSR_NIS (0x00010000UL) +#define ETH_DMA_DMASTSR_RSTS_POS (17U) +#define ETH_DMA_DMASTSR_RSTS (0x000E0000UL) +#define ETH_DMA_DMASTSR_RSTS_0 (0x00020000UL) +#define ETH_DMA_DMASTSR_RSTS_1 (0x00040000UL) +#define ETH_DMA_DMASTSR_RSTS_2 (0x00080000UL) +#define ETH_DMA_DMASTSR_TSTS_POS (20U) +#define ETH_DMA_DMASTSR_TSTS (0x00700000UL) +#define ETH_DMA_DMASTSR_TSTS_0 (0x00100000UL) +#define ETH_DMA_DMASTSR_TSTS_1 (0x00200000UL) +#define ETH_DMA_DMASTSR_TSTS_2 (0x00400000UL) +#define ETH_DMA_DMASTSR_EBUS_POS (23U) +#define ETH_DMA_DMASTSR_EBUS (0x03800000UL) +#define ETH_DMA_DMASTSR_EBUS_0 (0x00800000UL) +#define ETH_DMA_DMASTSR_EBUS_1 (0x01000000UL) +#define ETH_DMA_DMASTSR_EBUS_2 (0x02000000UL) +#define ETH_DMA_DMASTSR_MMCS_POS (27U) +#define ETH_DMA_DMASTSR_MMCS (0x08000000UL) +#define ETH_DMA_DMASTSR_PMTS_POS (28U) +#define ETH_DMA_DMASTSR_PMTS (0x10000000UL) +#define ETH_DMA_DMASTSR_PTPS_POS (29U) +#define ETH_DMA_DMASTSR_PTPS (0x20000000UL) + +/* Bit definition for ETH_DMA_OPRMODR register */ +#define ETH_DMA_OPRMODR_STR_POS (1U) +#define ETH_DMA_OPRMODR_STR (0x00000002UL) +#define ETH_DMA_OPRMODR_OSF_POS (2U) +#define ETH_DMA_OPRMODR_OSF (0x00000004UL) +#define ETH_DMA_OPRMODR_RTC_POS (3U) +#define ETH_DMA_OPRMODR_RTC (0x00000018UL) +#define ETH_DMA_OPRMODR_RTC_0 (0x00000008UL) +#define ETH_DMA_OPRMODR_RTC_1 (0x00000010UL) +#define ETH_DMA_OPRMODR_DGF_POS (5U) +#define ETH_DMA_OPRMODR_DGF (0x00000020UL) +#define ETH_DMA_OPRMODR_FUF_POS (6U) +#define ETH_DMA_OPRMODR_FUF (0x00000040UL) +#define ETH_DMA_OPRMODR_FEF_POS (7U) +#define ETH_DMA_OPRMODR_FEF (0x00000080UL) +#define ETH_DMA_OPRMODR_STT_POS (13U) +#define ETH_DMA_OPRMODR_STT (0x00002000UL) +#define ETH_DMA_OPRMODR_TTC_POS (14U) +#define ETH_DMA_OPRMODR_TTC (0x0001C000UL) +#define ETH_DMA_OPRMODR_TTC_0 (0x00004000UL) +#define ETH_DMA_OPRMODR_TTC_1 (0x00008000UL) +#define ETH_DMA_OPRMODR_TTC_2 (0x00010000UL) +#define ETH_DMA_OPRMODR_FTF_POS (20U) +#define ETH_DMA_OPRMODR_FTF (0x00100000UL) +#define ETH_DMA_OPRMODR_TSF_POS (21U) +#define ETH_DMA_OPRMODR_TSF (0x00200000UL) +#define ETH_DMA_OPRMODR_DFRF_POS (24U) +#define ETH_DMA_OPRMODR_DFRF (0x01000000UL) +#define ETH_DMA_OPRMODR_RSF_POS (25U) +#define ETH_DMA_OPRMODR_RSF (0x02000000UL) +#define ETH_DMA_OPRMODR_DTCOE_POS (26U) +#define ETH_DMA_OPRMODR_DTCOE (0x04000000UL) + +/* Bit definition for ETH_DMA_INTENAR register */ +#define ETH_DMA_INTENAR_TIE_POS (0U) +#define ETH_DMA_INTENAR_TIE (0x00000001UL) +#define ETH_DMA_INTENAR_TSE_POS (1U) +#define ETH_DMA_INTENAR_TSE (0x00000002UL) +#define ETH_DMA_INTENAR_TUE_POS (2U) +#define ETH_DMA_INTENAR_TUE (0x00000004UL) +#define ETH_DMA_INTENAR_TJE_POS (3U) +#define ETH_DMA_INTENAR_TJE (0x00000008UL) +#define ETH_DMA_INTENAR_OVE_POS (4U) +#define ETH_DMA_INTENAR_OVE (0x00000010UL) +#define ETH_DMA_INTENAR_UNE_POS (5U) +#define ETH_DMA_INTENAR_UNE (0x00000020UL) +#define ETH_DMA_INTENAR_RIE_POS (6U) +#define ETH_DMA_INTENAR_RIE (0x00000040UL) +#define ETH_DMA_INTENAR_RUE_POS (7U) +#define ETH_DMA_INTENAR_RUE (0x00000080UL) +#define ETH_DMA_INTENAR_RSE_POS (8U) +#define ETH_DMA_INTENAR_RSE (0x00000100UL) +#define ETH_DMA_INTENAR_RWE_POS (9U) +#define ETH_DMA_INTENAR_RWE (0x00000200UL) +#define ETH_DMA_INTENAR_ETE_POS (10U) +#define ETH_DMA_INTENAR_ETE (0x00000400UL) +#define ETH_DMA_INTENAR_FBE_POS (13U) +#define ETH_DMA_INTENAR_FBE (0x00002000UL) +#define ETH_DMA_INTENAR_ERE_POS (14U) +#define ETH_DMA_INTENAR_ERE (0x00004000UL) +#define ETH_DMA_INTENAR_AIE_POS (15U) +#define ETH_DMA_INTENAR_AIE (0x00008000UL) +#define ETH_DMA_INTENAR_NIE_POS (16U) +#define ETH_DMA_INTENAR_NIE (0x00010000UL) + +/* Bit definition for ETH_DMA_RFRCNTR register */ +#define ETH_DMA_RFRCNTR_UNACNT_POS (0U) +#define ETH_DMA_RFRCNTR_UNACNT (0x0000FFFFUL) +#define ETH_DMA_RFRCNTR_UNAOVF_POS (16U) +#define ETH_DMA_RFRCNTR_UNAOVF (0x00010000UL) +#define ETH_DMA_RFRCNTR_OVFCNT_POS (17U) +#define ETH_DMA_RFRCNTR_OVFCNT (0x0FFE0000UL) +#define ETH_DMA_RFRCNTR_OVFOVF_POS (28U) +#define ETH_DMA_RFRCNTR_OVFOVF (0x10000000UL) + +/* Bit definition for ETH_DMA_REVWDTR register */ +#define ETH_DMA_REVWDTR_RIWT (0x000000FFUL) + +/* Bit definition for ETH_DMA_CHTXDER register */ +#define ETH_DMA_CHTXDER_CHTXDE (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHRXDER register */ +#define ETH_DMA_CHRXDER_CHRXDE (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHTXBFR register */ +#define ETH_DMA_CHTXBFR_CHTXBF (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHRXBFR register */ +#define ETH_DMA_CHRXBFR_CHRXBF (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral FMAC +*******************************************************************************/ +/* Bit definition for FMAC_ENR register */ +#define FMAC_ENR_FMACEN (0x00000001UL) + +/* Bit definition for FMAC_CTR register */ +#define FMAC_CTR_STAGE_NUM_POS (0U) +#define FMAC_CTR_STAGE_NUM (0x0000001FUL) +#define FMAC_CTR_SHIFT_POS (8U) +#define FMAC_CTR_SHIFT (0x00001F00UL) + +/* Bit definition for FMAC_IER register */ +#define FMAC_IER_INTEN (0x00000001UL) + +/* Bit definition for FMAC_DTR register */ +#define FMAC_DTR_DIN (0x0000FFFFUL) + +/* Bit definition for FMAC_RTR0 register */ +#define FMAC_RTR0 (0xFFFFFFFFUL) + +/* Bit definition for FMAC_RTR1 register */ +#define FMAC_RTR1 (0xFFFFFFFFUL) + +/* Bit definition for FMAC_STR register */ +#define FMAC_STR_READY_POS (31U) +#define FMAC_STR_READY (0x80000000UL) + +/* Bit definition for FMAC_COR0 register */ +#define FMAC_COR0_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR1 register */ +#define FMAC_COR1_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR2 register */ +#define FMAC_COR2_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR3 register */ +#define FMAC_COR3_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR4 register */ +#define FMAC_COR4_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR5 register */ +#define FMAC_COR5_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR6 register */ +#define FMAC_COR6_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR7 register */ +#define FMAC_COR7_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR8 register */ +#define FMAC_COR8_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR9 register */ +#define FMAC_COR9_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR10 register */ +#define FMAC_COR10_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR11 register */ +#define FMAC_COR11_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR12 register */ +#define FMAC_COR12_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR13 register */ +#define FMAC_COR13_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR14 register */ +#define FMAC_COR14_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR15 register */ +#define FMAC_COR15_CIN (0x0000FFFFUL) + +/* Bit definition for FMAC_COR16 register */ +#define FMAC_COR16_CIN (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDR register */ +#define GPIO_PIDR_PIN00_POS (0U) +#define GPIO_PIDR_PIN00 (0x0001U) +#define GPIO_PIDR_PIN01_POS (1U) +#define GPIO_PIDR_PIN01 (0x0002U) +#define GPIO_PIDR_PIN02_POS (2U) +#define GPIO_PIDR_PIN02 (0x0004U) +#define GPIO_PIDR_PIN03_POS (3U) +#define GPIO_PIDR_PIN03 (0x0008U) +#define GPIO_PIDR_PIN04_POS (4U) +#define GPIO_PIDR_PIN04 (0x0010U) +#define GPIO_PIDR_PIN05_POS (5U) +#define GPIO_PIDR_PIN05 (0x0020U) +#define GPIO_PIDR_PIN06_POS (6U) +#define GPIO_PIDR_PIN06 (0x0040U) +#define GPIO_PIDR_PIN07_POS (7U) +#define GPIO_PIDR_PIN07 (0x0080U) +#define GPIO_PIDR_PIN08_POS (8U) +#define GPIO_PIDR_PIN08 (0x0100U) +#define GPIO_PIDR_PIN09_POS (9U) +#define GPIO_PIDR_PIN09 (0x0200U) +#define GPIO_PIDR_PIN10_POS (10U) +#define GPIO_PIDR_PIN10 (0x0400U) +#define GPIO_PIDR_PIN11_POS (11U) +#define GPIO_PIDR_PIN11 (0x0800U) +#define GPIO_PIDR_PIN12_POS (12U) +#define GPIO_PIDR_PIN12 (0x1000U) +#define GPIO_PIDR_PIN13_POS (13U) +#define GPIO_PIDR_PIN13 (0x2000U) +#define GPIO_PIDR_PIN14_POS (14U) +#define GPIO_PIDR_PIN14 (0x4000U) +#define GPIO_PIDR_PIN15_POS (15U) +#define GPIO_PIDR_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODR register */ +#define GPIO_PODR_POUT00_POS (0U) +#define GPIO_PODR_POUT00 (0x0001U) +#define GPIO_PODR_POUT01_POS (1U) +#define GPIO_PODR_POUT01 (0x0002U) +#define GPIO_PODR_POUT02_POS (2U) +#define GPIO_PODR_POUT02 (0x0004U) +#define GPIO_PODR_POUT03_POS (3U) +#define GPIO_PODR_POUT03 (0x0008U) +#define GPIO_PODR_POUT04_POS (4U) +#define GPIO_PODR_POUT04 (0x0010U) +#define GPIO_PODR_POUT05_POS (5U) +#define GPIO_PODR_POUT05 (0x0020U) +#define GPIO_PODR_POUT06_POS (6U) +#define GPIO_PODR_POUT06 (0x0040U) +#define GPIO_PODR_POUT07_POS (7U) +#define GPIO_PODR_POUT07 (0x0080U) +#define GPIO_PODR_POUT08_POS (8U) +#define GPIO_PODR_POUT08 (0x0100U) +#define GPIO_PODR_POUT09_POS (9U) +#define GPIO_PODR_POUT09 (0x0200U) +#define GPIO_PODR_POUT10_POS (10U) +#define GPIO_PODR_POUT10 (0x0400U) +#define GPIO_PODR_POUT11_POS (11U) +#define GPIO_PODR_POUT11 (0x0800U) +#define GPIO_PODR_POUT12_POS (12U) +#define GPIO_PODR_POUT12 (0x1000U) +#define GPIO_PODR_POUT13_POS (13U) +#define GPIO_PODR_POUT13 (0x2000U) +#define GPIO_PODR_POUT14_POS (14U) +#define GPIO_PODR_POUT14 (0x4000U) +#define GPIO_PODR_POUT15_POS (15U) +#define GPIO_PODR_POUT15 (0x8000U) + +/* Bit definition for GPIO_POER register */ +#define GPIO_POER_POUTE00_POS (0U) +#define GPIO_POER_POUTE00 (0x0001U) +#define GPIO_POER_POUTE01_POS (1U) +#define GPIO_POER_POUTE01 (0x0002U) +#define GPIO_POER_POUTE02_POS (2U) +#define GPIO_POER_POUTE02 (0x0004U) +#define GPIO_POER_POUTE03_POS (3U) +#define GPIO_POER_POUTE03 (0x0008U) +#define GPIO_POER_POUTE04_POS (4U) +#define GPIO_POER_POUTE04 (0x0010U) +#define GPIO_POER_POUTE05_POS (5U) +#define GPIO_POER_POUTE05 (0x0020U) +#define GPIO_POER_POUTE06_POS (6U) +#define GPIO_POER_POUTE06 (0x0040U) +#define GPIO_POER_POUTE07_POS (7U) +#define GPIO_POER_POUTE07 (0x0080U) +#define GPIO_POER_POUTE08_POS (8U) +#define GPIO_POER_POUTE08 (0x0100U) +#define GPIO_POER_POUTE09_POS (9U) +#define GPIO_POER_POUTE09 (0x0200U) +#define GPIO_POER_POUTE10_POS (10U) +#define GPIO_POER_POUTE10 (0x0400U) +#define GPIO_POER_POUTE11_POS (11U) +#define GPIO_POER_POUTE11 (0x0800U) +#define GPIO_POER_POUTE12_POS (12U) +#define GPIO_POER_POUTE12 (0x1000U) +#define GPIO_POER_POUTE13_POS (13U) +#define GPIO_POER_POUTE13 (0x2000U) +#define GPIO_POER_POUTE14_POS (14U) +#define GPIO_POER_POUTE14 (0x4000U) +#define GPIO_POER_POUTE15_POS (15U) +#define GPIO_POER_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSR register */ +#define GPIO_POSR_POS00_POS (0U) +#define GPIO_POSR_POS00 (0x0001U) +#define GPIO_POSR_POS01_POS (1U) +#define GPIO_POSR_POS01 (0x0002U) +#define GPIO_POSR_POS02_POS (2U) +#define GPIO_POSR_POS02 (0x0004U) +#define GPIO_POSR_POS03_POS (3U) +#define GPIO_POSR_POS03 (0x0008U) +#define GPIO_POSR_POS04_POS (4U) +#define GPIO_POSR_POS04 (0x0010U) +#define GPIO_POSR_POS05_POS (5U) +#define GPIO_POSR_POS05 (0x0020U) +#define GPIO_POSR_POS06_POS (6U) +#define GPIO_POSR_POS06 (0x0040U) +#define GPIO_POSR_POS07_POS (7U) +#define GPIO_POSR_POS07 (0x0080U) +#define GPIO_POSR_POS08_POS (8U) +#define GPIO_POSR_POS08 (0x0100U) +#define GPIO_POSR_POS09_POS (9U) +#define GPIO_POSR_POS09 (0x0200U) +#define GPIO_POSR_POS10_POS (10U) +#define GPIO_POSR_POS10 (0x0400U) +#define GPIO_POSR_POS11_POS (11U) +#define GPIO_POSR_POS11 (0x0800U) +#define GPIO_POSR_POS12_POS (12U) +#define GPIO_POSR_POS12 (0x1000U) +#define GPIO_POSR_POS13_POS (13U) +#define GPIO_POSR_POS13 (0x2000U) +#define GPIO_POSR_POS14_POS (14U) +#define GPIO_POSR_POS14 (0x4000U) +#define GPIO_POSR_POS15_POS (15U) +#define GPIO_POSR_POS15 (0x8000U) + +/* Bit definition for GPIO_PORR register */ +#define GPIO_PORR_POR00_POS (0U) +#define GPIO_PORR_POR00 (0x0001U) +#define GPIO_PORR_POR01_POS (1U) +#define GPIO_PORR_POR01 (0x0002U) +#define GPIO_PORR_POR02_POS (2U) +#define GPIO_PORR_POR02 (0x0004U) +#define GPIO_PORR_POR03_POS (3U) +#define GPIO_PORR_POR03 (0x0008U) +#define GPIO_PORR_POR04_POS (4U) +#define GPIO_PORR_POR04 (0x0010U) +#define GPIO_PORR_POR05_POS (5U) +#define GPIO_PORR_POR05 (0x0020U) +#define GPIO_PORR_POR06_POS (6U) +#define GPIO_PORR_POR06 (0x0040U) +#define GPIO_PORR_POR07_POS (7U) +#define GPIO_PORR_POR07 (0x0080U) +#define GPIO_PORR_POR08_POS (8U) +#define GPIO_PORR_POR08 (0x0100U) +#define GPIO_PORR_POR09_POS (9U) +#define GPIO_PORR_POR09 (0x0200U) +#define GPIO_PORR_POR10_POS (10U) +#define GPIO_PORR_POR10 (0x0400U) +#define GPIO_PORR_POR11_POS (11U) +#define GPIO_PORR_POR11 (0x0800U) +#define GPIO_PORR_POR12_POS (12U) +#define GPIO_PORR_POR12 (0x1000U) +#define GPIO_PORR_POR13_POS (13U) +#define GPIO_PORR_POR13 (0x2000U) +#define GPIO_PORR_POR14_POS (14U) +#define GPIO_PORR_POR14 (0x4000U) +#define GPIO_PORR_POR15_POS (15U) +#define GPIO_PORR_POR15 (0x8000U) + +/* Bit definition for GPIO_POTR register */ +#define GPIO_POTR_POT00_POS (0U) +#define GPIO_POTR_POT00 (0x0001U) +#define GPIO_POTR_POT01_POS (1U) +#define GPIO_POTR_POT01 (0x0002U) +#define GPIO_POTR_POT02_POS (2U) +#define GPIO_POTR_POT02 (0x0004U) +#define GPIO_POTR_POT03_POS (3U) +#define GPIO_POTR_POT03 (0x0008U) +#define GPIO_POTR_POT04_POS (4U) +#define GPIO_POTR_POT04 (0x0010U) +#define GPIO_POTR_POT05_POS (5U) +#define GPIO_POTR_POT05 (0x0020U) +#define GPIO_POTR_POT06_POS (6U) +#define GPIO_POTR_POT06 (0x0040U) +#define GPIO_POTR_POT07_POS (7U) +#define GPIO_POTR_POT07 (0x0080U) +#define GPIO_POTR_POT08_POS (8U) +#define GPIO_POTR_POT08 (0x0100U) +#define GPIO_POTR_POT09_POS (9U) +#define GPIO_POTR_POT09 (0x0200U) +#define GPIO_POTR_POT10_POS (10U) +#define GPIO_POTR_POT10 (0x0400U) +#define GPIO_POTR_POT11_POS (11U) +#define GPIO_POTR_POT11 (0x0800U) +#define GPIO_POTR_POT12_POS (12U) +#define GPIO_POTR_POT12 (0x1000U) +#define GPIO_POTR_POT13_POS (13U) +#define GPIO_POTR_POT13 (0x2000U) +#define GPIO_POTR_POT14_POS (14U) +#define GPIO_POTR_POT14 (0x4000U) +#define GPIO_POTR_POT15_POS (15U) +#define GPIO_POTR_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRI register */ +#define GPIO_PIDRI_PIN00_POS (0U) +#define GPIO_PIDRI_PIN00 (0x0001U) +#define GPIO_PIDRI_PIN01_POS (1U) +#define GPIO_PIDRI_PIN01 (0x0002U) +#define GPIO_PIDRI_PIN02_POS (2U) +#define GPIO_PIDRI_PIN02 (0x0004U) +#define GPIO_PIDRI_PIN03_POS (3U) +#define GPIO_PIDRI_PIN03 (0x0008U) +#define GPIO_PIDRI_PIN04_POS (4U) +#define GPIO_PIDRI_PIN04 (0x0010U) +#define GPIO_PIDRI_PIN05_POS (5U) +#define GPIO_PIDRI_PIN05 (0x0020U) +#define GPIO_PIDRI_PIN06_POS (6U) +#define GPIO_PIDRI_PIN06 (0x0040U) +#define GPIO_PIDRI_PIN07_POS (7U) +#define GPIO_PIDRI_PIN07 (0x0080U) +#define GPIO_PIDRI_PIN08_POS (8U) +#define GPIO_PIDRI_PIN08 (0x0100U) +#define GPIO_PIDRI_PIN09_POS (9U) +#define GPIO_PIDRI_PIN09 (0x0200U) +#define GPIO_PIDRI_PIN10_POS (10U) +#define GPIO_PIDRI_PIN10 (0x0400U) +#define GPIO_PIDRI_PIN11_POS (11U) +#define GPIO_PIDRI_PIN11 (0x0800U) +#define GPIO_PIDRI_PIN12_POS (12U) +#define GPIO_PIDRI_PIN12 (0x1000U) +#define GPIO_PIDRI_PIN13_POS (13U) +#define GPIO_PIDRI_PIN13 (0x2000U) + +/* Bit definition for GPIO_PODRI register */ +#define GPIO_PODRI_POUT00_POS (0U) +#define GPIO_PODRI_POUT00 (0x0001U) +#define GPIO_PODRI_POUT01_POS (1U) +#define GPIO_PODRI_POUT01 (0x0002U) +#define GPIO_PODRI_POUT02_POS (2U) +#define GPIO_PODRI_POUT02 (0x0004U) +#define GPIO_PODRI_POUT03_POS (3U) +#define GPIO_PODRI_POUT03 (0x0008U) +#define GPIO_PODRI_POUT04_POS (4U) +#define GPIO_PODRI_POUT04 (0x0010U) +#define GPIO_PODRI_POUT05_POS (5U) +#define GPIO_PODRI_POUT05 (0x0020U) +#define GPIO_PODRI_POUT06_POS (6U) +#define GPIO_PODRI_POUT06 (0x0040U) +#define GPIO_PODRI_POUT07_POS (7U) +#define GPIO_PODRI_POUT07 (0x0080U) +#define GPIO_PODRI_POUT08_POS (8U) +#define GPIO_PODRI_POUT08 (0x0100U) +#define GPIO_PODRI_POUT09_POS (9U) +#define GPIO_PODRI_POUT09 (0x0200U) +#define GPIO_PODRI_POUT10_POS (10U) +#define GPIO_PODRI_POUT10 (0x0400U) +#define GPIO_PODRI_POUT11_POS (11U) +#define GPIO_PODRI_POUT11 (0x0800U) +#define GPIO_PODRI_POUT12_POS (12U) +#define GPIO_PODRI_POUT12 (0x1000U) +#define GPIO_PODRI_POUT13_POS (13U) +#define GPIO_PODRI_POUT13 (0x2000U) + +/* Bit definition for GPIO_POERI register */ +#define GPIO_POERI_POUTE00_POS (0U) +#define GPIO_POERI_POUTE00 (0x0001U) +#define GPIO_POERI_POUTE01_POS (1U) +#define GPIO_POERI_POUTE01 (0x0002U) +#define GPIO_POERI_POUTE02_POS (2U) +#define GPIO_POERI_POUTE02 (0x0004U) +#define GPIO_POERI_POUTE03_POS (3U) +#define GPIO_POERI_POUTE03 (0x0008U) +#define GPIO_POERI_POUTE04_POS (4U) +#define GPIO_POERI_POUTE04 (0x0010U) +#define GPIO_POERI_POUTE05_POS (5U) +#define GPIO_POERI_POUTE05 (0x0020U) +#define GPIO_POERI_POUTE06_POS (6U) +#define GPIO_POERI_POUTE06 (0x0040U) +#define GPIO_POERI_POUTE07_POS (7U) +#define GPIO_POERI_POUTE07 (0x0080U) +#define GPIO_POERI_POUTE08_POS (8U) +#define GPIO_POERI_POUTE08 (0x0100U) +#define GPIO_POERI_POUTE09_POS (9U) +#define GPIO_POERI_POUTE09 (0x0200U) +#define GPIO_POERI_POUTE10_POS (10U) +#define GPIO_POERI_POUTE10 (0x0400U) +#define GPIO_POERI_POUTE11_POS (11U) +#define GPIO_POERI_POUTE11 (0x0800U) +#define GPIO_POERI_POUTE12_POS (12U) +#define GPIO_POERI_POUTE12 (0x1000U) +#define GPIO_POERI_POUTE13_POS (13U) +#define GPIO_POERI_POUTE13 (0x2000U) + +/* Bit definition for GPIO_POSRI register */ +#define GPIO_POSRI_POS00_POS (0U) +#define GPIO_POSRI_POS00 (0x0001U) +#define GPIO_POSRI_POS01_POS (1U) +#define GPIO_POSRI_POS01 (0x0002U) +#define GPIO_POSRI_POS02_POS (2U) +#define GPIO_POSRI_POS02 (0x0004U) +#define GPIO_POSRI_POS03_POS (3U) +#define GPIO_POSRI_POS03 (0x0008U) +#define GPIO_POSRI_POS04_POS (4U) +#define GPIO_POSRI_POS04 (0x0010U) +#define GPIO_POSRI_POS05_POS (5U) +#define GPIO_POSRI_POS05 (0x0020U) +#define GPIO_POSRI_POS06_POS (6U) +#define GPIO_POSRI_POS06 (0x0040U) +#define GPIO_POSRI_POS07_POS (7U) +#define GPIO_POSRI_POS07 (0x0080U) +#define GPIO_POSRI_POS08_POS (8U) +#define GPIO_POSRI_POS08 (0x0100U) +#define GPIO_POSRI_POS09_POS (9U) +#define GPIO_POSRI_POS09 (0x0200U) +#define GPIO_POSRI_POS10_POS (10U) +#define GPIO_POSRI_POS10 (0x0400U) +#define GPIO_POSRI_POS11_POS (11U) +#define GPIO_POSRI_POS11 (0x0800U) +#define GPIO_POSRI_POS12_POS (12U) +#define GPIO_POSRI_POS12 (0x1000U) +#define GPIO_POSRI_POS13_POS (13U) +#define GPIO_POSRI_POS13 (0x2000U) + +/* Bit definition for GPIO_PORRI register */ +#define GPIO_PORRI_POR00_POS (0U) +#define GPIO_PORRI_POR00 (0x0001U) +#define GPIO_PORRI_POR01_POS (1U) +#define GPIO_PORRI_POR01 (0x0002U) +#define GPIO_PORRI_POR02_POS (2U) +#define GPIO_PORRI_POR02 (0x0004U) +#define GPIO_PORRI_POR03_POS (3U) +#define GPIO_PORRI_POR03 (0x0008U) +#define GPIO_PORRI_POR04_POS (4U) +#define GPIO_PORRI_POR04 (0x0010U) +#define GPIO_PORRI_POR05_POS (5U) +#define GPIO_PORRI_POR05 (0x0020U) +#define GPIO_PORRI_POR06_POS (6U) +#define GPIO_PORRI_POR06 (0x0040U) +#define GPIO_PORRI_POR07_POS (7U) +#define GPIO_PORRI_POR07 (0x0080U) +#define GPIO_PORRI_POR08_POS (8U) +#define GPIO_PORRI_POR08 (0x0100U) +#define GPIO_PORRI_POR09_POS (9U) +#define GPIO_PORRI_POR09 (0x0200U) +#define GPIO_PORRI_POR10_POS (10U) +#define GPIO_PORRI_POR10 (0x0400U) +#define GPIO_PORRI_POR11_POS (11U) +#define GPIO_PORRI_POR11 (0x0800U) +#define GPIO_PORRI_POR12_POS (12U) +#define GPIO_PORRI_POR12 (0x1000U) +#define GPIO_PORRI_POR13_POS (13U) +#define GPIO_PORRI_POR13 (0x2000U) + +/* Bit definition for GPIO_POTRI register */ +#define GPIO_POTRI_POT00_POS (0U) +#define GPIO_POTRI_POT00 (0x0001U) +#define GPIO_POTRI_POT01_POS (1U) +#define GPIO_POTRI_POT01 (0x0002U) +#define GPIO_POTRI_POT02_POS (2U) +#define GPIO_POTRI_POT02 (0x0004U) +#define GPIO_POTRI_POT03_POS (3U) +#define GPIO_POTRI_POT03 (0x0008U) +#define GPIO_POTRI_POT04_POS (4U) +#define GPIO_POTRI_POT04 (0x0010U) +#define GPIO_POTRI_POT05_POS (5U) +#define GPIO_POTRI_POT05 (0x0020U) +#define GPIO_POTRI_POT06_POS (6U) +#define GPIO_POTRI_POT06 (0x0040U) +#define GPIO_POTRI_POT07_POS (7U) +#define GPIO_POTRI_POT07 (0x0080U) +#define GPIO_POTRI_POT08_POS (8U) +#define GPIO_POTRI_POT08 (0x0100U) +#define GPIO_POTRI_POT09_POS (9U) +#define GPIO_POTRI_POT09 (0x0200U) +#define GPIO_POTRI_POT10_POS (10U) +#define GPIO_POTRI_POT10 (0x0400U) +#define GPIO_POTRI_POT11_POS (11U) +#define GPIO_POTRI_POT11 (0x0800U) +#define GPIO_POTRI_POT12_POS (12U) +#define GPIO_POTRI_POT12 (0x1000U) +#define GPIO_POTRI_POT13_POS (13U) +#define GPIO_POTRI_POT13 (0x2000U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) +#define GPIO_PSPCR_SPFE_0 (0x0001U) +#define GPIO_PSPCR_SPFE_1 (0x0002U) +#define GPIO_PSPCR_SPFE_2 (0x0004U) +#define GPIO_PSPCR_SPFE_3 (0x0008U) +#define GPIO_PSPCR_SPFE_4 (0x0010U) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x003FU) +#define GPIO_PCCR_RDWT_POS (12U) +#define GPIO_PCCR_RDWT (0x7000U) + +/* Bit definition for GPIO_PINAER register */ +#define GPIO_PINAER_PINAE (0x01FFU) +#define GPIO_PINAER_PINAE_0 (0x0001U) +#define GPIO_PINAER_PINAE_1 (0x0002U) +#define GPIO_PINAER_PINAE_2 (0x0004U) +#define GPIO_PINAER_PINAE_3 (0x0008U) +#define GPIO_PINAER_PINAE_4 (0x0010U) +#define GPIO_PINAER_PINAE_5 (0x0020U) +#define GPIO_PINAER_PINAE_6 (0x0040U) +#define GPIO_PINAER_PINAE_7 (0x0080U) +#define GPIO_PINAER_PINAE_8 (0x0100U) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_CINSEL_POS (10U) +#define GPIO_PCR_CINSEL (0x0400U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) +#define HASH_CR_KMSG_END_POS (2U) +#define HASH_CR_KMSG_END (0x00000004UL) +#define HASH_CR_MODE_POS (4U) +#define HASH_CR_MODE (0x00000030UL) +#define HASH_CR_MODE_0 (0x00000010UL) +#define HASH_CR_MODE_1 (0x00000020UL) +#define HASH_CR_LKEY_POS (6U) +#define HASH_CR_LKEY (0x00000040UL) +#define HASH_CR_BUSY_POS (8U) +#define HASH_CR_BUSY (0x00000100UL) +#define HASH_CR_CYC_END_POS (9U) +#define HASH_CR_CYC_END (0x00000200UL) +#define HASH_CR_HMAC_END_POS (10U) +#define HASH_CR_HMAC_END (0x00000400UL) +#define HASH_CR_HCIE_POS (14U) +#define HASH_CR_HCIE (0x00004000UL) +#define HASH_CR_HEIE_POS (15U) +#define HASH_CR_HEIE (0x00008000UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral HRPWM +*******************************************************************************/ +/* Bit definition for HRPWM_CR register */ +#define HRPWM_CR_NSEL_POS (0U) +#define HRPWM_CR_NSEL (0x000000FFUL) +#define HRPWM_CR_PSEL_POS (8U) +#define HRPWM_CR_PSEL (0x0000FF00UL) +#define HRPWM_CR_NE_POS (29U) +#define HRPWM_CR_NE (0x20000000UL) +#define HRPWM_CR_PE_POS (30U) +#define HRPWM_CR_PE (0x40000000UL) +#define HRPWM_CR_EN_POS (31U) +#define HRPWM_CR_EN (0x80000000UL) + +/* Bit definition for HRPWM_CALCR register */ +#define HRPWM_CALCR_CALCODE_POS (0U) +#define HRPWM_CALCR_CALCODE (0x000000FFUL) +#define HRPWM_CALCR_ENDF_POS (12U) +#define HRPWM_CALCR_ENDF (0x00001000UL) +#define HRPWM_CALCR_CALEN_POS (15U) +#define HRPWM_CALCR_CALEN (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_GCEN_POS (6U) +#define I2C_CR1_GCEN (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMBHOSTIE_POS (22U) +#define I2C_CR2_SMBHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_CR4 register */ +#define I2C_CR4_BUSWAIT_POS (10U) +#define I2C_CR4_BUSWAIT (0x00000400UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x0000001FUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x00001F00UL) +#define I2C_CCR_FREQ_POS (16U) +#define I2C_CCR_FREQ (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/******************************************************************************* + Bit definition for Peripheral I2S +*******************************************************************************/ +/* Bit definition for I2S_CTRL register */ +#define I2S_CTRL_TXE_POS (0U) +#define I2S_CTRL_TXE (0x00000001UL) +#define I2S_CTRL_TXIE_POS (1U) +#define I2S_CTRL_TXIE (0x00000002UL) +#define I2S_CTRL_RXE_POS (2U) +#define I2S_CTRL_RXE (0x00000004UL) +#define I2S_CTRL_RXIE_POS (3U) +#define I2S_CTRL_RXIE (0x00000008UL) +#define I2S_CTRL_EIE_POS (4U) +#define I2S_CTRL_EIE (0x00000010UL) +#define I2S_CTRL_WMS_POS (5U) +#define I2S_CTRL_WMS (0x00000020UL) +#define I2S_CTRL_ODD_POS (6U) +#define I2S_CTRL_ODD (0x00000040UL) +#define I2S_CTRL_MCKOE_POS (7U) +#define I2S_CTRL_MCKOE (0x00000080UL) +#define I2S_CTRL_TXBIRQWL_POS (8U) +#define I2S_CTRL_TXBIRQWL (0x00000700UL) +#define I2S_CTRL_TXBIRQWL_0 (0x00000100UL) +#define I2S_CTRL_TXBIRQWL_1 (0x00000200UL) +#define I2S_CTRL_TXBIRQWL_2 (0x00000400UL) +#define I2S_CTRL_RXBIRQWL_POS (12U) +#define I2S_CTRL_RXBIRQWL (0x00007000UL) +#define I2S_CTRL_RXBIRQWL_0 (0x00001000UL) +#define I2S_CTRL_RXBIRQWL_1 (0x00002000UL) +#define I2S_CTRL_RXBIRQWL_2 (0x00004000UL) +#define I2S_CTRL_FIFOR_POS (16U) +#define I2S_CTRL_FIFOR (0x00010000UL) +#define I2S_CTRL_CODECRC_POS (17U) +#define I2S_CTRL_CODECRC (0x00020000UL) +#define I2S_CTRL_I2SPLLSEL_POS (18U) +#define I2S_CTRL_I2SPLLSEL (0x00040000UL) +#define I2S_CTRL_SDOE_POS (19U) +#define I2S_CTRL_SDOE (0x00080000UL) +#define I2S_CTRL_LRCKOE_POS (20U) +#define I2S_CTRL_LRCKOE (0x00100000UL) +#define I2S_CTRL_CKOE_POS (21U) +#define I2S_CTRL_CKOE (0x00200000UL) +#define I2S_CTRL_DUPLEX_POS (22U) +#define I2S_CTRL_DUPLEX (0x00400000UL) +#define I2S_CTRL_CLKSEL_POS (23U) +#define I2S_CTRL_CLKSEL (0x00800000UL) +#define I2S_CTRL_SRST_POS (24U) +#define I2S_CTRL_SRST (0x01000000UL) + +/* Bit definition for I2S_SR register */ +#define I2S_SR_TXBA_POS (0U) +#define I2S_SR_TXBA (0x00000001UL) +#define I2S_SR_RXBA_POS (1U) +#define I2S_SR_RXBA (0x00000002UL) +#define I2S_SR_TXBE_POS (2U) +#define I2S_SR_TXBE (0x00000004UL) +#define I2S_SR_TXBF_POS (3U) +#define I2S_SR_TXBF (0x00000008UL) +#define I2S_SR_RXBE_POS (4U) +#define I2S_SR_RXBE (0x00000010UL) +#define I2S_SR_RXBF_POS (5U) +#define I2S_SR_RXBF (0x00000020UL) + +/* Bit definition for I2S_ER register */ +#define I2S_ER_TXERR_POS (0U) +#define I2S_ER_TXERR (0x00000001UL) +#define I2S_ER_RXERR_POS (1U) +#define I2S_ER_RXERR (0x00000002UL) + +/* Bit definition for I2S_CFGR register */ +#define I2S_CFGR_I2SSTD_POS (0U) +#define I2S_CFGR_I2SSTD (0x00000003UL) +#define I2S_CFGR_I2SSTD_0 (0x00000001UL) +#define I2S_CFGR_I2SSTD_1 (0x00000002UL) +#define I2S_CFGR_DATLEN_POS (2U) +#define I2S_CFGR_DATLEN (0x0000000CUL) +#define I2S_CFGR_DATLEN_0 (0x00000004UL) +#define I2S_CFGR_DATLEN_1 (0x00000008UL) +#define I2S_CFGR_CHLEN_POS (4U) +#define I2S_CFGR_CHLEN (0x00000010UL) +#define I2S_CFGR_PCMSYNC_POS (5U) +#define I2S_CFGR_PCMSYNC (0x00000020UL) + +/* Bit definition for I2S_TXBUF register */ +#define I2S_TXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_RXBUF register */ +#define I2S_RXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_PR register */ +#define I2S_PR_I2SDIV (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTCKS_0 (0x00000010UL) +#define ICG_ICG0_SWDTCKS_1 (0x00000020UL) +#define ICG_ICG0_SWDTCKS_2 (0x00000040UL) +#define ICG_ICG0_SWDTCKS_3 (0x00000080UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTWDPT_0 (0x00000100UL) +#define ICG_ICG0_SWDTWDPT_1 (0x00000200UL) +#define ICG_ICG0_SWDTWDPT_2 (0x00000400UL) +#define ICG_ICG0_SWDTWDPT_3 (0x00000800UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTCKS_0 (0x00100000UL) +#define ICG_ICG0_WDTCKS_1 (0x00200000UL) +#define ICG_ICG0_WDTCKS_2 (0x00400000UL) +#define ICG_ICG0_WDTCKS_3 (0x00800000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTWDPT_0 (0x01000000UL) +#define ICG_ICG0_WDTWDPT_1 (0x02000000UL) +#define ICG_ICG0_WDTWDPT_2 (0x04000000UL) +#define ICG_ICG0_WDTWDPT_3 (0x08000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) + +/* Bit definition for ICG_ICG2 register */ +#define ICG_ICG2_BGO1M (0x00FFFFFFUL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3_DBUSPRT (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NOCCR register */ +#define INTC_NOCCR_NOCSEL_POS (12U) +#define INTC_NOCCR_NOCSEL (0x00003000UL) + +/* Bit definition for INTC_NMIENR register */ +#define INTC_NMIENR_SWDTENR_POS (1U) +#define INTC_NMIENR_SWDTENR (0x00000002UL) +#define INTC_NMIENR_PVD1ENR_POS (2U) +#define INTC_NMIENR_PVD1ENR (0x00000004UL) +#define INTC_NMIENR_PVD2ENR_POS (3U) +#define INTC_NMIENR_PVD2ENR (0x00000008UL) +#define INTC_NMIENR_XTALSTPENR_POS (5U) +#define INTC_NMIENR_XTALSTPENR (0x00000020UL) +#define INTC_NMIENR_REPENR_POS (8U) +#define INTC_NMIENR_REPENR (0x00000100UL) +#define INTC_NMIENR_RECCENR_POS (9U) +#define INTC_NMIENR_RECCENR (0x00000200UL) +#define INTC_NMIENR_BUSMENR_POS (10U) +#define INTC_NMIENR_BUSMENR (0x00000400UL) +#define INTC_NMIENR_WDTENR_POS (11U) +#define INTC_NMIENR_WDTENR (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_SWDTFR_POS (1U) +#define INTC_NMIFR_SWDTFR (0x00000002UL) +#define INTC_NMIFR_PVD1FR_POS (2U) +#define INTC_NMIFR_PVD1FR (0x00000004UL) +#define INTC_NMIFR_PVD2FR_POS (3U) +#define INTC_NMIFR_PVD2FR (0x00000008UL) +#define INTC_NMIFR_XTALSTPFR_POS (5U) +#define INTC_NMIFR_XTALSTPFR (0x00000020UL) +#define INTC_NMIFR_REPFR_POS (8U) +#define INTC_NMIFR_REPFR (0x00000100UL) +#define INTC_NMIFR_RECCFR_POS (9U) +#define INTC_NMIFR_RECCFR (0x00000200UL) +#define INTC_NMIFR_BUSMFR_POS (10U) +#define INTC_NMIFR_BUSMFR (0x00000400UL) +#define INTC_NMIFR_WDTFR_POS (11U) +#define INTC_NMIFR_WDTFR (0x00000800UL) + +/* Bit definition for INTC_NMICFR register */ +#define INTC_NMICFR_SWDTCFR_POS (1U) +#define INTC_NMICFR_SWDTCFR (0x00000002UL) +#define INTC_NMICFR_PVD1CFR_POS (2U) +#define INTC_NMICFR_PVD1CFR (0x00000004UL) +#define INTC_NMICFR_PVD2CFR_POS (3U) +#define INTC_NMICFR_PVD2CFR (0x00000008UL) +#define INTC_NMICFR_XTALSTPCFR_POS (5U) +#define INTC_NMICFR_XTALSTPCFR (0x00000020UL) +#define INTC_NMICFR_REPCFR_POS (8U) +#define INTC_NMICFR_REPCFR (0x00000100UL) +#define INTC_NMICFR_RECCCFR_POS (9U) +#define INTC_NMICFR_RECCCFR (0x00000200UL) +#define INTC_NMICFR_BUSMCFR_POS (10U) +#define INTC_NMICFR_BUSMCFR (0x00000400UL) +#define INTC_NMICFR_WDTCFR_POS (11U) +#define INTC_NMICFR_WDTCFR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) +#define INTC_EIRQCR_NOCEN_POS (15U) +#define INTC_EIRQCR_NOCEN (0x00008000UL) + +/* Bit definition for INTC_WUPEN register */ +#define INTC_WUPEN_EIRQWUEN_POS (0U) +#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL) +#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL) +#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL) +#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL) +#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL) +#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL) +#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL) +#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL) +#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL) +#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL) +#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL) +#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL) +#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL) +#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL) +#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL) +#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL) +#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL) +#define INTC_WUPEN_SWDTWUEN_POS (16U) +#define INTC_WUPEN_SWDTWUEN (0x00010000UL) +#define INTC_WUPEN_PVD1WUEN_POS (17U) +#define INTC_WUPEN_PVD1WUEN (0x00020000UL) +#define INTC_WUPEN_PVD2WUEN_POS (18U) +#define INTC_WUPEN_PVD2WUEN (0x00040000UL) +#define INTC_WUPEN_CMPWUEN_POS (19U) +#define INTC_WUPEN_CMPWUEN (0x00080000UL) +#define INTC_WUPEN_WKTMWUEN_POS (20U) +#define INTC_WUPEN_WKTMWUEN (0x00100000UL) +#define INTC_WUPEN_RTCALMWUEN_POS (21U) +#define INTC_WUPEN_RTCALMWUEN (0x00200000UL) +#define INTC_WUPEN_RTCPRDWUEN_POS (22U) +#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL) +#define INTC_WUPEN_TMR0GCMWUEN_POS (23U) +#define INTC_WUPEN_TMR0GCMWUEN (0x00800000UL) +#define INTC_WUPEN_TMR2GCMWUEN_POS (24U) +#define INTC_WUPEN_TMR2GCMWUEN (0x01000000UL) +#define INTC_WUPEN_TMR2OVFWUEN_POS (25U) +#define INTC_WUPEN_TMR2OVFWUEN (0x02000000UL) +#define INTC_WUPEN_RXWUEN_POS (26U) +#define INTC_WUPEN_RXWUEN (0x04000000UL) +#define INTC_WUPEN_USHWUEN_POS (27U) +#define INTC_WUPEN_USHWUEN (0x08000000UL) +#define INTC_WUPEN_USFWUEN_POS (28U) +#define INTC_WUPEN_USFWUEN (0x10000000UL) +#define INTC_WUPEN_ETHWUEN_POS (29U) +#define INTC_WUPEN_ETHWUEN (0x20000000UL) + +/* Bit definition for INTC_EIRQFR register */ +#define INTC_EIRQFR_EIRQFR0_POS (0U) +#define INTC_EIRQFR_EIRQFR0 (0x00000001UL) +#define INTC_EIRQFR_EIRQFR1_POS (1U) +#define INTC_EIRQFR_EIRQFR1 (0x00000002UL) +#define INTC_EIRQFR_EIRQFR2_POS (2U) +#define INTC_EIRQFR_EIRQFR2 (0x00000004UL) +#define INTC_EIRQFR_EIRQFR3_POS (3U) +#define INTC_EIRQFR_EIRQFR3 (0x00000008UL) +#define INTC_EIRQFR_EIRQFR4_POS (4U) +#define INTC_EIRQFR_EIRQFR4 (0x00000010UL) +#define INTC_EIRQFR_EIRQFR5_POS (5U) +#define INTC_EIRQFR_EIRQFR5 (0x00000020UL) +#define INTC_EIRQFR_EIRQFR6_POS (6U) +#define INTC_EIRQFR_EIRQFR6 (0x00000040UL) +#define INTC_EIRQFR_EIRQFR7_POS (7U) +#define INTC_EIRQFR_EIRQFR7 (0x00000080UL) +#define INTC_EIRQFR_EIRQFR8_POS (8U) +#define INTC_EIRQFR_EIRQFR8 (0x00000100UL) +#define INTC_EIRQFR_EIRQFR9_POS (9U) +#define INTC_EIRQFR_EIRQFR9 (0x00000200UL) +#define INTC_EIRQFR_EIRQFR10_POS (10U) +#define INTC_EIRQFR_EIRQFR10 (0x00000400UL) +#define INTC_EIRQFR_EIRQFR11_POS (11U) +#define INTC_EIRQFR_EIRQFR11 (0x00000800UL) +#define INTC_EIRQFR_EIRQFR12_POS (12U) +#define INTC_EIRQFR_EIRQFR12 (0x00001000UL) +#define INTC_EIRQFR_EIRQFR13_POS (13U) +#define INTC_EIRQFR_EIRQFR13 (0x00002000UL) +#define INTC_EIRQFR_EIRQFR14_POS (14U) +#define INTC_EIRQFR_EIRQFR14 (0x00004000UL) +#define INTC_EIRQFR_EIRQFR15_POS (15U) +#define INTC_EIRQFR_EIRQFR15 (0x00008000UL) + +/* Bit definition for INTC_EIRQCFR register */ +#define INTC_EIRQCFR_EIRQCFR0_POS (0U) +#define INTC_EIRQCFR_EIRQCFR0 (0x00000001UL) +#define INTC_EIRQCFR_EIRQCFR1_POS (1U) +#define INTC_EIRQCFR_EIRQCFR1 (0x00000002UL) +#define INTC_EIRQCFR_EIRQCFR2_POS (2U) +#define INTC_EIRQCFR_EIRQCFR2 (0x00000004UL) +#define INTC_EIRQCFR_EIRQCFR3_POS (3U) +#define INTC_EIRQCFR_EIRQCFR3 (0x00000008UL) +#define INTC_EIRQCFR_EIRQCFR4_POS (4U) +#define INTC_EIRQCFR_EIRQCFR4 (0x00000010UL) +#define INTC_EIRQCFR_EIRQCFR5_POS (5U) +#define INTC_EIRQCFR_EIRQCFR5 (0x00000020UL) +#define INTC_EIRQCFR_EIRQCFR6_POS (6U) +#define INTC_EIRQCFR_EIRQCFR6 (0x00000040UL) +#define INTC_EIRQCFR_EIRQCFR7_POS (7U) +#define INTC_EIRQCFR_EIRQCFR7 (0x00000080UL) +#define INTC_EIRQCFR_EIRQCFR8_POS (8U) +#define INTC_EIRQCFR_EIRQCFR8 (0x00000100UL) +#define INTC_EIRQCFR_EIRQCFR9_POS (9U) +#define INTC_EIRQCFR_EIRQCFR9 (0x00000200UL) +#define INTC_EIRQCFR_EIRQCFR10_POS (10U) +#define INTC_EIRQCFR_EIRQCFR10 (0x00000400UL) +#define INTC_EIRQCFR_EIRQCFR11_POS (11U) +#define INTC_EIRQCFR_EIRQCFR11 (0x00000800UL) +#define INTC_EIRQCFR_EIRQCFR12_POS (12U) +#define INTC_EIRQCFR_EIRQCFR12 (0x00001000UL) +#define INTC_EIRQCFR_EIRQCFR13_POS (13U) +#define INTC_EIRQCFR_EIRQCFR13 (0x00002000UL) +#define INTC_EIRQCFR_EIRQCFR14_POS (14U) +#define INTC_EIRQCFR_EIRQCFR14 (0x00004000UL) +#define INTC_EIRQCFR_EIRQCFR15_POS (15U) +#define INTC_EIRQCFR_EIRQCFR15 (0x00008000UL) + +/* Bit definition for INTC_SEL register */ +#define INTC_SEL_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_VSSEL register */ +#define INTC_VSSEL_VSEL0_POS (0U) +#define INTC_VSSEL_VSEL0 (0x00000001UL) +#define INTC_VSSEL_VSEL1_POS (1U) +#define INTC_VSSEL_VSEL1 (0x00000002UL) +#define INTC_VSSEL_VSEL2_POS (2U) +#define INTC_VSSEL_VSEL2 (0x00000004UL) +#define INTC_VSSEL_VSEL3_POS (3U) +#define INTC_VSSEL_VSEL3 (0x00000008UL) +#define INTC_VSSEL_VSEL4_POS (4U) +#define INTC_VSSEL_VSEL4 (0x00000010UL) +#define INTC_VSSEL_VSEL5_POS (5U) +#define INTC_VSSEL_VSEL5 (0x00000020UL) +#define INTC_VSSEL_VSEL6_POS (6U) +#define INTC_VSSEL_VSEL6 (0x00000040UL) +#define INTC_VSSEL_VSEL7_POS (7U) +#define INTC_VSSEL_VSEL7 (0x00000080UL) +#define INTC_VSSEL_VSEL8_POS (8U) +#define INTC_VSSEL_VSEL8 (0x00000100UL) +#define INTC_VSSEL_VSEL9_POS (9U) +#define INTC_VSSEL_VSEL9 (0x00000200UL) +#define INTC_VSSEL_VSEL10_POS (10U) +#define INTC_VSSEL_VSEL10 (0x00000400UL) +#define INTC_VSSEL_VSEL11_POS (11U) +#define INTC_VSSEL_VSEL11 (0x00000800UL) +#define INTC_VSSEL_VSEL12_POS (12U) +#define INTC_VSSEL_VSEL12 (0x00001000UL) +#define INTC_VSSEL_VSEL13_POS (13U) +#define INTC_VSSEL_VSEL13 (0x00002000UL) +#define INTC_VSSEL_VSEL14_POS (14U) +#define INTC_VSSEL_VSEL14 (0x00004000UL) +#define INTC_VSSEL_VSEL15_POS (15U) +#define INTC_VSSEL_VSEL15 (0x00008000UL) +#define INTC_VSSEL_VSEL16_POS (16U) +#define INTC_VSSEL_VSEL16 (0x00010000UL) +#define INTC_VSSEL_VSEL17_POS (17U) +#define INTC_VSSEL_VSEL17 (0x00020000UL) +#define INTC_VSSEL_VSEL18_POS (18U) +#define INTC_VSSEL_VSEL18 (0x00040000UL) +#define INTC_VSSEL_VSEL19_POS (19U) +#define INTC_VSSEL_VSEL19 (0x00080000UL) +#define INTC_VSSEL_VSEL20_POS (20U) +#define INTC_VSSEL_VSEL20 (0x00100000UL) +#define INTC_VSSEL_VSEL21_POS (21U) +#define INTC_VSSEL_VSEL21 (0x00200000UL) +#define INTC_VSSEL_VSEL22_POS (22U) +#define INTC_VSSEL_VSEL22 (0x00400000UL) +#define INTC_VSSEL_VSEL23_POS (23U) +#define INTC_VSSEL_VSEL23 (0x00800000UL) +#define INTC_VSSEL_VSEL24_POS (24U) +#define INTC_VSSEL_VSEL24 (0x01000000UL) +#define INTC_VSSEL_VSEL25_POS (25U) +#define INTC_VSSEL_VSEL25 (0x02000000UL) +#define INTC_VSSEL_VSEL26_POS (26U) +#define INTC_VSSEL_VSEL26 (0x04000000UL) +#define INTC_VSSEL_VSEL27_POS (27U) +#define INTC_VSSEL_VSEL27 (0x08000000UL) +#define INTC_VSSEL_VSEL28_POS (28U) +#define INTC_VSSEL_VSEL28 (0x10000000UL) +#define INTC_VSSEL_VSEL29_POS (29U) +#define INTC_VSSEL_VSEL29 (0x20000000UL) +#define INTC_VSSEL_VSEL30_POS (30U) +#define INTC_VSSEL_VSEL30 (0x40000000UL) +#define INTC_VSSEL_VSEL31_POS (31U) +#define INTC_VSSEL_VSEL31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IER0_POS (0U) +#define INTC_IER_IER0 (0x00000001UL) +#define INTC_IER_IER1_POS (1U) +#define INTC_IER_IER1 (0x00000002UL) +#define INTC_IER_IER2_POS (2U) +#define INTC_IER_IER2 (0x00000004UL) +#define INTC_IER_IER3_POS (3U) +#define INTC_IER_IER3 (0x00000008UL) +#define INTC_IER_IER4_POS (4U) +#define INTC_IER_IER4 (0x00000010UL) +#define INTC_IER_IER5_POS (5U) +#define INTC_IER_IER5 (0x00000020UL) +#define INTC_IER_IER6_POS (6U) +#define INTC_IER_IER6 (0x00000040UL) +#define INTC_IER_IER7_POS (7U) +#define INTC_IER_IER7 (0x00000080UL) +#define INTC_IER_IER8_POS (8U) +#define INTC_IER_IER8 (0x00000100UL) +#define INTC_IER_IER9_POS (9U) +#define INTC_IER_IER9 (0x00000200UL) +#define INTC_IER_IER10_POS (10U) +#define INTC_IER_IER10 (0x00000400UL) +#define INTC_IER_IER11_POS (11U) +#define INTC_IER_IER11 (0x00000800UL) +#define INTC_IER_IER12_POS (12U) +#define INTC_IER_IER12 (0x00001000UL) +#define INTC_IER_IER13_POS (13U) +#define INTC_IER_IER13 (0x00002000UL) +#define INTC_IER_IER14_POS (14U) +#define INTC_IER_IER14 (0x00004000UL) +#define INTC_IER_IER15_POS (15U) +#define INTC_IER_IER15 (0x00008000UL) +#define INTC_IER_IER16_POS (16U) +#define INTC_IER_IER16 (0x00010000UL) +#define INTC_IER_IER17_POS (17U) +#define INTC_IER_IER17 (0x00020000UL) +#define INTC_IER_IER18_POS (18U) +#define INTC_IER_IER18 (0x00040000UL) +#define INTC_IER_IER19_POS (19U) +#define INTC_IER_IER19 (0x00080000UL) +#define INTC_IER_IER20_POS (20U) +#define INTC_IER_IER20 (0x00100000UL) +#define INTC_IER_IER21_POS (21U) +#define INTC_IER_IER21 (0x00200000UL) +#define INTC_IER_IER22_POS (22U) +#define INTC_IER_IER22 (0x00400000UL) +#define INTC_IER_IER23_POS (23U) +#define INTC_IER_IER23 (0x00800000UL) +#define INTC_IER_IER24_POS (24U) +#define INTC_IER_IER24 (0x01000000UL) +#define INTC_IER_IER25_POS (25U) +#define INTC_IER_IER25 (0x02000000UL) +#define INTC_IER_IER26_POS (26U) +#define INTC_IER_IER26 (0x04000000UL) +#define INTC_IER_IER27_POS (27U) +#define INTC_IER_IER27 (0x08000000UL) +#define INTC_IER_IER28_POS (28U) +#define INTC_IER_IER28 (0x10000000UL) +#define INTC_IER_IER29_POS (29U) +#define INTC_IER_IER29 (0x20000000UL) +#define INTC_IER_IER30_POS (30U) +#define INTC_IER_IER30 (0x40000000UL) +#define INTC_IER_IER31_POS (31U) +#define INTC_IER_IER31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYINSEL_0 (0x00000001UL) +#define KEYSCAN_SCR_KEYINSEL_1 (0x00000002UL) +#define KEYSCAN_SCR_KEYINSEL_2 (0x00000004UL) +#define KEYSCAN_SCR_KEYINSEL_3 (0x00000008UL) +#define KEYSCAN_SCR_KEYINSEL_4 (0x00000010UL) +#define KEYSCAN_SCR_KEYINSEL_5 (0x00000020UL) +#define KEYSCAN_SCR_KEYINSEL_6 (0x00000040UL) +#define KEYSCAN_SCR_KEYINSEL_7 (0x00000080UL) +#define KEYSCAN_SCR_KEYINSEL_8 (0x00000100UL) +#define KEYSCAN_SCR_KEYINSEL_9 (0x00000200UL) +#define KEYSCAN_SCR_KEYINSEL_10 (0x00000400UL) +#define KEYSCAN_SCR_KEYINSEL_11 (0x00000800UL) +#define KEYSCAN_SCR_KEYINSEL_12 (0x00001000UL) +#define KEYSCAN_SCR_KEYINSEL_13 (0x00002000UL) +#define KEYSCAN_SCR_KEYINSEL_14 (0x00004000UL) +#define KEYSCAN_SCR_KEYINSEL_15 (0x00008000UL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MAU +*******************************************************************************/ +/* Bit definition for MAU_CSR register */ +#define MAU_CSR_START_POS (0U) +#define MAU_CSR_START (0x00000001UL) +#define MAU_CSR_INTEN_POS (1U) +#define MAU_CSR_INTEN (0x00000002UL) +#define MAU_CSR_BUSY_POS (3U) +#define MAU_CSR_BUSY (0x00000008UL) +#define MAU_CSR_SHIFT_POS (8U) +#define MAU_CSR_SHIFT (0x00001F00UL) + +/* Bit definition for MAU_DTR0 register */ +#define MAU_DTR0 (0xFFFFFFFFUL) + +/* Bit definition for MAU_RTR0 register */ +#define MAU_RTR0_SQRT_DOUT (0x0001FFFFUL) + +/* Bit definition for MAU_DTR1 register */ +#define MAU_DTR1_SIN_DIN (0x00000FFFUL) + +/* Bit definition for MAU_RTR1 register */ +#define MAU_RTR1_SIN_DOUT (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGSIZE_0 (0x00000001UL) +#define MPU_RGD_MPURGSIZE_1 (0x00000002UL) +#define MPU_RGD_MPURGSIZE_2 (0x00000004UL) +#define MPU_RGD_MPURGSIZE_3 (0x00000008UL) +#define MPU_RGD_MPURGSIZE_4 (0x00000010UL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU1EAF_POS (0U) +#define MPU_SR_SMPU1EAF (0x00000001UL) +#define MPU_SR_SMPU2EAF_POS (1U) +#define MPU_SR_SMPU2EAF (0x00000002UL) +#define MPU_SR_FMPUEAF_POS (2U) +#define MPU_SR_FMPUEAF (0x00000004UL) +#define MPU_SR_HMPUEAF_POS (3U) +#define MPU_SR_HMPUEAF (0x00000008UL) +#define MPU_SR_EMPUEAF_POS (4U) +#define MPU_SR_EMPUEAF (0x00000010UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU1ECLR_POS (0U) +#define MPU_ECLR_SMPU1ECLR (0x00000001UL) +#define MPU_ECLR_SMPU2ECLR_POS (1U) +#define MPU_ECLR_SMPU2ECLR (0x00000002UL) +#define MPU_ECLR_FMPUECLR_POS (2U) +#define MPU_ECLR_FMPUECLR (0x00000004UL) +#define MPU_ECLR_HMPUECLR_POS (3U) +#define MPU_ECLR_HMPUECLR (0x00000008UL) +#define MPU_ECLR_EMPUECLR_POS (4U) +#define MPU_ECLR_EMPUECLR (0x00000010UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_EFMRDP_POS (8U) +#define MPU_IPPR_EFMRDP (0x00000100UL) +#define MPU_IPPR_EFMWRP_POS (9U) +#define MPU_IPPR_EFMWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSPTWRP_POS (29U) +#define MPU_IPPR_MSPTWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/* Bit definition for MPU_S1RGE register */ +#define MPU_S1RGE_S1RG0E_POS (0U) +#define MPU_S1RGE_S1RG0E (0x00000001UL) +#define MPU_S1RGE_S1RG1E_POS (1U) +#define MPU_S1RGE_S1RG1E (0x00000002UL) +#define MPU_S1RGE_S1RG2E_POS (2U) +#define MPU_S1RGE_S1RG2E (0x00000004UL) +#define MPU_S1RGE_S1RG3E_POS (3U) +#define MPU_S1RGE_S1RG3E (0x00000008UL) +#define MPU_S1RGE_S1RG4E_POS (4U) +#define MPU_S1RGE_S1RG4E (0x00000010UL) +#define MPU_S1RGE_S1RG5E_POS (5U) +#define MPU_S1RGE_S1RG5E (0x00000020UL) +#define MPU_S1RGE_S1RG6E_POS (6U) +#define MPU_S1RGE_S1RG6E (0x00000040UL) +#define MPU_S1RGE_S1RG7E_POS (7U) +#define MPU_S1RGE_S1RG7E (0x00000080UL) +#define MPU_S1RGE_S1RG8E_POS (8U) +#define MPU_S1RGE_S1RG8E (0x00000100UL) +#define MPU_S1RGE_S1RG9E_POS (9U) +#define MPU_S1RGE_S1RG9E (0x00000200UL) +#define MPU_S1RGE_S1RG10E_POS (10U) +#define MPU_S1RGE_S1RG10E (0x00000400UL) +#define MPU_S1RGE_S1RG11E_POS (11U) +#define MPU_S1RGE_S1RG11E (0x00000800UL) +#define MPU_S1RGE_S1RG12E_POS (12U) +#define MPU_S1RGE_S1RG12E (0x00001000UL) +#define MPU_S1RGE_S1RG13E_POS (13U) +#define MPU_S1RGE_S1RG13E (0x00002000UL) +#define MPU_S1RGE_S1RG14E_POS (14U) +#define MPU_S1RGE_S1RG14E (0x00004000UL) +#define MPU_S1RGE_S1RG15E_POS (15U) +#define MPU_S1RGE_S1RG15E (0x00008000UL) + +/* Bit definition for MPU_S1RGWP register */ +#define MPU_S1RGWP_S1RG0WP_POS (0U) +#define MPU_S1RGWP_S1RG0WP (0x00000001UL) +#define MPU_S1RGWP_S1RG1WP_POS (1U) +#define MPU_S1RGWP_S1RG1WP (0x00000002UL) +#define MPU_S1RGWP_S1RG2WP_POS (2U) +#define MPU_S1RGWP_S1RG2WP (0x00000004UL) +#define MPU_S1RGWP_S1RG3WP_POS (3U) +#define MPU_S1RGWP_S1RG3WP (0x00000008UL) +#define MPU_S1RGWP_S1RG4WP_POS (4U) +#define MPU_S1RGWP_S1RG4WP (0x00000010UL) +#define MPU_S1RGWP_S1RG5WP_POS (5U) +#define MPU_S1RGWP_S1RG5WP (0x00000020UL) +#define MPU_S1RGWP_S1RG6WP_POS (6U) +#define MPU_S1RGWP_S1RG6WP (0x00000040UL) +#define MPU_S1RGWP_S1RG7WP_POS (7U) +#define MPU_S1RGWP_S1RG7WP (0x00000080UL) +#define MPU_S1RGWP_S1RG8WP_POS (8U) +#define MPU_S1RGWP_S1RG8WP (0x00000100UL) +#define MPU_S1RGWP_S1RG9WP_POS (9U) +#define MPU_S1RGWP_S1RG9WP (0x00000200UL) +#define MPU_S1RGWP_S1RG10WP_POS (10U) +#define MPU_S1RGWP_S1RG10WP (0x00000400UL) +#define MPU_S1RGWP_S1RG11WP_POS (11U) +#define MPU_S1RGWP_S1RG11WP (0x00000800UL) +#define MPU_S1RGWP_S1RG12WP_POS (12U) +#define MPU_S1RGWP_S1RG12WP (0x00001000UL) +#define MPU_S1RGWP_S1RG13WP_POS (13U) +#define MPU_S1RGWP_S1RG13WP (0x00002000UL) +#define MPU_S1RGWP_S1RG14WP_POS (14U) +#define MPU_S1RGWP_S1RG14WP (0x00004000UL) +#define MPU_S1RGWP_S1RG15WP_POS (15U) +#define MPU_S1RGWP_S1RG15WP (0x00008000UL) + +/* Bit definition for MPU_S1RGRP register */ +#define MPU_S1RGRP_S1RG0RP_POS (0U) +#define MPU_S1RGRP_S1RG0RP (0x00000001UL) +#define MPU_S1RGRP_S1RG1RP_POS (1U) +#define MPU_S1RGRP_S1RG1RP (0x00000002UL) +#define MPU_S1RGRP_S1RG2RP_POS (2U) +#define MPU_S1RGRP_S1RG2RP (0x00000004UL) +#define MPU_S1RGRP_S1RG3RP_POS (3U) +#define MPU_S1RGRP_S1RG3RP (0x00000008UL) +#define MPU_S1RGRP_S1RG4RP_POS (4U) +#define MPU_S1RGRP_S1RG4RP (0x00000010UL) +#define MPU_S1RGRP_S1RG5RP_POS (5U) +#define MPU_S1RGRP_S1RG5RP (0x00000020UL) +#define MPU_S1RGRP_S1RG6RP_POS (6U) +#define MPU_S1RGRP_S1RG6RP (0x00000040UL) +#define MPU_S1RGRP_S1RG7RP_POS (7U) +#define MPU_S1RGRP_S1RG7RP (0x00000080UL) +#define MPU_S1RGRP_S1RG8RP_POS (8U) +#define MPU_S1RGRP_S1RG8RP (0x00000100UL) +#define MPU_S1RGRP_S1RG9RP_POS (9U) +#define MPU_S1RGRP_S1RG9RP (0x00000200UL) +#define MPU_S1RGRP_S1RG10RP_POS (10U) +#define MPU_S1RGRP_S1RG10RP (0x00000400UL) +#define MPU_S1RGRP_S1RG11RP_POS (11U) +#define MPU_S1RGRP_S1RG11RP (0x00000800UL) +#define MPU_S1RGRP_S1RG12RP_POS (12U) +#define MPU_S1RGRP_S1RG12RP (0x00001000UL) +#define MPU_S1RGRP_S1RG13RP_POS (13U) +#define MPU_S1RGRP_S1RG13RP (0x00002000UL) +#define MPU_S1RGRP_S1RG14RP_POS (14U) +#define MPU_S1RGRP_S1RG14RP (0x00004000UL) +#define MPU_S1RGRP_S1RG15RP_POS (15U) +#define MPU_S1RGRP_S1RG15RP (0x00008000UL) + +/* Bit definition for MPU_S1CR register */ +#define MPU_S1CR_SMPU1BRP_POS (0U) +#define MPU_S1CR_SMPU1BRP (0x00000001UL) +#define MPU_S1CR_SMPU1BWP_POS (1U) +#define MPU_S1CR_SMPU1BWP (0x00000002UL) +#define MPU_S1CR_SMPU1ACT_POS (2U) +#define MPU_S1CR_SMPU1ACT (0x0000000CUL) +#define MPU_S1CR_SMPU1ACT_0 (0x00000004UL) +#define MPU_S1CR_SMPU1ACT_1 (0x00000008UL) +#define MPU_S1CR_SMPU1E_POS (7U) +#define MPU_S1CR_SMPU1E (0x00000080UL) + +/* Bit definition for MPU_S2RGE register */ +#define MPU_S2RGE_S2RG0E_POS (0U) +#define MPU_S2RGE_S2RG0E (0x00000001UL) +#define MPU_S2RGE_S2RG1E_POS (1U) +#define MPU_S2RGE_S2RG1E (0x00000002UL) +#define MPU_S2RGE_S2RG2E_POS (2U) +#define MPU_S2RGE_S2RG2E (0x00000004UL) +#define MPU_S2RGE_S2RG3E_POS (3U) +#define MPU_S2RGE_S2RG3E (0x00000008UL) +#define MPU_S2RGE_S2RG4E_POS (4U) +#define MPU_S2RGE_S2RG4E (0x00000010UL) +#define MPU_S2RGE_S2RG5E_POS (5U) +#define MPU_S2RGE_S2RG5E (0x00000020UL) +#define MPU_S2RGE_S2RG6E_POS (6U) +#define MPU_S2RGE_S2RG6E (0x00000040UL) +#define MPU_S2RGE_S2RG7E_POS (7U) +#define MPU_S2RGE_S2RG7E (0x00000080UL) +#define MPU_S2RGE_S2RG8E_POS (8U) +#define MPU_S2RGE_S2RG8E (0x00000100UL) +#define MPU_S2RGE_S2RG9E_POS (9U) +#define MPU_S2RGE_S2RG9E (0x00000200UL) +#define MPU_S2RGE_S2RG10E_POS (10U) +#define MPU_S2RGE_S2RG10E (0x00000400UL) +#define MPU_S2RGE_S2RG11E_POS (11U) +#define MPU_S2RGE_S2RG11E (0x00000800UL) +#define MPU_S2RGE_S2RG12E_POS (12U) +#define MPU_S2RGE_S2RG12E (0x00001000UL) +#define MPU_S2RGE_S2RG13E_POS (13U) +#define MPU_S2RGE_S2RG13E (0x00002000UL) +#define MPU_S2RGE_S2RG14E_POS (14U) +#define MPU_S2RGE_S2RG14E (0x00004000UL) +#define MPU_S2RGE_S2RG15E_POS (15U) +#define MPU_S2RGE_S2RG15E (0x00008000UL) + +/* Bit definition for MPU_S2RGWP register */ +#define MPU_S2RGWP_S2RG0WP_POS (0U) +#define MPU_S2RGWP_S2RG0WP (0x00000001UL) +#define MPU_S2RGWP_S2RG1WP_POS (1U) +#define MPU_S2RGWP_S2RG1WP (0x00000002UL) +#define MPU_S2RGWP_S2RG2WP_POS (2U) +#define MPU_S2RGWP_S2RG2WP (0x00000004UL) +#define MPU_S2RGWP_S2RG3WP_POS (3U) +#define MPU_S2RGWP_S2RG3WP (0x00000008UL) +#define MPU_S2RGWP_S2RG4WP_POS (4U) +#define MPU_S2RGWP_S2RG4WP (0x00000010UL) +#define MPU_S2RGWP_S2RG5WP_POS (5U) +#define MPU_S2RGWP_S2RG5WP (0x00000020UL) +#define MPU_S2RGWP_S2RG6WP_POS (6U) +#define MPU_S2RGWP_S2RG6WP (0x00000040UL) +#define MPU_S2RGWP_S2RG7WP_POS (7U) +#define MPU_S2RGWP_S2RG7WP (0x00000080UL) +#define MPU_S2RGWP_S2RG8WP_POS (8U) +#define MPU_S2RGWP_S2RG8WP (0x00000100UL) +#define MPU_S2RGWP_S2RG9WP_POS (9U) +#define MPU_S2RGWP_S2RG9WP (0x00000200UL) +#define MPU_S2RGWP_S2RG10WP_POS (10U) +#define MPU_S2RGWP_S2RG10WP (0x00000400UL) +#define MPU_S2RGWP_S2RG11WP_POS (11U) +#define MPU_S2RGWP_S2RG11WP (0x00000800UL) +#define MPU_S2RGWP_S2RG12WP_POS (12U) +#define MPU_S2RGWP_S2RG12WP (0x00001000UL) +#define MPU_S2RGWP_S2RG13WP_POS (13U) +#define MPU_S2RGWP_S2RG13WP (0x00002000UL) +#define MPU_S2RGWP_S2RG14WP_POS (14U) +#define MPU_S2RGWP_S2RG14WP (0x00004000UL) +#define MPU_S2RGWP_S2RG15WP_POS (15U) +#define MPU_S2RGWP_S2RG15WP (0x00008000UL) + +/* Bit definition for MPU_S2RGRP register */ +#define MPU_S2RGRP_S2RG0RP_POS (0U) +#define MPU_S2RGRP_S2RG0RP (0x00000001UL) +#define MPU_S2RGRP_S2RG1RP_POS (1U) +#define MPU_S2RGRP_S2RG1RP (0x00000002UL) +#define MPU_S2RGRP_S2RG2RP_POS (2U) +#define MPU_S2RGRP_S2RG2RP (0x00000004UL) +#define MPU_S2RGRP_S2RG3RP_POS (3U) +#define MPU_S2RGRP_S2RG3RP (0x00000008UL) +#define MPU_S2RGRP_S2RG4RP_POS (4U) +#define MPU_S2RGRP_S2RG4RP (0x00000010UL) +#define MPU_S2RGRP_S2RG5RP_POS (5U) +#define MPU_S2RGRP_S2RG5RP (0x00000020UL) +#define MPU_S2RGRP_S2RG6RP_POS (6U) +#define MPU_S2RGRP_S2RG6RP (0x00000040UL) +#define MPU_S2RGRP_S2RG7RP_POS (7U) +#define MPU_S2RGRP_S2RG7RP (0x00000080UL) +#define MPU_S2RGRP_S2RG8RP_POS (8U) +#define MPU_S2RGRP_S2RG8RP (0x00000100UL) +#define MPU_S2RGRP_S2RG9RP_POS (9U) +#define MPU_S2RGRP_S2RG9RP (0x00000200UL) +#define MPU_S2RGRP_S2RG10RP_POS (10U) +#define MPU_S2RGRP_S2RG10RP (0x00000400UL) +#define MPU_S2RGRP_S2RG11RP_POS (11U) +#define MPU_S2RGRP_S2RG11RP (0x00000800UL) +#define MPU_S2RGRP_S2RG12RP_POS (12U) +#define MPU_S2RGRP_S2RG12RP (0x00001000UL) +#define MPU_S2RGRP_S2RG13RP_POS (13U) +#define MPU_S2RGRP_S2RG13RP (0x00002000UL) +#define MPU_S2RGRP_S2RG14RP_POS (14U) +#define MPU_S2RGRP_S2RG14RP (0x00004000UL) +#define MPU_S2RGRP_S2RG15RP_POS (15U) +#define MPU_S2RGRP_S2RG15RP (0x00008000UL) + +/* Bit definition for MPU_S2CR register */ +#define MPU_S2CR_SMPU2BRP_POS (0U) +#define MPU_S2CR_SMPU2BRP (0x00000001UL) +#define MPU_S2CR_SMPU2BWP_POS (1U) +#define MPU_S2CR_SMPU2BWP (0x00000002UL) +#define MPU_S2CR_SMPU2ACT_POS (2U) +#define MPU_S2CR_SMPU2ACT (0x0000000CUL) +#define MPU_S2CR_SMPU2ACT_0 (0x00000004UL) +#define MPU_S2CR_SMPU2ACT_1 (0x00000008UL) +#define MPU_S2CR_SMPU2E_POS (7U) +#define MPU_S2CR_SMPU2E (0x00000080UL) + +/* Bit definition for MPU_FRGE register */ +#define MPU_FRGE_FRG0E_POS (0U) +#define MPU_FRGE_FRG0E (0x00000001UL) +#define MPU_FRGE_FRG1E_POS (1U) +#define MPU_FRGE_FRG1E (0x00000002UL) +#define MPU_FRGE_FRG2E_POS (2U) +#define MPU_FRGE_FRG2E (0x00000004UL) +#define MPU_FRGE_FRG3E_POS (3U) +#define MPU_FRGE_FRG3E (0x00000008UL) +#define MPU_FRGE_FRG4E_POS (4U) +#define MPU_FRGE_FRG4E (0x00000010UL) +#define MPU_FRGE_FRG5E_POS (5U) +#define MPU_FRGE_FRG5E (0x00000020UL) +#define MPU_FRGE_FRG6E_POS (6U) +#define MPU_FRGE_FRG6E (0x00000040UL) +#define MPU_FRGE_FRG7E_POS (7U) +#define MPU_FRGE_FRG7E (0x00000080UL) + +/* Bit definition for MPU_FRGWP register */ +#define MPU_FRGWP_FRG0WP_POS (0U) +#define MPU_FRGWP_FRG0WP (0x00000001UL) +#define MPU_FRGWP_FRG1WP_POS (1U) +#define MPU_FRGWP_FRG1WP (0x00000002UL) +#define MPU_FRGWP_FRG2WP_POS (2U) +#define MPU_FRGWP_FRG2WP (0x00000004UL) +#define MPU_FRGWP_FRG3WP_POS (3U) +#define MPU_FRGWP_FRG3WP (0x00000008UL) +#define MPU_FRGWP_FRG4WP_POS (4U) +#define MPU_FRGWP_FRG4WP (0x00000010UL) +#define MPU_FRGWP_FRG5WP_POS (5U) +#define MPU_FRGWP_FRG5WP (0x00000020UL) +#define MPU_FRGWP_FRG6WP_POS (6U) +#define MPU_FRGWP_FRG6WP (0x00000040UL) +#define MPU_FRGWP_FRG7WP_POS (7U) +#define MPU_FRGWP_FRG7WP (0x00000080UL) + +/* Bit definition for MPU_FRGRP register */ +#define MPU_FRGRP_FRG0RP_POS (0U) +#define MPU_FRGRP_FRG0RP (0x00000001UL) +#define MPU_FRGRP_FRG1RP_POS (1U) +#define MPU_FRGRP_FRG1RP (0x00000002UL) +#define MPU_FRGRP_FRG2RP_POS (2U) +#define MPU_FRGRP_FRG2RP (0x00000004UL) +#define MPU_FRGRP_FRG3RP_POS (3U) +#define MPU_FRGRP_FRG3RP (0x00000008UL) +#define MPU_FRGRP_FRG4RP_POS (4U) +#define MPU_FRGRP_FRG4RP (0x00000010UL) +#define MPU_FRGRP_FRG5RP_POS (5U) +#define MPU_FRGRP_FRG5RP (0x00000020UL) +#define MPU_FRGRP_FRG6RP_POS (6U) +#define MPU_FRGRP_FRG6RP (0x00000040UL) +#define MPU_FRGRP_FRG7RP_POS (7U) +#define MPU_FRGRP_FRG7RP (0x00000080UL) + +/* Bit definition for MPU_FCR register */ +#define MPU_FCR_FMPUBRP_POS (0U) +#define MPU_FCR_FMPUBRP (0x00000001UL) +#define MPU_FCR_FMPUBWP_POS (1U) +#define MPU_FCR_FMPUBWP (0x00000002UL) +#define MPU_FCR_FMPUACT_POS (2U) +#define MPU_FCR_FMPUACT (0x0000000CUL) +#define MPU_FCR_FMPUACT_0 (0x00000004UL) +#define MPU_FCR_FMPUACT_1 (0x00000008UL) +#define MPU_FCR_FMPUE_POS (7U) +#define MPU_FCR_FMPUE (0x00000080UL) + +/* Bit definition for MPU_HRGE register */ +#define MPU_HRGE_HRG0E_POS (0U) +#define MPU_HRGE_HRG0E (0x00000001UL) +#define MPU_HRGE_HRG1E_POS (1U) +#define MPU_HRGE_HRG1E (0x00000002UL) +#define MPU_HRGE_HRG2E_POS (2U) +#define MPU_HRGE_HRG2E (0x00000004UL) +#define MPU_HRGE_HRG3E_POS (3U) +#define MPU_HRGE_HRG3E (0x00000008UL) +#define MPU_HRGE_HRG4E_POS (4U) +#define MPU_HRGE_HRG4E (0x00000010UL) +#define MPU_HRGE_HRG5E_POS (5U) +#define MPU_HRGE_HRG5E (0x00000020UL) +#define MPU_HRGE_HRG6E_POS (6U) +#define MPU_HRGE_HRG6E (0x00000040UL) +#define MPU_HRGE_HRG7E_POS (7U) +#define MPU_HRGE_HRG7E (0x00000080UL) + +/* Bit definition for MPU_HRGWP register */ +#define MPU_HRGWP_HRG0WP_POS (0U) +#define MPU_HRGWP_HRG0WP (0x00000001UL) +#define MPU_HRGWP_HRG1WP_POS (1U) +#define MPU_HRGWP_HRG1WP (0x00000002UL) +#define MPU_HRGWP_HRG2WP_POS (2U) +#define MPU_HRGWP_HRG2WP (0x00000004UL) +#define MPU_HRGWP_HRG3WP_POS (3U) +#define MPU_HRGWP_HRG3WP (0x00000008UL) +#define MPU_HRGWP_HRG4WP_POS (4U) +#define MPU_HRGWP_HRG4WP (0x00000010UL) +#define MPU_HRGWP_HRG5WP_POS (5U) +#define MPU_HRGWP_HRG5WP (0x00000020UL) +#define MPU_HRGWP_HRG6WP_POS (6U) +#define MPU_HRGWP_HRG6WP (0x00000040UL) +#define MPU_HRGWP_HRG7WP_POS (7U) +#define MPU_HRGWP_HRG7WP (0x00000080UL) + +/* Bit definition for MPU_HRGRP register */ +#define MPU_HRGRP_HRG0RP_POS (0U) +#define MPU_HRGRP_HRG0RP (0x00000001UL) +#define MPU_HRGRP_HRG1RP_POS (1U) +#define MPU_HRGRP_HRG1RP (0x00000002UL) +#define MPU_HRGRP_HRG2RP_POS (2U) +#define MPU_HRGRP_HRG2RP (0x00000004UL) +#define MPU_HRGRP_HRG3RP_POS (3U) +#define MPU_HRGRP_HRG3RP (0x00000008UL) +#define MPU_HRGRP_HRG4RP_POS (4U) +#define MPU_HRGRP_HRG4RP (0x00000010UL) +#define MPU_HRGRP_HRG5RP_POS (5U) +#define MPU_HRGRP_HRG5RP (0x00000020UL) +#define MPU_HRGRP_HRG6RP_POS (6U) +#define MPU_HRGRP_HRG6RP (0x00000040UL) +#define MPU_HRGRP_HRG7RP_POS (7U) +#define MPU_HRGRP_HRG7RP (0x00000080UL) + +/* Bit definition for MPU_HCR register */ +#define MPU_HCR_HMPUBRP_POS (0U) +#define MPU_HCR_HMPUBRP (0x00000001UL) +#define MPU_HCR_HMPUBWP_POS (1U) +#define MPU_HCR_HMPUBWP (0x00000002UL) +#define MPU_HCR_HMPUACT_POS (2U) +#define MPU_HCR_HMPUACT (0x0000000CUL) +#define MPU_HCR_HMPUACT_0 (0x00000004UL) +#define MPU_HCR_HMPUACT_1 (0x00000008UL) +#define MPU_HCR_HMPUE_POS (7U) +#define MPU_HCR_HMPUE (0x00000080UL) + +/* Bit definition for MPU_ERGE register */ +#define MPU_ERGE_ERG0E_POS (0U) +#define MPU_ERGE_ERG0E (0x00000001UL) +#define MPU_ERGE_ERG1E_POS (1U) +#define MPU_ERGE_ERG1E (0x00000002UL) +#define MPU_ERGE_ERG2E_POS (2U) +#define MPU_ERGE_ERG2E (0x00000004UL) +#define MPU_ERGE_ERG3E_POS (3U) +#define MPU_ERGE_ERG3E (0x00000008UL) +#define MPU_ERGE_ERG4E_POS (4U) +#define MPU_ERGE_ERG4E (0x00000010UL) +#define MPU_ERGE_ERG5E_POS (5U) +#define MPU_ERGE_ERG5E (0x00000020UL) +#define MPU_ERGE_ERG6E_POS (6U) +#define MPU_ERGE_ERG6E (0x00000040UL) +#define MPU_ERGE_ERG7E_POS (7U) +#define MPU_ERGE_ERG7E (0x00000080UL) + +/* Bit definition for MPU_ERGWP register */ +#define MPU_ERGWP_ERG0WP_POS (0U) +#define MPU_ERGWP_ERG0WP (0x00000001UL) +#define MPU_ERGWP_ERG1WP_POS (1U) +#define MPU_ERGWP_ERG1WP (0x00000002UL) +#define MPU_ERGWP_ERG2WP_POS (2U) +#define MPU_ERGWP_ERG2WP (0x00000004UL) +#define MPU_ERGWP_ERG3WP_POS (3U) +#define MPU_ERGWP_ERG3WP (0x00000008UL) +#define MPU_ERGWP_ERG4WP_POS (4U) +#define MPU_ERGWP_ERG4WP (0x00000010UL) +#define MPU_ERGWP_ERG5WP_POS (5U) +#define MPU_ERGWP_ERG5WP (0x00000020UL) +#define MPU_ERGWP_ERG6WP_POS (6U) +#define MPU_ERGWP_ERG6WP (0x00000040UL) +#define MPU_ERGWP_ERG7WP_POS (7U) +#define MPU_ERGWP_ERG7WP (0x00000080UL) + +/* Bit definition for MPU_ERGRP register */ +#define MPU_ERGRP_ERG0RP_POS (0U) +#define MPU_ERGRP_ERG0RP (0x00000001UL) +#define MPU_ERGRP_ERG1RP_POS (1U) +#define MPU_ERGRP_ERG1RP (0x00000002UL) +#define MPU_ERGRP_ERG2RP_POS (2U) +#define MPU_ERGRP_ERG2RP (0x00000004UL) +#define MPU_ERGRP_ERG3RP_POS (3U) +#define MPU_ERGRP_ERG3RP (0x00000008UL) +#define MPU_ERGRP_ERG4RP_POS (4U) +#define MPU_ERGRP_ERG4RP (0x00000010UL) +#define MPU_ERGRP_ERG5RP_POS (5U) +#define MPU_ERGRP_ERG5RP (0x00000020UL) +#define MPU_ERGRP_ERG6RP_POS (6U) +#define MPU_ERGRP_ERG6RP (0x00000040UL) +#define MPU_ERGRP_ERG7RP_POS (7U) +#define MPU_ERGRP_ERG7RP (0x00000080UL) + +/* Bit definition for MPU_ECR register */ +#define MPU_ECR_EMPUBRP_POS (0U) +#define MPU_ECR_EMPUBRP (0x00000001UL) +#define MPU_ECR_EMPUBWP_POS (1U) +#define MPU_ECR_EMPUBWP (0x00000002UL) +#define MPU_ECR_EMPUACT_POS (2U) +#define MPU_ECR_EMPUACT (0x0000000CUL) +#define MPU_ECR_EMPUACT_0 (0x00000004UL) +#define MPU_ECR_EMPUACT_1 (0x00000008UL) +#define MPU_ECR_EMPUE_POS (7U) +#define MPU_ECR_EMPUE (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral NFC +*******************************************************************************/ +/* Bit definition for NFC_DATR_BASE register */ +#define NFC_DATR_BASE (0xFFFFFFFFUL) + +/* Bit definition for NFC_CMDR register */ +#define NFC_CMDR_CMD_POS (0U) +#define NFC_CMDR_CMD (0x000000FFUL) +#define NFC_CMDR_ARG_POS (8U) +#define NFC_CMDR_ARG (0xFFFFFF00UL) + +/* Bit definition for NFC_IDXR0 register */ +#define NFC_IDXR0 (0xFFFFFFFFUL) + +/* Bit definition for NFC_IENR register */ +#define NFC_IENR_ECCEUEN_POS (0U) +#define NFC_IENR_ECCEUEN (0x00000001UL) +#define NFC_IENR_ECCECEN_POS (1U) +#define NFC_IENR_ECCECEN (0x00000002UL) +#define NFC_IENR_ECCCEN_POS (4U) +#define NFC_IENR_ECCCEN (0x00000010UL) +#define NFC_IENR_ECCEEN_POS (6U) +#define NFC_IENR_ECCEEN (0x00000040UL) +#define NFC_IENR_ECCDIS_POS (7U) +#define NFC_IENR_ECCDIS (0x00000080UL) +#define NFC_IENR_RBEN_POS (8U) +#define NFC_IENR_RBEN (0x0000FF00UL) +#define NFC_IENR_RBEN_0 (0x00000100UL) +#define NFC_IENR_RBEN_1 (0x00000200UL) +#define NFC_IENR_RBEN_2 (0x00000400UL) +#define NFC_IENR_RBEN_3 (0x00000800UL) +#define NFC_IENR_RBEN_4 (0x00001000UL) +#define NFC_IENR_RBEN_5 (0x00002000UL) +#define NFC_IENR_RBEN_6 (0x00004000UL) +#define NFC_IENR_RBEN_7 (0x00008000UL) + +/* Bit definition for NFC_ISTR register */ +#define NFC_ISTR_ECCEUST_POS (0U) +#define NFC_ISTR_ECCEUST (0x00000001UL) +#define NFC_ISTR_ECCECST_POS (1U) +#define NFC_ISTR_ECCECST (0x00000002UL) +#define NFC_ISTR_ECCCST_POS (4U) +#define NFC_ISTR_ECCCST (0x00000010UL) +#define NFC_ISTR_ECCEST_POS (6U) +#define NFC_ISTR_ECCEST (0x00000040UL) +#define NFC_ISTR_RBST_POS (8U) +#define NFC_ISTR_RBST (0x0000FF00UL) +#define NFC_ISTR_RBST_0 (0x00000100UL) +#define NFC_ISTR_RBST_1 (0x00000200UL) +#define NFC_ISTR_RBST_2 (0x00000400UL) +#define NFC_ISTR_RBST_3 (0x00000800UL) +#define NFC_ISTR_RBST_4 (0x00001000UL) +#define NFC_ISTR_RBST_5 (0x00002000UL) +#define NFC_ISTR_RBST_6 (0x00004000UL) +#define NFC_ISTR_RBST_7 (0x00008000UL) + +/* Bit definition for NFC_IRSR register */ +#define NFC_IRSR_ECCEURS_POS (0U) +#define NFC_IRSR_ECCEURS (0x00000001UL) +#define NFC_IRSR_ECCECRS_POS (1U) +#define NFC_IRSR_ECCECRS (0x00000002UL) +#define NFC_IRSR_ECCCRS_POS (4U) +#define NFC_IRSR_ECCCRS (0x00000010UL) +#define NFC_IRSR_ECCERS_POS (6U) +#define NFC_IRSR_ECCERS (0x00000040UL) +#define NFC_IRSR_RBRS_POS (8U) +#define NFC_IRSR_RBRS (0x0000FF00UL) +#define NFC_IRSR_RBRS_0 (0x00000100UL) +#define NFC_IRSR_RBRS_1 (0x00000200UL) +#define NFC_IRSR_RBRS_2 (0x00000400UL) +#define NFC_IRSR_RBRS_3 (0x00000800UL) +#define NFC_IRSR_RBRS_4 (0x00001000UL) +#define NFC_IRSR_RBRS_5 (0x00002000UL) +#define NFC_IRSR_RBRS_6 (0x00004000UL) +#define NFC_IRSR_RBRS_7 (0x00008000UL) + +/* Bit definition for NFC_IDXR1 register */ +#define NFC_IDXR1_IDX1 (0x000000FFUL) + +/* Bit definition for NFC_TMCR0 register */ +#define NFC_TMCR0_TS_POS (0U) +#define NFC_TMCR0_TS (0x000000FFUL) +#define NFC_TMCR0_TWP_POS (8U) +#define NFC_TMCR0_TWP (0x0000FF00UL) +#define NFC_TMCR0_TRP_POS (16U) +#define NFC_TMCR0_TRP (0x00FF0000UL) +#define NFC_TMCR0_TH_POS (24U) +#define NFC_TMCR0_TH (0xFF000000UL) + +/* Bit definition for NFC_TMCR1 register */ +#define NFC_TMCR1_TWH_POS (0U) +#define NFC_TMCR1_TWH (0x000000FFUL) +#define NFC_TMCR1_TRH_POS (8U) +#define NFC_TMCR1_TRH (0x0000FF00UL) +#define NFC_TMCR1_TRR_POS (16U) +#define NFC_TMCR1_TRR (0x00FF0000UL) +#define NFC_TMCR1_TWB_POS (24U) +#define NFC_TMCR1_TWB (0xFF000000UL) + +/* Bit definition for NFC_BACR register */ +#define NFC_BACR_SIZE_POS (0U) +#define NFC_BACR_SIZE (0x00000007UL) +#define NFC_BACR_B16BIT_POS (3U) +#define NFC_BACR_B16BIT (0x00000008UL) +#define NFC_BACR_BANK_POS (6U) +#define NFC_BACR_BANK (0x000000C0UL) +#define NFC_BACR_BANK_0 (0x00000040UL) +#define NFC_BACR_BANK_1 (0x00000080UL) +#define NFC_BACR_PAGE_POS (8U) +#define NFC_BACR_PAGE (0x00000300UL) +#define NFC_BACR_PAGE_0 (0x00000100UL) +#define NFC_BACR_PAGE_1 (0x00000200UL) +#define NFC_BACR_WP_POS (10U) +#define NFC_BACR_WP (0x00000400UL) +#define NFC_BACR_ECCM_POS (11U) +#define NFC_BACR_ECCM (0x00001800UL) +#define NFC_BACR_ECCM_0 (0x00000800UL) +#define NFC_BACR_ECCM_1 (0x00001000UL) +#define NFC_BACR_RAC_POS (13U) +#define NFC_BACR_RAC (0x00002000UL) +#define NFC_BACR_SCS_POS (16U) +#define NFC_BACR_SCS (0x00FF0000UL) + +/* Bit definition for NFC_TMCR2 register */ +#define NFC_TMCR2_TCCS_POS (0U) +#define NFC_TMCR2_TCCS (0x000000FFUL) +#define NFC_TMCR2_TWTR_POS (8U) +#define NFC_TMCR2_TWTR (0x0000FF00UL) +#define NFC_TMCR2_TRTW_POS (16U) +#define NFC_TMCR2_TRTW (0x00FF0000UL) +#define NFC_TMCR2_TADL_POS (24U) +#define NFC_TMCR2_TADL (0xFF000000UL) + +/* Bit definition for NFC_ECCR register */ +#define NFC_ECCR_ERRLOC_POS (0U) +#define NFC_ECCR_ERRLOC (0x00000FFFUL) +#define NFC_ECCR_SE_POS (12U) +#define NFC_ECCR_SE (0x00001000UL) +#define NFC_ECCR_ME_POS (13U) +#define NFC_ECCR_ME (0x00002000UL) + +/* Bit definition for NFC_ECC_STAT register */ +#define NFC_ECC_STAT_ERRSEC (0x0000FFFFUL) + +/* Bit definition for NFC_ECC_SYND0_0 register */ +#define NFC_ECC_SYND0_0_S1_POS (0U) +#define NFC_ECC_SYND0_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND0_0_S2_POS (16U) +#define NFC_ECC_SYND0_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_1 register */ +#define NFC_ECC_SYND0_1_S3_POS (0U) +#define NFC_ECC_SYND0_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND0_1_S4_POS (16U) +#define NFC_ECC_SYND0_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_2 register */ +#define NFC_ECC_SYND0_2_S5_POS (0U) +#define NFC_ECC_SYND0_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND0_2_S6_POS (16U) +#define NFC_ECC_SYND0_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_3 register */ +#define NFC_ECC_SYND0_3_S7_POS (0U) +#define NFC_ECC_SYND0_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND0_3_S8_POS (16U) +#define NFC_ECC_SYND0_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_0 register */ +#define NFC_ECC_SYND1_0_S1_POS (0U) +#define NFC_ECC_SYND1_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND1_0_S2_POS (16U) +#define NFC_ECC_SYND1_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_1 register */ +#define NFC_ECC_SYND1_1_S3_POS (0U) +#define NFC_ECC_SYND1_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND1_1_S4_POS (16U) +#define NFC_ECC_SYND1_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_2 register */ +#define NFC_ECC_SYND1_2_S5_POS (0U) +#define NFC_ECC_SYND1_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND1_2_S6_POS (16U) +#define NFC_ECC_SYND1_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_3 register */ +#define NFC_ECC_SYND1_3_S7_POS (0U) +#define NFC_ECC_SYND1_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND1_3_S8_POS (16U) +#define NFC_ECC_SYND1_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_0 register */ +#define NFC_ECC_SYND2_0_S1_POS (0U) +#define NFC_ECC_SYND2_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND2_0_S2_POS (16U) +#define NFC_ECC_SYND2_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_1 register */ +#define NFC_ECC_SYND2_1_S3_POS (0U) +#define NFC_ECC_SYND2_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND2_1_S4_POS (16U) +#define NFC_ECC_SYND2_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_2 register */ +#define NFC_ECC_SYND2_2_S5_POS (0U) +#define NFC_ECC_SYND2_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND2_2_S6_POS (16U) +#define NFC_ECC_SYND2_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_3 register */ +#define NFC_ECC_SYND2_3_S7_POS (0U) +#define NFC_ECC_SYND2_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND2_3_S8_POS (16U) +#define NFC_ECC_SYND2_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_0 register */ +#define NFC_ECC_SYND3_0_S1_POS (0U) +#define NFC_ECC_SYND3_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND3_0_S2_POS (16U) +#define NFC_ECC_SYND3_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_1 register */ +#define NFC_ECC_SYND3_1_S3_POS (0U) +#define NFC_ECC_SYND3_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND3_1_S4_POS (16U) +#define NFC_ECC_SYND3_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_2 register */ +#define NFC_ECC_SYND3_2_S5_POS (0U) +#define NFC_ECC_SYND3_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND3_2_S6_POS (16U) +#define NFC_ECC_SYND3_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_3 register */ +#define NFC_ECC_SYND3_3_S7_POS (0U) +#define NFC_ECC_SYND3_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND3_3_S8_POS (16U) +#define NFC_ECC_SYND3_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_0 register */ +#define NFC_ECC_SYND4_0_S1_POS (0U) +#define NFC_ECC_SYND4_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND4_0_S2_POS (16U) +#define NFC_ECC_SYND4_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_1 register */ +#define NFC_ECC_SYND4_1_S3_POS (0U) +#define NFC_ECC_SYND4_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND4_1_S4_POS (16U) +#define NFC_ECC_SYND4_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_2 register */ +#define NFC_ECC_SYND4_2_S5_POS (0U) +#define NFC_ECC_SYND4_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND4_2_S6_POS (16U) +#define NFC_ECC_SYND4_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_3 register */ +#define NFC_ECC_SYND4_3_S7_POS (0U) +#define NFC_ECC_SYND4_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND4_3_S8_POS (16U) +#define NFC_ECC_SYND4_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_0 register */ +#define NFC_ECC_SYND5_0_S1_POS (0U) +#define NFC_ECC_SYND5_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND5_0_S2_POS (16U) +#define NFC_ECC_SYND5_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_1 register */ +#define NFC_ECC_SYND5_1_S3_POS (0U) +#define NFC_ECC_SYND5_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND5_1_S4_POS (16U) +#define NFC_ECC_SYND5_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_2 register */ +#define NFC_ECC_SYND5_2_S5_POS (0U) +#define NFC_ECC_SYND5_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND5_2_S6_POS (16U) +#define NFC_ECC_SYND5_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_3 register */ +#define NFC_ECC_SYND5_3_S7_POS (0U) +#define NFC_ECC_SYND5_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND5_3_S8_POS (16U) +#define NFC_ECC_SYND5_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_0 register */ +#define NFC_ECC_SYND6_0_S1_POS (0U) +#define NFC_ECC_SYND6_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND6_0_S2_POS (16U) +#define NFC_ECC_SYND6_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_1 register */ +#define NFC_ECC_SYND6_1_S3_POS (0U) +#define NFC_ECC_SYND6_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND6_1_S3_0 (0x00000001UL) +#define NFC_ECC_SYND6_1_S3_1 (0x00000002UL) +#define NFC_ECC_SYND6_1_S3_2 (0x00000004UL) +#define NFC_ECC_SYND6_1_S3_3 (0x00000008UL) +#define NFC_ECC_SYND6_1_S3_4 (0x00000010UL) +#define NFC_ECC_SYND6_1_S3_5 (0x00000020UL) +#define NFC_ECC_SYND6_1_S3_6 (0x00000040UL) +#define NFC_ECC_SYND6_1_S3_7 (0x00000080UL) +#define NFC_ECC_SYND6_1_S3_8 (0x00000100UL) +#define NFC_ECC_SYND6_1_S3_9 (0x00000200UL) +#define NFC_ECC_SYND6_1_S3_10 (0x00000400UL) +#define NFC_ECC_SYND6_1_S3_11 (0x00000800UL) +#define NFC_ECC_SYND6_1_S3_12 (0x00001000UL) +#define NFC_ECC_SYND6_1_S4_POS (16U) +#define NFC_ECC_SYND6_1_S4 (0x1FFF0000UL) +#define NFC_ECC_SYND6_1_S4_0 (0x00010000UL) +#define NFC_ECC_SYND6_1_S4_1 (0x00020000UL) +#define NFC_ECC_SYND6_1_S4_2 (0x00040000UL) +#define NFC_ECC_SYND6_1_S4_3 (0x00080000UL) +#define NFC_ECC_SYND6_1_S4_4 (0x00100000UL) +#define NFC_ECC_SYND6_1_S4_5 (0x00200000UL) +#define NFC_ECC_SYND6_1_S4_6 (0x00400000UL) +#define NFC_ECC_SYND6_1_S4_7 (0x00800000UL) +#define NFC_ECC_SYND6_1_S4_8 (0x01000000UL) +#define NFC_ECC_SYND6_1_S4_9 (0x02000000UL) +#define NFC_ECC_SYND6_1_S4_10 (0x04000000UL) +#define NFC_ECC_SYND6_1_S4_11 (0x08000000UL) +#define NFC_ECC_SYND6_1_S4_12 (0x10000000UL) +#define NFC_ECC_SYND6_1_RESV_POS (31U) +#define NFC_ECC_SYND6_1_RESV (0x80000000UL) + +/* Bit definition for NFC_ECC_SYND6_2 register */ +#define NFC_ECC_SYND6_2_S5_POS (0U) +#define NFC_ECC_SYND6_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND6_2_S6_POS (16U) +#define NFC_ECC_SYND6_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_3 register */ +#define NFC_ECC_SYND6_3_S7_POS (0U) +#define NFC_ECC_SYND6_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND6_3_S8_POS (16U) +#define NFC_ECC_SYND6_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_0 register */ +#define NFC_ECC_SYND7_0_S1_POS (0U) +#define NFC_ECC_SYND7_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND7_0_S2_POS (16U) +#define NFC_ECC_SYND7_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_1 register */ +#define NFC_ECC_SYND7_1_S3_POS (0U) +#define NFC_ECC_SYND7_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND7_1_S4_POS (16U) +#define NFC_ECC_SYND7_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_2 register */ +#define NFC_ECC_SYND7_2_S5_POS (0U) +#define NFC_ECC_SYND7_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND7_2_S6_POS (16U) +#define NFC_ECC_SYND7_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_3 register */ +#define NFC_ECC_SYND7_3_S7_POS (0U) +#define NFC_ECC_SYND7_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND7_3_S8_POS (16U) +#define NFC_ECC_SYND7_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_0 register */ +#define NFC_ECC_SYND8_0_S1_POS (0U) +#define NFC_ECC_SYND8_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND8_0_S2_POS (16U) +#define NFC_ECC_SYND8_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_1 register */ +#define NFC_ECC_SYND8_1_S3_POS (0U) +#define NFC_ECC_SYND8_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND8_1_S4_POS (16U) +#define NFC_ECC_SYND8_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_2 register */ +#define NFC_ECC_SYND8_2_S5_POS (0U) +#define NFC_ECC_SYND8_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND8_2_S6_POS (16U) +#define NFC_ECC_SYND8_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_3 register */ +#define NFC_ECC_SYND8_3_S7_POS (0U) +#define NFC_ECC_SYND8_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND8_3_S8_POS (16U) +#define NFC_ECC_SYND8_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_0 register */ +#define NFC_ECC_SYND9_0_S1_POS (0U) +#define NFC_ECC_SYND9_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND9_0_S2_POS (16U) +#define NFC_ECC_SYND9_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_1 register */ +#define NFC_ECC_SYND9_1_S3_POS (0U) +#define NFC_ECC_SYND9_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND9_1_S4_POS (16U) +#define NFC_ECC_SYND9_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_2 register */ +#define NFC_ECC_SYND9_2_S5_POS (0U) +#define NFC_ECC_SYND9_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND9_2_S6_POS (16U) +#define NFC_ECC_SYND9_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_3 register */ +#define NFC_ECC_SYND9_3_S7_POS (0U) +#define NFC_ECC_SYND9_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND9_3_S8_POS (16U) +#define NFC_ECC_SYND9_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_0 register */ +#define NFC_ECC_SYND10_0_S1_POS (0U) +#define NFC_ECC_SYND10_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND10_0_S2_POS (16U) +#define NFC_ECC_SYND10_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_1 register */ +#define NFC_ECC_SYND10_1_S3_POS (0U) +#define NFC_ECC_SYND10_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND10_1_S4_POS (16U) +#define NFC_ECC_SYND10_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_2 register */ +#define NFC_ECC_SYND10_2_S5_POS (0U) +#define NFC_ECC_SYND10_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND10_2_S6_POS (16U) +#define NFC_ECC_SYND10_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_3 register */ +#define NFC_ECC_SYND10_3_S7_POS (0U) +#define NFC_ECC_SYND10_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND10_3_S8_POS (16U) +#define NFC_ECC_SYND10_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_0 register */ +#define NFC_ECC_SYND11_0_S1_POS (0U) +#define NFC_ECC_SYND11_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND11_0_S2_POS (16U) +#define NFC_ECC_SYND11_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_1 register */ +#define NFC_ECC_SYND11_1_S3_POS (0U) +#define NFC_ECC_SYND11_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND11_1_S4_POS (16U) +#define NFC_ECC_SYND11_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_2 register */ +#define NFC_ECC_SYND11_2_S5_POS (0U) +#define NFC_ECC_SYND11_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND11_2_S6_POS (16U) +#define NFC_ECC_SYND11_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_3 register */ +#define NFC_ECC_SYND11_3_S7_POS (0U) +#define NFC_ECC_SYND11_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND11_3_S8_POS (16U) +#define NFC_ECC_SYND11_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_0 register */ +#define NFC_ECC_SYND12_0_S1_POS (0U) +#define NFC_ECC_SYND12_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND12_0_S2_POS (16U) +#define NFC_ECC_SYND12_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_1 register */ +#define NFC_ECC_SYND12_1_S3_POS (0U) +#define NFC_ECC_SYND12_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND12_1_S4_POS (16U) +#define NFC_ECC_SYND12_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_2 register */ +#define NFC_ECC_SYND12_2_S5_POS (0U) +#define NFC_ECC_SYND12_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND12_2_S6_POS (16U) +#define NFC_ECC_SYND12_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_3 register */ +#define NFC_ECC_SYND12_3_S7_POS (0U) +#define NFC_ECC_SYND12_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND12_3_S8_POS (16U) +#define NFC_ECC_SYND12_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_0 register */ +#define NFC_ECC_SYND13_0_S1_POS (0U) +#define NFC_ECC_SYND13_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND13_0_S2_POS (16U) +#define NFC_ECC_SYND13_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_1 register */ +#define NFC_ECC_SYND13_1_S3_POS (0U) +#define NFC_ECC_SYND13_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND13_1_S4_POS (16U) +#define NFC_ECC_SYND13_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_2 register */ +#define NFC_ECC_SYND13_2_S5_POS (0U) +#define NFC_ECC_SYND13_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND13_2_S6_POS (16U) +#define NFC_ECC_SYND13_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_3 register */ +#define NFC_ECC_SYND13_3_S7_POS (0U) +#define NFC_ECC_SYND13_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND13_3_S8_POS (16U) +#define NFC_ECC_SYND13_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_0 register */ +#define NFC_ECC_SYND14_0_S1_POS (0U) +#define NFC_ECC_SYND14_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND14_0_S2_POS (16U) +#define NFC_ECC_SYND14_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_1 register */ +#define NFC_ECC_SYND14_1_S3_POS (0U) +#define NFC_ECC_SYND14_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND14_1_S4_POS (16U) +#define NFC_ECC_SYND14_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_2 register */ +#define NFC_ECC_SYND14_2_S5_POS (0U) +#define NFC_ECC_SYND14_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND14_2_S6_POS (16U) +#define NFC_ECC_SYND14_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_3 register */ +#define NFC_ECC_SYND14_3_S7_POS (0U) +#define NFC_ECC_SYND14_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND14_3_S8_POS (16U) +#define NFC_ECC_SYND14_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_0 register */ +#define NFC_ECC_SYND15_0_S1_POS (0U) +#define NFC_ECC_SYND15_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND15_0_S2_POS (16U) +#define NFC_ECC_SYND15_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_1 register */ +#define NFC_ECC_SYND15_1_S3_POS (0U) +#define NFC_ECC_SYND15_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND15_1_S4_POS (16U) +#define NFC_ECC_SYND15_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_2 register */ +#define NFC_ECC_SYND15_2_S5_POS (0U) +#define NFC_ECC_SYND15_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND15_2_S6_POS (16U) +#define NFC_ECC_SYND15_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_3 register */ +#define NFC_ECC_SYND15_3_S7_POS (0U) +#define NFC_ECC_SYND15_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND15_3_S8_POS (16U) +#define NFC_ECC_SYND15_3_S8 (0x1FFF0000UL) + +/******************************************************************************* + Bit definition for Peripheral OTS +*******************************************************************************/ +/* Bit definition for OTS_PDR register */ +#define OTS_PDR_TSPD1_POS (0U) +#define OTS_PDR_TSPD1 (0x0000FFFFUL) +#define OTS_PDR_TSPD2_POS (16U) +#define OTS_PDR_TSPD2 (0xFFFF0000UL) + +/* Bit definition for OTS_CTL register */ +#define OTS_CTL_OTSST_POS (0U) +#define OTS_CTL_OTSST (0x0001U) +#define OTS_CTL_OTSCK_POS (1U) +#define OTS_CTL_OTSCK (0x0002U) +#define OTS_CTL_OTSIE_POS (2U) +#define OTS_CTL_OTSIE (0x0004U) +#define OTS_CTL_TSSTP_POS (3U) +#define OTS_CTL_TSSTP (0x0008U) + +/* Bit definition for OTS_DR register */ +#define OTS_DR (0xFFFFU) + +/* Bit definition for OTS_ECR register */ +#define OTS_ECR (0xFFFFU) + +/* Bit definition for OTS_LPR register */ +#define OTS_LPR_TSOFS_POS (0U) +#define OTS_LPR_TSOFS (0x000000FFUL) +#define OTS_LPR_TSSLP_POS (8U) +#define OTS_LPR_TSSLP (0xFFFFFF00UL) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_USB_SYCTLREG register */ +#define PERIC_USB_SYCTLREG_USBFS_DFB_POS (0U) +#define PERIC_USB_SYCTLREG_USBFS_DFB (0x00000001UL) +#define PERIC_USB_SYCTLREG_USBFS_SOFEN_POS (1U) +#define PERIC_USB_SYCTLREG_USBFS_SOFEN (0x00000002UL) +#define PERIC_USB_SYCTLREG_USBHS_DFB_POS (8U) +#define PERIC_USB_SYCTLREG_USBHS_DFB (0x00000100UL) +#define PERIC_USB_SYCTLREG_USBHS_SOFEN_POS (9U) +#define PERIC_USB_SYCTLREG_USBHS_SOFEN (0x00000200UL) +#define PERIC_USB_SYCTLREG_USBHS_FSPHYE_POS (10U) +#define PERIC_USB_SYCTLREG_USBHS_FSPHYE (0x00000400UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_POS (16U) +#define PERIC_USB_SYCTLREG_USBFS_NFS (0x00030000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_0 (0x00010000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_1 (0x00020000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFE_POS (18U) +#define PERIC_USB_SYCTLREG_USBFS_NFE (0x00040000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_POS (24U) +#define PERIC_USB_SYCTLREG_USBHS_NFS (0x03000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_0 (0x01000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_1 (0x02000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFE_POS (26U) +#define PERIC_USB_SYCTLREG_USBHS_NFE (0x04000000UL) + +/* Bit definition for PERIC_SDIOC_SYCTLREG register */ +#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U) +#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL) +#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U) +#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL) + +/* Bit definition for PERIC_NFC_STCR register */ +#define PERIC_NFC_STCR_OPENP (0x00000001UL) + +/* Bit definition for PERIC_NFC_ENAR register */ +#define PERIC_NFC_ENAR_NFCEN_POS (2U) +#define PERIC_NFC_ENAR_NFCEN (0x00000004UL) + +/* Bit definition for PERIC_SMC_ENAR register */ +#define PERIC_SMC_ENAR_SMCEN_POS (1U) +#define PERIC_SMC_ENAR_SMCEN (0x00000002UL) + +/* Bit definition for PERIC_DMC_ENAR register */ +#define PERIC_DMC_ENAR_DMCEN (0x00000001UL) + +/* Bit definition for PERIC_USART1_NFC register */ +#define PERIC_USART1_NFC_USASRT1_NFS_POS (0U) +#define PERIC_USART1_NFC_USASRT1_NFS (0x00000003UL) +#define PERIC_USART1_NFC_USASRT1_NFS_0 (0x00000001UL) +#define PERIC_USART1_NFC_USASRT1_NFS_1 (0x00000002UL) +#define PERIC_USART1_NFC_USART1_NFE_POS (2U) +#define PERIC_USART1_NFC_USART1_NFE (0x00000004UL) + +/* Bit definition for PERIC_NFC_STSR register */ +#define PERIC_NFC_STSR_CHIP_BUSY_POS (0U) +#define PERIC_NFC_STSR_CHIP_BUSY (0x000000FFUL) +#define PERIC_NFC_STSR_CHIP_BUSY_0 (0x00000001UL) +#define PERIC_NFC_STSR_CHIP_BUSY_1 (0x00000002UL) +#define PERIC_NFC_STSR_CHIP_BUSY_2 (0x00000004UL) +#define PERIC_NFC_STSR_CHIP_BUSY_3 (0x00000008UL) +#define PERIC_NFC_STSR_CHIP_BUSY_4 (0x00000010UL) +#define PERIC_NFC_STSR_CHIP_BUSY_5 (0x00000020UL) +#define PERIC_NFC_STSR_CHIP_BUSY_6 (0x00000040UL) +#define PERIC_NFC_STSR_CHIP_BUSY_7 (0x00000080UL) +#define PERIC_NFC_STSR_PECC_POS (8U) +#define PERIC_NFC_STSR_PECC (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM1_POS (4U) +#define PWC_FCG0_SRAM1 (0x00000010UL) +#define PWC_FCG0_SRAM2_POS (5U) +#define PWC_FCG0_SRAM2 (0x00000020UL) +#define PWC_FCG0_SRAM3_POS (6U) +#define PWC_FCG0_SRAM3 (0x00000040UL) +#define PWC_FCG0_SRAM4_POS (7U) +#define PWC_FCG0_SRAM4 (0x00000080UL) +#define PWC_FCG0_SRAMB_POS (10U) +#define PWC_FCG0_SRAMB (0x00000400UL) +#define PWC_FCG0_KEY_POS (13U) +#define PWC_FCG0_KEY (0x00002000UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_CTC_POS (18U) +#define PWC_FCG0_CTC (0x00040000UL) +#define PWC_FCG0_MAU_POS (19U) +#define PWC_FCG0_MAU (0x00080000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) +#define PWC_FCG0_DCU5_POS (28U) +#define PWC_FCG0_DCU5 (0x10000000UL) +#define PWC_FCG0_DCU6_POS (29U) +#define PWC_FCG0_DCU6 (0x20000000UL) +#define PWC_FCG0_DCU7_POS (30U) +#define PWC_FCG0_DCU7 (0x40000000UL) +#define PWC_FCG0_DCU8_POS (31U) +#define PWC_FCG0_DCU8 (0x80000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_CAN1_POS (0U) +#define PWC_FCG1_CAN1 (0x00000001UL) +#define PWC_FCG1_CAN2_POS (1U) +#define PWC_FCG1_CAN2 (0x00000002UL) +#define PWC_FCG1_ETHMAC_POS (2U) +#define PWC_FCG1_ETHMAC (0x00000004UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_I2C1_POS (4U) +#define PWC_FCG1_I2C1 (0x00000010UL) +#define PWC_FCG1_I2C2_POS (5U) +#define PWC_FCG1_I2C2 (0x00000020UL) +#define PWC_FCG1_I2C3_POS (6U) +#define PWC_FCG1_I2C3 (0x00000040UL) +#define PWC_FCG1_I2C4_POS (7U) +#define PWC_FCG1_I2C4 (0x00000080UL) +#define PWC_FCG1_I2C5_POS (8U) +#define PWC_FCG1_I2C5 (0x00000100UL) +#define PWC_FCG1_I2C6_POS (9U) +#define PWC_FCG1_I2C6 (0x00000200UL) +#define PWC_FCG1_SDIOC1_POS (10U) +#define PWC_FCG1_SDIOC1 (0x00000400UL) +#define PWC_FCG1_SDIOC2_POS (11U) +#define PWC_FCG1_SDIOC2 (0x00000800UL) +#define PWC_FCG1_I2S1_POS (12U) +#define PWC_FCG1_I2S1 (0x00001000UL) +#define PWC_FCG1_I2S2_POS (13U) +#define PWC_FCG1_I2S2 (0x00002000UL) +#define PWC_FCG1_I2S3_POS (14U) +#define PWC_FCG1_I2S3 (0x00004000UL) +#define PWC_FCG1_I2S4_POS (15U) +#define PWC_FCG1_I2S4 (0x00008000UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) +#define PWC_FCG1_SPI4_POS (19U) +#define PWC_FCG1_SPI4 (0x00080000UL) +#define PWC_FCG1_SPI5_POS (20U) +#define PWC_FCG1_SPI5 (0x00100000UL) +#define PWC_FCG1_SPI6_POS (21U) +#define PWC_FCG1_SPI6 (0x00200000UL) +#define PWC_FCG1_USBFS_POS (22U) +#define PWC_FCG1_USBFS (0x00400000UL) +#define PWC_FCG1_USBHS_POS (23U) +#define PWC_FCG1_USBHS (0x00800000UL) +#define PWC_FCG1_FMAC1_POS (24U) +#define PWC_FCG1_FMAC1 (0x01000000UL) +#define PWC_FCG1_FMAC2_POS (25U) +#define PWC_FCG1_FMAC2 (0x02000000UL) +#define PWC_FCG1_FMAC3_POS (26U) +#define PWC_FCG1_FMAC3 (0x04000000UL) +#define PWC_FCG1_FMAC4_POS (27U) +#define PWC_FCG1_FMAC4 (0x08000000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TMR6_1_POS (0U) +#define PWC_FCG2_TMR6_1 (0x00000001UL) +#define PWC_FCG2_TMR6_2_POS (1U) +#define PWC_FCG2_TMR6_2 (0x00000002UL) +#define PWC_FCG2_TMR6_3_POS (2U) +#define PWC_FCG2_TMR6_3 (0x00000004UL) +#define PWC_FCG2_TMR6_4_POS (3U) +#define PWC_FCG2_TMR6_4 (0x00000008UL) +#define PWC_FCG2_TMR6_5_POS (4U) +#define PWC_FCG2_TMR6_5 (0x00000010UL) +#define PWC_FCG2_TMR6_6_POS (5U) +#define PWC_FCG2_TMR6_6 (0x00000020UL) +#define PWC_FCG2_TMR6_7_POS (6U) +#define PWC_FCG2_TMR6_7 (0x00000040UL) +#define PWC_FCG2_TMR6_8_POS (7U) +#define PWC_FCG2_TMR6_8 (0x00000080UL) +#define PWC_FCG2_TMR4_1_POS (8U) +#define PWC_FCG2_TMR4_1 (0x00000100UL) +#define PWC_FCG2_TMR4_2_POS (9U) +#define PWC_FCG2_TMR4_2 (0x00000200UL) +#define PWC_FCG2_TMR4_3_POS (10U) +#define PWC_FCG2_TMR4_3 (0x00000400UL) +#define PWC_FCG2_HRPWM_POS (11U) +#define PWC_FCG2_HRPWM (0x00000800UL) +#define PWC_FCG2_TMR0_1_POS (12U) +#define PWC_FCG2_TMR0_1 (0x00001000UL) +#define PWC_FCG2_TMR0_2_POS (13U) +#define PWC_FCG2_TMR0_2 (0x00002000UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TMR2_1_POS (16U) +#define PWC_FCG2_TMR2_1 (0x00010000UL) +#define PWC_FCG2_TMR2_2_POS (17U) +#define PWC_FCG2_TMR2_2 (0x00020000UL) +#define PWC_FCG2_TMR2_3_POS (18U) +#define PWC_FCG2_TMR2_3 (0x00040000UL) +#define PWC_FCG2_TMR2_4_POS (19U) +#define PWC_FCG2_TMR2_4 (0x00080000UL) +#define PWC_FCG2_TMRA_1_POS (20U) +#define PWC_FCG2_TMRA_1 (0x00100000UL) +#define PWC_FCG2_TMRA_2_POS (21U) +#define PWC_FCG2_TMRA_2 (0x00200000UL) +#define PWC_FCG2_TMRA_3_POS (22U) +#define PWC_FCG2_TMRA_3 (0x00400000UL) +#define PWC_FCG2_TMRA_4_POS (23U) +#define PWC_FCG2_TMRA_4 (0x00800000UL) +#define PWC_FCG2_TMRA_5_POS (24U) +#define PWC_FCG2_TMRA_5 (0x01000000UL) +#define PWC_FCG2_TMRA_6_POS (25U) +#define PWC_FCG2_TMRA_6 (0x02000000UL) +#define PWC_FCG2_TMRA_7_POS (26U) +#define PWC_FCG2_TMRA_7 (0x04000000UL) +#define PWC_FCG2_TMRA_8_POS (27U) +#define PWC_FCG2_TMRA_8 (0x08000000UL) +#define PWC_FCG2_TMRA_9_POS (28U) +#define PWC_FCG2_TMRA_9 (0x10000000UL) +#define PWC_FCG2_TMRA_10_POS (29U) +#define PWC_FCG2_TMRA_10 (0x20000000UL) +#define PWC_FCG2_TMRA_11_POS (30U) +#define PWC_FCG2_TMRA_11 (0x40000000UL) +#define PWC_FCG2_TMRA_12_POS (31U) +#define PWC_FCG2_TMRA_12 (0x80000000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_ADC3_POS (2U) +#define PWC_FCG3_ADC3 (0x00000004UL) +#define PWC_FCG3_CMBIAS_POS (3U) +#define PWC_FCG3_CMBIAS (0x00000008UL) +#define PWC_FCG3_DAC1_POS (4U) +#define PWC_FCG3_DAC1 (0x00000010UL) +#define PWC_FCG3_DAC2_POS (5U) +#define PWC_FCG3_DAC2 (0x00000020UL) +#define PWC_FCG3_CMP1_POS (8U) +#define PWC_FCG3_CMP1 (0x00000100UL) +#define PWC_FCG3_CMP2_POS (9U) +#define PWC_FCG3_CMP2 (0x00000200UL) +#define PWC_FCG3_OTS_POS (12U) +#define PWC_FCG3_OTS (0x00001000UL) +#define PWC_FCG3_DVP_POS (15U) +#define PWC_FCG3_DVP (0x00008000UL) +#define PWC_FCG3_SMC_POS (16U) +#define PWC_FCG3_SMC (0x00010000UL) +#define PWC_FCG3_DMC_POS (17U) +#define PWC_FCG3_DMC (0x00020000UL) +#define PWC_FCG3_NFC_POS (18U) +#define PWC_FCG3_NFC (0x00040000UL) +#define PWC_FCG3_USART1_POS (20U) +#define PWC_FCG3_USART1 (0x00100000UL) +#define PWC_FCG3_USART2_POS (21U) +#define PWC_FCG3_USART2 (0x00200000UL) +#define PWC_FCG3_USART3_POS (22U) +#define PWC_FCG3_USART3 (0x00400000UL) +#define PWC_FCG3_USART4_POS (23U) +#define PWC_FCG3_USART4 (0x00800000UL) +#define PWC_FCG3_USART5_POS (24U) +#define PWC_FCG3_USART5 (0x01000000UL) +#define PWC_FCG3_USART6_POS (25U) +#define PWC_FCG3_USART6 (0x02000000UL) +#define PWC_FCG3_USART7_POS (26U) +#define PWC_FCG3_USART7 (0x04000000UL) +#define PWC_FCG3_USART8_POS (27U) +#define PWC_FCG3_USART8 (0x08000000UL) +#define PWC_FCG3_USART9_POS (28U) +#define PWC_FCG3_USART9 (0x10000000UL) +#define PWC_FCG3_USART10_POS (29U) +#define PWC_FCG3_USART10 (0x20000000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_VBATRSTR register */ +#define PWC_VBATRSTR (0xFFU) + +/* Bit definition for PWC_VBATCR register */ +#define PWC_VBATCR_VBTRSD_POS (0U) +#define PWC_VBATCR_VBTRSD (0x01U) +#define PWC_VBATCR_RAMVALID_POS (1U) +#define PWC_VBATCR_RAMVALID (0x02U) +#define PWC_VBATCR_RAMPDF_POS (2U) +#define PWC_VBATCR_RAMPDF (0x04U) +#define PWC_VBATCR_VBATDIVMONE_POS (3U) +#define PWC_VBATCR_VBATDIVMONE (0x08U) +#define PWC_VBATCR_CSDIS_POS (7U) +#define PWC_VBATCR_CSDIS (0x80U) + +/* Bit definition for PWC_WKTC0 register */ +#define PWC_WKTC0_WKTMCMP (0xFFU) + +/* Bit definition for PWC_WKTC1 register */ +#define PWC_WKTC1_WKTMCMP (0x0FU) + +/* Bit definition for PWC_WKTC2 register */ +#define PWC_WKTC2_WKOVF_POS (4U) +#define PWC_WKTC2_WKOVF (0x10U) +#define PWC_WKTC2_WKCKS_POS (5U) +#define PWC_WKTC2_WKCKS (0x60U) +#define PWC_WKTC2_WKCKS_0 (0x20U) +#define PWC_WKTC2_WKCKS_1 (0x40U) +#define PWC_WKTC2_WKTCE_POS (7U) +#define PWC_WKTC2_WKTCE (0x80U) + +/* Bit definition for PWC_BKR0 register */ +#define PWC_BKR0 (0xFFU) + +/* Bit definition for PWC_BKR1 register */ +#define PWC_BKR1 (0xFFU) + +/* Bit definition for PWC_BKR2 register */ +#define PWC_BKR2 (0xFFU) + +/* Bit definition for PWC_BKR3 register */ +#define PWC_BKR3 (0xFFU) + +/* Bit definition for PWC_BKR4 register */ +#define PWC_BKR4 (0xFFU) + +/* Bit definition for PWC_BKR5 register */ +#define PWC_BKR5 (0xFFU) + +/* Bit definition for PWC_BKR6 register */ +#define PWC_BKR6 (0xFFU) + +/* Bit definition for PWC_BKR7 register */ +#define PWC_BKR7 (0xFFU) + +/* Bit definition for PWC_BKR8 register */ +#define PWC_BKR8 (0xFFU) + +/* Bit definition for PWC_BKR9 register */ +#define PWC_BKR9 (0xFFU) + +/* Bit definition for PWC_BKR10 register */ +#define PWC_BKR10 (0xFFU) + +/* Bit definition for PWC_BKR11 register */ +#define PWC_BKR11 (0xFFU) + +/* Bit definition for PWC_BKR12 register */ +#define PWC_BKR12 (0xFFU) + +/* Bit definition for PWC_BKR13 register */ +#define PWC_BKR13 (0xFFU) + +/* Bit definition for PWC_BKR14 register */ +#define PWC_BKR14 (0xFFU) + +/* Bit definition for PWC_BKR15 register */ +#define PWC_BKR15 (0xFFU) + +/* Bit definition for PWC_BKR16 register */ +#define PWC_BKR16 (0xFFU) + +/* Bit definition for PWC_BKR17 register */ +#define PWC_BKR17 (0xFFU) + +/* Bit definition for PWC_BKR18 register */ +#define PWC_BKR18 (0xFFU) + +/* Bit definition for PWC_BKR19 register */ +#define PWC_BKR19 (0xFFU) + +/* Bit definition for PWC_BKR20 register */ +#define PWC_BKR20 (0xFFU) + +/* Bit definition for PWC_BKR21 register */ +#define PWC_BKR21 (0xFFU) + +/* Bit definition for PWC_BKR22 register */ +#define PWC_BKR22 (0xFFU) + +/* Bit definition for PWC_BKR23 register */ +#define PWC_BKR23 (0xFFU) + +/* Bit definition for PWC_BKR24 register */ +#define PWC_BKR24 (0xFFU) + +/* Bit definition for PWC_BKR25 register */ +#define PWC_BKR25 (0xFFU) + +/* Bit definition for PWC_BKR26 register */ +#define PWC_BKR26 (0xFFU) + +/* Bit definition for PWC_BKR27 register */ +#define PWC_BKR27 (0xFFU) + +/* Bit definition for PWC_BKR28 register */ +#define PWC_BKR28 (0xFFU) + +/* Bit definition for PWC_BKR29 register */ +#define PWC_BKR29 (0xFFU) + +/* Bit definition for PWC_BKR30 register */ +#define PWC_BKR30 (0xFFU) + +/* Bit definition for PWC_BKR31 register */ +#define PWC_BKR31 (0xFFU) + +/* Bit definition for PWC_BKR32 register */ +#define PWC_BKR32 (0xFFU) + +/* Bit definition for PWC_BKR33 register */ +#define PWC_BKR33 (0xFFU) + +/* Bit definition for PWC_BKR34 register */ +#define PWC_BKR34 (0xFFU) + +/* Bit definition for PWC_BKR35 register */ +#define PWC_BKR35 (0xFFU) + +/* Bit definition for PWC_BKR36 register */ +#define PWC_BKR36 (0xFFU) + +/* Bit definition for PWC_BKR37 register */ +#define PWC_BKR37 (0xFFU) + +/* Bit definition for PWC_BKR38 register */ +#define PWC_BKR38 (0xFFU) + +/* Bit definition for PWC_BKR39 register */ +#define PWC_BKR39 (0xFFU) + +/* Bit definition for PWC_BKR40 register */ +#define PWC_BKR40 (0xFFU) + +/* Bit definition for PWC_BKR41 register */ +#define PWC_BKR41 (0xFFU) + +/* Bit definition for PWC_BKR42 register */ +#define PWC_BKR42 (0xFFU) + +/* Bit definition for PWC_BKR43 register */ +#define PWC_BKR43 (0xFFU) + +/* Bit definition for PWC_BKR44 register */ +#define PWC_BKR44 (0xFFU) + +/* Bit definition for PWC_BKR45 register */ +#define PWC_BKR45 (0xFFU) + +/* Bit definition for PWC_BKR46 register */ +#define PWC_BKR46 (0xFFU) + +/* Bit definition for PWC_BKR47 register */ +#define PWC_BKR47 (0xFFU) + +/* Bit definition for PWC_BKR48 register */ +#define PWC_BKR48 (0xFFU) + +/* Bit definition for PWC_BKR49 register */ +#define PWC_BKR49 (0xFFU) + +/* Bit definition for PWC_BKR50 register */ +#define PWC_BKR50 (0xFFU) + +/* Bit definition for PWC_BKR51 register */ +#define PWC_BKR51 (0xFFU) + +/* Bit definition for PWC_BKR52 register */ +#define PWC_BKR52 (0xFFU) + +/* Bit definition for PWC_BKR53 register */ +#define PWC_BKR53 (0xFFU) + +/* Bit definition for PWC_BKR54 register */ +#define PWC_BKR54 (0xFFU) + +/* Bit definition for PWC_BKR55 register */ +#define PWC_BKR55 (0xFFU) + +/* Bit definition for PWC_BKR56 register */ +#define PWC_BKR56 (0xFFU) + +/* Bit definition for PWC_BKR57 register */ +#define PWC_BKR57 (0xFFU) + +/* Bit definition for PWC_BKR58 register */ +#define PWC_BKR58 (0xFFU) + +/* Bit definition for PWC_BKR59 register */ +#define PWC_BKR59 (0xFFU) + +/* Bit definition for PWC_BKR60 register */ +#define PWC_BKR60 (0xFFU) + +/* Bit definition for PWC_BKR61 register */ +#define PWC_BKR61 (0xFFU) + +/* Bit definition for PWC_BKR62 register */ +#define PWC_BKR62 (0xFFU) + +/* Bit definition for PWC_BKR63 register */ +#define PWC_BKR63 (0xFFU) + +/* Bit definition for PWC_BKR64 register */ +#define PWC_BKR64 (0xFFU) + +/* Bit definition for PWC_BKR65 register */ +#define PWC_BKR65 (0xFFU) + +/* Bit definition for PWC_BKR66 register */ +#define PWC_BKR66 (0xFFU) + +/* Bit definition for PWC_BKR67 register */ +#define PWC_BKR67 (0xFFU) + +/* Bit definition for PWC_BKR68 register */ +#define PWC_BKR68 (0xFFU) + +/* Bit definition for PWC_BKR69 register */ +#define PWC_BKR69 (0xFFU) + +/* Bit definition for PWC_BKR70 register */ +#define PWC_BKR70 (0xFFU) + +/* Bit definition for PWC_BKR71 register */ +#define PWC_BKR71 (0xFFU) + +/* Bit definition for PWC_BKR72 register */ +#define PWC_BKR72 (0xFFU) + +/* Bit definition for PWC_BKR73 register */ +#define PWC_BKR73 (0xFFU) + +/* Bit definition for PWC_BKR74 register */ +#define PWC_BKR74 (0xFFU) + +/* Bit definition for PWC_BKR75 register */ +#define PWC_BKR75 (0xFFU) + +/* Bit definition for PWC_BKR76 register */ +#define PWC_BKR76 (0xFFU) + +/* Bit definition for PWC_BKR77 register */ +#define PWC_BKR77 (0xFFU) + +/* Bit definition for PWC_BKR78 register */ +#define PWC_BKR78 (0xFFU) + +/* Bit definition for PWC_BKR79 register */ +#define PWC_BKR79 (0xFFU) + +/* Bit definition for PWC_BKR80 register */ +#define PWC_BKR80 (0xFFU) + +/* Bit definition for PWC_BKR81 register */ +#define PWC_BKR81 (0xFFU) + +/* Bit definition for PWC_BKR82 register */ +#define PWC_BKR82 (0xFFU) + +/* Bit definition for PWC_BKR83 register */ +#define PWC_BKR83 (0xFFU) + +/* Bit definition for PWC_BKR84 register */ +#define PWC_BKR84 (0xFFU) + +/* Bit definition for PWC_BKR85 register */ +#define PWC_BKR85 (0xFFU) + +/* Bit definition for PWC_BKR86 register */ +#define PWC_BKR86 (0xFFU) + +/* Bit definition for PWC_BKR87 register */ +#define PWC_BKR87 (0xFFU) + +/* Bit definition for PWC_BKR88 register */ +#define PWC_BKR88 (0xFFU) + +/* Bit definition for PWC_BKR89 register */ +#define PWC_BKR89 (0xFFU) + +/* Bit definition for PWC_BKR90 register */ +#define PWC_BKR90 (0xFFU) + +/* Bit definition for PWC_BKR91 register */ +#define PWC_BKR91 (0xFFU) + +/* Bit definition for PWC_BKR92 register */ +#define PWC_BKR92 (0xFFU) + +/* Bit definition for PWC_BKR93 register */ +#define PWC_BKR93 (0xFFU) + +/* Bit definition for PWC_BKR94 register */ +#define PWC_BKR94 (0xFFU) + +/* Bit definition for PWC_BKR95 register */ +#define PWC_BKR95 (0xFFU) + +/* Bit definition for PWC_BKR96 register */ +#define PWC_BKR96 (0xFFU) + +/* Bit definition for PWC_BKR97 register */ +#define PWC_BKR97 (0xFFU) + +/* Bit definition for PWC_BKR98 register */ +#define PWC_BKR98 (0xFFU) + +/* Bit definition for PWC_BKR99 register */ +#define PWC_BKR99 (0xFFU) + +/* Bit definition for PWC_BKR100 register */ +#define PWC_BKR100 (0xFFU) + +/* Bit definition for PWC_BKR101 register */ +#define PWC_BKR101 (0xFFU) + +/* Bit definition for PWC_BKR102 register */ +#define PWC_BKR102 (0xFFU) + +/* Bit definition for PWC_BKR103 register */ +#define PWC_BKR103 (0xFFU) + +/* Bit definition for PWC_BKR104 register */ +#define PWC_BKR104 (0xFFU) + +/* Bit definition for PWC_BKR105 register */ +#define PWC_BKR105 (0xFFU) + +/* Bit definition for PWC_BKR106 register */ +#define PWC_BKR106 (0xFFU) + +/* Bit definition for PWC_BKR107 register */ +#define PWC_BKR107 (0xFFU) + +/* Bit definition for PWC_BKR108 register */ +#define PWC_BKR108 (0xFFU) + +/* Bit definition for PWC_BKR109 register */ +#define PWC_BKR109 (0xFFU) + +/* Bit definition for PWC_BKR110 register */ +#define PWC_BKR110 (0xFFU) + +/* Bit definition for PWC_BKR111 register */ +#define PWC_BKR111 (0xFFU) + +/* Bit definition for PWC_BKR112 register */ +#define PWC_BKR112 (0xFFU) + +/* Bit definition for PWC_BKR113 register */ +#define PWC_BKR113 (0xFFU) + +/* Bit definition for PWC_BKR114 register */ +#define PWC_BKR114 (0xFFU) + +/* Bit definition for PWC_BKR115 register */ +#define PWC_BKR115 (0xFFU) + +/* Bit definition for PWC_BKR116 register */ +#define PWC_BKR116 (0xFFU) + +/* Bit definition for PWC_BKR117 register */ +#define PWC_BKR117 (0xFFU) + +/* Bit definition for PWC_BKR118 register */ +#define PWC_BKR118 (0xFFU) + +/* Bit definition for PWC_BKR119 register */ +#define PWC_BKR119 (0xFFU) + +/* Bit definition for PWC_BKR120 register */ +#define PWC_BKR120 (0xFFU) + +/* Bit definition for PWC_BKR121 register */ +#define PWC_BKR121 (0xFFU) + +/* Bit definition for PWC_BKR122 register */ +#define PWC_BKR122 (0xFFU) + +/* Bit definition for PWC_BKR123 register */ +#define PWC_BKR123 (0xFFU) + +/* Bit definition for PWC_BKR124 register */ +#define PWC_BKR124 (0xFFU) + +/* Bit definition for PWC_BKR125 register */ +#define PWC_BKR125 (0xFFU) + +/* Bit definition for PWC_BKR126 register */ +#define PWC_BKR126 (0xFFU) + +/* Bit definition for PWC_BKR127 register */ +#define PWC_BKR127 (0xFFU) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x03U) +#define PWC_PWRC1_VPLLSD_0 (0x01U) +#define PWC_PWRC1_VPLLSD_1 (0x02U) +#define PWC_PWRC1_VHRCSD_POS (2U) +#define PWC_PWRC1_VHRCSD (0x04U) +#define PWC_PWRC1_PDTS_POS (3U) +#define PWC_PWRC1_PDTS (0x08U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DDAS_POS (0U) +#define PWC_PWRC2_DDAS (0x0FU) +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_DDAS (0xFFU) + +/* Bit definition for PWC_PWRC4 register */ +#define PWC_PWRC4_VBATREFSEL_POS (0U) +#define PWC_PWRC4_VBATREFSEL (0x01U) +#define PWC_PWRC4_VBATME_POS (1U) +#define PWC_PWRC4_VBATME (0x02U) +#define PWC_PWRC4_VBATMON_POS (4U) +#define PWC_PWRC4_VBATMON (0x10U) +#define PWC_PWRC4_ADBUFS_POS (6U) +#define PWC_PWRC4_ADBUFS (0x40U) +#define PWC_PWRC4_ADBUFE_POS (7U) +#define PWC_PWRC4_ADBUFE (0x80U) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE00_POS (0U) +#define PWC_PDWKE0_WKE00 (0x01U) +#define PWC_PDWKE0_WKE01_POS (1U) +#define PWC_PDWKE0_WKE01 (0x02U) +#define PWC_PDWKE0_WKE02_POS (2U) +#define PWC_PDWKE0_WKE02 (0x04U) +#define PWC_PDWKE0_WKE03_POS (3U) +#define PWC_PDWKE0_WKE03 (0x08U) +#define PWC_PDWKE0_WKE10_POS (4U) +#define PWC_PDWKE0_WKE10 (0x10U) +#define PWC_PDWKE0_WKE11_POS (5U) +#define PWC_PDWKE0_WKE11 (0x20U) +#define PWC_PDWKE0_WKE12_POS (6U) +#define PWC_PDWKE0_WKE12 (0x40U) +#define PWC_PDWKE0_WKE13_POS (7U) +#define PWC_PDWKE0_WKE13 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE20_POS (0U) +#define PWC_PDWKE1_WKE20 (0x01U) +#define PWC_PDWKE1_WKE21_POS (1U) +#define PWC_PDWKE1_WKE21 (0x02U) +#define PWC_PDWKE1_WKE22_POS (2U) +#define PWC_PDWKE1_WKE22 (0x04U) +#define PWC_PDWKE1_WKE23_POS (3U) +#define PWC_PDWKE1_WKE23 (0x08U) +#define PWC_PDWKE1_WKE30_POS (4U) +#define PWC_PDWKE1_WKE30 (0x10U) +#define PWC_PDWKE1_WKE31_POS (5U) +#define PWC_PDWKE1_WKE31 (0x20U) +#define PWC_PDWKE1_WKE32_POS (6U) +#define PWC_PDWKE1_WKE32 (0x40U) +#define PWC_PDWKE1_WKE33_POS (7U) +#define PWC_PDWKE1_WKE33 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RXD0WKF_POS (3U) +#define PWC_PDWKF1_RXD0WKF (0x08U) +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC1_POS (1U) +#define PWC_RAMPC0_RAMPDC1 (0x00000002UL) +#define PWC_RAMPC0_RAMPDC2_POS (2U) +#define PWC_RAMPC0_RAMPDC2 (0x00000004UL) +#define PWC_RAMPC0_RAMPDC3_POS (3U) +#define PWC_RAMPC0_RAMPDC3 (0x00000008UL) +#define PWC_RAMPC0_RAMPDC4_POS (4U) +#define PWC_RAMPC0_RAMPDC4 (0x00000010UL) +#define PWC_RAMPC0_RAMPDC5_POS (5U) +#define PWC_RAMPC0_RAMPDC5 (0x00000020UL) +#define PWC_RAMPC0_RAMPDC6_POS (6U) +#define PWC_RAMPC0_RAMPDC6 (0x00000040UL) +#define PWC_RAMPC0_RAMPDC7_POS (7U) +#define PWC_RAMPC0_RAMPDC7 (0x00000080UL) +#define PWC_RAMPC0_RAMPDC8_POS (8U) +#define PWC_RAMPC0_RAMPDC8 (0x00000100UL) +#define PWC_RAMPC0_RAMPDC9_POS (9U) +#define PWC_RAMPC0_RAMPDC9 (0x00000200UL) +#define PWC_RAMPC0_RAMPDC10_POS (10U) +#define PWC_RAMPC0_RAMPDC10 (0x00000400UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM (0xFFFFU) + +/* Bit definition for PWC_PRAMLPC register */ +#define PWC_PRAMLPC_PRAMPDC0_POS (0U) +#define PWC_PRAMLPC_PRAMPDC0 (0x00000001UL) +#define PWC_PRAMLPC_PRAMPDC1_POS (1U) +#define PWC_PRAMLPC_PRAMPDC1 (0x00000002UL) +#define PWC_PRAMLPC_PRAMPDC2_POS (2U) +#define PWC_PRAMLPC_PRAMPDC2 (0x00000004UL) +#define PWC_PRAMLPC_PRAMPDC3_POS (3U) +#define PWC_PRAMLPC_PRAMPDC3 (0x00000008UL) +#define PWC_PRAMLPC_PRAMPDC4_POS (4U) +#define PWC_PRAMLPC_PRAMPDC4 (0x00000010UL) +#define PWC_PRAMLPC_PRAMPDC5_POS (5U) +#define PWC_PRAMLPC_PRAMPDC5 (0x00000020UL) +#define PWC_PRAMLPC_PRAMPDC6_POS (6U) +#define PWC_PRAMLPC_PRAMPDC6 (0x00000040UL) +#define PWC_PRAMLPC_PRAMPDC7_POS (7U) +#define PWC_PRAMLPC_PRAMPDC7 (0x00000080UL) +#define PWC_PRAMLPC_PRAMPDC8_POS (8U) +#define PWC_PRAMLPC_PRAMPDC8 (0x00000100UL) +#define PWC_PRAMLPC_PRAMPDC9_POS (9U) +#define PWC_PRAMLPC_PRAMPDC9 (0x00000200UL) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1NMIS_POS (0U) +#define PWC_PVDICR_PVD1NMIS (0x01U) +#define PWC_PVDICR_PVD1EDGS_POS (1U) +#define PWC_PVDICR_PVD1EDGS (0x06U) +#define PWC_PVDICR_PVD1EDGS_0 (0x02U) +#define PWC_PVDICR_PVD1EDGS_1 (0x04U) +#define PWC_PVDICR_PVD2NMIS_POS (4U) +#define PWC_PVDICR_PVD2NMIS (0x10U) +#define PWC_PVDICR_PVD2EDGS_POS (5U) +#define PWC_PVDICR_PVD2EDGS (0x60U) +#define PWC_PVDICR_PVD2EDGS_0 (0x20U) +#define PWC_PVDICR_PVD2EDGS_1 (0x40U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_EXBUSOE_POS (14U) +#define PWC_STPMCR_EXBUSOE (0x4000U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB2_POS (2U) +#define PWC_FPRC_FPRCB2 (0x0004U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM (0x000000FFUL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_SR2 register */ +#define QSPI_SR2_RAERCLR_POS (7U) +#define QSPI_SR2_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_PRSTCR0 register */ +#define RMU_PRSTCR0_LKUPREN_POS (5U) +#define RMU_PRSTCR0_LKUPREN (0x20U) + +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x00000001UL) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x00000002UL) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x00000004UL) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x00000008UL) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x00000010UL) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x00000020UL) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x00000040UL) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x00000080UL) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x00000100UL) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x00000200UL) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x00000400UL) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x00000800UL) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x00001000UL) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x00002000UL) +#define RMU_RSTF0_LKUPRF_POS (14U) +#define RMU_RSTF0_LKUPRF (0x00004000UL) +#define RMU_RSTF0_MULTIRF_POS (30U) +#define RMU_RSTF0_MULTIRF (0x40000000UL) +#define RMU_RSTF0_CLRF_POS (31U) +#define RMU_RSTF0_CLRF (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_PRDS_0 (0x01U) +#define RTC_CR1_PRDS_1 (0x02U) +#define RTC_CR1_PRDS_2 (0x04U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_PRDF_POS (2U) +#define RTC_CR2_PRDF (0x04U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURU_0 (0x01U) +#define RTC_HOUR_HOURU_1 (0x02U) +#define RTC_HOUR_HOURU_2 (0x04U) +#define RTC_HOUR_HOURU_3 (0x08U) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURU_0 (0x01U) +#define RTC_ALMHOUR_ALMHOURU_1 (0x02U) +#define RTC_ALMHOUR_ALMHOURU_2 (0x04U) +#define RTC_ALMHOUR_ALMHOURU_3 (0x08U) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) +#define RTC_ALMWEEK_ALMWEEK_0 (0x01U) +#define RTC_ALMWEEK_ALMWEEK_1 (0x02U) +#define RTC_ALMWEEK_ALMWEEK_2 (0x04U) +#define RTC_ALMWEEK_ALMWEEK_3 (0x08U) +#define RTC_ALMWEEK_ALMWEEK_4 (0x10U) +#define RTC_ALMWEEK_ALMWEEK_5 (0x20U) +#define RTC_ALMWEEK_ALMWEEK_6 (0x40U) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL_COMP (0xFFU) + +/* Bit definition for RTC_TPCR0 register */ +#define RTC_TPCR0_TPCT0_POS (0U) +#define RTC_TPCR0_TPCT0 (0x03U) +#define RTC_TPCR0_TPCT0_0 (0x01U) +#define RTC_TPCR0_TPCT0_1 (0x02U) +#define RTC_TPCR0_TPNF0_POS (2U) +#define RTC_TPCR0_TPNF0 (0x0CU) +#define RTC_TPCR0_TPNF0_0 (0x04U) +#define RTC_TPCR0_TPNF0_1 (0x08U) +#define RTC_TPCR0_TPRSTE0_POS (4U) +#define RTC_TPCR0_TPRSTE0 (0x10U) +#define RTC_TPCR0_TPIE0_POS (5U) +#define RTC_TPCR0_TPIE0 (0x20U) +#define RTC_TPCR0_TSTPE0_POS (6U) +#define RTC_TPCR0_TSTPE0 (0x40U) +#define RTC_TPCR0_TPEN0_POS (7U) +#define RTC_TPCR0_TPEN0 (0x80U) + +/* Bit definition for RTC_TPCR1 register */ +#define RTC_TPCR1_TPCT1_POS (0U) +#define RTC_TPCR1_TPCT1 (0x03U) +#define RTC_TPCR1_TPCT1_0 (0x01U) +#define RTC_TPCR1_TPCT1_1 (0x02U) +#define RTC_TPCR1_TPNF1_POS (2U) +#define RTC_TPCR1_TPNF1 (0x0CU) +#define RTC_TPCR1_TPNF1_0 (0x04U) +#define RTC_TPCR1_TPNF1_1 (0x08U) +#define RTC_TPCR1_TPRSTE1_POS (4U) +#define RTC_TPCR1_TPRSTE1 (0x10U) +#define RTC_TPCR1_TPIE1_POS (5U) +#define RTC_TPCR1_TPIE1 (0x20U) +#define RTC_TPCR1_TSTPE1_POS (6U) +#define RTC_TPCR1_TSTPE1 (0x40U) +#define RTC_TPCR1_TPEN1_POS (7U) +#define RTC_TPCR1_TPEN1 (0x80U) + +/* Bit definition for RTC_TPSR register */ +#define RTC_TPSR_TPF0_POS (0U) +#define RTC_TPSR_TPF0 (0x01U) +#define RTC_TPSR_TPF1_POS (1U) +#define RTC_TPSR_TPF1 (0x02U) +#define RTC_TPSR_TPOVF_POS (2U) +#define RTC_TPSR_TPOVF (0x04U) + +/* Bit definition for RTC_SECTP register */ +#define RTC_SECTP_SECTPU_POS (0U) +#define RTC_SECTP_SECTPU (0x0FU) +#define RTC_SECTP_SECTPD_POS (4U) +#define RTC_SECTP_SECTPD (0x70U) + +/* Bit definition for RTC_MINTP register */ +#define RTC_MINTP_MINTPU_POS (0U) +#define RTC_MINTP_MINTPU (0x0FU) +#define RTC_MINTP_MINTPD_POS (4U) +#define RTC_MINTP_MINTPD (0x70U) + +/* Bit definition for RTC_HOURTP register */ +#define RTC_HOURTP_HOURTPU_POS (0U) +#define RTC_HOURTP_HOURTPU (0x0FU) +#define RTC_HOURTP_HOURTPU_0 (0x01U) +#define RTC_HOURTP_HOURTPU_1 (0x02U) +#define RTC_HOURTP_HOURTPU_2 (0x04U) +#define RTC_HOURTP_HOURTPU_3 (0x08U) +#define RTC_HOURTP_HOURTPD_POS (4U) +#define RTC_HOURTP_HOURTPD (0x30U) +#define RTC_HOURTP_HOURTPD_0 (0x10U) +#define RTC_HOURTP_HOURTPD_1 (0x20U) + +/* Bit definition for RTC_DAYTP register */ +#define RTC_DAYTP_DAYTPU_POS (0U) +#define RTC_DAYTP_DAYTPU (0x0FU) +#define RTC_DAYTP_DAYTPD_POS (4U) +#define RTC_DAYTP_DAYTPD (0x30U) + +/* Bit definition for RTC_MONTP register */ +#define RTC_MONTP_MONTP (0x1FU) + +/******************************************************************************* + Bit definition for Peripheral SDIOC +*******************************************************************************/ +/* Bit definition for SDIOC_BLKSIZE register */ +#define SDIOC_BLKSIZE_TBS (0x0FFFU) + +/* Bit definition for SDIOC_BLKCNT register */ +#define SDIOC_BLKCNT (0xFFFFU) + +/* Bit definition for SDIOC_ARG0 register */ +#define SDIOC_ARG0 (0xFFFFU) + +/* Bit definition for SDIOC_ARG1 register */ +#define SDIOC_ARG1 (0xFFFFU) + +/* Bit definition for SDIOC_TRANSMODE register */ +#define SDIOC_TRANSMODE_BCE_POS (1U) +#define SDIOC_TRANSMODE_BCE (0x0002U) +#define SDIOC_TRANSMODE_ATCEN_POS (2U) +#define SDIOC_TRANSMODE_ATCEN (0x000CU) +#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U) +#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U) +#define SDIOC_TRANSMODE_DDIR_POS (4U) +#define SDIOC_TRANSMODE_DDIR (0x0010U) +#define SDIOC_TRANSMODE_MULB_POS (5U) +#define SDIOC_TRANSMODE_MULB (0x0020U) + +/* Bit definition for SDIOC_CMD register */ +#define SDIOC_CMD_RESTYP_POS (0U) +#define SDIOC_CMD_RESTYP (0x0003U) +#define SDIOC_CMD_RESTYP_0 (0x0001U) +#define SDIOC_CMD_RESTYP_1 (0x0002U) +#define SDIOC_CMD_CCE_POS (3U) +#define SDIOC_CMD_CCE (0x0008U) +#define SDIOC_CMD_ICE_POS (4U) +#define SDIOC_CMD_ICE (0x0010U) +#define SDIOC_CMD_DAT_POS (5U) +#define SDIOC_CMD_DAT (0x0020U) +#define SDIOC_CMD_TYP_POS (6U) +#define SDIOC_CMD_TYP (0x00C0U) +#define SDIOC_CMD_TYP_0 (0x0040U) +#define SDIOC_CMD_TYP_1 (0x0080U) +#define SDIOC_CMD_IDX_POS (8U) +#define SDIOC_CMD_IDX (0x3F00U) +#define SDIOC_CMD_IDX_0 (0x0100U) +#define SDIOC_CMD_IDX_1 (0x0200U) +#define SDIOC_CMD_IDX_2 (0x0400U) +#define SDIOC_CMD_IDX_3 (0x0800U) +#define SDIOC_CMD_IDX_4 (0x1000U) +#define SDIOC_CMD_IDX_5 (0x2000U) + +/* Bit definition for SDIOC_RESP0 register */ +#define SDIOC_RESP0 (0xFFFFU) + +/* Bit definition for SDIOC_RESP1 register */ +#define SDIOC_RESP1 (0xFFFFU) + +/* Bit definition for SDIOC_RESP2 register */ +#define SDIOC_RESP2 (0xFFFFU) + +/* Bit definition for SDIOC_RESP3 register */ +#define SDIOC_RESP3 (0xFFFFU) + +/* Bit definition for SDIOC_RESP4 register */ +#define SDIOC_RESP4 (0xFFFFU) + +/* Bit definition for SDIOC_RESP5 register */ +#define SDIOC_RESP5 (0xFFFFU) + +/* Bit definition for SDIOC_RESP6 register */ +#define SDIOC_RESP6 (0xFFFFU) + +/* Bit definition for SDIOC_RESP7 register */ +#define SDIOC_RESP7 (0xFFFFU) + +/* Bit definition for SDIOC_BUF0 register */ +#define SDIOC_BUF0 (0xFFFFU) + +/* Bit definition for SDIOC_BUF1 register */ +#define SDIOC_BUF1 (0xFFFFU) + +/* Bit definition for SDIOC_PSTAT register */ +#define SDIOC_PSTAT_CIC_POS (0U) +#define SDIOC_PSTAT_CIC (0x00000001UL) +#define SDIOC_PSTAT_CID_POS (1U) +#define SDIOC_PSTAT_CID (0x00000002UL) +#define SDIOC_PSTAT_DA_POS (2U) +#define SDIOC_PSTAT_DA (0x00000004UL) +#define SDIOC_PSTAT_WTA_POS (8U) +#define SDIOC_PSTAT_WTA (0x00000100UL) +#define SDIOC_PSTAT_RTA_POS (9U) +#define SDIOC_PSTAT_RTA (0x00000200UL) +#define SDIOC_PSTAT_BWE_POS (10U) +#define SDIOC_PSTAT_BWE (0x00000400UL) +#define SDIOC_PSTAT_BRE_POS (11U) +#define SDIOC_PSTAT_BRE (0x00000800UL) +#define SDIOC_PSTAT_CIN_POS (16U) +#define SDIOC_PSTAT_CIN (0x00010000UL) +#define SDIOC_PSTAT_CSS_POS (17U) +#define SDIOC_PSTAT_CSS (0x00020000UL) +#define SDIOC_PSTAT_CDL_POS (18U) +#define SDIOC_PSTAT_CDL (0x00040000UL) +#define SDIOC_PSTAT_WPL_POS (19U) +#define SDIOC_PSTAT_WPL (0x00080000UL) +#define SDIOC_PSTAT_DATL_POS (20U) +#define SDIOC_PSTAT_DATL (0x00F00000UL) +#define SDIOC_PSTAT_DATL_0 (0x00100000UL) +#define SDIOC_PSTAT_DATL_1 (0x00200000UL) +#define SDIOC_PSTAT_DATL_2 (0x00400000UL) +#define SDIOC_PSTAT_DATL_3 (0x00800000UL) +#define SDIOC_PSTAT_CMDL_POS (24U) +#define SDIOC_PSTAT_CMDL (0x01000000UL) + +/* Bit definition for SDIOC_HOSTCON register */ +#define SDIOC_HOSTCON_DW_POS (1U) +#define SDIOC_HOSTCON_DW (0x02U) +#define SDIOC_HOSTCON_HSEN_POS (2U) +#define SDIOC_HOSTCON_HSEN (0x04U) +#define SDIOC_HOSTCON_EXDW_POS (5U) +#define SDIOC_HOSTCON_EXDW (0x20U) +#define SDIOC_HOSTCON_CDTL_POS (6U) +#define SDIOC_HOSTCON_CDTL (0x40U) +#define SDIOC_HOSTCON_CDSS_POS (7U) +#define SDIOC_HOSTCON_CDSS (0x80U) + +/* Bit definition for SDIOC_PWRCON register */ +#define SDIOC_PWRCON_PWON (0x01U) + +/* Bit definition for SDIOC_BLKGPCON register */ +#define SDIOC_BLKGPCON_SABGR_POS (0U) +#define SDIOC_BLKGPCON_SABGR (0x01U) +#define SDIOC_BLKGPCON_CR_POS (1U) +#define SDIOC_BLKGPCON_CR (0x02U) +#define SDIOC_BLKGPCON_RWC_POS (2U) +#define SDIOC_BLKGPCON_RWC (0x04U) +#define SDIOC_BLKGPCON_IABG_POS (3U) +#define SDIOC_BLKGPCON_IABG (0x08U) + +/* Bit definition for SDIOC_CLKCON register */ +#define SDIOC_CLKCON_ICE_POS (0U) +#define SDIOC_CLKCON_ICE (0x0001U) +#define SDIOC_CLKCON_CE_POS (2U) +#define SDIOC_CLKCON_CE (0x0004U) +#define SDIOC_CLKCON_FS_POS (8U) +#define SDIOC_CLKCON_FS (0xFF00U) +#define SDIOC_CLKCON_FS_0 (0x0100U) +#define SDIOC_CLKCON_FS_1 (0x0200U) +#define SDIOC_CLKCON_FS_2 (0x0400U) +#define SDIOC_CLKCON_FS_3 (0x0800U) +#define SDIOC_CLKCON_FS_4 (0x1000U) +#define SDIOC_CLKCON_FS_5 (0x2000U) +#define SDIOC_CLKCON_FS_6 (0x4000U) +#define SDIOC_CLKCON_FS_7 (0x8000U) + +/* Bit definition for SDIOC_TOUTCON register */ +#define SDIOC_TOUTCON_DTO (0x0FU) + +/* Bit definition for SDIOC_SFTRST register */ +#define SDIOC_SFTRST_RSTA_POS (0U) +#define SDIOC_SFTRST_RSTA (0x01U) +#define SDIOC_SFTRST_RSTC_POS (1U) +#define SDIOC_SFTRST_RSTC (0x02U) +#define SDIOC_SFTRST_RSTD_POS (2U) +#define SDIOC_SFTRST_RSTD (0x04U) + +/* Bit definition for SDIOC_NORINTST register */ +#define SDIOC_NORINTST_CC_POS (0U) +#define SDIOC_NORINTST_CC (0x0001U) +#define SDIOC_NORINTST_TC_POS (1U) +#define SDIOC_NORINTST_TC (0x0002U) +#define SDIOC_NORINTST_BGE_POS (2U) +#define SDIOC_NORINTST_BGE (0x0004U) +#define SDIOC_NORINTST_BWR_POS (4U) +#define SDIOC_NORINTST_BWR (0x0010U) +#define SDIOC_NORINTST_BRR_POS (5U) +#define SDIOC_NORINTST_BRR (0x0020U) +#define SDIOC_NORINTST_CIST_POS (6U) +#define SDIOC_NORINTST_CIST (0x0040U) +#define SDIOC_NORINTST_CRM_POS (7U) +#define SDIOC_NORINTST_CRM (0x0080U) +#define SDIOC_NORINTST_CINT_POS (8U) +#define SDIOC_NORINTST_CINT (0x0100U) +#define SDIOC_NORINTST_EI_POS (15U) +#define SDIOC_NORINTST_EI (0x8000U) + +/* Bit definition for SDIOC_ERRINTST register */ +#define SDIOC_ERRINTST_CTOE_POS (0U) +#define SDIOC_ERRINTST_CTOE (0x0001U) +#define SDIOC_ERRINTST_CCE_POS (1U) +#define SDIOC_ERRINTST_CCE (0x0002U) +#define SDIOC_ERRINTST_CEBE_POS (2U) +#define SDIOC_ERRINTST_CEBE (0x0004U) +#define SDIOC_ERRINTST_CIE_POS (3U) +#define SDIOC_ERRINTST_CIE (0x0008U) +#define SDIOC_ERRINTST_DTOE_POS (4U) +#define SDIOC_ERRINTST_DTOE (0x0010U) +#define SDIOC_ERRINTST_DCE_POS (5U) +#define SDIOC_ERRINTST_DCE (0x0020U) +#define SDIOC_ERRINTST_DEBE_POS (6U) +#define SDIOC_ERRINTST_DEBE (0x0040U) +#define SDIOC_ERRINTST_ACE_POS (8U) +#define SDIOC_ERRINTST_ACE (0x0100U) + +/* Bit definition for SDIOC_NORINTSTEN register */ +#define SDIOC_NORINTSTEN_CCEN_POS (0U) +#define SDIOC_NORINTSTEN_CCEN (0x0001U) +#define SDIOC_NORINTSTEN_TCEN_POS (1U) +#define SDIOC_NORINTSTEN_TCEN (0x0002U) +#define SDIOC_NORINTSTEN_BGEEN_POS (2U) +#define SDIOC_NORINTSTEN_BGEEN (0x0004U) +#define SDIOC_NORINTSTEN_BWREN_POS (4U) +#define SDIOC_NORINTSTEN_BWREN (0x0010U) +#define SDIOC_NORINTSTEN_BRREN_POS (5U) +#define SDIOC_NORINTSTEN_BRREN (0x0020U) +#define SDIOC_NORINTSTEN_CISTEN_POS (6U) +#define SDIOC_NORINTSTEN_CISTEN (0x0040U) +#define SDIOC_NORINTSTEN_CRMEN_POS (7U) +#define SDIOC_NORINTSTEN_CRMEN (0x0080U) +#define SDIOC_NORINTSTEN_CINTEN_POS (8U) +#define SDIOC_NORINTSTEN_CINTEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSTEN register */ +#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U) +#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U) +#define SDIOC_ERRINTSTEN_CCEEN_POS (1U) +#define SDIOC_ERRINTSTEN_CCEEN (0x0002U) +#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U) +#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U) +#define SDIOC_ERRINTSTEN_CIEEN_POS (3U) +#define SDIOC_ERRINTSTEN_CIEEN (0x0008U) +#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U) +#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U) +#define SDIOC_ERRINTSTEN_DCEEN_POS (5U) +#define SDIOC_ERRINTSTEN_DCEEN (0x0020U) +#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U) +#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U) +#define SDIOC_ERRINTSTEN_ACEEN_POS (8U) +#define SDIOC_ERRINTSTEN_ACEEN (0x0100U) + +/* Bit definition for SDIOC_NORINTSGEN register */ +#define SDIOC_NORINTSGEN_CCSEN_POS (0U) +#define SDIOC_NORINTSGEN_CCSEN (0x0001U) +#define SDIOC_NORINTSGEN_TCSEN_POS (1U) +#define SDIOC_NORINTSGEN_TCSEN (0x0002U) +#define SDIOC_NORINTSGEN_BGESEN_POS (2U) +#define SDIOC_NORINTSGEN_BGESEN (0x0004U) +#define SDIOC_NORINTSGEN_BWRSEN_POS (4U) +#define SDIOC_NORINTSGEN_BWRSEN (0x0010U) +#define SDIOC_NORINTSGEN_BRRSEN_POS (5U) +#define SDIOC_NORINTSGEN_BRRSEN (0x0020U) +#define SDIOC_NORINTSGEN_CISTSEN_POS (6U) +#define SDIOC_NORINTSGEN_CISTSEN (0x0040U) +#define SDIOC_NORINTSGEN_CRMSEN_POS (7U) +#define SDIOC_NORINTSGEN_CRMSEN (0x0080U) +#define SDIOC_NORINTSGEN_CINTSEN_POS (8U) +#define SDIOC_NORINTSGEN_CINTSEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSGEN register */ +#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U) +#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U) +#define SDIOC_ERRINTSGEN_CCESEN_POS (1U) +#define SDIOC_ERRINTSGEN_CCESEN (0x0002U) +#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U) +#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U) +#define SDIOC_ERRINTSGEN_CIESEN_POS (3U) +#define SDIOC_ERRINTSGEN_CIESEN (0x0008U) +#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U) +#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U) +#define SDIOC_ERRINTSGEN_DCESEN_POS (5U) +#define SDIOC_ERRINTSGEN_DCESEN (0x0020U) +#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U) +#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U) +#define SDIOC_ERRINTSGEN_ACESEN_POS (8U) +#define SDIOC_ERRINTSGEN_ACESEN (0x0100U) + +/* Bit definition for SDIOC_ATCERRST register */ +#define SDIOC_ATCERRST_NE_POS (0U) +#define SDIOC_ATCERRST_NE (0x0001U) +#define SDIOC_ATCERRST_TOE_POS (1U) +#define SDIOC_ATCERRST_TOE (0x0002U) +#define SDIOC_ATCERRST_CE_POS (2U) +#define SDIOC_ATCERRST_CE (0x0004U) +#define SDIOC_ATCERRST_EBE_POS (3U) +#define SDIOC_ATCERRST_EBE (0x0008U) +#define SDIOC_ATCERRST_IE_POS (4U) +#define SDIOC_ATCERRST_IE (0x0010U) +#define SDIOC_ATCERRST_CMDE_POS (7U) +#define SDIOC_ATCERRST_CMDE (0x0080U) + +/* Bit definition for SDIOC_FEA register */ +#define SDIOC_FEA_FNE_POS (0U) +#define SDIOC_FEA_FNE (0x0001U) +#define SDIOC_FEA_FTOE_POS (1U) +#define SDIOC_FEA_FTOE (0x0002U) +#define SDIOC_FEA_FCE_POS (2U) +#define SDIOC_FEA_FCE (0x0004U) +#define SDIOC_FEA_FEBE_POS (3U) +#define SDIOC_FEA_FEBE (0x0008U) +#define SDIOC_FEA_FIE_POS (4U) +#define SDIOC_FEA_FIE (0x0010U) +#define SDIOC_FEA_FCMDE_POS (7U) +#define SDIOC_FEA_FCMDE (0x0080U) + +/* Bit definition for SDIOC_FEE register */ +#define SDIOC_FEE_FCTOE_POS (0U) +#define SDIOC_FEE_FCTOE (0x0001U) +#define SDIOC_FEE_FCCE_POS (1U) +#define SDIOC_FEE_FCCE (0x0002U) +#define SDIOC_FEE_FCEBE_POS (2U) +#define SDIOC_FEE_FCEBE (0x0004U) +#define SDIOC_FEE_FCIE_POS (3U) +#define SDIOC_FEE_FCIE (0x0008U) +#define SDIOC_FEE_FDTOE_POS (4U) +#define SDIOC_FEE_FDTOE (0x0010U) +#define SDIOC_FEE_FDCE_POS (5U) +#define SDIOC_FEE_FDCE (0x0020U) +#define SDIOC_FEE_FDEBE_POS (6U) +#define SDIOC_FEE_FDEBE (0x0040U) +#define SDIOC_FEE_FACE_POS (8U) +#define SDIOC_FEE_FACE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral SMC +*******************************************************************************/ +/* Bit definition for SMC_STSR register */ +#define SMC_STSR_STATUS (0x00000001UL) + +/* Bit definition for SMC_STCR0 register */ +#define SMC_STCR0_LPWIR_POS (2U) +#define SMC_STCR0_LPWIR (0x00000004UL) + +/* Bit definition for SMC_STCR1 register */ +#define SMC_STCR1_LPWOR_POS (2U) +#define SMC_STCR1_LPWOR (0x00000004UL) + +/* Bit definition for SMC_CMDR register */ +#define SMC_CMDR_CMDADD_POS (0U) +#define SMC_CMDR_CMDADD (0x000FFFFFUL) +#define SMC_CMDR_CRES_POS (20U) +#define SMC_CMDR_CRES (0x00100000UL) +#define SMC_CMDR_CMD_POS (21U) +#define SMC_CMDR_CMD (0x00600000UL) +#define SMC_CMDR_CMD_0 (0x00200000UL) +#define SMC_CMDR_CMD_1 (0x00400000UL) +#define SMC_CMDR_CMDCHIP_POS (23U) +#define SMC_CMDR_CMDCHIP (0x03800000UL) + +/* Bit definition for SMC_TMCR register */ +#define SMC_TMCR_T_RC_POS (0U) +#define SMC_TMCR_T_RC (0x0000000FUL) +#define SMC_TMCR_T_WC_POS (4U) +#define SMC_TMCR_T_WC (0x000000F0UL) +#define SMC_TMCR_T_CEOE_POS (8U) +#define SMC_TMCR_T_CEOE (0x00000700UL) +#define SMC_TMCR_T_WP_POS (12U) +#define SMC_TMCR_T_WP (0x00007000UL) +#define SMC_TMCR_T_PC_POS (16U) +#define SMC_TMCR_T_PC (0x00070000UL) +#define SMC_TMCR_T_TR_POS (20U) +#define SMC_TMCR_T_TR (0x00700000UL) + +/* Bit definition for SMC_CPCR register */ +#define SMC_CPCR_RSYN_POS (0U) +#define SMC_CPCR_RSYN (0x00000001UL) +#define SMC_CPCR_RBL_POS (1U) +#define SMC_CPCR_RBL (0x0000000EUL) +#define SMC_CPCR_RBL_0 (0x00000002UL) +#define SMC_CPCR_RBL_1 (0x00000004UL) +#define SMC_CPCR_RBL_2 (0x00000008UL) +#define SMC_CPCR_WSYN_POS (4U) +#define SMC_CPCR_WSYN (0x00000010UL) +#define SMC_CPCR_WBL_POS (5U) +#define SMC_CPCR_WBL (0x000000E0UL) +#define SMC_CPCR_MW_POS (8U) +#define SMC_CPCR_MW (0x00000300UL) +#define SMC_CPCR_MW_0 (0x00000100UL) +#define SMC_CPCR_MW_1 (0x00000200UL) +#define SMC_CPCR_BAAS_POS (10U) +#define SMC_CPCR_BAAS (0x00000400UL) +#define SMC_CPCR_ADVS_POS (11U) +#define SMC_CPCR_ADVS (0x00000800UL) +#define SMC_CPCR_BLSS_POS (12U) +#define SMC_CPCR_BLSS (0x00001000UL) + +/* Bit definition for SMC_RFTR register */ +#define SMC_RFTR_REFPRD (0x0000000FUL) + +/* Bit definition for SMC_TMSR register */ +#define SMC_TMSR_T_RC_POS (0U) +#define SMC_TMSR_T_RC (0x0000000FUL) +#define SMC_TMSR_T_WC_POS (4U) +#define SMC_TMSR_T_WC (0x000000F0UL) +#define SMC_TMSR_T_CEOE_POS (8U) +#define SMC_TMSR_T_CEOE (0x00000700UL) +#define SMC_TMSR_T_WP_POS (12U) +#define SMC_TMSR_T_WP (0x00007000UL) +#define SMC_TMSR_T_PC_POS (16U) +#define SMC_TMSR_T_PC (0x00070000UL) +#define SMC_TMSR_T_TR_POS (20U) +#define SMC_TMSR_T_TR (0x00700000UL) + +/* Bit definition for SMC_CPSR register */ +#define SMC_CPSR_RSYN_POS (0U) +#define SMC_CPSR_RSYN (0x00000001UL) +#define SMC_CPSR_RBL_POS (1U) +#define SMC_CPSR_RBL (0x0000000EUL) +#define SMC_CPSR_WSYN_POS (4U) +#define SMC_CPSR_WSYN (0x00000010UL) +#define SMC_CPSR_WBL_POS (5U) +#define SMC_CPSR_WBL (0x000000E0UL) +#define SMC_CPSR_MW_POS (8U) +#define SMC_CPSR_MW (0x00000300UL) +#define SMC_CPSR_BAAS_POS (10U) +#define SMC_CPSR_BAAS (0x00000400UL) +#define SMC_CPSR_ADVS_POS (11U) +#define SMC_CPSR_ADVS (0x00000800UL) +#define SMC_CPSR_BLSS_POS (12U) +#define SMC_CPSR_BLSS (0x00001000UL) +#define SMC_CPSR_ADDMSK_POS (16U) +#define SMC_CPSR_ADDMSK (0x00FF0000UL) +#define SMC_CPSR_ADDMAT_POS (24U) +#define SMC_CPSR_ADDMAT (0xFF000000UL) + +/* Bit definition for SMC_BACR register */ +#define SMC_BACR_MUXMD_POS (4U) +#define SMC_BACR_MUXMD (0x00000010UL) +#define SMC_BACR_CKSEL_POS (14U) +#define SMC_BACR_CKSEL (0x0000C000UL) +#define SMC_BACR_CKSEL_0 (0x00004000UL) +#define SMC_BACR_CKSEL_1 (0x00008000UL) + +/* Bit definition for SMC_CSCR0 register */ +#define SMC_CSCR0_ADDMSK0_POS (0U) +#define SMC_CSCR0_ADDMSK0 (0x000000FFUL) +#define SMC_CSCR0_ADDMSK1_POS (8U) +#define SMC_CSCR0_ADDMSK1 (0x0000FF00UL) +#define SMC_CSCR0_ADDMSK2_POS (16U) +#define SMC_CSCR0_ADDMSK2 (0x00FF0000UL) +#define SMC_CSCR0_ADDMSK3_POS (24U) +#define SMC_CSCR0_ADDMSK3 (0xFF000000UL) + +/* Bit definition for SMC_CSCR1 register */ +#define SMC_CSCR1_ADDMAT0_POS (0U) +#define SMC_CSCR1_ADDMAT0 (0x000000FFUL) +#define SMC_CSCR1_ADDMAT1_POS (8U) +#define SMC_CSCR1_ADDMAT1 (0x0000FF00UL) +#define SMC_CSCR1_ADDMAT2_POS (16U) +#define SMC_CSCR1_ADDMAT2 (0x00FF0000UL) +#define SMC_CSCR1_ADDMAT3_POS (24U) +#define SMC_CSCR1_ADDMAT3 (0xFF000000UL) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR1 register */ +#define SPI_CR1_SPIMDS_POS (0U) +#define SPI_CR1_SPIMDS (0x00000001UL) +#define SPI_CR1_TXMDS_POS (1U) +#define SPI_CR1_TXMDS (0x00000002UL) +#define SPI_CR1_MSTR_POS (3U) +#define SPI_CR1_MSTR (0x00000008UL) +#define SPI_CR1_SPLPBK_POS (4U) +#define SPI_CR1_SPLPBK (0x00000010UL) +#define SPI_CR1_SPLPBK2_POS (5U) +#define SPI_CR1_SPLPBK2 (0x00000020UL) +#define SPI_CR1_SPE_POS (6U) +#define SPI_CR1_SPE (0x00000040UL) +#define SPI_CR1_CSUSPE_POS (7U) +#define SPI_CR1_CSUSPE (0x00000080UL) +#define SPI_CR1_EIE_POS (8U) +#define SPI_CR1_EIE (0x00000100UL) +#define SPI_CR1_TXIE_POS (9U) +#define SPI_CR1_TXIE (0x00000200UL) +#define SPI_CR1_RXIE_POS (10U) +#define SPI_CR1_RXIE (0x00000400UL) +#define SPI_CR1_IDIE_POS (11U) +#define SPI_CR1_IDIE (0x00000800UL) +#define SPI_CR1_MODFE_POS (12U) +#define SPI_CR1_MODFE (0x00001000UL) +#define SPI_CR1_PATE_POS (13U) +#define SPI_CR1_PATE (0x00002000UL) +#define SPI_CR1_PAOE_POS (14U) +#define SPI_CR1_PAOE (0x00004000UL) +#define SPI_CR1_PAE_POS (15U) +#define SPI_CR1_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSI_0 (0x00100000UL) +#define SPI_CFG1_MSSI_1 (0x00200000UL) +#define SPI_CFG1_MSSI_2 (0x00400000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MSSDL_0 (0x01000000UL) +#define SPI_CFG1_MSSDL_1 (0x02000000UL) +#define SPI_CFG1_MSSDL_2 (0x04000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) +#define SPI_CFG1_MIDI_0 (0x10000000UL) +#define SPI_CFG1_MIDI_1 (0x20000000UL) +#define SPI_CFG1_MIDI_2 (0x40000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000001CUL) +#define SPI_CFG2_MBR_0 (0x00000004UL) +#define SPI_CFG2_MBR_1 (0x00000008UL) +#define SPI_CFG2_MBR_2 (0x00000010UL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_DSIZE_0 (0x00000100UL) +#define SPI_CFG2_DSIZE_1 (0x00000200UL) +#define SPI_CFG2_DSIZE_2 (0x00000400UL) +#define SPI_CFG2_DSIZE_3 (0x00000800UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM123RWT_POS (0U) +#define SRAMC_WTCR_SRAM123RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM123WWT_POS (4U) +#define SRAMC_WTCR_SRAM123WWT (0x00000070UL) +#define SRAMC_WTCR_SRAM4RWT_POS (8U) +#define SRAMC_WTCR_SRAM4RWT (0x00000700UL) +#define SRAMC_WTCR_SRAM4WWT_POS (12U) +#define SRAMC_WTCR_SRAM4WWT (0x00007000UL) +#define SRAMC_WTCR_SRAMHRWT_POS (16U) +#define SRAMC_WTCR_SRAMHRWT (0x00070000UL) +#define SRAMC_WTCR_SRAMHWWT_POS (20U) +#define SRAMC_WTCR_SRAMHWWT (0x00700000UL) +#define SRAMC_WTCR_SRAMBRWT_POS (24U) +#define SRAMC_WTCR_SRAMBRWT (0x07000000UL) +#define SRAMC_WTCR_SRAMBWWT_POS (28U) +#define SRAMC_WTCR_SRAMBWWT (0x70000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_BECCOAD_POS (17U) +#define SRAMC_CKCR_BECCOAD (0x00020000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) +#define SRAMC_CKCR_BECCMOD_POS (26U) +#define SRAMC_CKCR_BECCMOD (0x0C000000UL) +#define SRAMC_CKCR_BECCMOD_0 (0x04000000UL) +#define SRAMC_CKCR_BECCMOD_1 (0x08000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAM1_PYERR_POS (0U) +#define SRAMC_CKSR_SRAM1_PYERR (0x00000001UL) +#define SRAMC_CKSR_SRAM2_PYERR_POS (1U) +#define SRAMC_CKSR_SRAM2_PYERR (0x00000002UL) +#define SRAMC_CKSR_SRAM3_PYERR_POS (2U) +#define SRAMC_CKSR_SRAM3_PYERR (0x00000004UL) +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAM4_1ERR_POS (4U) +#define SRAMC_CKSR_SRAM4_1ERR (0x00000010UL) +#define SRAMC_CKSR_SRAM4_2ERR_POS (5U) +#define SRAMC_CKSR_SRAM4_2ERR (0x00000020UL) +#define SRAMC_CKSR_SRAMB_1ERR_POS (6U) +#define SRAMC_CKSR_SRAMB_1ERR (0x00000040UL) +#define SRAMC_CKSR_SRAMB_2ERR_POS (7U) +#define SRAMC_CKSR_SRAMB_2ERR (0x00000080UL) +#define SRAMC_CKSR_CACHE_PYERR_POS (8U) +#define SRAMC_CKSR_CACHE_PYERR (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_CR register */ +#define SWDT_CR_PERI_POS (0U) +#define SWDT_CR_PERI (0x00000003UL) +#define SWDT_CR_PERI_0 (0x00000001UL) +#define SWDT_CR_PERI_1 (0x00000002UL) +#define SWDT_CR_CKS_POS (4U) +#define SWDT_CR_CKS (0x000000F0UL) +#define SWDT_CR_CKS_0 (0x00000010UL) +#define SWDT_CR_CKS_1 (0x00000020UL) +#define SWDT_CR_CKS_2 (0x00000040UL) +#define SWDT_CR_CKS_3 (0x00000080UL) +#define SWDT_CR_WDPT_POS (8U) +#define SWDT_CR_WDPT (0x00000F00UL) +#define SWDT_CR_WDPT_0 (0x00000100UL) +#define SWDT_CR_WDPT_1 (0x00000200UL) +#define SWDT_CR_WDPT_2 (0x00000400UL) +#define SWDT_CR_WDPT_3 (0x00000800UL) +#define SWDT_CR_SLPOFF_POS (16U) +#define SWDT_CR_SLPOFF (0x00010000UL) +#define SWDT_CR_ITS_POS (31U) +#define SWDT_CR_ITS (0x80000000UL) + +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_INTENA_POS (2U) +#define TMR0_BCONR_INTENA (0x00000004UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_INTENB_POS (18U) +#define TMR0_BCONR_INTENB (0x00040000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR2 +*******************************************************************************/ +/* Bit definition for TMR2_CNTAR register */ +#define TMR2_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR2_CNTBR register */ +#define TMR2_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR2_CMPAR register */ +#define TMR2_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR2_CMPBR register */ +#define TMR2_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR2_BCONR register */ +#define TMR2_BCONR_CSTA_POS (0U) +#define TMR2_BCONR_CSTA (0x00000001UL) +#define TMR2_BCONR_CAPMDA_POS (1U) +#define TMR2_BCONR_CAPMDA (0x00000002UL) +#define TMR2_BCONR_SYNSA_POS (3U) +#define TMR2_BCONR_SYNSA (0x00000008UL) +#define TMR2_BCONR_CKDIVA_POS (4U) +#define TMR2_BCONR_CKDIVA (0x000000F0UL) +#define TMR2_BCONR_SYNCLKA_POS (8U) +#define TMR2_BCONR_SYNCLKA (0x00000300UL) +#define TMR2_BCONR_SYNCLKA_0 (0x00000100UL) +#define TMR2_BCONR_SYNCLKA_1 (0x00000200UL) +#define TMR2_BCONR_ASYNCLKA_POS (10U) +#define TMR2_BCONR_ASYNCLKA (0x00000C00UL) +#define TMR2_BCONR_ASYNCLKA_0 (0x00000400UL) +#define TMR2_BCONR_ASYNCLKA_1 (0x00000800UL) +#define TMR2_BCONR_SYNCLKAT_POS (12U) +#define TMR2_BCONR_SYNCLKAT (0x00003000UL) +#define TMR2_BCONR_SYNCLKAT_0 (0x00001000UL) +#define TMR2_BCONR_SYNCLKAT_1 (0x00002000UL) +#define TMR2_BCONR_CSTB_POS (16U) +#define TMR2_BCONR_CSTB (0x00010000UL) +#define TMR2_BCONR_CAPMDB_POS (17U) +#define TMR2_BCONR_CAPMDB (0x00020000UL) +#define TMR2_BCONR_SYNSB_POS (19U) +#define TMR2_BCONR_SYNSB (0x00080000UL) +#define TMR2_BCONR_CKDIVB_POS (20U) +#define TMR2_BCONR_CKDIVB (0x00F00000UL) +#define TMR2_BCONR_SYNCLKB_POS (24U) +#define TMR2_BCONR_SYNCLKB (0x03000000UL) +#define TMR2_BCONR_SYNCLKB_0 (0x01000000UL) +#define TMR2_BCONR_SYNCLKB_1 (0x02000000UL) +#define TMR2_BCONR_ASYNCLKB_POS (26U) +#define TMR2_BCONR_ASYNCLKB (0x0C000000UL) +#define TMR2_BCONR_ASYNCLKB_0 (0x04000000UL) +#define TMR2_BCONR_ASYNCLKB_1 (0x08000000UL) +#define TMR2_BCONR_SYNCLKBT_POS (28U) +#define TMR2_BCONR_SYNCLKBT (0x30000000UL) +#define TMR2_BCONR_SYNCLKBT_0 (0x10000000UL) +#define TMR2_BCONR_SYNCLKBT_1 (0x20000000UL) + +/* Bit definition for TMR2_ICONR register */ +#define TMR2_ICONR_CMENA_POS (0U) +#define TMR2_ICONR_CMENA (0x00000001UL) +#define TMR2_ICONR_OVENA_POS (1U) +#define TMR2_ICONR_OVENA (0x00000002UL) +#define TMR2_ICONR_CMENB_POS (16U) +#define TMR2_ICONR_CMENB (0x00010000UL) +#define TMR2_ICONR_OVENB_POS (17U) +#define TMR2_ICONR_OVENB (0x00020000UL) + +/* Bit definition for TMR2_PCONR register */ +#define TMR2_PCONR_STACA_POS (0U) +#define TMR2_PCONR_STACA (0x00000003UL) +#define TMR2_PCONR_STACA_0 (0x00000001UL) +#define TMR2_PCONR_STACA_1 (0x00000002UL) +#define TMR2_PCONR_STPCA_POS (2U) +#define TMR2_PCONR_STPCA (0x0000000CUL) +#define TMR2_PCONR_STPCA_0 (0x00000004UL) +#define TMR2_PCONR_STPCA_1 (0x00000008UL) +#define TMR2_PCONR_CMPCA_POS (4U) +#define TMR2_PCONR_CMPCA (0x00000030UL) +#define TMR2_PCONR_CMPCA_0 (0x00000010UL) +#define TMR2_PCONR_CMPCA_1 (0x00000020UL) +#define TMR2_PCONR_OUTENA_POS (8U) +#define TMR2_PCONR_OUTENA (0x00000100UL) +#define TMR2_PCONR_NOFIENA_POS (12U) +#define TMR2_PCONR_NOFIENA (0x00001000UL) +#define TMR2_PCONR_NOFICKA_POS (13U) +#define TMR2_PCONR_NOFICKA (0x00006000UL) +#define TMR2_PCONR_NOFICKA_0 (0x00002000UL) +#define TMR2_PCONR_NOFICKA_1 (0x00004000UL) +#define TMR2_PCONR_STACB_POS (16U) +#define TMR2_PCONR_STACB (0x00030000UL) +#define TMR2_PCONR_STACB_0 (0x00010000UL) +#define TMR2_PCONR_STACB_1 (0x00020000UL) +#define TMR2_PCONR_STPCB_POS (18U) +#define TMR2_PCONR_STPCB (0x000C0000UL) +#define TMR2_PCONR_STPCB_0 (0x00040000UL) +#define TMR2_PCONR_STPCB_1 (0x00080000UL) +#define TMR2_PCONR_CMPCB_POS (20U) +#define TMR2_PCONR_CMPCB (0x00300000UL) +#define TMR2_PCONR_CMPCB_0 (0x00100000UL) +#define TMR2_PCONR_CMPCB_1 (0x00200000UL) +#define TMR2_PCONR_OUTENB_POS (24U) +#define TMR2_PCONR_OUTENB (0x01000000UL) +#define TMR2_PCONR_NOFIENB_POS (28U) +#define TMR2_PCONR_NOFIENB (0x10000000UL) +#define TMR2_PCONR_NOFICKB_POS (29U) +#define TMR2_PCONR_NOFICKB (0x60000000UL) +#define TMR2_PCONR_NOFICKB_0 (0x20000000UL) +#define TMR2_PCONR_NOFICKB_1 (0x40000000UL) + +/* Bit definition for TMR2_HCONR register */ +#define TMR2_HCONR_HSTAA0_POS (0U) +#define TMR2_HCONR_HSTAA0 (0x00000001UL) +#define TMR2_HCONR_HSTAA1_POS (1U) +#define TMR2_HCONR_HSTAA1 (0x00000002UL) +#define TMR2_HCONR_HSTAA2_POS (2U) +#define TMR2_HCONR_HSTAA2 (0x00000004UL) +#define TMR2_HCONR_HSTPA0_POS (4U) +#define TMR2_HCONR_HSTPA0 (0x00000010UL) +#define TMR2_HCONR_HSTPA1_POS (5U) +#define TMR2_HCONR_HSTPA1 (0x00000020UL) +#define TMR2_HCONR_HSTPA2_POS (6U) +#define TMR2_HCONR_HSTPA2 (0x00000040UL) +#define TMR2_HCONR_HCLEA0_POS (8U) +#define TMR2_HCONR_HCLEA0 (0x00000100UL) +#define TMR2_HCONR_HCLEA1_POS (9U) +#define TMR2_HCONR_HCLEA1 (0x00000200UL) +#define TMR2_HCONR_HCLEA2_POS (10U) +#define TMR2_HCONR_HCLEA2 (0x00000400UL) +#define TMR2_HCONR_HICPA0_POS (12U) +#define TMR2_HCONR_HICPA0 (0x00001000UL) +#define TMR2_HCONR_HICPA1_POS (13U) +#define TMR2_HCONR_HICPA1 (0x00002000UL) +#define TMR2_HCONR_HICPA2_POS (14U) +#define TMR2_HCONR_HICPA2 (0x00004000UL) +#define TMR2_HCONR_HSTAB0_POS (16U) +#define TMR2_HCONR_HSTAB0 (0x00010000UL) +#define TMR2_HCONR_HSTAB1_POS (17U) +#define TMR2_HCONR_HSTAB1 (0x00020000UL) +#define TMR2_HCONR_HSTAB2_POS (18U) +#define TMR2_HCONR_HSTAB2 (0x00040000UL) +#define TMR2_HCONR_HSTPB0_POS (20U) +#define TMR2_HCONR_HSTPB0 (0x00100000UL) +#define TMR2_HCONR_HSTPB1_POS (21U) +#define TMR2_HCONR_HSTPB1 (0x00200000UL) +#define TMR2_HCONR_HSTPB2_POS (22U) +#define TMR2_HCONR_HSTPB2 (0x00400000UL) +#define TMR2_HCONR_HCLEB0_POS (24U) +#define TMR2_HCONR_HCLEB0 (0x01000000UL) +#define TMR2_HCONR_HCLEB1_POS (25U) +#define TMR2_HCONR_HCLEB1 (0x02000000UL) +#define TMR2_HCONR_HCLEB2_POS (26U) +#define TMR2_HCONR_HCLEB2 (0x04000000UL) +#define TMR2_HCONR_HICPB0_POS (28U) +#define TMR2_HCONR_HICPB0 (0x10000000UL) +#define TMR2_HCONR_HICPB1_POS (29U) +#define TMR2_HCONR_HICPB1 (0x20000000UL) +#define TMR2_HCONR_HICPB2_POS (30U) +#define TMR2_HCONR_HICPB2 (0x40000000UL) + +/* Bit definition for TMR2_STFLR register */ +#define TMR2_STFLR_CMFA_POS (0U) +#define TMR2_STFLR_CMFA (0x00000001UL) +#define TMR2_STFLR_OVFA_POS (1U) +#define TMR2_STFLR_OVFA (0x00000002UL) +#define TMR2_STFLR_CMFB_POS (16U) +#define TMR2_STFLR_CMFB (0x00010000UL) +#define TMR2_STFLR_OVFB_POS (17U) +#define TMR2_STFLR_OVFB (0x00020000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CKDIV_0 (0x0001U) +#define TMR4_CCSR_CKDIV_1 (0x0002U) +#define TMR4_CCSR_CKDIV_2 (0x0004U) +#define TMR4_CCSR_CKDIV_3 (0x0008U) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (13U) +#define TMR4_CCSR_IRQZEN (0x2000U) +#define TMR4_CCSR_IRQZF_POS (14U) +#define TMR4_CCSR_IRQZF (0x4000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_DIVCK_0 (0x0001U) +#define TMR4_POCR_DIVCK_1 (0x0002U) +#define TMR4_POCR_DIVCK_2 (0x0004U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x0001U) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x0002U) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x0004U) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x0010U) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x0020U) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x0040U) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x0080U) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x0100U) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x0200U) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x0400U) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x0800U) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x1000U) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x2000U) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x4000U) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x8000U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_EVTOS_0 (0x0004U) +#define TMR4_SCSR_EVTOS_1 (0x0008U) +#define TMR4_SCSR_EVTOS_2 (0x0010U) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_PSCR register */ +#define TMR4_PSCR_OEUH_POS (0U) +#define TMR4_PSCR_OEUH (0x00000001UL) +#define TMR4_PSCR_OEUL_POS (1U) +#define TMR4_PSCR_OEUL (0x00000002UL) +#define TMR4_PSCR_OEVH_POS (2U) +#define TMR4_PSCR_OEVH (0x00000004UL) +#define TMR4_PSCR_OEVL_POS (3U) +#define TMR4_PSCR_OEVL (0x00000008UL) +#define TMR4_PSCR_OEWH_POS (4U) +#define TMR4_PSCR_OEWH (0x00000010UL) +#define TMR4_PSCR_OEWL_POS (5U) +#define TMR4_PSCR_OEWL (0x00000020UL) +#define TMR4_PSCR_ODT_POS (6U) +#define TMR4_PSCR_ODT (0x000000C0UL) +#define TMR4_PSCR_ODT_0 (0x00000040UL) +#define TMR4_PSCR_ODT_1 (0x00000080UL) +#define TMR4_PSCR_MOE_POS (8U) +#define TMR4_PSCR_MOE (0x00000100UL) +#define TMR4_PSCR_AOE_POS (9U) +#define TMR4_PSCR_AOE (0x00000200UL) +#define TMR4_PSCR_OSUH_POS (16U) +#define TMR4_PSCR_OSUH (0x00030000UL) +#define TMR4_PSCR_OSUH_0 (0x00010000UL) +#define TMR4_PSCR_OSUH_1 (0x00020000UL) +#define TMR4_PSCR_OSUL_POS (18U) +#define TMR4_PSCR_OSUL (0x000C0000UL) +#define TMR4_PSCR_OSUL_0 (0x00040000UL) +#define TMR4_PSCR_OSUL_1 (0x00080000UL) +#define TMR4_PSCR_OSVH_POS (20U) +#define TMR4_PSCR_OSVH (0x00300000UL) +#define TMR4_PSCR_OSVH_0 (0x00100000UL) +#define TMR4_PSCR_OSVH_1 (0x00200000UL) +#define TMR4_PSCR_OSVL_POS (22U) +#define TMR4_PSCR_OSVL (0x00C00000UL) +#define TMR4_PSCR_OSVL_0 (0x00400000UL) +#define TMR4_PSCR_OSVL_1 (0x00800000UL) +#define TMR4_PSCR_OSWH_POS (24U) +#define TMR4_PSCR_OSWH (0x03000000UL) +#define TMR4_PSCR_OSWH_0 (0x01000000UL) +#define TMR4_PSCR_OSWH_1 (0x02000000UL) +#define TMR4_PSCR_OSWL_POS (26U) +#define TMR4_PSCR_OSWL (0x0C000000UL) +#define TMR4_PSCR_OSWL_0 (0x04000000UL) +#define TMR4_PSCR_OSWL_1 (0x08000000UL) + +/* Bit definition for TMR4_SCER register */ +#define TMR4_SCER_EVTRS_POS (0U) +#define TMR4_SCER_EVTRS (0x0007U) +#define TMR4_SCER_EVTRS_0 (0x0001U) +#define TMR4_SCER_EVTRS_1 (0x0002U) +#define TMR4_SCER_EVTRS_2 (0x0004U) +#define TMR4_SCER_PCTS_POS (3U) +#define TMR4_SCER_PCTS (0x0008U) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_UPDAR register */ +#define TMR6_UPDAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_DIR_POS (1U) +#define TMR6_GCONR_DIR (0x00000002UL) +#define TMR6_GCONR_MODE_POS (2U) +#define TMR6_GCONR_MODE (0x00000004UL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x000000F0UL) +#define TMR6_GCONR_CKDIV_0 (0x00000010UL) +#define TMR6_GCONR_CKDIV_1 (0x00000020UL) +#define TMR6_GCONR_CKDIV_2 (0x00000040UL) +#define TMR6_GCONR_CKDIV_3 (0x00000080UL) +#define TMR6_GCONR_OVSTP_POS (8U) +#define TMR6_GCONR_OVSTP (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BTRUA_POS (2U) +#define TMR6_BCONR_BTRUA (0x00000004UL) +#define TMR6_BCONR_BTRDA_POS (3U) +#define TMR6_BCONR_BTRDA (0x00000008UL) +#define TMR6_BCONR_BENB_POS (4U) +#define TMR6_BCONR_BENB (0x00000010UL) +#define TMR6_BCONR_BSEB_POS (5U) +#define TMR6_BCONR_BSEB (0x00000020UL) +#define TMR6_BCONR_BTRUB_POS (6U) +#define TMR6_BCONR_BTRUB (0x00000040UL) +#define TMR6_BCONR_BTRDB_POS (7U) +#define TMR6_BCONR_BTRDB (0x00000080UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BTRUP_POS (10U) +#define TMR6_BCONR_BTRUP (0x00000400UL) +#define TMR6_BCONR_BTRDP_POS (11U) +#define TMR6_BCONR_BTRDP (0x00000800UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (18U) +#define TMR6_BCONR_BTRUSPA (0x00040000UL) +#define TMR6_BCONR_BTRDSPA_POS (19U) +#define TMR6_BCONR_BTRDSPA (0x00080000UL) +#define TMR6_BCONR_BENSPB_POS (20U) +#define TMR6_BCONR_BENSPB (0x00100000UL) +#define TMR6_BCONR_BSESPB_POS (21U) +#define TMR6_BCONR_BSESPB (0x00200000UL) +#define TMR6_BCONR_BTRUSPB_POS (22U) +#define TMR6_BCONR_BTRUSPB (0x00400000UL) +#define TMR6_BCONR_BTRDSPB_POS (23U) +#define TMR6_BCONR_BTRDSPB (0x00800000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_SEPA_POS (1U) +#define TMR6_DCONR_SEPA (0x00000002UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_DTBTRU_POS (6U) +#define TMR6_DCONR_DTBTRU (0x00000040UL) +#define TMR6_DCONR_DTBTRD_POS (7U) +#define TMR6_DCONR_DTBTRD (0x00000080UL) + +/* Bit definition for TMR6_PCNAR register */ +#define TMR6_PCNAR_STACA_POS (0U) +#define TMR6_PCNAR_STACA (0x00000003UL) +#define TMR6_PCNAR_STACA_0 (0x00000001UL) +#define TMR6_PCNAR_STACA_1 (0x00000002UL) +#define TMR6_PCNAR_STPCA_POS (2U) +#define TMR6_PCNAR_STPCA (0x0000000CUL) +#define TMR6_PCNAR_STPCA_0 (0x00000004UL) +#define TMR6_PCNAR_STPCA_1 (0x00000008UL) +#define TMR6_PCNAR_OVFCA_POS (4U) +#define TMR6_PCNAR_OVFCA (0x00000030UL) +#define TMR6_PCNAR_OVFCA_0 (0x00000010UL) +#define TMR6_PCNAR_OVFCA_1 (0x00000020UL) +#define TMR6_PCNAR_UDFCA_POS (6U) +#define TMR6_PCNAR_UDFCA (0x000000C0UL) +#define TMR6_PCNAR_UDFCA_0 (0x00000040UL) +#define TMR6_PCNAR_UDFCA_1 (0x00000080UL) +#define TMR6_PCNAR_CMAUCA_POS (8U) +#define TMR6_PCNAR_CMAUCA (0x00000300UL) +#define TMR6_PCNAR_CMAUCA_0 (0x00000100UL) +#define TMR6_PCNAR_CMAUCA_1 (0x00000200UL) +#define TMR6_PCNAR_CMADCA_POS (10U) +#define TMR6_PCNAR_CMADCA (0x00000C00UL) +#define TMR6_PCNAR_CMADCA_0 (0x00000400UL) +#define TMR6_PCNAR_CMADCA_1 (0x00000800UL) +#define TMR6_PCNAR_CMBUCA_POS (12U) +#define TMR6_PCNAR_CMBUCA (0x00003000UL) +#define TMR6_PCNAR_CMBUCA_0 (0x00001000UL) +#define TMR6_PCNAR_CMBUCA_1 (0x00002000UL) +#define TMR6_PCNAR_CMBDCA_POS (14U) +#define TMR6_PCNAR_CMBDCA (0x0000C000UL) +#define TMR6_PCNAR_CMBDCA_0 (0x00004000UL) +#define TMR6_PCNAR_CMBDCA_1 (0x00008000UL) +#define TMR6_PCNAR_FORCA_POS (16U) +#define TMR6_PCNAR_FORCA (0x00030000UL) +#define TMR6_PCNAR_FORCA_0 (0x00010000UL) +#define TMR6_PCNAR_FORCA_1 (0x00020000UL) +#define TMR6_PCNAR_EMBCA_POS (20U) +#define TMR6_PCNAR_EMBCA (0x00300000UL) +#define TMR6_PCNAR_EMBCA_0 (0x00100000UL) +#define TMR6_PCNAR_EMBCA_1 (0x00200000UL) +#define TMR6_PCNAR_EMBRA_POS (22U) +#define TMR6_PCNAR_EMBRA (0x00C00000UL) +#define TMR6_PCNAR_EMBRA_0 (0x00400000UL) +#define TMR6_PCNAR_EMBRA_1 (0x00800000UL) +#define TMR6_PCNAR_EMBSA_POS (24U) +#define TMR6_PCNAR_EMBSA (0x03000000UL) +#define TMR6_PCNAR_EMBSA_0 (0x01000000UL) +#define TMR6_PCNAR_EMBSA_1 (0x02000000UL) +#define TMR6_PCNAR_OUTENA_POS (28U) +#define TMR6_PCNAR_OUTENA (0x10000000UL) +#define TMR6_PCNAR_CAPMDA_POS (31U) +#define TMR6_PCNAR_CAPMDA (0x80000000UL) + +/* Bit definition for TMR6_PCNBR register */ +#define TMR6_PCNBR_STACB_POS (0U) +#define TMR6_PCNBR_STACB (0x00000003UL) +#define TMR6_PCNBR_STACB_0 (0x00000001UL) +#define TMR6_PCNBR_STACB_1 (0x00000002UL) +#define TMR6_PCNBR_STPCB_POS (2U) +#define TMR6_PCNBR_STPCB (0x0000000CUL) +#define TMR6_PCNBR_STPCB_0 (0x00000004UL) +#define TMR6_PCNBR_STPCB_1 (0x00000008UL) +#define TMR6_PCNBR_OVFCB_POS (4U) +#define TMR6_PCNBR_OVFCB (0x00000030UL) +#define TMR6_PCNBR_OVFCB_0 (0x00000010UL) +#define TMR6_PCNBR_OVFCB_1 (0x00000020UL) +#define TMR6_PCNBR_UDFCB_POS (6U) +#define TMR6_PCNBR_UDFCB (0x000000C0UL) +#define TMR6_PCNBR_UDFCB_0 (0x00000040UL) +#define TMR6_PCNBR_UDFCB_1 (0x00000080UL) +#define TMR6_PCNBR_CMAUCB_POS (8U) +#define TMR6_PCNBR_CMAUCB (0x00000300UL) +#define TMR6_PCNBR_CMAUCB_0 (0x00000100UL) +#define TMR6_PCNBR_CMAUCB_1 (0x00000200UL) +#define TMR6_PCNBR_CMADCB_POS (10U) +#define TMR6_PCNBR_CMADCB (0x00000C00UL) +#define TMR6_PCNBR_CMADCB_0 (0x00000400UL) +#define TMR6_PCNBR_CMADCB_1 (0x00000800UL) +#define TMR6_PCNBR_CMBUCB_POS (12U) +#define TMR6_PCNBR_CMBUCB (0x00003000UL) +#define TMR6_PCNBR_CMBUCB_0 (0x00001000UL) +#define TMR6_PCNBR_CMBUCB_1 (0x00002000UL) +#define TMR6_PCNBR_CMBDCB_POS (14U) +#define TMR6_PCNBR_CMBDCB (0x0000C000UL) +#define TMR6_PCNBR_CMBDCB_0 (0x00004000UL) +#define TMR6_PCNBR_CMBDCB_1 (0x00008000UL) +#define TMR6_PCNBR_FORCB_POS (16U) +#define TMR6_PCNBR_FORCB (0x00030000UL) +#define TMR6_PCNBR_FORCB_0 (0x00010000UL) +#define TMR6_PCNBR_FORCB_1 (0x00020000UL) +#define TMR6_PCNBR_EMBCB_POS (20U) +#define TMR6_PCNBR_EMBCB (0x00300000UL) +#define TMR6_PCNBR_EMBCB_0 (0x00100000UL) +#define TMR6_PCNBR_EMBCB_1 (0x00200000UL) +#define TMR6_PCNBR_EMBRB_POS (22U) +#define TMR6_PCNBR_EMBRB (0x00C00000UL) +#define TMR6_PCNBR_EMBRB_0 (0x00400000UL) +#define TMR6_PCNBR_EMBRB_1 (0x00800000UL) +#define TMR6_PCNBR_EMBSB_POS (24U) +#define TMR6_PCNBR_EMBSB (0x03000000UL) +#define TMR6_PCNBR_EMBSB_0 (0x01000000UL) +#define TMR6_PCNBR_EMBSB_1 (0x02000000UL) +#define TMR6_PCNBR_OUTENB_POS (28U) +#define TMR6_PCNBR_OUTENB (0x10000000UL) +#define TMR6_PCNBR_CAPMDB_POS (31U) +#define TMR6_PCNBR_CAPMDB (0x80000000UL) + +/* Bit definition for TMR6_FCNGR register */ +#define TMR6_FCNGR_NOFIENGA_POS (0U) +#define TMR6_FCNGR_NOFIENGA (0x00000001UL) +#define TMR6_FCNGR_NOFICKGA_POS (1U) +#define TMR6_FCNGR_NOFICKGA (0x00000006UL) +#define TMR6_FCNGR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCNGR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCNGR_NOFIENGB_POS (4U) +#define TMR6_FCNGR_NOFIENGB (0x00000010UL) +#define TMR6_FCNGR_NOFICKGB_POS (5U) +#define TMR6_FCNGR_NOFICKGB (0x00000060UL) +#define TMR6_FCNGR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCNGR_NOFICKGB_1 (0x00000040UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) +#define TMR6_VPERR_PCNTS_0 (0x00040000UL) +#define TMR6_VPERR_PCNTS_1 (0x00080000UL) +#define TMR6_VPERR_PCNTS_2 (0x00100000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_VPERNUM_0 (0x00200000UL) +#define TMR6_STFLR_VPERNUM_1 (0x00400000UL) +#define TMR6_STFLR_VPERNUM_2 (0x00800000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA2_POS (2U) +#define TMR6_HSTAR_HSTA2 (0x00000004UL) +#define TMR6_HSTAR_HSTA3_POS (3U) +#define TMR6_HSTAR_HSTA3 (0x00000008UL) +#define TMR6_HSTAR_STAS_POS (7U) +#define TMR6_HSTAR_STAS (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA10_POS (10U) +#define TMR6_HSTAR_HSTA10 (0x00000400UL) +#define TMR6_HSTAR_HSTA11_POS (11U) +#define TMR6_HSTAR_HSTA11 (0x00000800UL) +#define TMR6_HSTAR_HSTA16_POS (16U) +#define TMR6_HSTAR_HSTA16 (0x00010000UL) +#define TMR6_HSTAR_HSTA17_POS (17U) +#define TMR6_HSTAR_HSTA17 (0x00020000UL) +#define TMR6_HSTAR_HSTA18_POS (18U) +#define TMR6_HSTAR_HSTA18 (0x00040000UL) +#define TMR6_HSTAR_HSTA19_POS (19U) +#define TMR6_HSTAR_HSTA19 (0x00080000UL) +#define TMR6_HSTAR_HSTA20_POS (20U) +#define TMR6_HSTAR_HSTA20 (0x00100000UL) +#define TMR6_HSTAR_HSTA21_POS (21U) +#define TMR6_HSTAR_HSTA21 (0x00200000UL) +#define TMR6_HSTAR_HSTA22_POS (22U) +#define TMR6_HSTAR_HSTA22 (0x00400000UL) +#define TMR6_HSTAR_HSTA23_POS (23U) +#define TMR6_HSTAR_HSTA23 (0x00800000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP2_POS (2U) +#define TMR6_HSTPR_HSTP2 (0x00000004UL) +#define TMR6_HSTPR_HSTP3_POS (3U) +#define TMR6_HSTPR_HSTP3 (0x00000008UL) +#define TMR6_HSTPR_STPS_POS (7U) +#define TMR6_HSTPR_STPS (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP10_POS (10U) +#define TMR6_HSTPR_HSTP10 (0x00000400UL) +#define TMR6_HSTPR_HSTP11_POS (11U) +#define TMR6_HSTPR_HSTP11 (0x00000800UL) +#define TMR6_HSTPR_HSTP16_POS (16U) +#define TMR6_HSTPR_HSTP16 (0x00010000UL) +#define TMR6_HSTPR_HSTP17_POS (17U) +#define TMR6_HSTPR_HSTP17 (0x00020000UL) +#define TMR6_HSTPR_HSTP18_POS (18U) +#define TMR6_HSTPR_HSTP18 (0x00040000UL) +#define TMR6_HSTPR_HSTP19_POS (19U) +#define TMR6_HSTPR_HSTP19 (0x00080000UL) +#define TMR6_HSTPR_HSTP20_POS (20U) +#define TMR6_HSTPR_HSTP20 (0x00100000UL) +#define TMR6_HSTPR_HSTP21_POS (21U) +#define TMR6_HSTPR_HSTP21 (0x00200000UL) +#define TMR6_HSTPR_HSTP22_POS (22U) +#define TMR6_HSTPR_HSTP22 (0x00400000UL) +#define TMR6_HSTPR_HSTP23_POS (23U) +#define TMR6_HSTPR_HSTP23 (0x00800000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE2_POS (2U) +#define TMR6_HCLRR_HCLE2 (0x00000004UL) +#define TMR6_HCLRR_HCLE3_POS (3U) +#define TMR6_HCLRR_HCLE3 (0x00000008UL) +#define TMR6_HCLRR_CLES_POS (7U) +#define TMR6_HCLRR_CLES (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE10_POS (10U) +#define TMR6_HCLRR_HCLE10 (0x00000400UL) +#define TMR6_HCLRR_HCLE11_POS (11U) +#define TMR6_HCLRR_HCLE11 (0x00000800UL) +#define TMR6_HCLRR_HCLE16_POS (16U) +#define TMR6_HCLRR_HCLE16 (0x00010000UL) +#define TMR6_HCLRR_HCLE17_POS (17U) +#define TMR6_HCLRR_HCLE17 (0x00020000UL) +#define TMR6_HCLRR_HCLE18_POS (18U) +#define TMR6_HCLRR_HCLE18 (0x00040000UL) +#define TMR6_HCLRR_HCLE19_POS (19U) +#define TMR6_HCLRR_HCLE19 (0x00080000UL) +#define TMR6_HCLRR_HCLE20_POS (20U) +#define TMR6_HCLRR_HCLE20 (0x00100000UL) +#define TMR6_HCLRR_HCLE21_POS (21U) +#define TMR6_HCLRR_HCLE21 (0x00200000UL) +#define TMR6_HCLRR_HCLE22_POS (22U) +#define TMR6_HCLRR_HCLE22 (0x00400000UL) +#define TMR6_HCLRR_HCLE23_POS (23U) +#define TMR6_HCLRR_HCLE23 (0x00800000UL) + +/* Bit definition for TMR6_HUPDR register */ +#define TMR6_HUPDR_HUPD0_POS (0U) +#define TMR6_HUPDR_HUPD0 (0x00000001UL) +#define TMR6_HUPDR_HUPD1_POS (1U) +#define TMR6_HUPDR_HUPD1 (0x00000002UL) +#define TMR6_HUPDR_HUPD2_POS (2U) +#define TMR6_HUPDR_HUPD2 (0x00000004UL) +#define TMR6_HUPDR_HUPD3_POS (3U) +#define TMR6_HUPDR_HUPD3 (0x00000008UL) +#define TMR6_HUPDR_UPDS_POS (7U) +#define TMR6_HUPDR_UPDS (0x00000080UL) +#define TMR6_HUPDR_HUPD8_POS (8U) +#define TMR6_HUPDR_HUPD8 (0x00000100UL) +#define TMR6_HUPDR_HUPD9_POS (9U) +#define TMR6_HUPDR_HUPD9 (0x00000200UL) +#define TMR6_HUPDR_HUPD10_POS (10U) +#define TMR6_HUPDR_HUPD10 (0x00000400UL) +#define TMR6_HUPDR_HUPD11_POS (11U) +#define TMR6_HUPDR_HUPD11 (0x00000800UL) +#define TMR6_HUPDR_HUPD16_POS (16U) +#define TMR6_HUPDR_HUPD16 (0x00010000UL) +#define TMR6_HUPDR_HUPD17_POS (17U) +#define TMR6_HUPDR_HUPD17 (0x00020000UL) +#define TMR6_HUPDR_HUPD18_POS (18U) +#define TMR6_HUPDR_HUPD18 (0x00040000UL) +#define TMR6_HUPDR_HUPD19_POS (19U) +#define TMR6_HUPDR_HUPD19 (0x00080000UL) +#define TMR6_HUPDR_HUPD20_POS (20U) +#define TMR6_HUPDR_HUPD20 (0x00100000UL) +#define TMR6_HUPDR_HUPD21_POS (21U) +#define TMR6_HUPDR_HUPD21 (0x00200000UL) +#define TMR6_HUPDR_HUPD22_POS (22U) +#define TMR6_HUPDR_HUPD22 (0x00400000UL) +#define TMR6_HUPDR_HUPD23_POS (23U) +#define TMR6_HUPDR_HUPD23 (0x00800000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA2_POS (2U) +#define TMR6_HCPAR_HCPA2 (0x00000004UL) +#define TMR6_HCPAR_HCPA3_POS (3U) +#define TMR6_HCPAR_HCPA3 (0x00000008UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA10_POS (10U) +#define TMR6_HCPAR_HCPA10 (0x00000400UL) +#define TMR6_HCPAR_HCPA11_POS (11U) +#define TMR6_HCPAR_HCPA11 (0x00000800UL) +#define TMR6_HCPAR_HCPA16_POS (16U) +#define TMR6_HCPAR_HCPA16 (0x00010000UL) +#define TMR6_HCPAR_HCPA17_POS (17U) +#define TMR6_HCPAR_HCPA17 (0x00020000UL) +#define TMR6_HCPAR_HCPA18_POS (18U) +#define TMR6_HCPAR_HCPA18 (0x00040000UL) +#define TMR6_HCPAR_HCPA19_POS (19U) +#define TMR6_HCPAR_HCPA19 (0x00080000UL) +#define TMR6_HCPAR_HCPA20_POS (20U) +#define TMR6_HCPAR_HCPA20 (0x00100000UL) +#define TMR6_HCPAR_HCPA21_POS (21U) +#define TMR6_HCPAR_HCPA21 (0x00200000UL) +#define TMR6_HCPAR_HCPA22_POS (22U) +#define TMR6_HCPAR_HCPA22 (0x00400000UL) +#define TMR6_HCPAR_HCPA23_POS (23U) +#define TMR6_HCPAR_HCPA23 (0x00800000UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB2_POS (2U) +#define TMR6_HCPBR_HCPB2 (0x00000004UL) +#define TMR6_HCPBR_HCPB3_POS (3U) +#define TMR6_HCPBR_HCPB3 (0x00000008UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB10_POS (10U) +#define TMR6_HCPBR_HCPB10 (0x00000400UL) +#define TMR6_HCPBR_HCPB11_POS (11U) +#define TMR6_HCPBR_HCPB11 (0x00000800UL) +#define TMR6_HCPBR_HCPB16_POS (16U) +#define TMR6_HCPBR_HCPB16 (0x00010000UL) +#define TMR6_HCPBR_HCPB17_POS (17U) +#define TMR6_HCPBR_HCPB17 (0x00020000UL) +#define TMR6_HCPBR_HCPB18_POS (18U) +#define TMR6_HCPBR_HCPB18 (0x00040000UL) +#define TMR6_HCPBR_HCPB19_POS (19U) +#define TMR6_HCPBR_HCPB19 (0x00080000UL) +#define TMR6_HCPBR_HCPB20_POS (20U) +#define TMR6_HCPBR_HCPB20 (0x00100000UL) +#define TMR6_HCPBR_HCPB21_POS (21U) +#define TMR6_HCPBR_HCPB21 (0x00200000UL) +#define TMR6_HCPBR_HCPB22_POS (22U) +#define TMR6_HCPBR_HCPB22 (0x00400000UL) +#define TMR6_HCPBR_HCPB23_POS (23U) +#define TMR6_HCPBR_HCPB23 (0x00800000UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP10_POS (10U) +#define TMR6_HCUPR_HCUP10 (0x00000400UL) +#define TMR6_HCUPR_HCUP11_POS (11U) +#define TMR6_HCUPR_HCUP11 (0x00000800UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) +#define TMR6_HCUPR_HCUP18_POS (18U) +#define TMR6_HCUPR_HCUP18 (0x00040000UL) +#define TMR6_HCUPR_HCUP19_POS (19U) +#define TMR6_HCUPR_HCUP19 (0x00080000UL) +#define TMR6_HCUPR_HCUP20_POS (20U) +#define TMR6_HCUPR_HCUP20 (0x00100000UL) +#define TMR6_HCUPR_HCUP21_POS (21U) +#define TMR6_HCUPR_HCUP21 (0x00200000UL) +#define TMR6_HCUPR_HCUP22_POS (22U) +#define TMR6_HCUPR_HCUP22 (0x00400000UL) +#define TMR6_HCUPR_HCUP23_POS (23U) +#define TMR6_HCUPR_HCUP23 (0x00800000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO10_POS (10U) +#define TMR6_HCDOR_HCDO10 (0x00000400UL) +#define TMR6_HCDOR_HCDO11_POS (11U) +#define TMR6_HCDOR_HCDO11 (0x00000800UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) +#define TMR6_HCDOR_HCDO18_POS (18U) +#define TMR6_HCDOR_HCDO18 (0x00040000UL) +#define TMR6_HCDOR_HCDO19_POS (19U) +#define TMR6_HCDOR_HCDO19 (0x00080000UL) +#define TMR6_HCDOR_HCDO20_POS (20U) +#define TMR6_HCDOR_HCDO20 (0x00100000UL) +#define TMR6_HCDOR_HCDO21_POS (21U) +#define TMR6_HCDOR_HCDO21 (0x00200000UL) +#define TMR6_HCDOR_HCDO22_POS (22U) +#define TMR6_HCDOR_HCDO22 (0x00400000UL) +#define TMR6_HCDOR_HCDO23_POS (23U) +#define TMR6_HCDOR_HCDO23 (0x00800000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6CR +*******************************************************************************/ +/* Bit definition for TMR6CR_FCNTR register */ +#define TMR6CR_FCNTR_NOFIENTA_POS (0U) +#define TMR6CR_FCNTR_NOFIENTA (0x00000001UL) +#define TMR6CR_FCNTR_NOFICKTA_POS (1U) +#define TMR6CR_FCNTR_NOFICKTA (0x00000006UL) +#define TMR6CR_FCNTR_NOFICKTA_0 (0x00000002UL) +#define TMR6CR_FCNTR_NOFICKTA_1 (0x00000004UL) +#define TMR6CR_FCNTR_NOFIENTB_POS (4U) +#define TMR6CR_FCNTR_NOFIENTB (0x00000010UL) +#define TMR6CR_FCNTR_NOFICKTB_POS (5U) +#define TMR6CR_FCNTR_NOFICKTB (0x00000060UL) +#define TMR6CR_FCNTR_NOFICKTB_0 (0x00000020UL) +#define TMR6CR_FCNTR_NOFICKTB_1 (0x00000040UL) +#define TMR6CR_FCNTR_NOFIENTC_POS (8U) +#define TMR6CR_FCNTR_NOFIENTC (0x00000100UL) +#define TMR6CR_FCNTR_NOFICKTC_POS (9U) +#define TMR6CR_FCNTR_NOFICKTC (0x00000600UL) +#define TMR6CR_FCNTR_NOFICKTC_0 (0x00000200UL) +#define TMR6CR_FCNTR_NOFICKTC_1 (0x00000400UL) +#define TMR6CR_FCNTR_NOFIENTD_POS (12U) +#define TMR6CR_FCNTR_NOFIENTD (0x00001000UL) +#define TMR6CR_FCNTR_NOFICKTD_POS (13U) +#define TMR6CR_FCNTR_NOFICKTD (0x00006000UL) +#define TMR6CR_FCNTR_NOFICKTD_0 (0x00002000UL) +#define TMR6CR_FCNTR_NOFICKTD_1 (0x00004000UL) + +/* Bit definition for TMR6CR_SSTAR register */ +#define TMR6CR_SSTAR_SSTA1_POS (0U) +#define TMR6CR_SSTAR_SSTA1 (0x00000001UL) +#define TMR6CR_SSTAR_SSTA2_POS (1U) +#define TMR6CR_SSTAR_SSTA2 (0x00000002UL) +#define TMR6CR_SSTAR_SSTA3_POS (2U) +#define TMR6CR_SSTAR_SSTA3 (0x00000004UL) +#define TMR6CR_SSTAR_SSTA4_POS (3U) +#define TMR6CR_SSTAR_SSTA4 (0x00000008UL) +#define TMR6CR_SSTAR_SSTA5_POS (4U) +#define TMR6CR_SSTAR_SSTA5 (0x00000010UL) +#define TMR6CR_SSTAR_SSTA6_POS (5U) +#define TMR6CR_SSTAR_SSTA6 (0x00000020UL) +#define TMR6CR_SSTAR_SSTA7_POS (6U) +#define TMR6CR_SSTAR_SSTA7 (0x00000040UL) +#define TMR6CR_SSTAR_SSTA8_POS (7U) +#define TMR6CR_SSTAR_SSTA8 (0x00000080UL) + +/* Bit definition for TMR6CR_SSTPR register */ +#define TMR6CR_SSTPR_SSTP1_POS (0U) +#define TMR6CR_SSTPR_SSTP1 (0x00000001UL) +#define TMR6CR_SSTPR_SSTP2_POS (1U) +#define TMR6CR_SSTPR_SSTP2 (0x00000002UL) +#define TMR6CR_SSTPR_SSTP3_POS (2U) +#define TMR6CR_SSTPR_SSTP3 (0x00000004UL) +#define TMR6CR_SSTPR_SSTP4_POS (3U) +#define TMR6CR_SSTPR_SSTP4 (0x00000008UL) +#define TMR6CR_SSTPR_SSTP5_POS (4U) +#define TMR6CR_SSTPR_SSTP5 (0x00000010UL) +#define TMR6CR_SSTPR_SSTP6_POS (5U) +#define TMR6CR_SSTPR_SSTP6 (0x00000020UL) +#define TMR6CR_SSTPR_SSTP7_POS (6U) +#define TMR6CR_SSTPR_SSTP7 (0x00000040UL) +#define TMR6CR_SSTPR_SSTP8_POS (7U) +#define TMR6CR_SSTPR_SSTP8 (0x00000080UL) + +/* Bit definition for TMR6CR_SCLRR register */ +#define TMR6CR_SCLRR_SCLE1_POS (0U) +#define TMR6CR_SCLRR_SCLE1 (0x00000001UL) +#define TMR6CR_SCLRR_SCLE2_POS (1U) +#define TMR6CR_SCLRR_SCLE2 (0x00000002UL) +#define TMR6CR_SCLRR_SCLE3_POS (2U) +#define TMR6CR_SCLRR_SCLE3 (0x00000004UL) +#define TMR6CR_SCLRR_SCLE4_POS (3U) +#define TMR6CR_SCLRR_SCLE4 (0x00000008UL) +#define TMR6CR_SCLRR_SCLE5_POS (4U) +#define TMR6CR_SCLRR_SCLE5 (0x00000010UL) +#define TMR6CR_SCLRR_SCLE6_POS (5U) +#define TMR6CR_SCLRR_SCLE6 (0x00000020UL) +#define TMR6CR_SCLRR_SCLE7_POS (6U) +#define TMR6CR_SCLRR_SCLE7 (0x00000040UL) +#define TMR6CR_SCLRR_SCLE8_POS (7U) +#define TMR6CR_SCLRR_SCLE8 (0x00000080UL) + +/* Bit definition for TMR6CR_SUPDR register */ +#define TMR6CR_SUPDR_SUPD1_POS (0U) +#define TMR6CR_SUPDR_SUPD1 (0x00000001UL) +#define TMR6CR_SUPDR_SUPD2_POS (1U) +#define TMR6CR_SUPDR_SUPD2 (0x00000002UL) +#define TMR6CR_SUPDR_SUPD3_POS (2U) +#define TMR6CR_SUPDR_SUPD3 (0x00000004UL) +#define TMR6CR_SUPDR_SUPD4_POS (3U) +#define TMR6CR_SUPDR_SUPD4 (0x00000008UL) +#define TMR6CR_SUPDR_SUPD5_POS (4U) +#define TMR6CR_SUPDR_SUPD5 (0x00000010UL) +#define TMR6CR_SUPDR_SUPD6_POS (5U) +#define TMR6CR_SUPDR_SUPD6 (0x00000020UL) +#define TMR6CR_SUPDR_SUPD7_POS (6U) +#define TMR6CR_SUPDR_SUPD7 (0x00000040UL) +#define TMR6CR_SUPDR_SUPD8_POS (7U) +#define TMR6CR_SUPDR_SUPD8 (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0xFFFFU) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0xFFFFU) + +/* Bit definition for TMRA_CMPAR register */ +#define TMRA_CMPAR_CMP (0xFFFFU) + +/* Bit definition for TMRA_BCSTR register */ +#define TMRA_BCSTR_START_POS (0U) +#define TMRA_BCSTR_START (0x0001U) +#define TMRA_BCSTR_DIR_POS (1U) +#define TMRA_BCSTR_DIR (0x0002U) +#define TMRA_BCSTR_MODE_POS (2U) +#define TMRA_BCSTR_MODE (0x0004U) +#define TMRA_BCSTR_SYNST_POS (3U) +#define TMRA_BCSTR_SYNST (0x0008U) +#define TMRA_BCSTR_CKDIV_POS (4U) +#define TMRA_BCSTR_CKDIV (0x00F0U) +#define TMRA_BCSTR_OVSTP_POS (8U) +#define TMRA_BCSTR_OVSTP (0x0100U) +#define TMRA_BCSTR_ITENOVF_POS (12U) +#define TMRA_BCSTR_ITENOVF (0x1000U) +#define TMRA_BCSTR_ITENUDF_POS (13U) +#define TMRA_BCSTR_ITENUDF (0x2000U) +#define TMRA_BCSTR_OVFF_POS (14U) +#define TMRA_BCSTR_OVFF (0x4000U) +#define TMRA_BCSTR_UDFF_POS (15U) +#define TMRA_BCSTR_UDFF (0x8000U) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x0001U) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x0002U) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x0004U) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x0010U) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x0020U) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x0040U) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x0100U) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x0200U) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x0400U) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x1000U) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x2000U) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x4000U) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x8000U) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x0001U) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x0002U) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x0004U) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x0008U) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x0010U) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x0020U) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x0040U) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x0080U) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x0100U) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x0200U) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x0400U) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x0800U) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x1000U) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x0001U) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x0002U) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x0004U) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x0008U) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x0010U) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x0020U) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x0040U) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x0080U) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x0100U) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x0200U) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x0400U) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x0800U) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x1000U) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x0001U) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x0002U) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x0004U) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x0008U) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x0001U) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x0002U) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x0004U) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x0008U) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x0001U) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x0006U) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x0100U) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x0600U) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x1000U) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x6000U) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x0001U) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x0002U) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x0004U) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x0008U) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x0001U) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x0002U) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x0004U) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x0001U) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x0010U) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x0020U) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x0040U) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x0100U) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x0200U) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x1000U) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x6000U) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x0003U) +#define TMRA_PCONR_STAC_0 (0x0001U) +#define TMRA_PCONR_STAC_1 (0x0002U) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x000CU) +#define TMRA_PCONR_STPC_0 (0x0004U) +#define TMRA_PCONR_STPC_1 (0x0008U) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x0030U) +#define TMRA_PCONR_CMPC_0 (0x0010U) +#define TMRA_PCONR_CMPC_1 (0x0020U) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x00C0U) +#define TMRA_PCONR_PERC_0 (0x0040U) +#define TMRA_PCONR_PERC_1 (0x0080U) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x0300U) +#define TMRA_PCONR_FORC_0 (0x0100U) +#define TMRA_PCONR_FORC_1 (0x0200U) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x1000U) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_BE_POS (4U) +#define USART_SR_BE (0x00000010UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_WKUP_POS (9U) +#define USART_SR_WKUP (0x00000200UL) +#define USART_SR_LBD_POS (10U) +#define USART_SR_LBD (0x00000400UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_DR register */ +#define USART_DR_TDR_POS (0U) +#define USART_DR_TDR (0x000001FFUL) +#define USART_DR_MPID_POS (9U) +#define USART_DR_MPID (0x00000200UL) +#define USART_DR_RDR_POS (16U) +#define USART_DR_RDR (0x01FF0000UL) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_CBE_POS (21U) +#define USART_CR1_CBE (0x00200000UL) +#define USART_CR1_CWKUP_POS (22U) +#define USART_CR1_CWKUP (0x00400000UL) +#define USART_CR1_CLBD_POS (23U) +#define USART_CR1_CLBD (0x00800000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_WKUPIE_POS (1U) +#define USART_CR2_WKUPIE (0x00000002UL) +#define USART_CR2_BEIE_POS (2U) +#define USART_CR2_BEIE (0x00000004UL) +#define USART_CR2_BEE_POS (3U) +#define USART_CR2_BEE (0x00000008UL) +#define USART_CR2_LBDIE_POS (4U) +#define USART_CR2_LBDIE (0x00000010UL) +#define USART_CR2_LBDL_POS (5U) +#define USART_CR2_LBDL (0x00000020UL) +#define USART_CR2_SBKL_POS (6U) +#define USART_CR2_SBKL (0x000000C0UL) +#define USART_CR2_SBKL_0 (0x00000040UL) +#define USART_CR2_SBKL_1 (0x00000080UL) +#define USART_CR2_WKUPE_POS (8U) +#define USART_CR2_WKUPE (0x00000100UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) +#define USART_CR2_LINEN_POS (14U) +#define USART_CR2_LINEN (0x00004000UL) +#define USART_CR2_SBK_POS (16U) +#define USART_CR2_SBK (0x00010000UL) +#define USART_CR2_SBKM_POS (17U) +#define USART_CR2_SBKM (0x00020000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_HDSEL_POS (3U) +#define USART_CR3_HDSEL (0x00000008UL) +#define USART_CR3_LOOP_POS (4U) +#define USART_CR3_LOOP (0x00000010UL) +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_RTSE_POS (8U) +#define USART_CR3_RTSE (0x00000100UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) +#define USART_CR3_BCN_0 (0x00200000UL) +#define USART_CR3_BCN_1 (0x00400000UL) +#define USART_CR3_BCN_2 (0x00800000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC_POS (0U) +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) +#define USART_PR_LBMPSC_POS (2U) +#define USART_PR_LBMPSC (0x0000000CUL) +#define USART_PR_LBMPSC_0 (0x00000004UL) +#define USART_PR_LBMPSC_1 (0x00000008UL) + +/* Bit definition for USART_LBMC register */ +#define USART_LBMC_LBMC (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USBFS +*******************************************************************************/ +/* Bit definition for USBFS_GVBUSCFG register */ +#define USBFS_GVBUSCFG_VBUSOVEN_POS (6U) +#define USBFS_GVBUSCFG_VBUSOVEN (0x00000040UL) +#define USBFS_GVBUSCFG_VBUSVAL_POS (7U) +#define USBFS_GVBUSCFG_VBUSVAL (0x00000080UL) + +/* Bit definition for USBFS_GAHBCFG register */ +#define USBFS_GAHBCFG_GINTMSK_POS (0U) +#define USBFS_GAHBCFG_GINTMSK (0x00000001UL) +#define USBFS_GAHBCFG_HBSTLEN_POS (1U) +#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBFS_GAHBCFG_DMAEN_POS (5U) +#define USBFS_GAHBCFG_DMAEN (0x00000020UL) +#define USBFS_GAHBCFG_TXFELVL_POS (7U) +#define USBFS_GAHBCFG_TXFELVL (0x00000080UL) +#define USBFS_GAHBCFG_PTXFELVL_POS (8U) +#define USBFS_GAHBCFG_PTXFELVL (0x00000100UL) + +/* Bit definition for USBFS_GUSBCFG register */ +#define USBFS_GUSBCFG_TOCAL_POS (0U) +#define USBFS_GUSBCFG_TOCAL (0x00000007UL) +#define USBFS_GUSBCFG_PHYSEL_POS (6U) +#define USBFS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBFS_GUSBCFG_TRDT_POS (10U) +#define USBFS_GUSBCFG_TRDT (0x00003C00UL) +#define USBFS_GUSBCFG_FHMOD_POS (29U) +#define USBFS_GUSBCFG_FHMOD (0x20000000UL) +#define USBFS_GUSBCFG_FDMOD_POS (30U) +#define USBFS_GUSBCFG_FDMOD (0x40000000UL) + +/* Bit definition for USBFS_GRSTCTL register */ +#define USBFS_GRSTCTL_CSRST_POS (0U) +#define USBFS_GRSTCTL_CSRST (0x00000001UL) +#define USBFS_GRSTCTL_HSRST_POS (1U) +#define USBFS_GRSTCTL_HSRST (0x00000002UL) +#define USBFS_GRSTCTL_FCRST_POS (2U) +#define USBFS_GRSTCTL_FCRST (0x00000004UL) +#define USBFS_GRSTCTL_RXFFLSH_POS (4U) +#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBFS_GRSTCTL_TXFFLSH_POS (5U) +#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBFS_GRSTCTL_TXFNUM_POS (6U) +#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBFS_GRSTCTL_DMAREQ_POS (30U) +#define USBFS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBFS_GRSTCTL_AHBIDL_POS (31U) +#define USBFS_GRSTCTL_AHBIDL (0x80000000UL) + +/* Bit definition for USBFS_GINTSTS register */ +#define USBFS_GINTSTS_CMOD_POS (0U) +#define USBFS_GINTSTS_CMOD (0x00000001UL) +#define USBFS_GINTSTS_MMIS_POS (1U) +#define USBFS_GINTSTS_MMIS (0x00000002UL) +#define USBFS_GINTSTS_SOF_POS (3U) +#define USBFS_GINTSTS_SOF (0x00000008UL) +#define USBFS_GINTSTS_RXFNE_POS (4U) +#define USBFS_GINTSTS_RXFNE (0x00000010UL) +#define USBFS_GINTSTS_NPTXFE_POS (5U) +#define USBFS_GINTSTS_NPTXFE (0x00000020UL) +#define USBFS_GINTSTS_GINAKEFF_POS (6U) +#define USBFS_GINTSTS_GINAKEFF (0x00000040UL) +#define USBFS_GINTSTS_GONAKEFF_POS (7U) +#define USBFS_GINTSTS_GONAKEFF (0x00000080UL) +#define USBFS_GINTSTS_ESUSP_POS (10U) +#define USBFS_GINTSTS_ESUSP (0x00000400UL) +#define USBFS_GINTSTS_USBSUSP_POS (11U) +#define USBFS_GINTSTS_USBSUSP (0x00000800UL) +#define USBFS_GINTSTS_USBRST_POS (12U) +#define USBFS_GINTSTS_USBRST (0x00001000UL) +#define USBFS_GINTSTS_ENUMDNE_POS (13U) +#define USBFS_GINTSTS_ENUMDNE (0x00002000UL) +#define USBFS_GINTSTS_ISOODRP_POS (14U) +#define USBFS_GINTSTS_ISOODRP (0x00004000UL) +#define USBFS_GINTSTS_EOPF_POS (15U) +#define USBFS_GINTSTS_EOPF (0x00008000UL) +#define USBFS_GINTSTS_IEPINT_POS (18U) +#define USBFS_GINTSTS_IEPINT (0x00040000UL) +#define USBFS_GINTSTS_OEPINT_POS (19U) +#define USBFS_GINTSTS_OEPINT (0x00080000UL) +#define USBFS_GINTSTS_IISOIXFR_POS (20U) +#define USBFS_GINTSTS_IISOIXFR (0x00100000UL) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT_POS (21U) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT (0x00200000UL) +#define USBFS_GINTSTS_DATAFSUSP_POS (22U) +#define USBFS_GINTSTS_DATAFSUSP (0x00400000UL) +#define USBFS_GINTSTS_HPRTINT_POS (24U) +#define USBFS_GINTSTS_HPRTINT (0x01000000UL) +#define USBFS_GINTSTS_HCINT_POS (25U) +#define USBFS_GINTSTS_HCINT (0x02000000UL) +#define USBFS_GINTSTS_PTXFE_POS (26U) +#define USBFS_GINTSTS_PTXFE (0x04000000UL) +#define USBFS_GINTSTS_LPMINT_POS (27U) +#define USBFS_GINTSTS_LPMINT (0x08000000UL) +#define USBFS_GINTSTS_CIDSCHG_POS (28U) +#define USBFS_GINTSTS_CIDSCHG (0x10000000UL) +#define USBFS_GINTSTS_DISCINT_POS (29U) +#define USBFS_GINTSTS_DISCINT (0x20000000UL) +#define USBFS_GINTSTS_VBUSVINT_POS (30U) +#define USBFS_GINTSTS_VBUSVINT (0x40000000UL) +#define USBFS_GINTSTS_WKUINT_POS (31U) +#define USBFS_GINTSTS_WKUINT (0x80000000UL) + +/* Bit definition for USBFS_GINTMSK register */ +#define USBFS_GINTMSK_MMISM_POS (1U) +#define USBFS_GINTMSK_MMISM (0x00000002UL) +#define USBFS_GINTMSK_SOFM_POS (3U) +#define USBFS_GINTMSK_SOFM (0x00000008UL) +#define USBFS_GINTMSK_RXFNEM_POS (4U) +#define USBFS_GINTMSK_RXFNEM (0x00000010UL) +#define USBFS_GINTMSK_NPTXFEM_POS (5U) +#define USBFS_GINTMSK_NPTXFEM (0x00000020UL) +#define USBFS_GINTMSK_GINAKEFFM_POS (6U) +#define USBFS_GINTMSK_GINAKEFFM (0x00000040UL) +#define USBFS_GINTMSK_GONAKEFFM_POS (7U) +#define USBFS_GINTMSK_GONAKEFFM (0x00000080UL) +#define USBFS_GINTMSK_ESUSPM_POS (10U) +#define USBFS_GINTMSK_ESUSPM (0x00000400UL) +#define USBFS_GINTMSK_USBSUSPM_POS (11U) +#define USBFS_GINTMSK_USBSUSPM (0x00000800UL) +#define USBFS_GINTMSK_USBRSTM_POS (12U) +#define USBFS_GINTMSK_USBRSTM (0x00001000UL) +#define USBFS_GINTMSK_ENUMDNEM_POS (13U) +#define USBFS_GINTMSK_ENUMDNEM (0x00002000UL) +#define USBFS_GINTMSK_ISOODRPM_POS (14U) +#define USBFS_GINTMSK_ISOODRPM (0x00004000UL) +#define USBFS_GINTMSK_EOPFM_POS (15U) +#define USBFS_GINTMSK_EOPFM (0x00008000UL) +#define USBFS_GINTMSK_IEPIM_POS (18U) +#define USBFS_GINTMSK_IEPIM (0x00040000UL) +#define USBFS_GINTMSK_OEPIM_POS (19U) +#define USBFS_GINTMSK_OEPIM (0x00080000UL) +#define USBFS_GINTMSK_IISOIXFRM_POS (20U) +#define USBFS_GINTMSK_IISOIXFRM (0x00100000UL) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS (21U) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (0x00200000UL) +#define USBFS_GINTMSK_DATAFSUSPM_POS (22U) +#define USBFS_GINTMSK_DATAFSUSPM (0x00400000UL) +#define USBFS_GINTMSK_HPRTIM_POS (24U) +#define USBFS_GINTMSK_HPRTIM (0x01000000UL) +#define USBFS_GINTMSK_HCIM_POS (25U) +#define USBFS_GINTMSK_HCIM (0x02000000UL) +#define USBFS_GINTMSK_PTXFEM_POS (26U) +#define USBFS_GINTMSK_PTXFEM (0x04000000UL) +#define USBFS_GINTMSK_LPMINTM_POS (27U) +#define USBFS_GINTMSK_LPMINTM (0x08000000UL) +#define USBFS_GINTMSK_CIDSCHGM_POS (28U) +#define USBFS_GINTMSK_CIDSCHGM (0x10000000UL) +#define USBFS_GINTMSK_DISCIM_POS (29U) +#define USBFS_GINTMSK_DISCIM (0x20000000UL) +#define USBFS_GINTMSK_VBUSVIM_POS (30U) +#define USBFS_GINTMSK_VBUSVIM (0x40000000UL) +#define USBFS_GINTMSK_WKUIM_POS (31U) +#define USBFS_GINTMSK_WKUIM (0x80000000UL) + +/* Bit definition for USBFS_GRXSTSR register */ +#define USBFS_GRXSTSR_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSR_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSR_BCNT_POS (4U) +#define USBFS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSR_DPID_POS (15U) +#define USBFS_GRXSTSR_DPID (0x00018000UL) +#define USBFS_GRXSTSR_PKTSTS_POS (17U) +#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXSTSP register */ +#define USBFS_GRXSTSP_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSP_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSP_BCNT_POS (4U) +#define USBFS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSP_DPID_POS (15U) +#define USBFS_GRXSTSP_DPID (0x00018000UL) +#define USBFS_GRXSTSP_PKTSTS_POS (17U) +#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXFSIZ register */ +#define USBFS_GRXFSIZ_RXFD (0x000007FFUL) + +/* Bit definition for USBFS_HNPTXFSIZ register */ +#define USBFS_HNPTXFSIZ_NPTXFSA_POS (0U) +#define USBFS_HNPTXFSIZ_NPTXFSA (0x0000FFFFUL) +#define USBFS_HNPTXFSIZ_NPTXFD_POS (16U) +#define USBFS_HNPTXFSIZ_NPTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_HNPTXSTS register */ +#define USBFS_HNPTXSTS_NPTXFSAV_POS (0U) +#define USBFS_HNPTXSTS_NPTXFSAV (0x0000FFFFUL) +#define USBFS_HNPTXSTS_NPTQXSAV_POS (16U) +#define USBFS_HNPTXSTS_NPTQXSAV (0x00FF0000UL) +#define USBFS_HNPTXSTS_NPTXQTOP_POS (24U) +#define USBFS_HNPTXSTS_NPTXQTOP (0x7F000000UL) + +/* Bit definition for USBFS_CID register */ +#define USBFS_CID (0xFFFFFFFFUL) + +/* Bit definition for USBFS_GLPMCFG register */ +#define USBFS_GLPMCFG_LPMEN_POS (0U) +#define USBFS_GLPMCFG_LPMEN (0x00000001UL) +#define USBFS_GLPMCFG_LPMACK_POS (1U) +#define USBFS_GLPMCFG_LPMACK (0x00000002UL) +#define USBFS_GLPMCFG_BSEL_POS (2U) +#define USBFS_GLPMCFG_BSEL (0x0000003CUL) +#define USBFS_GLPMCFG_REMWAKE_POS (6U) +#define USBFS_GLPMCFG_REMWAKE (0x00000040UL) +#define USBFS_GLPMCFG_L1SSEN_POS (7U) +#define USBFS_GLPMCFG_L1SSEN (0x00000080UL) +#define USBFS_GLPMCFG_BESLTHRS_POS (8U) +#define USBFS_GLPMCFG_BESLTHRS (0x00000F00UL) +#define USBFS_GLPMCFG_L1DSEN_POS (12U) +#define USBFS_GLPMCFG_L1DSEN (0x00001000UL) +#define USBFS_GLPMCFG_LPMRSP_POS (13U) +#define USBFS_GLPMCFG_LPMRSP (0x00006000UL) +#define USBFS_GLPMCFG_SLPSTS_POS (15U) +#define USBFS_GLPMCFG_SLPSTS (0x00008000UL) +#define USBFS_GLPMCFG_L1RSMOK_POS (16U) +#define USBFS_GLPMCFG_L1RSMOK (0x00010000UL) +#define USBFS_GLPMCFG_LPMCHIDX_POS (17U) +#define USBFS_GLPMCFG_LPMCHIDX (0x001E0000UL) +#define USBFS_GLPMCFG_LPMRCNT_POS (21U) +#define USBFS_GLPMCFG_LPMRCNT (0x00E00000UL) +#define USBFS_GLPMCFG_SENDLPM_POS (24U) +#define USBFS_GLPMCFG_SENDLPM (0x01000000UL) +#define USBFS_GLPMCFG_LPMRCNTSTS_POS (25U) +#define USBFS_GLPMCFG_LPMRCNTSTS (0x0E000000UL) +#define USBFS_GLPMCFG_ENBSEL_POS (28U) +#define USBFS_GLPMCFG_ENBSEL (0x10000000UL) + +/* Bit definition for USBFS_HPTXFSIZ register */ +#define USBFS_HPTXFSIZ_PTXSA_POS (0U) +#define USBFS_HPTXFSIZ_PTXSA (0x0000FFFFUL) +#define USBFS_HPTXFSIZ_PTXFD_POS (16U) +#define USBFS_HPTXFSIZ_PTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_DIEPTXF register */ +#define USBFS_DIEPTXF_INEPTXSA_POS (0U) +#define USBFS_DIEPTXF_INEPTXSA (0x0000FFFFUL) +#define USBFS_DIEPTXF_INEPTXFD_POS (16U) +#define USBFS_DIEPTXF_INEPTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_HCFG register */ +#define USBFS_HCFG_FSLSPCS_POS (0U) +#define USBFS_HCFG_FSLSPCS (0x00000003UL) +#define USBFS_HCFG_FSLSS_POS (2U) +#define USBFS_HCFG_FSLSS (0x00000004UL) + +/* Bit definition for USBFS_HFIR register */ +#define USBFS_HFIR_FRIVL (0x0000FFFFUL) + +/* Bit definition for USBFS_HFNUM register */ +#define USBFS_HFNUM_FRNUM_POS (0U) +#define USBFS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBFS_HFNUM_FTREM_POS (16U) +#define USBFS_HFNUM_FTREM (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXSTS register */ +#define USBFS_HPTXSTS_PTXFSAVL_POS (0U) +#define USBFS_HPTXSTS_PTXFSAVL (0x0000FFFFUL) +#define USBFS_HPTXSTS_PTXQSAV_POS (16U) +#define USBFS_HPTXSTS_PTXQSAV (0x00FF0000UL) +#define USBFS_HPTXSTS_PTXQTOP_POS (24U) +#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL) + +/* Bit definition for USBFS_HAINT register */ +#define USBFS_HAINT_HAINT (0x0000FFFFUL) + +/* Bit definition for USBFS_HAINTMSK register */ +#define USBFS_HAINTMSK_HAINTM (0x0000FFFFUL) + +/* Bit definition for USBFS_HPRT register */ +#define USBFS_HPRT_PCSTS_POS (0U) +#define USBFS_HPRT_PCSTS (0x00000001UL) +#define USBFS_HPRT_PCDET_POS (1U) +#define USBFS_HPRT_PCDET (0x00000002UL) +#define USBFS_HPRT_PENA_POS (2U) +#define USBFS_HPRT_PENA (0x00000004UL) +#define USBFS_HPRT_PENCHNG_POS (3U) +#define USBFS_HPRT_PENCHNG (0x00000008UL) +#define USBFS_HPRT_PRES_POS (6U) +#define USBFS_HPRT_PRES (0x00000040UL) +#define USBFS_HPRT_PSUSP_POS (7U) +#define USBFS_HPRT_PSUSP (0x00000080UL) +#define USBFS_HPRT_PRST_POS (8U) +#define USBFS_HPRT_PRST (0x00000100UL) +#define USBFS_HPRT_PLSTS_POS (10U) +#define USBFS_HPRT_PLSTS (0x00000C00UL) +#define USBFS_HPRT_PWPR_POS (12U) +#define USBFS_HPRT_PWPR (0x00001000UL) +#define USBFS_HPRT_PSPD_POS (17U) +#define USBFS_HPRT_PSPD (0x00060000UL) + +/* Bit definition for USBFS_HCCHAR register */ +#define USBFS_HCCHAR_MPSIZ_POS (0U) +#define USBFS_HCCHAR_MPSIZ (0x000007FFUL) +#define USBFS_HCCHAR_EPNUM_POS (11U) +#define USBFS_HCCHAR_EPNUM (0x00007800UL) +#define USBFS_HCCHAR_EPDIR_POS (15U) +#define USBFS_HCCHAR_EPDIR (0x00008000UL) +#define USBFS_HCCHAR_LSDEV_POS (17U) +#define USBFS_HCCHAR_LSDEV (0x00020000UL) +#define USBFS_HCCHAR_EPTYP_POS (18U) +#define USBFS_HCCHAR_EPTYP (0x000C0000UL) +#define USBFS_HCCHAR_DAD_POS (22U) +#define USBFS_HCCHAR_DAD (0x1FC00000UL) +#define USBFS_HCCHAR_ODDFRM_POS (29U) +#define USBFS_HCCHAR_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR_CHDIS_POS (30U) +#define USBFS_HCCHAR_CHDIS (0x40000000UL) +#define USBFS_HCCHAR_CHENA_POS (31U) +#define USBFS_HCCHAR_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT register */ +#define USBFS_HCINT_XFRC_POS (0U) +#define USBFS_HCINT_XFRC (0x00000001UL) +#define USBFS_HCINT_CHH_POS (1U) +#define USBFS_HCINT_CHH (0x00000002UL) +#define USBFS_HCINT_AHBERR_POS (2U) +#define USBFS_HCINT_AHBERR (0x00000004UL) +#define USBFS_HCINT_STALL_POS (3U) +#define USBFS_HCINT_STALL (0x00000008UL) +#define USBFS_HCINT_NAK_POS (4U) +#define USBFS_HCINT_NAK (0x00000010UL) +#define USBFS_HCINT_ACK_POS (5U) +#define USBFS_HCINT_ACK (0x00000020UL) +#define USBFS_HCINT_TXERR_POS (7U) +#define USBFS_HCINT_TXERR (0x00000080UL) +#define USBFS_HCINT_BBERR_POS (8U) +#define USBFS_HCINT_BBERR (0x00000100UL) +#define USBFS_HCINT_FRMOR_POS (9U) +#define USBFS_HCINT_FRMOR (0x00000200UL) +#define USBFS_HCINT_DTERR_POS (10U) +#define USBFS_HCINT_DTERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK register */ +#define USBFS_HCINTMSK_XFRCM_POS (0U) +#define USBFS_HCINTMSK_XFRCM (0x00000001UL) +#define USBFS_HCINTMSK_CHHM_POS (1U) +#define USBFS_HCINTMSK_CHHM (0x00000002UL) +#define USBFS_HCINTMSK_AHBERRM_POS (2U) +#define USBFS_HCINTMSK_AHBERRM (0x00000004UL) +#define USBFS_HCINTMSK_STALLM_POS (3U) +#define USBFS_HCINTMSK_STALLM (0x00000008UL) +#define USBFS_HCINTMSK_NAKM_POS (4U) +#define USBFS_HCINTMSK_NAKM (0x00000010UL) +#define USBFS_HCINTMSK_ACKM_POS (5U) +#define USBFS_HCINTMSK_ACKM (0x00000020UL) +#define USBFS_HCINTMSK_TXERRM_POS (7U) +#define USBFS_HCINTMSK_TXERRM (0x00000080UL) +#define USBFS_HCINTMSK_BBERRM_POS (8U) +#define USBFS_HCINTMSK_BBERRM (0x00000100UL) +#define USBFS_HCINTMSK_FRMORM_POS (9U) +#define USBFS_HCINTMSK_FRMORM (0x00000200UL) +#define USBFS_HCINTMSK_DTERRM_POS (10U) +#define USBFS_HCINTMSK_DTERRM (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ register */ +#define USBFS_HCTSIZ_XFRSIZ_POS (0U) +#define USBFS_HCTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_HCTSIZ_PKTCNT_POS (19U) +#define USBFS_HCTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ_DPID_POS (29U) +#define USBFS_HCTSIZ_DPID (0x60000000UL) + +/* Bit definition for USBFS_HCDMA register */ +#define USBFS_HCDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DCFG register */ +#define USBFS_DCFG_DSPD_POS (0U) +#define USBFS_DCFG_DSPD (0x00000003UL) +#define USBFS_DCFG_NZLSOHSK_POS (2U) +#define USBFS_DCFG_NZLSOHSK (0x00000004UL) +#define USBFS_DCFG_DAD_POS (4U) +#define USBFS_DCFG_DAD (0x000007F0UL) +#define USBFS_DCFG_PFIVL_POS (11U) +#define USBFS_DCFG_PFIVL (0x00001800UL) + +/* Bit definition for USBFS_DCTL register */ +#define USBFS_DCTL_RWUSIG_POS (0U) +#define USBFS_DCTL_RWUSIG (0x00000001UL) +#define USBFS_DCTL_SDIS_POS (1U) +#define USBFS_DCTL_SDIS (0x00000002UL) +#define USBFS_DCTL_GINSTS_POS (2U) +#define USBFS_DCTL_GINSTS (0x00000004UL) +#define USBFS_DCTL_GONSTS_POS (3U) +#define USBFS_DCTL_GONSTS (0x00000008UL) +#define USBFS_DCTL_SGINAK_POS (7U) +#define USBFS_DCTL_SGINAK (0x00000080UL) +#define USBFS_DCTL_CGINAK_POS (8U) +#define USBFS_DCTL_CGINAK (0x00000100UL) +#define USBFS_DCTL_SGONAK_POS (9U) +#define USBFS_DCTL_SGONAK (0x00000200UL) +#define USBFS_DCTL_CGONAK_POS (10U) +#define USBFS_DCTL_CGONAK (0x00000400UL) +#define USBFS_DCTL_POPRGDNE_POS (11U) +#define USBFS_DCTL_POPRGDNE (0x00000800UL) + +/* Bit definition for USBFS_DSTS register */ +#define USBFS_DSTS_SUSPSTS_POS (0U) +#define USBFS_DSTS_SUSPSTS (0x00000001UL) +#define USBFS_DSTS_ENUMSPD_POS (1U) +#define USBFS_DSTS_ENUMSPD (0x00000006UL) +#define USBFS_DSTS_EERR_POS (3U) +#define USBFS_DSTS_EERR (0x00000008UL) +#define USBFS_DSTS_FNSOF_POS (8U) +#define USBFS_DSTS_FNSOF (0x003FFF00UL) +#define USBFS_DSTS_LNSTS_POS (22U) +#define USBFS_DSTS_LNSTS (0x00C00000UL) + +/* Bit definition for USBFS_DIEPMSK register */ +#define USBFS_DIEPMSK_XFRCM_POS (0U) +#define USBFS_DIEPMSK_XFRCM (0x00000001UL) +#define USBFS_DIEPMSK_EPDM_POS (1U) +#define USBFS_DIEPMSK_EPDM (0x00000002UL) +#define USBFS_DIEPMSK_TOM_POS (3U) +#define USBFS_DIEPMSK_TOM (0x00000008UL) +#define USBFS_DIEPMSK_ITTXFEMSK_POS (4U) +#define USBFS_DIEPMSK_ITTXFEMSK (0x00000010UL) +#define USBFS_DIEPMSK_INEPNMM_POS (5U) +#define USBFS_DIEPMSK_INEPNMM (0x00000020UL) +#define USBFS_DIEPMSK_INEPNEM_POS (6U) +#define USBFS_DIEPMSK_INEPNEM (0x00000040UL) +#define USBFS_DIEPMSK_NAKM_POS (13U) +#define USBFS_DIEPMSK_NAKM (0x00002000UL) + +/* Bit definition for USBFS_DOEPMSK register */ +#define USBFS_DOEPMSK_XFRCM_POS (0U) +#define USBFS_DOEPMSK_XFRCM (0x00000001UL) +#define USBFS_DOEPMSK_EPDM_POS (1U) +#define USBFS_DOEPMSK_EPDM (0x00000002UL) +#define USBFS_DOEPMSK_STUPM_POS (3U) +#define USBFS_DOEPMSK_STUPM (0x00000008UL) +#define USBFS_DOEPMSK_OTEPDM_POS (4U) +#define USBFS_DOEPMSK_OTEPDM (0x00000010UL) + +/* Bit definition for USBFS_DAINT register */ +#define USBFS_DAINT_IEPINT_POS (0U) +#define USBFS_DAINT_IEPINT (0x0000FFFFUL) +#define USBFS_DAINT_OEPINT_POS (16U) +#define USBFS_DAINT_OEPINT (0xFFFF0000UL) + +/* Bit definition for USBFS_DAINTMSK register */ +#define USBFS_DAINTMSK_IEPINTM_POS (0U) +#define USBFS_DAINTMSK_IEPINTM (0x0000FFFFUL) +#define USBFS_DAINTMSK_OEPINTM_POS (16U) +#define USBFS_DAINTMSK_OEPINTM (0xFFFF0000UL) + +/* Bit definition for USBFS_DIEPEMPMSK register */ +#define USBFS_DIEPEMPMSK_INEPTXFEM (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL0 register */ +#define USBFS_DIEPCTL0_MPSIZ_POS (0U) +#define USBFS_DIEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DIEPCTL0_USBAEP_POS (15U) +#define USBFS_DIEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL0_NAKSTS_POS (17U) +#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL0_EPTYP_POS (18U) +#define USBFS_DIEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL0_STALL_POS (21U) +#define USBFS_DIEPCTL0_STALL (0x00200000UL) +#define USBFS_DIEPCTL0_TXFNUM_POS (22U) +#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL0_CNAK_POS (26U) +#define USBFS_DIEPCTL0_CNAK (0x04000000UL) +#define USBFS_DIEPCTL0_SNAK_POS (27U) +#define USBFS_DIEPCTL0_SNAK (0x08000000UL) +#define USBFS_DIEPCTL0_EPDIS_POS (30U) +#define USBFS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL0_EPENA_POS (31U) +#define USBFS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT register */ +#define USBFS_DIEPINT_XFRC_POS (0U) +#define USBFS_DIEPINT_XFRC (0x00000001UL) +#define USBFS_DIEPINT_EPDISD_POS (1U) +#define USBFS_DIEPINT_EPDISD (0x00000002UL) +#define USBFS_DIEPINT_TOC_POS (3U) +#define USBFS_DIEPINT_TOC (0x00000008UL) +#define USBFS_DIEPINT_TTXFE_POS (4U) +#define USBFS_DIEPINT_TTXFE (0x00000010UL) +#define USBFS_DIEPINT_INEPNE_POS (6U) +#define USBFS_DIEPINT_INEPNE (0x00000040UL) +#define USBFS_DIEPINT_TXFE_POS (7U) +#define USBFS_DIEPINT_TXFE (0x00000080UL) + +/* Bit definition for USBFS_DIEPTSIZ0 register */ +#define USBFS_DIEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBFS_DIEPDMA register */ +#define USBFS_DIEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS register */ +#define USBFS_DTXFSTS_INEPTFSAV (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL register */ +#define USBFS_DIEPCTL_MPSIZ_POS (0U) +#define USBFS_DIEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DIEPCTL_USBAEP_POS (15U) +#define USBFS_DIEPCTL_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL_EONUM_DPID_POS (16U) +#define USBFS_DIEPCTL_EONUM_DPID (0x00010000UL) +#define USBFS_DIEPCTL_NAKSTS_POS (17U) +#define USBFS_DIEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL_EPTYP_POS (18U) +#define USBFS_DIEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL_STALL_POS (21U) +#define USBFS_DIEPCTL_STALL (0x00200000UL) +#define USBFS_DIEPCTL_TXFNUM_POS (22U) +#define USBFS_DIEPCTL_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL_CNAK_POS (26U) +#define USBFS_DIEPCTL_CNAK (0x04000000UL) +#define USBFS_DIEPCTL_SNAK_POS (27U) +#define USBFS_DIEPCTL_SNAK (0x08000000UL) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM_POS (28U) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM (0x10000000UL) +#define USBFS_DIEPCTL_SODDFRM_POS (29U) +#define USBFS_DIEPCTL_SODDFRM (0x20000000UL) +#define USBFS_DIEPCTL_EPDIS_POS (30U) +#define USBFS_DIEPCTL_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL_EPENA_POS (31U) +#define USBFS_DIEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPTSIZ register */ +#define USBFS_DIEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DIEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ_MCNT_POS (29U) +#define USBFS_DIEPTSIZ_MCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPCTL0 register */ +#define USBFS_DOEPCTL0_MPSIZ_POS (0U) +#define USBFS_DOEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DOEPCTL0_USBAEP_POS (15U) +#define USBFS_DOEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL0_NAKSTS_POS (17U) +#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL0_EPTYP_POS (18U) +#define USBFS_DOEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL0_SNPM_POS (20U) +#define USBFS_DOEPCTL0_SNPM (0x00100000UL) +#define USBFS_DOEPCTL0_STALL_POS (21U) +#define USBFS_DOEPCTL0_STALL (0x00200000UL) +#define USBFS_DOEPCTL0_CNAK_POS (26U) +#define USBFS_DOEPCTL0_CNAK (0x04000000UL) +#define USBFS_DOEPCTL0_SNAK_POS (27U) +#define USBFS_DOEPCTL0_SNAK (0x08000000UL) +#define USBFS_DOEPCTL0_EPDIS_POS (30U) +#define USBFS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL0_EPENA_POS (31U) +#define USBFS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT register */ +#define USBFS_DOEPINT_XFRC_POS (0U) +#define USBFS_DOEPINT_XFRC (0x00000001UL) +#define USBFS_DOEPINT_EPDISD_POS (1U) +#define USBFS_DOEPINT_EPDISD (0x00000002UL) +#define USBFS_DOEPINT_STUP_POS (3U) +#define USBFS_DOEPINT_STUP (0x00000008UL) +#define USBFS_DOEPINT_OTEPDIS_POS (4U) +#define USBFS_DOEPINT_OTEPDIS (0x00000010UL) +#define USBFS_DOEPINT_B2BSTUP_POS (6U) +#define USBFS_DOEPINT_B2BSTUP (0x00000040UL) + +/* Bit definition for USBFS_DOEPTSIZ0 register */ +#define USBFS_DOEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBFS_DOEPTSIZ0_STUPCNT_POS (29U) +#define USBFS_DOEPTSIZ0_STUPCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPDMA register */ +#define USBFS_DOEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL register */ +#define USBFS_DOEPCTL_MPSIZ_POS (0U) +#define USBFS_DOEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DOEPCTL_USBAEP_POS (15U) +#define USBFS_DOEPCTL_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL_DPID_POS (16U) +#define USBFS_DOEPCTL_DPID (0x00010000UL) +#define USBFS_DOEPCTL_NAKSTS_POS (17U) +#define USBFS_DOEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL_EPTYP_POS (18U) +#define USBFS_DOEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL_SNPM_POS (20U) +#define USBFS_DOEPCTL_SNPM (0x00100000UL) +#define USBFS_DOEPCTL_STALL_POS (21U) +#define USBFS_DOEPCTL_STALL (0x00200000UL) +#define USBFS_DOEPCTL_CNAK_POS (26U) +#define USBFS_DOEPCTL_CNAK (0x04000000UL) +#define USBFS_DOEPCTL_SNAK_POS (27U) +#define USBFS_DOEPCTL_SNAK (0x08000000UL) +#define USBFS_DOEPCTL_SD0PID_POS (28U) +#define USBFS_DOEPCTL_SD0PID (0x10000000UL) +#define USBFS_DOEPCTL_SD1PID_POS (29U) +#define USBFS_DOEPCTL_SD1PID (0x20000000UL) +#define USBFS_DOEPCTL_EPDIS_POS (30U) +#define USBFS_DOEPCTL_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL_EPENA_POS (31U) +#define USBFS_DOEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPTSIZ register */ +#define USBFS_DOEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DOEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ_RXDPID_STUPCNT_POS (29U) +#define USBFS_DOEPTSIZ_RXDPID_STUPCNT (0x60000000UL) + +/* Bit definition for USBFS_GCCTL register */ +#define USBFS_GCCTL_STPPCLK_POS (0U) +#define USBFS_GCCTL_STPPCLK (0x00000001UL) +#define USBFS_GCCTL_GATEHCLK_POS (1U) +#define USBFS_GCCTL_GATEHCLK (0x00000002UL) +#define USBFS_GCCTL_ENL1GTG_POS (5U) +#define USBFS_GCCTL_ENL1GTG (0x00000020UL) +#define USBFS_GCCTL_PHYSLEEP_POS (6U) +#define USBFS_GCCTL_PHYSLEEP (0x00000040UL) +#define USBFS_GCCTL_SUSP_POS (7U) +#define USBFS_GCCTL_SUSP (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral USBHS +*******************************************************************************/ +/* Bit definition for USBHS_GVBUSCFG register */ +#define USBHS_GVBUSCFG_VBUSOVEN_POS (6U) +#define USBHS_GVBUSCFG_VBUSOVEN (0x00000040UL) +#define USBHS_GVBUSCFG_VBUSVAL_POS (7U) +#define USBHS_GVBUSCFG_VBUSVAL (0x00000080UL) + +/* Bit definition for USBHS_GAHBCFG register */ +#define USBHS_GAHBCFG_GINTMSK_POS (0U) +#define USBHS_GAHBCFG_GINTMSK (0x00000001UL) +#define USBHS_GAHBCFG_HBSTLEN_POS (1U) +#define USBHS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBHS_GAHBCFG_DMAEN_POS (5U) +#define USBHS_GAHBCFG_DMAEN (0x00000020UL) +#define USBHS_GAHBCFG_TXFELVL_POS (7U) +#define USBHS_GAHBCFG_TXFELVL (0x00000080UL) +#define USBHS_GAHBCFG_PTXFELVL_POS (8U) +#define USBHS_GAHBCFG_PTXFELVL (0x00000100UL) + +/* Bit definition for USBHS_GUSBCFG register */ +#define USBHS_GUSBCFG_TOCAL_POS (0U) +#define USBHS_GUSBCFG_TOCAL (0x00000007UL) +#define USBHS_GUSBCFG_PHYSEL_POS (6U) +#define USBHS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBHS_GUSBCFG_TRDT_POS (10U) +#define USBHS_GUSBCFG_TRDT (0x00003C00UL) +#define USBHS_GUSBCFG_PHYLPCS_POS (15U) +#define USBHS_GUSBCFG_PHYLPCS (0x00008000UL) +#define USBHS_GUSBCFG_ULFSLS_POS (17U) +#define USBHS_GUSBCFG_ULFSLS (0x00020000UL) +#define USBHS_GUSBCFG_ULPIAR_POS (18U) +#define USBHS_GUSBCFG_ULPIAR (0x00040000UL) +#define USBHS_GUSBCFG_ULPICSM_POS (19U) +#define USBHS_GUSBCFG_ULPICSM (0x00080000UL) +#define USBHS_GUSBCFG_ULPIEVBUSD_POS (20U) +#define USBHS_GUSBCFG_ULPIEVBUSD (0x00100000UL) +#define USBHS_GUSBCFG_ULPIEVBUSI_POS (21U) +#define USBHS_GUSBCFG_ULPIEVBUSI (0x00200000UL) +#define USBHS_GUSBCFG_PCCI_POS (23U) +#define USBHS_GUSBCFG_PCCI (0x00800000UL) +#define USBHS_GUSBCFG_PTCI_POS (24U) +#define USBHS_GUSBCFG_PTCI (0x01000000UL) +#define USBHS_GUSBCFG_ULPIPD_POS (25U) +#define USBHS_GUSBCFG_ULPIPD (0x02000000UL) +#define USBHS_GUSBCFG_FHMOD_POS (29U) +#define USBHS_GUSBCFG_FHMOD (0x20000000UL) +#define USBHS_GUSBCFG_FDMOD_POS (30U) +#define USBHS_GUSBCFG_FDMOD (0x40000000UL) + +/* Bit definition for USBHS_GRSTCTL register */ +#define USBHS_GRSTCTL_CSRST_POS (0U) +#define USBHS_GRSTCTL_CSRST (0x00000001UL) +#define USBHS_GRSTCTL_HSRST_POS (1U) +#define USBHS_GRSTCTL_HSRST (0x00000002UL) +#define USBHS_GRSTCTL_FCRST_POS (2U) +#define USBHS_GRSTCTL_FCRST (0x00000004UL) +#define USBHS_GRSTCTL_RXFFLSH_POS (4U) +#define USBHS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBHS_GRSTCTL_TXFFLSH_POS (5U) +#define USBHS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBHS_GRSTCTL_TXFNUM_POS (6U) +#define USBHS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBHS_GRSTCTL_DMAREQ_POS (30U) +#define USBHS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBHS_GRSTCTL_AHBIDL_POS (31U) +#define USBHS_GRSTCTL_AHBIDL (0x80000000UL) + +/* Bit definition for USBHS_GINTSTS register */ +#define USBHS_GINTSTS_CMOD_POS (0U) +#define USBHS_GINTSTS_CMOD (0x00000001UL) +#define USBHS_GINTSTS_MMIS_POS (1U) +#define USBHS_GINTSTS_MMIS (0x00000002UL) +#define USBHS_GINTSTS_SOF_POS (3U) +#define USBHS_GINTSTS_SOF (0x00000008UL) +#define USBHS_GINTSTS_RXFNE_POS (4U) +#define USBHS_GINTSTS_RXFNE (0x00000010UL) +#define USBHS_GINTSTS_NPTXFE_POS (5U) +#define USBHS_GINTSTS_NPTXFE (0x00000020UL) +#define USBHS_GINTSTS_GINAKEFF_POS (6U) +#define USBHS_GINTSTS_GINAKEFF (0x00000040UL) +#define USBHS_GINTSTS_GONAKEFF_POS (7U) +#define USBHS_GINTSTS_GONAKEFF (0x00000080UL) +#define USBHS_GINTSTS_ESUSP_POS (10U) +#define USBHS_GINTSTS_ESUSP (0x00000400UL) +#define USBHS_GINTSTS_USBSUSP_POS (11U) +#define USBHS_GINTSTS_USBSUSP (0x00000800UL) +#define USBHS_GINTSTS_USBRST_POS (12U) +#define USBHS_GINTSTS_USBRST (0x00001000UL) +#define USBHS_GINTSTS_ENUMDNE_POS (13U) +#define USBHS_GINTSTS_ENUMDNE (0x00002000UL) +#define USBHS_GINTSTS_ISOODRP_POS (14U) +#define USBHS_GINTSTS_ISOODRP (0x00004000UL) +#define USBHS_GINTSTS_EOPF_POS (15U) +#define USBHS_GINTSTS_EOPF (0x00008000UL) +#define USBHS_GINTSTS_IEPINT_POS (18U) +#define USBHS_GINTSTS_IEPINT (0x00040000UL) +#define USBHS_GINTSTS_OEPINT_POS (19U) +#define USBHS_GINTSTS_OEPINT (0x00080000UL) +#define USBHS_GINTSTS_IISOIXFR_POS (20U) +#define USBHS_GINTSTS_IISOIXFR (0x00100000UL) +#define USBHS_GINTSTS_IPXFR_INCOMPISOOUT_POS (21U) +#define USBHS_GINTSTS_IPXFR_INCOMPISOOUT (0x00200000UL) +#define USBHS_GINTSTS_DATAFSUSP_POS (22U) +#define USBHS_GINTSTS_DATAFSUSP (0x00400000UL) +#define USBHS_GINTSTS_HPRTINT_POS (24U) +#define USBHS_GINTSTS_HPRTINT (0x01000000UL) +#define USBHS_GINTSTS_HCINT_POS (25U) +#define USBHS_GINTSTS_HCINT (0x02000000UL) +#define USBHS_GINTSTS_PTXFE_POS (26U) +#define USBHS_GINTSTS_PTXFE (0x04000000UL) +#define USBHS_GINTSTS_LPMINT_POS (27U) +#define USBHS_GINTSTS_LPMINT (0x08000000UL) +#define USBHS_GINTSTS_CIDSCHG_POS (28U) +#define USBHS_GINTSTS_CIDSCHG (0x10000000UL) +#define USBHS_GINTSTS_DISCINT_POS (29U) +#define USBHS_GINTSTS_DISCINT (0x20000000UL) +#define USBHS_GINTSTS_VBUSVINT_POS (30U) +#define USBHS_GINTSTS_VBUSVINT (0x40000000UL) +#define USBHS_GINTSTS_WKUINT_POS (31U) +#define USBHS_GINTSTS_WKUINT (0x80000000UL) + +/* Bit definition for USBHS_GINTMSK register */ +#define USBHS_GINTMSK_MMISM_POS (1U) +#define USBHS_GINTMSK_MMISM (0x00000002UL) +#define USBHS_GINTMSK_SOFM_POS (3U) +#define USBHS_GINTMSK_SOFM (0x00000008UL) +#define USBHS_GINTMSK_RXFNEM_POS (4U) +#define USBHS_GINTMSK_RXFNEM (0x00000010UL) +#define USBHS_GINTMSK_NPTXFEM_POS (5U) +#define USBHS_GINTMSK_NPTXFEM (0x00000020UL) +#define USBHS_GINTMSK_GINAKEFFM_POS (6U) +#define USBHS_GINTMSK_GINAKEFFM (0x00000040UL) +#define USBHS_GINTMSK_GONAKEFFM_POS (7U) +#define USBHS_GINTMSK_GONAKEFFM (0x00000080UL) +#define USBHS_GINTMSK_ESUSPM_POS (10U) +#define USBHS_GINTMSK_ESUSPM (0x00000400UL) +#define USBHS_GINTMSK_USBSUSPM_POS (11U) +#define USBHS_GINTMSK_USBSUSPM (0x00000800UL) +#define USBHS_GINTMSK_USBRSTM_POS (12U) +#define USBHS_GINTMSK_USBRSTM (0x00001000UL) +#define USBHS_GINTMSK_ENUMDNEM_POS (13U) +#define USBHS_GINTMSK_ENUMDNEM (0x00002000UL) +#define USBHS_GINTMSK_ISOODRPM_POS (14U) +#define USBHS_GINTMSK_ISOODRPM (0x00004000UL) +#define USBHS_GINTMSK_EOPFM_POS (15U) +#define USBHS_GINTMSK_EOPFM (0x00008000UL) +#define USBHS_GINTMSK_IEPIM_POS (18U) +#define USBHS_GINTMSK_IEPIM (0x00040000UL) +#define USBHS_GINTMSK_OEPIM_POS (19U) +#define USBHS_GINTMSK_OEPIM (0x00080000UL) +#define USBHS_GINTMSK_IISOIXFRM_POS (20U) +#define USBHS_GINTMSK_IISOIXFRM (0x00100000UL) +#define USBHS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS (21U) +#define USBHS_GINTMSK_IPXFRM_INCOMPISOOUTM (0x00200000UL) +#define USBHS_GINTMSK_DATAFSUSPM_POS (22U) +#define USBHS_GINTMSK_DATAFSUSPM (0x00400000UL) +#define USBHS_GINTMSK_HPRTIM_POS (24U) +#define USBHS_GINTMSK_HPRTIM (0x01000000UL) +#define USBHS_GINTMSK_HCIM_POS (25U) +#define USBHS_GINTMSK_HCIM (0x02000000UL) +#define USBHS_GINTMSK_PTXFEM_POS (26U) +#define USBHS_GINTMSK_PTXFEM (0x04000000UL) +#define USBHS_GINTMSK_LPMINTM_POS (27U) +#define USBHS_GINTMSK_LPMINTM (0x08000000UL) +#define USBHS_GINTMSK_CIDSCHGM_POS (28U) +#define USBHS_GINTMSK_CIDSCHGM (0x10000000UL) +#define USBHS_GINTMSK_DISCIM_POS (29U) +#define USBHS_GINTMSK_DISCIM (0x20000000UL) +#define USBHS_GINTMSK_VBUSVIM_POS (30U) +#define USBHS_GINTMSK_VBUSVIM (0x40000000UL) +#define USBHS_GINTMSK_WKUIM_POS (31U) +#define USBHS_GINTMSK_WKUIM (0x80000000UL) + +/* Bit definition for USBHS_GRXSTSR register */ +#define USBHS_GRXSTSR_CHNUM_EPNUM_POS (0U) +#define USBHS_GRXSTSR_CHNUM_EPNUM (0x0000000FUL) +#define USBHS_GRXSTSR_BCNT_POS (4U) +#define USBHS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBHS_GRXSTSR_DPID_POS (15U) +#define USBHS_GRXSTSR_DPID (0x00018000UL) +#define USBHS_GRXSTSR_PKTSTS_POS (17U) +#define USBHS_GRXSTSR_PKTSTS (0x001E0000UL) + +/* Bit definition for USBHS_GRXSTSP register */ +#define USBHS_GRXSTSP_CHNUM_EPNUM_POS (0U) +#define USBHS_GRXSTSP_CHNUM_EPNUM (0x0000000FUL) +#define USBHS_GRXSTSP_BCNT_POS (4U) +#define USBHS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBHS_GRXSTSP_DPID_POS (15U) +#define USBHS_GRXSTSP_DPID (0x00018000UL) +#define USBHS_GRXSTSP_PKTSTS_POS (17U) +#define USBHS_GRXSTSP_PKTSTS (0x001E0000UL) + +/* Bit definition for USBHS_GRXFSIZ register */ +#define USBHS_GRXFSIZ_RXFD (0x00000FFFUL) + +/* Bit definition for USBHS_HNPTXFSIZ register */ +#define USBHS_HNPTXFSIZ_NPTXFSA_POS (0U) +#define USBHS_HNPTXFSIZ_NPTXFSA (0x0000FFFFUL) +#define USBHS_HNPTXFSIZ_NPTXFD_POS (16U) +#define USBHS_HNPTXFSIZ_NPTXFD (0xFFFF0000UL) + +/* Bit definition for USBHS_HNPTXSTS register */ +#define USBHS_HNPTXSTS_NPTXFSAV_POS (0U) +#define USBHS_HNPTXSTS_NPTXFSAV (0x0000FFFFUL) +#define USBHS_HNPTXSTS_NPTQXSAV_POS (16U) +#define USBHS_HNPTXSTS_NPTQXSAV (0x00FF0000UL) +#define USBHS_HNPTXSTS_NPTXQTOP_POS (24U) +#define USBHS_HNPTXSTS_NPTXQTOP (0x7F000000UL) + +/* Bit definition for USBHS_CID register */ +#define USBHS_CID (0xFFFFFFFFUL) + +/* Bit definition for USBHS_GLPMCFG register */ +#define USBHS_GLPMCFG_LPMEN_POS (0U) +#define USBHS_GLPMCFG_LPMEN (0x00000001UL) +#define USBHS_GLPMCFG_LPMACK_POS (1U) +#define USBHS_GLPMCFG_LPMACK (0x00000002UL) +#define USBHS_GLPMCFG_BSEL_POS (2U) +#define USBHS_GLPMCFG_BSEL (0x0000003CUL) +#define USBHS_GLPMCFG_REMWAKE_POS (6U) +#define USBHS_GLPMCFG_REMWAKE (0x00000040UL) +#define USBHS_GLPMCFG_L1SSEN_POS (7U) +#define USBHS_GLPMCFG_L1SSEN (0x00000080UL) +#define USBHS_GLPMCFG_BESLTHRS_POS (8U) +#define USBHS_GLPMCFG_BESLTHRS (0x00000F00UL) +#define USBHS_GLPMCFG_L1DSEN_POS (12U) +#define USBHS_GLPMCFG_L1DSEN (0x00001000UL) +#define USBHS_GLPMCFG_LPMRSP_POS (13U) +#define USBHS_GLPMCFG_LPMRSP (0x00006000UL) +#define USBHS_GLPMCFG_SLPSTS_POS (15U) +#define USBHS_GLPMCFG_SLPSTS (0x00008000UL) +#define USBHS_GLPMCFG_L1RSMOK_POS (16U) +#define USBHS_GLPMCFG_L1RSMOK (0x00010000UL) +#define USBHS_GLPMCFG_LPMCHIDX_POS (17U) +#define USBHS_GLPMCFG_LPMCHIDX (0x001E0000UL) +#define USBHS_GLPMCFG_LPMRCNT_POS (21U) +#define USBHS_GLPMCFG_LPMRCNT (0x00E00000UL) +#define USBHS_GLPMCFG_SENDLPM_POS (24U) +#define USBHS_GLPMCFG_SENDLPM (0x01000000UL) +#define USBHS_GLPMCFG_LPMRCNTSTS_POS (25U) +#define USBHS_GLPMCFG_LPMRCNTSTS (0x0E000000UL) +#define USBHS_GLPMCFG_ENBSEL_POS (28U) +#define USBHS_GLPMCFG_ENBSEL (0x10000000UL) + +/* Bit definition for USBHS_HPTXFSIZ register */ +#define USBHS_HPTXFSIZ_PTXSA_POS (0U) +#define USBHS_HPTXFSIZ_PTXSA (0x0000FFFFUL) +#define USBHS_HPTXFSIZ_PTXFD_POS (16U) +#define USBHS_HPTXFSIZ_PTXFD (0xFFFF0000UL) + +/* Bit definition for USBHS_DIEPTXF register */ +#define USBHS_DIEPTXF_INEPTXSA_POS (0U) +#define USBHS_DIEPTXF_INEPTXSA (0x0000FFFFUL) +#define USBHS_DIEPTXF_INEPTXFD_POS (16U) +#define USBHS_DIEPTXF_INEPTXFD (0xFFFF0000UL) + +/* Bit definition for USBHS_HCFG register */ +#define USBHS_HCFG_FSLSPCS_POS (0U) +#define USBHS_HCFG_FSLSPCS (0x00000003UL) +#define USBHS_HCFG_FSLSS_POS (2U) +#define USBHS_HCFG_FSLSS (0x00000004UL) + +/* Bit definition for USBHS_HFIR register */ +#define USBHS_HFIR_FRIVL (0x0000FFFFUL) + +/* Bit definition for USBHS_HFNUM register */ +#define USBHS_HFNUM_FRNUM_POS (0U) +#define USBHS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBHS_HFNUM_FTREM_POS (16U) +#define USBHS_HFNUM_FTREM (0xFFFF0000UL) + +/* Bit definition for USBHS_HPTXSTS register */ +#define USBHS_HPTXSTS_PTXFSAVL_POS (0U) +#define USBHS_HPTXSTS_PTXFSAVL (0x0000FFFFUL) +#define USBHS_HPTXSTS_PTXQSAV_POS (16U) +#define USBHS_HPTXSTS_PTXQSAV (0x00FF0000UL) +#define USBHS_HPTXSTS_PTXQTOP_POS (24U) +#define USBHS_HPTXSTS_PTXQTOP (0xFF000000UL) + +/* Bit definition for USBHS_HAINT register */ +#define USBHS_HAINT_HAINT (0x0000FFFFUL) + +/* Bit definition for USBHS_HAINTMSK register */ +#define USBHS_HAINTMSK_HAINTM (0x0000FFFFUL) + +/* Bit definition for USBHS_HPRT register */ +#define USBHS_HPRT_PCSTS_POS (0U) +#define USBHS_HPRT_PCSTS (0x00000001UL) +#define USBHS_HPRT_PCDET_POS (1U) +#define USBHS_HPRT_PCDET (0x00000002UL) +#define USBHS_HPRT_PENA_POS (2U) +#define USBHS_HPRT_PENA (0x00000004UL) +#define USBHS_HPRT_PENCHNG_POS (3U) +#define USBHS_HPRT_PENCHNG (0x00000008UL) +#define USBHS_HPRT_POCA_POS (4U) +#define USBHS_HPRT_POCA (0x00000010UL) +#define USBHS_HPRT_POCCHNG_POS (5U) +#define USBHS_HPRT_POCCHNG (0x00000020UL) +#define USBHS_HPRT_PRES_POS (6U) +#define USBHS_HPRT_PRES (0x00000040UL) +#define USBHS_HPRT_PSUSP_POS (7U) +#define USBHS_HPRT_PSUSP (0x00000080UL) +#define USBHS_HPRT_PRST_POS (8U) +#define USBHS_HPRT_PRST (0x00000100UL) +#define USBHS_HPRT_PLSTS_POS (10U) +#define USBHS_HPRT_PLSTS (0x00000C00UL) +#define USBHS_HPRT_PWPR_POS (12U) +#define USBHS_HPRT_PWPR (0x00001000UL) +#define USBHS_HPRT_PTCTL_POS (13U) +#define USBHS_HPRT_PTCTL (0x0001E000UL) +#define USBHS_HPRT_PSPD_POS (17U) +#define USBHS_HPRT_PSPD (0x00060000UL) + +/* Bit definition for USBHS_HCCHAR register */ +#define USBHS_HCCHAR_MPSIZ_POS (0U) +#define USBHS_HCCHAR_MPSIZ (0x000007FFUL) +#define USBHS_HCCHAR_EPNUM_POS (11U) +#define USBHS_HCCHAR_EPNUM (0x00007800UL) +#define USBHS_HCCHAR_EPDIR_POS (15U) +#define USBHS_HCCHAR_EPDIR (0x00008000UL) +#define USBHS_HCCHAR_LSDEV_POS (17U) +#define USBHS_HCCHAR_LSDEV (0x00020000UL) +#define USBHS_HCCHAR_EPTYP_POS (18U) +#define USBHS_HCCHAR_EPTYP (0x000C0000UL) +#define USBHS_HCCHAR_MC_POS (20U) +#define USBHS_HCCHAR_MC (0x00300000UL) +#define USBHS_HCCHAR_DAD_POS (22U) +#define USBHS_HCCHAR_DAD (0x1FC00000UL) +#define USBHS_HCCHAR_ODDFRM_POS (29U) +#define USBHS_HCCHAR_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR_CHDIS_POS (30U) +#define USBHS_HCCHAR_CHDIS (0x40000000UL) +#define USBHS_HCCHAR_CHENA_POS (31U) +#define USBHS_HCCHAR_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT register */ +#define USBHS_HCSPLT_PRTADDR_POS (0U) +#define USBHS_HCSPLT_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT_HUBADDR_POS (7U) +#define USBHS_HCSPLT_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT_XACTPOS_POS (14U) +#define USBHS_HCSPLT_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT_COMPLSPLT_POS (16U) +#define USBHS_HCSPLT_COMPLSPLT (0x00010000UL) +#define USBHS_HCSPLT_SPLITEN_POS (31U) +#define USBHS_HCSPLT_SPLITEN (0x80000000UL) + +/* Bit definition for USBHS_HCINT register */ +#define USBHS_HCINT_XFRC_POS (0U) +#define USBHS_HCINT_XFRC (0x00000001UL) +#define USBHS_HCINT_CHH_POS (1U) +#define USBHS_HCINT_CHH (0x00000002UL) +#define USBHS_HCINT_AHBERR_POS (2U) +#define USBHS_HCINT_AHBERR (0x00000004UL) +#define USBHS_HCINT_STALL_POS (3U) +#define USBHS_HCINT_STALL (0x00000008UL) +#define USBHS_HCINT_NAK_POS (4U) +#define USBHS_HCINT_NAK (0x00000010UL) +#define USBHS_HCINT_ACK_POS (5U) +#define USBHS_HCINT_ACK (0x00000020UL) +#define USBHS_HCINT_NYET_POS (6U) +#define USBHS_HCINT_NYET (0x00000040UL) +#define USBHS_HCINT_TXERR_POS (7U) +#define USBHS_HCINT_TXERR (0x00000080UL) +#define USBHS_HCINT_BBERR_POS (8U) +#define USBHS_HCINT_BBERR (0x00000100UL) +#define USBHS_HCINT_FRMOR_POS (9U) +#define USBHS_HCINT_FRMOR (0x00000200UL) +#define USBHS_HCINT_DTERR_POS (10U) +#define USBHS_HCINT_DTERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK register */ +#define USBHS_HCINTMSK_XFRCM_POS (0U) +#define USBHS_HCINTMSK_XFRCM (0x00000001UL) +#define USBHS_HCINTMSK_CHHM_POS (1U) +#define USBHS_HCINTMSK_CHHM (0x00000002UL) +#define USBHS_HCINTMSK_AHBERRM_POS (2U) +#define USBHS_HCINTMSK_AHBERRM (0x00000004UL) +#define USBHS_HCINTMSK_STALLM_POS (3U) +#define USBHS_HCINTMSK_STALLM (0x00000008UL) +#define USBHS_HCINTMSK_NAKM_POS (4U) +#define USBHS_HCINTMSK_NAKM (0x00000010UL) +#define USBHS_HCINTMSK_ACKM_POS (5U) +#define USBHS_HCINTMSK_ACKM (0x00000020UL) +#define USBHS_HCINTMSK_NYETM_POS (6U) +#define USBHS_HCINTMSK_NYETM (0x00000040UL) +#define USBHS_HCINTMSK_TXERRM_POS (7U) +#define USBHS_HCINTMSK_TXERRM (0x00000080UL) +#define USBHS_HCINTMSK_BBERRM_POS (8U) +#define USBHS_HCINTMSK_BBERRM (0x00000100UL) +#define USBHS_HCINTMSK_FRMORM_POS (9U) +#define USBHS_HCINTMSK_FRMORM (0x00000200UL) +#define USBHS_HCINTMSK_DTERRM_POS (10U) +#define USBHS_HCINTMSK_DTERRM (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ register */ +#define USBHS_HCTSIZ_XFRSIZ_POS (0U) +#define USBHS_HCTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBHS_HCTSIZ_PKTCNT_POS (19U) +#define USBHS_HCTSIZ_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ_DPID_POS (29U) +#define USBHS_HCTSIZ_DPID (0x60000000UL) +#define USBHS_HCTSIZ_DOPING_POS (31U) +#define USBHS_HCTSIZ_DOPING (0x80000000UL) + +/* Bit definition for USBHS_HCDMA register */ +#define USBHS_HCDMA (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DCFG register */ +#define USBHS_DCFG_DSPD_POS (0U) +#define USBHS_DCFG_DSPD (0x00000003UL) +#define USBHS_DCFG_NZLSOHSK_POS (2U) +#define USBHS_DCFG_NZLSOHSK (0x00000004UL) +#define USBHS_DCFG_DAD_POS (4U) +#define USBHS_DCFG_DAD (0x000007F0UL) +#define USBHS_DCFG_PFIVL_POS (11U) +#define USBHS_DCFG_PFIVL (0x00001800UL) + +/* Bit definition for USBHS_DCTL register */ +#define USBHS_DCTL_RWUSIG_POS (0U) +#define USBHS_DCTL_RWUSIG (0x00000001UL) +#define USBHS_DCTL_SDIS_POS (1U) +#define USBHS_DCTL_SDIS (0x00000002UL) +#define USBHS_DCTL_GINSTS_POS (2U) +#define USBHS_DCTL_GINSTS (0x00000004UL) +#define USBHS_DCTL_GONSTS_POS (3U) +#define USBHS_DCTL_GONSTS (0x00000008UL) +#define USBHS_DCTL_TCTL_POS (4U) +#define USBHS_DCTL_TCTL (0x00000070UL) +#define USBHS_DCTL_SGINAK_POS (7U) +#define USBHS_DCTL_SGINAK (0x00000080UL) +#define USBHS_DCTL_CGINAK_POS (8U) +#define USBHS_DCTL_CGINAK (0x00000100UL) +#define USBHS_DCTL_SGONAK_POS (9U) +#define USBHS_DCTL_SGONAK (0x00000200UL) +#define USBHS_DCTL_CGONAK_POS (10U) +#define USBHS_DCTL_CGONAK (0x00000400UL) +#define USBHS_DCTL_POPRGDNE_POS (11U) +#define USBHS_DCTL_POPRGDNE (0x00000800UL) + +/* Bit definition for USBHS_DSTS register */ +#define USBHS_DSTS_SUSPSTS_POS (0U) +#define USBHS_DSTS_SUSPSTS (0x00000001UL) +#define USBHS_DSTS_ENUMSPD_POS (1U) +#define USBHS_DSTS_ENUMSPD (0x00000006UL) +#define USBHS_DSTS_EERR_POS (3U) +#define USBHS_DSTS_EERR (0x00000008UL) +#define USBHS_DSTS_FNSOF_POS (8U) +#define USBHS_DSTS_FNSOF (0x003FFF00UL) +#define USBHS_DSTS_LNSTS_POS (22U) +#define USBHS_DSTS_LNSTS (0x00C00000UL) + +/* Bit definition for USBHS_DIEPMSK register */ +#define USBHS_DIEPMSK_XFRCM_POS (0U) +#define USBHS_DIEPMSK_XFRCM (0x00000001UL) +#define USBHS_DIEPMSK_EPDM_POS (1U) +#define USBHS_DIEPMSK_EPDM (0x00000002UL) +#define USBHS_DIEPMSK_TOM_POS (3U) +#define USBHS_DIEPMSK_TOM (0x00000008UL) +#define USBHS_DIEPMSK_TTXFEMSK_POS (4U) +#define USBHS_DIEPMSK_TTXFEMSK (0x00000010UL) +#define USBHS_DIEPMSK_INEPNMM_POS (5U) +#define USBHS_DIEPMSK_INEPNMM (0x00000020UL) +#define USBHS_DIEPMSK_INEPNEM_POS (6U) +#define USBHS_DIEPMSK_INEPNEM (0x00000040UL) +#define USBHS_DIEPMSK_TXFURM_POS (8U) +#define USBHS_DIEPMSK_TXFURM (0x00000100UL) +#define USBHS_DIEPMSK_NAKM_POS (13U) +#define USBHS_DIEPMSK_NAKM (0x00002000UL) + +/* Bit definition for USBHS_DOEPMSK register */ +#define USBHS_DOEPMSK_XFRCM_POS (0U) +#define USBHS_DOEPMSK_XFRCM (0x00000001UL) +#define USBHS_DOEPMSK_EPDM_POS (1U) +#define USBHS_DOEPMSK_EPDM (0x00000002UL) +#define USBHS_DOEPMSK_STUPM_POS (3U) +#define USBHS_DOEPMSK_STUPM (0x00000008UL) +#define USBHS_DOEPMSK_OTEPDM_POS (4U) +#define USBHS_DOEPMSK_OTEPDM (0x00000010UL) +#define USBHS_DOEPMSK_B2BSTUP_POS (6U) +#define USBHS_DOEPMSK_B2BSTUP (0x00000040UL) +#define USBHS_DOEPMSK_OPEM_POS (8U) +#define USBHS_DOEPMSK_OPEM (0x00000100UL) +#define USBHS_DOEPMSK_NYETM_POS (14U) +#define USBHS_DOEPMSK_NYETM (0x00004000UL) + +/* Bit definition for USBHS_DAINT register */ +#define USBHS_DAINT_IEPINT_POS (0U) +#define USBHS_DAINT_IEPINT (0x0000FFFFUL) +#define USBHS_DAINT_OEPINT_POS (16U) +#define USBHS_DAINT_OEPINT (0xFFFF0000UL) + +/* Bit definition for USBHS_DAINTMSK register */ +#define USBHS_DAINTMSK_IEPINTM_POS (0U) +#define USBHS_DAINTMSK_IEPINTM (0x0000FFFFUL) +#define USBHS_DAINTMSK_OEPINTM_POS (16U) +#define USBHS_DAINTMSK_OEPINTM (0xFFFF0000UL) + +/* Bit definition for USBHS_DTHRCTL register */ +#define USBHS_DTHRCTL_NONISOTHREN_POS (0U) +#define USBHS_DTHRCTL_NONISOTHREN (0x00000001UL) +#define USBHS_DTHRCTL_ISOTHREN_POS (1U) +#define USBHS_DTHRCTL_ISOTHREN (0x00000002UL) +#define USBHS_DTHRCTL_TXTHRLEN_POS (2U) +#define USBHS_DTHRCTL_TXTHRLEN (0x000007FCUL) +#define USBHS_DTHRCTL_RXTHREN_POS (16U) +#define USBHS_DTHRCTL_RXTHREN (0x00010000UL) +#define USBHS_DTHRCTL_RXTHRLEN_POS (17U) +#define USBHS_DTHRCTL_RXTHRLEN (0x03FE0000UL) +#define USBHS_DTHRCTL_ARPEN_POS (27U) +#define USBHS_DTHRCTL_ARPEN (0x08000000UL) + +/* Bit definition for USBHS_DIEPEMPMSK register */ +#define USBHS_DIEPEMPMSK_INEPTXFEM (0x0000FFFFUL) + +/* Bit definition for USBHS_DEACHINT register */ +#define USBHS_DEACHINT_IEP1INT_POS (1U) +#define USBHS_DEACHINT_IEP1INT (0x00000002UL) +#define USBHS_DEACHINT_OEP1INT_POS (17U) +#define USBHS_DEACHINT_OEP1INT (0x00020000UL) + +/* Bit definition for USBHS_DEACHINTMSK register */ +#define USBHS_DEACHINTMSK_IEP1INTM_POS (1U) +#define USBHS_DEACHINTMSK_IEP1INTM (0x00000002UL) +#define USBHS_DEACHINTMSK_OEP1INTM_POS (17U) +#define USBHS_DEACHINTMSK_OEP1INTM (0x00020000UL) + +/* Bit definition for USBHS_DIEPEACHMSK1 register */ +#define USBHS_DIEPEACHMSK1_XFRCM_POS (0U) +#define USBHS_DIEPEACHMSK1_XFRCM (0x00000001UL) +#define USBHS_DIEPEACHMSK1_EPDM_POS (1U) +#define USBHS_DIEPEACHMSK1_EPDM (0x00000002UL) +#define USBHS_DIEPEACHMSK1_TOM_POS (3U) +#define USBHS_DIEPEACHMSK1_TOM (0x00000008UL) +#define USBHS_DIEPEACHMSK1_TTXFEMSK_POS (4U) +#define USBHS_DIEPEACHMSK1_TTXFEMSK (0x00000010UL) +#define USBHS_DIEPEACHMSK1_INEPNMM_POS (5U) +#define USBHS_DIEPEACHMSK1_INEPNMM (0x00000020UL) +#define USBHS_DIEPEACHMSK1_INEPNEM_POS (6U) +#define USBHS_DIEPEACHMSK1_INEPNEM (0x00000040UL) +#define USBHS_DIEPEACHMSK1_TXFURM_POS (8U) +#define USBHS_DIEPEACHMSK1_TXFURM (0x00000100UL) +#define USBHS_DIEPEACHMSK1_NAKM_POS (13U) +#define USBHS_DIEPEACHMSK1_NAKM (0x00002000UL) + +/* Bit definition for USBHS_DOEPEACHMSK1 register */ +#define USBHS_DOEPEACHMSK1_XFRCM_POS (0U) +#define USBHS_DOEPEACHMSK1_XFRCM (0x00000001UL) +#define USBHS_DOEPEACHMSK1_EPDM_POS (1U) +#define USBHS_DOEPEACHMSK1_EPDM (0x00000002UL) +#define USBHS_DOEPEACHMSK1_STUPM_POS (3U) +#define USBHS_DOEPEACHMSK1_STUPM (0x00000008UL) +#define USBHS_DOEPEACHMSK1_OTEPDM_POS (4U) +#define USBHS_DOEPEACHMSK1_OTEPDM (0x00000010UL) +#define USBHS_DOEPEACHMSK1_B2BSTUP_POS (6U) +#define USBHS_DOEPEACHMSK1_B2BSTUP (0x00000040UL) +#define USBHS_DOEPEACHMSK1_OPEM_POS (8U) +#define USBHS_DOEPEACHMSK1_OPEM (0x00000100UL) +#define USBHS_DOEPEACHMSK1_NYETM_POS (14U) +#define USBHS_DOEPEACHMSK1_NYETM (0x00004000UL) + +/* Bit definition for USBHS_DIEPCTL0 register */ +#define USBHS_DIEPCTL0_MPSIZ_POS (0U) +#define USBHS_DIEPCTL0_MPSIZ (0x00000003UL) +#define USBHS_DIEPCTL0_USBAEP_POS (15U) +#define USBHS_DIEPCTL0_USBAEP (0x00008000UL) +#define USBHS_DIEPCTL0_NAKSTS_POS (17U) +#define USBHS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL0_EPTYP_POS (18U) +#define USBHS_DIEPCTL0_EPTYP (0x000C0000UL) +#define USBHS_DIEPCTL0_STALL_POS (21U) +#define USBHS_DIEPCTL0_STALL (0x00200000UL) +#define USBHS_DIEPCTL0_TXFNUM_POS (22U) +#define USBHS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL0_CNAK_POS (26U) +#define USBHS_DIEPCTL0_CNAK (0x04000000UL) +#define USBHS_DIEPCTL0_SNAK_POS (27U) +#define USBHS_DIEPCTL0_SNAK (0x08000000UL) +#define USBHS_DIEPCTL0_EPDIS_POS (30U) +#define USBHS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL0_EPENA_POS (31U) +#define USBHS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT register */ +#define USBHS_DIEPINT_XFRC_POS (0U) +#define USBHS_DIEPINT_XFRC (0x00000001UL) +#define USBHS_DIEPINT_EPDISD_POS (1U) +#define USBHS_DIEPINT_EPDISD (0x00000002UL) +#define USBHS_DIEPINT_TOC_POS (3U) +#define USBHS_DIEPINT_TOC (0x00000008UL) +#define USBHS_DIEPINT_TTXFE_POS (4U) +#define USBHS_DIEPINT_TTXFE (0x00000010UL) +#define USBHS_DIEPINT_INEPNE_POS (6U) +#define USBHS_DIEPINT_INEPNE (0x00000040UL) +#define USBHS_DIEPINT_TXFE_POS (7U) +#define USBHS_DIEPINT_TXFE (0x00000080UL) +#define USBHS_DIEPINT_TXFIFOUDRN_POS (8U) +#define USBHS_DIEPINT_TXFIFOUDRN (0x00000100UL) +#define USBHS_DIEPINT_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT_BERR_POS (12U) +#define USBHS_DIEPINT_BERR (0x00001000UL) +#define USBHS_DIEPINT_NAK_POS (13U) +#define USBHS_DIEPINT_NAK (0x00002000UL) + +/* Bit definition for USBHS_DIEPTSIZ0 register */ +#define USBHS_DIEPTSIZ0_XFRSIZ_POS (0U) +#define USBHS_DIEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBHS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBHS_DIEPDMA register */ +#define USBHS_DIEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS register */ +#define USBHS_DTXFSTS_INEPTFSAV (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL register */ +#define USBHS_DIEPCTL_MPSIZ_POS (0U) +#define USBHS_DIEPCTL_MPSIZ (0x000007FFUL) +#define USBHS_DIEPCTL_USBAEP_POS (15U) +#define USBHS_DIEPCTL_USBAEP (0x00008000UL) +#define USBHS_DIEPCTL_EONUM_DPID_POS (16U) +#define USBHS_DIEPCTL_EONUM_DPID (0x00010000UL) +#define USBHS_DIEPCTL_NAKSTS_POS (17U) +#define USBHS_DIEPCTL_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL_EPTYP_POS (18U) +#define USBHS_DIEPCTL_EPTYP (0x000C0000UL) +#define USBHS_DIEPCTL_STALL_POS (21U) +#define USBHS_DIEPCTL_STALL (0x00200000UL) +#define USBHS_DIEPCTL_TXFNUM_POS (22U) +#define USBHS_DIEPCTL_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL_CNAK_POS (26U) +#define USBHS_DIEPCTL_CNAK (0x04000000UL) +#define USBHS_DIEPCTL_SNAK_POS (27U) +#define USBHS_DIEPCTL_SNAK (0x08000000UL) +#define USBHS_DIEPCTL_SD0PID_SEVNFRM_POS (28U) +#define USBHS_DIEPCTL_SD0PID_SEVNFRM (0x10000000UL) +#define USBHS_DIEPCTL_SODDFRM_POS (29U) +#define USBHS_DIEPCTL_SODDFRM (0x20000000UL) +#define USBHS_DIEPCTL_EPDIS_POS (30U) +#define USBHS_DIEPCTL_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL_EPENA_POS (31U) +#define USBHS_DIEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPTSIZ register */ +#define USBHS_DIEPTSIZ_XFRSIZ_POS (0U) +#define USBHS_DIEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBHS_DIEPTSIZ_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ_MCNT_POS (29U) +#define USBHS_DIEPTSIZ_MCNT (0x60000000UL) + +/* Bit definition for USBHS_DOEPCTL0 register */ +#define USBHS_DOEPCTL0_MPSIZ_POS (0U) +#define USBHS_DOEPCTL0_MPSIZ (0x00000003UL) +#define USBHS_DOEPCTL0_USBAEP_POS (15U) +#define USBHS_DOEPCTL0_USBAEP (0x00008000UL) +#define USBHS_DOEPCTL0_NAKSTS_POS (17U) +#define USBHS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL0_EPTYP_POS (18U) +#define USBHS_DOEPCTL0_EPTYP (0x000C0000UL) +#define USBHS_DOEPCTL0_EPTYP_0 (0x00040000UL) +#define USBHS_DOEPCTL0_EPTYP_1 (0x00080000UL) +#define USBHS_DOEPCTL0_SNPM_POS (20U) +#define USBHS_DOEPCTL0_SNPM (0x00100000UL) +#define USBHS_DOEPCTL0_STALL_POS (21U) +#define USBHS_DOEPCTL0_STALL (0x00200000UL) +#define USBHS_DOEPCTL0_CNAK_POS (26U) +#define USBHS_DOEPCTL0_CNAK (0x04000000UL) +#define USBHS_DOEPCTL0_SNAK_POS (27U) +#define USBHS_DOEPCTL0_SNAK (0x08000000UL) +#define USBHS_DOEPCTL0_EPDIS_POS (30U) +#define USBHS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL0_EPENA_POS (31U) +#define USBHS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT register */ +#define USBHS_DOEPINT_XFRC_POS (0U) +#define USBHS_DOEPINT_XFRC (0x00000001UL) +#define USBHS_DOEPINT_EPDISD_POS (1U) +#define USBHS_DOEPINT_EPDISD (0x00000002UL) +#define USBHS_DOEPINT_STUP_POS (3U) +#define USBHS_DOEPINT_STUP (0x00000008UL) +#define USBHS_DOEPINT_OTEPDIS_POS (4U) +#define USBHS_DOEPINT_OTEPDIS (0x00000010UL) +#define USBHS_DOEPINT_B2BSTUP_POS (6U) +#define USBHS_DOEPINT_B2BSTUP (0x00000040UL) +#define USBHS_DOEPINT_NYET_POS (14U) +#define USBHS_DOEPINT_NYET (0x00004000UL) + +/* Bit definition for USBHS_DOEPTSIZ0 register */ +#define USBHS_DOEPTSIZ0_XFRSIZ_POS (0U) +#define USBHS_DOEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBHS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBHS_DOEPTSIZ0_STUPCNT_POS (29U) +#define USBHS_DOEPTSIZ0_STUPCNT (0x60000000UL) + +/* Bit definition for USBHS_DOEPDMA register */ +#define USBHS_DOEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL register */ +#define USBHS_DOEPCTL_MPSIZ_POS (0U) +#define USBHS_DOEPCTL_MPSIZ (0x000007FFUL) +#define USBHS_DOEPCTL_USBAEP_POS (15U) +#define USBHS_DOEPCTL_USBAEP (0x00008000UL) +#define USBHS_DOEPCTL_DPID_POS (16U) +#define USBHS_DOEPCTL_DPID (0x00010000UL) +#define USBHS_DOEPCTL_NAKSTS_POS (17U) +#define USBHS_DOEPCTL_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL_EPTYP_POS (18U) +#define USBHS_DOEPCTL_EPTYP (0x000C0000UL) +#define USBHS_DOEPCTL_SNPM_POS (20U) +#define USBHS_DOEPCTL_SNPM (0x00100000UL) +#define USBHS_DOEPCTL_STALL_POS (21U) +#define USBHS_DOEPCTL_STALL (0x00200000UL) +#define USBHS_DOEPCTL_CNAK_POS (26U) +#define USBHS_DOEPCTL_CNAK (0x04000000UL) +#define USBHS_DOEPCTL_SNAK_POS (27U) +#define USBHS_DOEPCTL_SNAK (0x08000000UL) +#define USBHS_DOEPCTL_SD0PID_POS (28U) +#define USBHS_DOEPCTL_SD0PID (0x10000000UL) +#define USBHS_DOEPCTL_SD1PID_POS (29U) +#define USBHS_DOEPCTL_SD1PID (0x20000000UL) +#define USBHS_DOEPCTL_EPDIS_POS (30U) +#define USBHS_DOEPCTL_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL_EPENA_POS (31U) +#define USBHS_DOEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPTSIZ register */ +#define USBHS_DOEPTSIZ_XFRSIZ_POS (0U) +#define USBHS_DOEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBHS_DOEPTSIZ_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ_RXDPID_STUPCNT_POS (29U) +#define USBHS_DOEPTSIZ_RXDPID_STUPCNT (0x60000000UL) + +/* Bit definition for USBHS_GCCTL register */ +#define USBHS_GCCTL_STPPCLK_POS (0U) +#define USBHS_GCCTL_STPPCLK (0x00000001UL) +#define USBHS_GCCTL_GATEHCLK_POS (1U) +#define USBHS_GCCTL_GATEHCLK (0x00000002UL) +#define USBHS_GCCTL_ENL1GTG_POS (5U) +#define USBHS_GCCTL_ENL1GTG (0x00000020UL) +#define USBHS_GCCTL_PHYSLEEP_POS (6U) +#define USBHS_GCCTL_PHYSLEEP (0x00000040UL) +#define USBHS_GCCTL_SUSP_POS (7U) +#define USBHS_GCCTL_SUSP (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_CKS_0 (0x00000010UL) +#define WDT_CR_CKS_1 (0x00000020UL) +#define WDT_CR_CKS_2 (0x00000040UL) +#define WDT_CR_CKS_3 (0x00000080UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_WDPT_0 (0x00000100UL) +#define WDT_CR_WDPT_1 (0x00000200UL) +#define WDT_CR_WDPT_2 (0x00000400UL) +#define WDT_CR_WDPT_3 (0x00000800UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct { + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct { + __IO uint32_t MS0; + __IO uint32_t MS1; + uint32_t RESERVED0[2]; + __IO uint32_t ACCSEL0; + __IO uint32_t ACCSEL1; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + uint32_t RESERVED1[8]; +} stc_adc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct { + __IO uint32_t TRGSELA0; + __IO uint32_t TRGSELA1; + uint32_t RESERVED0[5]; + __IO uint32_t TRGENA; + __IO uint32_t TRGSELB0; + __IO uint32_t TRGSELB1; + uint32_t RESERVED1[5]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct { + __IO uint32_t EXCHSEL; + uint32_t RESERVED0[7]; +} stc_adc_exchselr_bit_t; + +typedef struct { + __I uint32_t EOCAF; + __I uint32_t EOCBF; + uint32_t RESERVED0[2]; + __I uint32_t SASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isr_bit_t; + +typedef struct { + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct { + __IO uint32_t CLREOCAF; + __IO uint32_t CLREOCBF; + uint32_t RESERVED0[2]; + __IO uint32_t CLRSASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isclrr_bit_t; + +typedef struct { + __IO uint32_t SYNCEN; + uint32_t RESERVED0[3]; + __IO uint32_t SYNCMD0; + __IO uint32_t SYNCMD1; + __IO uint32_t SYNCMD2; + uint32_t RESERVED1[9]; +} stc_adc_synccr_bit_t; + +typedef struct { + __IO uint32_t AWD0EN; + __IO uint32_t AWD0IEN; + __IO uint32_t AWD0MD; + uint32_t RESERVED0[1]; + __IO uint32_t AWD1EN; + __IO uint32_t AWD1IEN; + __IO uint32_t AWD1MD; + uint32_t RESERVED1[1]; + __IO uint32_t AWDCM0; + __IO uint32_t AWDCM1; + uint32_t RESERVED2[6]; +} stc_adc_awdcr_bit_t; + +typedef struct { + __I uint32_t AWD0F; + __I uint32_t AWD1F; + uint32_t RESERVED0[2]; + __I uint32_t AWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsr_bit_t; + +typedef struct { + __IO uint32_t CLRAWD0F; + __IO uint32_t CLRAWD1F; + uint32_t RESERVED0[2]; + __IO uint32_t CLRAWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsclrr_bit_t; + +typedef struct { + __IO uint32_t AWDCH0; + __IO uint32_t AWDCH1; + __IO uint32_t AWDCH2; + __IO uint32_t AWDCH3; + __IO uint32_t AWDCH4; + uint32_t RESERVED0[3]; +} stc_adc_awd0chsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct { + __O uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_intsfttrg_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dcu_trgsel_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma1_trgsel_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma2_trgsel_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma_trgselrc_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr6_htssr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_pevnttrgsr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr0_htssr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr2_htssr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_hash_itrgsela_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_hash_itrgselb_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmra_htssr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_ots_trg_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc1_itrgselr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc2_itrgselr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc3_itrgselr_bit_t; + +typedef struct { + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_pevntnfcr_bit_t; + +typedef struct { + __IO uint32_t BUSOFF; + __I uint32_t TACTIVE; + __I uint32_t RACTIVE; + __IO uint32_t TSSS; + __IO uint32_t TPSS; + __IO uint32_t LBMI; + __IO uint32_t LBME; + __IO uint32_t RESET; +} stc_can_cfg_stat_bit_t; + +typedef struct { + __IO uint32_t TSA; + __IO uint32_t TSALL; + __IO uint32_t TSONE; + __IO uint32_t TPA; + __IO uint32_t TPE; + uint32_t RESERVED0[1]; + __IO uint32_t LOM; + __IO uint32_t TBSEL; +} stc_can_tcmd_bit_t; + +typedef struct { + __I uint32_t TSSTAT0; + __I uint32_t TSSTAT1; + uint32_t RESERVED0[2]; + __IO uint32_t TTTBM; + __IO uint32_t TSMODE; + __IO uint32_t TSNEXT; + __IO uint32_t FD_ISO; +} stc_can_tctrl_bit_t; + +typedef struct { + __I uint32_t RSTAT0; + __I uint32_t RSTAT1; + uint32_t RESERVED0[1]; + __IO uint32_t RBALL; + __IO uint32_t RREL; + __I uint32_t ROV; + __IO uint32_t ROM; + __IO uint32_t SACK; +} stc_can_rctrl_bit_t; + +typedef struct { + __I uint32_t TSFF; + __IO uint32_t EIE; + __IO uint32_t TSIE; + __IO uint32_t TPIE; + __IO uint32_t RAFIE; + __IO uint32_t RFIE; + __IO uint32_t ROIE; + __IO uint32_t RIE; +} stc_can_rtie_bit_t; + +typedef struct { + __IO uint32_t AIF; + __IO uint32_t EIF; + __IO uint32_t TSIF; + __IO uint32_t TPIF; + __IO uint32_t RAFIF; + __IO uint32_t RFIF; + __IO uint32_t ROIF; + __IO uint32_t RIF; +} stc_can_rtif_bit_t; + +typedef struct { + __IO uint32_t BEIF; + __IO uint32_t BEIE; + __IO uint32_t ALIF; + __IO uint32_t ALIE; + __IO uint32_t EPIF; + __IO uint32_t EPIE; + __I uint32_t EPASS; + __I uint32_t EWARN; +} stc_can_errint_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TDCEN; +} stc_can_tdc_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SELMASK; + uint32_t RESERVED1[2]; +} stc_can_acfctrl_bit_t; + +typedef struct { + __IO uint32_t AE_1; + __IO uint32_t AE_2; + __IO uint32_t AE_3; + __IO uint32_t AE_4; + __IO uint32_t AE_5; + __IO uint32_t AE_6; + __IO uint32_t AE_7; + __IO uint32_t AE_8; + __IO uint32_t AE_9; + __IO uint32_t AE_10; + __IO uint32_t AE_11; + __IO uint32_t AE_12; + __IO uint32_t AE_13; + __IO uint32_t AE_14; + __IO uint32_t AE_15; + __IO uint32_t AE_16; +} stc_can_acfen_bit_t; + +typedef struct { + uint32_t RESERVED0[29]; + __IO uint32_t AIDE; + __IO uint32_t AIDEE; + uint32_t RESERVED1[1]; +} stc_can_acf_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t TBF; + __IO uint32_t TBE; +} stc_can_tbslot_bit_t; + +typedef struct { + __IO uint32_t TTEN; + __IO uint32_t T_PRESC0; + __IO uint32_t T_PRESC1; + __IO uint32_t TTIF; + __IO uint32_t TTIE; + __IO uint32_t TEIF; + __IO uint32_t WTIF; + __IO uint32_t WTIE; +} stc_can_ttcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t REF_IDE; +} stc_can_ref_msg_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t TTYPE0; + __IO uint32_t TTYPE1; + __IO uint32_t TTYPE2; + uint32_t RESERVED1[5]; +} stc_can_trg_cfg_bit_t; + +typedef struct { + __IO uint32_t CENB; + __IO uint32_t CWDE; + uint32_t RESERVED0[5]; + __I uint32_t CMON; +} stc_cmp_mdr_bit_t; + +typedef struct { + __IO uint32_t FCKS0; + __IO uint32_t FCKS1; + uint32_t RESERVED0[2]; + __IO uint32_t EDGS0; + __IO uint32_t EDGS1; + __IO uint32_t CIEN; + uint32_t RESERVED1[1]; +} stc_cmp_fir_bit_t; + +typedef struct { + __IO uint32_t COEN; + __IO uint32_t COPS; + __IO uint32_t CPOE; + __IO uint32_t TWOE; + __IO uint32_t TWOL; + uint32_t RESERVED0[3]; +} stc_cmp_ocr_bit_t; + +typedef struct { + __IO uint32_t RVSL0; + __IO uint32_t RVSL1; + __IO uint32_t RVSL2; + __IO uint32_t RVSL3; + __IO uint32_t CVSL0; + __IO uint32_t CVSL1; + __IO uint32_t CVSL2; + __IO uint32_t CVSL3; +} stc_cmp_pmsr_bit_t; + +typedef struct { + __IO uint32_t CTWS0; + __IO uint32_t CTWS1; + __IO uint32_t CTWS2; + __IO uint32_t CTWS3; + __IO uint32_t CTWS4; + __IO uint32_t CTWS5; + __IO uint32_t CTWS6; + __IO uint32_t CTWS7; + __IO uint32_t CTWS8; + __IO uint32_t CTWS9; + __IO uint32_t CTWS10; + __IO uint32_t CTWS11; + __IO uint32_t CTWS12; + __IO uint32_t CTWS13; + __IO uint32_t CTWS14; + __IO uint32_t CTWS15; +} stc_cmp_twsr_bit_t; + +typedef struct { + __IO uint32_t CTWP0; + __IO uint32_t CTWP1; + __IO uint32_t CTWP2; + __IO uint32_t CTWP3; + __IO uint32_t CTWP4; + __IO uint32_t CTWP5; + __IO uint32_t CTWP6; + __IO uint32_t CTWP7; + __IO uint32_t CTWP8; + __IO uint32_t CTWP9; + __IO uint32_t CTWP10; + __IO uint32_t CTWP11; + __IO uint32_t CTWP12; + __IO uint32_t CTWP13; + __IO uint32_t CTWP14; + __IO uint32_t CTWP15; +} stc_cmp_twpr_bit_t; + +typedef struct { + __IO uint32_t P2SL0; + __IO uint32_t P2SL1; + __IO uint32_t P2SL2; + uint32_t RESERVED0[1]; + __IO uint32_t P3SL0; + __IO uint32_t P3SL1; + uint32_t RESERVED1[10]; +} stc_cmp_visr_bit_t; + +typedef struct { + __IO uint32_t XTAL32STP; + uint32_t RESERVED0[7]; +} stc_cmu_xtal32cr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t XTAL32IE; + uint32_t RESERVED1[4]; +} stc_cmu_xtal32cfgr_bit_t; + +typedef struct { + __IO uint32_t LRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_lrccr_bit_t; + +typedef struct { + __IO uint32_t RTCLRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_rtclrccr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t XTALMS; + uint32_t RESERVED1[1]; +} stc_cmu_xtalcfgr_bit_t; + +typedef struct { + __IO uint32_t PLLHOFF; + uint32_t RESERVED0[7]; +} stc_cmu_pllhcr_bit_t; + +typedef struct { + __IO uint32_t PLLAOFF; + uint32_t RESERVED0[7]; +} stc_cmu_pllacr_bit_t; + +typedef struct { + __IO uint32_t XTALSTP; + uint32_t RESERVED0[7]; +} stc_cmu_xtalcr_bit_t; + +typedef struct { + __IO uint32_t HRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_hrccr_bit_t; + +typedef struct { + __IO uint32_t MRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_mrccr_bit_t; + +typedef struct { + __IO uint32_t HRCSTBF; + uint32_t RESERVED0[2]; + __IO uint32_t XTALSTBF; + uint32_t RESERVED1[1]; + __IO uint32_t PLLHSTBF; + __IO uint32_t PLLASTBF; + uint32_t RESERVED2[1]; +} stc_cmu_oscstbsr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t MCOEN; +} stc_cmu_mcocfgr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TPIUCKOE; +} stc_cmu_tpiuckcfgr_bit_t; + +typedef struct { + __IO uint32_t XTALSTDIE; + __IO uint32_t XTALSTDRE; + __IO uint32_t XTALSTDRIS; + uint32_t RESERVED0[4]; + __IO uint32_t XTALSTDE; +} stc_cmu_xtalstdcr_bit_t; + +typedef struct { + __IO uint32_t XTALSTDF; + uint32_t RESERVED0[7]; +} stc_cmu_xtalstdsr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t PLLSRC; + uint32_t RESERVED1[24]; +} stc_cmu_pllhcfgr_bit_t; + +typedef struct { + __IO uint32_t CR; + __I uint32_t FLAG; + uint32_t RESERVED0[30]; +} stc_crc_cr_bit_t; + +typedef struct { + __IO uint32_t REFPSC0; + __IO uint32_t REFPSC1; + __IO uint32_t REFPSC2; + uint32_t RESERVED0[1]; + __IO uint32_t REFCKS0; + __IO uint32_t REFCKS1; + __IO uint32_t ERRIE; + __IO uint32_t CTCEN; + uint32_t RESERVED1[24]; +} stc_ctc_cr1_bit_t; + +typedef struct { + __I uint32_t TRIMOK; + __I uint32_t TRMOVF; + __I uint32_t TRMUDF; + __I uint32_t CTCBSY; + uint32_t RESERVED0[28]; +} stc_ctc_str_bit_t; + +typedef struct { + __IO uint32_t DAEN; + __IO uint32_t DA1EN; + __IO uint32_t DA2EN; + uint32_t RESERVED0[5]; + __IO uint32_t ALIGN; + __IO uint32_t DAAMP1; + __IO uint32_t DAAMP2; + __IO uint32_t EXTDSL1; + __IO uint32_t EXTDSL2; + uint32_t RESERVED1[3]; +} stc_dac_dacr_bit_t; + +typedef struct { + __IO uint32_t ADPSL1; + __IO uint32_t ADPSL2; + __IO uint32_t ADPSL3; + uint32_t RESERVED0[5]; + __I uint32_t DA1SF; + __I uint32_t DA2SF; + uint32_t RESERVED1[5]; + __IO uint32_t ADPEN; +} stc_dac_daadpcr_bit_t; + +typedef struct { + uint32_t RESERVED0[14]; + __IO uint32_t DAODIS1; + __IO uint32_t DAODIS2; +} stc_dac_daocr_bit_t; + +typedef struct { + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t MODE2; + __IO uint32_t MODE3; + __IO uint32_t DATASIZE0; + __IO uint32_t DATASIZE1; + uint32_t RESERVED0[2]; + __IO uint32_t COMP_TRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct { + __I uint32_t FLAG_OP; + __I uint32_t FLAG_LS2; + __I uint32_t FLAG_EQ2; + __I uint32_t FLAG_GT2; + __I uint32_t FLAG_LS1; + __I uint32_t FLAG_EQ1; + __I uint32_t FLAG_GT1; + uint32_t RESERVED0[2]; + __I uint32_t FLAG_RLD; + __I uint32_t FLAG_BTM; + __I uint32_t FLAG_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flag_bit_t; + +typedef struct { + __O uint32_t CLR_OP; + __O uint32_t CLR_LS2; + __O uint32_t CLR_EQ2; + __O uint32_t CLR_GT2; + __O uint32_t CLR_LS1; + __O uint32_t CLR_EQ1; + __O uint32_t CLR_GT1; + uint32_t RESERVED0[2]; + __IO uint32_t CLR_RLD; + __IO uint32_t CLR_BTM; + __IO uint32_t CLR_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flagclr_bit_t; + +typedef struct { + __IO uint32_t INT_OP; + __IO uint32_t INT_LS2; + __IO uint32_t INT_EQ2; + __IO uint32_t INT_GT2; + __IO uint32_t INT_LS1; + __IO uint32_t INT_EQ1; + __IO uint32_t INT_GT1; + __IO uint32_t INT_WIN0; + __IO uint32_t INT_WIN1; + __IO uint32_t INT_RLD; + __IO uint32_t INT_BTM; + __IO uint32_t INT_TOP; + uint32_t RESERVED0[20]; +} stc_dcu_intsel_bit_t; + +typedef struct { + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct { + __I uint32_t TRNERR0; + __I uint32_t TRNERR1; + __I uint32_t TRNERR2; + __I uint32_t TRNERR3; + __I uint32_t TRNERR4; + __I uint32_t TRNERR5; + __I uint32_t TRNERR6; + __I uint32_t TRNERR7; + uint32_t RESERVED0[8]; + __I uint32_t REQERR0; + __I uint32_t REQERR1; + __I uint32_t REQERR2; + __I uint32_t REQERR3; + __I uint32_t REQERR4; + __I uint32_t REQERR5; + __I uint32_t REQERR6; + __I uint32_t REQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intstat0_bit_t; + +typedef struct { + __I uint32_t TC0; + __I uint32_t TC1; + __I uint32_t TC2; + __I uint32_t TC3; + __I uint32_t TC4; + __I uint32_t TC5; + __I uint32_t TC6; + __I uint32_t TC7; + uint32_t RESERVED0[8]; + __I uint32_t BTC0; + __I uint32_t BTC1; + __I uint32_t BTC2; + __I uint32_t BTC3; + __I uint32_t BTC4; + __I uint32_t BTC5; + __I uint32_t BTC6; + __I uint32_t BTC7; + uint32_t RESERVED1[8]; +} stc_dma_intstat1_bit_t; + +typedef struct { + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + __IO uint32_t MSKTRNERR4; + __IO uint32_t MSKTRNERR5; + __IO uint32_t MSKTRNERR6; + __IO uint32_t MSKTRNERR7; + uint32_t RESERVED0[8]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + __IO uint32_t MSKREQERR4; + __IO uint32_t MSKREQERR5; + __IO uint32_t MSKREQERR6; + __IO uint32_t MSKREQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intmask0_bit_t; + +typedef struct { + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + __IO uint32_t MSKTC4; + __IO uint32_t MSKTC5; + __IO uint32_t MSKTC6; + __IO uint32_t MSKTC7; + uint32_t RESERVED0[8]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + __IO uint32_t MSKBTC4; + __IO uint32_t MSKBTC5; + __IO uint32_t MSKBTC6; + __IO uint32_t MSKBTC7; + uint32_t RESERVED1[8]; +} stc_dma_intmask1_bit_t; + +typedef struct { + __IO uint32_t CLRTRNERR0; + __IO uint32_t CLRTRNERR1; + __IO uint32_t CLRTRNERR2; + __IO uint32_t CLRTRNERR3; + __IO uint32_t CLRTRNERR4; + __IO uint32_t CLRTRNERR5; + __IO uint32_t CLRTRNERR6; + __IO uint32_t CLRTRNERR7; + uint32_t RESERVED0[8]; + __IO uint32_t CLRREQERR0; + __IO uint32_t CLRREQERR1; + __IO uint32_t CLRREQERR2; + __IO uint32_t CLRREQERR3; + __IO uint32_t CLRREQERR4; + __IO uint32_t CLRREQERR5; + __IO uint32_t CLRREQERR6; + __IO uint32_t CLRREQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intclr0_bit_t; + +typedef struct { + __IO uint32_t CLRTC0; + __IO uint32_t CLRTC1; + __IO uint32_t CLRTC2; + __IO uint32_t CLRTC3; + __IO uint32_t CLRTC4; + __IO uint32_t CLRTC5; + __IO uint32_t CLRTC6; + __IO uint32_t CLRTC7; + uint32_t RESERVED0[8]; + __IO uint32_t CLRBTC0; + __IO uint32_t CLRBTC1; + __IO uint32_t CLRBTC2; + __IO uint32_t CLRBTC3; + __IO uint32_t CLRBTC4; + __IO uint32_t CLRBTC5; + __IO uint32_t CLRBTC6; + __IO uint32_t CLRBTC7; + uint32_t RESERVED1[8]; +} stc_dma_intclr1_bit_t; + +typedef struct { + __IO uint32_t CHEN0; + __IO uint32_t CHEN1; + __IO uint32_t CHEN2; + __IO uint32_t CHEN3; + __IO uint32_t CHEN4; + __IO uint32_t CHEN5; + __IO uint32_t CHEN6; + __IO uint32_t CHEN7; + uint32_t RESERVED0[24]; +} stc_dma_chen_bit_t; + +typedef struct { + __I uint32_t CHREQ0; + __I uint32_t CHREQ1; + __I uint32_t CHREQ2; + __I uint32_t CHREQ3; + __I uint32_t CHREQ4; + __I uint32_t CHREQ5; + __I uint32_t CHREQ6; + __I uint32_t CHREQ7; + uint32_t RESERVED0[7]; + __I uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct { + __I uint32_t DMAACT; + __I uint32_t RCFGACT; + uint32_t RESERVED0[14]; + __I uint32_t CHACT0; + __I uint32_t CHACT1; + __I uint32_t CHACT2; + __I uint32_t CHACT3; + __I uint32_t CHACT4; + __I uint32_t CHACT5; + __I uint32_t CHACT6; + __I uint32_t CHACT7; + uint32_t RESERVED1[8]; +} stc_dma_chstat_bit_t; + +typedef struct { + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[14]; + __IO uint32_t SARMD0; + __IO uint32_t SARMD1; + __IO uint32_t DARMD0; + __IO uint32_t DARMD1; + __IO uint32_t CNTMD0; + __IO uint32_t CNTMD1; + uint32_t RESERVED1[10]; +} stc_dma_rcfgctl_bit_t; + +typedef struct { + __IO uint32_t CHENCLR0; + __IO uint32_t CHENCLR1; + __IO uint32_t CHENCLR2; + __IO uint32_t CHENCLR3; + __IO uint32_t CHENCLR4; + __IO uint32_t CHENCLR5; + __IO uint32_t CHENCLR6; + __IO uint32_t CHENCLR7; + uint32_t RESERVED0[24]; +} stc_dma_chenclr_bit_t; + +typedef struct { + __IO uint32_t SINC0; + __IO uint32_t SINC1; + __IO uint32_t DINC0; + __IO uint32_t DINC1; + __IO uint32_t SRPTEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + __IO uint32_t HSIZE0; + __IO uint32_t HSIZE1; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED0[19]; +} stc_dma_chctl_bit_t; + +typedef struct { + __IO uint32_t CAPEN; + __IO uint32_t CAPMD; + __IO uint32_t CROPEN; + __IO uint32_t JPEGEN; + __IO uint32_t SWSYNC; + __IO uint32_t PIXCKSEL; + __IO uint32_t HSYNCSEL; + __IO uint32_t VSYNCSEL; + __IO uint32_t CAPFRC0; + __IO uint32_t CAPFRC1; + __IO uint32_t BITSEL0; + __IO uint32_t BITSEL1; + uint32_t RESERVED0[2]; + __IO uint32_t DVPEN; + uint32_t RESERVED1[17]; +} stc_dvp_ctr_bit_t; + +typedef struct { + __IO uint32_t FSF; + __IO uint32_t LSF; + __IO uint32_t LEF; + __IO uint32_t FEF; + __IO uint32_t SQUERF; + __IO uint32_t FIFOERF; + uint32_t RESERVED0[26]; +} stc_dvp_str_bit_t; + +typedef struct { + __IO uint32_t FSIEN; + __IO uint32_t LSIEN; + __IO uint32_t LEIEN; + __IO uint32_t FEIEN; + __IO uint32_t SQUERIEN; + __IO uint32_t FIFOERIEN; + uint32_t RESERVED0[26]; +} stc_dvp_ier_bit_t; + +typedef struct { + __IO uint32_t F0STP; + __IO uint32_t F1STP; + uint32_t RESERVED0[30]; +} stc_efm_fstp_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t ICACHE; + __IO uint32_t DCACHE; + __IO uint32_t PREFETE; + __IO uint32_t CRST; + uint32_t RESERVED2[12]; +} stc_efm_frmc_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[7]; + __IO uint32_t KEY1LOCK; + __IO uint32_t KEY2LOCK; + uint32_t RESERVED2[14]; +} stc_efm_fwmc_bit_t; + +typedef struct { + __I uint32_t OTPWERR0; + __I uint32_t PRTWERR0; + __I uint32_t PGSZERR0; + __I uint32_t MISMTCH0; + __I uint32_t OPTEND0; + __I uint32_t COLERR0; + uint32_t RESERVED0[2]; + __I uint32_t RDY0; + uint32_t RESERVED1[8]; + __I uint32_t PRTWERR1; + __I uint32_t PGSZERR1; + __I uint32_t MISMTCH1; + __I uint32_t OPTEND1; + __I uint32_t COLERR1; + uint32_t RESERVED2[2]; + __I uint32_t RDY1; + uint32_t RESERVED3[7]; +} stc_efm_fsr_bit_t; + +typedef struct { + __IO uint32_t OTPWERRCLR0; + __IO uint32_t PRTWERRCLR0; + __IO uint32_t PGSZERRCLR0; + __IO uint32_t MISMTCHCLR0; + __IO uint32_t OPTENDCLR0; + __IO uint32_t COLERRCLR0; + uint32_t RESERVED0[11]; + __IO uint32_t PRTWERRCLR1; + __IO uint32_t PGSZERRCLR1; + __IO uint32_t MISMTCHCLR1; + __IO uint32_t OPTENDCLR1; + __IO uint32_t COLERRCLR1; + uint32_t RESERVED1[10]; +} stc_efm_fsclr_bit_t; + +typedef struct { + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct { + __I uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t EN; +} stc_efm_mmf_remcr_bit_t; + +typedef struct { + __IO uint32_t WLOCK0; + __IO uint32_t WLOCK1; + __IO uint32_t WLOCK2; + __IO uint32_t WLOCK3; + __IO uint32_t WLOCK4; + __IO uint32_t WLOCK5; + __IO uint32_t WLOCK6; + __IO uint32_t WLOCK7; + uint32_t RESERVED0[24]; +} stc_efm_wlock_bit_t; + +typedef struct { + __IO uint32_t F0NWPRT0; + __IO uint32_t F0NWPRT1; + __IO uint32_t F0NWPRT2; + __IO uint32_t F0NWPRT3; + __IO uint32_t F0NWPRT4; + __IO uint32_t F0NWPRT5; + __IO uint32_t F0NWPRT6; + __IO uint32_t F0NWPRT7; + __IO uint32_t F0NWPRT8; + __IO uint32_t F0NWPRT9; + __IO uint32_t F0NWPRT10; + __IO uint32_t F0NWPRT11; + __IO uint32_t F0NWPRT12; + __IO uint32_t F0NWPRT13; + __IO uint32_t F0NWPRT14; + __IO uint32_t F0NWPRT15; + __IO uint32_t F0NWPRT16; + __IO uint32_t F0NWPRT17; + __IO uint32_t F0NWPRT18; + __IO uint32_t F0NWPRT19; + __IO uint32_t F0NWPRT20; + __IO uint32_t F0NWPRT21; + __IO uint32_t F0NWPRT22; + __IO uint32_t F0NWPRT23; + __IO uint32_t F0NWPRT24; + __IO uint32_t F0NWPRT25; + __IO uint32_t F0NWPRT26; + __IO uint32_t F0NWPRT27; + __IO uint32_t F0NWPRT28; + __IO uint32_t F0NWPRT29; + __IO uint32_t F0NWPRT30; + __IO uint32_t F0NWPRT31; +} stc_efm_f0nwprt0_bit_t; + +typedef struct { + __IO uint32_t F0NWPRT32; + __IO uint32_t F0NWPRT33; + __IO uint32_t F0NWPRT34; + __IO uint32_t F0NWPRT35; + __IO uint32_t F0NWPRT36; + __IO uint32_t F0NWPRT37; + __IO uint32_t F0NWPRT38; + __IO uint32_t F0NWPRT39; + __IO uint32_t F0NWPRT40; + __IO uint32_t F0NWPRT41; + __IO uint32_t F0NWPRT42; + __IO uint32_t F0NWPRT43; + __IO uint32_t F0NWPRT44; + __IO uint32_t F0NWPRT45; + __IO uint32_t F0NWPRT46; + __IO uint32_t F0NWPRT47; + __IO uint32_t F0NWPRT48; + __IO uint32_t F0NWPRT49; + __IO uint32_t F0NWPRT50; + __IO uint32_t F0NWPRT51; + __IO uint32_t F0NWPRT52; + __IO uint32_t F0NWPRT53; + __IO uint32_t F0NWPRT54; + __IO uint32_t F0NWPRT55; + __IO uint32_t F0NWPRT56; + __IO uint32_t F0NWPRT57; + __IO uint32_t F0NWPRT58; + __IO uint32_t F0NWPRT59; + __IO uint32_t F0NWPRT60; + __IO uint32_t F0NWPRT61; + __IO uint32_t F0NWPRT62; + __IO uint32_t F0NWPRT63; +} stc_efm_f0nwprt1_bit_t; + +typedef struct { + __IO uint32_t F0NWPRT64; + __IO uint32_t F0NWPRT65; + __IO uint32_t F0NWPRT66; + __IO uint32_t F0NWPRT67; + __IO uint32_t F0NWPRT68; + __IO uint32_t F0NWPRT69; + __IO uint32_t F0NWPRT70; + __IO uint32_t F0NWPRT71; + __IO uint32_t F0NWPRT72; + __IO uint32_t F0NWPRT73; + __IO uint32_t F0NWPRT74; + __IO uint32_t F0NWPRT75; + __IO uint32_t F0NWPRT76; + __IO uint32_t F0NWPRT77; + __IO uint32_t F0NWPRT78; + __IO uint32_t F0NWPRT79; + __IO uint32_t F0NWPRT80; + __IO uint32_t F0NWPRT81; + __IO uint32_t F0NWPRT82; + __IO uint32_t F0NWPRT83; + __IO uint32_t F0NWPRT84; + __IO uint32_t F0NWPRT85; + __IO uint32_t F0NWPRT86; + __IO uint32_t F0NWPRT87; + __IO uint32_t F0NWPRT88; + __IO uint32_t F0NWPRT89; + __IO uint32_t F0NWPRT90; + __IO uint32_t F0NWPRT91; + __IO uint32_t F0NWPRT92; + __IO uint32_t F0NWPRT93; + __IO uint32_t F0NWPRT94; + __IO uint32_t F0NWPRT95; +} stc_efm_f0nwprt2_bit_t; + +typedef struct { + __IO uint32_t F0NWPRT96; + __IO uint32_t F0NWPRT97; + __IO uint32_t F0NWPRT98; + __IO uint32_t F0NWPRT99; + __IO uint32_t F0NWPRT100; + __IO uint32_t F0NWPRT101; + __IO uint32_t F0NWPRT102; + __IO uint32_t F0NWPRT103; + __IO uint32_t F0NWPRT104; + __IO uint32_t F0NWPRT105; + __IO uint32_t F0NWPRT106; + __IO uint32_t F0NWPRT107; + __IO uint32_t F0NWPRT108; + __IO uint32_t F0NWPRT109; + __IO uint32_t F0NWPRT110; + __IO uint32_t F0NWPRT111; + __IO uint32_t F0NWPRT112; + __IO uint32_t F0NWPRT113; + __IO uint32_t F0NWPRT114; + __IO uint32_t F0NWPRT115; + __IO uint32_t F0NWPRT116; + __IO uint32_t F0NWPRT117; + __IO uint32_t F0NWPRT118; + __IO uint32_t F0NWPRT119; + __IO uint32_t F0NWPRT120; + __IO uint32_t F0NWPRT121; + __IO uint32_t F0NWPRT122; + __IO uint32_t F0NWPRT123; + __IO uint32_t F0NWPRT124; + __IO uint32_t F0NWPRT125; + __IO uint32_t F0NWPRT126; + __IO uint32_t F0NWPRT127; +} stc_efm_f0nwprt3_bit_t; + +typedef struct { + __IO uint32_t F1NWPRT0; + __IO uint32_t F1NWPRT1; + __IO uint32_t F1NWPRT2; + __IO uint32_t F1NWPRT3; + __IO uint32_t F1NWPRT4; + __IO uint32_t F1NWPRT5; + __IO uint32_t F1NWPRT6; + __IO uint32_t F1NWPRT7; + __IO uint32_t F1NWPRT8; + __IO uint32_t F1NWPRT9; + __IO uint32_t F1NWPRT10; + __IO uint32_t F1NWPRT11; + __IO uint32_t F1NWPRT12; + __IO uint32_t F1NWPRT13; + __IO uint32_t F1NWPRT14; + __IO uint32_t F1NWPRT15; + __IO uint32_t F1NWPRT16; + __IO uint32_t F1NWPRT17; + __IO uint32_t F1NWPRT18; + __IO uint32_t F1NWPRT19; + __IO uint32_t F1NWPRT20; + __IO uint32_t F1NWPRT21; + __IO uint32_t F1NWPRT22; + __IO uint32_t F1NWPRT23; + __IO uint32_t F1NWPRT24; + __IO uint32_t F1NWPRT25; + __IO uint32_t F1NWPRT26; + __IO uint32_t F1NWPRT27; + __IO uint32_t F1NWPRT28; + __IO uint32_t F1NWPRT29; + __IO uint32_t F1NWPRT30; + __IO uint32_t F1NWPRT31; +} stc_efm_f1nwprt0_bit_t; + +typedef struct { + __IO uint32_t F1NWPRT32; + __IO uint32_t F1NWPRT33; + __IO uint32_t F1NWPRT34; + __IO uint32_t F1NWPRT35; + __IO uint32_t F1NWPRT36; + __IO uint32_t F1NWPRT37; + __IO uint32_t F1NWPRT38; + __IO uint32_t F1NWPRT39; + __IO uint32_t F1NWPRT40; + __IO uint32_t F1NWPRT41; + __IO uint32_t F1NWPRT42; + __IO uint32_t F1NWPRT43; + __IO uint32_t F1NWPRT44; + __IO uint32_t F1NWPRT45; + __IO uint32_t F1NWPRT46; + __IO uint32_t F1NWPRT47; + __IO uint32_t F1NWPRT48; + __IO uint32_t F1NWPRT49; + __IO uint32_t F1NWPRT50; + __IO uint32_t F1NWPRT51; + __IO uint32_t F1NWPRT52; + __IO uint32_t F1NWPRT53; + __IO uint32_t F1NWPRT54; + __IO uint32_t F1NWPRT55; + __IO uint32_t F1NWPRT56; + __IO uint32_t F1NWPRT57; + __IO uint32_t F1NWPRT58; + __IO uint32_t F1NWPRT59; + __IO uint32_t F1NWPRT60; + __IO uint32_t F1NWPRT61; + __IO uint32_t F1NWPRT62; + __IO uint32_t F1NWPRT63; +} stc_efm_f1nwprt1_bit_t; + +typedef struct { + __IO uint32_t F1NWPRT64; + __IO uint32_t F1NWPRT65; + __IO uint32_t F1NWPRT66; + __IO uint32_t F1NWPRT67; + __IO uint32_t F1NWPRT68; + __IO uint32_t F1NWPRT69; + __IO uint32_t F1NWPRT70; + __IO uint32_t F1NWPRT71; + __IO uint32_t F1NWPRT72; + __IO uint32_t F1NWPRT73; + __IO uint32_t F1NWPRT74; + __IO uint32_t F1NWPRT75; + __IO uint32_t F1NWPRT76; + __IO uint32_t F1NWPRT77; + __IO uint32_t F1NWPRT78; + __IO uint32_t F1NWPRT79; + __IO uint32_t F1NWPRT80; + __IO uint32_t F1NWPRT81; + __IO uint32_t F1NWPRT82; + __IO uint32_t F1NWPRT83; + __IO uint32_t F1NWPRT84; + __IO uint32_t F1NWPRT85; + __IO uint32_t F1NWPRT86; + __IO uint32_t F1NWPRT87; + __IO uint32_t F1NWPRT88; + __IO uint32_t F1NWPRT89; + __IO uint32_t F1NWPRT90; + __IO uint32_t F1NWPRT91; + __IO uint32_t F1NWPRT92; + __IO uint32_t F1NWPRT93; + __IO uint32_t F1NWPRT94; + __IO uint32_t F1NWPRT95; +} stc_efm_f1nwprt2_bit_t; + +typedef struct { + __IO uint32_t F1NWPRT96; + __IO uint32_t F1NWPRT97; + __IO uint32_t F1NWPRT98; + __IO uint32_t F1NWPRT99; + __IO uint32_t F1NWPRT100; + __IO uint32_t F1NWPRT101; + __IO uint32_t F1NWPRT102; + __IO uint32_t F1NWPRT103; + __IO uint32_t F1NWPRT104; + __IO uint32_t F1NWPRT105; + __IO uint32_t F1NWPRT106; + __IO uint32_t F1NWPRT107; + __IO uint32_t F1NWPRT108; + __IO uint32_t F1NWPRT109; + __IO uint32_t F1NWPRT110; + __IO uint32_t F1NWPRT111; + __IO uint32_t F1NWPRT112; + __IO uint32_t F1NWPRT113; + __IO uint32_t F1NWPRT114; + __IO uint32_t F1NWPRT115; + __IO uint32_t F1NWPRT116; + __IO uint32_t F1NWPRT117; + __IO uint32_t F1NWPRT118; + __IO uint32_t F1NWPRT119; + __IO uint32_t F1NWPRT120; + __IO uint32_t F1NWPRT121; + __IO uint32_t F1NWPRT122; + __IO uint32_t F1NWPRT123; + __IO uint32_t F1NWPRT124; + __IO uint32_t F1NWPRT125; + __IO uint32_t F1NWPRT126; + __IO uint32_t F1NWPRT127; +} stc_efm_f1nwprt3_bit_t; + +typedef struct { + __IO uint32_t CMPEN0; + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + __IO uint32_t OSCSTPEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + __IO uint32_t PWMSEN3; + __IO uint32_t PWMSEN4; + __IO uint32_t PWMSEN5; + __IO uint32_t PWMSEN6; + __IO uint32_t PWMSEN7; + uint32_t RESERVED0[3]; + __IO uint32_t PORTINEN1; + __IO uint32_t PORTINEN2; + __IO uint32_t PORTINEN3; + __IO uint32_t PORTINEN4; + uint32_t RESERVED1[2]; + __IO uint32_t INVSEL1; + __IO uint32_t INVSEL2; + __IO uint32_t INVSEL3; + __IO uint32_t INVSEL4; + uint32_t RESERVED2[6]; +} stc_emb_ctl1_bit_t; + +typedef struct { + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + __IO uint32_t PWMLV3; + __IO uint32_t PWMLV4; + __IO uint32_t PWMLV5; + __IO uint32_t PWMLV6; + __IO uint32_t PWMLV7; + uint32_t RESERVED0[10]; + __IO uint32_t NFEN1; + uint32_t RESERVED1[2]; + __IO uint32_t NFEN2; + uint32_t RESERVED2[2]; + __IO uint32_t NFEN3; + uint32_t RESERVED3[2]; + __IO uint32_t NFEN4; + uint32_t RESERVED4[4]; +} stc_emb_ctl2_bit_t; + +typedef struct { + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t PWMSF; + __I uint32_t CMPF; + __I uint32_t OSF; + uint32_t RESERVED1[1]; + __I uint32_t PWMST; + __I uint32_t CMPST; + __I uint32_t OSST; + __I uint32_t PORTINF1; + __I uint32_t PORTINF2; + __I uint32_t PORTINF3; + __I uint32_t PORTINF4; + uint32_t RESERVED2[2]; + __I uint32_t PORTINST1; + __I uint32_t PORTINST2; + __I uint32_t PORTINST3; + __I uint32_t PORTINST4; + uint32_t RESERVED3[14]; +} stc_emb_stat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __O uint32_t PWMSFCLR; + __O uint32_t CMPFCLR; + __O uint32_t OSFCLR; + uint32_t RESERVED1[4]; + __O uint32_t PORTINFCLR1; + __O uint32_t PORTINFCLR2; + __O uint32_t PORTINFCLR3; + __O uint32_t PORTINFCLR4; + uint32_t RESERVED2[20]; +} stc_emb_statclr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t OSINTEN; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINTEN1; + __IO uint32_t PORTINTEN2; + __IO uint32_t PORTINTEN3; + __IO uint32_t PORTINTEN4; + uint32_t RESERVED2[20]; +} stc_emb_inten_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t PWMRSEL; + __IO uint32_t CMPRSEL; + __IO uint32_t OSRSEL; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINRSEL1; + __IO uint32_t PORTINRSEL2; + __IO uint32_t PORTINRSEL3; + __IO uint32_t PORTINRSEL4; + uint32_t RESERVED2[20]; +} stc_emb_rlssel_bit_t; + +typedef struct { + __IO uint32_t IFSEL; + uint32_t RESERVED0[3]; + __IO uint32_t RCKINV; + __IO uint32_t TCKINV; + uint32_t RESERVED1[26]; +} stc_eth_mac_ifconfr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t DC; + __IO uint32_t BL0; + __IO uint32_t BL1; + __IO uint32_t ACS; + uint32_t RESERVED1[1]; + __IO uint32_t DRTY; + __IO uint32_t IPCO; + __IO uint32_t DM; + __IO uint32_t LM; + __IO uint32_t DO; + __IO uint32_t FES; + uint32_t RESERVED2[1]; + __IO uint32_t DCRS; + __IO uint32_t IFG0; + __IO uint32_t IFG1; + __IO uint32_t IFG2; + uint32_t RESERVED3[2]; + __IO uint32_t MJB; + __IO uint32_t MWD; + uint32_t RESERVED4[1]; + __IO uint32_t CST; + uint32_t RESERVED5[2]; + __IO uint32_t SAIRC0; + __IO uint32_t SAIRC1; + __IO uint32_t SAIRC2; + uint32_t RESERVED6[1]; +} stc_eth_mac_configr_bit_t; + +typedef struct { + __IO uint32_t PR; + __IO uint32_t HUC; + __IO uint32_t HMC; + __IO uint32_t DAIF; + __IO uint32_t PMF; + __IO uint32_t DBF; + __IO uint32_t PCF0; + __IO uint32_t PCF1; + __IO uint32_t SAIF; + __IO uint32_t SAF; + __IO uint32_t HPF; + uint32_t RESERVED0[5]; + __IO uint32_t VTFE; + uint32_t RESERVED1[3]; + __IO uint32_t IPFE; + __IO uint32_t DNTU; + uint32_t RESERVED2[9]; + __IO uint32_t RA; +} stc_eth_mac_fltctlr_bit_t; + +typedef struct { + __IO uint32_t SMIB; + __IO uint32_t SMIW; + __IO uint32_t SMIC0; + __IO uint32_t SMIC1; + __IO uint32_t SMIC2; + __IO uint32_t SMIC3; + __IO uint32_t SMIR0; + __IO uint32_t SMIR1; + __IO uint32_t SMIR2; + __IO uint32_t SMIR3; + __IO uint32_t SMIR4; + __IO uint32_t SMIA0; + __IO uint32_t SMIA1; + __IO uint32_t SMIA2; + __IO uint32_t SMIA3; + __IO uint32_t SMIA4; + uint32_t RESERVED0[16]; +} stc_eth_mac_smiaddr_bit_t; + +typedef struct { + __IO uint32_t FCA_BPA; + __IO uint32_t TFE; + __IO uint32_t RFE; + __IO uint32_t UNP; + __IO uint32_t PLT0; + __IO uint32_t PLT1; + uint32_t RESERVED0[1]; + __IO uint32_t DZPQ; + uint32_t RESERVED1[24]; +} stc_eth_mac_floctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t VTAL; + __IO uint32_t VTIM; + uint32_t RESERVED1[1]; + __IO uint32_t VTHM; + uint32_t RESERVED2[12]; +} stc_eth_mac_vtafltr_bit_t; + +typedef struct { + __I uint32_t MREA; + __I uint32_t MRS0; + __I uint32_t MRS1; + uint32_t RESERVED0[1]; + __I uint32_t RFWA; + __I uint32_t RFRS0; + __I uint32_t RFRS1; + uint32_t RESERVED1[1]; + __I uint32_t RFFL0; + __I uint32_t RFFL1; + uint32_t RESERVED2[6]; + __I uint32_t MTEA; + __I uint32_t MTS0; + __I uint32_t MTS1; + __I uint32_t MTP; + __I uint32_t TFRS0; + __I uint32_t TFRS1; + __I uint32_t TFWA; + uint32_t RESERVED3[1]; + __I uint32_t TFNE; + __I uint32_t TFF; + uint32_t RESERVED4[6]; +} stc_eth_mac_macstsr_bit_t; + +typedef struct { + __IO uint32_t PWDN; + __IO uint32_t MPEN; + __IO uint32_t WKEN; + uint32_t RESERVED0[2]; + __I uint32_t MPFR; + __I uint32_t WKFR; + uint32_t RESERVED1[2]; + __IO uint32_t GLUB; + __IO uint32_t RTWKTR; + uint32_t RESERVED2[13]; + __I uint32_t RTWKPT0; + __I uint32_t RTWKPT1; + __I uint32_t RTWKPT2; + uint32_t RESERVED3[4]; + __IO uint32_t RTWKFR; +} stc_eth_mac_pmtctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __I uint32_t PMTIS; + __I uint32_t MMCIS; + __I uint32_t MMCRXIS; + __I uint32_t MMCTXIS; + uint32_t RESERVED1[2]; + __I uint32_t TSPIS; + uint32_t RESERVED2[22]; +} stc_eth_mac_intstsr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t PMTIM; + uint32_t RESERVED1[5]; + __IO uint32_t TSPIM; + uint32_t RESERVED2[22]; +} stc_eth_mac_intmskr_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __I uint32_t AE0; +} stc_eth_mac_macadhr0_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __IO uint32_t MBC10; + __IO uint32_t MBC11; + __IO uint32_t MBC12; + __IO uint32_t MBC13; + __IO uint32_t MBC14; + __IO uint32_t MBC15; + __IO uint32_t SA1; + __IO uint32_t AE1; +} stc_eth_mac_macadhr1_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __IO uint32_t MBC20; + __IO uint32_t MBC21; + __IO uint32_t MBC22; + __IO uint32_t MBC23; + __IO uint32_t MBC24; + __IO uint32_t MBC25; + __IO uint32_t SA2; + __IO uint32_t AE2; +} stc_eth_mac_macadhr2_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __IO uint32_t MBC30; + __IO uint32_t MBC31; + __IO uint32_t MBC32; + __IO uint32_t MBC33; + __IO uint32_t MBC34; + __IO uint32_t MBC35; + __IO uint32_t SA3; + __IO uint32_t AE3; +} stc_eth_mac_macadhr3_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __IO uint32_t MBC40; + __IO uint32_t MBC41; + __IO uint32_t MBC42; + __IO uint32_t MBC43; + __IO uint32_t MBC44; + __IO uint32_t MBC45; + __IO uint32_t SA4; + __IO uint32_t AE4; +} stc_eth_mac_macadhr4_bit_t; + +typedef struct { + __IO uint32_t CRST; + __IO uint32_t COS; + __IO uint32_t ROR; + __IO uint32_t MCF; + __IO uint32_t MCPSET; + __IO uint32_t MCPSEL; + uint32_t RESERVED0[26]; +} stc_eth_mmc_mmcctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __I uint32_t RXBGIS; + __I uint32_t RXMGIS; + __I uint32_t RXCEIS; + __I uint32_t RXAEIS; + __I uint32_t RXREIS; + uint32_t RESERVED1[9]; + __I uint32_t RXUGIS; + __I uint32_t RXLEIS; + __I uint32_t RXOEIS; + uint32_t RESERVED2[12]; +} stc_eth_mmc_revstsr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __I uint32_t TXBGIS; + __I uint32_t TXMGIS; + uint32_t RESERVED1[12]; + __I uint32_t TXDEEIS; + __I uint32_t TXLCEIS; + __I uint32_t TXECEIS; + __I uint32_t TXCAEIS; + uint32_t RESERVED2[1]; + __I uint32_t TXUGIS; + __I uint32_t TXEDEIS; + uint32_t RESERVED3[9]; +} stc_eth_mmc_trsstsr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RXBGIM; + __IO uint32_t RXMGIM; + __IO uint32_t RXCEIM; + __IO uint32_t RXAEIM; + __IO uint32_t RXREIM; + uint32_t RESERVED1[9]; + __IO uint32_t RXUGIM; + __IO uint32_t RXLEIM; + __IO uint32_t RXOEIM; + uint32_t RESERVED2[12]; +} stc_eth_mmc_ritctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t TXBGIM; + __IO uint32_t TXMGIM; + uint32_t RESERVED1[12]; + __IO uint32_t TXDEEIM; + __IO uint32_t TXLCEIM; + __IO uint32_t TXECEIM; + __IO uint32_t TXCAEIM; + uint32_t RESERVED2[1]; + __IO uint32_t TXUGIM; + __IO uint32_t TXEDEIM; + uint32_t RESERVED3[9]; +} stc_eth_mmc_titctlr_bit_t; + +typedef struct { + __IO uint32_t L3PEN; + uint32_t RESERVED0[1]; + __IO uint32_t L3SAM; + __IO uint32_t L3SAIM; + __IO uint32_t L3DAM; + __IO uint32_t L3DAIM; + __IO uint32_t L3HSBM0; + __IO uint32_t L3HSBM1; + __IO uint32_t L3HSBM2; + __IO uint32_t L3HSBM3; + __IO uint32_t L3HSBM4; + __IO uint32_t L3HDBM0; + __IO uint32_t L3HDBM1; + __IO uint32_t L3HDBM2; + __IO uint32_t L3HDBM3; + __IO uint32_t L3HDBM4; + __IO uint32_t L4PEN; + uint32_t RESERVED1[1]; + __IO uint32_t L4SPM; + __IO uint32_t L4SPIM; + __IO uint32_t L4DPM; + __IO uint32_t L4DPIM; + uint32_t RESERVED2[10]; +} stc_eth_mac_l34ctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t VLANC0; + __IO uint32_t VLANC1; + __IO uint32_t VLANS; + uint32_t RESERVED1[13]; +} stc_eth_mac_vtactlr_bit_t; + +typedef struct { + __IO uint32_t TSPEN; + __IO uint32_t TSPUPSEL; + __IO uint32_t TSPINI; + __IO uint32_t TSPUP; + __IO uint32_t TSPINT; + __IO uint32_t TSPADUP; + uint32_t RESERVED0[2]; + __IO uint32_t TSPEALL; + __IO uint32_t TSPSSR; + __IO uint32_t TSPVER; + __IO uint32_t TSPOVETH; + __IO uint32_t TSPOVIPV6; + __IO uint32_t TSPOVIPV4; + __IO uint32_t TSPMTSEL0; + __IO uint32_t TSPMTSEL1; + __IO uint32_t TSPMTSEL2; + __IO uint32_t TSPMTSEL3; + __IO uint32_t TSPADF; + uint32_t RESERVED1[13]; +} stc_eth_ptp_tspctlr_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t TSPUPNS; +} stc_eth_ptp_tmunser_bit_t; + +typedef struct { + __I uint32_t TSOVF; + __I uint32_t TSTAR0; + uint32_t RESERVED0[1]; + __I uint32_t TSERR0; + __I uint32_t TSTAR1; + __I uint32_t TSERR1; + uint32_t RESERVED1[26]; +} stc_eth_ptp_tspstsr_bit_t; + +typedef struct { + __IO uint32_t PPSFRE00; + __IO uint32_t PPSFRE01; + __IO uint32_t PPSFRE02; + __IO uint32_t PPSFRE03; + __IO uint32_t PPSOMD; + __IO uint32_t TT0SEL0; + __IO uint32_t TT0SEL1; + uint32_t RESERVED0[1]; + __IO uint32_t PPSFRE10; + __IO uint32_t PPSFRE11; + __IO uint32_t PPSFRE12; + uint32_t RESERVED1[2]; + __IO uint32_t TT1SEL0; + __IO uint32_t TT1SEL1; + uint32_t RESERVED2[17]; +} stc_eth_ptp_ppsctlr_bit_t; + +typedef struct { + __IO uint32_t SWR; + __IO uint32_t DMAA; + __IO uint32_t DSL0; + __IO uint32_t DSL1; + __IO uint32_t DSL2; + __IO uint32_t DSL3; + __IO uint32_t DSL4; + __IO uint32_t DSEN; + __IO uint32_t TPBL0; + __IO uint32_t TPBL1; + __IO uint32_t TPBL2; + __IO uint32_t TPBL3; + __IO uint32_t TPBL4; + __IO uint32_t TPBL5; + __IO uint32_t PRAT0; + __IO uint32_t PRAT1; + __IO uint32_t FBST; + __IO uint32_t RPBL0; + __IO uint32_t RPBL1; + __IO uint32_t RPBL2; + __IO uint32_t RPBL3; + __IO uint32_t RPBL4; + __IO uint32_t RPBL5; + __IO uint32_t SPBL; + __IO uint32_t M8PBL; + __IO uint32_t AAL; + __IO uint32_t MBST; + __IO uint32_t TXPR; + uint32_t RESERVED0[4]; +} stc_eth_dma_busmodr_bit_t; + +typedef struct { + __IO uint32_t TIS; + __IO uint32_t TSS; + __IO uint32_t TUS; + __IO uint32_t TJS; + __IO uint32_t OVS; + __IO uint32_t UNS; + __IO uint32_t RIS; + __IO uint32_t RUS; + __IO uint32_t RSS; + __IO uint32_t RWS; + __IO uint32_t ETS; + uint32_t RESERVED0[2]; + __IO uint32_t FBS; + __IO uint32_t ERS; + __IO uint32_t AIS; + __IO uint32_t NIS; + __I uint32_t RSTS0; + __I uint32_t RSTS1; + __I uint32_t RSTS2; + __I uint32_t TSTS0; + __I uint32_t TSTS1; + __I uint32_t TSTS2; + __I uint32_t EBUS0; + __I uint32_t EBUS1; + __I uint32_t EBUS2; + uint32_t RESERVED1[1]; + __I uint32_t MMCS; + __I uint32_t PMTS; + __I uint32_t PTPS; + uint32_t RESERVED2[2]; +} stc_eth_dma_dmastsr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t STR; + __IO uint32_t OSF; + __IO uint32_t RTC0; + __IO uint32_t RTC1; + __IO uint32_t DGF; + __IO uint32_t FUF; + __IO uint32_t FEF; + uint32_t RESERVED1[5]; + __IO uint32_t STT; + __IO uint32_t TTC0; + __IO uint32_t TTC1; + __IO uint32_t TTC2; + uint32_t RESERVED2[3]; + __IO uint32_t FTF; + __IO uint32_t TSF; + uint32_t RESERVED3[2]; + __IO uint32_t DFRF; + __IO uint32_t RSF; + __IO uint32_t DTCOE; + uint32_t RESERVED4[5]; +} stc_eth_dma_oprmodr_bit_t; + +typedef struct { + __IO uint32_t TIE; + __IO uint32_t TSE; + __IO uint32_t TUE; + __IO uint32_t TJE; + __IO uint32_t OVE; + __IO uint32_t UNE; + __IO uint32_t RIE; + __IO uint32_t RUE; + __IO uint32_t RSE; + __IO uint32_t RWE; + __IO uint32_t ETE; + uint32_t RESERVED0[2]; + __IO uint32_t FBE; + __IO uint32_t ERE; + __IO uint32_t AIE; + __IO uint32_t NIE; + uint32_t RESERVED1[15]; +} stc_eth_dma_intenar_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __I uint32_t UNAOVF; + uint32_t RESERVED1[11]; + __I uint32_t OVFOVF; + uint32_t RESERVED2[3]; +} stc_eth_dma_rfrcntr_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + __IO uint32_t DNFS0; + __IO uint32_t DNFS1; + uint32_t RESERVED1[2]; + __IO uint32_t EDGES0; + __IO uint32_t EDGES1; + uint32_t RESERVED2[1]; + __IO uint32_t EXREFE; + uint32_t RESERVED3[16]; +} stc_fcm_rccr_bit_t; + +typedef struct { + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct { + __I uint32_t ERRF; + __I uint32_t MENDF; + __I uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct { + __O uint32_t ERRFCLR; + __O uint32_t MENDFCLR; + __O uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct { + __IO uint32_t FMACEN; + uint32_t RESERVED0[31]; +} stc_fmac_enr_bit_t; + +typedef struct { + __IO uint32_t INTEN; + uint32_t RESERVED0[31]; +} stc_fmac_ier_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t READY; +} stc_fmac_str_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + __I uint32_t PIN14; + __I uint32_t PIN15; +} stc_gpio_pidr_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podr_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poer_bit_t; + +typedef struct { + __O uint32_t POS00; + __O uint32_t POS01; + __O uint32_t POS02; + __O uint32_t POS03; + __O uint32_t POS04; + __O uint32_t POS05; + __O uint32_t POS06; + __O uint32_t POS07; + __O uint32_t POS08; + __O uint32_t POS09; + __O uint32_t POS10; + __O uint32_t POS11; + __O uint32_t POS12; + __O uint32_t POS13; + __O uint32_t POS14; + __O uint32_t POS15; +} stc_gpio_posr_bit_t; + +typedef struct { + __O uint32_t POR00; + __O uint32_t POR01; + __O uint32_t POR02; + __O uint32_t POR03; + __O uint32_t POR04; + __O uint32_t POR05; + __O uint32_t POR06; + __O uint32_t POR07; + __O uint32_t POR08; + __O uint32_t POR09; + __O uint32_t POR10; + __O uint32_t POR11; + __O uint32_t POR12; + __O uint32_t POR13; + __O uint32_t POR14; + __O uint32_t POR15; +} stc_gpio_porr_bit_t; + +typedef struct { + __O uint32_t POT00; + __O uint32_t POT01; + __O uint32_t POT02; + __O uint32_t POT03; + __O uint32_t POT04; + __O uint32_t POT05; + __O uint32_t POT06; + __O uint32_t POT07; + __O uint32_t POT08; + __O uint32_t POT09; + __O uint32_t POT10; + __O uint32_t POT11; + __O uint32_t POT12; + __O uint32_t POT13; + __O uint32_t POT14; + __O uint32_t POT15; +} stc_gpio_potr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + uint32_t RESERVED0[2]; +} stc_gpio_pidri_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + uint32_t RESERVED0[2]; +} stc_gpio_podri_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + uint32_t RESERVED0[2]; +} stc_gpio_poeri_bit_t; + +typedef struct { + __O uint32_t POS00; + __O uint32_t POS01; + __O uint32_t POS02; + __O uint32_t POS03; + __O uint32_t POS04; + __O uint32_t POS05; + __O uint32_t POS06; + __O uint32_t POS07; + __O uint32_t POS08; + __O uint32_t POS09; + __O uint32_t POS10; + __O uint32_t POS11; + __O uint32_t POS12; + __O uint32_t POS13; + uint32_t RESERVED0[2]; +} stc_gpio_posri_bit_t; + +typedef struct { + __O uint32_t POR00; + __O uint32_t POR01; + __O uint32_t POR02; + __O uint32_t POR03; + __O uint32_t POR04; + __O uint32_t POR05; + __O uint32_t POR06; + __O uint32_t POR07; + __O uint32_t POR08; + __O uint32_t POR09; + __O uint32_t POR10; + __O uint32_t POR11; + __O uint32_t POR12; + __O uint32_t POR13; + uint32_t RESERVED0[2]; +} stc_gpio_porri_bit_t; + +typedef struct { + __O uint32_t POT00; + __O uint32_t POT01; + __O uint32_t POT02; + __O uint32_t POT03; + __O uint32_t POT04; + __O uint32_t POT05; + __O uint32_t POT06; + __O uint32_t POT07; + __O uint32_t POT08; + __O uint32_t POT09; + __O uint32_t POT10; + __O uint32_t POT11; + __O uint32_t POT12; + __O uint32_t POT13; + uint32_t RESERVED0[2]; +} stc_gpio_potri_bit_t; + +typedef struct { + __IO uint32_t SPFE0; + __IO uint32_t SPFE1; + __IO uint32_t SPFE2; + __IO uint32_t SPFE3; + __IO uint32_t SPFE4; + uint32_t RESERVED0[11]; +} stc_gpio_pspcr_bit_t; + +typedef struct { + __IO uint32_t PINAE0; + __IO uint32_t PINAE1; + __IO uint32_t PINAE2; + __IO uint32_t PINAE3; + __IO uint32_t PINAE4; + __IO uint32_t PINAE5; + __IO uint32_t PINAE6; + __IO uint32_t PINAE7; + __IO uint32_t PINAE8; + uint32_t RESERVED0[7]; +} stc_gpio_pinaer_bit_t; + +typedef struct { + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct { + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[1]; + __IO uint32_t DRV0; + __IO uint32_t DRV1; + __IO uint32_t PUU; + uint32_t RESERVED1[1]; + __I uint32_t PIN; + __IO uint32_t INVE; + __IO uint32_t CINSEL; + uint32_t RESERVED2[1]; + __IO uint32_t INTE; + uint32_t RESERVED3[1]; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t FST_GRP; + __IO uint32_t KMSG_END; + uint32_t RESERVED0[1]; + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t LKEY; + uint32_t RESERVED1[1]; + __IO uint32_t BUSY; + __IO uint32_t CYC_END; + __IO uint32_t HMAC_END; + uint32_t RESERVED2[3]; + __IO uint32_t HCIE; + __IO uint32_t HEIE; + uint32_t RESERVED3[16]; +} stc_hash_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[29]; + __IO uint32_t NE; + __IO uint32_t PE; + __IO uint32_t EN; +} stc_hrpwm_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t ENDF; + uint32_t RESERVED1[2]; + __IO uint32_t CALEN; + uint32_t RESERVED2[16]; +} stc_hrpwm_calcr_bit_t; + +typedef struct { + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t GCEN; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct { + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[2]; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMBHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct { + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[10]; + __IO uint32_t BUSWAIT; + uint32_t RESERVED1[21]; +} stc_i2c_cr4_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[16]; +} stc_i2c_slr0_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[16]; +} stc_i2c_slr1_bit_t; + +typedef struct { + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + uint32_t RESERVED6[8]; +} stc_i2c_sr_bit_t; + +typedef struct { + __O uint32_t STARTFCLR; + __O uint32_t SLADDR0FCLR; + __O uint32_t SLADDR1FCLR; + __O uint32_t TENDFCLR; + __O uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __O uint32_t RFULLFCLR; + __O uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __O uint32_t ARLOFCLR; + uint32_t RESERVED2[2]; + __O uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __O uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __O uint32_t GENCALLFCLR; + __O uint32_t SMBDEFAULTFCLR; + __O uint32_t SMBHOSTFCLR; + __O uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct { + __IO uint32_t TXE; + __IO uint32_t TXIE; + __IO uint32_t RXE; + __IO uint32_t RXIE; + __IO uint32_t EIE; + __IO uint32_t WMS; + __IO uint32_t ODD; + __IO uint32_t MCKOE; + __IO uint32_t TXBIRQWL0; + __IO uint32_t TXBIRQWL1; + __IO uint32_t TXBIRQWL2; + uint32_t RESERVED0[1]; + __IO uint32_t RXBIRQWL0; + __IO uint32_t RXBIRQWL1; + __IO uint32_t RXBIRQWL2; + uint32_t RESERVED1[1]; + __IO uint32_t FIFOR; + __IO uint32_t CODECRC; + __IO uint32_t I2SPLLSEL; + __IO uint32_t SDOE; + __IO uint32_t LRCKOE; + __IO uint32_t CKOE; + __IO uint32_t DUPLEX; + __IO uint32_t CLKSEL; + __IO uint32_t SRST; + uint32_t RESERVED2[7]; +} stc_i2s_ctrl_bit_t; + +typedef struct { + __I uint32_t TXBA; + __I uint32_t RXBA; + __I uint32_t TXBE; + __I uint32_t TXBF; + __I uint32_t RXBE; + __I uint32_t RXBF; + uint32_t RESERVED0[26]; +} stc_i2s_sr_bit_t; + +typedef struct { + __IO uint32_t TXERR; + __IO uint32_t RXERR; + uint32_t RESERVED0[30]; +} stc_i2s_er_bit_t; + +typedef struct { + __IO uint32_t I2SSTD0; + __IO uint32_t I2SSTD1; + __IO uint32_t DATLEN0; + __IO uint32_t DATLEN1; + __IO uint32_t CHLEN; + __IO uint32_t PCMSYNC; + uint32_t RESERVED0[26]; +} stc_i2s_cfgr_bit_t; + +typedef struct { + __I uint32_t SWDTAUTS; + __I uint32_t SWDTITS; + __I uint32_t SWDTPERI0; + __I uint32_t SWDTPERI1; + __I uint32_t SWDTCKS0; + __I uint32_t SWDTCKS1; + __I uint32_t SWDTCKS2; + __I uint32_t SWDTCKS3; + __I uint32_t SWDTWDPT0; + __I uint32_t SWDTWDPT1; + __I uint32_t SWDTWDPT2; + __I uint32_t SWDTWDPT3; + __I uint32_t SWDTSLPOFF; + uint32_t RESERVED0[3]; + __I uint32_t WDTAUTS; + __I uint32_t WDTITS; + __I uint32_t WDTPERI0; + __I uint32_t WDTPERI1; + __I uint32_t WDTCKS0; + __I uint32_t WDTCKS1; + __I uint32_t WDTCKS2; + __I uint32_t WDTCKS3; + __I uint32_t WDTWDPT0; + __I uint32_t WDTWDPT1; + __I uint32_t WDTWDPT2; + __I uint32_t WDTWDPT3; + __I uint32_t WDTSLPOFF; + uint32_t RESERVED1[3]; +} stc_icg_icg0_bit_t; + +typedef struct { + __I uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __I uint32_t HRCSTOP; + uint32_t RESERVED1[7]; + __I uint32_t BOR_LEV0; + __I uint32_t BOR_LEV1; + __I uint32_t BORDIS; + uint32_t RESERVED2[13]; +} stc_icg_icg1_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTENR; + __IO uint32_t PVD1ENR; + __IO uint32_t PVD2ENR; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPENR; + uint32_t RESERVED2[2]; + __IO uint32_t REPENR; + __IO uint32_t RECCENR; + __IO uint32_t BUSMENR; + __IO uint32_t WDTENR; + uint32_t RESERVED3[20]; +} stc_intc_nmienr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTFR; + __IO uint32_t PVD1FR; + __IO uint32_t PVD2FR; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPFR; + uint32_t RESERVED2[2]; + __IO uint32_t REPFR; + __IO uint32_t RECCFR; + __IO uint32_t BUSMFR; + __IO uint32_t WDTFR; + uint32_t RESERVED3[20]; +} stc_intc_nmifr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTCFR; + __IO uint32_t PVD1CFR; + __IO uint32_t PVD2CFR; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPCFR; + uint32_t RESERVED2[2]; + __IO uint32_t REPCFR; + __IO uint32_t RECCCFR; + __IO uint32_t BUSMCFR; + __IO uint32_t WDTCFR; + uint32_t RESERVED3[20]; +} stc_intc_nmicfr_bit_t; + +typedef struct { + __IO uint32_t EIRQTRG0; + __IO uint32_t EIRQTRG1; + uint32_t RESERVED0[2]; + __IO uint32_t EISMPCLK0; + __IO uint32_t EISMPCLK1; + uint32_t RESERVED1[1]; + __IO uint32_t EFEN; + uint32_t RESERVED2[7]; + __IO uint32_t NOCEN; + uint32_t RESERVED3[16]; +} stc_intc_eirqcr_bit_t; + +typedef struct { + __IO uint32_t EIRQWUEN0; + __IO uint32_t EIRQWUEN1; + __IO uint32_t EIRQWUEN2; + __IO uint32_t EIRQWUEN3; + __IO uint32_t EIRQWUEN4; + __IO uint32_t EIRQWUEN5; + __IO uint32_t EIRQWUEN6; + __IO uint32_t EIRQWUEN7; + __IO uint32_t EIRQWUEN8; + __IO uint32_t EIRQWUEN9; + __IO uint32_t EIRQWUEN10; + __IO uint32_t EIRQWUEN11; + __IO uint32_t EIRQWUEN12; + __IO uint32_t EIRQWUEN13; + __IO uint32_t EIRQWUEN14; + __IO uint32_t EIRQWUEN15; + __IO uint32_t SWDTWUEN; + __IO uint32_t PVD1WUEN; + __IO uint32_t PVD2WUEN; + __IO uint32_t CMPWUEN; + __IO uint32_t WKTMWUEN; + __IO uint32_t RTCALMWUEN; + __IO uint32_t RTCPRDWUEN; + __IO uint32_t TMR0GCMWUEN; + __IO uint32_t TMR2GCMWUEN; + __IO uint32_t TMR2OVFWUEN; + __IO uint32_t RXWUEN; + __IO uint32_t USHWUEN; + __IO uint32_t USFWUEN; + __IO uint32_t ETHWUEN; + uint32_t RESERVED0[2]; +} stc_intc_wupen_bit_t; + +typedef struct { + __IO uint32_t EIRQFR0; + __IO uint32_t EIRQFR1; + __IO uint32_t EIRQFR2; + __IO uint32_t EIRQFR3; + __IO uint32_t EIRQFR4; + __IO uint32_t EIRQFR5; + __IO uint32_t EIRQFR6; + __IO uint32_t EIRQFR7; + __IO uint32_t EIRQFR8; + __IO uint32_t EIRQFR9; + __IO uint32_t EIRQFR10; + __IO uint32_t EIRQFR11; + __IO uint32_t EIRQFR12; + __IO uint32_t EIRQFR13; + __IO uint32_t EIRQFR14; + __IO uint32_t EIRQFR15; + uint32_t RESERVED0[16]; +} stc_intc_eirqfr_bit_t; + +typedef struct { + __IO uint32_t EIRQCFR0; + __IO uint32_t EIRQCFR1; + __IO uint32_t EIRQCFR2; + __IO uint32_t EIRQCFR3; + __IO uint32_t EIRQCFR4; + __IO uint32_t EIRQCFR5; + __IO uint32_t EIRQCFR6; + __IO uint32_t EIRQCFR7; + __IO uint32_t EIRQCFR8; + __IO uint32_t EIRQCFR9; + __IO uint32_t EIRQCFR10; + __IO uint32_t EIRQCFR11; + __IO uint32_t EIRQCFR12; + __IO uint32_t EIRQCFR13; + __IO uint32_t EIRQCFR14; + __IO uint32_t EIRQCFR15; + uint32_t RESERVED0[16]; +} stc_intc_eirqcfr_bit_t; + +typedef struct { + __IO uint32_t VSEL0; + __IO uint32_t VSEL1; + __IO uint32_t VSEL2; + __IO uint32_t VSEL3; + __IO uint32_t VSEL4; + __IO uint32_t VSEL5; + __IO uint32_t VSEL6; + __IO uint32_t VSEL7; + __IO uint32_t VSEL8; + __IO uint32_t VSEL9; + __IO uint32_t VSEL10; + __IO uint32_t VSEL11; + __IO uint32_t VSEL12; + __IO uint32_t VSEL13; + __IO uint32_t VSEL14; + __IO uint32_t VSEL15; + __IO uint32_t VSEL16; + __IO uint32_t VSEL17; + __IO uint32_t VSEL18; + __IO uint32_t VSEL19; + __IO uint32_t VSEL20; + __IO uint32_t VSEL21; + __IO uint32_t VSEL22; + __IO uint32_t VSEL23; + __IO uint32_t VSEL24; + __IO uint32_t VSEL25; + __IO uint32_t VSEL26; + __IO uint32_t VSEL27; + __IO uint32_t VSEL28; + __IO uint32_t VSEL29; + __IO uint32_t VSEL30; + __IO uint32_t VSEL31; +} stc_intc_vssel_bit_t; + +typedef struct { + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct { + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct { + __IO uint32_t IER0; + __IO uint32_t IER1; + __IO uint32_t IER2; + __IO uint32_t IER3; + __IO uint32_t IER4; + __IO uint32_t IER5; + __IO uint32_t IER6; + __IO uint32_t IER7; + __IO uint32_t IER8; + __IO uint32_t IER9; + __IO uint32_t IER10; + __IO uint32_t IER11; + __IO uint32_t IER12; + __IO uint32_t IER13; + __IO uint32_t IER14; + __IO uint32_t IER15; + __IO uint32_t IER16; + __IO uint32_t IER17; + __IO uint32_t IER18; + __IO uint32_t IER19; + __IO uint32_t IER20; + __IO uint32_t IER21; + __IO uint32_t IER22; + __IO uint32_t IER23; + __IO uint32_t IER24; + __IO uint32_t IER25; + __IO uint32_t IER26; + __IO uint32_t IER27; + __IO uint32_t IER28; + __IO uint32_t IER29; + __IO uint32_t IER30; + __IO uint32_t IER31; +} stc_intc_ier_bit_t; + +typedef struct { + __IO uint32_t KEYINSEL0; + __IO uint32_t KEYINSEL1; + __IO uint32_t KEYINSEL2; + __IO uint32_t KEYINSEL3; + __IO uint32_t KEYINSEL4; + __IO uint32_t KEYINSEL5; + __IO uint32_t KEYINSEL6; + __IO uint32_t KEYINSEL7; + __IO uint32_t KEYINSEL8; + __IO uint32_t KEYINSEL9; + __IO uint32_t KEYINSEL10; + __IO uint32_t KEYINSEL11; + __IO uint32_t KEYINSEL12; + __IO uint32_t KEYINSEL13; + __IO uint32_t KEYINSEL14; + __IO uint32_t KEYINSEL15; + uint32_t RESERVED0[4]; + __IO uint32_t CKSEL0; + __IO uint32_t CKSEL1; + uint32_t RESERVED1[10]; +} stc_keyscan_scr_bit_t; + +typedef struct { + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t INTEN; + uint32_t RESERVED0[1]; + __IO uint32_t BUSY; + uint32_t RESERVED1[28]; +} stc_mau_csr_bit_t; + +typedef struct { + __IO uint32_t MPURGSIZE0; + __IO uint32_t MPURGSIZE1; + __IO uint32_t MPURGSIZE2; + __IO uint32_t MPURGSIZE3; + __IO uint32_t MPURGSIZE4; + uint32_t RESERVED0[27]; +} stc_mpu_rgd_bit_t; + +typedef struct { + __I uint32_t SMPU1EAF; + __I uint32_t SMPU2EAF; + __I uint32_t FMPUEAF; + __I uint32_t HMPUEAF; + __I uint32_t EMPUEAF; + uint32_t RESERVED0[27]; +} stc_mpu_sr_bit_t; + +typedef struct { + __O uint32_t SMPU1ECLR; + __O uint32_t SMPU2ECLR; + __O uint32_t FMPUECLR; + __O uint32_t HMPUECLR; + __O uint32_t EMPUECLR; + uint32_t RESERVED0[27]; +} stc_mpu_eclr_bit_t; + +typedef struct { + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct { + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t EFMRDP; + __IO uint32_t EFMWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSPTWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct { + __IO uint32_t S1RG0E; + __IO uint32_t S1RG1E; + __IO uint32_t S1RG2E; + __IO uint32_t S1RG3E; + __IO uint32_t S1RG4E; + __IO uint32_t S1RG5E; + __IO uint32_t S1RG6E; + __IO uint32_t S1RG7E; + __IO uint32_t S1RG8E; + __IO uint32_t S1RG9E; + __IO uint32_t S1RG10E; + __IO uint32_t S1RG11E; + __IO uint32_t S1RG12E; + __IO uint32_t S1RG13E; + __IO uint32_t S1RG14E; + __IO uint32_t S1RG15E; + uint32_t RESERVED0[16]; +} stc_mpu_s1rge_bit_t; + +typedef struct { + __IO uint32_t S1RG0WP; + __IO uint32_t S1RG1WP; + __IO uint32_t S1RG2WP; + __IO uint32_t S1RG3WP; + __IO uint32_t S1RG4WP; + __IO uint32_t S1RG5WP; + __IO uint32_t S1RG6WP; + __IO uint32_t S1RG7WP; + __IO uint32_t S1RG8WP; + __IO uint32_t S1RG9WP; + __IO uint32_t S1RG10WP; + __IO uint32_t S1RG11WP; + __IO uint32_t S1RG12WP; + __IO uint32_t S1RG13WP; + __IO uint32_t S1RG14WP; + __IO uint32_t S1RG15WP; + uint32_t RESERVED0[16]; +} stc_mpu_s1rgwp_bit_t; + +typedef struct { + __IO uint32_t S1RG0RP; + __IO uint32_t S1RG1RP; + __IO uint32_t S1RG2RP; + __IO uint32_t S1RG3RP; + __IO uint32_t S1RG4RP; + __IO uint32_t S1RG5RP; + __IO uint32_t S1RG6RP; + __IO uint32_t S1RG7RP; + __IO uint32_t S1RG8RP; + __IO uint32_t S1RG9RP; + __IO uint32_t S1RG10RP; + __IO uint32_t S1RG11RP; + __IO uint32_t S1RG12RP; + __IO uint32_t S1RG13RP; + __IO uint32_t S1RG14RP; + __IO uint32_t S1RG15RP; + uint32_t RESERVED0[16]; +} stc_mpu_s1rgrp_bit_t; + +typedef struct { + __IO uint32_t SMPU1BRP; + __IO uint32_t SMPU1BWP; + __IO uint32_t SMPU1ACT0; + __IO uint32_t SMPU1ACT1; + uint32_t RESERVED0[3]; + __IO uint32_t SMPU1E; + uint32_t RESERVED1[24]; +} stc_mpu_s1cr_bit_t; + +typedef struct { + __IO uint32_t S2RG0E; + __IO uint32_t S2RG1E; + __IO uint32_t S2RG2E; + __IO uint32_t S2RG3E; + __IO uint32_t S2RG4E; + __IO uint32_t S2RG5E; + __IO uint32_t S2RG6E; + __IO uint32_t S2RG7E; + __IO uint32_t S2RG8E; + __IO uint32_t S2RG9E; + __IO uint32_t S2RG10E; + __IO uint32_t S2RG11E; + __IO uint32_t S2RG12E; + __IO uint32_t S2RG13E; + __IO uint32_t S2RG14E; + __IO uint32_t S2RG15E; + uint32_t RESERVED0[16]; +} stc_mpu_s2rge_bit_t; + +typedef struct { + __IO uint32_t S2RG0WP; + __IO uint32_t S2RG1WP; + __IO uint32_t S2RG2WP; + __IO uint32_t S2RG3WP; + __IO uint32_t S2RG4WP; + __IO uint32_t S2RG5WP; + __IO uint32_t S2RG6WP; + __IO uint32_t S2RG7WP; + __IO uint32_t S2RG8WP; + __IO uint32_t S2RG9WP; + __IO uint32_t S2RG10WP; + __IO uint32_t S2RG11WP; + __IO uint32_t S2RG12WP; + __IO uint32_t S2RG13WP; + __IO uint32_t S2RG14WP; + __IO uint32_t S2RG15WP; + uint32_t RESERVED0[16]; +} stc_mpu_s2rgwp_bit_t; + +typedef struct { + __IO uint32_t S2RG0RP; + __IO uint32_t S2RG1RP; + __IO uint32_t S2RG2RP; + __IO uint32_t S2RG3RP; + __IO uint32_t S2RG4RP; + __IO uint32_t S2RG5RP; + __IO uint32_t S2RG6RP; + __IO uint32_t S2RG7RP; + __IO uint32_t S2RG8RP; + __IO uint32_t S2RG9RP; + __IO uint32_t S2RG10RP; + __IO uint32_t S2RG11RP; + __IO uint32_t S2RG12RP; + __IO uint32_t S2RG13RP; + __IO uint32_t S2RG14RP; + __IO uint32_t S2RG15RP; + uint32_t RESERVED0[16]; +} stc_mpu_s2rgrp_bit_t; + +typedef struct { + __IO uint32_t SMPU2BRP; + __IO uint32_t SMPU2BWP; + __IO uint32_t SMPU2ACT0; + __IO uint32_t SMPU2ACT1; + uint32_t RESERVED0[3]; + __IO uint32_t SMPU2E; + uint32_t RESERVED1[24]; +} stc_mpu_s2cr_bit_t; + +typedef struct { + __IO uint32_t FRG0E; + __IO uint32_t FRG1E; + __IO uint32_t FRG2E; + __IO uint32_t FRG3E; + __IO uint32_t FRG4E; + __IO uint32_t FRG5E; + __IO uint32_t FRG6E; + __IO uint32_t FRG7E; + uint32_t RESERVED0[24]; +} stc_mpu_frge_bit_t; + +typedef struct { + __IO uint32_t FRG0WP; + __IO uint32_t FRG1WP; + __IO uint32_t FRG2WP; + __IO uint32_t FRG3WP; + __IO uint32_t FRG4WP; + __IO uint32_t FRG5WP; + __IO uint32_t FRG6WP; + __IO uint32_t FRG7WP; + uint32_t RESERVED0[24]; +} stc_mpu_frgwp_bit_t; + +typedef struct { + __IO uint32_t FRG0RP; + __IO uint32_t FRG1RP; + __IO uint32_t FRG2RP; + __IO uint32_t FRG3RP; + __IO uint32_t FRG4RP; + __IO uint32_t FRG5RP; + __IO uint32_t FRG6RP; + __IO uint32_t FRG7RP; + uint32_t RESERVED0[24]; +} stc_mpu_frgrp_bit_t; + +typedef struct { + __IO uint32_t FMPUBRP; + __IO uint32_t FMPUBWP; + __IO uint32_t FMPUACT0; + __IO uint32_t FMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t FMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_fcr_bit_t; + +typedef struct { + __IO uint32_t HRG0E; + __IO uint32_t HRG1E; + __IO uint32_t HRG2E; + __IO uint32_t HRG3E; + __IO uint32_t HRG4E; + __IO uint32_t HRG5E; + __IO uint32_t HRG6E; + __IO uint32_t HRG7E; + uint32_t RESERVED0[24]; +} stc_mpu_hrge_bit_t; + +typedef struct { + __IO uint32_t HRG0WP; + __IO uint32_t HRG1WP; + __IO uint32_t HRG2WP; + __IO uint32_t HRG3WP; + __IO uint32_t HRG4WP; + __IO uint32_t HRG5WP; + __IO uint32_t HRG6WP; + __IO uint32_t HRG7WP; + uint32_t RESERVED0[24]; +} stc_mpu_hrgwp_bit_t; + +typedef struct { + __IO uint32_t HRG0RP; + __IO uint32_t HRG1RP; + __IO uint32_t HRG2RP; + __IO uint32_t HRG3RP; + __IO uint32_t HRG4RP; + __IO uint32_t HRG5RP; + __IO uint32_t HRG6RP; + __IO uint32_t HRG7RP; + uint32_t RESERVED0[24]; +} stc_mpu_hrgrp_bit_t; + +typedef struct { + __IO uint32_t HMPUBRP; + __IO uint32_t HMPUBWP; + __IO uint32_t HMPUACT0; + __IO uint32_t HMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t HMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_hcr_bit_t; + +typedef struct { + __IO uint32_t ERG0E; + __IO uint32_t ERG1E; + __IO uint32_t ERG2E; + __IO uint32_t ERG3E; + __IO uint32_t ERG4E; + __IO uint32_t ERG5E; + __IO uint32_t ERG6E; + __IO uint32_t ERG7E; + uint32_t RESERVED0[24]; +} stc_mpu_erge_bit_t; + +typedef struct { + __IO uint32_t ERG0WP; + __IO uint32_t ERG1WP; + __IO uint32_t ERG2WP; + __IO uint32_t ERG3WP; + __IO uint32_t ERG4WP; + __IO uint32_t ERG5WP; + __IO uint32_t ERG6WP; + __IO uint32_t ERG7WP; + uint32_t RESERVED0[24]; +} stc_mpu_ergwp_bit_t; + +typedef struct { + __IO uint32_t ERG0RP; + __IO uint32_t ERG1RP; + __IO uint32_t ERG2RP; + __IO uint32_t ERG3RP; + __IO uint32_t ERG4RP; + __IO uint32_t ERG5RP; + __IO uint32_t ERG6RP; + __IO uint32_t ERG7RP; + uint32_t RESERVED0[24]; +} stc_mpu_ergrp_bit_t; + +typedef struct { + __IO uint32_t EMPUBRP; + __IO uint32_t EMPUBWP; + __IO uint32_t EMPUACT0; + __IO uint32_t EMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t EMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_ecr_bit_t; + +typedef struct { + __IO uint32_t OTSST; + __IO uint32_t OTSCK; + __IO uint32_t OTSIE; + __IO uint32_t TSSTP; + uint32_t RESERVED0[12]; +} stc_ots_ctl_bit_t; + +typedef struct { + __IO uint32_t USBFS_DFB; + __IO uint32_t USBFS_SOFEN; + uint32_t RESERVED0[6]; + __IO uint32_t USBHS_DFB; + __IO uint32_t USBHS_SOFEN; + __IO uint32_t USBHS_FSPHYE; + uint32_t RESERVED1[5]; + __IO uint32_t USBFS_NFS0; + __IO uint32_t USBFS_NFS1; + __IO uint32_t USBFS_NFE; + uint32_t RESERVED2[5]; + __IO uint32_t USBHS_NFS0; + __IO uint32_t USBHS_NFS1; + __IO uint32_t USBHS_NFE; + uint32_t RESERVED3[5]; +} stc_peric_usb_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SELMMC1; + uint32_t RESERVED1[1]; + __IO uint32_t SELMMC2; + uint32_t RESERVED2[28]; +} stc_peric_sdioc_syctlreg_bit_t; + +typedef struct { + __IO uint32_t OPENP; + uint32_t RESERVED0[31]; +} stc_peric_nfc_stcr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NFCEN; + uint32_t RESERVED1[29]; +} stc_peric_nfc_enar_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SMCEN; + uint32_t RESERVED1[30]; +} stc_peric_smc_enar_bit_t; + +typedef struct { + __IO uint32_t DMCEN; + uint32_t RESERVED0[31]; +} stc_peric_dmc_enar_bit_t; + +typedef struct { + __IO uint32_t USASRT1_NFS0; + __IO uint32_t USASRT1_NFS1; + __IO uint32_t USART1_NFE; + uint32_t RESERVED0[29]; +} stc_peric_usart1_nfc_bit_t; + +typedef struct { + __I uint32_t CHIP_BUSY0; + __I uint32_t CHIP_BUSY1; + __I uint32_t CHIP_BUSY2; + __I uint32_t CHIP_BUSY3; + __I uint32_t CHIP_BUSY4; + __I uint32_t CHIP_BUSY5; + __I uint32_t CHIP_BUSY6; + __I uint32_t CHIP_BUSY7; + __I uint32_t PECC; + uint32_t RESERVED0[23]; +} stc_peric_nfc_stsr_bit_t; + +typedef struct { + __IO uint32_t SRAMH; + uint32_t RESERVED0[3]; + __IO uint32_t SRAM1; + __IO uint32_t SRAM2; + __IO uint32_t SRAM3; + __IO uint32_t SRAM4; + uint32_t RESERVED1[2]; + __IO uint32_t SRAMB; + uint32_t RESERVED2[2]; + __IO uint32_t KEY; + __IO uint32_t DMA1; + __IO uint32_t DMA2; + __IO uint32_t FCM; + __IO uint32_t AOS; + __IO uint32_t CTC; + __IO uint32_t MAU; + __IO uint32_t AES; + __IO uint32_t HASH; + __IO uint32_t TRNG; + __IO uint32_t CRC; + __IO uint32_t DCU1; + __IO uint32_t DCU2; + __IO uint32_t DCU3; + __IO uint32_t DCU4; + __IO uint32_t DCU5; + __IO uint32_t DCU6; + __IO uint32_t DCU7; + __IO uint32_t DCU8; +} stc_pwc_fcg0_bit_t; + +typedef struct { + __IO uint32_t CAN1; + __IO uint32_t CAN2; + __IO uint32_t ETHMAC; + __IO uint32_t QSPI; + __IO uint32_t I2C1; + __IO uint32_t I2C2; + __IO uint32_t I2C3; + __IO uint32_t I2C4; + __IO uint32_t I2C5; + __IO uint32_t I2C6; + __IO uint32_t SDIOC1; + __IO uint32_t SDIOC2; + __IO uint32_t I2S1; + __IO uint32_t I2S2; + __IO uint32_t I2S3; + __IO uint32_t I2S4; + __IO uint32_t SPI1; + __IO uint32_t SPI2; + __IO uint32_t SPI3; + __IO uint32_t SPI4; + __IO uint32_t SPI5; + __IO uint32_t SPI6; + __IO uint32_t USBFS; + __IO uint32_t USBHS; + __IO uint32_t FMAC1; + __IO uint32_t FMAC2; + __IO uint32_t FMAC3; + __IO uint32_t FMAC4; + uint32_t RESERVED0[4]; +} stc_pwc_fcg1_bit_t; + +typedef struct { + __IO uint32_t TMR6_1; + __IO uint32_t TMR6_2; + __IO uint32_t TMR6_3; + __IO uint32_t TMR6_4; + __IO uint32_t TMR6_5; + __IO uint32_t TMR6_6; + __IO uint32_t TMR6_7; + __IO uint32_t TMR6_8; + __IO uint32_t TMR4_1; + __IO uint32_t TMR4_2; + __IO uint32_t TMR4_3; + __IO uint32_t HRPWM; + __IO uint32_t TMR0_1; + __IO uint32_t TMR0_2; + uint32_t RESERVED0[1]; + __IO uint32_t EMB; + __IO uint32_t TMR2_1; + __IO uint32_t TMR2_2; + __IO uint32_t TMR2_3; + __IO uint32_t TMR2_4; + __IO uint32_t TMRA_1; + __IO uint32_t TMRA_2; + __IO uint32_t TMRA_3; + __IO uint32_t TMRA_4; + __IO uint32_t TMRA_5; + __IO uint32_t TMRA_6; + __IO uint32_t TMRA_7; + __IO uint32_t TMRA_8; + __IO uint32_t TMRA_9; + __IO uint32_t TMRA_10; + __IO uint32_t TMRA_11; + __IO uint32_t TMRA_12; +} stc_pwc_fcg2_bit_t; + +typedef struct { + __IO uint32_t ADC1; + __IO uint32_t ADC2; + __IO uint32_t ADC3; + __IO uint32_t CMBIAS; + __IO uint32_t DAC1; + __IO uint32_t DAC2; + uint32_t RESERVED0[2]; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + uint32_t RESERVED1[2]; + __IO uint32_t OTS; + uint32_t RESERVED2[2]; + __IO uint32_t DVP; + __IO uint32_t SMC; + __IO uint32_t DMC; + __IO uint32_t NFC; + uint32_t RESERVED3[1]; + __IO uint32_t USART1; + __IO uint32_t USART2; + __IO uint32_t USART3; + __IO uint32_t USART4; + __IO uint32_t USART5; + __IO uint32_t USART6; + __IO uint32_t USART7; + __IO uint32_t USART8; + __IO uint32_t USART9; + __IO uint32_t USART10; + uint32_t RESERVED4[2]; +} stc_pwc_fcg3_bit_t; + +typedef struct { + __IO uint32_t PRT0; + uint32_t RESERVED0[31]; +} stc_pwc_fcg0pc_bit_t; + +typedef struct { + __IO uint32_t VBTRSD; + __IO uint32_t RAMVALID; + __IO uint32_t RAMPDF; + __IO uint32_t VBATDIVMONE; + uint32_t RESERVED0[3]; + __IO uint32_t CSDIS; +} stc_pwc_vbatcr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t WKOVF; + __IO uint32_t WKCKS0; + __IO uint32_t WKCKS1; + __IO uint32_t WKTCE; +} stc_pwc_wktc2_bit_t; + +typedef struct { + __IO uint32_t PDMDS0; + __IO uint32_t PDMDS1; + uint32_t RESERVED0[2]; + __IO uint32_t IORTN0; + __IO uint32_t IORTN1; + uint32_t RESERVED1[1]; + __IO uint32_t PWDN; +} stc_pwc_pwrc0_bit_t; + +typedef struct { + __IO uint32_t VPLLSD0; + __IO uint32_t VPLLSD1; + __IO uint32_t VHRCSD; + __IO uint32_t PDTS; + uint32_t RESERVED0[2]; + __IO uint32_t STPDAS0; + __IO uint32_t STPDAS1; +} stc_pwc_pwrc1_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DVS0; + __IO uint32_t DVS1; + uint32_t RESERVED1[2]; +} stc_pwc_pwrc2_bit_t; + +typedef struct { + __IO uint32_t VBATREFSEL; + __IO uint32_t VBATME; + uint32_t RESERVED0[2]; + __IO uint32_t VBATMON; + uint32_t RESERVED1[1]; + __IO uint32_t ADBUFS; + __IO uint32_t ADBUFE; +} stc_pwc_pwrc4_bit_t; + +typedef struct { + __IO uint32_t EXVCCINEN; + uint32_t RESERVED0[4]; + __IO uint32_t PVD1EN; + __IO uint32_t PVD2EN; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr0_bit_t; + +typedef struct { + __IO uint32_t PVD1IRE; + __IO uint32_t PVD1IRS; + __IO uint32_t PVD1CMPOE; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2IRE; + __IO uint32_t PVD2IRS; + __IO uint32_t PVD2CMPOE; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr1_bit_t; + +typedef struct { + __IO uint32_t PVD1NFDIS; + __IO uint32_t PVD1NFCKS0; + __IO uint32_t PVD1NFCKS1; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2NFDIS; + __IO uint32_t PVD2NFCKS0; + __IO uint32_t PVD2NFCKS1; + uint32_t RESERVED1[1]; +} stc_pwc_pvdfcr_bit_t; + +typedef struct { + __IO uint32_t WKE00; + __IO uint32_t WKE01; + __IO uint32_t WKE02; + __IO uint32_t WKE03; + __IO uint32_t WKE10; + __IO uint32_t WKE11; + __IO uint32_t WKE12; + __IO uint32_t WKE13; +} stc_pwc_pdwke0_bit_t; + +typedef struct { + __IO uint32_t WKE20; + __IO uint32_t WKE21; + __IO uint32_t WKE22; + __IO uint32_t WKE23; + __IO uint32_t WKE30; + __IO uint32_t WKE31; + __IO uint32_t WKE32; + __IO uint32_t WKE33; +} stc_pwc_pdwke1_bit_t; + +typedef struct { + __IO uint32_t VD1WKE; + __IO uint32_t VD2WKE; + uint32_t RESERVED0[2]; + __IO uint32_t RTCPRDWKE; + __IO uint32_t RTCALMWKE; + uint32_t RESERVED1[1]; + __IO uint32_t WKTMWKE; +} stc_pwc_pdwke2_bit_t; + +typedef struct { + __IO uint32_t WK0EGS; + __IO uint32_t WK1EGS; + __IO uint32_t WK2EGS; + __IO uint32_t WK3EGS; + __IO uint32_t VD1EGS; + __IO uint32_t VD2EGS; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkes_bit_t; + +typedef struct { + __IO uint32_t PTWK0F; + __IO uint32_t PTWK1F; + __IO uint32_t PTWK2F; + __IO uint32_t PTWK3F; + __IO uint32_t VD1WKF; + __IO uint32_t VD2WKF; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkf0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RXD0WKF; + __IO uint32_t RTCPRDWKF; + __IO uint32_t RTCALMWKF; + uint32_t RESERVED1[1]; + __IO uint32_t WKTMWKF; +} stc_pwc_pdwkf1_bit_t; + +typedef struct { + __IO uint32_t RAMPDC0; + __IO uint32_t RAMPDC1; + __IO uint32_t RAMPDC2; + __IO uint32_t RAMPDC3; + __IO uint32_t RAMPDC4; + __IO uint32_t RAMPDC5; + __IO uint32_t RAMPDC6; + __IO uint32_t RAMPDC7; + __IO uint32_t RAMPDC8; + __IO uint32_t RAMPDC9; + __IO uint32_t RAMPDC10; + uint32_t RESERVED0[21]; +} stc_pwc_rampc0_bit_t; + +typedef struct { + __IO uint32_t PRAMPDC0; + __IO uint32_t PRAMPDC1; + __IO uint32_t PRAMPDC2; + __IO uint32_t PRAMPDC3; + __IO uint32_t PRAMPDC4; + __IO uint32_t PRAMPDC5; + __IO uint32_t PRAMPDC6; + __IO uint32_t PRAMPDC7; + __IO uint32_t PRAMPDC8; + __IO uint32_t PRAMPDC9; + uint32_t RESERVED0[22]; +} stc_pwc_pramlpc_bit_t; + +typedef struct { + __IO uint32_t PVD1NMIS; + __IO uint32_t PVD1EDGS0; + __IO uint32_t PVD1EDGS1; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2NMIS; + __IO uint32_t PVD2EDGS0; + __IO uint32_t PVD2EDGS1; + uint32_t RESERVED1[1]; +} stc_pwc_pvdicr_bit_t; + +typedef struct { + __IO uint32_t PVD1MON; + __IO uint32_t PVD1DETFLG; + uint32_t RESERVED0[2]; + __IO uint32_t PVD2MON; + __IO uint32_t PVD2DETFLG; + uint32_t RESERVED1[2]; +} stc_pwc_pvddsr_bit_t; + +typedef struct { + __IO uint32_t FLNWT; + __IO uint32_t CKSMRC; + uint32_t RESERVED0[12]; + __IO uint32_t EXBUSOE; + __IO uint32_t STOP; +} stc_pwc_stpmcr_bit_t; + +typedef struct { + __IO uint32_t FPRCB0; + __IO uint32_t FPRCB1; + __IO uint32_t FPRCB2; + __IO uint32_t FPRCB3; + uint32_t RESERVED0[12]; +} stc_pwc_fprc_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LKUPREN; + uint32_t RESERVED1[2]; +} stc_rmu_prstcr0_bit_t; + +typedef struct { + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t LKUPRF; + uint32_t RESERVED0[15]; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct { + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct { + __IO uint32_t PRDS0; + __IO uint32_t PRDS1; + __IO uint32_t PRDS2; + __IO uint32_t AMPM; + uint32_t RESERVED0[1]; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct { + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + __IO uint32_t PRDF; + __IO uint32_t ALMF; + uint32_t RESERVED0[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct { + __IO uint32_t HOURU0; + __IO uint32_t HOURU1; + __IO uint32_t HOURU2; + __IO uint32_t HOURU3; + __IO uint32_t HOURD0; + __IO uint32_t HOURD1; + uint32_t RESERVED0[2]; +} stc_rtc_hour_bit_t; + +typedef struct { + __IO uint32_t ALMHOURU0; + __IO uint32_t ALMHOURU1; + __IO uint32_t ALMHOURU2; + __IO uint32_t ALMHOURU3; + __IO uint32_t ALMHOURD0; + __IO uint32_t ALMHOURD1; + uint32_t RESERVED0[2]; +} stc_rtc_almhour_bit_t; + +typedef struct { + __IO uint32_t ALMWEEK0; + __IO uint32_t ALMWEEK1; + __IO uint32_t ALMWEEK2; + __IO uint32_t ALMWEEK3; + __IO uint32_t ALMWEEK4; + __IO uint32_t ALMWEEK5; + __IO uint32_t ALMWEEK6; + uint32_t RESERVED0[1]; +} stc_rtc_almweek_bit_t; + +typedef struct { + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct { + __IO uint32_t TPCT00; + __IO uint32_t TPCT01; + __IO uint32_t TPNF00; + __IO uint32_t TPNF01; + __IO uint32_t TPRSTE0; + __IO uint32_t TPIE0; + __IO uint32_t TSTPE0; + __IO uint32_t TPEN0; +} stc_rtc_tpcr0_bit_t; + +typedef struct { + __IO uint32_t TPCT10; + __IO uint32_t TPCT11; + __IO uint32_t TPNF10; + __IO uint32_t TPNF11; + __IO uint32_t TPRSTE1; + __IO uint32_t TPIE1; + __IO uint32_t TSTPE1; + __IO uint32_t TPEN1; +} stc_rtc_tpcr1_bit_t; + +typedef struct { + __IO uint32_t TPF0; + __IO uint32_t TPF1; + __IO uint32_t TPOVF; + uint32_t RESERVED0[5]; +} stc_rtc_tpsr_bit_t; + +typedef struct { + __IO uint32_t HOURTPU0; + __IO uint32_t HOURTPU1; + __IO uint32_t HOURTPU2; + __IO uint32_t HOURTPU3; + __IO uint32_t HOURTPD0; + __IO uint32_t HOURTPD1; + uint32_t RESERVED0[2]; +} stc_rtc_hourtp_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t BCE; + __IO uint32_t ATCEN0; + __IO uint32_t ATCEN1; + __IO uint32_t DDIR; + __IO uint32_t MULB; + uint32_t RESERVED1[10]; +} stc_sdioc_transmode_bit_t; + +typedef struct { + __IO uint32_t RESTYP0; + __IO uint32_t RESTYP1; + uint32_t RESERVED0[1]; + __IO uint32_t CCE; + __IO uint32_t ICE; + __IO uint32_t DAT; + __IO uint32_t TYP0; + __IO uint32_t TYP1; + __IO uint32_t IDX0; + __IO uint32_t IDX1; + __IO uint32_t IDX2; + __IO uint32_t IDX3; + __IO uint32_t IDX4; + __IO uint32_t IDX5; + uint32_t RESERVED1[2]; +} stc_sdioc_cmd_bit_t; + +typedef struct { + __I uint32_t CIC; + __I uint32_t CID; + __I uint32_t DA; + uint32_t RESERVED0[5]; + __I uint32_t WTA; + __I uint32_t RTA; + __I uint32_t BWE; + __I uint32_t BRE; + uint32_t RESERVED1[4]; + __I uint32_t CIN; + __I uint32_t CSS; + __I uint32_t CDL; + __I uint32_t WPL; + __I uint32_t DATL0; + __I uint32_t DATL1; + __I uint32_t DATL2; + __I uint32_t DATL3; + __I uint32_t CMDL; + uint32_t RESERVED2[7]; +} stc_sdioc_pstat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t DW; + __IO uint32_t HSEN; + uint32_t RESERVED1[2]; + __IO uint32_t EXDW; + __IO uint32_t CDTL; + __IO uint32_t CDSS; +} stc_sdioc_hostcon_bit_t; + +typedef struct { + __IO uint32_t PWON; + uint32_t RESERVED0[7]; +} stc_sdioc_pwrcon_bit_t; + +typedef struct { + __IO uint32_t SABGR; + __IO uint32_t CR; + __IO uint32_t RWC; + __IO uint32_t IABG; + uint32_t RESERVED0[4]; +} stc_sdioc_blkgpcon_bit_t; + +typedef struct { + __IO uint32_t ICE; + uint32_t RESERVED0[1]; + __IO uint32_t CE; + uint32_t RESERVED1[5]; + __IO uint32_t FS0; + __IO uint32_t FS1; + __IO uint32_t FS2; + __IO uint32_t FS3; + __IO uint32_t FS4; + __IO uint32_t FS5; + __IO uint32_t FS6; + __IO uint32_t FS7; +} stc_sdioc_clkcon_bit_t; + +typedef struct { + __IO uint32_t RSTA; + __IO uint32_t RSTC; + __IO uint32_t RSTD; + uint32_t RESERVED0[5]; +} stc_sdioc_sftrst_bit_t; + +typedef struct { + __IO uint32_t CC; + __IO uint32_t TC; + __IO uint32_t BGE; + uint32_t RESERVED0[1]; + __IO uint32_t BWR; + __IO uint32_t BRR; + __IO uint32_t CIST; + __IO uint32_t CRM; + __I uint32_t CINT; + uint32_t RESERVED1[6]; + __I uint32_t EI; +} stc_sdioc_norintst_bit_t; + +typedef struct { + __IO uint32_t CTOE; + __IO uint32_t CCE; + __IO uint32_t CEBE; + __IO uint32_t CIE; + __IO uint32_t DTOE; + __IO uint32_t DCE; + __IO uint32_t DEBE; + uint32_t RESERVED0[1]; + __IO uint32_t ACE; + uint32_t RESERVED1[7]; +} stc_sdioc_errintst_bit_t; + +typedef struct { + __IO uint32_t CCEN; + __IO uint32_t TCEN; + __IO uint32_t BGEEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWREN; + __IO uint32_t BRREN; + __IO uint32_t CISTEN; + __IO uint32_t CRMEN; + __IO uint32_t CINTEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsten_bit_t; + +typedef struct { + __IO uint32_t CTOEEN; + __IO uint32_t CCEEN; + __IO uint32_t CEBEEN; + __IO uint32_t CIEEN; + __IO uint32_t DTOEEN; + __IO uint32_t DCEEN; + __IO uint32_t DEBEEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACEEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsten_bit_t; + +typedef struct { + __IO uint32_t CCSEN; + __IO uint32_t TCSEN; + __IO uint32_t BGESEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWRSEN; + __IO uint32_t BRRSEN; + __IO uint32_t CISTSEN; + __IO uint32_t CRMSEN; + __IO uint32_t CINTSEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsgen_bit_t; + +typedef struct { + __IO uint32_t CTOESEN; + __IO uint32_t CCESEN; + __IO uint32_t CEBESEN; + __IO uint32_t CIESEN; + __IO uint32_t DTOESEN; + __IO uint32_t DCESEN; + __IO uint32_t DEBESEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACESEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsgen_bit_t; + +typedef struct { + __I uint32_t NE; + __I uint32_t TOE; + __I uint32_t CE; + __I uint32_t EBE; + __I uint32_t IE; + uint32_t RESERVED0[2]; + __I uint32_t CMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_atcerrst_bit_t; + +typedef struct { + __O uint32_t FNE; + __O uint32_t FTOE; + __O uint32_t FCE; + __O uint32_t FEBE; + __O uint32_t FIE; + uint32_t RESERVED0[2]; + __O uint32_t FCMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_fea_bit_t; + +typedef struct { + __O uint32_t FCTOE; + __O uint32_t FCCE; + __O uint32_t FCEBE; + __O uint32_t FCIE; + __O uint32_t FDTOE; + __O uint32_t FDCE; + __O uint32_t FDEBE; + uint32_t RESERVED0[1]; + __O uint32_t FACE; + uint32_t RESERVED1[7]; +} stc_sdioc_fee_bit_t; + +typedef struct { + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr1_bit_t; + +typedef struct { + __IO uint32_t FTHLV0; + __IO uint32_t FTHLV1; + uint32_t RESERVED0[4]; + __IO uint32_t SPRDTD; + uint32_t RESERVED1[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED2[8]; + __IO uint32_t MSSI0; + __IO uint32_t MSSI1; + __IO uint32_t MSSI2; + uint32_t RESERVED3[1]; + __IO uint32_t MSSDL0; + __IO uint32_t MSSDL1; + __IO uint32_t MSSDL2; + uint32_t RESERVED4[1]; + __IO uint32_t MIDI0; + __IO uint32_t MIDI1; + __IO uint32_t MIDI2; + uint32_t RESERVED5[1]; +} stc_spi_cfg1_bit_t; + +typedef struct { + __IO uint32_t OVRERF; + __I uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __I uint32_t TDEF; + uint32_t RESERVED0[1]; + __I uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct { + __IO uint32_t CPHA; + __IO uint32_t CPOL; + __IO uint32_t MBR0; + __IO uint32_t MBR1; + __IO uint32_t MBR2; + __IO uint32_t SSA0; + __IO uint32_t SSA1; + __IO uint32_t SSA2; + __IO uint32_t DSIZE0; + __IO uint32_t DSIZE1; + __IO uint32_t DSIZE2; + __IO uint32_t DSIZE3; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED0[16]; +} stc_spi_cfg2_bit_t; + +typedef struct { + __IO uint32_t WTPRC; + uint32_t RESERVED0[31]; +} stc_sramc_wtpr_bit_t; + +typedef struct { + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + __IO uint32_t BECCOAD; + uint32_t RESERVED1[6]; + __IO uint32_t ECCMOD0; + __IO uint32_t ECCMOD1; + __IO uint32_t BECCMOD0; + __IO uint32_t BECCMOD1; + uint32_t RESERVED2[4]; +} stc_sramc_ckcr_bit_t; + +typedef struct { + __IO uint32_t CKPRC; + uint32_t RESERVED0[31]; +} stc_sramc_ckpr_bit_t; + +typedef struct { + __IO uint32_t SRAM1_PYERR; + __IO uint32_t SRAM2_PYERR; + __IO uint32_t SRAM3_PYERR; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAM4_1ERR; + __IO uint32_t SRAM4_2ERR; + __IO uint32_t SRAMB_1ERR; + __IO uint32_t SRAMB_2ERR; + __IO uint32_t CACHE_PYERR; + uint32_t RESERVED0[23]; +} stc_sramc_cksr_bit_t; + +typedef struct { + __IO uint32_t PERI0; + __IO uint32_t PERI1; + uint32_t RESERVED0[2]; + __IO uint32_t CKS0; + __IO uint32_t CKS1; + __IO uint32_t CKS2; + __IO uint32_t CKS3; + __IO uint32_t WDPT0; + __IO uint32_t WDPT1; + __IO uint32_t WDPT2; + __IO uint32_t WDPT3; + uint32_t RESERVED1[4]; + __IO uint32_t SLPOFF; + uint32_t RESERVED2[14]; + __IO uint32_t ITS; +} stc_swdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t INTENA; + uint32_t RESERVED0[5]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t INTENB; + uint32_t RESERVED2[5]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + uint32_t RESERVED0[15]; + __IO uint32_t CMFB; + uint32_t RESERVED1[15]; +} stc_tmr0_stflr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + uint32_t RESERVED0[1]; + __IO uint32_t SYNSA; + uint32_t RESERVED1[4]; + __IO uint32_t SYNCLKA0; + __IO uint32_t SYNCLKA1; + __IO uint32_t ASYNCLKA0; + __IO uint32_t ASYNCLKA1; + __IO uint32_t SYNCLKAT0; + __IO uint32_t SYNCLKAT1; + uint32_t RESERVED2[2]; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + uint32_t RESERVED3[1]; + __IO uint32_t SYNSB; + uint32_t RESERVED4[4]; + __IO uint32_t SYNCLKB0; + __IO uint32_t SYNCLKB1; + __IO uint32_t ASYNCLKB0; + __IO uint32_t ASYNCLKB1; + __IO uint32_t SYNCLKBT0; + __IO uint32_t SYNCLKBT1; + uint32_t RESERVED5[2]; +} stc_tmr2_bconr_bit_t; + +typedef struct { + __IO uint32_t CMENA; + __IO uint32_t OVENA; + uint32_t RESERVED0[14]; + __IO uint32_t CMENB; + __IO uint32_t OVENB; + uint32_t RESERVED1[14]; +} stc_tmr2_iconr_bit_t; + +typedef struct { + __IO uint32_t STACA0; + __IO uint32_t STACA1; + __IO uint32_t STPCA0; + __IO uint32_t STPCA1; + __IO uint32_t CMPCA0; + __IO uint32_t CMPCA1; + uint32_t RESERVED0[2]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENA; + __IO uint32_t NOFICKA0; + __IO uint32_t NOFICKA1; + uint32_t RESERVED2[1]; + __IO uint32_t STACB0; + __IO uint32_t STACB1; + __IO uint32_t STPCB0; + __IO uint32_t STPCB1; + __IO uint32_t CMPCB0; + __IO uint32_t CMPCB1; + uint32_t RESERVED3[2]; + __IO uint32_t OUTENB; + uint32_t RESERVED4[3]; + __IO uint32_t NOFIENB; + __IO uint32_t NOFICKB0; + __IO uint32_t NOFICKB1; + uint32_t RESERVED5[1]; +} stc_tmr2_pconr_bit_t; + +typedef struct { + __IO uint32_t HSTAA0; + __IO uint32_t HSTAA1; + __IO uint32_t HSTAA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTPA0; + __IO uint32_t HSTPA1; + __IO uint32_t HSTPA2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLEA0; + __IO uint32_t HCLEA1; + __IO uint32_t HCLEA2; + uint32_t RESERVED2[1]; + __IO uint32_t HICPA0; + __IO uint32_t HICPA1; + __IO uint32_t HICPA2; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB0; + __IO uint32_t HSTAB1; + __IO uint32_t HSTAB2; + uint32_t RESERVED4[1]; + __IO uint32_t HSTPB0; + __IO uint32_t HSTPB1; + __IO uint32_t HSTPB2; + uint32_t RESERVED5[1]; + __IO uint32_t HCLEB0; + __IO uint32_t HCLEB1; + __IO uint32_t HCLEB2; + uint32_t RESERVED6[1]; + __IO uint32_t HICPB0; + __IO uint32_t HICPB1; + __IO uint32_t HICPB2; + uint32_t RESERVED7[1]; +} stc_tmr2_hconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + __IO uint32_t OVFA; + uint32_t RESERVED0[14]; + __IO uint32_t CMFB; + __IO uint32_t OVFB; + uint32_t RESERVED1[14]; +} stc_tmr2_stflr_bit_t; + +typedef struct { + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct { + __IO uint32_t CHBUFEN0; + __IO uint32_t CHBUFEN1; + __IO uint32_t CLBUFEN0; + __IO uint32_t CLBUFEN1; + __IO uint32_t MHBUFEN0; + __IO uint32_t MHBUFEN1; + __IO uint32_t MLBUFEN0; + __IO uint32_t MLBUFEN1; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED0[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct { + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + __IO uint32_t OPDCH0; + __IO uint32_t OPDCH1; + __IO uint32_t OPPKH0; + __IO uint32_t OPPKH1; + __IO uint32_t OPUCH0; + __IO uint32_t OPUCH1; + __IO uint32_t OPZRH0; + __IO uint32_t OPZRH1; + __IO uint32_t OPNPKH0; + __IO uint32_t OPNPKH1; + __IO uint32_t OPNZRH0; + __IO uint32_t OPNZRH1; +} stc_tmr4_ocmrh_bit_t; + +typedef struct { + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + __IO uint32_t OPDCL0; + __IO uint32_t OPDCL1; + __IO uint32_t OPPKL0; + __IO uint32_t OPPKL1; + __IO uint32_t OPUCL0; + __IO uint32_t OPUCL1; + __IO uint32_t OPZRL0; + __IO uint32_t OPZRL1; + __IO uint32_t OPNPKL0; + __IO uint32_t OPNPKL1; + __IO uint32_t OPNZRL0; + __IO uint32_t OPNZRL1; + __IO uint32_t EOPNDCL0; + __IO uint32_t EOPNDCL1; + __IO uint32_t EOPNUCL0; + __IO uint32_t EOPNUCL1; + __IO uint32_t EOPDCL0; + __IO uint32_t EOPDCL1; + __IO uint32_t EOPPKL0; + __IO uint32_t EOPPKL1; + __IO uint32_t EOPUCL0; + __IO uint32_t EOPUCL1; + __IO uint32_t EOPZRL0; + __IO uint32_t EOPZRL1; + __IO uint32_t EOPNPKL0; + __IO uint32_t EOPNPKL1; + __IO uint32_t EOPNZRL0; + __IO uint32_t EOPNZRL1; +} stc_tmr4_ocmrl_bit_t; + +typedef struct { + __IO uint32_t CKDIV0; + __IO uint32_t CKDIV1; + __IO uint32_t CKDIV2; + __IO uint32_t CKDIV3; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + uint32_t RESERVED0[3]; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct { + __IO uint32_t DIVCK0; + __IO uint32_t DIVCK1; + __IO uint32_t DIVCK2; + uint32_t RESERVED0[1]; + __IO uint32_t PWMMD0; + __IO uint32_t PWMMD1; + __IO uint32_t LVLS0; + __IO uint32_t LVLS1; + uint32_t RESERVED1[8]; +} stc_tmr4_pocr_bit_t; + +typedef struct { + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + uint32_t RESERVED0[1]; + __I uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __I uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __I uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; +} stc_tmr4_rcsr_bit_t; + +typedef struct { + __IO uint32_t BUFEN0; + __IO uint32_t BUFEN1; + __IO uint32_t EVTOS0; + __IO uint32_t EVTOS1; + __IO uint32_t EVTOS2; + __IO uint32_t LMC; + uint32_t RESERVED0[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED1[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct { + __IO uint32_t OEUH; + __IO uint32_t OEUL; + __IO uint32_t OEVH; + __IO uint32_t OEVL; + __IO uint32_t OEWH; + __IO uint32_t OEWL; + __IO uint32_t ODT0; + __IO uint32_t ODT1; + __IO uint32_t MOE; + __IO uint32_t AOE; + uint32_t RESERVED0[6]; + __IO uint32_t OSUH0; + __IO uint32_t OSUH1; + __IO uint32_t OSUL0; + __IO uint32_t OSUL1; + __IO uint32_t OSVH0; + __IO uint32_t OSVH1; + __IO uint32_t OSVL0; + __IO uint32_t OSVL1; + __IO uint32_t OSWH0; + __IO uint32_t OSWH1; + __IO uint32_t OSWL0; + __IO uint32_t OSWL1; + uint32_t RESERVED1[4]; +} stc_tmr4_pscr_bit_t; + +typedef struct { + __IO uint32_t EVTRS0; + __IO uint32_t EVTRS1; + __IO uint32_t EVTRS2; + __IO uint32_t PCTS; + uint32_t RESERVED0[12]; +} stc_tmr4_scer_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + uint32_t RESERVED0[1]; + __IO uint32_t CKDIV0; + __IO uint32_t CKDIV1; + __IO uint32_t CKDIV2; + __IO uint32_t CKDIV3; + __IO uint32_t OVSTP; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + __IO uint32_t ZMSKVAL0; + __IO uint32_t ZMSKVAL1; + uint32_t RESERVED2[12]; +} stc_tmr6_gconr_bit_t; + +typedef struct { + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct { + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BTRUA; + __IO uint32_t BTRDA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + __IO uint32_t BTRUB; + __IO uint32_t BTRDB; + __IO uint32_t BENP; + __IO uint32_t BSEP; + __IO uint32_t BTRUP; + __IO uint32_t BTRDP; + uint32_t RESERVED0[4]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED1[8]; +} stc_tmr6_bconr_bit_t; + +typedef struct { + __IO uint32_t DTCEN; + __IO uint32_t SEPA; + uint32_t RESERVED0[2]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + __IO uint32_t DTBTRU; + __IO uint32_t DTBTRD; + uint32_t RESERVED1[24]; +} stc_tmr6_dconr_bit_t; + +typedef struct { + __IO uint32_t STACA0; + __IO uint32_t STACA1; + __IO uint32_t STPCA0; + __IO uint32_t STPCA1; + __IO uint32_t OVFCA0; + __IO uint32_t OVFCA1; + __IO uint32_t UDFCA0; + __IO uint32_t UDFCA1; + __IO uint32_t CMAUCA0; + __IO uint32_t CMAUCA1; + __IO uint32_t CMADCA0; + __IO uint32_t CMADCA1; + __IO uint32_t CMBUCA0; + __IO uint32_t CMBUCA1; + __IO uint32_t CMBDCA0; + __IO uint32_t CMBDCA1; + __IO uint32_t FORCA0; + __IO uint32_t FORCA1; + uint32_t RESERVED0[2]; + __IO uint32_t EMBCA0; + __IO uint32_t EMBCA1; + __IO uint32_t EMBRA0; + __IO uint32_t EMBRA1; + __IO uint32_t EMBSA0; + __IO uint32_t EMBSA1; + uint32_t RESERVED1[2]; + __IO uint32_t OUTENA; + uint32_t RESERVED2[2]; + __IO uint32_t CAPMDA; +} stc_tmr6_pcnar_bit_t; + +typedef struct { + __IO uint32_t STACB0; + __IO uint32_t STACB1; + __IO uint32_t STPCB0; + __IO uint32_t STPCB1; + __IO uint32_t OVFCB0; + __IO uint32_t OVFCB1; + __IO uint32_t UDFCB0; + __IO uint32_t UDFCB1; + __IO uint32_t CMAUCB0; + __IO uint32_t CMAUCB1; + __IO uint32_t CMADCB0; + __IO uint32_t CMADCB1; + __IO uint32_t CMBUCB0; + __IO uint32_t CMBUCB1; + __IO uint32_t CMBDCB0; + __IO uint32_t CMBDCB1; + __IO uint32_t FORCB0; + __IO uint32_t FORCB1; + uint32_t RESERVED0[2]; + __IO uint32_t EMBCB0; + __IO uint32_t EMBCB1; + __IO uint32_t EMBRB0; + __IO uint32_t EMBRB1; + __IO uint32_t EMBSB0; + __IO uint32_t EMBSB1; + uint32_t RESERVED1[2]; + __IO uint32_t OUTENB; + uint32_t RESERVED2[2]; + __IO uint32_t CAPMDB; +} stc_tmr6_pcnbr_bit_t; + +typedef struct { + __IO uint32_t NOFIENGA; + __IO uint32_t NOFICKGA0; + __IO uint32_t NOFICKGA1; + uint32_t RESERVED0[1]; + __IO uint32_t NOFIENGB; + __IO uint32_t NOFICKGB0; + __IO uint32_t NOFICKGB1; + uint32_t RESERVED1[25]; +} stc_tmr6_fcngr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[6]; + __IO uint32_t PCNTE0; + __IO uint32_t PCNTE1; + __IO uint32_t PCNTS0; + __IO uint32_t PCNTS1; + __IO uint32_t PCNTS2; + uint32_t RESERVED2[11]; +} stc_tmr6_vperr_bit_t; + +typedef struct { + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __I uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[8]; + __I uint32_t VPERNUM0; + __I uint32_t VPERNUM1; + __I uint32_t VPERNUM2; + uint32_t RESERVED1[7]; + __I uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + __IO uint32_t HSTA3; + uint32_t RESERVED0[3]; + __IO uint32_t STAS; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + __IO uint32_t HSTA10; + __IO uint32_t HSTA11; + uint32_t RESERVED1[4]; + __IO uint32_t HSTA16; + __IO uint32_t HSTA17; + __IO uint32_t HSTA18; + __IO uint32_t HSTA19; + __IO uint32_t HSTA20; + __IO uint32_t HSTA21; + __IO uint32_t HSTA22; + __IO uint32_t HSTA23; + uint32_t RESERVED2[8]; +} stc_tmr6_hstar_bit_t; + +typedef struct { + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + __IO uint32_t HSTP3; + uint32_t RESERVED0[3]; + __IO uint32_t STPS; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + __IO uint32_t HSTP10; + __IO uint32_t HSTP11; + uint32_t RESERVED1[4]; + __IO uint32_t HSTP16; + __IO uint32_t HSTP17; + __IO uint32_t HSTP18; + __IO uint32_t HSTP19; + __IO uint32_t HSTP20; + __IO uint32_t HSTP21; + __IO uint32_t HSTP22; + __IO uint32_t HSTP23; + uint32_t RESERVED2[8]; +} stc_tmr6_hstpr_bit_t; + +typedef struct { + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + __IO uint32_t HCLE3; + uint32_t RESERVED0[3]; + __IO uint32_t CLES; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + __IO uint32_t HCLE10; + __IO uint32_t HCLE11; + uint32_t RESERVED1[4]; + __IO uint32_t HCLE16; + __IO uint32_t HCLE17; + __IO uint32_t HCLE18; + __IO uint32_t HCLE19; + __IO uint32_t HCLE20; + __IO uint32_t HCLE21; + __IO uint32_t HCLE22; + __IO uint32_t HCLE23; + uint32_t RESERVED2[8]; +} stc_tmr6_hclrr_bit_t; + +typedef struct { + __IO uint32_t HUPD0; + __IO uint32_t HUPD1; + __IO uint32_t HUPD2; + __IO uint32_t HUPD3; + uint32_t RESERVED0[3]; + __IO uint32_t UPDS; + __IO uint32_t HUPD8; + __IO uint32_t HUPD9; + __IO uint32_t HUPD10; + __IO uint32_t HUPD11; + uint32_t RESERVED1[4]; + __IO uint32_t HUPD16; + __IO uint32_t HUPD17; + __IO uint32_t HUPD18; + __IO uint32_t HUPD19; + __IO uint32_t HUPD20; + __IO uint32_t HUPD21; + __IO uint32_t HUPD22; + __IO uint32_t HUPD23; + uint32_t RESERVED2[8]; +} stc_tmr6_hupdr_bit_t; + +typedef struct { + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + __IO uint32_t HCPA2; + __IO uint32_t HCPA3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + __IO uint32_t HCPA10; + __IO uint32_t HCPA11; + uint32_t RESERVED1[4]; + __IO uint32_t HCPA16; + __IO uint32_t HCPA17; + __IO uint32_t HCPA18; + __IO uint32_t HCPA19; + __IO uint32_t HCPA20; + __IO uint32_t HCPA21; + __IO uint32_t HCPA22; + __IO uint32_t HCPA23; + uint32_t RESERVED2[8]; +} stc_tmr6_hcpar_bit_t; + +typedef struct { + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + __IO uint32_t HCPB2; + __IO uint32_t HCPB3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + __IO uint32_t HCPB10; + __IO uint32_t HCPB11; + uint32_t RESERVED1[4]; + __IO uint32_t HCPB16; + __IO uint32_t HCPB17; + __IO uint32_t HCPB18; + __IO uint32_t HCPB19; + __IO uint32_t HCPB20; + __IO uint32_t HCPB21; + __IO uint32_t HCPB22; + __IO uint32_t HCPB23; + uint32_t RESERVED2[8]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + uint32_t RESERVED0[4]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + __IO uint32_t HCUP18; + __IO uint32_t HCUP19; + __IO uint32_t HCUP20; + __IO uint32_t HCUP21; + __IO uint32_t HCUP22; + __IO uint32_t HCUP23; + uint32_t RESERVED1[8]; +} stc_tmr6_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + uint32_t RESERVED0[4]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + __IO uint32_t HCDO18; + __IO uint32_t HCDO19; + __IO uint32_t HCDO20; + __IO uint32_t HCDO21; + __IO uint32_t HCDO22; + __IO uint32_t HCDO23; + uint32_t RESERVED1[8]; +} stc_tmr6_hcdor_bit_t; + +typedef struct { + __IO uint32_t NOFIENTA; + __IO uint32_t NOFICKTA0; + __IO uint32_t NOFICKTA1; + uint32_t RESERVED0[1]; + __IO uint32_t NOFIENTB; + __IO uint32_t NOFICKTB0; + __IO uint32_t NOFICKTB1; + uint32_t RESERVED1[1]; + __IO uint32_t NOFIENTC; + __IO uint32_t NOFICKTC0; + __IO uint32_t NOFICKTC1; + uint32_t RESERVED2[1]; + __IO uint32_t NOFIENTD; + __IO uint32_t NOFICKTD0; + __IO uint32_t NOFICKTD1; + uint32_t RESERVED3[17]; +} stc_tmr6cr_fcntr_bit_t; + +typedef struct { + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + __IO uint32_t SSTA3; + __IO uint32_t SSTA4; + __IO uint32_t SSTA5; + __IO uint32_t SSTA6; + __IO uint32_t SSTA7; + __IO uint32_t SSTA8; + uint32_t RESERVED0[24]; +} stc_tmr6cr_sstar_bit_t; + +typedef struct { + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + __IO uint32_t SSTP3; + __IO uint32_t SSTP4; + __IO uint32_t SSTP5; + __IO uint32_t SSTP6; + __IO uint32_t SSTP7; + __IO uint32_t SSTP8; + uint32_t RESERVED0[24]; +} stc_tmr6cr_sstpr_bit_t; + +typedef struct { + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + __IO uint32_t SCLE3; + __IO uint32_t SCLE4; + __IO uint32_t SCLE5; + __IO uint32_t SCLE6; + __IO uint32_t SCLE7; + __IO uint32_t SCLE8; + uint32_t RESERVED0[24]; +} stc_tmr6cr_sclrr_bit_t; + +typedef struct { + __IO uint32_t SUPD1; + __IO uint32_t SUPD2; + __IO uint32_t SUPD3; + __IO uint32_t SUPD4; + __IO uint32_t SUPD5; + __IO uint32_t SUPD6; + __IO uint32_t SUPD7; + __IO uint32_t SUPD8; + uint32_t RESERVED0[24]; +} stc_tmr6cr_supdr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + uint32_t RESERVED0[4]; + __IO uint32_t OVSTP; + uint32_t RESERVED1[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; +} stc_tmra_bcstr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; +} stc_tmra_hconr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[3]; +} stc_tmra_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[3]; +} stc_tmra_hcdor_bit_t; + +typedef struct { + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + uint32_t RESERVED0[12]; +} stc_tmra_iconr_bit_t; + +typedef struct { + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + uint32_t RESERVED0[12]; +} stc_tmra_econr_bit_t; + +typedef struct { + __IO uint32_t NOFIENTG; + uint32_t RESERVED0[7]; + __IO uint32_t NOFIENCA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENCB; + uint32_t RESERVED2[3]; +} stc_tmra_fconr_bit_t; + +typedef struct { + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + uint32_t RESERVED0[12]; +} stc_tmra_stflr_bit_t; + +typedef struct { + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + uint32_t RESERVED0[13]; +} stc_tmra_bconr_bit_t; + +typedef struct { + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + uint32_t RESERVED2[2]; + __IO uint32_t NOFIENCP; + uint32_t RESERVED3[3]; +} stc_tmra_cconr_bit_t; + +typedef struct { + __IO uint32_t STAC0; + __IO uint32_t STAC1; + __IO uint32_t STPC0; + __IO uint32_t STPC1; + __IO uint32_t CMPC0; + __IO uint32_t CMPC1; + __IO uint32_t PERC0; + __IO uint32_t PERC1; + __IO uint32_t FORC0; + __IO uint32_t FORC1; + uint32_t RESERVED0[2]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[3]; +} stc_tmra_pconr_bit_t; + +typedef struct { + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct { + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct { + __I uint32_t PE; + __I uint32_t FE; + uint32_t RESERVED0[1]; + __I uint32_t ORE; + __I uint32_t BE; + __I uint32_t RXNE; + __I uint32_t TC; + __I uint32_t TXE; + __I uint32_t RTOF; + __I uint32_t WKUP; + __I uint32_t LBD; + uint32_t RESERVED1[5]; + __I uint32_t MPB; + uint32_t RESERVED2[15]; +} stc_usart_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[22]; +} stc_usart_dr_bit_t; + +typedef struct { + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + uint32_t RESERVED0[1]; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED1[1]; + __IO uint32_t M; + uint32_t RESERVED2[2]; + __IO uint32_t OVER8; + __IO uint32_t CPE; + __IO uint32_t CFE; + uint32_t RESERVED3[1]; + __IO uint32_t CORE; + __IO uint32_t CRTOF; + __IO uint32_t CBE; + __IO uint32_t CWKUP; + __IO uint32_t CLBD; + __IO uint32_t MS; + uint32_t RESERVED4[3]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct { + __IO uint32_t MPE; + __IO uint32_t WKUPIE; + __IO uint32_t BEIE; + __IO uint32_t BEE; + __IO uint32_t LBDIE; + __IO uint32_t LBDL; + __IO uint32_t SBKL0; + __IO uint32_t SBKL1; + __IO uint32_t WKUPE; + uint32_t RESERVED0[2]; + __IO uint32_t CLKC0; + __IO uint32_t CLKC1; + __IO uint32_t STOP; + __IO uint32_t LINEN; + uint32_t RESERVED1[1]; + __IO uint32_t SBK; + __IO uint32_t SBKM; + uint32_t RESERVED2[14]; +} stc_usart_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t HDSEL; + __IO uint32_t LOOP; + __IO uint32_t SCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RTSE; + __IO uint32_t CTSE; + uint32_t RESERVED2[11]; + __IO uint32_t BCN0; + __IO uint32_t BCN1; + __IO uint32_t BCN2; + uint32_t RESERVED3[8]; +} stc_usart_cr3_bit_t; + +typedef struct { + __IO uint32_t PSC0; + __IO uint32_t PSC1; + __IO uint32_t LBMPSC0; + __IO uint32_t LBMPSC1; + uint32_t RESERVED0[28]; +} stc_usart_pr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t VBUSOVEN; + __IO uint32_t VBUSVAL; + uint32_t RESERVED1[24]; +} stc_usbfs_gvbuscfg_bit_t; + +typedef struct { + __IO uint32_t GINTMSK; + uint32_t RESERVED0[4]; + __IO uint32_t DMAEN; + uint32_t RESERVED1[1]; + __IO uint32_t TXFELVL; + __IO uint32_t PTXFELVL; + uint32_t RESERVED2[23]; +} stc_usbfs_gahbcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[22]; + __IO uint32_t FHMOD; + __IO uint32_t FDMOD; + uint32_t RESERVED2[1]; +} stc_usbfs_gusbcfg_bit_t; + +typedef struct { + __IO uint32_t CSRST; + __IO uint32_t HSRST; + __IO uint32_t FCRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __I uint32_t DMAREQ; + __I uint32_t AHBIDL; +} stc_usbfs_grstctl_bit_t; + +typedef struct { + __I uint32_t CMOD; + __IO uint32_t MMIS; + uint32_t RESERVED0[1]; + __IO uint32_t SOF; + __I uint32_t RXFNE; + __I uint32_t NPTXFE; + __I uint32_t GINAKEFF; + __I uint32_t GONAKEFF; + uint32_t RESERVED1[2]; + __IO uint32_t ESUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDNE; + __IO uint32_t ISOODRP; + __IO uint32_t EOPF; + uint32_t RESERVED2[2]; + __I uint32_t IEPINT; + __I uint32_t OEPINT; + __IO uint32_t IISOIXFR; + __IO uint32_t IPXFR_INCOMPISOOUT; + __IO uint32_t DATAFSUSP; + uint32_t RESERVED3[1]; + __I uint32_t HPRTINT; + __I uint32_t HCINT; + __I uint32_t PTXFE; + __IO uint32_t LPMINT; + __IO uint32_t CIDSCHG; + __IO uint32_t DISCINT; + __IO uint32_t VBUSVINT; + __IO uint32_t WKUINT; +} stc_usbfs_gintsts_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t MMISM; + uint32_t RESERVED1[1]; + __IO uint32_t SOFM; + __IO uint32_t RXFNEM; + __IO uint32_t NPTXFEM; + __IO uint32_t GINAKEFFM; + __IO uint32_t GONAKEFFM; + uint32_t RESERVED2[2]; + __IO uint32_t ESUSPM; + __IO uint32_t USBSUSPM; + __IO uint32_t USBRSTM; + __IO uint32_t ENUMDNEM; + __IO uint32_t ISOODRPM; + __IO uint32_t EOPFM; + uint32_t RESERVED3[2]; + __IO uint32_t IEPIM; + __IO uint32_t OEPIM; + __IO uint32_t IISOIXFRM; + __IO uint32_t IPXFRM_INCOMPISOOUTM; + __IO uint32_t DATAFSUSPM; + uint32_t RESERVED4[1]; + __IO uint32_t HPRTIM; + __IO uint32_t HCIM; + __IO uint32_t PTXFEM; + __IO uint32_t LPMINTM; + __IO uint32_t CIDSCHGM; + __IO uint32_t DISCIM; + __IO uint32_t VBUSVIM; + __IO uint32_t WKUIM; +} stc_usbfs_gintmsk_bit_t; + +typedef struct { + __IO uint32_t LPMEN; + __IO uint32_t LPMACK; + uint32_t RESERVED0[4]; + __IO uint32_t REMWAKE; + __IO uint32_t L1SSEN; + uint32_t RESERVED1[4]; + __IO uint32_t L1DSEN; + uint32_t RESERVED2[2]; + __I uint32_t SLPSTS; + __I uint32_t L1RSMOK; + uint32_t RESERVED3[7]; + __IO uint32_t SENDLPM; + uint32_t RESERVED4[3]; + __IO uint32_t ENBSEL; + uint32_t RESERVED5[3]; +} stc_usbfs_glpmcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FSLSS; + uint32_t RESERVED1[29]; +} stc_usbfs_hcfg_bit_t; + +typedef struct { + __I uint32_t PCSTS; + __IO uint32_t PCDET; + __IO uint32_t PENA; + __IO uint32_t PENCHNG; + uint32_t RESERVED0[2]; + __IO uint32_t PRES; + __IO uint32_t PSUSP; + __IO uint32_t PRST; + uint32_t RESERVED1[3]; + __IO uint32_t PWPR; + uint32_t RESERVED2[19]; +} stc_usbfs_hprt_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSDEV; + uint32_t RESERVED2[11]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t CHH; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + uint32_t RESERVED0[1]; + __IO uint32_t TXERR; + __IO uint32_t BBERR; + __IO uint32_t FRMOR; + __IO uint32_t DTERR; + uint32_t RESERVED1[21]; +} stc_usbfs_hcint_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t CHHM; + __IO uint32_t AHBERRM; + __IO uint32_t STALLM; + __IO uint32_t NAKM; + __IO uint32_t ACKM; + uint32_t RESERVED0[1]; + __IO uint32_t TXERRM; + __IO uint32_t BBERRM; + __IO uint32_t FRMORM; + __IO uint32_t DTERRM; + uint32_t RESERVED1[21]; +} stc_usbfs_hcintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NZLSOHSK; + uint32_t RESERVED1[29]; +} stc_usbfs_dcfg_bit_t; + +typedef struct { + __IO uint32_t RWUSIG; + __IO uint32_t SDIS; + __I uint32_t GINSTS; + __I uint32_t GONSTS; + uint32_t RESERVED0[3]; + __O uint32_t SGINAK; + __O uint32_t CGINAK; + __O uint32_t SGONAK; + __O uint32_t CGONAK; + __IO uint32_t POPRGDNE; + uint32_t RESERVED1[20]; +} stc_usbfs_dctl_bit_t; + +typedef struct { + __I uint32_t SUSPSTS; + uint32_t RESERVED0[2]; + __I uint32_t EERR; + uint32_t RESERVED1[28]; +} stc_usbfs_dsts_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t ITTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[6]; + __IO uint32_t NAKM; + uint32_t RESERVED2[18]; +} stc_usbfs_diepmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[27]; +} stc_usbfs_doepmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[3]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t TOC; + __IO uint32_t TTXFE; + uint32_t RESERVED1[1]; + __IO uint32_t INEPNE; + __I uint32_t TXFE; + uint32_t RESERVED2[24]; +} stc_usbfs_diepint_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t EONUM_DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[3]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID_SEVNFRM; + __IO uint32_t SODDFRM; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t STUP; + __IO uint32_t OTEPDIS; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[25]; +} stc_usbfs_doepint_bit_t; + +typedef struct { + uint32_t RESERVED0[19]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[12]; +} stc_usbfs_doeptsiz0_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + __I uint32_t DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID; + __IO uint32_t SD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl_bit_t; + +typedef struct { + __IO uint32_t STPPCLK; + __IO uint32_t GATEHCLK; + uint32_t RESERVED0[3]; + __IO uint32_t ENL1GTG; + __IO uint32_t PHYSLEEP; + __IO uint32_t SUSP; + uint32_t RESERVED1[24]; +} stc_usbfs_gcctl_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t VBUSOVEN; + __IO uint32_t VBUSVAL; + uint32_t RESERVED1[24]; +} stc_usbhs_gvbuscfg_bit_t; + +typedef struct { + __IO uint32_t GINTMSK; + uint32_t RESERVED0[4]; + __IO uint32_t DMAEN; + uint32_t RESERVED1[1]; + __IO uint32_t TXFELVL; + __IO uint32_t PTXFELVL; + uint32_t RESERVED2[23]; +} stc_usbhs_gahbcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[8]; + __IO uint32_t PHYLPCS; + uint32_t RESERVED2[1]; + __IO uint32_t ULFSLS; + __IO uint32_t ULPIAR; + __IO uint32_t ULPICSM; + __IO uint32_t ULPIEVBUSD; + __IO uint32_t ULPIEVBUSI; + uint32_t RESERVED3[1]; + __IO uint32_t PCCI; + __IO uint32_t PTCI; + __IO uint32_t ULPIPD; + uint32_t RESERVED4[3]; + __IO uint32_t FHMOD; + __IO uint32_t FDMOD; + uint32_t RESERVED5[1]; +} stc_usbhs_gusbcfg_bit_t; + +typedef struct { + __IO uint32_t CSRST; + __IO uint32_t HSRST; + __IO uint32_t FCRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __I uint32_t DMAREQ; + __I uint32_t AHBIDL; +} stc_usbhs_grstctl_bit_t; + +typedef struct { + __I uint32_t CMOD; + __IO uint32_t MMIS; + uint32_t RESERVED0[1]; + __IO uint32_t SOF; + __I uint32_t RXFNE; + __I uint32_t NPTXFE; + __I uint32_t GINAKEFF; + __I uint32_t GONAKEFF; + uint32_t RESERVED1[2]; + __IO uint32_t ESUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDNE; + __IO uint32_t ISOODRP; + __IO uint32_t EOPF; + uint32_t RESERVED2[2]; + __I uint32_t IEPINT; + __I uint32_t OEPINT; + __IO uint32_t IISOIXFR; + __IO uint32_t IPXFR_INCOMPISOOUT; + __IO uint32_t DATAFSUSP; + uint32_t RESERVED3[1]; + __I uint32_t HPRTINT; + __I uint32_t HCINT; + __I uint32_t PTXFE; + __IO uint32_t LPMINT; + __IO uint32_t CIDSCHG; + __IO uint32_t DISCINT; + __IO uint32_t VBUSVINT; + __IO uint32_t WKUINT; +} stc_usbhs_gintsts_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t MMISM; + uint32_t RESERVED1[1]; + __IO uint32_t SOFM; + __IO uint32_t RXFNEM; + __IO uint32_t NPTXFEM; + __IO uint32_t GINAKEFFM; + __IO uint32_t GONAKEFFM; + uint32_t RESERVED2[2]; + __IO uint32_t ESUSPM; + __IO uint32_t USBSUSPM; + __IO uint32_t USBRSTM; + __IO uint32_t ENUMDNEM; + __IO uint32_t ISOODRPM; + __IO uint32_t EOPFM; + uint32_t RESERVED3[2]; + __IO uint32_t IEPIM; + __IO uint32_t OEPIM; + __IO uint32_t IISOIXFRM; + __IO uint32_t IPXFRM_INCOMPISOOUTM; + __IO uint32_t DATAFSUSPM; + uint32_t RESERVED4[1]; + __IO uint32_t HPRTIM; + __IO uint32_t HCIM; + __IO uint32_t PTXFEM; + __IO uint32_t LPMINTM; + __IO uint32_t CIDSCHGM; + __IO uint32_t DISCIM; + __IO uint32_t VBUSVIM; + __IO uint32_t WKUIM; +} stc_usbhs_gintmsk_bit_t; + +typedef struct { + __IO uint32_t LPMEN; + __IO uint32_t LPMACK; + uint32_t RESERVED0[4]; + __IO uint32_t REMWAKE; + __IO uint32_t L1SSEN; + uint32_t RESERVED1[4]; + __IO uint32_t L1DSEN; + uint32_t RESERVED2[2]; + __I uint32_t SLPSTS; + __I uint32_t L1RSMOK; + uint32_t RESERVED3[7]; + __IO uint32_t SENDLPM; + uint32_t RESERVED4[3]; + __IO uint32_t ENBSEL; + uint32_t RESERVED5[3]; +} stc_usbhs_glpmcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FSLSS; + uint32_t RESERVED1[29]; +} stc_usbhs_hcfg_bit_t; + +typedef struct { + __I uint32_t PCSTS; + __IO uint32_t PCDET; + __IO uint32_t PENA; + __IO uint32_t PENCHNG; + __IO uint32_t POCA; + __IO uint32_t POCCHNG; + __IO uint32_t PRES; + __IO uint32_t PSUSP; + __IO uint32_t PRST; + uint32_t RESERVED0[3]; + __IO uint32_t PWPR; + uint32_t RESERVED1[19]; +} stc_usbhs_hprt_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSDEV; + uint32_t RESERVED2[11]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t COMPLSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLITEN; +} stc_usbhs_hcsplt_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t CHH; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t TXERR; + __IO uint32_t BBERR; + __IO uint32_t FRMOR; + __IO uint32_t DTERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t CHHM; + __IO uint32_t AHBERRM; + __IO uint32_t STALLM; + __IO uint32_t NAKM; + __IO uint32_t ACKM; + __IO uint32_t NYETM; + __IO uint32_t TXERRM; + __IO uint32_t BBERRM; + __IO uint32_t FRMORM; + __IO uint32_t DTERRM; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t DOPING; +} stc_usbhs_hctsiz_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NZLSOHSK; + uint32_t RESERVED1[29]; +} stc_usbhs_dcfg_bit_t; + +typedef struct { + __IO uint32_t RWUSIG; + __IO uint32_t SDIS; + __I uint32_t GINSTS; + __I uint32_t GONSTS; + uint32_t RESERVED0[3]; + __IO uint32_t SGINAK; + __IO uint32_t CGINAK; + __IO uint32_t SGONAK; + __IO uint32_t CGONAK; + __IO uint32_t POPRGDNE; + uint32_t RESERVED1[20]; +} stc_usbhs_dctl_bit_t; + +typedef struct { + __I uint32_t SUSPSTS; + uint32_t RESERVED0[2]; + __I uint32_t EERR; + uint32_t RESERVED1[28]; +} stc_usbhs_dsts_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t TTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[1]; + __IO uint32_t TXFURM; + uint32_t RESERVED2[4]; + __IO uint32_t NAKM; + uint32_t RESERVED3[18]; +} stc_usbhs_diepmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[1]; + __IO uint32_t OPEM; + uint32_t RESERVED3[5]; + __IO uint32_t NYETM; + uint32_t RESERVED4[17]; +} stc_usbhs_doepmsk_bit_t; + +typedef struct { + __IO uint32_t NONISOTHREN; + __IO uint32_t ISOTHREN; + uint32_t RESERVED0[14]; + __IO uint32_t RXTHREN; + uint32_t RESERVED1[10]; + __IO uint32_t ARPEN; + uint32_t RESERVED2[4]; +} stc_usbhs_dthrctl_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t IEP1INT; + uint32_t RESERVED1[15]; + __IO uint32_t OEP1INT; + uint32_t RESERVED2[14]; +} stc_usbhs_deachint_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t IEP1INTM; + uint32_t RESERVED1[15]; + __IO uint32_t OEP1INTM; + uint32_t RESERVED2[14]; +} stc_usbhs_deachintmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t TTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[1]; + __IO uint32_t TXFURM; + uint32_t RESERVED2[4]; + __IO uint32_t NAKM; + uint32_t RESERVED3[18]; +} stc_usbhs_diepeachmsk1_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[1]; + __IO uint32_t OPEM; + uint32_t RESERVED3[5]; + __IO uint32_t NYETM; + uint32_t RESERVED4[17]; +} stc_usbhs_doepeachmsk1_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[3]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t TOC; + __IO uint32_t TTXFE; + uint32_t RESERVED1[1]; + __IO uint32_t INEPNE; + __I uint32_t TXFE; + __IO uint32_t TXFIFOUDRN; + uint32_t RESERVED2[2]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BERR; + __IO uint32_t NAK; + uint32_t RESERVED3[18]; +} stc_usbhs_diepint_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + __I uint32_t EONUM_DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[3]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID_SEVNFRM; + __IO uint32_t SODDFRM; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + __I uint32_t EPTYP0; + __I uint32_t EPTYP1; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED3[2]; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t STUP; + __IO uint32_t OTEPDIS; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[7]; + __IO uint32_t NYET; + uint32_t RESERVED3[17]; +} stc_usbhs_doepint_bit_t; + +typedef struct { + uint32_t RESERVED0[19]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[12]; +} stc_usbhs_doeptsiz0_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + __I uint32_t DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID; + __IO uint32_t SD1PID; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl_bit_t; + +typedef struct { + __IO uint32_t STPPCLK; + __IO uint32_t GATEHCLK; + uint32_t RESERVED0[3]; + __IO uint32_t ENL1GTG; + __IO uint32_t PHYSLEEP; + __IO uint32_t SUSP; + uint32_t RESERVED1[24]; +} stc_usbhs_gcctl_bit_t; + +typedef struct { + __IO uint32_t PERI0; + __IO uint32_t PERI1; + uint32_t RESERVED0[2]; + __IO uint32_t CKS0; + __IO uint32_t CKS1; + __IO uint32_t CKS2; + __IO uint32_t CKS3; + __IO uint32_t WDPT0; + __IO uint32_t WDPT1; + __IO uint32_t WDPT2; + __IO uint32_t WDPT3; + uint32_t RESERVED1[4]; + __IO uint32_t SLPOFF; + uint32_t RESERVED2[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct { + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_adc_trgsr_bit_t TRGSR_b; + uint32_t RESERVED2[96]; + stc_adc_exchselr_bit_t EXCHSELR_b; + uint32_t RESERVED3[344]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + stc_adc_isclrr_bit_t ISCLRR_b; + uint32_t RESERVED4[40]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED5[656]; + stc_adc_awdcr_bit_t AWDCR_b; + stc_adc_awdsr_bit_t AWDSR_b; + stc_adc_awdsclrr_bit_t AWDSCLRR_b; + uint32_t RESERVED6[32]; + stc_adc_awd0chsr_bit_t AWD0CHSR_b; +} bCM_ADC_TypeDef; + +typedef struct { + stc_aes_cr_bit_t CR_b; +} bCM_AES_TypeDef; + +typedef struct { + stc_aos_intsfttrg_bit_t INTSFTTRG_b; + stc_aos_dcu_trgsel_bit_t DCU_TRGSEL1_b; + stc_aos_dcu_trgsel_bit_t DCU_TRGSEL2_b; + stc_aos_dcu_trgsel_bit_t DCU_TRGSEL3_b; + stc_aos_dcu_trgsel_bit_t DCU_TRGSEL4_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL0_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL1_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL2_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL3_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL4_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL5_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL6_b; + stc_aos_dma1_trgsel_bit_t DMA1_TRGSEL7_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL0_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL1_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL2_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL3_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL4_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL5_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL6_b; + stc_aos_dma2_trgsel_bit_t DMA2_TRGSEL7_b; + stc_aos_dma_trgselrc_bit_t DMA_TRGSELRC_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR0_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR1_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR2_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR3_b; + stc_aos_pevnttrgsr_bit_t PEVNTTRGSR12_b; + stc_aos_pevnttrgsr_bit_t PEVNTTRGSR34_b; + stc_aos_tmr0_htssr_bit_t TMR0_HTSSR_b; + stc_aos_tmr2_htssr_bit_t TMR2_HTSSR_b; + stc_aos_hash_itrgsela_bit_t HASH_ITRGSELA_b; + stc_aos_hash_itrgselb_bit_t HASH_ITRGSELB_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR0_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR1_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR2_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR3_b; + stc_aos_ots_trg_bit_t OTS_TRG_b; + stc_aos_adc1_itrgselr_bit_t ADC1_ITRGSELR0_b; + stc_aos_adc1_itrgselr_bit_t ADC1_ITRGSELR1_b; + stc_aos_adc2_itrgselr_bit_t ADC2_ITRGSELR0_b; + stc_aos_adc2_itrgselr_bit_t ADC2_ITRGSELR1_b; + stc_aos_adc3_itrgselr_bit_t ADC3_ITRGSELR0_b; + stc_aos_adc3_itrgselr_bit_t ADC3_ITRGSELR1_b; + uint32_t RESERVED0[1568]; + stc_aos_pevntnfcr_bit_t PEVNTNFCR_b; +} bCM_AOS_TypeDef; + +typedef struct { + uint32_t RESERVED0[1280]; + stc_can_cfg_stat_bit_t CFG_STAT_b; + stc_can_tcmd_bit_t TCMD_b; + stc_can_tctrl_bit_t TCTRL_b; + stc_can_rctrl_bit_t RCTRL_b; + stc_can_rtie_bit_t RTIE_b; + stc_can_rtif_bit_t RTIF_b; + stc_can_errint_bit_t ERRINT_b; + uint32_t RESERVED1[80]; + stc_can_tdc_bit_t TDC_b; + uint32_t RESERVED2[16]; + stc_can_acfctrl_bit_t ACFCTRL_b; + uint32_t RESERVED3[8]; + stc_can_acfen_bit_t ACFEN_b; + stc_can_acf_bit_t ACF_b; + uint32_t RESERVED4[16]; + stc_can_tbslot_bit_t TBSLOT_b; + stc_can_ttcfg_bit_t TTCFG_b; + stc_can_ref_msg_bit_t REF_MSG_b; + stc_can_trg_cfg_bit_t TRG_CFG_b; +} bCM_CAN_TypeDef; + +typedef struct { + stc_cmp_mdr_bit_t MDR_b; + stc_cmp_fir_bit_t FIR_b; + stc_cmp_ocr_bit_t OCR_b; + stc_cmp_pmsr_bit_t PMSR_b; + stc_cmp_twsr_bit_t TWSR_b; + stc_cmp_twpr_bit_t TWPR_b; + stc_cmp_visr_bit_t VISR_b; +} bCM_CMP_TypeDef; + +typedef struct { + stc_cmu_xtal32cr_bit_t XTAL32CR_b; + uint32_t RESERVED0[24]; + stc_cmu_xtal32cfgr_bit_t XTAL32CFGR_b; + uint32_t RESERVED1[184]; + stc_cmu_lrccr_bit_t LRCCR_b; + uint32_t RESERVED2[24]; + stc_cmu_rtclrccr_bit_t RTCLRCCR_b; + uint32_t RESERVED3[17080]; + stc_cmu_xtalcfgr_bit_t XTALCFGR_b; + uint32_t RESERVED4[236936]; + stc_cmu_pllhcr_bit_t PLLHCR_b; + uint32_t RESERVED5[24]; + stc_cmu_pllacr_bit_t PLLACR_b; + uint32_t RESERVED6[24]; + stc_cmu_xtalcr_bit_t XTALCR_b; + uint32_t RESERVED7[24]; + stc_cmu_hrccr_bit_t HRCCR_b; + uint32_t RESERVED8[8]; + stc_cmu_mrccr_bit_t MRCCR_b; + uint32_t RESERVED9[24]; + stc_cmu_oscstbsr_bit_t OSCSTBSR_b; + stc_cmu_mcocfgr_bit_t MCOCFGR1_b; + stc_cmu_mcocfgr_bit_t MCOCFGR2_b; + stc_cmu_tpiuckcfgr_bit_t TPIUCKCFGR_b; + stc_cmu_xtalstdcr_bit_t XTALSTDCR_b; + stc_cmu_xtalstdsr_bit_t XTALSTDSR_b; + uint32_t RESERVED10[1520]; + stc_cmu_pllhcfgr_bit_t PLLHCFGR_b; +} bCM_CMU_TypeDef; + +typedef struct { + stc_crc_cr_bit_t CR_b; +} bCM_CRC_TypeDef; + +typedef struct { + stc_ctc_cr1_bit_t CR1_b; + uint32_t RESERVED0[32]; + stc_ctc_str_bit_t STR_b; +} bCM_CTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_dac_dacr_bit_t DACR_b; + stc_dac_daadpcr_bit_t DAADPCR_b; + uint32_t RESERVED1[160]; + stc_dac_daocr_bit_t DAOCR_b; +} bCM_DAC_TypeDef; + +typedef struct { + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intsel_bit_t INTSEL_b; +} bCM_DCU_TypeDef; + +typedef struct { + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + stc_dma_chen_bit_t CHEN_b; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED0[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + uint32_t RESERVED1[32]; + stc_dma_chenclr_bit_t CHENCLR_b; + uint32_t RESERVED2[288]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[480]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[480]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[480]; + stc_dma_chctl_bit_t CHCTL3_b; + uint32_t RESERVED6[480]; + stc_dma_chctl_bit_t CHCTL4_b; + uint32_t RESERVED7[480]; + stc_dma_chctl_bit_t CHCTL5_b; + uint32_t RESERVED8[480]; + stc_dma_chctl_bit_t CHCTL6_b; + uint32_t RESERVED9[480]; + stc_dma_chctl_bit_t CHCTL7_b; +} bCM_DMA_TypeDef; + +typedef struct { + stc_dvp_ctr_bit_t CTR_b; + uint32_t RESERVED0[32]; + stc_dvp_str_bit_t STR_b; + stc_dvp_ier_bit_t IER_b; +} bCM_DVP_TypeDef; + +typedef struct { + uint32_t RESERVED0[160]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1696]; + stc_efm_mmf_remcr_bit_t MMF_REMCR0_b; + stc_efm_mmf_remcr_bit_t MMF_REMCR1_b; + uint32_t RESERVED2[928]; + stc_efm_wlock_bit_t WLOCK_b; + uint32_t RESERVED3[96]; + stc_efm_f0nwprt0_bit_t F0NWPRT0_b; + stc_efm_f0nwprt1_bit_t F0NWPRT1_b; + stc_efm_f0nwprt2_bit_t F0NWPRT2_b; + stc_efm_f0nwprt3_bit_t F0NWPRT3_b; + stc_efm_f1nwprt0_bit_t F1NWPRT0_b; + stc_efm_f1nwprt1_bit_t F1NWPRT1_b; + stc_efm_f1nwprt2_bit_t F1NWPRT2_b; + stc_efm_f1nwprt3_bit_t F1NWPRT3_b; +} bCM_EFM_TypeDef; + +typedef struct { + stc_emb_ctl1_bit_t CTL1_b; + stc_emb_ctl2_bit_t CTL2_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; + stc_emb_rlssel_bit_t RLSSEL_b; +} bCM_EMB_TypeDef; + +typedef struct { + uint32_t RESERVED0[172160]; + stc_eth_mac_ifconfr_bit_t MAC_IFCONFR_b; + uint32_t RESERVED1[352096]; + stc_eth_mac_configr_bit_t MAC_CONFIGR_b; + stc_eth_mac_fltctlr_bit_t MAC_FLTCTLR_b; + uint32_t RESERVED2[64]; + stc_eth_mac_smiaddr_bit_t MAC_SMIADDR_b; + uint32_t RESERVED3[32]; + stc_eth_mac_floctlr_bit_t MAC_FLOCTLR_b; + stc_eth_mac_vtafltr_bit_t MAC_VTAFLTR_b; + uint32_t RESERVED4[32]; + stc_eth_mac_macstsr_bit_t MAC_MACSTSR_b; + uint32_t RESERVED5[32]; + stc_eth_mac_pmtctlr_bit_t MAC_PMTCTLR_b; + uint32_t RESERVED6[64]; + stc_eth_mac_intstsr_bit_t MAC_INTSTSR_b; + stc_eth_mac_intmskr_bit_t MAC_INTMSKR_b; + stc_eth_mac_macadhr0_bit_t MAC_MACADHR0_b; + uint32_t RESERVED7[32]; + stc_eth_mac_macadhr1_bit_t MAC_MACADHR1_b; + uint32_t RESERVED8[32]; + stc_eth_mac_macadhr2_bit_t MAC_MACADHR2_b; + uint32_t RESERVED9[32]; + stc_eth_mac_macadhr3_bit_t MAC_MACADHR3_b; + uint32_t RESERVED10[32]; + stc_eth_mac_macadhr4_bit_t MAC_MACADHR4_b; + uint32_t RESERVED11[1248]; + stc_eth_mmc_mmcctlr_bit_t MMC_MMCCTLR_b; + stc_eth_mmc_revstsr_bit_t MMC_REVSTSR_b; + stc_eth_mmc_trsstsr_bit_t MMC_TRSSTSR_b; + stc_eth_mmc_ritctlr_bit_t MMC_RITCTLR_b; + stc_eth_mmc_titctlr_bit_t MMC_TITCTLR_b; + uint32_t RESERVED12[5984]; + stc_eth_mac_l34ctlr_bit_t MAC_L34CTLR_b; + uint32_t RESERVED13[3072]; + stc_eth_mac_vtactlr_bit_t MAC_VTACTLR_b; + uint32_t RESERVED14[3008]; + stc_eth_ptp_tspctlr_bit_t PTP_TSPCTLR_b; + uint32_t RESERVED15[128]; + stc_eth_ptp_tmunser_bit_t PTP_TMUNSER_b; + uint32_t RESERVED16[128]; + stc_eth_ptp_tspstsr_bit_t PTP_TSPSTSR_b; + stc_eth_ptp_ppsctlr_bit_t PTP_PPSCTLR_b; + uint32_t RESERVED17[18048]; + stc_eth_dma_busmodr_bit_t DMA_BUSMODR_b; + uint32_t RESERVED18[128]; + stc_eth_dma_dmastsr_bit_t DMA_DMASTSR_b; + stc_eth_dma_oprmodr_bit_t DMA_OPRMODR_b; + stc_eth_dma_intenar_bit_t DMA_INTENAR_b; + stc_eth_dma_rfrcntr_bit_t DMA_RFRCNTR_b; +} bCM_ETH_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bCM_FCM_TypeDef; + +typedef struct { + stc_fmac_enr_bit_t ENR_b; + uint32_t RESERVED0[32]; + stc_fmac_ier_bit_t IER_b; + uint32_t RESERVED1[96]; + stc_fmac_str_bit_t STR_b; +} bCM_FMAC_TypeDef; + +typedef struct { + stc_gpio_pidr_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podr_bit_t PODRA_b; + stc_gpio_poer_bit_t POERA_b; + stc_gpio_posr_bit_t POSRA_b; + stc_gpio_porr_bit_t PORRA_b; + stc_gpio_potr_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidr_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podr_bit_t PODRB_b; + stc_gpio_poer_bit_t POERB_b; + stc_gpio_posr_bit_t POSRB_b; + stc_gpio_porr_bit_t PORRB_b; + stc_gpio_potr_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidr_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podr_bit_t PODRC_b; + stc_gpio_poer_bit_t POERC_b; + stc_gpio_posr_bit_t POSRC_b; + stc_gpio_porr_bit_t PORRC_b; + stc_gpio_potr_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidr_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podr_bit_t PODRD_b; + stc_gpio_poer_bit_t POERD_b; + stc_gpio_posr_bit_t POSRD_b; + stc_gpio_porr_bit_t PORRD_b; + stc_gpio_potr_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidr_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podr_bit_t PODRE_b; + stc_gpio_poer_bit_t POERE_b; + stc_gpio_posr_bit_t POSRE_b; + stc_gpio_porr_bit_t PORRE_b; + stc_gpio_potr_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidr_bit_t PIDRF_b; + uint32_t RESERVED10[16]; + stc_gpio_podr_bit_t PODRF_b; + stc_gpio_poer_bit_t POERF_b; + stc_gpio_posr_bit_t POSRF_b; + stc_gpio_porr_bit_t PORRF_b; + stc_gpio_potr_bit_t POTRF_b; + uint32_t RESERVED11[16]; + stc_gpio_pidr_bit_t PIDRG_b; + uint32_t RESERVED12[16]; + stc_gpio_podr_bit_t PODRG_b; + stc_gpio_poer_bit_t POERG_b; + stc_gpio_posr_bit_t POSRG_b; + stc_gpio_porr_bit_t PORRG_b; + stc_gpio_potr_bit_t POTRG_b; + uint32_t RESERVED13[16]; + stc_gpio_pidr_bit_t PIDRH_b; + uint32_t RESERVED14[16]; + stc_gpio_podr_bit_t PODRH_b; + stc_gpio_poer_bit_t POERH_b; + stc_gpio_posr_bit_t POSRH_b; + stc_gpio_porr_bit_t PORRH_b; + stc_gpio_potr_bit_t POTRH_b; + uint32_t RESERVED15[16]; + stc_gpio_pidri_bit_t PIDRI_b; + uint32_t RESERVED16[16]; + stc_gpio_podri_bit_t PODRI_b; + stc_gpio_poeri_bit_t POERI_b; + stc_gpio_posri_bit_t POSRI_b; + stc_gpio_porri_bit_t PORRI_b; + stc_gpio_potri_bit_t POTRI_b; + uint32_t RESERVED17[6960]; + stc_gpio_pspcr_bit_t PSPCR_b; + uint32_t RESERVED18[32]; + stc_gpio_pinaer_bit_t PINAER_b; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED19[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + stc_gpio_pcr_bit_t PCRD3_b; + stc_gpio_pfsr_bit_t PFSRD3_b; + stc_gpio_pcr_bit_t PCRD4_b; + stc_gpio_pfsr_bit_t PFSRD4_b; + stc_gpio_pcr_bit_t PCRD5_b; + stc_gpio_pfsr_bit_t PFSRD5_b; + stc_gpio_pcr_bit_t PCRD6_b; + stc_gpio_pfsr_bit_t PFSRD6_b; + stc_gpio_pcr_bit_t PCRD7_b; + stc_gpio_pfsr_bit_t PFSRD7_b; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + stc_gpio_pcr_bit_t PCRD12_b; + stc_gpio_pfsr_bit_t PFSRD12_b; + stc_gpio_pcr_bit_t PCRD13_b; + stc_gpio_pfsr_bit_t PFSRD13_b; + stc_gpio_pcr_bit_t PCRD14_b; + stc_gpio_pfsr_bit_t PFSRD14_b; + stc_gpio_pcr_bit_t PCRD15_b; + stc_gpio_pfsr_bit_t PFSRD15_b; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + stc_gpio_pcr_bit_t PCRE5_b; + stc_gpio_pfsr_bit_t PFSRE5_b; + stc_gpio_pcr_bit_t PCRE6_b; + stc_gpio_pfsr_bit_t PFSRE6_b; + stc_gpio_pcr_bit_t PCRE7_b; + stc_gpio_pfsr_bit_t PFSRE7_b; + stc_gpio_pcr_bit_t PCRE8_b; + stc_gpio_pfsr_bit_t PFSRE8_b; + stc_gpio_pcr_bit_t PCRE9_b; + stc_gpio_pfsr_bit_t PFSRE9_b; + stc_gpio_pcr_bit_t PCRE10_b; + stc_gpio_pfsr_bit_t PFSRE10_b; + stc_gpio_pcr_bit_t PCRE11_b; + stc_gpio_pfsr_bit_t PFSRE11_b; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRF0_b; + stc_gpio_pfsr_bit_t PFSRF0_b; + stc_gpio_pcr_bit_t PCRF1_b; + stc_gpio_pfsr_bit_t PFSRF1_b; + stc_gpio_pcr_bit_t PCRF2_b; + stc_gpio_pfsr_bit_t PFSRF2_b; + stc_gpio_pcr_bit_t PCRF3_b; + stc_gpio_pfsr_bit_t PFSRF3_b; + stc_gpio_pcr_bit_t PCRF4_b; + stc_gpio_pfsr_bit_t PFSRF4_b; + stc_gpio_pcr_bit_t PCRF5_b; + stc_gpio_pfsr_bit_t PFSRF5_b; + stc_gpio_pcr_bit_t PCRF6_b; + stc_gpio_pfsr_bit_t PFSRF6_b; + stc_gpio_pcr_bit_t PCRF7_b; + stc_gpio_pfsr_bit_t PFSRF7_b; + stc_gpio_pcr_bit_t PCRF8_b; + stc_gpio_pfsr_bit_t PFSRF8_b; + stc_gpio_pcr_bit_t PCRF9_b; + stc_gpio_pfsr_bit_t PFSRF9_b; + stc_gpio_pcr_bit_t PCRF10_b; + stc_gpio_pfsr_bit_t PFSRF10_b; + stc_gpio_pcr_bit_t PCRF11_b; + stc_gpio_pfsr_bit_t PFSRF11_b; + stc_gpio_pcr_bit_t PCRF12_b; + stc_gpio_pfsr_bit_t PFSRF12_b; + stc_gpio_pcr_bit_t PCRF13_b; + stc_gpio_pfsr_bit_t PFSRF13_b; + stc_gpio_pcr_bit_t PCRF14_b; + stc_gpio_pfsr_bit_t PFSRF14_b; + stc_gpio_pcr_bit_t PCRF15_b; + stc_gpio_pfsr_bit_t PFSRF15_b; + stc_gpio_pcr_bit_t PCRG0_b; + stc_gpio_pfsr_bit_t PFSRG0_b; + stc_gpio_pcr_bit_t PCRG1_b; + stc_gpio_pfsr_bit_t PFSRG1_b; + stc_gpio_pcr_bit_t PCRG2_b; + stc_gpio_pfsr_bit_t PFSRG2_b; + stc_gpio_pcr_bit_t PCRG3_b; + stc_gpio_pfsr_bit_t PFSRG3_b; + stc_gpio_pcr_bit_t PCRG4_b; + stc_gpio_pfsr_bit_t PFSRG4_b; + stc_gpio_pcr_bit_t PCRG5_b; + stc_gpio_pfsr_bit_t PFSRG5_b; + stc_gpio_pcr_bit_t PCRG6_b; + stc_gpio_pfsr_bit_t PFSRG6_b; + stc_gpio_pcr_bit_t PCRG7_b; + stc_gpio_pfsr_bit_t PFSRG7_b; + stc_gpio_pcr_bit_t PCRG8_b; + stc_gpio_pfsr_bit_t PFSRG8_b; + stc_gpio_pcr_bit_t PCRG9_b; + stc_gpio_pfsr_bit_t PFSRG9_b; + stc_gpio_pcr_bit_t PCRG10_b; + stc_gpio_pfsr_bit_t PFSRG10_b; + stc_gpio_pcr_bit_t PCRG11_b; + stc_gpio_pfsr_bit_t PFSRG11_b; + stc_gpio_pcr_bit_t PCRG12_b; + stc_gpio_pfsr_bit_t PFSRG12_b; + stc_gpio_pcr_bit_t PCRG13_b; + stc_gpio_pfsr_bit_t PFSRG13_b; + stc_gpio_pcr_bit_t PCRG14_b; + stc_gpio_pfsr_bit_t PFSRG14_b; + stc_gpio_pcr_bit_t PCRG15_b; + stc_gpio_pfsr_bit_t PFSRG15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; + stc_gpio_pcr_bit_t PCRH3_b; + stc_gpio_pfsr_bit_t PFSRH3_b; + stc_gpio_pcr_bit_t PCRH4_b; + stc_gpio_pfsr_bit_t PFSRH4_b; + stc_gpio_pcr_bit_t PCRH5_b; + stc_gpio_pfsr_bit_t PFSRH5_b; + stc_gpio_pcr_bit_t PCRH6_b; + stc_gpio_pfsr_bit_t PFSRH6_b; + stc_gpio_pcr_bit_t PCRH7_b; + stc_gpio_pfsr_bit_t PFSRH7_b; + stc_gpio_pcr_bit_t PCRH8_b; + stc_gpio_pfsr_bit_t PFSRH8_b; + stc_gpio_pcr_bit_t PCRH9_b; + stc_gpio_pfsr_bit_t PFSRH9_b; + stc_gpio_pcr_bit_t PCRH10_b; + stc_gpio_pfsr_bit_t PFSRH10_b; + stc_gpio_pcr_bit_t PCRH11_b; + stc_gpio_pfsr_bit_t PFSRH11_b; + stc_gpio_pcr_bit_t PCRH12_b; + stc_gpio_pfsr_bit_t PFSRH12_b; + stc_gpio_pcr_bit_t PCRH13_b; + stc_gpio_pfsr_bit_t PFSRH13_b; + stc_gpio_pcr_bit_t PCRH14_b; + stc_gpio_pfsr_bit_t PFSRH14_b; + stc_gpio_pcr_bit_t PCRH15_b; + stc_gpio_pfsr_bit_t PFSRH15_b; + stc_gpio_pcr_bit_t PCRI0_b; + stc_gpio_pfsr_bit_t PFSRI0_b; + stc_gpio_pcr_bit_t PCRI1_b; + stc_gpio_pfsr_bit_t PFSRI1_b; + stc_gpio_pcr_bit_t PCRI2_b; + stc_gpio_pfsr_bit_t PFSRI2_b; + stc_gpio_pcr_bit_t PCRI3_b; + stc_gpio_pfsr_bit_t PFSRI3_b; + stc_gpio_pcr_bit_t PCRI4_b; + stc_gpio_pfsr_bit_t PFSRI4_b; + stc_gpio_pcr_bit_t PCRI5_b; + stc_gpio_pfsr_bit_t PFSRI5_b; + stc_gpio_pcr_bit_t PCRI6_b; + stc_gpio_pfsr_bit_t PFSRI6_b; + stc_gpio_pcr_bit_t PCRI7_b; + stc_gpio_pfsr_bit_t PFSRI7_b; + stc_gpio_pcr_bit_t PCRI8_b; + stc_gpio_pfsr_bit_t PFSRI8_b; + stc_gpio_pcr_bit_t PCRI9_b; + stc_gpio_pfsr_bit_t PFSRI9_b; + stc_gpio_pcr_bit_t PCRI10_b; + stc_gpio_pfsr_bit_t PFSRI10_b; + stc_gpio_pcr_bit_t PCRI11_b; + stc_gpio_pfsr_bit_t PFSRI11_b; + stc_gpio_pcr_bit_t PCRI12_b; + stc_gpio_pfsr_bit_t PFSRI12_b; + stc_gpio_pcr_bit_t PCRI13_b; + stc_gpio_pfsr_bit_t PFSRI13_b; +} bCM_GPIO_TypeDef; + +typedef struct { + stc_hash_cr_bit_t CR_b; +} bCM_HASH_TypeDef; + +typedef struct { + stc_hrpwm_cr_bit_t CR1_b; + stc_hrpwm_cr_bit_t CR2_b; + stc_hrpwm_cr_bit_t CR3_b; + stc_hrpwm_cr_bit_t CR4_b; + stc_hrpwm_cr_bit_t CR5_b; + stc_hrpwm_cr_bit_t CR6_b; + stc_hrpwm_cr_bit_t CR7_b; + stc_hrpwm_cr_bit_t CR8_b; + stc_hrpwm_cr_bit_t CR9_b; + stc_hrpwm_cr_bit_t CR10_b; + stc_hrpwm_cr_bit_t CR11_b; + stc_hrpwm_cr_bit_t CR12_b; + stc_hrpwm_cr_bit_t CR13_b; + stc_hrpwm_cr_bit_t CR14_b; + stc_hrpwm_cr_bit_t CR15_b; + stc_hrpwm_cr_bit_t CR16_b; + uint32_t RESERVED0[128]; + stc_hrpwm_calcr_bit_t CALCR0_b; + stc_hrpwm_calcr_bit_t CALCR1_b; +} bCM_HRPWM_TypeDef; + +typedef struct { + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + stc_i2c_cr4_bit_t CR4_b; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED0[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + uint32_t RESERVED1[96]; + stc_i2c_fltr_bit_t FLTR_b; +} bCM_I2C_TypeDef; + +typedef struct { + stc_i2s_ctrl_bit_t CTRL_b; + stc_i2s_sr_bit_t SR_b; + stc_i2s_er_bit_t ER_b; + stc_i2s_cfgr_bit_t CFGR_b; +} bCM_I2S_TypeDef; + +typedef struct { + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bCM_ICG_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_intc_nmienr_bit_t NMIENR_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmicfr_bit_t NMICFR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wupen_bit_t WUPEN_b; + stc_intc_eirqfr_bit_t EIRQFR_b; + stc_intc_eirqcfr_bit_t EIRQCFR_b; + uint32_t RESERVED1[4096]; + stc_intc_vssel_bit_t VSSEL128_b; + stc_intc_vssel_bit_t VSSEL129_b; + stc_intc_vssel_bit_t VSSEL130_b; + stc_intc_vssel_bit_t VSSEL131_b; + stc_intc_vssel_bit_t VSSEL132_b; + stc_intc_vssel_bit_t VSSEL133_b; + stc_intc_vssel_bit_t VSSEL134_b; + stc_intc_vssel_bit_t VSSEL135_b; + stc_intc_vssel_bit_t VSSEL136_b; + stc_intc_vssel_bit_t VSSEL137_b; + stc_intc_vssel_bit_t VSSEL138_b; + stc_intc_vssel_bit_t VSSEL139_b; + stc_intc_vssel_bit_t VSSEL140_b; + stc_intc_vssel_bit_t VSSEL141_b; + stc_intc_vssel_bit_t VSSEL142_b; + stc_intc_vssel_bit_t VSSEL143_b; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bCM_INTC_TypeDef; + +typedef struct { + stc_keyscan_scr_bit_t SCR_b; + stc_keyscan_ser_bit_t SER_b; +} bCM_KEYSCAN_TypeDef; + +typedef struct { + stc_mau_csr_bit_t CSR_b; +} bCM_MAU_TypeDef; + +typedef struct { + stc_mpu_rgd_bit_t RGD0_b; + stc_mpu_rgd_bit_t RGD1_b; + stc_mpu_rgd_bit_t RGD2_b; + stc_mpu_rgd_bit_t RGD3_b; + stc_mpu_rgd_bit_t RGD4_b; + stc_mpu_rgd_bit_t RGD5_b; + stc_mpu_rgd_bit_t RGD6_b; + stc_mpu_rgd_bit_t RGD7_b; + stc_mpu_rgd_bit_t RGD8_b; + stc_mpu_rgd_bit_t RGD9_b; + stc_mpu_rgd_bit_t RGD10_b; + stc_mpu_rgd_bit_t RGD11_b; + stc_mpu_rgd_bit_t RGD12_b; + stc_mpu_rgd_bit_t RGD13_b; + stc_mpu_rgd_bit_t RGD14_b; + stc_mpu_rgd_bit_t RGD15_b; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + stc_mpu_ippr_bit_t IPPR_b; + stc_mpu_s1rge_bit_t S1RGE_b; + stc_mpu_s1rgwp_bit_t S1RGWP_b; + stc_mpu_s1rgrp_bit_t S1RGRP_b; + stc_mpu_s1cr_bit_t S1CR_b; + stc_mpu_s2rge_bit_t S2RGE_b; + stc_mpu_s2rgwp_bit_t S2RGWP_b; + stc_mpu_s2rgrp_bit_t S2RGRP_b; + stc_mpu_s2cr_bit_t S2CR_b; + stc_mpu_frge_bit_t FRGE_b; + stc_mpu_frgwp_bit_t FRGWP_b; + stc_mpu_frgrp_bit_t FRGRP_b; + stc_mpu_fcr_bit_t FCR_b; + stc_mpu_hrge_bit_t HRGE_b; + stc_mpu_hrgwp_bit_t HRGWP_b; + stc_mpu_hrgrp_bit_t HRGRP_b; + stc_mpu_hcr_bit_t HCR_b; + stc_mpu_erge_bit_t ERGE_b; + stc_mpu_ergwp_bit_t ERGWP_b; + stc_mpu_ergrp_bit_t ERGRP_b; + stc_mpu_ecr_bit_t ECR_b; +} bCM_MPU_TypeDef; + +typedef struct { + uint32_t RESERVED0[1904640]; + stc_ots_ctl_bit_t CTL_b; +} bCM_OTS_TypeDef; + +typedef struct { + stc_peric_usb_syctlreg_bit_t USB_SYCTLREG_b; + stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b; + stc_peric_nfc_stcr_bit_t NFC_STCR_b; + union { + stc_peric_nfc_enar_bit_t NFC_ENAR_b; + stc_peric_smc_enar_bit_t SMC_ENAR_b; + stc_peric_dmc_enar_bit_t DMC_ENAR_b; + }; + uint32_t RESERVED0[96]; + stc_peric_usart1_nfc_bit_t USART1_NFC_b; + uint32_t RESERVED1[64]; + stc_peric_nfc_stsr_bit_t NFC_STSR_b; +} bCM_PERIC_TypeDef; + +typedef struct { + stc_pwc_fcg0_bit_t FCG0_b; + stc_pwc_fcg1_bit_t FCG1_b; + stc_pwc_fcg2_bit_t FCG2_b; + stc_pwc_fcg3_bit_t FCG3_b; + stc_pwc_fcg0pc_bit_t FCG0PC_b; + uint32_t RESERVED0[139616]; + stc_pwc_vbatcr_bit_t VBATCR_b; + uint32_t RESERVED1[184]; + stc_pwc_wktc2_bit_t WKTC2_b; + uint32_t RESERVED2[15672]; + stc_pwc_pwrc0_bit_t PWRC0_b; + uint32_t RESERVED3[24]; + stc_pwc_pwrc1_bit_t PWRC1_b; + uint32_t RESERVED4[24]; + stc_pwc_pwrc2_bit_t PWRC2_b; + uint32_t RESERVED5[56]; + stc_pwc_pwrc4_bit_t PWRC4_b; + uint32_t RESERVED6[24]; + stc_pwc_pvdcr0_bit_t PVDCR0_b; + uint32_t RESERVED7[24]; + stc_pwc_pvdcr1_bit_t PVDCR1_b; + uint32_t RESERVED8[24]; + stc_pwc_pvdfcr_bit_t PVDFCR_b; + uint32_t RESERVED9[88]; + stc_pwc_pdwke0_bit_t PDWKE0_b; + uint32_t RESERVED10[24]; + stc_pwc_pdwke1_bit_t PDWKE1_b; + uint32_t RESERVED11[24]; + stc_pwc_pdwke2_bit_t PDWKE2_b; + uint32_t RESERVED12[24]; + stc_pwc_pdwkes_bit_t PDWKES_b; + uint32_t RESERVED13[24]; + stc_pwc_pdwkf0_bit_t PDWKF0_b; + uint32_t RESERVED14[24]; + stc_pwc_pdwkf1_bit_t PDWKF1_b; + uint32_t RESERVED15[1304]; + stc_pwc_rampc0_bit_t RAMPC0_b; + uint32_t RESERVED16[32]; + stc_pwc_pramlpc_bit_t PRAMLPC_b; + uint32_t RESERVED17[32]; + stc_pwc_pvdicr_bit_t PVDICR_b; + uint32_t RESERVED18[24]; + stc_pwc_pvddsr_bit_t PVDDSR_b; + uint32_t RESERVED19[235704]; + stc_pwc_stpmcr_bit_t STPMCR_b; + uint32_t RESERVED20[8064]; + stc_pwc_fprc_bit_t FPRC_b; +} bCM_PWC_TypeDef; + +typedef struct { + uint32_t RESERVED0[1984]; + stc_rmu_prstcr0_bit_t PRSTCR0_b; + uint32_t RESERVED1[24]; + stc_rmu_rstf0_bit_t RSTF0_b; +} bCM_RMU_TypeDef; + +typedef struct { + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[88]; + stc_rtc_hour_bit_t HOUR_b; + uint32_t RESERVED4[184]; + stc_rtc_almhour_bit_t ALMHOUR_b; + uint32_t RESERVED5[24]; + stc_rtc_almweek_bit_t ALMWEEK_b; + uint32_t RESERVED6[24]; + stc_rtc_errcrh_bit_t ERRCRH_b; + uint32_t RESERVED7[56]; + stc_rtc_tpcr0_bit_t TPCR0_b; + uint32_t RESERVED8[24]; + stc_rtc_tpcr1_bit_t TPCR1_b; + uint32_t RESERVED9[24]; + stc_rtc_tpsr_bit_t TPSR_b; + uint32_t RESERVED10[88]; + stc_rtc_hourtp_bit_t HOURTP_b; +} bCM_RTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_sdioc_transmode_bit_t TRANSMODE_b; + stc_sdioc_cmd_bit_t CMD_b; + uint32_t RESERVED1[160]; + stc_sdioc_pstat_bit_t PSTAT_b; + stc_sdioc_hostcon_bit_t HOSTCON_b; + stc_sdioc_pwrcon_bit_t PWRCON_b; + stc_sdioc_blkgpcon_bit_t BLKGPCON_b; + uint32_t RESERVED2[8]; + stc_sdioc_clkcon_bit_t CLKCON_b; + uint32_t RESERVED3[8]; + stc_sdioc_sftrst_bit_t SFTRST_b; + stc_sdioc_norintst_bit_t NORINTST_b; + stc_sdioc_errintst_bit_t ERRINTST_b; + stc_sdioc_norintsten_bit_t NORINTSTEN_b; + stc_sdioc_errintsten_bit_t ERRINTSTEN_b; + stc_sdioc_norintsgen_bit_t NORINTSGEN_b; + stc_sdioc_errintsgen_bit_t ERRINTSGEN_b; + stc_sdioc_atcerrst_bit_t ATCERRST_b; + uint32_t RESERVED4[144]; + stc_sdioc_fea_bit_t FEA_b; + stc_sdioc_fee_bit_t FEE_b; +} bCM_SDIOC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_spi_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bCM_SPI_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; +} bCM_SRAMC_TypeDef; + +typedef struct { + stc_swdt_cr_bit_t CR_b; + stc_swdt_sr_bit_t SR_b; +} bCM_SWDT_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bCM_TMR0_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr2_bconr_bit_t BCONR_b; + stc_tmr2_iconr_bit_t ICONR_b; + stc_tmr2_pconr_bit_t PCONR_b; + stc_tmr2_hconr_bit_t HCONR_b; + stc_tmr2_stflr_bit_t STFLR_b; +} bCM_TMR2_TypeDef; + +typedef struct { + uint32_t RESERVED0[192]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocmrh_bit_t OCMRHUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRLUL_b; + stc_tmr4_ocmrh_bit_t OCMRHVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRLVL_b; + stc_tmr4_ocmrh_bit_t OCMRHWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRLWL_b; + uint32_t RESERVED4[96]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED5[624]; + stc_tmr4_pocr_bit_t POCRU_b; + uint32_t RESERVED6[16]; + stc_tmr4_pocr_bit_t POCRV_b; + uint32_t RESERVED7[16]; + stc_tmr4_pocr_bit_t POCRW_b; + uint32_t RESERVED8[16]; + stc_tmr4_rcsr_bit_t RCSR_b; + uint32_t RESERVED9[272]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + stc_tmr4_pscr_bit_t PSCR_b; + stc_tmr4_scer_bit_t SCER_b; +} bCM_TMR4_TypeDef; + +typedef struct { + uint32_t RESERVED0[2560]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_pcnar_bit_t PCNAR_b; + stc_tmr6_pcnbr_bit_t PCNBR_b; + stc_tmr6_fcngr_bit_t FCNGR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + uint32_t RESERVED2[192]; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hupdr_bit_t HUPDR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; +} bCM_TMR6_TypeDef; + +typedef struct { + uint32_t RESERVED0[8032]; + stc_tmr6cr_fcntr_bit_t FCNTR_b; + stc_tmr6cr_sstar_bit_t SSTAR_b; + stc_tmr6cr_sstpr_bit_t SSTPR_b; + stc_tmr6cr_sclrr_bit_t SCLRR_b; + stc_tmr6cr_supdr_bit_t SUPDR_b; +} bCM_TMR6CR_TypeDef; + +typedef struct { + uint32_t RESERVED0[1024]; + stc_tmra_bcstr_bit_t BCSTR_b; + uint32_t RESERVED1[16]; + stc_tmra_hconr_bit_t HCONR_b; + uint32_t RESERVED2[16]; + stc_tmra_hcupr_bit_t HCUPR_b; + uint32_t RESERVED3[16]; + stc_tmra_hcdor_bit_t HCDOR_b; + uint32_t RESERVED4[16]; + stc_tmra_iconr_bit_t ICONR_b; + uint32_t RESERVED5[16]; + stc_tmra_econr_bit_t ECONR_b; + uint32_t RESERVED6[16]; + stc_tmra_fconr_bit_t FCONR_b; + uint32_t RESERVED7[16]; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED8[272]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED9[48]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED10[432]; + stc_tmra_cconr_bit_t CCONR1_b; + uint32_t RESERVED11[16]; + stc_tmra_cconr_bit_t CCONR2_b; + uint32_t RESERVED12[16]; + stc_tmra_cconr_bit_t CCONR3_b; + uint32_t RESERVED13[16]; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED14[400]; + stc_tmra_pconr_bit_t PCONR1_b; + uint32_t RESERVED15[16]; + stc_tmra_pconr_bit_t PCONR2_b; + uint32_t RESERVED16[16]; + stc_tmra_pconr_bit_t PCONR3_b; + uint32_t RESERVED17[16]; + stc_tmra_pconr_bit_t PCONR4_b; +} bCM_TMRA_TypeDef; + +typedef struct { + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bCM_TRNG_TypeDef; + +typedef struct { + stc_usart_sr_bit_t SR_b; + stc_usart_dr_bit_t DR_b; + uint32_t RESERVED0[32]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; + stc_usart_pr_bit_t PR_b; +} bCM_USART_TypeDef; + +typedef struct { + stc_usbfs_gvbuscfg_bit_t GVBUSCFG_b; + uint32_t RESERVED0[32]; + stc_usbfs_gahbcfg_bit_t GAHBCFG_b; + stc_usbfs_gusbcfg_bit_t GUSBCFG_b; + stc_usbfs_grstctl_bit_t GRSTCTL_b; + stc_usbfs_gintsts_bit_t GINTSTS_b; + stc_usbfs_gintmsk_bit_t GINTMSK_b; + uint32_t RESERVED1[448]; + stc_usbfs_glpmcfg_bit_t GLPMCFG_b; + uint32_t RESERVED2[7488]; + stc_usbfs_hcfg_bit_t HCFG_b; + uint32_t RESERVED3[480]; + stc_usbfs_hprt_bit_t HPRT_b; + uint32_t RESERVED4[1504]; + stc_usbfs_hcchar_bit_t HCCHAR0_b; + uint32_t RESERVED5[32]; + stc_usbfs_hcint_bit_t HCINT0_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK0_b; + uint32_t RESERVED6[128]; + stc_usbfs_hcchar_bit_t HCCHAR1_b; + uint32_t RESERVED7[32]; + stc_usbfs_hcint_bit_t HCINT1_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK1_b; + uint32_t RESERVED8[128]; + stc_usbfs_hcchar_bit_t HCCHAR2_b; + uint32_t RESERVED9[32]; + stc_usbfs_hcint_bit_t HCINT2_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK2_b; + uint32_t RESERVED10[128]; + stc_usbfs_hcchar_bit_t HCCHAR3_b; + uint32_t RESERVED11[32]; + stc_usbfs_hcint_bit_t HCINT3_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK3_b; + uint32_t RESERVED12[128]; + stc_usbfs_hcchar_bit_t HCCHAR4_b; + uint32_t RESERVED13[32]; + stc_usbfs_hcint_bit_t HCINT4_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK4_b; + uint32_t RESERVED14[128]; + stc_usbfs_hcchar_bit_t HCCHAR5_b; + uint32_t RESERVED15[32]; + stc_usbfs_hcint_bit_t HCINT5_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK5_b; + uint32_t RESERVED16[128]; + stc_usbfs_hcchar_bit_t HCCHAR6_b; + uint32_t RESERVED17[32]; + stc_usbfs_hcint_bit_t HCINT6_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK6_b; + uint32_t RESERVED18[128]; + stc_usbfs_hcchar_bit_t HCCHAR7_b; + uint32_t RESERVED19[32]; + stc_usbfs_hcint_bit_t HCINT7_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK7_b; + uint32_t RESERVED20[128]; + stc_usbfs_hcchar_bit_t HCCHAR8_b; + uint32_t RESERVED21[32]; + stc_usbfs_hcint_bit_t HCINT8_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK8_b; + uint32_t RESERVED22[128]; + stc_usbfs_hcchar_bit_t HCCHAR9_b; + uint32_t RESERVED23[32]; + stc_usbfs_hcint_bit_t HCINT9_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK9_b; + uint32_t RESERVED24[128]; + stc_usbfs_hcchar_bit_t HCCHAR10_b; + uint32_t RESERVED25[32]; + stc_usbfs_hcint_bit_t HCINT10_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK10_b; + uint32_t RESERVED26[128]; + stc_usbfs_hcchar_bit_t HCCHAR11_b; + uint32_t RESERVED27[32]; + stc_usbfs_hcint_bit_t HCINT11_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK11_b; + uint32_t RESERVED28[128]; + stc_usbfs_hcchar_bit_t HCCHAR12_b; + uint32_t RESERVED29[32]; + stc_usbfs_hcint_bit_t HCINT12_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK12_b; + uint32_t RESERVED30[128]; + stc_usbfs_hcchar_bit_t HCCHAR13_b; + uint32_t RESERVED31[32]; + stc_usbfs_hcint_bit_t HCINT13_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK13_b; + uint32_t RESERVED32[128]; + stc_usbfs_hcchar_bit_t HCCHAR14_b; + uint32_t RESERVED33[32]; + stc_usbfs_hcint_bit_t HCINT14_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK14_b; + uint32_t RESERVED34[128]; + stc_usbfs_hcchar_bit_t HCCHAR15_b; + uint32_t RESERVED35[32]; + stc_usbfs_hcint_bit_t HCINT15_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK15_b; + uint32_t RESERVED36[2176]; + stc_usbfs_dcfg_bit_t DCFG_b; + stc_usbfs_dctl_bit_t DCTL_b; + stc_usbfs_dsts_bit_t DSTS_b; + uint32_t RESERVED37[32]; + stc_usbfs_diepmsk_bit_t DIEPMSK_b; + stc_usbfs_doepmsk_bit_t DOEPMSK_b; + uint32_t RESERVED38[1856]; + stc_usbfs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED39[32]; + stc_usbfs_diepint_bit_t DIEPINT0_b; + uint32_t RESERVED40[160]; + stc_usbfs_diepctl_bit_t DIEPCTL1_b; + uint32_t RESERVED41[32]; + stc_usbfs_diepint_bit_t DIEPINT1_b; + uint32_t RESERVED42[160]; + stc_usbfs_diepctl_bit_t DIEPCTL2_b; + uint32_t RESERVED43[32]; + stc_usbfs_diepint_bit_t DIEPINT2_b; + uint32_t RESERVED44[160]; + stc_usbfs_diepctl_bit_t DIEPCTL3_b; + uint32_t RESERVED45[32]; + stc_usbfs_diepint_bit_t DIEPINT3_b; + uint32_t RESERVED46[160]; + stc_usbfs_diepctl_bit_t DIEPCTL4_b; + uint32_t RESERVED47[32]; + stc_usbfs_diepint_bit_t DIEPINT4_b; + uint32_t RESERVED48[160]; + stc_usbfs_diepctl_bit_t DIEPCTL5_b; + uint32_t RESERVED49[32]; + stc_usbfs_diepint_bit_t DIEPINT5_b; + uint32_t RESERVED50[160]; + stc_usbfs_diepctl_bit_t DIEPCTL6_b; + uint32_t RESERVED51[32]; + stc_usbfs_diepint_bit_t DIEPINT6_b; + uint32_t RESERVED52[160]; + stc_usbfs_diepctl_bit_t DIEPCTL7_b; + uint32_t RESERVED53[32]; + stc_usbfs_diepint_bit_t DIEPINT7_b; + uint32_t RESERVED54[160]; + stc_usbfs_diepctl_bit_t DIEPCTL8_b; + uint32_t RESERVED55[32]; + stc_usbfs_diepint_bit_t DIEPINT8_b; + uint32_t RESERVED56[160]; + stc_usbfs_diepctl_bit_t DIEPCTL9_b; + uint32_t RESERVED57[32]; + stc_usbfs_diepint_bit_t DIEPINT9_b; + uint32_t RESERVED58[160]; + stc_usbfs_diepctl_bit_t DIEPCTL10_b; + uint32_t RESERVED59[32]; + stc_usbfs_diepint_bit_t DIEPINT10_b; + uint32_t RESERVED60[160]; + stc_usbfs_diepctl_bit_t DIEPCTL11_b; + uint32_t RESERVED61[32]; + stc_usbfs_diepint_bit_t DIEPINT11_b; + uint32_t RESERVED62[160]; + stc_usbfs_diepctl_bit_t DIEPCTL12_b; + uint32_t RESERVED63[32]; + stc_usbfs_diepint_bit_t DIEPINT12_b; + uint32_t RESERVED64[160]; + stc_usbfs_diepctl_bit_t DIEPCTL13_b; + uint32_t RESERVED65[32]; + stc_usbfs_diepint_bit_t DIEPINT13_b; + uint32_t RESERVED66[160]; + stc_usbfs_diepctl_bit_t DIEPCTL14_b; + uint32_t RESERVED67[32]; + stc_usbfs_diepint_bit_t DIEPINT14_b; + uint32_t RESERVED68[160]; + stc_usbfs_diepctl_bit_t DIEPCTL15_b; + uint32_t RESERVED69[32]; + stc_usbfs_diepint_bit_t DIEPINT15_b; + uint32_t RESERVED70[160]; + stc_usbfs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED71[32]; + stc_usbfs_doepint_bit_t DOEPINT0_b; + uint32_t RESERVED72[32]; + stc_usbfs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED73[96]; + stc_usbfs_doepctl_bit_t DOEPCTL1_b; + uint32_t RESERVED74[32]; + stc_usbfs_doepint_bit_t DOEPINT1_b; + uint32_t RESERVED75[160]; + stc_usbfs_doepctl_bit_t DOEPCTL2_b; + uint32_t RESERVED76[32]; + stc_usbfs_doepint_bit_t DOEPINT2_b; + uint32_t RESERVED77[160]; + stc_usbfs_doepctl_bit_t DOEPCTL3_b; + uint32_t RESERVED78[32]; + stc_usbfs_doepint_bit_t DOEPINT3_b; + uint32_t RESERVED79[160]; + stc_usbfs_doepctl_bit_t DOEPCTL4_b; + uint32_t RESERVED80[32]; + stc_usbfs_doepint_bit_t DOEPINT4_b; + uint32_t RESERVED81[160]; + stc_usbfs_doepctl_bit_t DOEPCTL5_b; + uint32_t RESERVED82[32]; + stc_usbfs_doepint_bit_t DOEPINT5_b; + uint32_t RESERVED83[160]; + stc_usbfs_doepctl_bit_t DOEPCTL6_b; + uint32_t RESERVED84[32]; + stc_usbfs_doepint_bit_t DOEPINT6_b; + uint32_t RESERVED85[160]; + stc_usbfs_doepctl_bit_t DOEPCTL7_b; + uint32_t RESERVED86[32]; + stc_usbfs_doepint_bit_t DOEPINT7_b; + uint32_t RESERVED87[160]; + stc_usbfs_doepctl_bit_t DOEPCTL8_b; + uint32_t RESERVED88[32]; + stc_usbfs_doepint_bit_t DOEPINT8_b; + uint32_t RESERVED89[160]; + stc_usbfs_doepctl_bit_t DOEPCTL9_b; + uint32_t RESERVED90[32]; + stc_usbfs_doepint_bit_t DOEPINT9_b; + uint32_t RESERVED91[160]; + stc_usbfs_doepctl_bit_t DOEPCTL10_b; + uint32_t RESERVED92[32]; + stc_usbfs_doepint_bit_t DOEPINT10_b; + uint32_t RESERVED93[160]; + stc_usbfs_doepctl_bit_t DOEPCTL11_b; + uint32_t RESERVED94[32]; + stc_usbfs_doepint_bit_t DOEPINT11_b; + uint32_t RESERVED95[160]; + stc_usbfs_doepctl_bit_t DOEPCTL12_b; + uint32_t RESERVED96[32]; + stc_usbfs_doepint_bit_t DOEPINT12_b; + uint32_t RESERVED97[160]; + stc_usbfs_doepctl_bit_t DOEPCTL13_b; + uint32_t RESERVED98[32]; + stc_usbfs_doepint_bit_t DOEPINT13_b; + uint32_t RESERVED99[160]; + stc_usbfs_doepctl_bit_t DOEPCTL14_b; + uint32_t RESERVED100[32]; + stc_usbfs_doepint_bit_t DOEPINT14_b; + uint32_t RESERVED101[160]; + stc_usbfs_doepctl_bit_t DOEPCTL15_b; + uint32_t RESERVED102[32]; + stc_usbfs_doepint_bit_t DOEPINT15_b; + uint32_t RESERVED103[2208]; + stc_usbfs_gcctl_bit_t GCCTL_b; +} bCM_USBFS_TypeDef; + +typedef struct { + stc_usbhs_gvbuscfg_bit_t GVBUSCFG_b; + uint32_t RESERVED0[32]; + stc_usbhs_gahbcfg_bit_t GAHBCFG_b; + stc_usbhs_gusbcfg_bit_t GUSBCFG_b; + stc_usbhs_grstctl_bit_t GRSTCTL_b; + stc_usbhs_gintsts_bit_t GINTSTS_b; + stc_usbhs_gintmsk_bit_t GINTMSK_b; + uint32_t RESERVED1[448]; + stc_usbhs_glpmcfg_bit_t GLPMCFG_b; + uint32_t RESERVED2[7488]; + stc_usbhs_hcfg_bit_t HCFG_b; + uint32_t RESERVED3[480]; + stc_usbhs_hprt_bit_t HPRT_b; + uint32_t RESERVED4[1504]; + stc_usbhs_hcchar_bit_t HCCHAR0_b; + stc_usbhs_hcsplt_bit_t HCSPLT0_b; + stc_usbhs_hcint_bit_t HCINT0_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK0_b; + stc_usbhs_hctsiz_bit_t HCTSIZ0_b; + uint32_t RESERVED5[96]; + stc_usbhs_hcchar_bit_t HCCHAR1_b; + stc_usbhs_hcsplt_bit_t HCSPLT1_b; + stc_usbhs_hcint_bit_t HCINT1_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK1_b; + stc_usbhs_hctsiz_bit_t HCTSIZ1_b; + uint32_t RESERVED6[96]; + stc_usbhs_hcchar_bit_t HCCHAR2_b; + stc_usbhs_hcsplt_bit_t HCSPLT2_b; + stc_usbhs_hcint_bit_t HCINT2_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK2_b; + stc_usbhs_hctsiz_bit_t HCTSIZ2_b; + uint32_t RESERVED7[96]; + stc_usbhs_hcchar_bit_t HCCHAR3_b; + stc_usbhs_hcsplt_bit_t HCSPLT3_b; + stc_usbhs_hcint_bit_t HCINT3_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK3_b; + stc_usbhs_hctsiz_bit_t HCTSIZ3_b; + uint32_t RESERVED8[96]; + stc_usbhs_hcchar_bit_t HCCHAR4_b; + stc_usbhs_hcsplt_bit_t HCSPLT4_b; + stc_usbhs_hcint_bit_t HCINT4_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK4_b; + stc_usbhs_hctsiz_bit_t HCTSIZ4_b; + uint32_t RESERVED9[96]; + stc_usbhs_hcchar_bit_t HCCHAR5_b; + stc_usbhs_hcsplt_bit_t HCSPLT5_b; + stc_usbhs_hcint_bit_t HCINT5_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK5_b; + stc_usbhs_hctsiz_bit_t HCTSIZ5_b; + uint32_t RESERVED10[96]; + stc_usbhs_hcchar_bit_t HCCHAR6_b; + stc_usbhs_hcsplt_bit_t HCSPLT6_b; + stc_usbhs_hcint_bit_t HCINT6_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK6_b; + stc_usbhs_hctsiz_bit_t HCTSIZ6_b; + uint32_t RESERVED11[96]; + stc_usbhs_hcchar_bit_t HCCHAR7_b; + stc_usbhs_hcsplt_bit_t HCSPLT7_b; + stc_usbhs_hcint_bit_t HCINT7_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK7_b; + stc_usbhs_hctsiz_bit_t HCTSIZ7_b; + uint32_t RESERVED12[96]; + stc_usbhs_hcchar_bit_t HCCHAR8_b; + stc_usbhs_hcsplt_bit_t HCSPLT8_b; + stc_usbhs_hcint_bit_t HCINT8_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK8_b; + stc_usbhs_hctsiz_bit_t HCTSIZ8_b; + uint32_t RESERVED13[96]; + stc_usbhs_hcchar_bit_t HCCHAR9_b; + stc_usbhs_hcsplt_bit_t HCSPLT9_b; + stc_usbhs_hcint_bit_t HCINT9_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK9_b; + stc_usbhs_hctsiz_bit_t HCTSIZ9_b; + uint32_t RESERVED14[96]; + stc_usbhs_hcchar_bit_t HCCHAR10_b; + stc_usbhs_hcsplt_bit_t HCSPLT10_b; + stc_usbhs_hcint_bit_t HCINT10_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK10_b; + stc_usbhs_hctsiz_bit_t HCTSIZ10_b; + uint32_t RESERVED15[96]; + stc_usbhs_hcchar_bit_t HCCHAR11_b; + stc_usbhs_hcsplt_bit_t HCSPLT11_b; + stc_usbhs_hcint_bit_t HCINT11_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK11_b; + stc_usbhs_hctsiz_bit_t HCTSIZ11_b; + uint32_t RESERVED16[96]; + stc_usbhs_hcchar_bit_t HCCHAR12_b; + stc_usbhs_hcsplt_bit_t HCSPLT12_b; + stc_usbhs_hcint_bit_t HCINT12_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK12_b; + stc_usbhs_hctsiz_bit_t HCTSIZ12_b; + uint32_t RESERVED17[96]; + stc_usbhs_hcchar_bit_t HCCHAR13_b; + stc_usbhs_hcsplt_bit_t HCSPLT13_b; + stc_usbhs_hcint_bit_t HCINT13_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK13_b; + stc_usbhs_hctsiz_bit_t HCTSIZ13_b; + uint32_t RESERVED18[96]; + stc_usbhs_hcchar_bit_t HCCHAR14_b; + stc_usbhs_hcsplt_bit_t HCSPLT14_b; + stc_usbhs_hcint_bit_t HCINT14_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK14_b; + stc_usbhs_hctsiz_bit_t HCTSIZ14_b; + uint32_t RESERVED19[96]; + stc_usbhs_hcchar_bit_t HCCHAR15_b; + stc_usbhs_hcsplt_bit_t HCSPLT15_b; + stc_usbhs_hcint_bit_t HCINT15_b; + stc_usbhs_hcintmsk_bit_t HCINTMSK15_b; + stc_usbhs_hctsiz_bit_t HCTSIZ15_b; + uint32_t RESERVED20[2144]; + stc_usbhs_dcfg_bit_t DCFG_b; + stc_usbhs_dctl_bit_t DCTL_b; + stc_usbhs_dsts_bit_t DSTS_b; + uint32_t RESERVED21[32]; + stc_usbhs_diepmsk_bit_t DIEPMSK_b; + stc_usbhs_doepmsk_bit_t DOEPMSK_b; + uint32_t RESERVED22[192]; + stc_usbhs_dthrctl_bit_t DTHRCTL_b; + uint32_t RESERVED23[32]; + stc_usbhs_deachint_bit_t DEACHINT_b; + stc_usbhs_deachintmsk_bit_t DEACHINTMSK_b; + uint32_t RESERVED24[32]; + stc_usbhs_diepeachmsk1_bit_t DIEPEACHMSK1_b; + uint32_t RESERVED25[480]; + stc_usbhs_doepeachmsk1_bit_t DOEPEACHMSK1_b; + uint32_t RESERVED26[960]; + stc_usbhs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED27[32]; + stc_usbhs_diepint_bit_t DIEPINT0_b; + uint32_t RESERVED28[160]; + stc_usbhs_diepctl_bit_t DIEPCTL1_b; + uint32_t RESERVED29[32]; + stc_usbhs_diepint_bit_t DIEPINT1_b; + uint32_t RESERVED30[160]; + stc_usbhs_diepctl_bit_t DIEPCTL2_b; + uint32_t RESERVED31[32]; + stc_usbhs_diepint_bit_t DIEPINT2_b; + uint32_t RESERVED32[160]; + stc_usbhs_diepctl_bit_t DIEPCTL3_b; + uint32_t RESERVED33[32]; + stc_usbhs_diepint_bit_t DIEPINT3_b; + uint32_t RESERVED34[160]; + stc_usbhs_diepctl_bit_t DIEPCTL4_b; + uint32_t RESERVED35[32]; + stc_usbhs_diepint_bit_t DIEPINT4_b; + uint32_t RESERVED36[160]; + stc_usbhs_diepctl_bit_t DIEPCTL5_b; + uint32_t RESERVED37[32]; + stc_usbhs_diepint_bit_t DIEPINT5_b; + uint32_t RESERVED38[160]; + stc_usbhs_diepctl_bit_t DIEPCTL6_b; + uint32_t RESERVED39[32]; + stc_usbhs_diepint_bit_t DIEPINT6_b; + uint32_t RESERVED40[160]; + stc_usbhs_diepctl_bit_t DIEPCTL7_b; + uint32_t RESERVED41[32]; + stc_usbhs_diepint_bit_t DIEPINT7_b; + uint32_t RESERVED42[160]; + stc_usbhs_diepctl_bit_t DIEPCTL8_b; + uint32_t RESERVED43[32]; + stc_usbhs_diepint_bit_t DIEPINT8_b; + uint32_t RESERVED44[160]; + stc_usbhs_diepctl_bit_t DIEPCTL9_b; + uint32_t RESERVED45[32]; + stc_usbhs_diepint_bit_t DIEPINT9_b; + uint32_t RESERVED46[160]; + stc_usbhs_diepctl_bit_t DIEPCTL10_b; + uint32_t RESERVED47[32]; + stc_usbhs_diepint_bit_t DIEPINT10_b; + uint32_t RESERVED48[160]; + stc_usbhs_diepctl_bit_t DIEPCTL11_b; + uint32_t RESERVED49[32]; + stc_usbhs_diepint_bit_t DIEPINT11_b; + uint32_t RESERVED50[160]; + stc_usbhs_diepctl_bit_t DIEPCTL12_b; + uint32_t RESERVED51[32]; + stc_usbhs_diepint_bit_t DIEPINT12_b; + uint32_t RESERVED52[160]; + stc_usbhs_diepctl_bit_t DIEPCTL13_b; + uint32_t RESERVED53[32]; + stc_usbhs_diepint_bit_t DIEPINT13_b; + uint32_t RESERVED54[160]; + stc_usbhs_diepctl_bit_t DIEPCTL14_b; + uint32_t RESERVED55[32]; + stc_usbhs_diepint_bit_t DIEPINT14_b; + uint32_t RESERVED56[160]; + stc_usbhs_diepctl_bit_t DIEPCTL15_b; + uint32_t RESERVED57[32]; + stc_usbhs_diepint_bit_t DIEPINT15_b; + uint32_t RESERVED58[160]; + stc_usbhs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED59[32]; + stc_usbhs_doepint_bit_t DOEPINT0_b; + uint32_t RESERVED60[32]; + stc_usbhs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED61[96]; + stc_usbhs_doepctl_bit_t DOEPCTL1_b; + uint32_t RESERVED62[32]; + stc_usbhs_doepint_bit_t DOEPINT1_b; + uint32_t RESERVED63[160]; + stc_usbhs_doepctl_bit_t DOEPCTL2_b; + uint32_t RESERVED64[32]; + stc_usbhs_doepint_bit_t DOEPINT2_b; + uint32_t RESERVED65[160]; + stc_usbhs_doepctl_bit_t DOEPCTL3_b; + uint32_t RESERVED66[32]; + stc_usbhs_doepint_bit_t DOEPINT3_b; + uint32_t RESERVED67[160]; + stc_usbhs_doepctl_bit_t DOEPCTL4_b; + uint32_t RESERVED68[32]; + stc_usbhs_doepint_bit_t DOEPINT4_b; + uint32_t RESERVED69[160]; + stc_usbhs_doepctl_bit_t DOEPCTL5_b; + uint32_t RESERVED70[32]; + stc_usbhs_doepint_bit_t DOEPINT5_b; + uint32_t RESERVED71[160]; + stc_usbhs_doepctl_bit_t DOEPCTL6_b; + uint32_t RESERVED72[32]; + stc_usbhs_doepint_bit_t DOEPINT6_b; + uint32_t RESERVED73[160]; + stc_usbhs_doepctl_bit_t DOEPCTL7_b; + uint32_t RESERVED74[32]; + stc_usbhs_doepint_bit_t DOEPINT7_b; + uint32_t RESERVED75[160]; + stc_usbhs_doepctl_bit_t DOEPCTL8_b; + uint32_t RESERVED76[32]; + stc_usbhs_doepint_bit_t DOEPINT8_b; + uint32_t RESERVED77[160]; + stc_usbhs_doepctl_bit_t DOEPCTL9_b; + uint32_t RESERVED78[32]; + stc_usbhs_doepint_bit_t DOEPINT9_b; + uint32_t RESERVED79[160]; + stc_usbhs_doepctl_bit_t DOEPCTL10_b; + uint32_t RESERVED80[32]; + stc_usbhs_doepint_bit_t DOEPINT10_b; + uint32_t RESERVED81[160]; + stc_usbhs_doepctl_bit_t DOEPCTL11_b; + uint32_t RESERVED82[32]; + stc_usbhs_doepint_bit_t DOEPINT11_b; + uint32_t RESERVED83[160]; + stc_usbhs_doepctl_bit_t DOEPCTL12_b; + uint32_t RESERVED84[32]; + stc_usbhs_doepint_bit_t DOEPINT12_b; + uint32_t RESERVED85[160]; + stc_usbhs_doepctl_bit_t DOEPCTL13_b; + uint32_t RESERVED86[32]; + stc_usbhs_doepint_bit_t DOEPINT13_b; + uint32_t RESERVED87[160]; + stc_usbhs_doepctl_bit_t DOEPCTL14_b; + uint32_t RESERVED88[32]; + stc_usbhs_doepint_bit_t DOEPINT14_b; + uint32_t RESERVED89[160]; + stc_usbhs_doepctl_bit_t DOEPCTL15_b; + uint32_t RESERVED90[32]; + stc_usbhs_doepint_bit_t DOEPINT15_b; + uint32_t RESERVED91[2208]; + stc_usbhs_gcctl_bit_t GCCTL_b; +} bCM_USBHS_TypeDef; + +typedef struct { + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bCM_WDT_TypeDef; + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ +#define bCM_ADC1 ((bCM_ADC_TypeDef *)0x42800000UL) +#define bCM_ADC2 ((bCM_ADC_TypeDef *)0x42808000UL) +#define bCM_ADC3 ((bCM_ADC_TypeDef *)0x42810000UL) +#define bCM_AES ((bCM_AES_TypeDef *)0x42100000UL) +#define bCM_AOS ((bCM_AOS_TypeDef *)0x42210000UL) +#define bCM_CAN1 ((bCM_CAN_TypeDef *)0x42120000UL) +#define bCM_CAN2 ((bCM_CAN_TypeDef *)0x42F00000UL) +#define bCM_CMP1 ((bCM_CMP_TypeDef *)0x42940000UL) +#define bCM_CMP2 ((bCM_CMP_TypeDef *)0x42940200UL) +#define bCM_CMP3 ((bCM_CMP_TypeDef *)0x42948000UL) +#define bCM_CMP4 ((bCM_CMP_TypeDef *)0x42948200UL) +#define bCM_CMU ((bCM_CMU_TypeDef *)0x42988000UL) +#define bCM_CRC ((bCM_CRC_TypeDef *)0x42118000UL) +#define bCM_CTC ((bCM_CTC_TypeDef *)0x42938000UL) +#define bCM_DAC1 ((bCM_DAC_TypeDef *)0x42820000UL) +#define bCM_DAC2 ((bCM_DAC_TypeDef *)0x42828000UL) +#define bCM_DCU1 ((bCM_DCU_TypeDef *)0x42AC0000UL) +#define bCM_DCU2 ((bCM_DCU_TypeDef *)0x42AC8000UL) +#define bCM_DCU3 ((bCM_DCU_TypeDef *)0x42AD0000UL) +#define bCM_DCU4 ((bCM_DCU_TypeDef *)0x42AD8000UL) +#define bCM_DCU5 ((bCM_DCU_TypeDef *)0x42AE0000UL) +#define bCM_DCU6 ((bCM_DCU_TypeDef *)0x42AE8000UL) +#define bCM_DCU7 ((bCM_DCU_TypeDef *)0x42AF0000UL) +#define bCM_DCU8 ((bCM_DCU_TypeDef *)0x42AF8000UL) +#define bCM_DMA1 ((bCM_DMA_TypeDef *)0x42A60000UL) +#define bCM_DMA2 ((bCM_DMA_TypeDef *)0x42A68000UL) +#define bCM_DVP ((bCM_DVP_TypeDef *)0x42AB0000UL) +#define bCM_EFM ((bCM_EFM_TypeDef *)0x42208000UL) +#define bCM_EMB0 ((bCM_EMB_TypeDef *)0x422F8000UL) +#define bCM_EMB1 ((bCM_EMB_TypeDef *)0x422F8400UL) +#define bCM_EMB2 ((bCM_EMB_TypeDef *)0x422F8800UL) +#define bCM_EMB3 ((bCM_EMB_TypeDef *)0x422F8C00UL) +#define bCM_EMB4 ((bCM_EMB_TypeDef *)0x422F9000UL) +#define bCM_EMB5 ((bCM_EMB_TypeDef *)0x422F9400UL) +#define bCM_EMB6 ((bCM_EMB_TypeDef *)0x422F9800UL) +#define bCM_ETH ((bCM_ETH_TypeDef *)0x42A00000UL) +#define bCM_FCM ((bCM_FCM_TypeDef *)0x42908000UL) +#define bCM_FMAC1 ((bCM_FMAC_TypeDef *)0x42B00000UL) +#define bCM_FMAC2 ((bCM_FMAC_TypeDef *)0x42B08000UL) +#define bCM_FMAC3 ((bCM_FMAC_TypeDef *)0x42B10000UL) +#define bCM_FMAC4 ((bCM_FMAC_TypeDef *)0x42B18000UL) +#define bCM_GPIO ((bCM_GPIO_TypeDef *)0x42A70000UL) +#define bCM_HASH ((bCM_HASH_TypeDef *)0x42108000UL) +#define bCM_HRPWM ((bCM_HRPWM_TypeDef *)0x42780000UL) +#define bCM_I2C1 ((bCM_I2C_TypeDef *)0x429C0000UL) +#define bCM_I2C2 ((bCM_I2C_TypeDef *)0x429C8000UL) +#define bCM_I2C3 ((bCM_I2C_TypeDef *)0x429D0000UL) +#define bCM_I2C4 ((bCM_I2C_TypeDef *)0x429D8000UL) +#define bCM_I2C5 ((bCM_I2C_TypeDef *)0x429E0000UL) +#define bCM_I2C6 ((bCM_I2C_TypeDef *)0x429E8000UL) +#define bCM_I2S1 ((bCM_I2S_TypeDef *)0x423C0000UL) +#define bCM_I2S2 ((bCM_I2S_TypeDef *)0x423C8000UL) +#define bCM_I2S3 ((bCM_I2S_TypeDef *)0x42440000UL) +#define bCM_I2S4 ((bCM_I2S_TypeDef *)0x42448000UL) +#define bCM_INTC ((bCM_INTC_TypeDef *)0x42A20000UL) +#define bCM_KEYSCAN ((bCM_KEYSCAN_TypeDef *)0x42A18000UL) +#define bCM_MAU ((bCM_MAU_TypeDef *)0x42AA0000UL) +#define bCM_MPU ((bCM_MPU_TypeDef *)0x42A00000UL) +#define bCM_OTS ((bCM_OTS_TypeDef *)0x4220C000UL) +#define bCM_PERIC ((bCM_PERIC_TypeDef *)0x42AA8000UL) +#define bCM_PWC ((bCM_PWC_TypeDef *)0x42900000UL) +#define bCM_RMU ((bCM_RMU_TypeDef *)0x42998000UL) +#define bCM_RTC ((bCM_RTC_TypeDef *)0x42980000UL) +#define bCM_SDIOC1 ((bCM_SDIOC_TypeDef *)0x42E00000UL) +#define bCM_SDIOC2 ((bCM_SDIOC_TypeDef *)0x42F08000UL) +#define bCM_SPI1 ((bCM_SPI_TypeDef *)0x42380000UL) +#define bCM_SPI2 ((bCM_SPI_TypeDef *)0x42388000UL) +#define bCM_SPI3 ((bCM_SPI_TypeDef *)0x42390000UL) +#define bCM_SPI4 ((bCM_SPI_TypeDef *)0x42400000UL) +#define bCM_SPI5 ((bCM_SPI_TypeDef *)0x42408000UL) +#define bCM_SPI6 ((bCM_SPI_TypeDef *)0x42410000UL) +#define bCM_SRAMC ((bCM_SRAMC_TypeDef *)0x42A10000UL) +#define bCM_SWDT ((bCM_SWDT_TypeDef *)0x42928000UL) +#define bCM_TMR0_1 ((bCM_TMR0_TypeDef *)0x42480000UL) +#define bCM_TMR0_2 ((bCM_TMR0_TypeDef *)0x42488000UL) +#define bCM_TMR2_1 ((bCM_TMR2_TypeDef *)0x42490000UL) +#define bCM_TMR2_2 ((bCM_TMR2_TypeDef *)0x42498000UL) +#define bCM_TMR2_3 ((bCM_TMR2_TypeDef *)0x424A0000UL) +#define bCM_TMR2_4 ((bCM_TMR2_TypeDef *)0x424A8000UL) +#define bCM_TMR4_1 ((bCM_TMR4_TypeDef *)0x42700000UL) +#define bCM_TMR4_2 ((bCM_TMR4_TypeDef *)0x42708000UL) +#define bCM_TMR4_3 ((bCM_TMR4_TypeDef *)0x42710000UL) +#define bCM_TMR6_1 ((bCM_TMR6_TypeDef *)0x42300000UL) +#define bCM_TMR6_2 ((bCM_TMR6_TypeDef *)0x42308000UL) +#define bCM_TMR6_3 ((bCM_TMR6_TypeDef *)0x42310000UL) +#define bCM_TMR6_4 ((bCM_TMR6_TypeDef *)0x42318000UL) +#define bCM_TMR6_5 ((bCM_TMR6_TypeDef *)0x42320000UL) +#define bCM_TMR6_6 ((bCM_TMR6_TypeDef *)0x42328000UL) +#define bCM_TMR6_7 ((bCM_TMR6_TypeDef *)0x42330000UL) +#define bCM_TMR6_8 ((bCM_TMR6_TypeDef *)0x42338000UL) +#define bCM_TMR6CR ((bCM_TMR6CR_TypeDef *)0x42300000UL) +#define bCM_TMRA_1 ((bCM_TMRA_TypeDef *)0x42740000UL) +#define bCM_TMRA_10 ((bCM_TMRA_TypeDef *)0x424E8000UL) +#define bCM_TMRA_11 ((bCM_TMRA_TypeDef *)0x424F0000UL) +#define bCM_TMRA_12 ((bCM_TMRA_TypeDef *)0x424F8000UL) +#define bCM_TMRA_2 ((bCM_TMRA_TypeDef *)0x42748000UL) +#define bCM_TMRA_3 ((bCM_TMRA_TypeDef *)0x42750000UL) +#define bCM_TMRA_4 ((bCM_TMRA_TypeDef *)0x42758000UL) +#define bCM_TMRA_5 ((bCM_TMRA_TypeDef *)0x424C0000UL) +#define bCM_TMRA_6 ((bCM_TMRA_TypeDef *)0x424C8000UL) +#define bCM_TMRA_7 ((bCM_TMRA_TypeDef *)0x424D0000UL) +#define bCM_TMRA_8 ((bCM_TMRA_TypeDef *)0x424D8000UL) +#define bCM_TMRA_9 ((bCM_TMRA_TypeDef *)0x424E0000UL) +#define bCM_TRNG ((bCM_TRNG_TypeDef *)0x42840000UL) +#define bCM_USART1 ((bCM_USART_TypeDef *)0x42398000UL) +#define bCM_USART10 ((bCM_USART_TypeDef *)0x42438000UL) +#define bCM_USART2 ((bCM_USART_TypeDef *)0x423A0000UL) +#define bCM_USART3 ((bCM_USART_TypeDef *)0x423A8000UL) +#define bCM_USART4 ((bCM_USART_TypeDef *)0x423B0000UL) +#define bCM_USART5 ((bCM_USART_TypeDef *)0x423B8000UL) +#define bCM_USART6 ((bCM_USART_TypeDef *)0x42418000UL) +#define bCM_USART7 ((bCM_USART_TypeDef *)0x42420000UL) +#define bCM_USART8 ((bCM_USART_TypeDef *)0x42428000UL) +#define bCM_USART9 ((bCM_USART_TypeDef *)0x42430000UL) +#define bCM_USBFS ((bCM_USBFS_TypeDef *)0x43000000UL) +#define bCM_USBHS ((bCM_USBHS_TypeDef *)0x43800000UL) +#define bCM_WDT ((bCM_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_H__ */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h new file mode 100644 index 0000000000..6e9c227a9a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h @@ -0,0 +1,66 @@ +/** + ******************************************************************************* + * @file hc32f4xx.h + * @brief This file contains the common part of the HC32 series. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_H__ +#define __HC32F4XX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +/** + * @brief HC32F4xx Device Include + */ +#if defined(HC32F4A0) +#include "hc32f4a0.h" +#include "system_hc32f4a0.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h new file mode 100644 index 0000000000..12817f78be --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h @@ -0,0 +1,142 @@ +/** + ******************************************************************************* + * @file system_hc32f4a0.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F4A0_H__ +#define __SYSTEM_HC32F4A0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F4A0_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Macros + * @{ + */ + +/** + * @addtogroup HC32F4A0_System_Clock_Source + * @{ + */ +#if !defined (MRC_VALUE) +#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (RTCLRC_VALUE) +#define RTCLRC_VALUE (32768UL) /*!< Internal RTC low speed RC freq. */ +#endif + +#if !defined (SWDTLRC_VALUE) +#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Exported_Variable + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Functions + * @{ + */ + +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +#if defined (ROM_EXT_QSPI) +void SystemInit_QspiMem(void); +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F4A0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_1M.FLM b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_1M.FLM new file mode 100644 index 0000000000..674f37e276 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_1M.FLM differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_2M.FLM b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_2M.FLM new file mode 100644 index 0000000000..d6329e6271 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_2M.FLM differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_RAM.FLM b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_RAM.FLM new file mode 100644 index 0000000000..2c8149793b Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_RAM.FLM differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_otp.FLM b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_otp.FLM new file mode 100644 index 0000000000..775741755e Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_otp.FLM differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini new file mode 100644 index 0000000000..4984db95e2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini @@ -0,0 +1,16 @@ +FUNC void Setup (void) { + + SP = _RDWORD(0x1FFE0000); + + PC = _RDWORD(0x1FFE0004); + + _WDWORD(0xE000ED08, 0x1FFE0000); + +} + + +LOAD .\output\release\efm_sequence_program.axf INCREMENTAL + +Setup(); + +g, main diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR new file mode 100644 index 0000000000..31dd19b3c2 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s new file mode 100644 index 0000000000..48c7fba25c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s @@ -0,0 +1,594 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Startup for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/* Target-mcu HC32F4A0 */ +;/****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xG.ld b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xG.ld new file mode 100644 index 0000000000..5572d181ff --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xG.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A0xG.ld */ +/* Abstract Linker script for HC32F4A0 Device with */ +/* 1MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000000; +__OTP_DATA_SIZE = 2048; +__OTP_LOCK_START = 0x03001840; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 1M + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xI.ld b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xI.ld new file mode 100644 index 0000000000..0129f986e0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F4A0xI.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A0xI.ld */ +/* Abstract Linker script for HC32F4A0 Device with */ +/* 2MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000000; +__OTP_DATA_SIZE = 2048; +__OTP_LOCK_START = 0x03001840; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S new file mode 100644 index 0000000000..2ea6cd3e70 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S @@ -0,0 +1,529 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +/*****************************************************************************/ +/* Startup for GCC */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/* Target-mcu HC32F4A0 */ +/*****************************************************************************/ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00002000 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00002000 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ +StackInit: + ldr r1, =__StackLimit + ldr r2, =__StackTop + + movs r0, 0 +StackInitLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt StackInitLoop + +ClrSramSR: + ldr r0, =0x40050810 + movw r1, #0x1FF + str r1, [r0] + + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ramb + ldr r2, =__data_start_ramb__ + ldr r3, =__data_end_ramb__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ramb__ + ldr r2, =__bss_end_ramb__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl entry + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F4A0.svd b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F4A0.svd new file mode 100644 index 0000000000..a8542c60e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F4A0.svd @@ -0,0 +1,102653 @@ + + + HDSC + HDSC + HDSC_HC32F4A0 + ARMCM4 + 1.0 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xC5 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SHCR + desc SHCR + 0x1A + 16 + read-write + 0x18 + 0x7FF + + + SHSST + desc SHSST + 7 + 0 + read-write + + + SHSEL + desc SHSEL + 10 + 8 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + read-write + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + read-write + + + CLREOCBF + desc CLREOCBF + 1 + 1 + read-write + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + read-write + + + + + SYNCCR + desc SYNCCR + 0x4C + 16 + read-write + 0xC00 + 0xFF71 + + + SYNCEN + desc SYNCEN + 0 + 0 + read-write + + + SYNCMD + desc SYNCMD + 6 + 4 + read-write + + + SYNCDLY + desc SYNCDLY + 15 + 8 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + PGACR1 + desc PGACR1 + 0xC0 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGACR2 + desc PGACR2 + 0xC1 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGACR3 + desc PGACR3 + 0xC2 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGAVSSENR + desc PGAVSSENR + 0xC4 + 8 + read-write + 0x0 + 0x7 + + + PGAVSSEN + desc PGAVSSEN + 2 + 0 + read-write + + + + + + + ADC2 + desc ADC2 + 0x40040400 + + 0x0 + 0xC5 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + write-only + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + write-only + + + CLREOCBF + desc CLREOCBF + 1 + 1 + write-only + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + write-only + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + PGACR1 + desc PGACR1 + 0xC0 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGAVSSENR + desc PGAVSSENR + 0xC4 + 8 + read-write + 0x0 + 0x1 + + + PGAVSSEN + desc PGAVSSEN + 0 + 0 + read-write + + + + + + + ADC3 + desc ADC3 + 0x40040800 + + 0x0 + 0xB1 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFFF + + + CHSELA + desc CHSELA + 19 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFFF + + + CHSELB + desc CHSELB + 19 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFFF + + + AVCHSEL + desc AVCHSEL + 19 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + write-only + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + write-only + + + CLREOCBF + desc CLREOCBF + 1 + 1 + write-only + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + write-only + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + DR16 + desc DR16 + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + DR17 + desc DR17 + 0x72 + 16 + read-only + 0x0 + 0xFFFF + + + DR18 + desc DR18 + 0x74 + 16 + read-only + 0x0 + 0xFFFF + + + DR19 + desc DR19 + 0x76 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + + + AES + desc AES + 0x40008000 + + 0x0 + 0x40 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x1B + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 1 + 1 + read-write + + + KEYSIZE + desc KEYSIZE + 4 + 3 + read-write + + + + + DR0 + desc DR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR0 + desc KR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR1 + desc KR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR2 + desc KR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR3 + desc KR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR4 + desc KR4 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR5 + desc KR5 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR6 + desc KR6 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR7 + desc KR7 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + AOS + desc AOS + 0x40010800 + + 0x0 + 0x174 + + + + INTSFTTRG + desc INTSFTTRG + 0x0 + 32 + write-only + 0x0 + 0x1 + + + STRG + desc STRG + 0 + 0 + write-only + + + + + DCU_TRGSEL1 + desc DCU_TRGSEL1 + 0x4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL2 + desc DCU_TRGSEL2 + 0x8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL3 + desc DCU_TRGSEL3 + 0xC + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL4 + desc DCU_TRGSEL4 + 0x10 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL0 + desc DMA1_TRGSEL0 + 0x14 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL1 + desc DMA1_TRGSEL1 + 0x18 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL2 + desc DMA1_TRGSEL2 + 0x1C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL3 + desc DMA1_TRGSEL3 + 0x20 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL4 + desc DMA1_TRGSEL4 + 0x24 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL5 + desc DMA1_TRGSEL5 + 0x28 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL6 + desc DMA1_TRGSEL6 + 0x2C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL7 + desc DMA1_TRGSEL7 + 0x30 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL0 + desc DMA2_TRGSEL0 + 0x34 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL1 + desc DMA2_TRGSEL1 + 0x38 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL2 + desc DMA2_TRGSEL2 + 0x3C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL3 + desc DMA2_TRGSEL3 + 0x40 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL4 + desc DMA2_TRGSEL4 + 0x44 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL5 + desc DMA2_TRGSEL5 + 0x48 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL6 + desc DMA2_TRGSEL6 + 0x4C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL7 + desc DMA2_TRGSEL7 + 0x50 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA_TRGSELRC + desc DMA_TRGSELRC + 0x54 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR0 + desc TMR6_HTSSR0 + 0x58 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR1 + desc TMR6_HTSSR1 + 0x5C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR2 + desc TMR6_HTSSR2 + 0x60 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR3 + desc TMR6_HTSSR3 + 0x64 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR12 + desc PEVNTTRGSR12 + 0x68 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR34 + desc PEVNTTRGSR34 + 0x6C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR0_HTSSR + desc TMR0_HTSSR + 0x70 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR2_HTSSR + desc TMR2_HTSSR + 0x74 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + HASH_ITRGSELA + desc HASH_ITRGSELA + 0x78 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + HASH_ITRGSELB + desc HASH_ITRGSELB + 0x7C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR0 + desc TMRA_HTSSR0 + 0x80 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR1 + desc TMRA_HTSSR1 + 0x84 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR2 + desc TMRA_HTSSR2 + 0x88 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR3 + desc TMRA_HTSSR3 + 0x8C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + OTS_TRG + desc OTS_TRG + 0x90 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR0 + desc ADC1_ITRGSELR0 + 0x94 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR1 + desc ADC1_ITRGSELR1 + 0x98 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR0 + desc ADC2_ITRGSELR0 + 0x9C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR1 + desc ADC2_ITRGSELR1 + 0xA0 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC3_ITRGSELR0 + desc ADC3_ITRGSELR0 + 0xA4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC3_ITRGSELR1 + desc ADC3_ITRGSELR1 + 0xA8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + COMTRG1 + desc COMTRG1 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + COMTRG2 + desc COMTRG2 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + PEVNTDIRR1 + desc PEVNTDIRR1 + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR1 + desc PEVNTIDR1 + 0x104 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR1 + desc PEVNTODR1 + 0x108 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR1 + desc PEVNTORR1 + 0x10C + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR1 + desc PEVNTOSR1 + 0x110 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR1 + desc PEVNTRISR1 + 0x114 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL1 + desc PEVNTFAL1 + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR2 + desc PEVNTDIRR2 + 0x11C + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR2 + desc PEVNTIDR2 + 0x120 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR2 + desc PEVNTODR2 + 0x124 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR2 + desc PEVNTORR2 + 0x128 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR2 + desc PEVNTOSR2 + 0x12C + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR2 + desc PEVNTRISR2 + 0x130 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL2 + desc PEVNTFAL2 + 0x134 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR3 + desc PEVNTDIRR3 + 0x138 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR3 + desc PEVNTIDR3 + 0x13C + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR3 + desc PEVNTODR3 + 0x140 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR3 + desc PEVNTORR3 + 0x144 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR3 + desc PEVNTOSR3 + 0x148 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR3 + desc PEVNTRISR3 + 0x14C + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL3 + desc PEVNTFAL3 + 0x150 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR4 + desc PEVNTDIRR4 + 0x154 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR4 + desc PEVNTIDR4 + 0x158 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR4 + desc PEVNTODR4 + 0x15C + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR4 + desc PEVNTORR4 + 0x160 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR4 + desc PEVNTOSR4 + 0x164 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR4 + desc PEVNTRISR4 + 0x168 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL4 + desc PEVNTFAL4 + 0x16C + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTNFCR + desc PEVNTNFCR + 0x170 + 32 + read-write + 0x0 + 0x7070707 + + + NFEN1 + desc NFEN1 + 0 + 0 + read-write + + + DIVS1 + desc DIVS1 + 2 + 1 + read-write + + + NFEN2 + desc NFEN2 + 8 + 8 + read-write + + + DIVS2 + desc DIVS2 + 10 + 9 + read-write + + + NFEN3 + desc NFEN3 + 16 + 16 + read-write + + + DIVS3 + desc DIVS3 + 18 + 17 + read-write + + + NFEN4 + desc NFEN4 + 24 + 24 + read-write + + + DIVS4 + desc DIVS4 + 26 + 25 + read-write + + + + + + + CAN1 + desc CAN + 0x40009000 + + 0x0 + 0xCA + + + + RBUF + desc RBUF + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TBUF + desc TBUF + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFG_STAT + desc CFG_STAT + 0xA0 + 8 + read-write + 0x80 + 0xFF + + + BUSOFF + desc BUSOFF + 0 + 0 + read-write + + + TACTIVE + desc TACTIVE + 1 + 1 + read-only + + + RACTIVE + desc RACTIVE + 2 + 2 + read-only + + + TSSS + desc TSSS + 3 + 3 + read-write + + + TPSS + desc TPSS + 4 + 4 + read-write + + + LBMI + desc LBMI + 5 + 5 + read-write + + + LBME + desc LBME + 6 + 6 + read-write + + + RESET + desc RESET + 7 + 7 + read-write + + + + + TCMD + desc TCMD + 0xA1 + 8 + read-write + 0x0 + 0xDF + + + TSA + desc TSA + 0 + 0 + read-write + + + TSALL + desc TSALL + 1 + 1 + read-write + + + TSONE + desc TSONE + 2 + 2 + read-write + + + TPA + desc TPA + 3 + 3 + read-write + + + TPE + desc TPE + 4 + 4 + read-write + + + LOM + desc LOM + 6 + 6 + read-write + + + TBSEL + desc TBSEL + 7 + 7 + read-write + + + + + TCTRL + desc TCTRL + 0xA2 + 8 + read-write + 0x90 + 0xF3 + + + TSSTAT + desc TSSTAT + 1 + 0 + read-only + + + TTTBM + desc TTTBM + 4 + 4 + read-write + + + TSMODE + desc TSMODE + 5 + 5 + read-write + + + TSNEXT + desc TSNEXT + 6 + 6 + read-write + + + FD_ISO + desc FD_ISO + 7 + 7 + read-write + + + + + RCTRL + desc RCTRL + 0xA3 + 8 + read-write + 0x0 + 0xFB + + + RSTAT + desc RSTAT + 1 + 0 + read-only + + + RBALL + desc RBALL + 3 + 3 + read-write + + + RREL + desc RREL + 4 + 4 + read-write + + + ROV + desc ROV + 5 + 5 + read-only + + + ROM + desc ROM + 6 + 6 + read-write + + + SACK + desc SACK + 7 + 7 + read-write + + + + + RTIE + desc RTIE + 0xA4 + 8 + read-write + 0xFE + 0xFF + + + TSFF + desc TSFF + 0 + 0 + read-only + + + EIE + desc EIE + 1 + 1 + read-write + + + TSIE + desc TSIE + 2 + 2 + read-write + + + TPIE + desc TPIE + 3 + 3 + read-write + + + RAFIE + desc RAFIE + 4 + 4 + read-write + + + RFIE + desc RFIE + 5 + 5 + read-write + + + ROIE + desc ROIE + 6 + 6 + read-write + + + RIE + desc RIE + 7 + 7 + read-write + + + + + RTIF + desc RTIF + 0xA5 + 8 + read-write + 0x0 + 0xFF + + + AIF + desc AIF + 0 + 0 + read-write + + + EIF + desc EIF + 1 + 1 + read-write + + + TSIF + desc TSIF + 2 + 2 + read-write + + + TPIF + desc TPIF + 3 + 3 + read-write + + + RAFIF + desc RAFIF + 4 + 4 + read-write + + + RFIF + desc RFIF + 5 + 5 + read-write + + + ROIF + desc ROIF + 6 + 6 + read-write + + + RIF + desc RIF + 7 + 7 + read-write + + + + + ERRINT + desc ERRINT + 0xA6 + 8 + read-write + 0x0 + 0xFF + + + BEIF + desc BEIF + 0 + 0 + read-write + + + BEIE + desc BEIE + 1 + 1 + read-write + + + ALIF + desc ALIF + 2 + 2 + read-write + + + ALIE + desc ALIE + 3 + 3 + read-write + + + EPIF + desc EPIF + 4 + 4 + read-write + + + EPIE + desc EPIE + 5 + 5 + read-write + + + EPASS + desc EPASS + 6 + 6 + read-only + + + EWARN + desc EWARN + 7 + 7 + read-only + + + + + LIMIT + desc LIMIT + 0xA7 + 8 + read-write + 0x1B + 0xFF + + + EWL + desc EWL + 3 + 0 + read-write + + + AFWL + desc AFWL + 7 + 4 + read-write + + + + + SBT + desc SBT + 0xA8 + 32 + read-write + 0x1020203 + 0xFF7F7FFF + + + S_SEG_1 + desc S_SEG_1 + 7 + 0 + read-write + + + S_SEG_2 + desc S_SEG_2 + 14 + 8 + read-write + + + S_SJW + desc S_SJW + 22 + 16 + read-write + + + S_PRESC + desc S_PRESC + 31 + 24 + read-write + + + + + FBT + desc FBT + 0xAC + 32 + read-write + 0x1020203 + 0xFF0F0F1F + + + F_SEG_1 + desc F_SEG_1 + 4 + 0 + read-write + + + F_SEG_2 + desc F_SEG_2 + 11 + 8 + read-write + + + F_SJW + desc F_SJW + 19 + 16 + read-write + + + F_PRESC + desc F_PRESC + 31 + 24 + read-write + + + + + EALCAP + desc EALCAP + 0xB0 + 8 + read-only + 0x0 + 0xFF + + + ALC + desc ALC + 4 + 0 + read-only + + + KOER + desc KOER + 7 + 5 + read-only + + + + + TDC + desc TDC + 0xB1 + 8 + read-write + 0x0 + 0xFF + + + SSPOFF + desc SSPOFF + 6 + 0 + read-write + + + TDCEN + desc TDCEN + 7 + 7 + read-write + + + + + RECNT + desc RECNT + 0xB2 + 8 + read-write + 0x0 + 0xFF + + + TECNT + desc TECNT + 0xB3 + 8 + read-write + 0x0 + 0xFF + + + ACFCTRL + desc ACFCTRL + 0xB4 + 8 + read-write + 0x0 + 0x2F + + + ACFADR + desc ACFADR + 3 + 0 + read-write + + + SELMASK + desc SELMASK + 5 + 5 + read-write + + + + + ACFEN + desc ACFEN + 0xB6 + 16 + read-write + 0x1 + 0xFFFF + + + AE_1 + desc AE_1 + 0 + 0 + read-write + + + AE_2 + desc AE_2 + 1 + 1 + read-write + + + AE_3 + desc AE_3 + 2 + 2 + read-write + + + AE_4 + desc AE_4 + 3 + 3 + read-write + + + AE_5 + desc AE_5 + 4 + 4 + read-write + + + AE_6 + desc AE_6 + 5 + 5 + read-write + + + AE_7 + desc AE_7 + 6 + 6 + read-write + + + AE_8 + desc AE_8 + 7 + 7 + read-write + + + AE_9 + desc AE_9 + 8 + 8 + read-write + + + AE_10 + desc AE_10 + 9 + 9 + read-write + + + AE_11 + desc AE_11 + 10 + 10 + read-write + + + AE_12 + desc AE_12 + 11 + 11 + read-write + + + AE_13 + desc AE_13 + 12 + 12 + read-write + + + AE_14 + desc AE_14 + 13 + 13 + read-write + + + AE_15 + desc AE_15 + 14 + 14 + read-write + + + AE_16 + desc AE_16 + 15 + 15 + read-write + + + + + ACF + desc ACF + 0xB8 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + ACODEORAMASK + desc ACODEORAMASK + 28 + 0 + read-write + + + AIDE + desc AIDE + 29 + 29 + read-write + + + AIDEE + desc AIDEE + 30 + 30 + read-write + + + + + TBSLOT + desc TBSLOT + 0xBE + 8 + read-write + 0x0 + 0xFF + + + TBPTR + desc TBPTR + 5 + 0 + read-write + + + TBF + desc TBF + 6 + 6 + read-write + + + TBE + desc TBE + 7 + 7 + read-write + + + + + TTCFG + desc TTCFG + 0xBF + 8 + read-write + 0x90 + 0xFF + + + TTEN + desc TTEN + 0 + 0 + read-write + + + T_PRESC + desc T_PRESC + 2 + 1 + read-write + + + TTIF + desc TTIF + 3 + 3 + read-write + + + TTIE + desc TTIE + 4 + 4 + read-write + + + TEIF + desc TEIF + 5 + 5 + read-write + + + WTIF + desc WTIF + 6 + 6 + read-write + + + WTIE + desc WTIE + 7 + 7 + read-write + + + + + REF_MSG + desc REF_MSG + 0xC0 + 32 + read-write + 0x0 + 0x9FFFFFFF + + + REF_ID + desc REF_ID + 28 + 0 + read-write + + + REF_IDE + desc REF_IDE + 31 + 31 + read-write + + + + + TRG_CFG + desc TRG_CFG + 0xC4 + 16 + read-write + 0x0 + 0xF73F + + + TTPTR + desc TTPTR + 5 + 0 + read-write + + + TTYPE + desc TTYPE + 10 + 8 + read-write + + + TEW + desc TEW + 15 + 12 + read-write + + + + + TT_TRIG + desc TT_TRIG + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + TT_WTRIG + desc TT_WTRIG + 0xC8 + 16 + read-write + 0xFFFF + 0xFFFF + + + + + CAN2 + desc CAN + 0x40078000 + + 0x0 + 0xCA + + + + CMP1 + desc CMP + 0x4004A000 + + 0x0 + 0xA + + + + MDR + desc MDR + 0x0 + 8 + read-write + 0x0 + 0x83 + + + CENB + desc CENB + 0 + 0 + read-write + + + CWDE + desc CWDE + 1 + 1 + read-write + + + CMON + desc CMON + 7 + 7 + read-only + + + + + FIR + desc FIR + 0x1 + 8 + read-write + 0x0 + 0x73 + + + FCKS + desc FCKS + 1 + 0 + read-write + + + EDGS + desc EDGS + 5 + 4 + read-write + + + CIEN + desc CIEN + 6 + 6 + read-write + + + + + OCR + desc OCR + 0x2 + 8 + read-write + 0x0 + 0x1F + + + COEN + desc COEN + 0 + 0 + read-write + + + COPS + desc COPS + 1 + 1 + read-write + + + CPOE + desc CPOE + 2 + 2 + read-write + + + TWOE + desc TWOE + 3 + 3 + read-write + + + TWOL + desc TWOL + 4 + 4 + read-write + + + + + PMSR + desc PMSR + 0x3 + 8 + read-write + 0x0 + 0xFF + + + RVSL + desc RVSL + 3 + 0 + read-write + + + CVSL + desc CVSL + 7 + 4 + read-write + + + + + TWSR + desc TWSR + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + CTWS0 + desc CTWS0 + 0 + 0 + read-write + + + CTWS1 + desc CTWS1 + 1 + 1 + read-write + + + CTWS2 + desc CTWS2 + 2 + 2 + read-write + + + CTWS3 + desc CTWS3 + 3 + 3 + read-write + + + CTWS4 + desc CTWS4 + 4 + 4 + read-write + + + CTWS5 + desc CTWS5 + 5 + 5 + read-write + + + CTWS6 + desc CTWS6 + 6 + 6 + read-write + + + CTWS7 + desc CTWS7 + 7 + 7 + read-write + + + CTWS8 + desc CTWS8 + 8 + 8 + read-write + + + CTWS9 + desc CTWS9 + 9 + 9 + read-write + + + CTWS10 + desc CTWS10 + 10 + 10 + read-write + + + CTWS11 + desc CTWS11 + 11 + 11 + read-write + + + CTWS12 + desc CTWS12 + 12 + 12 + read-write + + + CTWS13 + desc CTWS13 + 13 + 13 + read-write + + + CTWS14 + desc CTWS14 + 14 + 14 + read-write + + + CTWS15 + desc CTWS15 + 15 + 15 + read-write + + + + + TWPR + desc TWPR + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + CTWP0 + desc CTWP0 + 0 + 0 + read-write + + + CTWP1 + desc CTWP1 + 1 + 1 + read-write + + + CTWP2 + desc CTWP2 + 2 + 2 + read-write + + + CTWP3 + desc CTWP3 + 3 + 3 + read-write + + + CTWP4 + desc CTWP4 + 4 + 4 + read-write + + + CTWP5 + desc CTWP5 + 5 + 5 + read-write + + + CTWP6 + desc CTWP6 + 6 + 6 + read-write + + + CTWP7 + desc CTWP7 + 7 + 7 + read-write + + + CTWP8 + desc CTWP8 + 8 + 8 + read-write + + + CTWP9 + desc CTWP9 + 9 + 9 + read-write + + + CTWP10 + desc CTWP10 + 10 + 10 + read-write + + + CTWP11 + desc CTWP11 + 11 + 11 + read-write + + + CTWP12 + desc CTWP12 + 12 + 12 + read-write + + + CTWP13 + desc CTWP13 + 13 + 13 + read-write + + + CTWP14 + desc CTWP14 + 14 + 14 + read-write + + + CTWP15 + desc CTWP15 + 15 + 15 + read-write + + + + + VISR + desc VISR + 0x8 + 16 + read-write + 0x0 + 0x37 + + + P2SL + desc P2SL + 2 + 0 + read-write + + + P3SL + desc P3SL + 5 + 4 + read-write + + + + + + + CMP2 + desc CMP + 0x4004A010 + + 0x0 + 0xA + + + + CMP3 + desc CMP + 0x4004A400 + + 0x0 + 0xA + + + + CMP4 + desc CMP + 0x4004A410 + + 0x0 + 0xA + + + + CMU + desc CMU + 0x4004C400 + + 0x0 + 0x7D08 + + + + XTAL32CR + desc XTAL32CR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + XTAL32STP + desc XTAL32STP + 0 + 0 + read-write + + + + + XTAL32CFGR + desc XTAL32CFGR + 0x4 + 8 + read-write + 0x0 + 0x7 + + + XTAL32DRV + desc XTAL32DRV + 2 + 0 + read-write + + + XTAL32IE + desc XTAL32IE + 3 + 3 + read-write + + + + + XTAL32NFR + desc XTAL32NFR + 0x14 + 8 + read-write + 0x0 + 0x3 + + + XTAL32NF + desc XTAL32NF + 1 + 0 + read-write + + + + + LRCCR + desc LRCCR + 0x1C + 8 + read-write + 0x0 + 0x1 + + + LRCSTP + desc LRCSTP + 0 + 0 + read-write + + + + + RTCLRCCR + desc RTCLRCCR + 0x20 + 8 + read-write + 0x0 + 0x1 + + + RTCLRCSTP + desc RTCLRCSTP + 0 + 0 + read-write + + + + + LRCTRM + desc LRCTRM + 0x24 + 8 + read-write + 0x0 + 0xFF + + + RTCLRCTRM + desc RTCLRCTRM + 0x2C + 8 + read-write + 0x0 + 0xFF + + + XTALCFGR + desc XTALCFGR + 0x878 + 8 + read-write + 0x80 + 0x70 + + + XTALDRV + desc XTALDRV + 5 + 4 + read-write + + + XTALMS + desc XTALMS + 6 + 6 + read-write + + + + + PERICKSEL + desc PERICKSEL + 0x7C10 + 16 + read-write + 0x0 + 0xF + + + PERICKSEL + desc PERICKSEL + 3 + 0 + read-write + + + + + I2SCKSEL + desc I2SCKSEL + 0x7C12 + 16 + read-write + 0xBBBB + 0xFFFF + + + I2S1CKSEL + desc I2S1CKSEL + 3 + 0 + read-write + + + I2S2CKSEL + desc I2S2CKSEL + 7 + 4 + read-write + + + I2S3CKSEL + desc I2S3CKSEL + 11 + 8 + read-write + + + I2S4CKSEL + desc I2S4CKSEL + 15 + 12 + read-write + + + + + CANCKCFGR + desc CANCKCFGR + 0x7C18 + 8 + read-write + 0xDD + 0xFF + + + CAN1CKS + desc CAN1CKS + 3 + 0 + read-write + + + CAN2CKS + desc CAN2CKS + 7 + 4 + read-write + + + + + SCFGR + desc SCFGR + 0x7C20 + 32 + read-write + 0x0 + 0x7777777 + + + PCLK0S + desc PCLK0S + 2 + 0 + read-write + + + PCLK1S + desc PCLK1S + 6 + 4 + read-write + + + PCLK2S + desc PCLK2S + 10 + 8 + read-write + + + PCLK3S + desc PCLK3S + 14 + 12 + read-write + + + PCLK4S + desc PCLK4S + 18 + 16 + read-write + + + EXCKS + desc EXCKS + 22 + 20 + read-write + + + HCLKS + desc HCLKS + 26 + 24 + read-write + + + + + USBCKCFGR + desc USBCKCFGR + 0x7C24 + 8 + read-write + 0x40 + 0xF0 + + + USBCKS + desc USBCKS + 7 + 4 + read-write + + + + + CKSWR + desc CKSWR + 0x7C26 + 8 + read-write + 0x1 + 0x7 + + + CKSW + desc CKSW + 2 + 0 + read-write + + + + + PLLHCR + desc PLLHCR + 0x7C2A + 8 + read-write + 0x1 + 0x1 + + + PLLHOFF + desc PLLHOFF + 0 + 0 + read-write + + + + + PLLACR + desc PLLACR + 0x7C2E + 8 + read-write + 0x1 + 0x1 + + + PLLAOFF + desc PLLAOFF + 0 + 0 + read-write + + + + + XTALCR + desc XTALCR + 0x7C32 + 8 + read-write + 0x1 + 0x1 + + + XTALSTP + desc XTALSTP + 0 + 0 + read-write + + + + + HRCCR + desc HRCCR + 0x7C36 + 8 + read-write + 0x1 + 0x1 + + + HRCSTP + desc HRCSTP + 0 + 0 + read-write + + + + + MRCCR + desc MRCCR + 0x7C38 + 8 + read-write + 0x80 + 0x1 + + + MRCSTP + desc MRCSTP + 0 + 0 + read-write + + + + + OSCSTBSR + desc OSCSTBSR + 0x7C3C + 8 + read-write + 0x0 + 0xE9 + + + HRCSTBF + desc HRCSTBF + 0 + 0 + read-write + + + XTALSTBF + desc XTALSTBF + 3 + 3 + read-write + + + PLLHSTBF + desc PLLHSTBF + 5 + 5 + read-write + + + PLLASTBF + desc PLLASTBF + 6 + 6 + read-write + + + + + MCOCFGR1 + desc MCOCFGR1 + 0x7C3D + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + MCOCFGR2 + desc MCOCFGR2 + 0x7C3E + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + TPIUCKCFGR + desc TPIUCKCFGR + 0x7C3F + 8 + read-write + 0x0 + 0x83 + + + TPIUCKS + desc TPIUCKS + 1 + 0 + read-write + + + TPIUCKOE + desc TPIUCKOE + 7 + 7 + read-write + + + + + XTALSTDCR + desc XTALSTDCR + 0x7C40 + 8 + read-write + 0x0 + 0x87 + + + XTALSTDIE + desc XTALSTDIE + 0 + 0 + read-write + + + XTALSTDRE + desc XTALSTDRE + 1 + 1 + read-write + + + XTALSTDRIS + desc XTALSTDRIS + 2 + 2 + read-write + + + XTALSTDE + desc XTALSTDE + 7 + 7 + read-write + + + + + XTALSTDSR + desc XTALSTDSR + 0x7C41 + 8 + read-write + 0x0 + 0x1 + + + XTALSTDF + desc XTALSTDF + 0 + 0 + read-write + + + + + MRCTRM + desc MRCTRM + 0x7C61 + 8 + read-write + 0x0 + 0xFF + + + HRCTRM + desc HRCTRM + 0x7C62 + 8 + read-write + 0x0 + 0xFF + + + XTALSTBCR + desc XTALSTBCR + 0x7CA2 + 8 + read-write + 0x5 + 0xF + + + XTALSTB + desc XTALSTB + 3 + 0 + read-write + + + + + PLLHCFGR + desc PLLHCFGR + 0x7D00 + 32 + read-write + 0x11101300 + 0xFFF1FF9F + + + PLLHM + desc PLLHM + 1 + 0 + read-write + + + PLLSRC + desc PLLSRC + 7 + 7 + read-write + + + PLLHN + desc PLLHN + 15 + 8 + read-write + + + PLLHR + desc PLLHR + 23 + 20 + read-write + + + PLLHQ + desc PLLHQ + 27 + 24 + read-write + + + PLLHP + desc PLLHP + 31 + 28 + read-write + + + + + PLLACFGR + desc PLLACFGR + 0x7D04 + 32 + read-write + 0x11101300 + 0xFFF1FF1F + + + PLLAM + desc PLLAM + 4 + 0 + read-write + + + PLLAN + desc PLLAN + 16 + 8 + read-write + + + PLLAR + desc PLLAR + 23 + 20 + read-write + + + PLLAQ + desc PLLAQ + 27 + 24 + read-write + + + PLLAP + desc PLLAP + 31 + 28 + read-write + + + + + + + CRC + desc CRC + 0x40008C00 + + 0x0 + 0x100 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x1 + 0x3 + + + CR + desc CR + 0 + 0 + read-write + + + FLAG + desc FLAG + 1 + 1 + read-only + + + + + RESLT + desc RESLT + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT0 + desc DAT0 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT1 + desc DAT1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT2 + desc DAT2 + 0x88 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT3 + desc DAT3 + 0x8C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT4 + desc DAT4 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT5 + desc DAT5 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT6 + desc DAT6 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT7 + desc DAT7 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT8 + desc DAT8 + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT9 + desc DAT9 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT10 + desc DAT10 + 0xA8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT11 + desc DAT11 + 0xAC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT12 + desc DAT12 + 0xB0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT13 + desc DAT13 + 0xB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT14 + desc DAT14 + 0xB8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT15 + desc DAT15 + 0xBC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT16 + desc DAT16 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT17 + desc DAT17 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT18 + desc DAT18 + 0xC8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT19 + desc DAT19 + 0xCC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT20 + desc DAT20 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT21 + desc DAT21 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT22 + desc DAT22 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT23 + desc DAT23 + 0xDC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT24 + desc DAT24 + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT25 + desc DAT25 + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT26 + desc DAT26 + 0xE8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT27 + desc DAT27 + 0xEC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT28 + desc DAT28 + 0xF0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT29 + desc DAT29 + 0xF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT30 + desc DAT30 + 0xF8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT31 + desc DAT31 + 0xFC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + CTC + desc CTC + 0x40049C00 + + 0x0 + 0xC + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0x3F00F7 + + + REFPSC + desc REFPSC + 2 + 0 + read-write + + + REFCKS + desc REFCKS + 5 + 4 + read-write + + + ERRIE + desc ERRIE + 6 + 6 + read-write + + + CTCEN + desc CTCEN + 7 + 7 + read-write + + + TRMVAL + desc TRMVAL + 21 + 16 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xFFFF00FF + + + OFSVAL + desc OFSVAL + 7 + 0 + read-write + + + RLDVAL + desc RLDVAL + 31 + 16 + read-write + + + + + STR + desc STR + 0x8 + 32 + read-only + 0x0 + 0xF + + + TRIMOK + desc TRIMOK + 0 + 0 + read-only + + + TRMOVF + desc TRMOVF + 1 + 1 + read-only + + + TRMUDF + desc TRMUDF + 2 + 2 + read-only + + + CTCBSY + desc CTCBSY + 3 + 3 + read-only + + + + + + + DAC1 + desc DAC + 0x40041000 + + 0x0 + 0x1E + + + + DADR1 + desc DADR1 + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + DADR2 + desc DADR2 + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + DACR + desc DACR + 0x4 + 16 + read-write + 0x0 + 0x1F07 + + + DAEN + desc DAEN + 0 + 0 + read-write + + + DA1EN + desc DA1EN + 1 + 1 + read-write + + + DA2EN + desc DA2EN + 2 + 2 + read-write + + + ALIGN + desc ALIGN + 8 + 8 + read-write + + + DAAMP1 + desc DAAMP1 + 9 + 9 + read-write + + + DAAMP2 + desc DAAMP2 + 10 + 10 + read-write + + + EXTDSL1 + desc EXTDSL1 + 11 + 11 + read-write + + + EXTDSL2 + desc EXTDSL2 + 12 + 12 + read-write + + + + + DAADPCR + desc DAADPCR + 0x6 + 16 + read-write + 0x0 + 0x8307 + + + ADPSL1 + desc ADPSL1 + 0 + 0 + read-write + + + ADPSL2 + desc ADPSL2 + 1 + 1 + read-write + + + ADPSL3 + desc ADPSL3 + 2 + 2 + read-write + + + DA1SF + desc DA1SF + 8 + 8 + read-only + + + DA2SF + desc DA2SF + 9 + 9 + read-only + + + ADPEN + desc ADPEN + 15 + 15 + read-write + + + + + DAOCR + desc DAOCR + 0x1C + 16 + read-write + 0x0 + 0xC000 + + + DAODIS1 + desc DAODIS1 + 14 + 14 + read-write + + + DAODIS2 + desc DAODIS2 + 15 + 15 + read-write + + + + + + + DAC2 + desc DAC + 0x40041400 + + 0x0 + 0x1E + + + + DBGC + desc DBGC + 0xE0042000 + + 0x0 + 0x2C + + + + AUTHID0 + desc AUTHID0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID1 + desc AUTHID1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID2 + desc AUTHID2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESV0 + desc RESV0 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MCUSTAT + desc MCUSTAT + 0x10 + 32 + read-write + 0x0 + 0x30F + + + AUTH + desc AUTH + 0 + 0 + read-write + + + REMVLOCK + desc REMVLOCK + 1 + 1 + read-write + + + SAFTYLOCK1 + desc SAFTYLOCK1 + 2 + 2 + read-write + + + SAFTYLOCK2 + desc SAFTYLOCK2 + 3 + 3 + read-write + + + CPUSTOP + desc CPUSTOP + 8 + 8 + read-write + + + CPUSLEEP + desc CPUSLEEP + 9 + 9 + read-write + + + + + MCUCTL + desc MCUCTL + 0x14 + 32 + read-write + 0x0 + 0x103 + + + EDBGRQ + desc EDBGRQ + 0 + 0 + read-write + + + RESTART + desc RESTART + 1 + 1 + read-write + + + DIRQ + desc DIRQ + 8 + 8 + read-write + + + + + FMCCTL + desc FMCCTL + 0x18 + 32 + read-write + 0x0 + 0x7 + + + ERASEREQ + desc ERASEREQ + 0 + 0 + read-write + + + ERASEACK + desc ERASEACK + 1 + 1 + read-write + + + ERASEERR + desc ERASEERR + 2 + 2 + read-write + + + + + MCUDBGCSTAT + desc MCUDBGCSTAT + 0x1C + 32 + read-write + 0x0 + 0x3 + + + CDBGPWRUPREQ + desc CDBGPWRUPREQ + 0 + 0 + read-write + + + CDBGPWRUPACK + desc CDBGPWRUPACK + 1 + 1 + read-write + + + + + MCUSTPCTL + desc MCUSTPCTL + 0x20 + 32 + read-write + 0x3B + 0x7FFFFF + + + SWDTSTP + desc SWDTSTP + 0 + 0 + read-write + + + WDTSTP + desc WDTSTP + 1 + 1 + read-write + + + RTCSTP + desc RTCSTP + 2 + 2 + read-write + + + PVD0STP + desc PVD0STP + 3 + 3 + read-write + + + PVD1STP + desc PVD1STP + 4 + 4 + read-write + + + PVD2STP + desc PVD2STP + 5 + 5 + read-write + + + M06STP + desc M06STP + 6 + 6 + read-write + + + M07STP + desc M07STP + 7 + 7 + read-write + + + M08STP + desc M08STP + 8 + 8 + read-write + + + M09STP + desc M09STP + 9 + 9 + read-write + + + M10STP + desc M10STP + 10 + 10 + read-write + + + M11STP + desc M11STP + 11 + 11 + read-write + + + M12STP + desc M12STP + 12 + 12 + read-write + + + M13STP + desc M13STP + 13 + 13 + read-write + + + M14STP + desc M14STP + 14 + 14 + read-write + + + M15STP + desc M15STP + 15 + 15 + read-write + + + M16STP + desc M16STP + 16 + 16 + read-write + + + M17STP + desc M17STP + 17 + 17 + read-write + + + M18STP + desc M18STP + 18 + 18 + read-write + + + M19STP + desc M19STP + 19 + 19 + read-write + + + M20STP + desc M20STP + 20 + 20 + read-write + + + M21STP + desc M21STP + 21 + 21 + read-write + + + M22STP + desc M22STP + 22 + 22 + read-write + + + + + MCUTRACECTL + desc MCUTRACECTL + 0x24 + 32 + read-write + 0x0 + 0x7 + + + TRACEMODE + desc TRACEMODE + 1 + 0 + read-write + + + TRACEIOEN + desc TRACEIOEN + 2 + 2 + read-write + + + + + MCUSTPCTL2 + desc MCUSTPCTL2 + 0x28 + 32 + read-write + 0x0 + 0xFFF + + + M32STP + desc M32STP + 0 + 0 + read-write + + + M33STP + desc M33STP + 1 + 1 + read-write + + + M34STP + desc M34STP + 2 + 2 + read-write + + + M35STP + desc M35STP + 3 + 3 + read-write + + + M36STP + desc M36STP + 4 + 4 + read-write + + + M37STP + desc M37STP + 5 + 5 + read-write + + + M38STP + desc M38STP + 6 + 6 + read-write + + + M39STP + desc M39STP + 7 + 7 + read-write + + + M40STP + desc M40STP + 8 + 8 + read-write + + + M41STP + desc M41STP + 9 + 9 + read-write + + + M42STP + desc M42STP + 10 + 10 + read-write + + + M43STP + desc M43STP + 11 + 11 + read-write + + + + + + + DCU1 + desc DCU + 0x40056000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000013F + + + MODE + desc MODE + 3 + 0 + read-write + + + DATASIZE + desc DATASIZE + 5 + 4 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0xE7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + FLAG_RLD + desc FLAG_RLD + 9 + 9 + read-only + + + FLAG_BTM + desc FLAG_BTM + 10 + 10 + read-only + + + FLAG_TOP + desc FLAG_TOP + 11 + 11 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0xE7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + CLR_RLD + desc CLR_RLD + 9 + 9 + read-write + + + CLR_BTM + desc CLR_BTM + 10 + 10 + read-write + + + CLR_TOP + desc CLR_TOP + 11 + 11 + read-write + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0xFFF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + INT_RLD + desc INT_RLD + 9 + 9 + read-write + + + INT_BTM + desc INT_BTM + 10 + 10 + read-write + + + INT_TOP + desc INT_TOP + 11 + 11 + read-write + + + + + + + DCU2 + desc DCU + 0x40056400 + + 0x0 + 0x1C + + + + DCU3 + desc DCU + 0x40056800 + + 0x0 + 0x1C + + + + DCU4 + desc DCU + 0x40056C00 + + 0x0 + 0x1C + + + + DCU5 + desc DCU + 0x40057000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000013F + + + MODE + desc MODE + 3 + 0 + read-write + + + DATASIZE + desc DATASIZE + 5 + 4 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0x7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0x7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + + + + + DCU6 + desc DCU + 0x40057400 + + 0x0 + 0x1C + + + + DCU7 + desc DCU + 0x40057800 + + 0x0 + 0x1C + + + + DCU8 + desc DCU + 0x40057C00 + + 0x0 + 0x1C + + + + DMA1 + desc DMA + 0x40053000 + + 0x0 + 0x238 + + + + EN + desc EN + 0x0 + 32 + read-write + 0x0 + 0x1 + + + EN + desc EN + 0 + 0 + read-write + + + + + INTSTAT0 + desc INTSTAT0 + 0x4 + 32 + read-only + 0x0 + 0xFF00FF + + + TRNERR + desc TRNERR + 7 + 0 + read-only + + + REQERR + desc REQERR + 23 + 16 + read-only + + + + + INTSTAT1 + desc INTSTAT1 + 0x8 + 32 + read-only + 0x0 + 0xFF00FF + + + TC + desc TC + 7 + 0 + read-only + + + BTC + desc BTC + 23 + 16 + read-only + + + + + INTMASK0 + desc INTMASK0 + 0xC + 32 + read-write + 0x0 + 0xFF00FF + + + MSKTRNERR + desc MSKTRNERR + 7 + 0 + read-write + + + MSKREQERR + desc MSKREQERR + 23 + 16 + read-write + + + + + INTMASK1 + desc INTMASK1 + 0x10 + 32 + read-write + 0x0 + 0xFF00FF + + + MSKTC + desc MSKTC + 7 + 0 + read-write + + + MSKBTC + desc MSKBTC + 23 + 16 + read-write + + + + + INTCLR0 + desc INTCLR0 + 0x14 + 32 + read-write + 0x0 + 0xFF00FF + + + CLRTRNERR + desc CLRTRNERR + 7 + 0 + read-write + + + CLRREQERR + desc CLRREQERR + 23 + 16 + read-write + + + + + INTCLR1 + desc INTCLR1 + 0x18 + 32 + read-write + 0x0 + 0xFF00FF + + + CLRTC + desc CLRTC + 7 + 0 + read-write + + + CLRBTC + desc CLRBTC + 23 + 16 + read-write + + + + + CHEN + desc CHEN + 0x1C + 32 + read-write + 0x0 + 0xFF + + + CHEN + desc CHEN + 7 + 0 + read-write + + + + + REQSTAT + desc REQSTAT + 0x20 + 32 + read-only + 0x0 + 0x80FF + + + CHREQ + desc CHREQ + 7 + 0 + read-only + + + RCFGREQ + desc RCFGREQ + 15 + 15 + read-only + + + + + CHSTAT + desc CHSTAT + 0x24 + 32 + read-only + 0x0 + 0xFF0003 + + + DMAACT + desc DMAACT + 0 + 0 + read-only + + + RCFGACT + desc RCFGACT + 1 + 1 + read-only + + + CHACT + desc CHACT + 23 + 16 + read-only + + + + + RCFGCTL + desc RCFGCTL + 0x2C + 32 + read-write + 0x0 + 0x3F0F03 + + + RCFGEN + desc RCFGEN + 0 + 0 + read-write + + + RCFGLLP + desc RCFGLLP + 1 + 1 + read-write + + + RCFGCHS + desc RCFGCHS + 11 + 8 + read-write + + + SARMD + desc SARMD + 17 + 16 + read-write + + + DARMD + desc DARMD + 19 + 18 + read-write + + + CNTMD + desc CNTMD + 21 + 20 + read-write + + + + + CHENCLR + desc CHENCLR + 0x34 + 32 + read-write + 0x0 + 0xFF + + + CHENCLR + desc CHENCLR + 7 + 0 + read-write + + + + + SAR0 + desc SAR0 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR0 + desc DAR0 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL0 + desc DTCTL0 + 0x48 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT0 + desc RPT0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB0 + desc RPTB0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL0 + desc SNSEQCTL0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB0 + desc SNSEQCTLB0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL0 + desc DNSEQCTL0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB0 + desc DNSEQCTLB0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP0 + desc LLP0 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL0 + desc CHCTL0 + 0x5C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR0 + desc MONSAR0 + 0x60 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR0 + desc MONDAR0 + 0x64 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL0 + desc MONDTCTL0 + 0x68 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT0 + desc MONRPT0 + 0x6C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL0 + desc MONSNSEQCTL0 + 0x70 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL0 + desc MONDNSEQCTL0 + 0x74 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR1 + desc SAR1 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR1 + desc DAR1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL1 + desc DTCTL1 + 0x88 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT1 + desc RPT1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB1 + desc RPTB1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL1 + desc SNSEQCTL1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB1 + desc SNSEQCTLB1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL1 + desc DNSEQCTL1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB1 + desc DNSEQCTLB1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP1 + desc LLP1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL1 + desc CHCTL1 + 0x9C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR1 + desc MONSAR1 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR1 + desc MONDAR1 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL1 + desc MONDTCTL1 + 0xA8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT1 + desc MONRPT1 + 0xAC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL1 + desc MONSNSEQCTL1 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL1 + desc MONDNSEQCTL1 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR2 + desc SAR2 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR2 + desc DAR2 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL2 + desc DTCTL2 + 0xC8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT2 + desc RPT2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB2 + desc RPTB2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL2 + desc SNSEQCTL2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB2 + desc SNSEQCTLB2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL2 + desc DNSEQCTL2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB2 + desc DNSEQCTLB2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP2 + desc LLP2 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL2 + desc CHCTL2 + 0xDC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR2 + desc MONSAR2 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR2 + desc MONDAR2 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL2 + desc MONDTCTL2 + 0xE8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT2 + desc MONRPT2 + 0xEC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL2 + desc MONSNSEQCTL2 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL2 + desc MONDNSEQCTL2 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR3 + desc SAR3 + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR3 + desc DAR3 + 0x104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL3 + desc DTCTL3 + 0x108 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT3 + desc RPT3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB3 + desc RPTB3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL3 + desc SNSEQCTL3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB3 + desc SNSEQCTLB3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL3 + desc DNSEQCTL3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB3 + desc DNSEQCTLB3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP3 + desc LLP3 + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL3 + desc CHCTL3 + 0x11C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR3 + desc MONSAR3 + 0x120 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR3 + desc MONDAR3 + 0x124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL3 + desc MONDTCTL3 + 0x128 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT3 + desc MONRPT3 + 0x12C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL3 + desc MONSNSEQCTL3 + 0x130 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL3 + desc MONDNSEQCTL3 + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR4 + desc SAR4 + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR4 + desc DAR4 + 0x144 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL4 + desc DTCTL4 + 0x148 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT4 + desc RPT4 + 0x14C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB4 + desc RPTB4 + 0x14C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL4 + desc SNSEQCTL4 + 0x150 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB4 + desc SNSEQCTLB4 + 0x150 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL4 + desc DNSEQCTL4 + 0x154 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB4 + desc DNSEQCTLB4 + 0x154 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP4 + desc LLP4 + 0x158 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL4 + desc CHCTL4 + 0x15C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR4 + desc MONSAR4 + 0x160 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR4 + desc MONDAR4 + 0x164 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL4 + desc MONDTCTL4 + 0x168 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT4 + desc MONRPT4 + 0x16C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL4 + desc MONSNSEQCTL4 + 0x170 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL4 + desc MONDNSEQCTL4 + 0x174 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR5 + desc SAR5 + 0x180 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR5 + desc DAR5 + 0x184 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL5 + desc DTCTL5 + 0x188 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT5 + desc RPT5 + 0x18C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB5 + desc RPTB5 + 0x18C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL5 + desc SNSEQCTL5 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB5 + desc SNSEQCTLB5 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL5 + desc DNSEQCTL5 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB5 + desc DNSEQCTLB5 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP5 + desc LLP5 + 0x198 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL5 + desc CHCTL5 + 0x19C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR5 + desc MONSAR5 + 0x1A0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR5 + desc MONDAR5 + 0x1A4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL5 + desc MONDTCTL5 + 0x1A8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT5 + desc MONRPT5 + 0x1AC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL5 + desc MONSNSEQCTL5 + 0x1B0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL5 + desc MONDNSEQCTL5 + 0x1B4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR6 + desc SAR6 + 0x1C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR6 + desc DAR6 + 0x1C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL6 + desc DTCTL6 + 0x1C8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT6 + desc RPT6 + 0x1CC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB6 + desc RPTB6 + 0x1CC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL6 + desc SNSEQCTL6 + 0x1D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB6 + desc SNSEQCTLB6 + 0x1D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL6 + desc DNSEQCTL6 + 0x1D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB6 + desc DNSEQCTLB6 + 0x1D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP6 + desc LLP6 + 0x1D8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL6 + desc CHCTL6 + 0x1DC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR6 + desc MONSAR6 + 0x1E0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR6 + desc MONDAR6 + 0x1E4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL6 + desc MONDTCTL6 + 0x1E8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT6 + desc MONRPT6 + 0x1EC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL6 + desc MONSNSEQCTL6 + 0x1F0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL6 + desc MONDNSEQCTL6 + 0x1F4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR7 + desc SAR7 + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR7 + desc DAR7 + 0x204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL7 + desc DTCTL7 + 0x208 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT7 + desc RPT7 + 0x20C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB7 + desc RPTB7 + 0x20C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL7 + desc SNSEQCTL7 + 0x210 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB7 + desc SNSEQCTLB7 + 0x210 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL7 + desc DNSEQCTL7 + 0x214 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB7 + desc DNSEQCTLB7 + 0x214 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP7 + desc LLP7 + 0x218 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL7 + desc CHCTL7 + 0x21C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR7 + desc MONSAR7 + 0x220 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR7 + desc MONDAR7 + 0x224 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL7 + desc MONDTCTL7 + 0x228 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT7 + desc MONRPT7 + 0x22C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL7 + desc MONSNSEQCTL7 + 0x230 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL7 + desc MONDNSEQCTL7 + 0x234 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + + + DMA2 + desc DMA + 0x40053400 + + 0x0 + 0x238 + + + + DMC + desc DMC + 0x88000400 + + 0x0 + 0x304 + + + + STSR + desc STSR + 0x0 + 32 + read-only + 0x700 + 0xF + + + STATUS + desc STATUS + 1 + 0 + read-only + + + MEMW + desc MEMW + 3 + 2 + read-only + + + + + STCR + desc STCR + 0x4 + 32 + write-only + 0x0 + 0x7 + + + STCTL + desc STCTL + 2 + 0 + write-only + + + + + CMDR + desc CMDR + 0x8 + 32 + write-only + 0x0 + 0x13F3FFF + + + CMDADD + desc CMDADD + 13 + 0 + write-only + + + CMDBA + desc CMDBA + 17 + 16 + write-only + + + CMD + desc CMD + 19 + 18 + write-only + + + CMDCHIP + desc CMDCHIP + 21 + 20 + write-only + + + + + CPCR + desc CPCR + 0xC + 32 + read-write + 0x20040 + 0x307FFF7 + + + COLBS + desc COLBS + 2 + 0 + read-write + + + ROWBS + desc ROWBS + 6 + 4 + read-write + + + APBS + desc APBS + 7 + 7 + read-write + + + CKEDIS + desc CKEDIS + 8 + 8 + read-write + + + CKSTOP + desc CKSTOP + 9 + 9 + read-write + + + CKEDISPRD + desc CKEDISPRD + 15 + 10 + read-write + + + BURST + desc BURST + 18 + 16 + read-write + + + ACTCP + desc ACTCP + 25 + 24 + read-write + + + + + RFTR + desc RFTR + 0x10 + 32 + read-write + 0xA60 + 0x7FFF + + + REFPRD + desc REFPRD + 14 + 0 + read-write + + + + + TMCR_T_CASL + desc TMCR_T_CASL + 0x14 + 32 + read-write + 0x3 + 0x7 + + + T_CASL + desc T_CASL + 2 + 0 + read-write + + + + + TMCR_T_DQSS + desc TMCR_T_DQSS + 0x18 + 32 + read-write + 0x1 + 0x3 + + + T_DQSS + desc T_DQSS + 1 + 0 + read-write + + + + + TMCR_T_MRD + desc TMCR_T_MRD + 0x1C + 32 + read-write + 0x2 + 0x7F + + + T_MRD + desc T_MRD + 6 + 0 + read-write + + + + + TMCR_T_RAS + desc TMCR_T_RAS + 0x20 + 32 + read-write + 0x7 + 0xF + + + T_RAS + desc T_RAS + 3 + 0 + read-write + + + + + TMCR_T_RC + desc TMCR_T_RC + 0x24 + 32 + read-write + 0xB + 0xF + + + T_RC + desc T_RC + 3 + 0 + read-write + + + + + TMCR_T_RCD + desc TMCR_T_RCD + 0x28 + 32 + read-write + 0x35 + 0x77 + + + T_RCD_B + desc T_RCD_B + 2 + 0 + read-write + + + T_RCD_P + desc T_RCD_P + 6 + 4 + read-write + + + + + TMCR_T_RFC + desc TMCR_T_RFC + 0x2C + 32 + read-write + 0x1012 + 0x1F1F + + + T_RFC_B + desc T_RFC_B + 4 + 0 + read-write + + + T_RFC_P + desc T_RFC_P + 12 + 8 + read-write + + + + + TMCR_T_RP + desc TMCR_T_RP + 0x30 + 32 + read-write + 0x35 + 0x77 + + + T_RP_B + desc T_RP_B + 2 + 0 + read-write + + + T_RP_P + desc T_RP_P + 6 + 4 + read-write + + + + + TMCR_T_RRD + desc TMCR_T_RRD + 0x34 + 32 + read-write + 0x2 + 0xF + + + T_RRD + desc T_RRD + 3 + 0 + read-write + + + + + TMCR_T_WR + desc TMCR_T_WR + 0x38 + 32 + read-write + 0x3 + 0x7 + + + T_WR + desc T_WR + 2 + 0 + read-write + + + + + TMCR_T_WTR + desc TMCR_T_WTR + 0x3C + 32 + read-write + 0x2 + 0x7 + + + T_WTR + desc T_WTR + 2 + 0 + read-write + + + + + TMCR_T_XP + desc TMCR_T_XP + 0x40 + 32 + read-write + 0x1 + 0xFF + + + T_XP + desc T_XP + 7 + 0 + read-write + + + + + TMCR_T_XSR + desc TMCR_T_XSR + 0x44 + 32 + read-write + 0xA + 0xFF + + + T_XSR + desc T_XSR + 7 + 0 + read-write + + + + + TMCR_T_ESR + desc TMCR_T_ESR + 0x48 + 32 + read-write + 0x14 + 0xFF + + + T_ESR + desc T_ESR + 7 + 0 + read-write + + + + + CSCR0 + desc CSCR0 + 0x200 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR1 + desc CSCR1 + 0x204 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR2 + desc CSCR2 + 0x208 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR3 + desc CSCR3 + 0x20C + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + BACR + desc BACR + 0x300 + 32 + read-write + 0x300 + 0x100C003 + + + DMCMW + desc DMCMW + 1 + 0 + read-write + + + CKSEL + desc CKSEL + 15 + 14 + read-write + + + + + + + DVP + desc DVP + 0x40055800 + + 0x0 + 0x30 + + + + CTR + desc CTR + 0x0 + 32 + read-write + 0x0 + 0x4FFF + + + CAPEN + desc CAPEN + 0 + 0 + read-write + + + CAPMD + desc CAPMD + 1 + 1 + read-write + + + CROPEN + desc CROPEN + 2 + 2 + read-write + + + JPEGEN + desc JPEGEN + 3 + 3 + read-write + + + SWSYNC + desc SWSYNC + 4 + 4 + read-write + + + PIXCKSEL + desc PIXCKSEL + 5 + 5 + read-write + + + HSYNCSEL + desc HSYNCSEL + 6 + 6 + read-write + + + VSYNCSEL + desc VSYNCSEL + 7 + 7 + read-write + + + CAPFRC + desc CAPFRC + 9 + 8 + read-write + + + BITSEL + desc BITSEL + 11 + 10 + read-write + + + DVPEN + desc DVPEN + 14 + 14 + read-write + + + + + DTR + desc DTR + 0x4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + STR + desc STR + 0x8 + 32 + read-write + 0x0 + 0x3F + + + FSF + desc FSF + 0 + 0 + read-write + + + LSF + desc LSF + 1 + 1 + read-write + + + LEF + desc LEF + 2 + 2 + read-write + + + FEF + desc FEF + 3 + 3 + read-write + + + SQUERF + desc SQUERF + 4 + 4 + read-write + + + FIFOERF + desc FIFOERF + 5 + 5 + read-write + + + + + IER + desc IER + 0xC + 32 + read-write + 0x0 + 0x3F + + + FSIEN + desc FSIEN + 0 + 0 + read-write + + + LSIEN + desc LSIEN + 1 + 1 + read-write + + + LEIEN + desc LEIEN + 2 + 2 + read-write + + + FEIEN + desc FEIEN + 3 + 3 + read-write + + + SQUERIEN + desc SQUERIEN + 4 + 4 + read-write + + + FIFOERIEN + desc FIFOERIEN + 5 + 5 + read-write + + + + + DMR + desc DMR + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SSYNDR + desc SSYNDR + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FSDAT + desc FSDAT + 7 + 0 + read-write + + + LSDAT + desc LSDAT + 15 + 8 + read-write + + + LEDAT + desc LEDAT + 23 + 16 + read-write + + + FEDAT + desc FEDAT + 31 + 24 + read-write + + + + + SSYNMR + desc SSYNMR + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FSMSK + desc FSMSK + 7 + 0 + read-write + + + LSMSK + desc LSMSK + 15 + 8 + read-write + + + LEMSK + desc LEMSK + 23 + 16 + read-write + + + FEMSK + desc FEMSK + 31 + 24 + read-write + + + + + CPSFTR + desc CPSFTR + 0x28 + 32 + read-write + 0x0 + 0x3FFF3FFF + + + RSHIFT + desc RSHIFT + 13 + 0 + read-write + + + CSHIFT + desc CSHIFT + 29 + 16 + read-write + + + + + CPSZER + desc CPSZER + 0x2C + 32 + read-write + 0x0 + 0x3FFF3FFF + + + RSIZE + desc RSIZE + 13 + 0 + read-write + + + CSIZE + desc CSIZE + 29 + 16 + read-write + + + + + + + EFM + desc EFM + 0x40010400 + + 0x0 + 0x1B0 + + + + FAPRT + desc FAPRT + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + FAPRT + desc FAPRT + 15 + 0 + read-write + + + + + KEY1 + desc KEY1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KEY2 + desc KEY2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FSTP + desc FSTP + 0x14 + 32 + read-write + 0x0 + 0x3 + + + F0STP + desc F0STP + 0 + 0 + read-write + + + F1STP + desc F1STP + 1 + 1 + read-write + + + + + FRMC + desc FRMC + 0x18 + 32 + read-write + 0x0 + 0xF010F + + + FLWT + desc FLWT + 3 + 0 + read-write + + + LVM + desc LVM + 8 + 8 + read-write + + + ICACHE + desc ICACHE + 16 + 16 + read-write + + + DCACHE + desc DCACHE + 17 + 17 + read-write + + + PREFETE + desc PREFETE + 18 + 18 + read-write + + + CRST + desc CRST + 19 + 19 + read-write + + + + + FWMC + desc FWMC + 0x1C + 32 + read-write + 0x30000 + 0x30107 + + + PEMOD + desc PEMOD + 2 + 0 + read-write + + + BUSHLDCTL + desc BUSHLDCTL + 8 + 8 + read-write + + + KEY1LOCK + desc KEY1LOCK + 16 + 16 + read-write + + + KEY2LOCK + desc KEY2LOCK + 17 + 17 + read-write + + + + + FSR + desc FSR + 0x20 + 32 + read-only + 0x1000100 + 0x13E013F + + + OTPWERR0 + desc OTPWERR0 + 0 + 0 + read-only + + + PRTWERR0 + desc PRTWERR0 + 1 + 1 + read-only + + + PGSZERR0 + desc PGSZERR0 + 2 + 2 + read-only + + + MISMTCH0 + desc MISMTCH0 + 3 + 3 + read-only + + + OPTEND0 + desc OPTEND0 + 4 + 4 + read-only + + + COLERR0 + desc COLERR0 + 5 + 5 + read-only + + + RDY0 + desc RDY0 + 8 + 8 + read-only + + + PRTWERR1 + desc PRTWERR1 + 17 + 17 + read-only + + + PGSZERR1 + desc PGSZERR1 + 18 + 18 + read-only + + + MISMTCH1 + desc MISMTCH1 + 19 + 19 + read-only + + + OPTEND1 + desc OPTEND1 + 20 + 20 + read-only + + + COLERR1 + desc COLERR1 + 21 + 21 + read-only + + + RDY1 + desc RDY1 + 24 + 24 + read-only + + + + + FSCLR + desc FSCLR + 0x24 + 32 + read-write + 0x0 + 0x3E003F + + + OTPWERRCLR0 + desc OTPWERRCLR0 + 0 + 0 + read-write + + + PRTWERRCLR0 + desc PRTWERRCLR0 + 1 + 1 + read-write + + + PGSZERRCLR0 + desc PGSZERRCLR0 + 2 + 2 + read-write + + + MISMTCHCLR0 + desc MISMTCHCLR0 + 3 + 3 + read-write + + + OPTENDCLR0 + desc OPTENDCLR0 + 4 + 4 + read-write + + + COLERRCLR0 + desc COLERRCLR0 + 5 + 5 + read-write + + + PRTWERRCLR1 + desc PRTWERRCLR1 + 17 + 17 + read-write + + + PGSZERRCLR1 + desc PGSZERRCLR1 + 18 + 18 + read-write + + + MISMTCHCLR1 + desc MISMTCHCLR1 + 19 + 19 + read-write + + + OPTENDCLR1 + desc OPTENDCLR1 + 20 + 20 + read-write + + + COLERRCLR1 + desc COLERRCLR1 + 21 + 21 + read-write + + + + + FITE + desc FITE + 0x28 + 32 + read-write + 0x0 + 0x7 + + + PEERRITE + desc PEERRITE + 0 + 0 + read-write + + + OPTENDITE + desc OPTENDITE + 1 + 1 + read-write + + + COLERRITE + desc COLERRITE + 2 + 2 + read-write + + + + + FSWP + desc FSWP + 0x2C + 32 + read-only + 0x0 + 0x1 + + + FSWP + desc FSWP + 0 + 0 + read-only + + + + + CHIPID + desc CHIPID + 0x40 + 32 + read-only + 0x484404A0 + 0xFFFFFFFF + + + UQID0 + desc UQID0 + 0x50 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID1 + desc UQID1 + 0x54 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID2 + desc UQID2 + 0x58 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 15 + 0 + read-write + + + + + MMF_REMCR0 + desc MMF_REMCR0 + 0x104 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + MMF_REMCR1 + desc MMF_REMCR1 + 0x108 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + WLOCK + desc WLOCK + 0x180 + 32 + read-write + 0x0 + 0xFF + + + WLOCK + desc WLOCK + 7 + 0 + read-write + + + + + F0NWPRT0 + desc F0NWPRT0 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT0 + desc F0NWPRT0 + 0 + 0 + read-write + + + F0NWPRT1 + desc F0NWPRT1 + 1 + 1 + read-write + + + F0NWPRT2 + desc F0NWPRT2 + 2 + 2 + read-write + + + F0NWPRT3 + desc F0NWPRT3 + 3 + 3 + read-write + + + F0NWPRT4 + desc F0NWPRT4 + 4 + 4 + read-write + + + F0NWPRT5 + desc F0NWPRT5 + 5 + 5 + read-write + + + F0NWPRT6 + desc F0NWPRT6 + 6 + 6 + read-write + + + F0NWPRT7 + desc F0NWPRT7 + 7 + 7 + read-write + + + F0NWPRT8 + desc F0NWPRT8 + 8 + 8 + read-write + + + F0NWPRT9 + desc F0NWPRT9 + 9 + 9 + read-write + + + F0NWPRT10 + desc F0NWPRT10 + 10 + 10 + read-write + + + F0NWPRT11 + desc F0NWPRT11 + 11 + 11 + read-write + + + F0NWPRT12 + desc F0NWPRT12 + 12 + 12 + read-write + + + F0NWPRT13 + desc F0NWPRT13 + 13 + 13 + read-write + + + F0NWPRT14 + desc F0NWPRT14 + 14 + 14 + read-write + + + F0NWPRT15 + desc F0NWPRT15 + 15 + 15 + read-write + + + F0NWPRT16 + desc F0NWPRT16 + 16 + 16 + read-write + + + F0NWPRT17 + desc F0NWPRT17 + 17 + 17 + read-write + + + F0NWPRT18 + desc F0NWPRT18 + 18 + 18 + read-write + + + F0NWPRT19 + desc F0NWPRT19 + 19 + 19 + read-write + + + F0NWPRT20 + desc F0NWPRT20 + 20 + 20 + read-write + + + F0NWPRT21 + desc F0NWPRT21 + 21 + 21 + read-write + + + F0NWPRT22 + desc F0NWPRT22 + 22 + 22 + read-write + + + F0NWPRT23 + desc F0NWPRT23 + 23 + 23 + read-write + + + F0NWPRT24 + desc F0NWPRT24 + 24 + 24 + read-write + + + F0NWPRT25 + desc F0NWPRT25 + 25 + 25 + read-write + + + F0NWPRT26 + desc F0NWPRT26 + 26 + 26 + read-write + + + F0NWPRT27 + desc F0NWPRT27 + 27 + 27 + read-write + + + F0NWPRT28 + desc F0NWPRT28 + 28 + 28 + read-write + + + F0NWPRT29 + desc F0NWPRT29 + 29 + 29 + read-write + + + F0NWPRT30 + desc F0NWPRT30 + 30 + 30 + read-write + + + F0NWPRT31 + desc F0NWPRT31 + 31 + 31 + read-write + + + + + F0NWPRT1 + desc F0NWPRT1 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT32 + desc F0NWPRT32 + 0 + 0 + read-write + + + F0NWPRT33 + desc F0NWPRT33 + 1 + 1 + read-write + + + F0NWPRT34 + desc F0NWPRT34 + 2 + 2 + read-write + + + F0NWPRT35 + desc F0NWPRT35 + 3 + 3 + read-write + + + F0NWPRT36 + desc F0NWPRT36 + 4 + 4 + read-write + + + F0NWPRT37 + desc F0NWPRT37 + 5 + 5 + read-write + + + F0NWPRT38 + desc F0NWPRT38 + 6 + 6 + read-write + + + F0NWPRT39 + desc F0NWPRT39 + 7 + 7 + read-write + + + F0NWPRT40 + desc F0NWPRT40 + 8 + 8 + read-write + + + F0NWPRT41 + desc F0NWPRT41 + 9 + 9 + read-write + + + F0NWPRT42 + desc F0NWPRT42 + 10 + 10 + read-write + + + F0NWPRT43 + desc F0NWPRT43 + 11 + 11 + read-write + + + F0NWPRT44 + desc F0NWPRT44 + 12 + 12 + read-write + + + F0NWPRT45 + desc F0NWPRT45 + 13 + 13 + read-write + + + F0NWPRT46 + desc F0NWPRT46 + 14 + 14 + read-write + + + F0NWPRT47 + desc F0NWPRT47 + 15 + 15 + read-write + + + F0NWPRT48 + desc F0NWPRT48 + 16 + 16 + read-write + + + F0NWPRT49 + desc F0NWPRT49 + 17 + 17 + read-write + + + F0NWPRT50 + desc F0NWPRT50 + 18 + 18 + read-write + + + F0NWPRT51 + desc F0NWPRT51 + 19 + 19 + read-write + + + F0NWPRT52 + desc F0NWPRT52 + 20 + 20 + read-write + + + F0NWPRT53 + desc F0NWPRT53 + 21 + 21 + read-write + + + F0NWPRT54 + desc F0NWPRT54 + 22 + 22 + read-write + + + F0NWPRT55 + desc F0NWPRT55 + 23 + 23 + read-write + + + F0NWPRT56 + desc F0NWPRT56 + 24 + 24 + read-write + + + F0NWPRT57 + desc F0NWPRT57 + 25 + 25 + read-write + + + F0NWPRT58 + desc F0NWPRT58 + 26 + 26 + read-write + + + F0NWPRT59 + desc F0NWPRT59 + 27 + 27 + read-write + + + F0NWPRT60 + desc F0NWPRT60 + 28 + 28 + read-write + + + F0NWPRT61 + desc F0NWPRT61 + 29 + 29 + read-write + + + F0NWPRT62 + desc F0NWPRT62 + 30 + 30 + read-write + + + F0NWPRT63 + desc F0NWPRT63 + 31 + 31 + read-write + + + + + F0NWPRT2 + desc F0NWPRT2 + 0x198 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT64 + desc F0NWPRT64 + 0 + 0 + read-write + + + F0NWPRT65 + desc F0NWPRT65 + 1 + 1 + read-write + + + F0NWPRT66 + desc F0NWPRT66 + 2 + 2 + read-write + + + F0NWPRT67 + desc F0NWPRT67 + 3 + 3 + read-write + + + F0NWPRT68 + desc F0NWPRT68 + 4 + 4 + read-write + + + F0NWPRT69 + desc F0NWPRT69 + 5 + 5 + read-write + + + F0NWPRT70 + desc F0NWPRT70 + 6 + 6 + read-write + + + F0NWPRT71 + desc F0NWPRT71 + 7 + 7 + read-write + + + F0NWPRT72 + desc F0NWPRT72 + 8 + 8 + read-write + + + F0NWPRT73 + desc F0NWPRT73 + 9 + 9 + read-write + + + F0NWPRT74 + desc F0NWPRT74 + 10 + 10 + read-write + + + F0NWPRT75 + desc F0NWPRT75 + 11 + 11 + read-write + + + F0NWPRT76 + desc F0NWPRT76 + 12 + 12 + read-write + + + F0NWPRT77 + desc F0NWPRT77 + 13 + 13 + read-write + + + F0NWPRT78 + desc F0NWPRT78 + 14 + 14 + read-write + + + F0NWPRT79 + desc F0NWPRT79 + 15 + 15 + read-write + + + F0NWPRT80 + desc F0NWPRT80 + 16 + 16 + read-write + + + F0NWPRT81 + desc F0NWPRT81 + 17 + 17 + read-write + + + F0NWPRT82 + desc F0NWPRT82 + 18 + 18 + read-write + + + F0NWPRT83 + desc F0NWPRT83 + 19 + 19 + read-write + + + F0NWPRT84 + desc F0NWPRT84 + 20 + 20 + read-write + + + F0NWPRT85 + desc F0NWPRT85 + 21 + 21 + read-write + + + F0NWPRT86 + desc F0NWPRT86 + 22 + 22 + read-write + + + F0NWPRT87 + desc F0NWPRT87 + 23 + 23 + read-write + + + F0NWPRT88 + desc F0NWPRT88 + 24 + 24 + read-write + + + F0NWPRT89 + desc F0NWPRT89 + 25 + 25 + read-write + + + F0NWPRT90 + desc F0NWPRT90 + 26 + 26 + read-write + + + F0NWPRT91 + desc F0NWPRT91 + 27 + 27 + read-write + + + F0NWPRT92 + desc F0NWPRT92 + 28 + 28 + read-write + + + F0NWPRT93 + desc F0NWPRT93 + 29 + 29 + read-write + + + F0NWPRT94 + desc F0NWPRT94 + 30 + 30 + read-write + + + F0NWPRT95 + desc F0NWPRT95 + 31 + 31 + read-write + + + + + F0NWPRT3 + desc F0NWPRT3 + 0x19C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT96 + desc F0NWPRT96 + 0 + 0 + read-write + + + F0NWPRT97 + desc F0NWPRT97 + 1 + 1 + read-write + + + F0NWPRT98 + desc F0NWPRT98 + 2 + 2 + read-write + + + F0NWPRT99 + desc F0NWPRT99 + 3 + 3 + read-write + + + F0NWPRT100 + desc F0NWPRT100 + 4 + 4 + read-write + + + F0NWPRT101 + desc F0NWPRT101 + 5 + 5 + read-write + + + F0NWPRT102 + desc F0NWPRT102 + 6 + 6 + read-write + + + F0NWPRT103 + desc F0NWPRT103 + 7 + 7 + read-write + + + F0NWPRT104 + desc F0NWPRT104 + 8 + 8 + read-write + + + F0NWPRT105 + desc F0NWPRT105 + 9 + 9 + read-write + + + F0NWPRT106 + desc F0NWPRT106 + 10 + 10 + read-write + + + F0NWPRT107 + desc F0NWPRT107 + 11 + 11 + read-write + + + F0NWPRT108 + desc F0NWPRT108 + 12 + 12 + read-write + + + F0NWPRT109 + desc F0NWPRT109 + 13 + 13 + read-write + + + F0NWPRT110 + desc F0NWPRT110 + 14 + 14 + read-write + + + F0NWPRT111 + desc F0NWPRT111 + 15 + 15 + read-write + + + F0NWPRT112 + desc F0NWPRT112 + 16 + 16 + read-write + + + F0NWPRT113 + desc F0NWPRT113 + 17 + 17 + read-write + + + F0NWPRT114 + desc F0NWPRT114 + 18 + 18 + read-write + + + F0NWPRT115 + desc F0NWPRT115 + 19 + 19 + read-write + + + F0NWPRT116 + desc F0NWPRT116 + 20 + 20 + read-write + + + F0NWPRT117 + desc F0NWPRT117 + 21 + 21 + read-write + + + F0NWPRT118 + desc F0NWPRT118 + 22 + 22 + read-write + + + F0NWPRT119 + desc F0NWPRT119 + 23 + 23 + read-write + + + F0NWPRT120 + desc F0NWPRT120 + 24 + 24 + read-write + + + F0NWPRT121 + desc F0NWPRT121 + 25 + 25 + read-write + + + F0NWPRT122 + desc F0NWPRT122 + 26 + 26 + read-write + + + F0NWPRT123 + desc F0NWPRT123 + 27 + 27 + read-write + + + F0NWPRT124 + desc F0NWPRT124 + 28 + 28 + read-write + + + F0NWPRT125 + desc F0NWPRT125 + 29 + 29 + read-write + + + F0NWPRT126 + desc F0NWPRT126 + 30 + 30 + read-write + + + F0NWPRT127 + desc F0NWPRT127 + 31 + 31 + read-write + + + + + F1NWPRT0 + desc F1NWPRT0 + 0x1A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT0 + desc F1NWPRT0 + 0 + 0 + read-write + + + F1NWPRT1 + desc F1NWPRT1 + 1 + 1 + read-write + + + F1NWPRT2 + desc F1NWPRT2 + 2 + 2 + read-write + + + F1NWPRT3 + desc F1NWPRT3 + 3 + 3 + read-write + + + F1NWPRT4 + desc F1NWPRT4 + 4 + 4 + read-write + + + F1NWPRT5 + desc F1NWPRT5 + 5 + 5 + read-write + + + F1NWPRT6 + desc F1NWPRT6 + 6 + 6 + read-write + + + F1NWPRT7 + desc F1NWPRT7 + 7 + 7 + read-write + + + F1NWPRT8 + desc F1NWPRT8 + 8 + 8 + read-write + + + F1NWPRT9 + desc F1NWPRT9 + 9 + 9 + read-write + + + F1NWPRT10 + desc F1NWPRT10 + 10 + 10 + read-write + + + F1NWPRT11 + desc F1NWPRT11 + 11 + 11 + read-write + + + F1NWPRT12 + desc F1NWPRT12 + 12 + 12 + read-write + + + F1NWPRT13 + desc F1NWPRT13 + 13 + 13 + read-write + + + F1NWPRT14 + desc F1NWPRT14 + 14 + 14 + read-write + + + F1NWPRT15 + desc F1NWPRT15 + 15 + 15 + read-write + + + F1NWPRT16 + desc F1NWPRT16 + 16 + 16 + read-write + + + F1NWPRT17 + desc F1NWPRT17 + 17 + 17 + read-write + + + F1NWPRT18 + desc F1NWPRT18 + 18 + 18 + read-write + + + F1NWPRT19 + desc F1NWPRT19 + 19 + 19 + read-write + + + F1NWPRT20 + desc F1NWPRT20 + 20 + 20 + read-write + + + F1NWPRT21 + desc F1NWPRT21 + 21 + 21 + read-write + + + F1NWPRT22 + desc F1NWPRT22 + 22 + 22 + read-write + + + F1NWPRT23 + desc F1NWPRT23 + 23 + 23 + read-write + + + F1NWPRT24 + desc F1NWPRT24 + 24 + 24 + read-write + + + F1NWPRT25 + desc F1NWPRT25 + 25 + 25 + read-write + + + F1NWPRT26 + desc F1NWPRT26 + 26 + 26 + read-write + + + F1NWPRT27 + desc F1NWPRT27 + 27 + 27 + read-write + + + F1NWPRT28 + desc F1NWPRT28 + 28 + 28 + read-write + + + F1NWPRT29 + desc F1NWPRT29 + 29 + 29 + read-write + + + F1NWPRT30 + desc F1NWPRT30 + 30 + 30 + read-write + + + F1NWPRT31 + desc F1NWPRT31 + 31 + 31 + read-write + + + + + F1NWPRT1 + desc F1NWPRT1 + 0x1A4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT32 + desc F1NWPRT32 + 0 + 0 + read-write + + + F1NWPRT33 + desc F1NWPRT33 + 1 + 1 + read-write + + + F1NWPRT34 + desc F1NWPRT34 + 2 + 2 + read-write + + + F1NWPRT35 + desc F1NWPRT35 + 3 + 3 + read-write + + + F1NWPRT36 + desc F1NWPRT36 + 4 + 4 + read-write + + + F1NWPRT37 + desc F1NWPRT37 + 5 + 5 + read-write + + + F1NWPRT38 + desc F1NWPRT38 + 6 + 6 + read-write + + + F1NWPRT39 + desc F1NWPRT39 + 7 + 7 + read-write + + + F1NWPRT40 + desc F1NWPRT40 + 8 + 8 + read-write + + + F1NWPRT41 + desc F1NWPRT41 + 9 + 9 + read-write + + + F1NWPRT42 + desc F1NWPRT42 + 10 + 10 + read-write + + + F1NWPRT43 + desc F1NWPRT43 + 11 + 11 + read-write + + + F1NWPRT44 + desc F1NWPRT44 + 12 + 12 + read-write + + + F1NWPRT45 + desc F1NWPRT45 + 13 + 13 + read-write + + + F1NWPRT46 + desc F1NWPRT46 + 14 + 14 + read-write + + + F1NWPRT47 + desc F1NWPRT47 + 15 + 15 + read-write + + + F1NWPRT48 + desc F1NWPRT48 + 16 + 16 + read-write + + + F1NWPRT49 + desc F1NWPRT49 + 17 + 17 + read-write + + + F1NWPRT50 + desc F1NWPRT50 + 18 + 18 + read-write + + + F1NWPRT51 + desc F1NWPRT51 + 19 + 19 + read-write + + + F1NWPRT52 + desc F1NWPRT52 + 20 + 20 + read-write + + + F1NWPRT53 + desc F1NWPRT53 + 21 + 21 + read-write + + + F1NWPRT54 + desc F1NWPRT54 + 22 + 22 + read-write + + + F1NWPRT55 + desc F1NWPRT55 + 23 + 23 + read-write + + + F1NWPRT56 + desc F1NWPRT56 + 24 + 24 + read-write + + + F1NWPRT57 + desc F1NWPRT57 + 25 + 25 + read-write + + + F1NWPRT58 + desc F1NWPRT58 + 26 + 26 + read-write + + + F1NWPRT59 + desc F1NWPRT59 + 27 + 27 + read-write + + + F1NWPRT60 + desc F1NWPRT60 + 28 + 28 + read-write + + + F1NWPRT61 + desc F1NWPRT61 + 29 + 29 + read-write + + + F1NWPRT62 + desc F1NWPRT62 + 30 + 30 + read-write + + + F1NWPRT63 + desc F1NWPRT63 + 31 + 31 + read-write + + + + + F1NWPRT2 + desc F1NWPRT2 + 0x1A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT64 + desc F1NWPRT64 + 0 + 0 + read-write + + + F1NWPRT65 + desc F1NWPRT65 + 1 + 1 + read-write + + + F1NWPRT66 + desc F1NWPRT66 + 2 + 2 + read-write + + + F1NWPRT67 + desc F1NWPRT67 + 3 + 3 + read-write + + + F1NWPRT68 + desc F1NWPRT68 + 4 + 4 + read-write + + + F1NWPRT69 + desc F1NWPRT69 + 5 + 5 + read-write + + + F1NWPRT70 + desc F1NWPRT70 + 6 + 6 + read-write + + + F1NWPRT71 + desc F1NWPRT71 + 7 + 7 + read-write + + + F1NWPRT72 + desc F1NWPRT72 + 8 + 8 + read-write + + + F1NWPRT73 + desc F1NWPRT73 + 9 + 9 + read-write + + + F1NWPRT74 + desc F1NWPRT74 + 10 + 10 + read-write + + + F1NWPRT75 + desc F1NWPRT75 + 11 + 11 + read-write + + + F1NWPRT76 + desc F1NWPRT76 + 12 + 12 + read-write + + + F1NWPRT77 + desc F1NWPRT77 + 13 + 13 + read-write + + + F1NWPRT78 + desc F1NWPRT78 + 14 + 14 + read-write + + + F1NWPRT79 + desc F1NWPRT79 + 15 + 15 + read-write + + + F1NWPRT80 + desc F1NWPRT80 + 16 + 16 + read-write + + + F1NWPRT81 + desc F1NWPRT81 + 17 + 17 + read-write + + + F1NWPRT82 + desc F1NWPRT82 + 18 + 18 + read-write + + + F1NWPRT83 + desc F1NWPRT83 + 19 + 19 + read-write + + + F1NWPRT84 + desc F1NWPRT84 + 20 + 20 + read-write + + + F1NWPRT85 + desc F1NWPRT85 + 21 + 21 + read-write + + + F1NWPRT86 + desc F1NWPRT86 + 22 + 22 + read-write + + + F1NWPRT87 + desc F1NWPRT87 + 23 + 23 + read-write + + + F1NWPRT88 + desc F1NWPRT88 + 24 + 24 + read-write + + + F1NWPRT89 + desc F1NWPRT89 + 25 + 25 + read-write + + + F1NWPRT90 + desc F1NWPRT90 + 26 + 26 + read-write + + + F1NWPRT91 + desc F1NWPRT91 + 27 + 27 + read-write + + + F1NWPRT92 + desc F1NWPRT92 + 28 + 28 + read-write + + + F1NWPRT93 + desc F1NWPRT93 + 29 + 29 + read-write + + + F1NWPRT94 + desc F1NWPRT94 + 30 + 30 + read-write + + + F1NWPRT95 + desc F1NWPRT95 + 31 + 31 + read-write + + + + + F1NWPRT3 + desc F1NWPRT3 + 0x1AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT96 + desc F1NWPRT96 + 0 + 0 + read-write + + + F1NWPRT97 + desc F1NWPRT97 + 1 + 1 + read-write + + + F1NWPRT98 + desc F1NWPRT98 + 2 + 2 + read-write + + + F1NWPRT99 + desc F1NWPRT99 + 3 + 3 + read-write + + + F1NWPRT100 + desc F1NWPRT100 + 4 + 4 + read-write + + + F1NWPRT101 + desc F1NWPRT101 + 5 + 5 + read-write + + + F1NWPRT102 + desc F1NWPRT102 + 6 + 6 + read-write + + + F1NWPRT103 + desc F1NWPRT103 + 7 + 7 + read-write + + + F1NWPRT104 + desc F1NWPRT104 + 8 + 8 + read-write + + + F1NWPRT105 + desc F1NWPRT105 + 9 + 9 + read-write + + + F1NWPRT106 + desc F1NWPRT106 + 10 + 10 + read-write + + + F1NWPRT107 + desc F1NWPRT107 + 11 + 11 + read-write + + + F1NWPRT108 + desc F1NWPRT108 + 12 + 12 + read-write + + + F1NWPRT109 + desc F1NWPRT109 + 13 + 13 + read-write + + + F1NWPRT110 + desc F1NWPRT110 + 14 + 14 + read-write + + + F1NWPRT111 + desc F1NWPRT111 + 15 + 15 + read-write + + + F1NWPRT112 + desc F1NWPRT112 + 16 + 16 + read-write + + + F1NWPRT113 + desc F1NWPRT113 + 17 + 17 + read-write + + + F1NWPRT114 + desc F1NWPRT114 + 18 + 18 + read-write + + + F1NWPRT115 + desc F1NWPRT115 + 19 + 19 + read-write + + + F1NWPRT116 + desc F1NWPRT116 + 20 + 20 + read-write + + + F1NWPRT117 + desc F1NWPRT117 + 21 + 21 + read-write + + + F1NWPRT118 + desc F1NWPRT118 + 22 + 22 + read-write + + + F1NWPRT119 + desc F1NWPRT119 + 23 + 23 + read-write + + + F1NWPRT120 + desc F1NWPRT120 + 24 + 24 + read-write + + + F1NWPRT121 + desc F1NWPRT121 + 25 + 25 + read-write + + + F1NWPRT122 + desc F1NWPRT122 + 26 + 26 + read-write + + + F1NWPRT123 + desc F1NWPRT123 + 27 + 27 + read-write + + + F1NWPRT124 + desc F1NWPRT124 + 28 + 28 + read-write + + + F1NWPRT125 + desc F1NWPRT125 + 29 + 29 + read-write + + + F1NWPRT126 + desc F1NWPRT126 + 30 + 30 + read-write + + + F1NWPRT127 + desc F1NWPRT127 + 31 + 31 + read-write + + + + + + + EMB0 + desc EMB + 0x40017C00 + + 0x0 + 0x1C + + + + CTL1 + desc CTL1 + 0x0 + 32 + read-write + 0x0 + 0x3CF1FFF + + + CMPEN0 + desc CMPEN0 + 0 + 0 + read-write + + + CMPEN1 + desc CMPEN1 + 1 + 1 + read-write + + + CMPEN2 + desc CMPEN2 + 2 + 2 + read-write + + + CMPEN3 + desc CMPEN3 + 3 + 3 + read-write + + + OSCSTPEN + desc OSCSTPEN + 4 + 4 + read-write + + + PWMSEN0 + desc PWMSEN0 + 5 + 5 + read-write + + + PWMSEN1 + desc PWMSEN1 + 6 + 6 + read-write + + + PWMSEN2 + desc PWMSEN2 + 7 + 7 + read-write + + + PWMSEN3 + desc PWMSEN3 + 8 + 8 + read-write + + + PWMSEN4 + desc PWMSEN4 + 9 + 9 + read-write + + + PWMSEN5 + desc PWMSEN5 + 10 + 10 + read-write + + + PWMSEN6 + desc PWMSEN6 + 11 + 11 + read-write + + + PWMSEN7 + desc PWMSEN7 + 12 + 12 + read-write + + + PORTINEN1 + desc PORTINEN1 + 16 + 16 + read-write + + + PORTINEN2 + desc PORTINEN2 + 17 + 17 + read-write + + + PORTINEN3 + desc PORTINEN3 + 18 + 18 + read-write + + + PORTINEN4 + desc PORTINEN4 + 19 + 19 + read-write + + + INVSEL1 + desc INVSEL1 + 22 + 22 + read-write + + + INVSEL2 + desc INVSEL2 + 23 + 23 + read-write + + + INVSEL3 + desc INVSEL3 + 24 + 24 + read-write + + + INVSEL4 + desc INVSEL4 + 25 + 25 + read-write + + + + + CTL2 + desc CTL2 + 0x4 + 32 + read-write + 0x0 + 0xFFF00FF + + + PWMLV0 + desc PWMLV0 + 0 + 0 + read-write + + + PWMLV1 + desc PWMLV1 + 1 + 1 + read-write + + + PWMLV2 + desc PWMLV2 + 2 + 2 + read-write + + + PWMLV3 + desc PWMLV3 + 3 + 3 + read-write + + + PWMLV4 + desc PWMLV4 + 4 + 4 + read-write + + + PWMLV5 + desc PWMLV5 + 5 + 5 + read-write + + + PWMLV6 + desc PWMLV6 + 6 + 6 + read-write + + + PWMLV7 + desc PWMLV7 + 7 + 7 + read-write + + + NFSEL1 + desc NFSEL1 + 17 + 16 + read-write + + + NFEN1 + desc NFEN1 + 18 + 18 + read-write + + + NFSEL2 + desc NFSEL2 + 20 + 19 + read-write + + + NFEN2 + desc NFEN2 + 21 + 21 + read-write + + + NFSEL3 + desc NFSEL3 + 23 + 22 + read-write + + + NFEN3 + desc NFEN3 + 24 + 24 + read-write + + + NFSEL4 + desc NFSEL4 + 26 + 25 + read-write + + + NFEN4 + desc NFEN4 + 27 + 27 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3CFEE + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + CMPST + desc CMPST + 6 + 6 + read-only + + + OSST + desc OSST + 7 + 7 + read-only + + + PORTINF1 + desc PORTINF1 + 8 + 8 + read-only + + + PORTINF2 + desc PORTINF2 + 9 + 9 + read-only + + + PORTINF3 + desc PORTINF3 + 10 + 10 + read-only + + + PORTINF4 + desc PORTINF4 + 11 + 11 + read-only + + + PORTINST1 + desc PORTINST1 + 14 + 14 + read-only + + + PORTINST2 + desc PORTINST2 + 15 + 15 + read-only + + + PORTINST3 + desc PORTINST3 + 16 + 16 + read-only + + + PORTINST4 + desc PORTINST4 + 17 + 17 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF0E + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + PORTINFCLR1 + desc PORTINFCLR1 + 8 + 8 + write-only + + + PORTINFCLR2 + desc PORTINFCLR2 + 9 + 9 + write-only + + + PORTINFCLR3 + desc PORTINFCLR3 + 10 + 10 + write-only + + + PORTINFCLR4 + desc PORTINFCLR4 + 11 + 11 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF0E + + + PWMSINTEN + desc PWMSINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + PORTINTEN1 + desc PORTINTEN1 + 8 + 8 + read-write + + + PORTINTEN2 + desc PORTINTEN2 + 9 + 9 + read-write + + + PORTINTEN3 + desc PORTINTEN3 + 10 + 10 + read-write + + + PORTINTEN4 + desc PORTINTEN4 + 11 + 11 + read-write + + + + + RLSSEL + desc RLSSEL + 0x18 + 32 + read-write + 0x0 + 0xF0E + + + PWMRSEL + desc PWMRSEL + 1 + 1 + read-write + + + CMPRSEL + desc CMPRSEL + 2 + 2 + read-write + + + OSRSEL + desc OSRSEL + 3 + 3 + read-write + + + PORTINRSEL1 + desc PORTINRSEL1 + 8 + 8 + read-write + + + PORTINRSEL2 + desc PORTINRSEL2 + 9 + 9 + read-write + + + PORTINRSEL3 + desc PORTINRSEL3 + 10 + 10 + read-write + + + PORTINRSEL4 + desc PORTINRSEL4 + 11 + 11 + read-write + + + + + + + EMB1 + desc EMB + 0x40017C20 + + 0x0 + 0x1C + + + + EMB2 + desc EMB + 0x40017C40 + + 0x0 + 0x1C + + + + EMB3 + desc EMB + 0x40017C60 + + 0x0 + 0x1C + + + + EMB4 + desc EMB + 0x40017C80 + + 0x0 + 0x1C + + + + CTL1 + desc CTL1 + 0x0 + 32 + read-write + 0x0 + 0x3CF00FF + + + CMPEN + desc CMPEN + 3 + 0 + read-write + + + OSCSTPEN + desc OSCSTPEN + 4 + 4 + read-write + + + PWMSEN + desc PWMSEN + 7 + 5 + read-write + + + PORTINEN1 + desc PORTINEN1 + 16 + 16 + read-write + + + PORTINEN2 + desc PORTINEN2 + 17 + 17 + read-write + + + PORTINEN3 + desc PORTINEN3 + 18 + 18 + read-write + + + PORTINEN4 + desc PORTINEN4 + 19 + 19 + read-write + + + INVSEL1 + desc INVSEL1 + 22 + 22 + read-write + + + INVSEL2 + desc INVSEL2 + 23 + 23 + read-write + + + INVSEL3 + desc INVSEL3 + 24 + 24 + read-write + + + INVSEL4 + desc INVSEL4 + 25 + 25 + read-write + + + + + CTL2 + desc CTL2 + 0x4 + 32 + read-write + 0x0 + 0xFFF0007 + + + PWMLV + desc PWMLV + 2 + 0 + read-write + + + NFSEL1 + desc NFSEL1 + 17 + 16 + read-write + + + NFEN1 + desc NFEN1 + 18 + 18 + read-write + + + NFSEL2 + desc NFSEL2 + 20 + 19 + read-write + + + NFEN2 + desc NFEN2 + 21 + 21 + read-write + + + NFSEL3 + desc NFSEL3 + 23 + 22 + read-write + + + NFEN3 + desc NFEN3 + 24 + 24 + read-write + + + NFSEL4 + desc NFSEL4 + 26 + 25 + read-write + + + NFEN4 + desc NFEN4 + 27 + 27 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3CFEE + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + CMPST + desc CMPST + 6 + 6 + read-only + + + OSST + desc OSST + 7 + 7 + read-only + + + PORTINF1 + desc PORTINF1 + 8 + 8 + read-only + + + PORTINF2 + desc PORTINF2 + 9 + 9 + read-only + + + PORTINF3 + desc PORTINF3 + 10 + 10 + read-only + + + PORTINF4 + desc PORTINF4 + 11 + 11 + read-only + + + PORTINST1 + desc PORTINST1 + 14 + 14 + read-only + + + PORTINST2 + desc PORTINST2 + 15 + 15 + read-only + + + PORTINST3 + desc PORTINST3 + 16 + 16 + read-only + + + PORTINST4 + desc PORTINST4 + 17 + 17 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF0E + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + PORTINFCLR1 + desc PORTINFCLR1 + 8 + 8 + write-only + + + PORTINFCLR2 + desc PORTINFCLR2 + 9 + 9 + write-only + + + PORTINFCLR3 + desc PORTINFCLR3 + 10 + 10 + write-only + + + PORTINFCLR4 + desc PORTINFCLR4 + 11 + 11 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF0E + + + PWMSINTEN + desc PWMSINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + PORTINTEN1 + desc PORTINTEN1 + 8 + 8 + read-write + + + PORTINTEN2 + desc PORTINTEN2 + 9 + 9 + read-write + + + PORTINTEN3 + desc PORTINTEN3 + 10 + 10 + read-write + + + PORTINTEN4 + desc PORTINTEN4 + 11 + 11 + read-write + + + + + RLSSEL + desc RLSSEL + 0x18 + 32 + read-write + 0x0 + 0xF0E + + + PWMRSEL + desc PWMRSEL + 1 + 1 + read-write + + + CMPRSEL + desc CMPRSEL + 2 + 2 + read-write + + + OSRSEL + desc OSRSEL + 3 + 3 + read-write + + + PORTINRSEL1 + desc PORTINRSEL1 + 8 + 8 + read-write + + + PORTINRSEL2 + desc PORTINRSEL2 + 9 + 9 + read-write + + + PORTINRSEL3 + desc PORTINRSEL3 + 10 + 10 + read-write + + + PORTINRSEL4 + desc PORTINRSEL4 + 11 + 11 + read-write + + + + + + + EMB5 + desc EMB + 0x40017CA0 + + 0x0 + 0x1C + + + + EMB6 + desc EMB + 0x40017CC0 + + 0x0 + 0x1C + + + + ETH + desc ETH + 0x40050000 + + 0x0 + 0x11058 + + + + MAC_IFCONFR + desc MAC_IFCONFR + 0x5410 + 32 + read-write + 0x0 + 0x31 + + + IFSEL + desc IFSEL + 0 + 0 + read-write + + + RCKINV + desc RCKINV + 4 + 4 + read-write + + + TCKINV + desc TCKINV + 5 + 5 + read-write + + + + + MAC_CONFIGR + desc MAC_CONFIGR + 0x10000 + 32 + read-write + 0x8000 + 0x72CF7EFC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + DC + desc DC + 4 + 4 + read-write + + + BL + desc BL + 6 + 5 + read-write + + + ACS + desc ACS + 7 + 7 + read-write + + + DRTY + desc DRTY + 9 + 9 + read-write + + + IPCO + desc IPCO + 10 + 10 + read-write + + + DM + desc DM + 11 + 11 + read-write + + + LM + desc LM + 12 + 12 + read-write + + + DO + desc DO + 13 + 13 + read-write + + + FES + desc FES + 14 + 14 + read-write + + + DCRS + desc DCRS + 16 + 16 + read-write + + + IFG + desc IFG + 19 + 17 + read-write + + + MJB + desc MJB + 22 + 22 + read-write + + + MWD + desc MWD + 23 + 23 + read-write + + + CST + desc CST + 25 + 25 + read-write + + + SAIRC + desc SAIRC + 30 + 28 + read-write + + + + + MAC_FLTCTLR + desc MAC_FLTCTLR + 0x10004 + 32 + read-write + 0x0 + 0x803107FF + + + PR + desc PR + 0 + 0 + read-write + + + HUC + desc HUC + 1 + 1 + read-write + + + HMC + desc HMC + 2 + 2 + read-write + + + DAIF + desc DAIF + 3 + 3 + read-write + + + PMF + desc PMF + 4 + 4 + read-write + + + DBF + desc DBF + 5 + 5 + read-write + + + PCF + desc PCF + 7 + 6 + read-write + + + SAIF + desc SAIF + 8 + 8 + read-write + + + SAF + desc SAF + 9 + 9 + read-write + + + HPF + desc HPF + 10 + 10 + read-write + + + VTFE + desc VTFE + 16 + 16 + read-write + + + IPFE + desc IPFE + 20 + 20 + read-write + + + DNTU + desc DNTU + 21 + 21 + read-write + + + RA + desc RA + 31 + 31 + read-write + + + + + MAC_HASHTHR + desc MAC_HASHTHR + 0x10008 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HTH + desc HTH + 31 + 0 + read-write + + + + + MAC_HASHTLR + desc MAC_HASHTLR + 0x1000C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HTL + desc HTL + 31 + 0 + read-write + + + + + MAC_SMIADDR + desc MAC_SMIADDR + 0x10010 + 32 + read-write + 0x0 + 0xFFFF + + + SMIB + desc SMIB + 0 + 0 + read-write + + + SMIW + desc SMIW + 1 + 1 + read-write + + + SMIC + desc SMIC + 5 + 2 + read-write + + + SMIR + desc SMIR + 10 + 6 + read-write + + + SMIA + desc SMIA + 15 + 11 + read-write + + + + + MAC_SMIDATR + desc MAC_SMIDATR + 0x10014 + 32 + read-write + 0x0 + 0xFFFF + + + SMID + desc SMID + 15 + 0 + read-write + + + + + MAC_FLOCTLR + desc MAC_FLOCTLR + 0x10018 + 32 + read-write + 0x0 + 0xFFFF00BF + + + FCA_BPA + desc FCA_BPA + 0 + 0 + read-write + + + TFE + desc TFE + 1 + 1 + read-write + + + RFE + desc RFE + 2 + 2 + read-write + + + UNP + desc UNP + 3 + 3 + read-write + + + PLT + desc PLT + 5 + 4 + read-write + + + DZPQ + desc DZPQ + 7 + 7 + read-write + + + PAUSET + desc PAUSET + 31 + 16 + read-write + + + + + MAC_VTAFLTR + desc MAC_VTAFLTR + 0x1001C + 32 + read-write + 0x0 + 0x10BFFFF + + + VLFLT + desc VLFLT + 15 + 0 + read-write + + + VTAL + desc VTAL + 16 + 16 + read-write + + + VTIM + desc VTIM + 17 + 17 + read-write + + + VTHM + desc VTHM + 19 + 19 + read-write + + + + + MAC_MACSTSR + desc MAC_MACSTSR + 0x10024 + 32 + read-only + 0x0 + 0x37F0377 + + + MREA + desc MREA + 0 + 0 + read-only + + + MRS + desc MRS + 2 + 1 + read-only + + + RFWA + desc RFWA + 4 + 4 + read-only + + + RFRS + desc RFRS + 6 + 5 + read-only + + + RFFL + desc RFFL + 9 + 8 + read-only + + + MTEA + desc MTEA + 16 + 16 + read-only + + + MTS + desc MTS + 18 + 17 + read-only + + + MTP + desc MTP + 19 + 19 + read-only + + + TFRS + desc TFRS + 21 + 20 + read-only + + + TFWA + desc TFWA + 22 + 22 + read-only + + + TFNE + desc TFNE + 24 + 24 + read-only + + + TFF + desc TFF + 25 + 25 + read-only + + + + + MAC_RTWKFFR + desc MAC_RTWKFFR + 0x10028 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WKUPFRMFT + desc WKUPFRMFT + 31 + 0 + read-write + + + + + MAC_PMTCTLR + desc MAC_PMTCTLR + 0x1002C + 32 + read-write + 0x0 + 0x87000667 + + + PWDN + desc PWDN + 0 + 0 + read-write + + + MPEN + desc MPEN + 1 + 1 + read-write + + + WKEN + desc WKEN + 2 + 2 + read-write + + + MPFR + desc MPFR + 5 + 5 + read-only + + + WKFR + desc WKFR + 6 + 6 + read-only + + + GLUB + desc GLUB + 9 + 9 + read-write + + + RTWKTR + desc RTWKTR + 10 + 10 + read-write + + + RTWKPT + desc RTWKPT + 26 + 24 + read-only + + + RTWKFR + desc RTWKFR + 31 + 31 + read-write + + + + + MAC_INTSTSR + desc MAC_INTSTSR + 0x10038 + 32 + read-only + 0x0 + 0x278 + + + PMTIS + desc PMTIS + 3 + 3 + read-only + + + MMCIS + desc MMCIS + 4 + 4 + read-only + + + MMCRXIS + desc MMCRXIS + 5 + 5 + read-only + + + MMCTXIS + desc MMCTXIS + 6 + 6 + read-only + + + TSPIS + desc TSPIS + 9 + 9 + read-only + + + + + MAC_INTMSKR + desc MAC_INTMSKR + 0x1003C + 32 + read-write + 0x0 + 0x208 + + + PMTIM + desc PMTIM + 3 + 3 + read-write + + + TSPIM + desc TSPIM + 9 + 9 + read-write + + + + + MAC_MACADHR0 + desc MAC_MACADHR0 + 0x10040 + 32 + read-write + 0x8000FFFF + 0x8000FFFF + + + ADDRH0 + desc ADDRH0 + 15 + 0 + read-write + + + AE0 + desc AE0 + 31 + 31 + read-only + + + + + MAC_MACADLR0 + desc MAC_MACADLR0 + 0x10044 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL0 + desc ADDRL0 + 31 + 0 + read-write + + + + + MAC_MACADHR1 + desc MAC_MACADHR1 + 0x10048 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH1 + desc ADDRH1 + 15 + 0 + read-write + + + MBC1 + desc MBC1 + 29 + 24 + read-write + + + SA1 + desc SA1 + 30 + 30 + read-write + + + AE1 + desc AE1 + 31 + 31 + read-write + + + + + MAC_MACADLR1 + desc MAC_MACADLR1 + 0x1004C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL1 + desc ADDRL1 + 31 + 0 + read-write + + + + + MAC_MACADHR2 + desc MAC_MACADHR2 + 0x10050 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH2 + desc ADDRH2 + 15 + 0 + read-write + + + MBC2 + desc MBC2 + 29 + 24 + read-write + + + SA2 + desc SA2 + 30 + 30 + read-write + + + AE2 + desc AE2 + 31 + 31 + read-write + + + + + MAC_MACADLR2 + desc MAC_MACADLR2 + 0x10054 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL2 + desc ADDRL2 + 31 + 0 + read-write + + + + + MAC_MACADHR3 + desc MAC_MACADHR3 + 0x10058 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH3 + desc ADDRH3 + 15 + 0 + read-write + + + MBC3 + desc MBC3 + 29 + 24 + read-write + + + SA3 + desc SA3 + 30 + 30 + read-write + + + AE3 + desc AE3 + 31 + 31 + read-write + + + + + MAC_MACADLR3 + desc MAC_MACADLR3 + 0x1005C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL3 + desc ADDRL3 + 31 + 0 + read-write + + + + + MAC_MACADHR4 + desc MAC_MACADHR4 + 0x10060 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH4 + desc ADDRH4 + 15 + 0 + read-write + + + MBC4 + desc MBC4 + 29 + 24 + read-write + + + SA4 + desc SA4 + 30 + 30 + read-write + + + AE4 + desc AE4 + 31 + 31 + read-write + + + + + MAC_MACADLR4 + desc MAC_MACADLR4 + 0x10064 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL4 + desc ADDRL4 + 31 + 0 + read-write + + + + + MMC_MMCCTLR + desc MMC_MMCCTLR + 0x10100 + 32 + read-write + 0x0 + 0x3F + + + CRST + desc CRST + 0 + 0 + read-write + + + COS + desc COS + 1 + 1 + read-write + + + ROR + desc ROR + 2 + 2 + read-write + + + MCF + desc MCF + 3 + 3 + read-write + + + MCPSET + desc MCPSET + 4 + 4 + read-write + + + MCPSEL + desc MCPSEL + 5 + 5 + read-write + + + + + MMC_REVSTSR + desc MMC_REVSTSR + 0x10104 + 32 + read-only + 0x0 + 0x10E00F8 + + + RXBGIS + desc RXBGIS + 3 + 3 + read-only + + + RXMGIS + desc RXMGIS + 4 + 4 + read-only + + + RXCEIS + desc RXCEIS + 5 + 5 + read-only + + + RXAEIS + desc RXAEIS + 6 + 6 + read-only + + + RXREIS + desc RXREIS + 7 + 7 + read-only + + + RXUGIS + desc RXUGIS + 17 + 17 + read-only + + + RXLEIS + desc RXLEIS + 18 + 18 + read-only + + + RXOEIS + desc RXOEIS + 19 + 19 + read-only + + + + + MMC_TRSSTSR + desc MMC_TRSSTSR + 0x10108 + 32 + read-only + 0x0 + 0x16F000C + + + TXBGIS + desc TXBGIS + 2 + 2 + read-only + + + TXMGIS + desc TXMGIS + 3 + 3 + read-only + + + TXDEEIS + desc TXDEEIS + 16 + 16 + read-only + + + TXLCEIS + desc TXLCEIS + 17 + 17 + read-only + + + TXECEIS + desc TXECEIS + 18 + 18 + read-only + + + TXCAEIS + desc TXCAEIS + 19 + 19 + read-only + + + TXUGIS + desc TXUGIS + 21 + 21 + read-only + + + TXEDEIS + desc TXEDEIS + 22 + 22 + read-only + + + + + MMC_RITCTLR + desc MMC_RITCTLR + 0x1010C + 32 + read-write + 0x0 + 0x10E00F8 + + + RXBGIM + desc RXBGIM + 3 + 3 + read-write + + + RXMGIM + desc RXMGIM + 4 + 4 + read-write + + + RXCEIM + desc RXCEIM + 5 + 5 + read-write + + + RXAEIM + desc RXAEIM + 6 + 6 + read-write + + + RXREIM + desc RXREIM + 7 + 7 + read-write + + + RXUGIM + desc RXUGIM + 17 + 17 + read-write + + + RXLEIM + desc RXLEIM + 18 + 18 + read-write + + + RXOEIM + desc RXOEIM + 19 + 19 + read-write + + + + + MMC_TITCTLR + desc MMC_TITCTLR + 0x10110 + 32 + read-write + 0x0 + 0x16F000C + + + TXBGIM + desc TXBGIM + 2 + 2 + read-write + + + TXMGIM + desc TXMGIM + 3 + 3 + read-write + + + TXDEEIM + desc TXDEEIM + 16 + 16 + read-write + + + TXLCEIM + desc TXLCEIM + 17 + 17 + read-write + + + TXECEIM + desc TXECEIM + 18 + 18 + read-write + + + TXCAEIM + desc TXCAEIM + 19 + 19 + read-write + + + TXUGIM + desc TXUGIM + 21 + 21 + read-write + + + TXEDEIM + desc TXEDEIM + 22 + 22 + read-write + + + + + MMC_TXBRGFR + desc MMC_TXBRGFR + 0x1011C + 32 + read-only + 0x0 + 0xFFFF + + + TXBRGCNT + desc TXBRGCNT + 15 + 0 + read-only + + + + + MMC_TXMUGFR + desc MMC_TXMUGFR + 0x10120 + 32 + read-only + 0x0 + 0xFFFF + + + TXMUGCNT + desc TXMUGCNT + 15 + 0 + read-only + + + + + MMC_TXDEEFR + desc MMC_TXDEEFR + 0x10154 + 32 + read-only + 0x0 + 0xFFFF + + + TXDEECNT + desc TXDEECNT + 15 + 0 + read-only + + + + + MMC_TXLCEFR + desc MMC_TXLCEFR + 0x10158 + 32 + read-only + 0x0 + 0xFFFF + + + TXLCECNT + desc TXLCECNT + 15 + 0 + read-only + + + + + MMC_TXECEFR + desc MMC_TXECEFR + 0x1015C + 32 + read-only + 0x0 + 0xFFFF + + + TXECECNT + desc TXECECNT + 15 + 0 + read-only + + + + + MMC_TXCAEFR + desc MMC_TXCAEFR + 0x10160 + 32 + read-only + 0x0 + 0xFFFF + + + TXCAECNT + desc TXCAECNT + 15 + 0 + read-only + + + + + MMC_TXUNGFR + desc MMC_TXUNGFR + 0x10168 + 32 + read-only + 0x0 + 0xFFFF + + + TXUNGCNT + desc TXUNGCNT + 15 + 0 + read-only + + + + + MMC_TXEDEFR + desc MMC_TXEDEFR + 0x1016C + 32 + read-only + 0x0 + 0xFFFF + + + TXEDECNT + desc TXEDECNT + 15 + 0 + read-only + + + + + MMC_RXBRGFR + desc MMC_RXBRGFR + 0x1018C + 32 + read-only + 0x0 + 0xFFFF + + + RXBRGCNT + desc RXBRGCNT + 15 + 0 + read-only + + + + + MMC_RXMUGFR + desc MMC_RXMUGFR + 0x10190 + 32 + read-only + 0x0 + 0xFFFF + + + RXMUGCNT + desc RXMUGCNT + 15 + 0 + read-only + + + + + MMC_RXCREFR + desc MMC_RXCREFR + 0x10194 + 32 + read-only + 0x0 + 0xFFFF + + + RXCRECNT + desc RXCRECNT + 15 + 0 + read-only + + + + + MMC_RXALEFR + desc MMC_RXALEFR + 0x10198 + 32 + read-only + 0x0 + 0xFFFF + + + RXALECNT + desc RXALECNT + 15 + 0 + read-only + + + + + MMC_RXRUEFR + desc MMC_RXRUEFR + 0x1019C + 32 + read-only + 0x0 + 0xFFFF + + + RXRUECNT + desc RXRUECNT + 15 + 0 + read-only + + + + + MMC_RXUNGFR + desc MMC_RXUNGFR + 0x101C4 + 32 + read-only + 0x0 + 0xFFFF + + + RXUNGCNT + desc RXUNGCNT + 15 + 0 + read-only + + + + + MMC_RXLEEFR + desc MMC_RXLEEFR + 0x101C8 + 32 + read-only + 0x0 + 0xFFFF + + + RXLEECNT + desc RXLEECNT + 15 + 0 + read-only + + + + + MMC_RXOREFR + desc MMC_RXOREFR + 0x101CC + 32 + read-only + 0x0 + 0xFFFF + + + RXORECNT + desc RXORECNT + 15 + 0 + read-only + + + + + MAC_L34CTLR + desc MAC_L34CTLR + 0x10400 + 32 + read-write + 0x0 + 0x13DFFFD + + + L3PEN + desc L3PEN + 0 + 0 + read-write + + + L3SAM + desc L3SAM + 2 + 2 + read-write + + + L3SAIM + desc L3SAIM + 3 + 3 + read-write + + + L3DAM + desc L3DAM + 4 + 4 + read-write + + + L3DAIM + desc L3DAIM + 5 + 5 + read-write + + + L3HSBM + desc L3HSBM + 10 + 6 + read-write + + + L3HDBM + desc L3HDBM + 15 + 11 + read-write + + + L4PEN + desc L4PEN + 16 + 16 + read-write + + + L4SPM + desc L4SPM + 18 + 18 + read-write + + + L4SPIM + desc L4SPIM + 19 + 19 + read-write + + + L4DPM + desc L4DPM + 20 + 20 + read-write + + + L4DPIM + desc L4DPIM + 21 + 21 + read-write + + + + + MAC_L4PORTR + desc MAC_L4PORTR + 0x10404 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L4SPVAL + desc L4SPVAL + 15 + 0 + read-write + + + L4DPVAL + desc L4DPVAL + 31 + 16 + read-write + + + + + MAC_L3ADDRR0 + desc MAC_L3ADDRR0 + 0x10410 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR0 + desc L3ADDR0 + 31 + 0 + read-write + + + + + MAC_L3ADDRR1 + desc MAC_L3ADDRR1 + 0x10414 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR2 + desc L3ADDR2 + 31 + 0 + read-write + + + + + MAC_L3ADDRR2 + desc MAC_L3ADDRR2 + 0x10418 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR2 + desc L3ADDR2 + 31 + 0 + read-write + + + + + MAC_L3ADDRR3 + desc MAC_L3ADDRR3 + 0x1041C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR3 + desc L3ADDR3 + 31 + 0 + read-write + + + + + MAC_VTACTLR + desc MAC_VTACTLR + 0x10584 + 32 + read-write + 0x0 + 0x107FFFF + + + VLANV + desc VLANV + 15 + 0 + read-write + + + VLANC + desc VLANC + 17 + 16 + read-write + + + VLANS + desc VLANS + 18 + 18 + read-write + + + + + MAC_VLAHTBR + desc MAC_VLAHTBR + 0x10588 + 32 + read-write + 0x0 + 0xFFFF + + + VLHT + desc VLHT + 15 + 0 + read-write + + + + + PTP_TSPCTLR + desc PTP_TSPCTLR + 0x10700 + 32 + read-write + 0x2000 + 0x107FF3F + + + TSPEN + desc TSPEN + 0 + 0 + read-write + + + TSPUPSEL + desc TSPUPSEL + 1 + 1 + read-write + + + TSPINI + desc TSPINI + 2 + 2 + read-write + + + TSPUP + desc TSPUP + 3 + 3 + read-write + + + TSPINT + desc TSPINT + 4 + 4 + read-write + + + TSPADUP + desc TSPADUP + 5 + 5 + read-write + + + TSPEALL + desc TSPEALL + 8 + 8 + read-write + + + TSPSSR + desc TSPSSR + 9 + 9 + read-write + + + TSPVER + desc TSPVER + 10 + 10 + read-write + + + TSPOVETH + desc TSPOVETH + 11 + 11 + read-write + + + TSPOVIPV6 + desc TSPOVIPV6 + 12 + 12 + read-write + + + TSPOVIPV4 + desc TSPOVIPV4 + 13 + 13 + read-write + + + TSPMTSEL + desc TSPMTSEL + 17 + 14 + read-write + + + TSPADF + desc TSPADF + 18 + 18 + read-write + + + + + PTP_TSPNSAR + desc PTP_TSPNSAR + 0x10704 + 32 + read-write + 0x0 + 0xFF + + + TSPNSEADD + desc TSPNSEADD + 7 + 0 + read-write + + + + + PTP_TMSSECR + desc PTP_TMSSECR + 0x10708 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TSPSYSSEC + desc TSPSYSSEC + 31 + 0 + read-only + + + + + PTP_TMSNSER + desc PTP_TMSNSER + 0x1070C + 32 + read-only + 0x0 + 0x7FFFFFFF + + + TSPSYSNSEC + desc TSPSYSNSEC + 30 + 0 + read-only + + + + + PTP_TMUSECR + desc PTP_TMUSECR + 0x10710 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPUPSEC + desc TSPUPSEC + 31 + 0 + read-write + + + + + PTP_TMUNSER + desc PTP_TMUNSER + 0x10714 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPUPNSEC + desc TSPUPNSEC + 30 + 0 + read-write + + + TSPUPNS + desc TSPUPNS + 31 + 31 + read-write + + + + + PTP_TSPADDR + desc PTP_TSPADDR + 0x10718 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPADD + desc TSPADD + 31 + 0 + read-write + + + + + PTP_TMTSECR0 + desc PTP_TMTSECR0 + 0x1071C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPTAGSEC0 + desc TSPTAGSEC0 + 31 + 0 + read-write + + + + + PTP_TMTNSER0 + desc PTP_TMTNSER0 + 0x10720 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + TSPTAGNSEC0 + desc TSPTAGNSEC0 + 30 + 0 + read-write + + + + + PTP_TSPSTSR + desc PTP_TSPSTSR + 0x10728 + 32 + read-only + 0x0 + 0x3B + + + TSOVF + desc TSOVF + 0 + 0 + read-only + + + TSTAR0 + desc TSTAR0 + 1 + 1 + read-only + + + TSERR0 + desc TSERR0 + 3 + 3 + read-only + + + TSTAR1 + desc TSTAR1 + 4 + 4 + read-only + + + TSERR1 + desc TSERR1 + 5 + 5 + read-only + + + + + PTP_PPSCTLR + desc PTP_PPSCTLR + 0x1072C + 32 + read-write + 0x0 + 0x677F + + + PPSFRE0 + desc PPSFRE0 + 3 + 0 + read-write + + + PPSOMD + desc PPSOMD + 4 + 4 + read-write + + + TT0SEL + desc TT0SEL + 6 + 5 + read-write + + + PPSFRE1 + desc PPSFRE1 + 10 + 8 + read-write + + + TT1SEL + desc TT1SEL + 14 + 13 + read-write + + + + + PTP_TMTSECR1 + desc PTP_TMTSECR1 + 0x10780 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPTAGSEC1 + desc TSPTAGSEC1 + 31 + 0 + read-write + + + + + PTP_TMTNSER1 + desc PTP_TMTNSER1 + 0x10784 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + TSPTAGNSEC1 + desc TSPTAGNSEC1 + 30 + 0 + read-write + + + + + DMA_BUSMODR + desc DMA_BUSMODR + 0x11000 + 32 + read-write + 0x20101 + 0xFFFFFFF + + + SWR + desc SWR + 0 + 0 + read-write + + + DMAA + desc DMAA + 1 + 1 + read-write + + + DSL + desc DSL + 6 + 2 + read-write + + + DSEN + desc DSEN + 7 + 7 + read-write + + + TPBL + desc TPBL + 13 + 8 + read-write + + + PRAT + desc PRAT + 15 + 14 + read-write + + + FBST + desc FBST + 16 + 16 + read-write + + + RPBL + desc RPBL + 22 + 17 + read-write + + + SPBL + desc SPBL + 23 + 23 + read-write + + + M8PBL + desc M8PBL + 24 + 24 + read-write + + + AAL + desc AAL + 25 + 25 + read-write + + + MBST + desc MBST + 26 + 26 + read-write + + + TXPR + desc TXPR + 27 + 27 + read-write + + + + + DMA_TXPOLLR + desc DMA_TXPOLLR + 0x11004 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TXPOLL + desc TXPOLL + 31 + 0 + read-write + + + + + DMA_RXPOLLR + desc DMA_RXPOLLR + 0x11008 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RXPOLL + desc RXPOLL + 31 + 0 + read-write + + + + + DMA_RXDLADR + desc DMA_RXDLADR + 0x1100C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RXDLAD + desc RXDLAD + 31 + 0 + read-write + + + + + DMA_TXDLADR + desc DMA_TXDLADR + 0x11010 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TXDLAD + desc TXDLAD + 31 + 0 + read-write + + + + + DMA_DMASTSR + desc DMA_DMASTSR + 0x11014 + 32 + read-write + 0x0 + 0x3BFFE7FF + + + TIS + desc TIS + 0 + 0 + read-write + + + TSS + desc TSS + 1 + 1 + read-write + + + TUS + desc TUS + 2 + 2 + read-write + + + TJS + desc TJS + 3 + 3 + read-write + + + OVS + desc OVS + 4 + 4 + read-write + + + UNS + desc UNS + 5 + 5 + read-write + + + RIS + desc RIS + 6 + 6 + read-write + + + RUS + desc RUS + 7 + 7 + read-write + + + RSS + desc RSS + 8 + 8 + read-write + + + RWS + desc RWS + 9 + 9 + read-write + + + ETS + desc ETS + 10 + 10 + read-write + + + FBS + desc FBS + 13 + 13 + read-write + + + ERS + desc ERS + 14 + 14 + read-write + + + AIS + desc AIS + 15 + 15 + read-write + + + NIS + desc NIS + 16 + 16 + read-write + + + RSTS + desc RSTS + 19 + 17 + read-only + + + TSTS + desc TSTS + 22 + 20 + read-only + + + EBUS + desc EBUS + 25 + 23 + read-only + + + MMCS + desc MMCS + 27 + 27 + read-only + + + PMTS + desc PMTS + 28 + 28 + read-only + + + PTPS + desc PTPS + 29 + 29 + read-only + + + + + DMA_OPRMODR + desc DMA_OPRMODR + 0x11018 + 32 + read-write + 0x0 + 0x731E0FE + + + STR + desc STR + 1 + 1 + read-write + + + OSF + desc OSF + 2 + 2 + read-write + + + RTC + desc RTC + 4 + 3 + read-write + + + DGF + desc DGF + 5 + 5 + read-write + + + FUF + desc FUF + 6 + 6 + read-write + + + FEF + desc FEF + 7 + 7 + read-write + + + STT + desc STT + 13 + 13 + read-write + + + TTC + desc TTC + 16 + 14 + read-write + + + FTF + desc FTF + 20 + 20 + read-write + + + TSF + desc TSF + 21 + 21 + read-write + + + DFRF + desc DFRF + 24 + 24 + read-write + + + RSF + desc RSF + 25 + 25 + read-write + + + DTCOE + desc DTCOE + 26 + 26 + read-write + + + + + DMA_INTENAR + desc DMA_INTENAR + 0x1101C + 32 + read-write + 0x0 + 0x101E7FF + + + TIE + desc TIE + 0 + 0 + read-write + + + TSE + desc TSE + 1 + 1 + read-write + + + TUE + desc TUE + 2 + 2 + read-write + + + TJE + desc TJE + 3 + 3 + read-write + + + OVE + desc OVE + 4 + 4 + read-write + + + UNE + desc UNE + 5 + 5 + read-write + + + RIE + desc RIE + 6 + 6 + read-write + + + RUE + desc RUE + 7 + 7 + read-write + + + RSE + desc RSE + 8 + 8 + read-write + + + RWE + desc RWE + 9 + 9 + read-write + + + ETE + desc ETE + 10 + 10 + read-write + + + FBE + desc FBE + 13 + 13 + read-write + + + ERE + desc ERE + 14 + 14 + read-write + + + AIE + desc AIE + 15 + 15 + read-write + + + NIE + desc NIE + 16 + 16 + read-write + + + + + DMA_RFRCNTR + desc DMA_RFRCNTR + 0x11020 + 32 + read-only + 0x0 + 0x1FFFFFFF + + + UNACNT + desc UNACNT + 15 + 0 + read-only + + + UNAOVF + desc UNAOVF + 16 + 16 + read-only + + + OVFCNT + desc OVFCNT + 27 + 17 + read-only + + + OVFOVF + desc OVFOVF + 28 + 28 + read-only + + + + + DMA_REVWDTR + desc DMA_REVWDTR + 0x11024 + 32 + read-write + 0x0 + 0xFF + + + RIWT + desc RIWT + 7 + 0 + read-write + + + + + DMA_CHTXDER + desc DMA_CHTXDER + 0x11048 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHTXDE + desc CHTXDE + 31 + 0 + read-only + + + + + DMA_CHRXDER + desc DMA_CHRXDER + 0x1104C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHRXDE + desc CHRXDE + 31 + 0 + read-only + + + + + DMA_CHTXBFR + desc DMA_CHTXBFR + 0x11050 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHTXBF + desc CHTXBF + 31 + 0 + read-only + + + + + DMA_CHRXBFR + desc DMA_CHRXBFR + 0x11054 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHRXBF + desc CHRXBF + 31 + 0 + read-only + + + + + + + FCM + desc FCM + 0x40048400 + + 0x0 + 0x24 + + + + LVR + desc LVR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + LVR + desc LVR + 15 + 0 + read-write + + + + + UVR + desc UVR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + UVR + desc UVR + 15 + 0 + read-write + + + + + CNTR + desc CNTR + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + CNTR + desc CNTR + 15 + 0 + read-only + + + + + STR + desc STR + 0xC + 32 + read-write + 0x0 + 0x1 + + + START + desc START + 0 + 0 + read-write + + + + + MCCR + desc MCCR + 0x10 + 32 + read-write + 0x0 + 0xF3 + + + MDIVS + desc MDIVS + 1 + 0 + read-write + + + MCKS + desc MCKS + 7 + 4 + read-write + + + + + RCCR + desc RCCR + 0x14 + 32 + read-write + 0x0 + 0xB3FB + + + RDIVS + desc RDIVS + 1 + 0 + read-write + + + RCKS + desc RCKS + 6 + 3 + read-write + + + INEXS + desc INEXS + 7 + 7 + read-write + + + DNFS + desc DNFS + 9 + 8 + read-write + + + EDGES + desc EDGES + 13 + 12 + read-write + + + EXREFE + desc EXREFE + 15 + 15 + read-write + + + + + RIER + desc RIER + 0x18 + 32 + read-write + 0x0 + 0x97 + + + ERRIE + desc ERRIE + 0 + 0 + read-write + + + MENDIE + desc MENDIE + 1 + 1 + read-write + + + OVFIE + desc OVFIE + 2 + 2 + read-write + + + ERRINTRS + desc ERRINTRS + 4 + 4 + read-write + + + ERRE + desc ERRE + 7 + 7 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-only + 0x0 + 0x7 + + + ERRF + desc ERRF + 0 + 0 + read-only + + + MENDF + desc MENDF + 1 + 1 + read-only + + + OVF + desc OVF + 2 + 2 + read-only + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0x7 + + + ERRFCLR + desc ERRFCLR + 0 + 0 + write-only + + + MENDFCLR + desc MENDFCLR + 1 + 1 + write-only + + + OVFCLR + desc OVFCLR + 2 + 2 + write-only + + + + + + + FMAC1 + desc FMAC + 0x40058000 + + 0x0 + 0x64 + + + + ENR + desc ENR + 0x0 + 32 + read-write + 0x0 + 0x1 + + + FMACEN + desc FMACEN + 0 + 0 + read-write + + + + + CTR + desc CTR + 0x4 + 32 + read-write + 0x10 + 0x1F1F + + + STAGE_NUM + desc STAGE_NUM + 4 + 0 + read-write + + + SHIFT + desc SHIFT + 12 + 8 + read-write + + + + + IER + desc IER + 0x8 + 32 + read-write + 0x0 + 0x1 + + + INTEN + desc INTEN + 0 + 0 + read-write + + + + + DTR + desc DTR + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + DIN + desc DIN + 15 + 0 + read-write + + + + + RTR0 + desc RTR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RTR1 + desc RTR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + STR + desc STR + 0x18 + 32 + read-write + 0x0 + 0x80000000 + + + READY + desc READY + 31 + 31 + read-write + + + + + COR0 + desc COR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR1 + desc COR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR2 + desc COR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR3 + desc COR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR4 + desc COR4 + 0x30 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR5 + desc COR5 + 0x34 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR6 + desc COR6 + 0x38 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR7 + desc COR7 + 0x3C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR8 + desc COR8 + 0x40 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR9 + desc COR9 + 0x44 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR10 + desc COR10 + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR11 + desc COR11 + 0x4C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR12 + desc COR12 + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR13 + desc COR13 + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR14 + desc COR14 + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR15 + desc COR15 + 0x5C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR16 + desc COR16 + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + + + FMAC2 + desc FMAC + 0x40058400 + + 0x0 + 0x64 + + + + FMAC3 + desc FMAC + 0x40058800 + + 0x0 + 0x64 + + + + FMAC4 + desc FMAC + 0x40058C00 + + 0x0 + 0x64 + + + + GPIO + desc GPIO + 0x40053800 + + 0x0 + 0x638 + + + + PIDRA + desc PIDRA + 0x0 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRA + desc PODRA + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERA + desc POERA + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRA + desc POSRA + 0x8 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRA + desc PORRA + 0xA + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRA + desc POTRA + 0xC + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRB + desc PIDRB + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRB + desc PODRB + 0x14 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERB + desc POERB + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRB + desc POSRB + 0x18 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRB + desc PORRB + 0x1A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRB + desc POTRB + 0x1C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRC + desc PIDRC + 0x20 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRC + desc PODRC + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERC + desc POERC + 0x26 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRC + desc POSRC + 0x28 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRC + desc PORRC + 0x2A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRC + desc POTRC + 0x2C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRD + desc PIDRD + 0x30 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRD + desc PODRD + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERD + desc POERD + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRD + desc POSRD + 0x38 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRD + desc PORRD + 0x3A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRD + desc POTRD + 0x3C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRE + desc PIDRE + 0x40 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRE + desc PODRE + 0x44 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERE + desc POERE + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRE + desc POSRE + 0x48 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRE + desc PORRE + 0x4A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRE + desc POTRE + 0x4C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRF + desc PIDRF + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRF + desc PODRF + 0x54 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERF + desc POERF + 0x56 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRF + desc POSRF + 0x58 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRF + desc PORRF + 0x5A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRF + desc POTRF + 0x5C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRG + desc PIDRG + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRG + desc PODRG + 0x64 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERG + desc POERG + 0x66 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRG + desc POSRG + 0x68 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRG + desc PORRG + 0x6A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRG + desc POTRG + 0x6C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRH + desc PIDRH + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRH + desc PODRH + 0x74 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERH + desc POERH + 0x76 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRH + desc POSRH + 0x78 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRH + desc PORRH + 0x7A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRH + desc POTRH + 0x7C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRI + desc PIDRI + 0x80 + 16 + read-only + 0x0 + 0x3FFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + + + PODRI + desc PODRI + 0x84 + 16 + read-write + 0x0 + 0x3FFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + + + POERI + desc POERI + 0x86 + 16 + read-write + 0x0 + 0x3FFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + + + POSRI + desc POSRI + 0x88 + 16 + write-only + 0x0 + 0x3FFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + + + PORRI + desc PORRI + 0x8A + 16 + write-only + 0x0 + 0x3FFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + + + POTRI + desc POTRI + 0x8C + 16 + write-only + 0x0 + 0x3FFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + + + PSPCR + desc PSPCR + 0x3F4 + 16 + read-write + 0x1F + 0x1F + + + SPFE + desc SPFE + 4 + 0 + read-write + + + + + PCCR + desc PCCR + 0x3F8 + 16 + read-write + 0x1000 + 0x703F + + + BFSEL + desc BFSEL + 5 + 0 + read-write + + + RDWT + desc RDWT + 14 + 12 + read-write + + + + + PINAER + desc PINAER + 0x3FA + 16 + read-write + 0x0 + 0x1FF + + + PINAE + desc PINAE + 8 + 0 + read-write + + + + + PWPR + desc PWPR + 0x3FC + 16 + read-write + 0x0 + 0xFF01 + + + WE + desc WE + 0 + 0 + read-write + + + WP + desc WP + 15 + 8 + write-only + + + + + PCRA0 + desc PCRA0 + 0x400 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA0 + desc PFSRA0 + 0x402 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA1 + desc PCRA1 + 0x404 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA1 + desc PFSRA1 + 0x406 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA2 + desc PCRA2 + 0x408 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA2 + desc PFSRA2 + 0x40A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA3 + desc PCRA3 + 0x40C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA3 + desc PFSRA3 + 0x40E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA4 + desc PCRA4 + 0x410 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA4 + desc PFSRA4 + 0x412 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA5 + desc PCRA5 + 0x414 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA5 + desc PFSRA5 + 0x416 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA6 + desc PCRA6 + 0x418 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA6 + desc PFSRA6 + 0x41A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA7 + desc PCRA7 + 0x41C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA7 + desc PFSRA7 + 0x41E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA8 + desc PCRA8 + 0x420 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA8 + desc PFSRA8 + 0x422 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA9 + desc PCRA9 + 0x424 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA9 + desc PFSRA9 + 0x426 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA10 + desc PCRA10 + 0x428 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA10 + desc PFSRA10 + 0x42A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA11 + desc PCRA11 + 0x42C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA11 + desc PFSRA11 + 0x42E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA12 + desc PCRA12 + 0x430 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA12 + desc PFSRA12 + 0x432 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA13 + desc PCRA13 + 0x434 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA13 + desc PFSRA13 + 0x436 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA14 + desc PCRA14 + 0x438 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA14 + desc PFSRA14 + 0x43A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA15 + desc PCRA15 + 0x43C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA15 + desc PFSRA15 + 0x43E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB0 + desc PCRB0 + 0x440 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB0 + desc PFSRB0 + 0x442 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB1 + desc PCRB1 + 0x444 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB1 + desc PFSRB1 + 0x446 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB2 + desc PCRB2 + 0x448 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB2 + desc PFSRB2 + 0x44A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB3 + desc PCRB3 + 0x44C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB3 + desc PFSRB3 + 0x44E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB4 + desc PCRB4 + 0x450 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB4 + desc PFSRB4 + 0x452 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB5 + desc PCRB5 + 0x454 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB5 + desc PFSRB5 + 0x456 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB6 + desc PCRB6 + 0x458 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB6 + desc PFSRB6 + 0x45A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB7 + desc PCRB7 + 0x45C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB7 + desc PFSRB7 + 0x45E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB8 + desc PCRB8 + 0x460 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB8 + desc PFSRB8 + 0x462 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB9 + desc PCRB9 + 0x464 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB9 + desc PFSRB9 + 0x466 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB10 + desc PCRB10 + 0x468 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB10 + desc PFSRB10 + 0x46A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB11 + desc PCRB11 + 0x46C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB11 + desc PFSRB11 + 0x46E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB12 + desc PCRB12 + 0x470 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB12 + desc PFSRB12 + 0x472 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB13 + desc PCRB13 + 0x474 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB13 + desc PFSRB13 + 0x476 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB14 + desc PCRB14 + 0x478 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB14 + desc PFSRB14 + 0x47A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB15 + desc PCRB15 + 0x47C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB15 + desc PFSRB15 + 0x47E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC0 + desc PCRC0 + 0x480 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC0 + desc PFSRC0 + 0x482 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC1 + desc PCRC1 + 0x484 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC1 + desc PFSRC1 + 0x486 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC2 + desc PCRC2 + 0x488 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC2 + desc PFSRC2 + 0x48A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC3 + desc PCRC3 + 0x48C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC3 + desc PFSRC3 + 0x48E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC4 + desc PCRC4 + 0x490 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC4 + desc PFSRC4 + 0x492 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC5 + desc PCRC5 + 0x494 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC5 + desc PFSRC5 + 0x496 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC6 + desc PCRC6 + 0x498 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC6 + desc PFSRC6 + 0x49A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC7 + desc PCRC7 + 0x49C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC7 + desc PFSRC7 + 0x49E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC8 + desc PCRC8 + 0x4A0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC8 + desc PFSRC8 + 0x4A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC9 + desc PCRC9 + 0x4A4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC9 + desc PFSRC9 + 0x4A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC10 + desc PCRC10 + 0x4A8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC10 + desc PFSRC10 + 0x4AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC11 + desc PCRC11 + 0x4AC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC11 + desc PFSRC11 + 0x4AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC12 + desc PCRC12 + 0x4B0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC12 + desc PFSRC12 + 0x4B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC13 + desc PCRC13 + 0x4B4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC13 + desc PFSRC13 + 0x4B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC14 + desc PCRC14 + 0x4B8 + 16 + read-write + 0x8100 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC14 + desc PFSRC14 + 0x4BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC15 + desc PCRC15 + 0x4BC + 16 + read-write + 0x8100 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC15 + desc PFSRC15 + 0x4BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD0 + desc PCRD0 + 0x4C0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD0 + desc PFSRD0 + 0x4C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD1 + desc PCRD1 + 0x4C4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD1 + desc PFSRD1 + 0x4C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD2 + desc PCRD2 + 0x4C8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD2 + desc PFSRD2 + 0x4CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD3 + desc PCRD3 + 0x4CC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD3 + desc PFSRD3 + 0x4CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD4 + desc PCRD4 + 0x4D0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD4 + desc PFSRD4 + 0x4D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD5 + desc PCRD5 + 0x4D4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD5 + desc PFSRD5 + 0x4D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD6 + desc PCRD6 + 0x4D8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD6 + desc PFSRD6 + 0x4DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD7 + desc PCRD7 + 0x4DC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD7 + desc PFSRD7 + 0x4DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD8 + desc PCRD8 + 0x4E0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD8 + desc PFSRD8 + 0x4E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD9 + desc PCRD9 + 0x4E4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD9 + desc PFSRD9 + 0x4E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD10 + desc PCRD10 + 0x4E8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD10 + desc PFSRD10 + 0x4EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD11 + desc PCRD11 + 0x4EC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD11 + desc PFSRD11 + 0x4EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD12 + desc PCRD12 + 0x4F0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD12 + desc PFSRD12 + 0x4F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD13 + desc PCRD13 + 0x4F4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD13 + desc PFSRD13 + 0x4F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD14 + desc PCRD14 + 0x4F8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD14 + desc PFSRD14 + 0x4FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD15 + desc PCRD15 + 0x4FC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD15 + desc PFSRD15 + 0x4FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE0 + desc PCRE0 + 0x500 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE0 + desc PFSRE0 + 0x502 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE1 + desc PCRE1 + 0x504 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE1 + desc PFSRE1 + 0x506 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE2 + desc PCRE2 + 0x508 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE2 + desc PFSRE2 + 0x50A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE3 + desc PCRE3 + 0x50C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE3 + desc PFSRE3 + 0x50E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE4 + desc PCRE4 + 0x510 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE4 + desc PFSRE4 + 0x512 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE5 + desc PCRE5 + 0x514 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE5 + desc PFSRE5 + 0x516 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE6 + desc PCRE6 + 0x518 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE6 + desc PFSRE6 + 0x51A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE7 + desc PCRE7 + 0x51C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE7 + desc PFSRE7 + 0x51E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE8 + desc PCRE8 + 0x520 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE8 + desc PFSRE8 + 0x522 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE9 + desc PCRE9 + 0x524 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE9 + desc PFSRE9 + 0x526 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE10 + desc PCRE10 + 0x528 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE10 + desc PFSRE10 + 0x52A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE11 + desc PCRE11 + 0x52C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE11 + desc PFSRE11 + 0x52E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE12 + desc PCRE12 + 0x530 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE12 + desc PFSRE12 + 0x532 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE13 + desc PCRE13 + 0x534 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE13 + desc PFSRE13 + 0x536 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE14 + desc PCRE14 + 0x538 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE14 + desc PFSRE14 + 0x53A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE15 + desc PCRE15 + 0x53C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE15 + desc PFSRE15 + 0x53E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF0 + desc PCRF0 + 0x540 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF0 + desc PFSRF0 + 0x542 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF1 + desc PCRF1 + 0x544 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF1 + desc PFSRF1 + 0x546 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF2 + desc PCRF2 + 0x548 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF2 + desc PFSRF2 + 0x54A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF3 + desc PCRF3 + 0x54C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF3 + desc PFSRF3 + 0x54E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF4 + desc PCRF4 + 0x550 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF4 + desc PFSRF4 + 0x552 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF5 + desc PCRF5 + 0x554 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF5 + desc PFSRF5 + 0x556 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF6 + desc PCRF6 + 0x558 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF6 + desc PFSRF6 + 0x55A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF7 + desc PCRF7 + 0x55C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF7 + desc PFSRF7 + 0x55E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF8 + desc PCRF8 + 0x560 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF8 + desc PFSRF8 + 0x562 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF9 + desc PCRF9 + 0x564 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF9 + desc PFSRF9 + 0x566 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF10 + desc PCRF10 + 0x568 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF10 + desc PFSRF10 + 0x56A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF11 + desc PCRF11 + 0x56C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF11 + desc PFSRF11 + 0x56E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF12 + desc PCRF12 + 0x570 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF12 + desc PFSRF12 + 0x572 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF13 + desc PCRF13 + 0x574 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF13 + desc PFSRF13 + 0x576 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF14 + desc PCRF14 + 0x578 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF14 + desc PFSRF14 + 0x57A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF15 + desc PCRF15 + 0x57C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF15 + desc PFSRF15 + 0x57E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG0 + desc PCRG0 + 0x580 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG0 + desc PFSRG0 + 0x582 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG1 + desc PCRG1 + 0x584 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG1 + desc PFSRG1 + 0x586 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG2 + desc PCRG2 + 0x588 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG2 + desc PFSRG2 + 0x58A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG3 + desc PCRG3 + 0x58C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG3 + desc PFSRG3 + 0x58E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG4 + desc PCRG4 + 0x590 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG4 + desc PFSRG4 + 0x592 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG5 + desc PCRG5 + 0x594 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG5 + desc PFSRG5 + 0x596 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG6 + desc PCRG6 + 0x598 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG6 + desc PFSRG6 + 0x59A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG7 + desc PCRG7 + 0x59C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG7 + desc PFSRG7 + 0x59E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG8 + desc PCRG8 + 0x5A0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG8 + desc PFSRG8 + 0x5A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG9 + desc PCRG9 + 0x5A4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG9 + desc PFSRG9 + 0x5A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG10 + desc PCRG10 + 0x5A8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG10 + desc PFSRG10 + 0x5AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG11 + desc PCRG11 + 0x5AC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG11 + desc PFSRG11 + 0x5AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG12 + desc PCRG12 + 0x5B0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG12 + desc PFSRG12 + 0x5B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG13 + desc PCRG13 + 0x5B4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG13 + desc PFSRG13 + 0x5B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG14 + desc PCRG14 + 0x5B8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG14 + desc PFSRG14 + 0x5BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG15 + desc PCRG15 + 0x5BC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG15 + desc PFSRG15 + 0x5BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH0 + desc PCRH0 + 0x5C0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH0 + desc PFSRH0 + 0x5C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH1 + desc PCRH1 + 0x5C4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH1 + desc PFSRH1 + 0x5C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH2 + desc PCRH2 + 0x5C8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH2 + desc PFSRH2 + 0x5CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH3 + desc PCRH3 + 0x5CC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH3 + desc PFSRH3 + 0x5CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH4 + desc PCRH4 + 0x5D0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH4 + desc PFSRH4 + 0x5D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH5 + desc PCRH5 + 0x5D4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH5 + desc PFSRH5 + 0x5D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH6 + desc PCRH6 + 0x5D8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH6 + desc PFSRH6 + 0x5DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH7 + desc PCRH7 + 0x5DC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH7 + desc PFSRH7 + 0x5DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH8 + desc PCRH8 + 0x5E0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH8 + desc PFSRH8 + 0x5E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH9 + desc PCRH9 + 0x5E4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH9 + desc PFSRH9 + 0x5E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH10 + desc PCRH10 + 0x5E8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH10 + desc PFSRH10 + 0x5EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH11 + desc PCRH11 + 0x5EC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH11 + desc PFSRH11 + 0x5EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH12 + desc PCRH12 + 0x5F0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH12 + desc PFSRH12 + 0x5F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH13 + desc PCRH13 + 0x5F4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH13 + desc PFSRH13 + 0x5F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH14 + desc PCRH14 + 0x5F8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH14 + desc PFSRH14 + 0x5FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH15 + desc PCRH15 + 0x5FC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH15 + desc PFSRH15 + 0x5FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI0 + desc PCRI0 + 0x600 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI0 + desc PFSRI0 + 0x602 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI1 + desc PCRI1 + 0x604 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI1 + desc PFSRI1 + 0x606 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI2 + desc PCRI2 + 0x608 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI2 + desc PFSRI2 + 0x60A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI3 + desc PCRI3 + 0x60C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI3 + desc PFSRI3 + 0x60E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI4 + desc PCRI4 + 0x610 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI4 + desc PFSRI4 + 0x612 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI5 + desc PCRI5 + 0x614 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI5 + desc PFSRI5 + 0x616 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI6 + desc PCRI6 + 0x618 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI6 + desc PFSRI6 + 0x61A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI7 + desc PCRI7 + 0x61C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI7 + desc PFSRI7 + 0x61E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI8 + desc PCRI8 + 0x620 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI8 + desc PFSRI8 + 0x622 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI9 + desc PCRI9 + 0x624 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI9 + desc PFSRI9 + 0x626 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI10 + desc PCRI10 + 0x628 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI10 + desc PFSRI10 + 0x62A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI11 + desc PCRI11 + 0x62C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI11 + desc PFSRI11 + 0x62E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI12 + desc PCRI12 + 0x630 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI12 + desc PFSRI12 + 0x632 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI13 + desc PCRI13 + 0x634 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI13 + desc PFSRI13 + 0x636 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + + + HASH + desc HASH + 0x40008400 + + 0x0 + 0x80 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0xC777 + + + START + desc START + 0 + 0 + read-write + + + FST_GRP + desc FST_GRP + 1 + 1 + read-write + + + KMSG_END + desc KMSG_END + 2 + 2 + read-write + + + MODE + desc MODE + 5 + 4 + read-write + + + LKEY + desc LKEY + 6 + 6 + read-write + + + BUSY + desc BUSY + 8 + 8 + read-write + + + CYC_END + desc CYC_END + 9 + 9 + read-write + + + HMAC_END + desc HMAC_END + 10 + 10 + read-write + + + HCIE + desc HCIE + 14 + 14 + read-write + + + HEIE + desc HEIE + 15 + 15 + read-write + + + + + HR7 + desc HR7 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR6 + desc HR6 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR5 + desc HR5 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR4 + desc HR4 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR3 + desc HR3 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR2 + desc HR2 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR1 + desc HR1 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR0 + desc HR0 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR15 + desc DR15 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR14 + desc DR14 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR13 + desc DR13 + 0x48 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR12 + desc DR12 + 0x4C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR11 + desc DR11 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR10 + desc DR10 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR9 + desc DR9 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR8 + desc DR8 + 0x5C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR7 + desc DR7 + 0x60 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR6 + desc DR6 + 0x64 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR5 + desc DR5 + 0x68 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR4 + desc DR4 + 0x6C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x70 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR0 + desc DR0 + 0x7C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + HRPWM + desc HRPWM + 0x4003C000 + + 0x0 + 0x58 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR5 + desc CR5 + 0x10 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR6 + desc CR6 + 0x14 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR7 + desc CR7 + 0x18 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR8 + desc CR8 + 0x1C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR9 + desc CR9 + 0x20 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR10 + desc CR10 + 0x24 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR11 + desc CR11 + 0x28 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR12 + desc CR12 + 0x2C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR13 + desc CR13 + 0x30 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR14 + desc CR14 + 0x34 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR15 + desc CR15 + 0x38 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR16 + desc CR16 + 0x3C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CALCR0 + desc CALCR0 + 0x50 + 32 + read-write + 0x0 + 0x90FF + + + CALCODE + desc CALCODE + 7 + 0 + read-write + + + ENDF + desc ENDF + 12 + 12 + read-write + + + CALEN + desc CALEN + 15 + 15 + read-write + + + + + CALCR1 + desc CALCR1 + 0x54 + 32 + read-write + 0x0 + 0x90FF + + + CALCODE + desc CALCODE + 7 + 0 + read-write + + + ENDF + desc ENDF + 12 + 12 + read-write + + + CALEN + desc CALEN + 15 + 15 + read-write + + + + + + + I2C1 + desc I2C + 0x4004E000 + + 0x0 + 0x34 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x40 + 0x87DF + + + PE + desc PE + 0 + 0 + read-write + + + SMBUS + desc SMBUS + 1 + 1 + read-write + + + SMBALRTEN + desc SMBALRTEN + 2 + 2 + read-write + + + SMBDEFAULTEN + desc SMBDEFAULTEN + 3 + 3 + read-write + + + SMBHOSTEN + desc SMBHOSTEN + 4 + 4 + read-write + + + GCEN + desc GCEN + 6 + 6 + read-write + + + RESTART + desc RESTART + 7 + 7 + read-write + + + START + desc START + 8 + 8 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + ACK + desc ACK + 10 + 10 + read-write + + + SWRST + desc SWRST + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF052DF + + + STARTIE + desc STARTIE + 0 + 0 + read-write + + + SLADDR0IE + desc SLADDR0IE + 1 + 1 + read-write + + + SLADDR1IE + desc SLADDR1IE + 2 + 2 + read-write + + + TENDIE + desc TENDIE + 3 + 3 + read-write + + + STOPIE + desc STOPIE + 4 + 4 + read-write + + + RFULLIE + desc RFULLIE + 6 + 6 + read-write + + + TEMPTYIE + desc TEMPTYIE + 7 + 7 + read-write + + + ARLOIE + desc ARLOIE + 9 + 9 + read-write + + + NACKIE + desc NACKIE + 12 + 12 + read-write + + + TMOUTIE + desc TMOUTIE + 14 + 14 + read-write + + + GENCALLIE + desc GENCALLIE + 20 + 20 + read-write + + + SMBDEFAULTIE + desc SMBDEFAULTIE + 21 + 21 + read-write + + + SMBHOSTIE + desc SMBHOSTIE + 22 + 22 + read-write + + + SMBALRTIE + desc SMBALRTIE + 23 + 23 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x6 + 0x87 + + + TMOUTEN + desc TMOUTEN + 0 + 0 + read-write + + + LTMOUT + desc LTMOUT + 1 + 1 + read-write + + + HTMOUT + desc HTMOUT + 2 + 2 + read-write + + + FACKEN + desc FACKEN + 7 + 7 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x300307 + 0x400 + + + BUSWAIT + desc BUSWAIT + 10 + 10 + read-write + + + + + SLR0 + desc SLR0 + 0x10 + 32 + read-write + 0x1000 + 0x93FF + + + SLADDR0 + desc SLADDR0 + 9 + 0 + read-write + + + SLADDR0EN + desc SLADDR0EN + 12 + 12 + read-write + + + ADDRMOD0 + desc ADDRMOD0 + 15 + 15 + read-write + + + + + SLR1 + desc SLR1 + 0x14 + 32 + read-write + 0x0 + 0x93FF + + + SLADDR1 + desc SLADDR1 + 9 + 0 + read-write + + + SLADDR1EN + desc SLADDR1EN + 12 + 12 + read-write + + + ADDRMOD1 + desc ADDRMOD1 + 15 + 15 + read-write + + + + + SLTR + desc SLTR + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TOUTLOW + desc TOUTLOW + 15 + 0 + read-write + + + TOUTHIGH + desc TOUTHIGH + 31 + 16 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-write + 0x0 + 0xF756DF + + + STARTF + desc STARTF + 0 + 0 + read-write + + + SLADDR0F + desc SLADDR0F + 1 + 1 + read-write + + + SLADDR1F + desc SLADDR1F + 2 + 2 + read-write + + + TENDF + desc TENDF + 3 + 3 + read-write + + + STOPF + desc STOPF + 4 + 4 + read-write + + + RFULLF + desc RFULLF + 6 + 6 + read-write + + + TEMPTYF + desc TEMPTYF + 7 + 7 + read-write + + + ARLOF + desc ARLOF + 9 + 9 + read-write + + + ACKRF + desc ACKRF + 10 + 10 + read-write + + + NACKF + desc NACKF + 12 + 12 + read-write + + + TMOUTF + desc TMOUTF + 14 + 14 + read-write + + + MSL + desc MSL + 16 + 16 + read-write + + + BUSY + desc BUSY + 17 + 17 + read-write + + + TRA + desc TRA + 18 + 18 + read-write + + + GENCALLF + desc GENCALLF + 20 + 20 + read-write + + + SMBDEFAULTF + desc SMBDEFAULTF + 21 + 21 + read-write + + + SMBHOSTF + desc SMBHOSTF + 22 + 22 + read-write + + + SMBALRTF + desc SMBALRTF + 23 + 23 + read-write + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0xF052DF + + + STARTFCLR + desc STARTFCLR + 0 + 0 + write-only + + + SLADDR0FCLR + desc SLADDR0FCLR + 1 + 1 + write-only + + + SLADDR1FCLR + desc SLADDR1FCLR + 2 + 2 + write-only + + + TENDFCLR + desc TENDFCLR + 3 + 3 + write-only + + + STOPFCLR + desc STOPFCLR + 4 + 4 + write-only + + + RFULLFCLR + desc RFULLFCLR + 6 + 6 + write-only + + + TEMPTYFCLR + desc TEMPTYFCLR + 7 + 7 + write-only + + + ARLOFCLR + desc ARLOFCLR + 9 + 9 + write-only + + + NACKFCLR + desc NACKFCLR + 12 + 12 + write-only + + + TMOUTFCLR + desc TMOUTFCLR + 14 + 14 + write-only + + + GENCALLFCLR + desc GENCALLFCLR + 20 + 20 + write-only + + + SMBDEFAULTFCLR + desc SMBDEFAULTFCLR + 21 + 21 + write-only + + + SMBHOSTFCLR + desc SMBHOSTFCLR + 22 + 22 + write-only + + + SMBALRTFCLR + desc SMBALRTFCLR + 23 + 23 + write-only + + + + + DTR + desc DTR + 0x24 + 8 + write-only + 0xFF + 0xFF + + + DT + desc DT + 7 + 0 + write-only + + + + + DRR + desc DRR + 0x28 + 8 + read-only + 0x0 + 0xFF + + + DR + desc DR + 7 + 0 + read-only + + + + + CCR + desc CCR + 0x2C + 32 + read-write + 0x1F1F + 0x71F1F + + + SLOWW + desc SLOWW + 4 + 0 + read-write + + + SHIGHW + desc SHIGHW + 12 + 8 + read-write + + + FREQ + desc FREQ + 18 + 16 + read-write + + + + + FLTR + desc FLTR + 0x30 + 32 + read-write + 0x10 + 0x33 + + + DNF + desc DNF + 1 + 0 + read-write + + + DNFEN + desc DNFEN + 4 + 4 + read-write + + + ANFEN + desc ANFEN + 5 + 5 + read-write + + + + + + + I2C2 + desc I2C + 0x4004E400 + + 0x0 + 0x34 + + + + I2C3 + desc I2C + 0x4004E800 + + 0x0 + 0x34 + + + + I2C4 + desc I2C + 0x4004EC00 + + 0x0 + 0x34 + + + + I2C5 + desc I2C + 0x4004F000 + + 0x0 + 0x34 + + + + I2C6 + desc I2C + 0x4004F400 + + 0x0 + 0x34 + + + + I2S1 + desc I2S + 0x4001E000 + + 0x0 + 0x1C + + + + CTRL + desc CTRL + 0x0 + 32 + read-write + 0x2200 + 0x1FF77FF + + + TXE + desc TXE + 0 + 0 + read-write + + + TXIE + desc TXIE + 1 + 1 + read-write + + + RXE + desc RXE + 2 + 2 + read-write + + + RXIE + desc RXIE + 3 + 3 + read-write + + + EIE + desc EIE + 4 + 4 + read-write + + + WMS + desc WMS + 5 + 5 + read-write + + + ODD + desc ODD + 6 + 6 + read-write + + + MCKOE + desc MCKOE + 7 + 7 + read-write + + + TXBIRQWL + desc TXBIRQWL + 10 + 8 + read-write + + + RXBIRQWL + desc RXBIRQWL + 14 + 12 + read-write + + + FIFOR + desc FIFOR + 16 + 16 + read-write + + + CODECRC + desc CODECRC + 17 + 17 + read-write + + + I2SPLLSEL + desc I2SPLLSEL + 18 + 18 + read-write + + + SDOE + desc SDOE + 19 + 19 + read-write + + + LRCKOE + desc LRCKOE + 20 + 20 + read-write + + + CKOE + desc CKOE + 21 + 21 + read-write + + + DUPLEX + desc DUPLEX + 22 + 22 + read-write + + + CLKSEL + desc CLKSEL + 23 + 23 + read-write + + + SRST + desc SRST + 24 + 24 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-only + 0x14 + 0x3F + + + TXBA + desc TXBA + 0 + 0 + read-only + + + RXBA + desc RXBA + 1 + 1 + read-only + + + TXBE + desc TXBE + 2 + 2 + read-only + + + TXBF + desc TXBF + 3 + 3 + read-only + + + RXBE + desc RXBE + 4 + 4 + read-only + + + RXBF + desc RXBF + 5 + 5 + read-only + + + + + ER + desc ER + 0x8 + 32 + read-write + 0x0 + 0x3 + + + TXERR + desc TXERR + 0 + 0 + read-write + + + RXERR + desc RXERR + 1 + 1 + read-write + + + + + CFGR + desc CFGR + 0xC + 32 + read-write + 0x0 + 0x3F + + + I2SSTD + desc I2SSTD + 1 + 0 + read-write + + + DATLEN + desc DATLEN + 3 + 2 + read-write + + + CHLEN + desc CHLEN + 4 + 4 + read-write + + + PCMSYNC + desc PCMSYNC + 5 + 5 + read-write + + + + + TXBUF + desc TXBUF + 0x10 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + RXBUF + desc RXBUF + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PR + desc PR + 0x18 + 32 + read-write + 0x2 + 0xFF + + + I2SDIV + desc I2SDIV + 7 + 0 + read-write + + + + + + + I2S2 + desc I2S + 0x4001E400 + + 0x0 + 0x1C + + + + I2S3 + desc I2S + 0x40022000 + + 0x0 + 0x1C + + + + I2S4 + desc I2S + 0x40022400 + + 0x0 + 0x1C + + + + ICG + desc ICG + 0x00000400 + + 0x0 + 0x10 + + + + ICG0 + desc ICG0 + 0x0 + 32 + read-only + 0xFFFFFFFF + 0x1FFF1FFF + + + SWDTAUTS + desc SWDTAUTS + 0 + 0 + read-only + + + SWDTITS + desc SWDTITS + 1 + 1 + read-only + + + SWDTPERI + desc SWDTPERI + 3 + 2 + read-only + + + SWDTCKS + desc SWDTCKS + 7 + 4 + read-only + + + SWDTWDPT + desc SWDTWDPT + 11 + 8 + read-only + + + SWDTSLPOFF + desc SWDTSLPOFF + 12 + 12 + read-only + + + WDTAUTS + desc WDTAUTS + 16 + 16 + read-only + + + WDTITS + desc WDTITS + 17 + 17 + read-only + + + WDTPERI + desc WDTPERI + 19 + 18 + read-only + + + WDTCKS + desc WDTCKS + 23 + 20 + read-only + + + WDTWDPT + desc WDTWDPT + 27 + 24 + read-only + + + WDTSLPOFF + desc WDTSLPOFF + 28 + 28 + read-only + + + + + ICG1 + desc ICG1 + 0x4 + 32 + read-only + 0xFFFFFFFF + 0x70101 + + + HRCFREQSEL + desc HRCFREQSEL + 0 + 0 + read-only + + + HRCSTOP + desc HRCSTOP + 8 + 8 + read-only + + + BOR_LEV + desc BOR_LEV + 17 + 16 + read-only + + + BORDIS + desc BORDIS + 18 + 18 + read-only + + + + + ICG2 + desc ICG2 + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFF + + + BGO1M + desc BGO1M + 23 + 0 + read-only + + + + + ICG3 + desc ICG3 + 0xC + 32 + read-only + 0xFFFFFFFF + 0xFFFF + + + DBUSPRT + desc DBUSPRT + 15 + 0 + read-only + + + + + + + INTC + desc INTC + 0x40051000 + + 0x0 + 0x2B4 + + + + NOCCR + desc NOCCR + 0x0 + 32 + read-write + 0x0 + 0x3000 + + + NOCSEL + desc NOCSEL + 13 + 12 + read-write + + + + + NMIENR + desc NMIENR + 0x4 + 32 + read-write + 0x0 + 0xF2E + + + SWDTENR + desc SWDTENR + 1 + 1 + read-write + + + PVD1ENR + desc PVD1ENR + 2 + 2 + read-write + + + PVD2ENR + desc PVD2ENR + 3 + 3 + read-write + + + XTALSTPENR + desc XTALSTPENR + 5 + 5 + read-write + + + REPENR + desc REPENR + 8 + 8 + read-write + + + RECCENR + desc RECCENR + 9 + 9 + read-write + + + BUSMENR + desc BUSMENR + 10 + 10 + read-write + + + WDTENR + desc WDTENR + 11 + 11 + read-write + + + + + NMIFR + desc NMIFR + 0x8 + 32 + read-write + 0x0 + 0xF2E + + + SWDTFR + desc SWDTFR + 1 + 1 + read-write + + + PVD1FR + desc PVD1FR + 2 + 2 + read-write + + + PVD2FR + desc PVD2FR + 3 + 3 + read-write + + + XTALSTPFR + desc XTALSTPFR + 5 + 5 + read-write + + + REPFR + desc REPFR + 8 + 8 + read-write + + + RECCFR + desc RECCFR + 9 + 9 + read-write + + + BUSMFR + desc BUSMFR + 10 + 10 + read-write + + + WDTFR + desc WDTFR + 11 + 11 + read-write + + + + + NMICFR + desc NMICFR + 0xC + 32 + read-write + 0x0 + 0xF2E + + + SWDTCFR + desc SWDTCFR + 1 + 1 + read-write + + + PVD1CFR + desc PVD1CFR + 2 + 2 + read-write + + + PVD2CFR + desc PVD2CFR + 3 + 3 + read-write + + + XTALSTPCFR + desc XTALSTPCFR + 5 + 5 + read-write + + + REPCFR + desc REPCFR + 8 + 8 + read-write + + + RECCCFR + desc RECCCFR + 9 + 9 + read-write + + + BUSMCFR + desc BUSMCFR + 10 + 10 + read-write + + + WDTCFR + desc WDTCFR + 11 + 11 + read-write + + + + + EIRQCR0 + desc EIRQCR0 + 0x10 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR1 + desc EIRQCR1 + 0x14 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR2 + desc EIRQCR2 + 0x18 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR3 + desc EIRQCR3 + 0x1C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR4 + desc EIRQCR4 + 0x20 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR5 + desc EIRQCR5 + 0x24 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR6 + desc EIRQCR6 + 0x28 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR7 + desc EIRQCR7 + 0x2C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR8 + desc EIRQCR8 + 0x30 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR9 + desc EIRQCR9 + 0x34 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR10 + desc EIRQCR10 + 0x38 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR11 + desc EIRQCR11 + 0x3C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR12 + desc EIRQCR12 + 0x40 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR13 + desc EIRQCR13 + 0x44 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR14 + desc EIRQCR14 + 0x48 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR15 + desc EIRQCR15 + 0x4C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + WUPEN + desc WUPEN + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + EIRQWUEN + desc EIRQWUEN + 15 + 0 + read-write + + + SWDTWUEN + desc SWDTWUEN + 16 + 16 + read-write + + + PVD1WUEN + desc PVD1WUEN + 17 + 17 + read-write + + + PVD2WUEN + desc PVD2WUEN + 18 + 18 + read-write + + + CMPWUEN + desc CMPWUEN + 19 + 19 + read-write + + + WKTMWUEN + desc WKTMWUEN + 20 + 20 + read-write + + + RTCALMWUEN + desc RTCALMWUEN + 21 + 21 + read-write + + + RTCPRDWUEN + desc RTCPRDWUEN + 22 + 22 + read-write + + + TMR0GCMWUEN + desc TMR0GCMWUEN + 23 + 23 + read-write + + + TMR2GCMWUEN + desc TMR2GCMWUEN + 24 + 24 + read-write + + + TMR2OVFWUEN + desc TMR2OVFWUEN + 25 + 25 + read-write + + + RXWUEN + desc RXWUEN + 26 + 26 + read-write + + + USHWUEN + desc USHWUEN + 27 + 27 + read-write + + + USFWUEN + desc USFWUEN + 28 + 28 + read-write + + + ETHWUEN + desc ETHWUEN + 29 + 29 + read-write + + + + + EIRQFR + desc EIRQFR + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQFR0 + desc EIRQFR0 + 0 + 0 + read-write + + + EIRQFR1 + desc EIRQFR1 + 1 + 1 + read-write + + + EIRQFR2 + desc EIRQFR2 + 2 + 2 + read-write + + + EIRQFR3 + desc EIRQFR3 + 3 + 3 + read-write + + + EIRQFR4 + desc EIRQFR4 + 4 + 4 + read-write + + + EIRQFR5 + desc EIRQFR5 + 5 + 5 + read-write + + + EIRQFR6 + desc EIRQFR6 + 6 + 6 + read-write + + + EIRQFR7 + desc EIRQFR7 + 7 + 7 + read-write + + + EIRQFR8 + desc EIRQFR8 + 8 + 8 + read-write + + + EIRQFR9 + desc EIRQFR9 + 9 + 9 + read-write + + + EIRQFR10 + desc EIRQFR10 + 10 + 10 + read-write + + + EIRQFR11 + desc EIRQFR11 + 11 + 11 + read-write + + + EIRQFR12 + desc EIRQFR12 + 12 + 12 + read-write + + + EIRQFR13 + desc EIRQFR13 + 13 + 13 + read-write + + + EIRQFR14 + desc EIRQFR14 + 14 + 14 + read-write + + + EIRQFR15 + desc EIRQFR15 + 15 + 15 + read-write + + + + + EIRQCFR + desc EIRQCFR + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQCFR0 + desc EIRQCFR0 + 0 + 0 + read-write + + + EIRQCFR1 + desc EIRQCFR1 + 1 + 1 + read-write + + + EIRQCFR2 + desc EIRQCFR2 + 2 + 2 + read-write + + + EIRQCFR3 + desc EIRQCFR3 + 3 + 3 + read-write + + + EIRQCFR4 + desc EIRQCFR4 + 4 + 4 + read-write + + + EIRQCFR5 + desc EIRQCFR5 + 5 + 5 + read-write + + + EIRQCFR6 + desc EIRQCFR6 + 6 + 6 + read-write + + + EIRQCFR7 + desc EIRQCFR7 + 7 + 7 + read-write + + + EIRQCFR8 + desc EIRQCFR8 + 8 + 8 + read-write + + + EIRQCFR9 + desc EIRQCFR9 + 9 + 9 + read-write + + + EIRQCFR10 + desc EIRQCFR10 + 10 + 10 + read-write + + + EIRQCFR11 + desc EIRQCFR11 + 11 + 11 + read-write + + + EIRQCFR12 + desc EIRQCFR12 + 12 + 12 + read-write + + + EIRQCFR13 + desc EIRQCFR13 + 13 + 13 + read-write + + + EIRQCFR14 + desc EIRQCFR14 + 14 + 14 + read-write + + + EIRQCFR15 + desc EIRQCFR15 + 15 + 15 + read-write + + + + + SEL0 + desc SEL0 + 0x5C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL1 + desc SEL1 + 0x60 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL2 + desc SEL2 + 0x64 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL3 + desc SEL3 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL4 + desc SEL4 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL5 + desc SEL5 + 0x70 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL6 + desc SEL6 + 0x74 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL7 + desc SEL7 + 0x78 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL8 + desc SEL8 + 0x7C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL9 + desc SEL9 + 0x80 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL10 + desc SEL10 + 0x84 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL11 + desc SEL11 + 0x88 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL12 + desc SEL12 + 0x8C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL13 + desc SEL13 + 0x90 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL14 + desc SEL14 + 0x94 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL15 + desc SEL15 + 0x98 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL16 + desc SEL16 + 0x9C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL17 + desc SEL17 + 0xA0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL18 + desc SEL18 + 0xA4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL19 + desc SEL19 + 0xA8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL20 + desc SEL20 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL21 + desc SEL21 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL22 + desc SEL22 + 0xB4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL23 + desc SEL23 + 0xB8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL24 + desc SEL24 + 0xBC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL25 + desc SEL25 + 0xC0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL26 + desc SEL26 + 0xC4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL27 + desc SEL27 + 0xC8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL28 + desc SEL28 + 0xCC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL29 + desc SEL29 + 0xD0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL30 + desc SEL30 + 0xD4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL31 + desc SEL31 + 0xD8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL32 + desc SEL32 + 0xDC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL46 + desc SEL46 + 0x114 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL47 + desc SEL47 + 0x118 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL48 + desc SEL48 + 0x11C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL49 + desc SEL49 + 0x120 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL50 + desc SEL50 + 0x124 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL51 + desc SEL51 + 0x128 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL52 + desc SEL52 + 0x12C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL53 + desc SEL53 + 0x130 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL54 + desc SEL54 + 0x134 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL55 + desc SEL55 + 0x138 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL56 + desc SEL56 + 0x13C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL57 + desc SEL57 + 0x140 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL58 + desc SEL58 + 0x144 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL59 + desc SEL59 + 0x148 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL60 + desc SEL60 + 0x14C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL61 + desc SEL61 + 0x150 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL62 + desc SEL62 + 0x154 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL63 + desc SEL63 + 0x158 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL64 + desc SEL64 + 0x15C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL65 + desc SEL65 + 0x160 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL66 + desc SEL66 + 0x164 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL67 + desc SEL67 + 0x168 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL68 + desc SEL68 + 0x16C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL69 + desc SEL69 + 0x170 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL70 + desc SEL70 + 0x174 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL71 + desc SEL71 + 0x178 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL72 + desc SEL72 + 0x17C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL73 + desc SEL73 + 0x180 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL74 + desc SEL74 + 0x184 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL75 + desc SEL75 + 0x188 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL76 + desc SEL76 + 0x18C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL77 + desc SEL77 + 0x190 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL78 + desc SEL78 + 0x194 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL79 + desc SEL79 + 0x198 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL80 + desc SEL80 + 0x19C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL81 + desc SEL81 + 0x1A0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL82 + desc SEL82 + 0x1A4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL83 + desc SEL83 + 0x1A8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL84 + desc SEL84 + 0x1AC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL85 + desc SEL85 + 0x1B0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL86 + desc SEL86 + 0x1B4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL87 + desc SEL87 + 0x1B8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL88 + desc SEL88 + 0x1BC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL89 + desc SEL89 + 0x1C0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL90 + desc SEL90 + 0x1C4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL91 + desc SEL91 + 0x1C8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL92 + desc SEL92 + 0x1CC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL93 + desc SEL93 + 0x1D0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL94 + desc SEL94 + 0x1D4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL95 + desc SEL95 + 0x1D8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL96 + desc SEL96 + 0x1DC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL97 + desc SEL97 + 0x1E0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL98 + desc SEL98 + 0x1E4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL99 + desc SEL99 + 0x1E8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL100 + desc SEL100 + 0x1EC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL101 + desc SEL101 + 0x1F0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL102 + desc SEL102 + 0x1F4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL103 + desc SEL103 + 0x1F8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL104 + desc SEL104 + 0x1FC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL105 + desc SEL105 + 0x200 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL106 + desc SEL106 + 0x204 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL107 + desc SEL107 + 0x208 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL108 + desc SEL108 + 0x20C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL109 + desc SEL109 + 0x210 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL110 + desc SEL110 + 0x214 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL111 + desc SEL111 + 0x218 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL112 + desc SEL112 + 0x21C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL113 + desc SEL113 + 0x220 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL114 + desc SEL114 + 0x224 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL115 + desc SEL115 + 0x228 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL122 + desc SEL122 + 0x244 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL123 + desc SEL123 + 0x248 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL124 + desc SEL124 + 0x24C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL125 + desc SEL125 + 0x250 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL126 + desc SEL126 + 0x254 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL127 + desc SEL127 + 0x258 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + VSSEL128 + desc VSSEL128 + 0x25C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL129 + desc VSSEL129 + 0x260 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL130 + desc VSSEL130 + 0x264 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL131 + desc VSSEL131 + 0x268 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL132 + desc VSSEL132 + 0x26C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL133 + desc VSSEL133 + 0x270 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL134 + desc VSSEL134 + 0x274 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL135 + desc VSSEL135 + 0x278 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL136 + desc VSSEL136 + 0x27C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL137 + desc VSSEL137 + 0x280 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL138 + desc VSSEL138 + 0x284 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL139 + desc VSSEL139 + 0x288 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL140 + desc VSSEL140 + 0x28C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL141 + desc VSSEL141 + 0x290 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL142 + desc VSSEL142 + 0x294 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL143 + desc VSSEL143 + 0x298 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + SWIER + desc SWIER + 0x29C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SWIE0 + desc SWIE0 + 0 + 0 + read-write + + + SWIE1 + desc SWIE1 + 1 + 1 + read-write + + + SWIE2 + desc SWIE2 + 2 + 2 + read-write + + + SWIE3 + desc SWIE3 + 3 + 3 + read-write + + + SWIE4 + desc SWIE4 + 4 + 4 + read-write + + + SWIE5 + desc SWIE5 + 5 + 5 + read-write + + + SWIE6 + desc SWIE6 + 6 + 6 + read-write + + + SWIE7 + desc SWIE7 + 7 + 7 + read-write + + + SWIE8 + desc SWIE8 + 8 + 8 + read-write + + + SWIE9 + desc SWIE9 + 9 + 9 + read-write + + + SWIE10 + desc SWIE10 + 10 + 10 + read-write + + + SWIE11 + desc SWIE11 + 11 + 11 + read-write + + + SWIE12 + desc SWIE12 + 12 + 12 + read-write + + + SWIE13 + desc SWIE13 + 13 + 13 + read-write + + + SWIE14 + desc SWIE14 + 14 + 14 + read-write + + + SWIE15 + desc SWIE15 + 15 + 15 + read-write + + + SWIE16 + desc SWIE16 + 16 + 16 + read-write + + + SWIE17 + desc SWIE17 + 17 + 17 + read-write + + + SWIE18 + desc SWIE18 + 18 + 18 + read-write + + + SWIE19 + desc SWIE19 + 19 + 19 + read-write + + + SWIE20 + desc SWIE20 + 20 + 20 + read-write + + + SWIE21 + desc SWIE21 + 21 + 21 + read-write + + + SWIE22 + desc SWIE22 + 22 + 22 + read-write + + + SWIE23 + desc SWIE23 + 23 + 23 + read-write + + + SWIE24 + desc SWIE24 + 24 + 24 + read-write + + + SWIE25 + desc SWIE25 + 25 + 25 + read-write + + + SWIE26 + desc SWIE26 + 26 + 26 + read-write + + + SWIE27 + desc SWIE27 + 27 + 27 + read-write + + + SWIE28 + desc SWIE28 + 28 + 28 + read-write + + + SWIE29 + desc SWIE29 + 29 + 29 + read-write + + + SWIE30 + desc SWIE30 + 30 + 30 + read-write + + + SWIE31 + desc SWIE31 + 31 + 31 + read-write + + + + + EVTER + desc EVTER + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + EVTE0 + desc EVTE0 + 0 + 0 + read-write + + + EVTE1 + desc EVTE1 + 1 + 1 + read-write + + + EVTE2 + desc EVTE2 + 2 + 2 + read-write + + + EVTE3 + desc EVTE3 + 3 + 3 + read-write + + + EVTE4 + desc EVTE4 + 4 + 4 + read-write + + + EVTE5 + desc EVTE5 + 5 + 5 + read-write + + + EVTE6 + desc EVTE6 + 6 + 6 + read-write + + + EVTE7 + desc EVTE7 + 7 + 7 + read-write + + + EVTE8 + desc EVTE8 + 8 + 8 + read-write + + + EVTE9 + desc EVTE9 + 9 + 9 + read-write + + + EVTE10 + desc EVTE10 + 10 + 10 + read-write + + + EVTE11 + desc EVTE11 + 11 + 11 + read-write + + + EVTE12 + desc EVTE12 + 12 + 12 + read-write + + + EVTE13 + desc EVTE13 + 13 + 13 + read-write + + + EVTE14 + desc EVTE14 + 14 + 14 + read-write + + + EVTE15 + desc EVTE15 + 15 + 15 + read-write + + + EVTE16 + desc EVTE16 + 16 + 16 + read-write + + + EVTE17 + desc EVTE17 + 17 + 17 + read-write + + + EVTE18 + desc EVTE18 + 18 + 18 + read-write + + + EVTE19 + desc EVTE19 + 19 + 19 + read-write + + + EVTE20 + desc EVTE20 + 20 + 20 + read-write + + + EVTE21 + desc EVTE21 + 21 + 21 + read-write + + + EVTE22 + desc EVTE22 + 22 + 22 + read-write + + + EVTE23 + desc EVTE23 + 23 + 23 + read-write + + + EVTE24 + desc EVTE24 + 24 + 24 + read-write + + + EVTE25 + desc EVTE25 + 25 + 25 + read-write + + + EVTE26 + desc EVTE26 + 26 + 26 + read-write + + + EVTE27 + desc EVTE27 + 27 + 27 + read-write + + + EVTE28 + desc EVTE28 + 28 + 28 + read-write + + + EVTE29 + desc EVTE29 + 29 + 29 + read-write + + + EVTE30 + desc EVTE30 + 30 + 30 + read-write + + + EVTE31 + desc EVTE31 + 31 + 31 + read-write + + + + + IER + desc IER + 0x2A4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IER0 + desc IER0 + 0 + 0 + read-write + + + IER1 + desc IER1 + 1 + 1 + read-write + + + IER2 + desc IER2 + 2 + 2 + read-write + + + IER3 + desc IER3 + 3 + 3 + read-write + + + IER4 + desc IER4 + 4 + 4 + read-write + + + IER5 + desc IER5 + 5 + 5 + read-write + + + IER6 + desc IER6 + 6 + 6 + read-write + + + IER7 + desc IER7 + 7 + 7 + read-write + + + IER8 + desc IER8 + 8 + 8 + read-write + + + IER9 + desc IER9 + 9 + 9 + read-write + + + IER10 + desc IER10 + 10 + 10 + read-write + + + IER11 + desc IER11 + 11 + 11 + read-write + + + IER12 + desc IER12 + 12 + 12 + read-write + + + IER13 + desc IER13 + 13 + 13 + read-write + + + IER14 + desc IER14 + 14 + 14 + read-write + + + IER15 + desc IER15 + 15 + 15 + read-write + + + IER16 + desc IER16 + 16 + 16 + read-write + + + IER17 + desc IER17 + 17 + 17 + read-write + + + IER18 + desc IER18 + 18 + 18 + read-write + + + IER19 + desc IER19 + 19 + 19 + read-write + + + IER20 + desc IER20 + 20 + 20 + read-write + + + IER21 + desc IER21 + 21 + 21 + read-write + + + IER22 + desc IER22 + 22 + 22 + read-write + + + IER23 + desc IER23 + 23 + 23 + read-write + + + IER24 + desc IER24 + 24 + 24 + read-write + + + IER25 + desc IER25 + 25 + 25 + read-write + + + IER26 + desc IER26 + 26 + 26 + read-write + + + IER27 + desc IER27 + 27 + 27 + read-write + + + IER28 + desc IER28 + 28 + 28 + read-write + + + IER29 + desc IER29 + 29 + 29 + read-write + + + IER30 + desc IER30 + 30 + 30 + read-write + + + IER31 + desc IER31 + 31 + 31 + read-write + + + + + + + KEYSCAN + desc KEYSCAN + 0x40050C00 + + 0x0 + 0xC + + + + SCR + desc SCR + 0x0 + 32 + read-write + 0x0 + 0xFF37FFFF + + + KEYINSEL + desc KEYINSEL + 15 + 0 + read-write + + + KEYOUTSEL + desc KEYOUTSEL + 18 + 16 + read-write + + + CKSEL + desc CKSEL + 21 + 20 + read-write + + + T_LLEVEL + desc T_LLEVEL + 28 + 24 + read-write + + + T_HIZ + desc T_HIZ + 31 + 29 + read-write + + + + + SER + desc SER + 0x4 + 32 + read-write + 0x0 + 0x1 + + + SEN + desc SEN + 0 + 0 + read-write + + + + + SSR + desc SSR + 0x8 + 32 + read-write + 0x0 + 0x7 + + + INDEX + desc INDEX + 2 + 0 + read-write + + + + + + + MAU + desc MAU + 0x40055000 + + 0x0 + 0x18 + + + + CSR + desc CSR + 0x0 + 32 + read-write + 0x0 + 0x1F0B + + + START + desc START + 0 + 0 + read-write + + + INTEN + desc INTEN + 1 + 1 + read-write + + + BUSY + desc BUSY + 3 + 3 + read-write + + + SHIFT + desc SHIFT + 12 + 8 + read-write + + + + + DTR0 + desc DTR0 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RTR0 + desc RTR0 + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + SQRT_DOUT + desc SQRT_DOUT + 16 + 0 + read-write + + + + + DTR1 + desc DTR1 + 0x10 + 32 + read-write + 0x0 + 0xFFF + + + SIN_DIN + desc SIN_DIN + 11 + 0 + read-write + + + + + RTR1 + desc RTR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + SIN_DOUT + desc SIN_DOUT + 15 + 0 + read-write + + + + + + + MPU + desc MPU + 0x40050000 + ETH + + 0x0 + 0xA0 + + + + RGD0 + desc RGD0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD1 + desc RGD1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD2 + desc RGD2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD3 + desc RGD3 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD4 + desc RGD4 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD5 + desc RGD5 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD6 + desc RGD6 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD7 + desc RGD7 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD8 + desc RGD8 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD9 + desc RGD9 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD10 + desc RGD10 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD11 + desc RGD11 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD12 + desc RGD12 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD13 + desc RGD13 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD14 + desc RGD14 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD15 + desc RGD15 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + SR + desc SR + 0x40 + 32 + read-only + 0x0 + 0x1F + + + SMPU1EAF + desc SMPU1EAF + 0 + 0 + read-only + + + SMPU2EAF + desc SMPU2EAF + 1 + 1 + read-only + + + FMPUEAF + desc FMPUEAF + 2 + 2 + read-only + + + HMPUEAF + desc HMPUEAF + 3 + 3 + read-only + + + EMPUEAF + desc EMPUEAF + 4 + 4 + read-only + + + + + ECLR + desc ECLR + 0x44 + 32 + write-only + 0x0 + 0x1F + + + SMPU1ECLR + desc SMPU1ECLR + 0 + 0 + write-only + + + SMPU2ECLR + desc SMPU2ECLR + 1 + 1 + write-only + + + FMPUECLR + desc FMPUECLR + 2 + 2 + write-only + + + HMPUECLR + desc HMPUECLR + 3 + 3 + write-only + + + EMPUECLR + desc EMPUECLR + 4 + 4 + write-only + + + + + WP + desc WP + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + MPUWE + desc MPUWE + 0 + 0 + read-write + + + WKEY + desc WKEY + 15 + 1 + write-only + + + + + IPPR + desc IPPR + 0x4C + 32 + read-write + 0x0 + 0xBFFFF3FF + + + AESRDP + desc AESRDP + 0 + 0 + read-write + + + AESWRP + desc AESWRP + 1 + 1 + read-write + + + HASHRDP + desc HASHRDP + 2 + 2 + read-write + + + HASHWRP + desc HASHWRP + 3 + 3 + read-write + + + TRNGRDP + desc TRNGRDP + 4 + 4 + read-write + + + TRNGWRP + desc TRNGWRP + 5 + 5 + read-write + + + CRCRDP + desc CRCRDP + 6 + 6 + read-write + + + CRCWRP + desc CRCWRP + 7 + 7 + read-write + + + EFMRDP + desc EFMRDP + 8 + 8 + read-write + + + EFMWRP + desc EFMWRP + 9 + 9 + read-write + + + WDTRDP + desc WDTRDP + 12 + 12 + read-write + + + WDTWRP + desc WDTWRP + 13 + 13 + read-write + + + SWDTRDP + desc SWDTRDP + 14 + 14 + read-write + + + SWDTWRP + desc SWDTWRP + 15 + 15 + read-write + + + BKSRAMRDP + desc BKSRAMRDP + 16 + 16 + read-write + + + BKSRAMWRP + desc BKSRAMWRP + 17 + 17 + read-write + + + RTCRDP + desc RTCRDP + 18 + 18 + read-write + + + RTCWRP + desc RTCWRP + 19 + 19 + read-write + + + DMPURDP + desc DMPURDP + 20 + 20 + read-write + + + DMPUWRP + desc DMPUWRP + 21 + 21 + read-write + + + SRAMCRDP + desc SRAMCRDP + 22 + 22 + read-write + + + SRAMCWRP + desc SRAMCWRP + 23 + 23 + read-write + + + INTCRDP + desc INTCRDP + 24 + 24 + read-write + + + INTCWRP + desc INTCWRP + 25 + 25 + read-write + + + SYSCRDP + desc SYSCRDP + 26 + 26 + read-write + + + SYSCWRP + desc SYSCWRP + 27 + 27 + read-write + + + MSTPRDP + desc MSTPRDP + 28 + 28 + read-write + + + MSPTWRP + desc MSPTWRP + 29 + 29 + read-write + + + BUSERRE + desc BUSERRE + 31 + 31 + read-write + + + + + S1RGE + desc S1RGE + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0E + desc S1RG0E + 0 + 0 + read-write + + + S1RG1E + desc S1RG1E + 1 + 1 + read-write + + + S1RG2E + desc S1RG2E + 2 + 2 + read-write + + + S1RG3E + desc S1RG3E + 3 + 3 + read-write + + + S1RG4E + desc S1RG4E + 4 + 4 + read-write + + + S1RG5E + desc S1RG5E + 5 + 5 + read-write + + + S1RG6E + desc S1RG6E + 6 + 6 + read-write + + + S1RG7E + desc S1RG7E + 7 + 7 + read-write + + + S1RG8E + desc S1RG8E + 8 + 8 + read-write + + + S1RG9E + desc S1RG9E + 9 + 9 + read-write + + + S1RG10E + desc S1RG10E + 10 + 10 + read-write + + + S1RG11E + desc S1RG11E + 11 + 11 + read-write + + + S1RG12E + desc S1RG12E + 12 + 12 + read-write + + + S1RG13E + desc S1RG13E + 13 + 13 + read-write + + + S1RG14E + desc S1RG14E + 14 + 14 + read-write + + + S1RG15E + desc S1RG15E + 15 + 15 + read-write + + + + + S1RGWP + desc S1RGWP + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0WP + desc S1RG0WP + 0 + 0 + read-write + + + S1RG1WP + desc S1RG1WP + 1 + 1 + read-write + + + S1RG2WP + desc S1RG2WP + 2 + 2 + read-write + + + S1RG3WP + desc S1RG3WP + 3 + 3 + read-write + + + S1RG4WP + desc S1RG4WP + 4 + 4 + read-write + + + S1RG5WP + desc S1RG5WP + 5 + 5 + read-write + + + S1RG6WP + desc S1RG6WP + 6 + 6 + read-write + + + S1RG7WP + desc S1RG7WP + 7 + 7 + read-write + + + S1RG8WP + desc S1RG8WP + 8 + 8 + read-write + + + S1RG9WP + desc S1RG9WP + 9 + 9 + read-write + + + S1RG10WP + desc S1RG10WP + 10 + 10 + read-write + + + S1RG11WP + desc S1RG11WP + 11 + 11 + read-write + + + S1RG12WP + desc S1RG12WP + 12 + 12 + read-write + + + S1RG13WP + desc S1RG13WP + 13 + 13 + read-write + + + S1RG14WP + desc S1RG14WP + 14 + 14 + read-write + + + S1RG15WP + desc S1RG15WP + 15 + 15 + read-write + + + + + S1RGRP + desc S1RGRP + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0RP + desc S1RG0RP + 0 + 0 + read-write + + + S1RG1RP + desc S1RG1RP + 1 + 1 + read-write + + + S1RG2RP + desc S1RG2RP + 2 + 2 + read-write + + + S1RG3RP + desc S1RG3RP + 3 + 3 + read-write + + + S1RG4RP + desc S1RG4RP + 4 + 4 + read-write + + + S1RG5RP + desc S1RG5RP + 5 + 5 + read-write + + + S1RG6RP + desc S1RG6RP + 6 + 6 + read-write + + + S1RG7RP + desc S1RG7RP + 7 + 7 + read-write + + + S1RG8RP + desc S1RG8RP + 8 + 8 + read-write + + + S1RG9RP + desc S1RG9RP + 9 + 9 + read-write + + + S1RG10RP + desc S1RG10RP + 10 + 10 + read-write + + + S1RG11RP + desc S1RG11RP + 11 + 11 + read-write + + + S1RG12RP + desc S1RG12RP + 12 + 12 + read-write + + + S1RG13RP + desc S1RG13RP + 13 + 13 + read-write + + + S1RG14RP + desc S1RG14RP + 14 + 14 + read-write + + + S1RG15RP + desc S1RG15RP + 15 + 15 + read-write + + + + + S1CR + desc S1CR + 0x5C + 32 + read-write + 0x0 + 0x8F + + + SMPU1BRP + desc SMPU1BRP + 0 + 0 + read-write + + + SMPU1BWP + desc SMPU1BWP + 1 + 1 + read-write + + + SMPU1ACT + desc SMPU1ACT + 3 + 2 + read-write + + + SMPU1E + desc SMPU1E + 7 + 7 + read-write + + + + + S2RGE + desc S2RGE + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0E + desc S2RG0E + 0 + 0 + read-write + + + S2RG1E + desc S2RG1E + 1 + 1 + read-write + + + S2RG2E + desc S2RG2E + 2 + 2 + read-write + + + S2RG3E + desc S2RG3E + 3 + 3 + read-write + + + S2RG4E + desc S2RG4E + 4 + 4 + read-write + + + S2RG5E + desc S2RG5E + 5 + 5 + read-write + + + S2RG6E + desc S2RG6E + 6 + 6 + read-write + + + S2RG7E + desc S2RG7E + 7 + 7 + read-write + + + S2RG8E + desc S2RG8E + 8 + 8 + read-write + + + S2RG9E + desc S2RG9E + 9 + 9 + read-write + + + S2RG10E + desc S2RG10E + 10 + 10 + read-write + + + S2RG11E + desc S2RG11E + 11 + 11 + read-write + + + S2RG12E + desc S2RG12E + 12 + 12 + read-write + + + S2RG13E + desc S2RG13E + 13 + 13 + read-write + + + S2RG14E + desc S2RG14E + 14 + 14 + read-write + + + S2RG15E + desc S2RG15E + 15 + 15 + read-write + + + + + S2RGWP + desc S2RGWP + 0x64 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0WP + desc S2RG0WP + 0 + 0 + read-write + + + S2RG1WP + desc S2RG1WP + 1 + 1 + read-write + + + S2RG2WP + desc S2RG2WP + 2 + 2 + read-write + + + S2RG3WP + desc S2RG3WP + 3 + 3 + read-write + + + S2RG4WP + desc S2RG4WP + 4 + 4 + read-write + + + S2RG5WP + desc S2RG5WP + 5 + 5 + read-write + + + S2RG6WP + desc S2RG6WP + 6 + 6 + read-write + + + S2RG7WP + desc S2RG7WP + 7 + 7 + read-write + + + S2RG8WP + desc S2RG8WP + 8 + 8 + read-write + + + S2RG9WP + desc S2RG9WP + 9 + 9 + read-write + + + S2RG10WP + desc S2RG10WP + 10 + 10 + read-write + + + S2RG11WP + desc S2RG11WP + 11 + 11 + read-write + + + S2RG12WP + desc S2RG12WP + 12 + 12 + read-write + + + S2RG13WP + desc S2RG13WP + 13 + 13 + read-write + + + S2RG14WP + desc S2RG14WP + 14 + 14 + read-write + + + S2RG15WP + desc S2RG15WP + 15 + 15 + read-write + + + + + S2RGRP + desc S2RGRP + 0x68 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0RP + desc S2RG0RP + 0 + 0 + read-write + + + S2RG1RP + desc S2RG1RP + 1 + 1 + read-write + + + S2RG2RP + desc S2RG2RP + 2 + 2 + read-write + + + S2RG3RP + desc S2RG3RP + 3 + 3 + read-write + + + S2RG4RP + desc S2RG4RP + 4 + 4 + read-write + + + S2RG5RP + desc S2RG5RP + 5 + 5 + read-write + + + S2RG6RP + desc S2RG6RP + 6 + 6 + read-write + + + S2RG7RP + desc S2RG7RP + 7 + 7 + read-write + + + S2RG8RP + desc S2RG8RP + 8 + 8 + read-write + + + S2RG9RP + desc S2RG9RP + 9 + 9 + read-write + + + S2RG10RP + desc S2RG10RP + 10 + 10 + read-write + + + S2RG11RP + desc S2RG11RP + 11 + 11 + read-write + + + S2RG12RP + desc S2RG12RP + 12 + 12 + read-write + + + S2RG13RP + desc S2RG13RP + 13 + 13 + read-write + + + S2RG14RP + desc S2RG14RP + 14 + 14 + read-write + + + S2RG15RP + desc S2RG15RP + 15 + 15 + read-write + + + + + S2CR + desc S2CR + 0x6C + 32 + read-write + 0x0 + 0x8F + + + SMPU2BRP + desc SMPU2BRP + 0 + 0 + read-write + + + SMPU2BWP + desc SMPU2BWP + 1 + 1 + read-write + + + SMPU2ACT + desc SMPU2ACT + 3 + 2 + read-write + + + SMPU2E + desc SMPU2E + 7 + 7 + read-write + + + + + FRGE + desc FRGE + 0x70 + 32 + read-write + 0x0 + 0xFF + + + FRG0E + desc FRG0E + 0 + 0 + read-write + + + FRG1E + desc FRG1E + 1 + 1 + read-write + + + FRG2E + desc FRG2E + 2 + 2 + read-write + + + FRG3E + desc FRG3E + 3 + 3 + read-write + + + FRG4E + desc FRG4E + 4 + 4 + read-write + + + FRG5E + desc FRG5E + 5 + 5 + read-write + + + FRG6E + desc FRG6E + 6 + 6 + read-write + + + FRG7E + desc FRG7E + 7 + 7 + read-write + + + + + FRGWP + desc FRGWP + 0x74 + 32 + read-write + 0x0 + 0xFF + + + FRG0WP + desc FRG0WP + 0 + 0 + read-write + + + FRG1WP + desc FRG1WP + 1 + 1 + read-write + + + FRG2WP + desc FRG2WP + 2 + 2 + read-write + + + FRG3WP + desc FRG3WP + 3 + 3 + read-write + + + FRG4WP + desc FRG4WP + 4 + 4 + read-write + + + FRG5WP + desc FRG5WP + 5 + 5 + read-write + + + FRG6WP + desc FRG6WP + 6 + 6 + read-write + + + FRG7WP + desc FRG7WP + 7 + 7 + read-write + + + + + FRGRP + desc FRGRP + 0x78 + 32 + read-write + 0x0 + 0xFF + + + FRG0RP + desc FRG0RP + 0 + 0 + read-write + + + FRG1RP + desc FRG1RP + 1 + 1 + read-write + + + FRG2RP + desc FRG2RP + 2 + 2 + read-write + + + FRG3RP + desc FRG3RP + 3 + 3 + read-write + + + FRG4RP + desc FRG4RP + 4 + 4 + read-write + + + FRG5RP + desc FRG5RP + 5 + 5 + read-write + + + FRG6RP + desc FRG6RP + 6 + 6 + read-write + + + FRG7RP + desc FRG7RP + 7 + 7 + read-write + + + + + FCR + desc FCR + 0x7C + 32 + read-write + 0x0 + 0x8F + + + FMPUBRP + desc FMPUBRP + 0 + 0 + read-write + + + FMPUBWP + desc FMPUBWP + 1 + 1 + read-write + + + FMPUACT + desc FMPUACT + 3 + 2 + read-write + + + FMPUE + desc FMPUE + 7 + 7 + read-write + + + + + HRGE + desc HRGE + 0x80 + 32 + read-write + 0x0 + 0xFF + + + HRG0E + desc HRG0E + 0 + 0 + read-write + + + HRG1E + desc HRG1E + 1 + 1 + read-write + + + HRG2E + desc HRG2E + 2 + 2 + read-write + + + HRG3E + desc HRG3E + 3 + 3 + read-write + + + HRG4E + desc HRG4E + 4 + 4 + read-write + + + HRG5E + desc HRG5E + 5 + 5 + read-write + + + HRG6E + desc HRG6E + 6 + 6 + read-write + + + HRG7E + desc HRG7E + 7 + 7 + read-write + + + + + HRGWP + desc HRGWP + 0x84 + 32 + read-write + 0x0 + 0xFF + + + HRG0WP + desc HRG0WP + 0 + 0 + read-write + + + HRG1WP + desc HRG1WP + 1 + 1 + read-write + + + HRG2WP + desc HRG2WP + 2 + 2 + read-write + + + HRG3WP + desc HRG3WP + 3 + 3 + read-write + + + HRG4WP + desc HRG4WP + 4 + 4 + read-write + + + HRG5WP + desc HRG5WP + 5 + 5 + read-write + + + HRG6WP + desc HRG6WP + 6 + 6 + read-write + + + HRG7WP + desc HRG7WP + 7 + 7 + read-write + + + + + HRGRP + desc HRGRP + 0x88 + 32 + read-write + 0x0 + 0xFF + + + HRG0RP + desc HRG0RP + 0 + 0 + read-write + + + HRG1RP + desc HRG1RP + 1 + 1 + read-write + + + HRG2RP + desc HRG2RP + 2 + 2 + read-write + + + HRG3RP + desc HRG3RP + 3 + 3 + read-write + + + HRG4RP + desc HRG4RP + 4 + 4 + read-write + + + HRG5RP + desc HRG5RP + 5 + 5 + read-write + + + HRG6RP + desc HRG6RP + 6 + 6 + read-write + + + HRG7RP + desc HRG7RP + 7 + 7 + read-write + + + + + HCR + desc HCR + 0x8C + 32 + read-write + 0x0 + 0x8F + + + HMPUBRP + desc HMPUBRP + 0 + 0 + read-write + + + HMPUBWP + desc HMPUBWP + 1 + 1 + read-write + + + HMPUACT + desc HMPUACT + 3 + 2 + read-write + + + HMPUE + desc HMPUE + 7 + 7 + read-write + + + + + ERGE + desc ERGE + 0x90 + 32 + read-write + 0x0 + 0xFF + + + ERG0E + desc ERG0E + 0 + 0 + read-write + + + ERG1E + desc ERG1E + 1 + 1 + read-write + + + ERG2E + desc ERG2E + 2 + 2 + read-write + + + ERG3E + desc ERG3E + 3 + 3 + read-write + + + ERG4E + desc ERG4E + 4 + 4 + read-write + + + ERG5E + desc ERG5E + 5 + 5 + read-write + + + ERG6E + desc ERG6E + 6 + 6 + read-write + + + ERG7E + desc ERG7E + 7 + 7 + read-write + + + + + ERGWP + desc ERGWP + 0x94 + 32 + read-write + 0x0 + 0xFF + + + ERG0WP + desc ERG0WP + 0 + 0 + read-write + + + ERG1WP + desc ERG1WP + 1 + 1 + read-write + + + ERG2WP + desc ERG2WP + 2 + 2 + read-write + + + ERG3WP + desc ERG3WP + 3 + 3 + read-write + + + ERG4WP + desc ERG4WP + 4 + 4 + read-write + + + ERG5WP + desc ERG5WP + 5 + 5 + read-write + + + ERG6WP + desc ERG6WP + 6 + 6 + read-write + + + ERG7WP + desc ERG7WP + 7 + 7 + read-write + + + + + ERGRP + desc ERGRP + 0x98 + 32 + read-write + 0x0 + 0xFF + + + ERG0RP + desc ERG0RP + 0 + 0 + read-write + + + ERG1RP + desc ERG1RP + 1 + 1 + read-write + + + ERG2RP + desc ERG2RP + 2 + 2 + read-write + + + ERG3RP + desc ERG3RP + 3 + 3 + read-write + + + ERG4RP + desc ERG4RP + 4 + 4 + read-write + + + ERG5RP + desc ERG5RP + 5 + 5 + read-write + + + ERG6RP + desc ERG6RP + 6 + 6 + read-write + + + ERG7RP + desc ERG7RP + 7 + 7 + read-write + + + + + ECR + desc ECR + 0x9C + 32 + read-write + 0x0 + 0x8F + + + EMPUBRP + desc EMPUBRP + 0 + 0 + read-write + + + EMPUBWP + desc EMPUBWP + 1 + 1 + read-write + + + EMPUACT + desc EMPUACT + 3 + 2 + read-write + + + EMPUE + desc EMPUE + 7 + 7 + read-write + + + + + + + NFC + desc NFC + 0x88100000 + + 0x0 + 0x8180 + + + + DATR_BASE + desc DATR_BASE + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CMDR + desc CMDR + 0x8000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CMD + desc CMD + 7 + 0 + read-write + + + ARG + desc ARG + 31 + 8 + read-write + + + + + IDXR0 + desc IDXR0 + 0x8004 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IENR + desc IENR + 0x8030 + 32 + read-write + 0x0 + 0xFFD3 + + + ECCEUEN + desc ECCEUEN + 0 + 0 + read-write + + + ECCECEN + desc ECCECEN + 1 + 1 + read-write + + + ECCCEN + desc ECCCEN + 4 + 4 + read-write + + + ECCEEN + desc ECCEEN + 6 + 6 + read-write + + + ECCDIS + desc ECCDIS + 7 + 7 + read-write + + + RBEN + desc RBEN + 15 + 8 + read-write + + + + + ISTR + desc ISTR + 0x8034 + 32 + read-write + 0x0 + 0xFF53 + + + ECCEUST + desc ECCEUST + 0 + 0 + read-write + + + ECCECST + desc ECCECST + 1 + 1 + read-write + + + ECCCST + desc ECCCST + 4 + 4 + read-write + + + ECCEST + desc ECCEST + 6 + 6 + read-write + + + RBST + desc RBST + 15 + 8 + read-write + + + + + IRSR + desc IRSR + 0x8038 + 32 + read-write + 0x0 + 0xFF53 + + + ECCEURS + desc ECCEURS + 0 + 0 + read-write + + + ECCECRS + desc ECCECRS + 1 + 1 + read-write + + + ECCCRS + desc ECCCRS + 4 + 4 + read-write + + + ECCERS + desc ECCERS + 6 + 6 + read-write + + + RBRS + desc RBRS + 15 + 8 + read-write + + + + + IDXR1 + desc IDXR1 + 0x8048 + 32 + read-write + 0x0 + 0xFF + + + IDX1 + desc IDX1 + 7 + 0 + read-write + + + + + TMCR0 + desc TMCR0 + 0x804C + 32 + read-write + 0x3030202 + 0xFFFFFFFF + + + TS + desc TS + 7 + 0 + read-write + + + TWP + desc TWP + 15 + 8 + read-write + + + TRP + desc TRP + 23 + 16 + read-write + + + TH + desc TH + 31 + 24 + read-write + + + + + TMCR1 + desc TMCR1 + 0x8050 + 32 + read-write + 0x28080303 + 0xFFFFFFFF + + + TWH + desc TWH + 7 + 0 + read-write + + + TRH + desc TRH + 15 + 8 + read-write + + + TRR + desc TRR + 23 + 16 + read-write + + + TWB + desc TWB + 31 + 24 + read-write + + + + + BACR + desc BACR + 0x8054 + 32 + read-write + 0x2187 + 0xFF3FCF + + + SIZE + desc SIZE + 2 + 0 + read-write + + + B16BIT + desc B16BIT + 3 + 3 + read-write + + + BANK + desc BANK + 7 + 6 + read-write + + + PAGE + desc PAGE + 9 + 8 + read-write + + + WP + desc WP + 10 + 10 + read-write + + + ECCM + desc ECCM + 12 + 11 + read-write + + + RAC + desc RAC + 13 + 13 + read-write + + + SCS + desc SCS + 23 + 16 + read-write + + + + + TMCR2 + desc TMCR2 + 0x805C + 32 + read-write + 0x3050D03 + 0xFFFFFFFF + + + TCCS + desc TCCS + 7 + 0 + read-write + + + TWTR + desc TWTR + 15 + 8 + read-write + + + TRTW + desc TRTW + 23 + 16 + read-write + + + TADL + desc TADL + 31 + 24 + read-write + + + + + ECCR0 + desc ECCR0 + 0x8060 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR1 + desc ECCR1 + 0x8064 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR2 + desc ECCR2 + 0x8068 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR3 + desc ECCR3 + 0x806C + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR4 + desc ECCR4 + 0x8070 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR5 + desc ECCR5 + 0x8074 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR6 + desc ECCR6 + 0x8078 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECC_STAT + desc ECC_STAT + 0x807C + 32 + read-only + 0x0 + 0xFFFF + + + ERRSEC + desc ERRSEC + 15 + 0 + read-only + + + + + ECC_SYND0_0 + desc ECC_SYND0_0 + 0x8080 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND0_1 + desc ECC_SYND0_1 + 0x8084 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND0_2 + desc ECC_SYND0_2 + 0x8088 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND0_3 + desc ECC_SYND0_3 + 0x808C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND1_0 + desc ECC_SYND1_0 + 0x8090 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND1_1 + desc ECC_SYND1_1 + 0x8094 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND1_2 + desc ECC_SYND1_2 + 0x8098 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND1_3 + desc ECC_SYND1_3 + 0x809C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND2_0 + desc ECC_SYND2_0 + 0x80A0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND2_1 + desc ECC_SYND2_1 + 0x80A4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND2_2 + desc ECC_SYND2_2 + 0x80A8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND2_3 + desc ECC_SYND2_3 + 0x80AC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND3_0 + desc ECC_SYND3_0 + 0x80B0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND3_1 + desc ECC_SYND3_1 + 0x80B4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND3_2 + desc ECC_SYND3_2 + 0x80B8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND3_3 + desc ECC_SYND3_3 + 0x80BC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND4_0 + desc ECC_SYND4_0 + 0x80C0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND4_1 + desc ECC_SYND4_1 + 0x80C4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND4_2 + desc ECC_SYND4_2 + 0x80C8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND4_3 + desc ECC_SYND4_3 + 0x80CC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND5_0 + desc ECC_SYND5_0 + 0x80D0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND5_1 + desc ECC_SYND5_1 + 0x80D4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND5_2 + desc ECC_SYND5_2 + 0x80D8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND5_3 + desc ECC_SYND5_3 + 0x80DC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND6_0 + desc ECC_SYND6_0 + 0x80E0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND6_1 + desc ECC_SYND6_1 + 0x80E4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + RESV + desc RESV + 31 + 31 + read-write + + + + + ECC_SYND6_2 + desc ECC_SYND6_2 + 0x80E8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND6_3 + desc ECC_SYND6_3 + 0x80EC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND7_0 + desc ECC_SYND7_0 + 0x80F0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND7_1 + desc ECC_SYND7_1 + 0x80F4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND7_2 + desc ECC_SYND7_2 + 0x80F8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND7_3 + desc ECC_SYND7_3 + 0x80FC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND8_0 + desc ECC_SYND8_0 + 0x8100 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND8_1 + desc ECC_SYND8_1 + 0x8104 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND8_2 + desc ECC_SYND8_2 + 0x8108 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND8_3 + desc ECC_SYND8_3 + 0x810C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND9_0 + desc ECC_SYND9_0 + 0x8110 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND9_1 + desc ECC_SYND9_1 + 0x8114 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND9_2 + desc ECC_SYND9_2 + 0x8118 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND9_3 + desc ECC_SYND9_3 + 0x811C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND10_0 + desc ECC_SYND10_0 + 0x8120 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND10_1 + desc ECC_SYND10_1 + 0x8124 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND10_2 + desc ECC_SYND10_2 + 0x8128 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND10_3 + desc ECC_SYND10_3 + 0x812C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND11_0 + desc ECC_SYND11_0 + 0x8130 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND11_1 + desc ECC_SYND11_1 + 0x8134 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND11_2 + desc ECC_SYND11_2 + 0x8138 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND11_3 + desc ECC_SYND11_3 + 0x813C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND12_0 + desc ECC_SYND12_0 + 0x8140 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND12_1 + desc ECC_SYND12_1 + 0x8144 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND12_2 + desc ECC_SYND12_2 + 0x8148 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND12_3 + desc ECC_SYND12_3 + 0x814C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND13_0 + desc ECC_SYND13_0 + 0x8150 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND13_1 + desc ECC_SYND13_1 + 0x8154 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND13_2 + desc ECC_SYND13_2 + 0x8158 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND13_3 + desc ECC_SYND13_3 + 0x815C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND14_0 + desc ECC_SYND14_0 + 0x8160 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND14_1 + desc ECC_SYND14_1 + 0x8164 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND14_2 + desc ECC_SYND14_2 + 0x8168 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND14_3 + desc ECC_SYND14_3 + 0x816C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND15_0 + desc ECC_SYND15_0 + 0x8170 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND15_1 + desc ECC_SYND15_1 + 0x8174 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND15_2 + desc ECC_SYND15_2 + 0x8178 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND15_3 + desc ECC_SYND15_3 + 0x817C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + + + OTS + desc OTS + 0x40010600 + + 0x0 + 0x3A20C + + + + PDR1 + desc PDR1 + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + PDR2 + desc PDR2 + 0xF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + PDR3 + desc PDR3 + 0xF8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + CTL + desc CTL + 0x3A200 + 16 + read-write + 0x0 + 0xF + + + OTSST + desc OTSST + 0 + 0 + read-write + + + OTSCK + desc OTSCK + 1 + 1 + read-write + + + OTSIE + desc OTSIE + 2 + 2 + read-write + + + TSSTP + desc TSSTP + 3 + 3 + read-write + + + + + DR1 + desc DR1 + 0x3A202 + 16 + read-write + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x3A204 + 16 + read-write + 0x0 + 0xFFFF + + + ECR + desc ECR + 0x3A206 + 16 + read-write + 0x0 + 0xFFFF + + + LPR + desc LPR + 0x3A208 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + TSOFS + desc TSOFS + 7 + 0 + read-only + + + TSSLP + desc TSSLP + 31 + 8 + read-only + + + + + + + PERIC + desc PERIC + 0x40055400 + + 0x0 + 0x2C + + + + USB_SYCTLREG + desc USB_SYCTLREG + 0x0 + 32 + read-write + 0x0 + 0x7070703 + + + USBFS_DFB + desc USBFS_DFB + 0 + 0 + read-write + + + USBFS_SOFEN + desc USBFS_SOFEN + 1 + 1 + read-write + + + USBHS_DFB + desc USBHS_DFB + 8 + 8 + read-write + + + USBHS_SOFEN + desc USBHS_SOFEN + 9 + 9 + read-write + + + USBHS_FSPHYE + desc USBHS_FSPHYE + 10 + 10 + read-write + + + USBFS_NFS + desc USBFS_NFS + 17 + 16 + read-write + + + USBFS_NFE + desc USBFS_NFE + 18 + 18 + read-write + + + USBHS_NFS + desc USBHS_NFS + 25 + 24 + read-write + + + USBHS_NFE + desc USBHS_NFE + 26 + 26 + read-write + + + + + SDIOC_SYCTLREG + desc SDIOC_SYCTLREG + 0x4 + 32 + read-write + 0x0 + 0xA + + + SELMMC1 + desc SELMMC1 + 1 + 1 + read-write + + + SELMMC2 + desc SELMMC2 + 3 + 3 + read-write + + + + + NFC_STCR + desc NFC_STCR + 0x8 + 32 + read-write + 0x0 + 0x1 + + + OPENP + desc OPENP + 0 + 0 + read-write + + + + + NFC_ENAR + desc NFC_ENAR + 0xC + 32 + read-write + 0x0 + 0x4 + + + NFCEN + desc NFCEN + 2 + 2 + read-write + + + + + SMC_ENAR + desc SMC_ENAR + 0xC + 32 + read-write + 0x0 + 0x2 + + + SMCEN + desc SMCEN + 1 + 1 + read-write + + + + + DMC_ENAR + desc DMC_ENAR + 0xC + 32 + read-write + 0x0 + 0x1 + + + DMCEN + desc DMCEN + 0 + 0 + read-write + + + + + USART1_NFC + desc USART1_NFC + 0x1C + 32 + read-write + 0x0 + 0x7 + + + USASRT1_NFS + desc USASRT1_NFS + 1 + 0 + read-write + + + USART1_NFE + desc USART1_NFE + 2 + 2 + read-write + + + + + NFC_STSR + desc NFC_STSR + 0x28 + 32 + read-only + 0x0 + 0x1FF + + + CHIP_BUSY + desc CHIP_BUSY + 7 + 0 + read-only + + + PECC + desc PECC + 8 + 8 + read-only + + + + + + + PWC + desc PWC + 0x40048000 + + 0x0 + 0xC400 + + + + FCG0 + desc FCG0 + 0x0 + 32 + read-write + 0xFFFFFA0E + 0xFFFFE4F1 + + + SRAMH + desc SRAMH + 0 + 0 + read-write + + + SRAM1 + desc SRAM1 + 4 + 4 + read-write + + + SRAM2 + desc SRAM2 + 5 + 5 + read-write + + + SRAM3 + desc SRAM3 + 6 + 6 + read-write + + + SRAM4 + desc SRAM4 + 7 + 7 + read-write + + + SRAMB + desc SRAMB + 10 + 10 + read-write + + + KEY + desc KEY + 13 + 13 + read-write + + + DMA1 + desc DMA1 + 14 + 14 + read-write + + + DMA2 + desc DMA2 + 15 + 15 + read-write + + + FCM + desc FCM + 16 + 16 + read-write + + + AOS + desc AOS + 17 + 17 + read-write + + + CTC + desc CTC + 18 + 18 + read-write + + + MAU + desc MAU + 19 + 19 + read-write + + + AES + desc AES + 20 + 20 + read-write + + + HASH + desc HASH + 21 + 21 + read-write + + + TRNG + desc TRNG + 22 + 22 + read-write + + + CRC + desc CRC + 23 + 23 + read-write + + + DCU1 + desc DCU1 + 24 + 24 + read-write + + + DCU2 + desc DCU2 + 25 + 25 + read-write + + + DCU3 + desc DCU3 + 26 + 26 + read-write + + + DCU4 + desc DCU4 + 27 + 27 + read-write + + + DCU5 + desc DCU5 + 28 + 28 + read-write + + + DCU6 + desc DCU6 + 29 + 29 + read-write + + + DCU7 + desc DCU7 + 30 + 30 + read-write + + + DCU8 + desc DCU8 + 31 + 31 + read-write + + + + + FCG1 + desc FCG1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFF + + + CAN1 + desc CAN1 + 0 + 0 + read-write + + + CAN2 + desc CAN2 + 1 + 1 + read-write + + + ETHMAC + desc ETHMAC + 2 + 2 + read-write + + + QSPI + desc QSPI + 3 + 3 + read-write + + + I2C1 + desc I2C1 + 4 + 4 + read-write + + + I2C2 + desc I2C2 + 5 + 5 + read-write + + + I2C3 + desc I2C3 + 6 + 6 + read-write + + + I2C4 + desc I2C4 + 7 + 7 + read-write + + + I2C5 + desc I2C5 + 8 + 8 + read-write + + + I2C6 + desc I2C6 + 9 + 9 + read-write + + + SDIOC1 + desc SDIOC1 + 10 + 10 + read-write + + + SDIOC2 + desc SDIOC2 + 11 + 11 + read-write + + + I2S1 + desc I2S1 + 12 + 12 + read-write + + + I2S2 + desc I2S2 + 13 + 13 + read-write + + + I2S3 + desc I2S3 + 14 + 14 + read-write + + + I2S4 + desc I2S4 + 15 + 15 + read-write + + + SPI1 + desc SPI1 + 16 + 16 + read-write + + + SPI2 + desc SPI2 + 17 + 17 + read-write + + + SPI3 + desc SPI3 + 18 + 18 + read-write + + + SPI4 + desc SPI4 + 19 + 19 + read-write + + + SPI5 + desc SPI5 + 20 + 20 + read-write + + + SPI6 + desc SPI6 + 21 + 21 + read-write + + + USBFS + desc USBFS + 22 + 22 + read-write + + + USBHS + desc USBHS + 23 + 23 + read-write + + + FMAC1 + desc FMAC1 + 24 + 24 + read-write + + + FMAC2 + desc FMAC2 + 25 + 25 + read-write + + + FMAC3 + desc FMAC3 + 26 + 26 + read-write + + + FMAC4 + desc FMAC4 + 27 + 27 + read-write + + + + + FCG2 + desc FCG2 + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFBFFF + + + TMR6_1 + desc TMR6_1 + 0 + 0 + read-write + + + TMR6_2 + desc TMR6_2 + 1 + 1 + read-write + + + TMR6_3 + desc TMR6_3 + 2 + 2 + read-write + + + TMR6_4 + desc TMR6_4 + 3 + 3 + read-write + + + TMR6_5 + desc TMR6_5 + 4 + 4 + read-write + + + TMR6_6 + desc TMR6_6 + 5 + 5 + read-write + + + TMR6_7 + desc TMR6_7 + 6 + 6 + read-write + + + TMR6_8 + desc TMR6_8 + 7 + 7 + read-write + + + TMR4_1 + desc TMR4_1 + 8 + 8 + read-write + + + TMR4_2 + desc TMR4_2 + 9 + 9 + read-write + + + TMR4_3 + desc TMR4_3 + 10 + 10 + read-write + + + HRPWM + desc HRPWM + 11 + 11 + read-write + + + TMR0_1 + desc TMR0_1 + 12 + 12 + read-write + + + TMR0_2 + desc TMR0_2 + 13 + 13 + read-write + + + EMB + desc EMB + 15 + 15 + read-write + + + TMR2_1 + desc TMR2_1 + 16 + 16 + read-write + + + TMR2_2 + desc TMR2_2 + 17 + 17 + read-write + + + TMR2_3 + desc TMR2_3 + 18 + 18 + read-write + + + TMR2_4 + desc TMR2_4 + 19 + 19 + read-write + + + TMRA_1 + desc TMRA_1 + 20 + 20 + read-write + + + TMRA_2 + desc TMRA_2 + 21 + 21 + read-write + + + TMRA_3 + desc TMRA_3 + 22 + 22 + read-write + + + TMRA_4 + desc TMRA_4 + 23 + 23 + read-write + + + TMRA_5 + desc TMRA_5 + 24 + 24 + read-write + + + TMRA_6 + desc TMRA_6 + 25 + 25 + read-write + + + TMRA_7 + desc TMRA_7 + 26 + 26 + read-write + + + TMRA_8 + desc TMRA_8 + 27 + 27 + read-write + + + TMRA_9 + desc TMRA_9 + 28 + 28 + read-write + + + TMRA_10 + desc TMRA_10 + 29 + 29 + read-write + + + TMRA_11 + desc TMRA_11 + 30 + 30 + read-write + + + TMRA_12 + desc TMRA_12 + 31 + 31 + read-write + + + + + FCG3 + desc FCG3 + 0xC + 32 + read-write + 0xFFFFFFFF + 0x3FF7933F + + + ADC1 + desc ADC1 + 0 + 0 + read-write + + + ADC2 + desc ADC2 + 1 + 1 + read-write + + + ADC3 + desc ADC3 + 2 + 2 + read-write + + + CMBIAS + desc CMBIAS + 3 + 3 + read-write + + + DAC1 + desc DAC1 + 4 + 4 + read-write + + + DAC2 + desc DAC2 + 5 + 5 + read-write + + + CMP1 + desc CMP1 + 8 + 8 + read-write + + + CMP2 + desc CMP2 + 9 + 9 + read-write + + + OTS + desc OTS + 12 + 12 + read-write + + + DVP + desc DVP + 15 + 15 + read-write + + + SMC + desc SMC + 16 + 16 + read-write + + + DMC + desc DMC + 17 + 17 + read-write + + + NFC + desc NFC + 18 + 18 + read-write + + + USART1 + desc USART1 + 20 + 20 + read-write + + + USART2 + desc USART2 + 21 + 21 + read-write + + + USART3 + desc USART3 + 22 + 22 + read-write + + + USART4 + desc USART4 + 23 + 23 + read-write + + + USART5 + desc USART5 + 24 + 24 + read-write + + + USART6 + desc USART6 + 25 + 25 + read-write + + + USART7 + desc USART7 + 26 + 26 + read-write + + + USART8 + desc USART8 + 27 + 27 + read-write + + + USART9 + desc USART9 + 28 + 28 + read-write + + + USART10 + desc USART10 + 29 + 29 + read-write + + + + + FCG0PC + desc FCG0PC + 0x10 + 32 + read-write + 0x0 + 0xFFFF0001 + + + PRT0 + desc PRT0 + 0 + 0 + read-write + + + FCG0PCWE + desc FCG0PCWE + 31 + 16 + write-only + + + + + VBATRSTR + desc VBATRSTR + 0x4430 + 8 + read-write + 0x0 + 0xFF + + + VBATCR + desc VBATCR + 0x4440 + 8 + read-write + 0x0 + 0x8F + + + VBTRSD + desc VBTRSD + 0 + 0 + read-write + + + RAMVALID + desc RAMVALID + 1 + 1 + read-write + + + RAMPDF + desc RAMPDF + 2 + 2 + read-write + + + VBATDIVMONE + desc VBATDIVMONE + 3 + 3 + read-write + + + CSDIS + desc CSDIS + 7 + 7 + read-write + + + + + WKTC0 + desc WKTC0 + 0x4450 + 8 + read-write + 0x0 + 0xFF + + + WKTMCMP + desc WKTMCMP + 7 + 0 + read-write + + + + + WKTC1 + desc WKTC1 + 0x4454 + 8 + read-write + 0x0 + 0xF + + + WKTMCMP + desc WKTMCMP + 3 + 0 + read-write + + + + + WKTC2 + desc WKTC2 + 0x4458 + 8 + read-write + 0x0 + 0xF0 + + + WKOVF + desc WKOVF + 4 + 4 + read-write + + + WKCKS + desc WKCKS + 6 + 5 + read-write + + + WKTCE + desc WKTCE + 7 + 7 + read-write + + + + + BKR0 + desc BKR0 + 0x4600 + 8 + read-write + 0x0 + 0xFF + + + BKR1 + desc BKR1 + 0x4604 + 8 + read-write + 0x0 + 0xFF + + + BKR2 + desc BKR2 + 0x4608 + 8 + read-write + 0x0 + 0xFF + + + BKR3 + desc BKR3 + 0x460C + 8 + read-write + 0x0 + 0xFF + + + BKR4 + desc BKR4 + 0x4610 + 8 + read-write + 0x0 + 0xFF + + + BKR5 + desc BKR5 + 0x4614 + 8 + read-write + 0x0 + 0xFF + + + BKR6 + desc BKR6 + 0x4618 + 8 + read-write + 0x0 + 0xFF + + + BKR7 + desc BKR7 + 0x461C + 8 + read-write + 0x0 + 0xFF + + + BKR8 + desc BKR8 + 0x4620 + 8 + read-write + 0x0 + 0xFF + + + BKR9 + desc BKR9 + 0x4624 + 8 + read-write + 0x0 + 0xFF + + + BKR10 + desc BKR10 + 0x4628 + 8 + read-write + 0x0 + 0xFF + + + BKR11 + desc BKR11 + 0x462C + 8 + read-write + 0x0 + 0xFF + + + BKR12 + desc BKR12 + 0x4630 + 8 + read-write + 0x0 + 0xFF + + + BKR13 + desc BKR13 + 0x4634 + 8 + read-write + 0x0 + 0xFF + + + BKR14 + desc BKR14 + 0x4638 + 8 + read-write + 0x0 + 0xFF + + + BKR15 + desc BKR15 + 0x463C + 8 + read-write + 0x0 + 0xFF + + + BKR16 + desc BKR16 + 0x4640 + 8 + read-write + 0x0 + 0xFF + + + BKR17 + desc BKR17 + 0x4644 + 8 + read-write + 0x0 + 0xFF + + + BKR18 + desc BKR18 + 0x4648 + 8 + read-write + 0x0 + 0xFF + + + BKR19 + desc BKR19 + 0x464C + 8 + read-write + 0x0 + 0xFF + + + BKR20 + desc BKR20 + 0x4650 + 8 + read-write + 0x0 + 0xFF + + + BKR21 + desc BKR21 + 0x4654 + 8 + read-write + 0x0 + 0xFF + + + BKR22 + desc BKR22 + 0x4658 + 8 + read-write + 0x0 + 0xFF + + + BKR23 + desc BKR23 + 0x465C + 8 + read-write + 0x0 + 0xFF + + + BKR24 + desc BKR24 + 0x4660 + 8 + read-write + 0x0 + 0xFF + + + BKR25 + desc BKR25 + 0x4664 + 8 + read-write + 0x0 + 0xFF + + + BKR26 + desc BKR26 + 0x4668 + 8 + read-write + 0x0 + 0xFF + + + BKR27 + desc BKR27 + 0x466C + 8 + read-write + 0x0 + 0xFF + + + BKR28 + desc BKR28 + 0x4670 + 8 + read-write + 0x0 + 0xFF + + + BKR29 + desc BKR29 + 0x4674 + 8 + read-write + 0x0 + 0xFF + + + BKR30 + desc BKR30 + 0x4678 + 8 + read-write + 0x0 + 0xFF + + + BKR31 + desc BKR31 + 0x467C + 8 + read-write + 0x0 + 0xFF + + + BKR32 + desc BKR32 + 0x4680 + 8 + read-write + 0x0 + 0xFF + + + BKR33 + desc BKR33 + 0x4684 + 8 + read-write + 0x0 + 0xFF + + + BKR34 + desc BKR34 + 0x4688 + 8 + read-write + 0x0 + 0xFF + + + BKR35 + desc BKR35 + 0x468C + 8 + read-write + 0x0 + 0xFF + + + BKR36 + desc BKR36 + 0x4690 + 8 + read-write + 0x0 + 0xFF + + + BKR37 + desc BKR37 + 0x4694 + 8 + read-write + 0x0 + 0xFF + + + BKR38 + desc BKR38 + 0x4698 + 8 + read-write + 0x0 + 0xFF + + + BKR39 + desc BKR39 + 0x469C + 8 + read-write + 0x0 + 0xFF + + + BKR40 + desc BKR40 + 0x46A0 + 8 + read-write + 0x0 + 0xFF + + + BKR41 + desc BKR41 + 0x46A4 + 8 + read-write + 0x0 + 0xFF + + + BKR42 + desc BKR42 + 0x46A8 + 8 + read-write + 0x0 + 0xFF + + + BKR43 + desc BKR43 + 0x46AC + 8 + read-write + 0x0 + 0xFF + + + BKR44 + desc BKR44 + 0x46B0 + 8 + read-write + 0x0 + 0xFF + + + BKR45 + desc BKR45 + 0x46B4 + 8 + read-write + 0x0 + 0xFF + + + BKR46 + desc BKR46 + 0x46B8 + 8 + read-write + 0x0 + 0xFF + + + BKR47 + desc BKR47 + 0x46BC + 8 + read-write + 0x0 + 0xFF + + + BKR48 + desc BKR48 + 0x46C0 + 8 + read-write + 0x0 + 0xFF + + + BKR49 + desc BKR49 + 0x46C4 + 8 + read-write + 0x0 + 0xFF + + + BKR50 + desc BKR50 + 0x46C8 + 8 + read-write + 0x0 + 0xFF + + + BKR51 + desc BKR51 + 0x46CC + 8 + read-write + 0x0 + 0xFF + + + BKR52 + desc BKR52 + 0x46D0 + 8 + read-write + 0x0 + 0xFF + + + BKR53 + desc BKR53 + 0x46D4 + 8 + read-write + 0x0 + 0xFF + + + BKR54 + desc BKR54 + 0x46D8 + 8 + read-write + 0x0 + 0xFF + + + BKR55 + desc BKR55 + 0x46DC + 8 + read-write + 0x0 + 0xFF + + + BKR56 + desc BKR56 + 0x46E0 + 8 + read-write + 0x0 + 0xFF + + + BKR57 + desc BKR57 + 0x46E4 + 8 + read-write + 0x0 + 0xFF + + + BKR58 + desc BKR58 + 0x46E8 + 8 + read-write + 0x0 + 0xFF + + + BKR59 + desc BKR59 + 0x46EC + 8 + read-write + 0x0 + 0xFF + + + BKR60 + desc BKR60 + 0x46F0 + 8 + read-write + 0x0 + 0xFF + + + BKR61 + desc BKR61 + 0x46F4 + 8 + read-write + 0x0 + 0xFF + + + BKR62 + desc BKR62 + 0x46F8 + 8 + read-write + 0x0 + 0xFF + + + BKR63 + desc BKR63 + 0x46FC + 8 + read-write + 0x0 + 0xFF + + + BKR64 + desc BKR64 + 0x4700 + 8 + read-write + 0x0 + 0xFF + + + BKR65 + desc BKR65 + 0x4704 + 8 + read-write + 0x0 + 0xFF + + + BKR66 + desc BKR66 + 0x4708 + 8 + read-write + 0x0 + 0xFF + + + BKR67 + desc BKR67 + 0x470C + 8 + read-write + 0x0 + 0xFF + + + BKR68 + desc BKR68 + 0x4710 + 8 + read-write + 0x0 + 0xFF + + + BKR69 + desc BKR69 + 0x4714 + 8 + read-write + 0x0 + 0xFF + + + BKR70 + desc BKR70 + 0x4718 + 8 + read-write + 0x0 + 0xFF + + + BKR71 + desc BKR71 + 0x471C + 8 + read-write + 0x0 + 0xFF + + + BKR72 + desc BKR72 + 0x4720 + 8 + read-write + 0x0 + 0xFF + + + BKR73 + desc BKR73 + 0x4724 + 8 + read-write + 0x0 + 0xFF + + + BKR74 + desc BKR74 + 0x4728 + 8 + read-write + 0x0 + 0xFF + + + BKR75 + desc BKR75 + 0x472C + 8 + read-write + 0x0 + 0xFF + + + BKR76 + desc BKR76 + 0x4730 + 8 + read-write + 0x0 + 0xFF + + + BKR77 + desc BKR77 + 0x4734 + 8 + read-write + 0x0 + 0xFF + + + BKR78 + desc BKR78 + 0x4738 + 8 + read-write + 0x0 + 0xFF + + + BKR79 + desc BKR79 + 0x473C + 8 + read-write + 0x0 + 0xFF + + + BKR80 + desc BKR80 + 0x4740 + 8 + read-write + 0x0 + 0xFF + + + BKR81 + desc BKR81 + 0x4744 + 8 + read-write + 0x0 + 0xFF + + + BKR82 + desc BKR82 + 0x4748 + 8 + read-write + 0x0 + 0xFF + + + BKR83 + desc BKR83 + 0x474C + 8 + read-write + 0x0 + 0xFF + + + BKR84 + desc BKR84 + 0x4750 + 8 + read-write + 0x0 + 0xFF + + + BKR85 + desc BKR85 + 0x4754 + 8 + read-write + 0x0 + 0xFF + + + BKR86 + desc BKR86 + 0x4758 + 8 + read-write + 0x0 + 0xFF + + + BKR87 + desc BKR87 + 0x475C + 8 + read-write + 0x0 + 0xFF + + + BKR88 + desc BKR88 + 0x4760 + 8 + read-write + 0x0 + 0xFF + + + BKR89 + desc BKR89 + 0x4764 + 8 + read-write + 0x0 + 0xFF + + + BKR90 + desc BKR90 + 0x4768 + 8 + read-write + 0x0 + 0xFF + + + BKR91 + desc BKR91 + 0x476C + 8 + read-write + 0x0 + 0xFF + + + BKR92 + desc BKR92 + 0x4770 + 8 + read-write + 0x0 + 0xFF + + + BKR93 + desc BKR93 + 0x4774 + 8 + read-write + 0x0 + 0xFF + + + BKR94 + desc BKR94 + 0x4778 + 8 + read-write + 0x0 + 0xFF + + + BKR95 + desc BKR95 + 0x477C + 8 + read-write + 0x0 + 0xFF + + + BKR96 + desc BKR96 + 0x4780 + 8 + read-write + 0x0 + 0xFF + + + BKR97 + desc BKR97 + 0x4784 + 8 + read-write + 0x0 + 0xFF + + + BKR98 + desc BKR98 + 0x4788 + 8 + read-write + 0x0 + 0xFF + + + BKR99 + desc BKR99 + 0x478C + 8 + read-write + 0x0 + 0xFF + + + BKR100 + desc BKR100 + 0x4790 + 8 + read-write + 0x0 + 0xFF + + + BKR101 + desc BKR101 + 0x4794 + 8 + read-write + 0x0 + 0xFF + + + BKR102 + desc BKR102 + 0x4798 + 8 + read-write + 0x0 + 0xFF + + + BKR103 + desc BKR103 + 0x479C + 8 + read-write + 0x0 + 0xFF + + + BKR104 + desc BKR104 + 0x47A0 + 8 + read-write + 0x0 + 0xFF + + + BKR105 + desc BKR105 + 0x47A4 + 8 + read-write + 0x0 + 0xFF + + + BKR106 + desc BKR106 + 0x47A8 + 8 + read-write + 0x0 + 0xFF + + + BKR107 + desc BKR107 + 0x47AC + 8 + read-write + 0x0 + 0xFF + + + BKR108 + desc BKR108 + 0x47B0 + 8 + read-write + 0x0 + 0xFF + + + BKR109 + desc BKR109 + 0x47B4 + 8 + read-write + 0x0 + 0xFF + + + BKR110 + desc BKR110 + 0x47B8 + 8 + read-write + 0x0 + 0xFF + + + BKR111 + desc BKR111 + 0x47BC + 8 + read-write + 0x0 + 0xFF + + + BKR112 + desc BKR112 + 0x47C0 + 8 + read-write + 0x0 + 0xFF + + + BKR113 + desc BKR113 + 0x47C4 + 8 + read-write + 0x0 + 0xFF + + + BKR114 + desc BKR114 + 0x47C8 + 8 + read-write + 0x0 + 0xFF + + + BKR115 + desc BKR115 + 0x47CC + 8 + read-write + 0x0 + 0xFF + + + BKR116 + desc BKR116 + 0x47D0 + 8 + read-write + 0x0 + 0xFF + + + BKR117 + desc BKR117 + 0x47D4 + 8 + read-write + 0x0 + 0xFF + + + BKR118 + desc BKR118 + 0x47D8 + 8 + read-write + 0x0 + 0xFF + + + BKR119 + desc BKR119 + 0x47DC + 8 + read-write + 0x0 + 0xFF + + + BKR120 + desc BKR120 + 0x47E0 + 8 + read-write + 0x0 + 0xFF + + + BKR121 + desc BKR121 + 0x47E4 + 8 + read-write + 0x0 + 0xFF + + + BKR122 + desc BKR122 + 0x47E8 + 8 + read-write + 0x0 + 0xFF + + + BKR123 + desc BKR123 + 0x47EC + 8 + read-write + 0x0 + 0xFF + + + BKR124 + desc BKR124 + 0x47F0 + 8 + read-write + 0x0 + 0xFF + + + BKR125 + desc BKR125 + 0x47F4 + 8 + read-write + 0x0 + 0xFF + + + BKR126 + desc BKR126 + 0x47F8 + 8 + read-write + 0x0 + 0xFF + + + BKR127 + desc BKR127 + 0x47FC + 8 + read-write + 0x0 + 0xFF + + + PWRC0 + desc PWRC0 + 0x4C00 + 8 + read-write + 0x0 + 0xBB + + + PDMDS + desc PDMDS + 1 + 0 + read-write + + + IORTN + desc IORTN + 5 + 4 + read-write + + + PWDN + desc PWDN + 7 + 7 + read-write + + + + + PWRC1 + desc PWRC1 + 0x4C04 + 8 + read-write + 0x0 + 0xCF + + + VPLLSD + desc VPLLSD + 1 + 0 + read-write + + + VHRCSD + desc VHRCSD + 2 + 2 + read-write + + + PDTS + desc PDTS + 3 + 3 + read-write + + + STPDAS + desc STPDAS + 7 + 6 + read-write + + + + + PWRC2 + desc PWRC2 + 0x4C08 + 8 + read-write + 0xFF + 0x3F + + + DDAS + desc DDAS + 3 + 0 + read-write + + + DVS + desc DVS + 5 + 4 + read-write + + + + + PWRC3 + desc PWRC3 + 0x4C0C + 8 + read-write + 0xFF + 0xFF + + + DDAS + desc DDAS + 7 + 0 + read-write + + + + + PWRC4 + desc PWRC4 + 0x4C10 + 8 + read-write + 0x0 + 0xD3 + + + VBATREFSEL + desc VBATREFSEL + 0 + 0 + read-write + + + VBATME + desc VBATME + 1 + 1 + read-write + + + VBATMON + desc VBATMON + 4 + 4 + read-write + + + ADBUFS + desc ADBUFS + 6 + 6 + read-write + + + ADBUFE + desc ADBUFE + 7 + 7 + read-write + + + + + PVDCR0 + desc PVDCR0 + 0x4C14 + 8 + read-write + 0x0 + 0x61 + + + EXVCCINEN + desc EXVCCINEN + 0 + 0 + read-write + + + PVD1EN + desc PVD1EN + 5 + 5 + read-write + + + PVD2EN + desc PVD2EN + 6 + 6 + read-write + + + + + PVDCR1 + desc PVDCR1 + 0x4C18 + 8 + read-write + 0x0 + 0x77 + + + PVD1IRE + desc PVD1IRE + 0 + 0 + read-write + + + PVD1IRS + desc PVD1IRS + 1 + 1 + read-write + + + PVD1CMPOE + desc PVD1CMPOE + 2 + 2 + read-write + + + PVD2IRE + desc PVD2IRE + 4 + 4 + read-write + + + PVD2IRS + desc PVD2IRS + 5 + 5 + read-write + + + PVD2CMPOE + desc PVD2CMPOE + 6 + 6 + read-write + + + + + PVDFCR + desc PVDFCR + 0x4C1C + 8 + read-write + 0x11 + 0x77 + + + PVD1NFDIS + desc PVD1NFDIS + 0 + 0 + read-write + + + PVD1NFCKS + desc PVD1NFCKS + 2 + 1 + read-write + + + PVD2NFDIS + desc PVD2NFDIS + 4 + 4 + read-write + + + PVD2NFCKS + desc PVD2NFCKS + 6 + 5 + read-write + + + + + PVDLCR + desc PVDLCR + 0x4C20 + 8 + read-write + 0x0 + 0x77 + + + PVD1LVL + desc PVD1LVL + 2 + 0 + read-write + + + PVD2LVL + desc PVD2LVL + 6 + 4 + read-write + + + + + PDWKE0 + desc PDWKE0 + 0x4C28 + 8 + read-write + 0x0 + 0xFF + + + WKE00 + desc WKE00 + 0 + 0 + read-write + + + WKE01 + desc WKE01 + 1 + 1 + read-write + + + WKE02 + desc WKE02 + 2 + 2 + read-write + + + WKE03 + desc WKE03 + 3 + 3 + read-write + + + WKE10 + desc WKE10 + 4 + 4 + read-write + + + WKE11 + desc WKE11 + 5 + 5 + read-write + + + WKE12 + desc WKE12 + 6 + 6 + read-write + + + WKE13 + desc WKE13 + 7 + 7 + read-write + + + + + PDWKE1 + desc PDWKE1 + 0x4C2C + 8 + read-write + 0x0 + 0xFF + + + WKE20 + desc WKE20 + 0 + 0 + read-write + + + WKE21 + desc WKE21 + 1 + 1 + read-write + + + WKE22 + desc WKE22 + 2 + 2 + read-write + + + WKE23 + desc WKE23 + 3 + 3 + read-write + + + WKE30 + desc WKE30 + 4 + 4 + read-write + + + WKE31 + desc WKE31 + 5 + 5 + read-write + + + WKE32 + desc WKE32 + 6 + 6 + read-write + + + WKE33 + desc WKE33 + 7 + 7 + read-write + + + + + PDWKE2 + desc PDWKE2 + 0x4C30 + 8 + read-write + 0x0 + 0xF3 + + + VD1WKE + desc VD1WKE + 0 + 0 + read-write + + + VD2WKE + desc VD2WKE + 1 + 1 + read-write + + + RTCPRDWKE + desc RTCPRDWKE + 4 + 4 + read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0x4C34 + 8 + read-write + 0x0 + 0x3F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0x4C38 + 8 + read-write + 0x0 + 0x3F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0x4C3C + 8 + read-write + 0x0 + 0xF8 + + + RXD0WKF + desc RXD0WKF + 3 + 3 + read-write + + + RTCPRDWKF + desc RTCPRDWKF + 4 + 4 + read-write + + + RTCALMWKF + desc RTCALMWKF + 5 + 5 + read-write + + + WKTMWKF + desc WKTMWKF + 7 + 7 + read-write + + + + + RAMPC0 + desc RAMPC0 + 0x4CE0 + 32 + read-write + 0x0 + 0x7FF + + + RAMPDC0 + desc RAMPDC0 + 0 + 0 + read-write + + + RAMPDC1 + desc RAMPDC1 + 1 + 1 + read-write + + + RAMPDC2 + desc RAMPDC2 + 2 + 2 + read-write + + + RAMPDC3 + desc RAMPDC3 + 3 + 3 + read-write + + + RAMPDC4 + desc RAMPDC4 + 4 + 4 + read-write + + + RAMPDC5 + desc RAMPDC5 + 5 + 5 + read-write + + + RAMPDC6 + desc RAMPDC6 + 6 + 6 + read-write + + + RAMPDC7 + desc RAMPDC7 + 7 + 7 + read-write + + + RAMPDC8 + desc RAMPDC8 + 8 + 8 + read-write + + + RAMPDC9 + desc RAMPDC9 + 9 + 9 + read-write + + + RAMPDC10 + desc RAMPDC10 + 10 + 10 + read-write + + + + + RAMOPM + desc RAMOPM + 0x4CE4 + 16 + read-write + 0x8043 + 0xFFFF + + + PRAMLPC + desc PRAMLPC + 0x4CE8 + 32 + read-write + 0x0 + 0x3FF + + + PRAMPDC0 + desc PRAMPDC0 + 0 + 0 + read-write + + + PRAMPDC1 + desc PRAMPDC1 + 1 + 1 + read-write + + + PRAMPDC2 + desc PRAMPDC2 + 2 + 2 + read-write + + + PRAMPDC3 + desc PRAMPDC3 + 3 + 3 + read-write + + + PRAMPDC4 + desc PRAMPDC4 + 4 + 4 + read-write + + + PRAMPDC5 + desc PRAMPDC5 + 5 + 5 + read-write + + + PRAMPDC6 + desc PRAMPDC6 + 6 + 6 + read-write + + + PRAMPDC7 + desc PRAMPDC7 + 7 + 7 + read-write + + + PRAMPDC8 + desc PRAMPDC8 + 8 + 8 + read-write + + + PRAMPDC9 + desc PRAMPDC9 + 9 + 9 + read-write + + + + + PVDICR + desc PVDICR + 0x4CF0 + 8 + read-write + 0x0 + 0x77 + + + PVD1NMIS + desc PVD1NMIS + 0 + 0 + read-write + + + PVD1EDGS + desc PVD1EDGS + 2 + 1 + read-write + + + PVD2NMIS + desc PVD2NMIS + 4 + 4 + read-write + + + PVD2EDGS + desc PVD2EDGS + 6 + 5 + read-write + + + + + PVDDSR + desc PVDDSR + 0x4CF4 + 8 + read-write + 0x11 + 0x33 + + + PVD1MON + desc PVD1MON + 0 + 0 + read-write + + + PVD1DETFLG + desc PVD1DETFLG + 1 + 1 + read-write + + + PVD2MON + desc PVD2MON + 4 + 4 + read-write + + + PVD2DETFLG + desc PVD2DETFLG + 5 + 5 + read-write + + + + + STPMCR + desc STPMCR + 0xC00C + 16 + read-write + 0x0 + 0xC003 + + + FLNWT + desc FLNWT + 0 + 0 + read-write + + + CKSMRC + desc CKSMRC + 1 + 1 + read-write + + + EXBUSOE + desc EXBUSOE + 14 + 14 + read-write + + + STOP + desc STOP + 15 + 15 + read-write + + + + + FPRC + desc FPRC + 0xC3FE + 16 + read-write + 0x0 + 0xFF0F + + + FPRCB0 + desc FPRCB0 + 0 + 0 + read-write + + + FPRCB1 + desc FPRCB1 + 1 + 1 + read-write + + + FPRCB2 + desc FPRCB2 + 2 + 2 + read-write + + + FPRCB3 + desc FPRCB3 + 3 + 3 + read-write + + + FPRCWE + desc FPRCWE + 15 + 8 + read-write + + + + + + + QSPI + desc QSPI + 0x9C000000 + + 0x0 + 0x808 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x3F0000 + 0x3F3FFF + + + MDSEL + desc MDSEL + 2 + 0 + read-write + + + PFE + desc PFE + 3 + 3 + read-write + + + PFSAE + desc PFSAE + 4 + 4 + read-write + + + DCOME + desc DCOME + 5 + 5 + read-write + + + XIPE + desc XIPE + 6 + 6 + read-write + + + SPIMD3 + desc SPIMD3 + 7 + 7 + read-write + + + IPRSL + desc IPRSL + 9 + 8 + read-write + + + APRSL + desc APRSL + 11 + 10 + read-write + + + DPRSL + desc DPRSL + 13 + 12 + read-write + + + DIV + desc DIV + 21 + 16 + read-write + + + + + CSCR + desc CSCR + 0x4 + 32 + read-write + 0xF + 0x3F + + + SSHW + desc SSHW + 3 + 0 + read-write + + + SSNW + desc SSNW + 5 + 4 + read-write + + + + + FCR + desc FCR + 0x8 + 32 + read-write + 0x80B3 + 0x8F77 + + + AWSL + desc AWSL + 1 + 0 + read-write + + + FOUR_BIC + desc FOUR_BIC + 2 + 2 + read-write + + + SSNHD + desc SSNHD + 4 + 4 + read-write + + + SSNLD + desc SSNLD + 5 + 5 + read-write + + + WPOL + desc WPOL + 6 + 6 + read-write + + + DMCYCN + desc DMCYCN + 11 + 8 + read-write + + + DUTY + desc DUTY + 15 + 15 + read-write + + + + + SR + desc SR + 0xC + 32 + read-write + 0x8000 + 0xDFC1 + + + BUSY + desc BUSY + 0 + 0 + read-write + + + XIPF + desc XIPF + 6 + 6 + read-write + + + RAER + desc RAER + 7 + 7 + read-write + + + PFNUM + desc PFNUM + 12 + 8 + read-write + + + PFFUL + desc PFFUL + 14 + 14 + read-write + + + PFAN + desc PFAN + 15 + 15 + read-write + + + + + DCOM + desc DCOM + 0x10 + 32 + read-write + 0x0 + 0xFF + + + DCOM + desc DCOM + 7 + 0 + read-write + + + + + CCMD + desc CCMD + 0x14 + 32 + read-write + 0x0 + 0xFF + + + RIC + desc RIC + 7 + 0 + read-write + + + + + XCMD + desc XCMD + 0x18 + 32 + read-write + 0xFF + 0xFF + + + XIPMC + desc XIPMC + 7 + 0 + read-write + + + + + SR2 + desc SR2 + 0x24 + 32 + write-only + 0x0 + 0x80 + + + RAERCLR + desc RAERCLR + 7 + 7 + write-only + + + + + EXAR + desc EXAR + 0x804 + 32 + read-write + 0x0 + 0xFC000000 + + + EXADR + desc EXADR + 31 + 26 + read-write + + + + + + + RMU + desc RMU + 0x4004CC00 + + 0x0 + 0x100 + + + + PRSTCR0 + desc PRSTCR0 + 0xF8 + 8 + read-write + 0x40 + 0x20 + + + LKUPREN + desc LKUPREN + 5 + 5 + read-write + + + + + RSTF0 + desc RSTF0 + 0xFC + 32 + read-write + 0x2 + 0xC0007FFF + + + PORF + desc PORF + 0 + 0 + read-write + + + PINRF + desc PINRF + 1 + 1 + read-write + + + BORF + desc BORF + 2 + 2 + read-write + + + PVD1RF + desc PVD1RF + 3 + 3 + read-write + + + PVD2RF + desc PVD2RF + 4 + 4 + read-write + + + WDRF + desc WDRF + 5 + 5 + read-write + + + SWDRF + desc SWDRF + 6 + 6 + read-write + + + PDRF + desc PDRF + 7 + 7 + read-write + + + SWRF + desc SWRF + 8 + 8 + read-write + + + MPUERF + desc MPUERF + 9 + 9 + read-write + + + RAPERF + desc RAPERF + 10 + 10 + read-write + + + RAECRF + desc RAECRF + 11 + 11 + read-write + + + CKFERF + desc CKFERF + 12 + 12 + read-write + + + XTALERF + desc XTALERF + 13 + 13 + read-write + + + LKUPRF + desc LKUPRF + 14 + 14 + read-write + + + MULTIRF + desc MULTIRF + 30 + 30 + read-write + + + CLRF + desc CLRF + 31 + 31 + read-write + + + + + + + RTC + desc RTC + 0x4004C000 + + 0x0 + 0x60 + + + + CR0 + desc CR0 + 0x0 + 8 + read-write + 0x0 + 0x1 + + + RESET + desc RESET + 0 + 0 + read-write + + + + + CR1 + desc CR1 + 0x4 + 8 + read-write + 0x0 + 0xEF + + + PRDS + desc PRDS + 2 + 0 + read-write + + + AMPM + desc AMPM + 3 + 3 + read-write + + + ONEHZOE + desc ONEHZOE + 5 + 5 + read-write + + + ONEHZSEL + desc ONEHZSEL + 6 + 6 + read-write + + + START + desc START + 7 + 7 + read-write + + + + + CR2 + desc CR2 + 0x8 + 8 + read-write + 0x0 + 0xEF + + + RWREQ + desc RWREQ + 0 + 0 + read-write + + + RWEN + desc RWEN + 1 + 1 + read-write + + + PRDF + desc PRDF + 2 + 2 + read-write + + + ALMF + desc ALMF + 3 + 3 + read-write + + + PRDIE + desc PRDIE + 5 + 5 + read-write + + + ALMIE + desc ALMIE + 6 + 6 + read-write + + + ALME + desc ALME + 7 + 7 + read-write + + + + + CR3 + desc CR3 + 0xC + 8 + read-write + 0x0 + 0x90 + + + LRCEN + desc LRCEN + 4 + 4 + read-write + + + RCKSEL + desc RCKSEL + 7 + 7 + read-write + + + + + SEC + desc SEC + 0x10 + 8 + read-write + 0x0 + 0x7F + + + SECU + desc SECU + 3 + 0 + read-write + + + SECD + desc SECD + 6 + 4 + read-write + + + + + MIN + desc MIN + 0x14 + 8 + read-write + 0x0 + 0x7F + + + MINU + desc MINU + 3 + 0 + read-write + + + MIND + desc MIND + 6 + 4 + read-write + + + + + HOUR + desc HOUR + 0x18 + 8 + read-write + 0x12 + 0x3F + + + HOURU + desc HOURU + 3 + 0 + read-write + + + HOURD + desc HOURD + 5 + 4 + read-write + + + + + WEEK + desc WEEK + 0x1C + 8 + read-write + 0x0 + 0x7 + + + WEEK + desc WEEK + 2 + 0 + read-write + + + + + DAY + desc DAY + 0x20 + 8 + read-write + 0x0 + 0x3F + + + DAYU + desc DAYU + 3 + 0 + read-write + + + DAYD + desc DAYD + 5 + 4 + read-write + + + + + MON + desc MON + 0x24 + 8 + read-write + 0x0 + 0x1F + + + MON + desc MON + 4 + 0 + read-write + + + + + YEAR + desc YEAR + 0x28 + 8 + read-write + 0x0 + 0xFF + + + YEARU + desc YEARU + 3 + 0 + read-write + + + YEARD + desc YEARD + 7 + 4 + read-write + + + + + ALMMIN + desc ALMMIN + 0x2C + 8 + read-write + 0x12 + 0x7F + + + ALMMINU + desc ALMMINU + 3 + 0 + read-write + + + ALMMIND + desc ALMMIND + 6 + 4 + read-write + + + + + ALMHOUR + desc ALMHOUR + 0x30 + 8 + read-write + 0x0 + 0x3F + + + ALMHOURU + desc ALMHOURU + 3 + 0 + read-write + + + ALMHOURD + desc ALMHOURD + 5 + 4 + read-write + + + + + ALMWEEK + desc ALMWEEK + 0x34 + 8 + read-write + 0x0 + 0x7F + + + ALMWEEK + desc ALMWEEK + 6 + 0 + read-write + + + + + ERRCRH + desc ERRCRH + 0x38 + 8 + read-write + 0x0 + 0x81 + + + COMP8 + desc COMP8 + 0 + 0 + read-write + + + COMPEN + desc COMPEN + 7 + 7 + read-write + + + + + ERRCRL + desc ERRCRL + 0x3C + 8 + read-write + 0x0 + 0xFF + + + COMP + desc COMP + 7 + 0 + read-write + + + + + TPCR0 + desc TPCR0 + 0x40 + 8 + read-write + 0x0 + 0xFF + + + TPCT0 + desc TPCT0 + 1 + 0 + read-write + + + TPNF0 + desc TPNF0 + 3 + 2 + read-write + + + TPRSTE0 + desc TPRSTE0 + 4 + 4 + read-write + + + TPIE0 + desc TPIE0 + 5 + 5 + read-write + + + TSTPE0 + desc TSTPE0 + 6 + 6 + read-write + + + TPEN0 + desc TPEN0 + 7 + 7 + read-write + + + + + TPCR1 + desc TPCR1 + 0x44 + 8 + read-write + 0x0 + 0xFF + + + TPCT1 + desc TPCT1 + 1 + 0 + read-write + + + TPNF1 + desc TPNF1 + 3 + 2 + read-write + + + TPRSTE1 + desc TPRSTE1 + 4 + 4 + read-write + + + TPIE1 + desc TPIE1 + 5 + 5 + read-write + + + TSTPE1 + desc TSTPE1 + 6 + 6 + read-write + + + TPEN1 + desc TPEN1 + 7 + 7 + read-write + + + + + TPSR + desc TPSR + 0x48 + 8 + read-write + 0x0 + 0x7 + + + TPF0 + desc TPF0 + 0 + 0 + read-write + + + TPF1 + desc TPF1 + 1 + 1 + read-write + + + TPOVF + desc TPOVF + 2 + 2 + read-write + + + + + SECTP + desc SECTP + 0x4C + 8 + read-write + 0x0 + 0x7F + + + SECTPU + desc SECTPU + 3 + 0 + read-write + + + SECTPD + desc SECTPD + 6 + 4 + read-write + + + + + MINTP + desc MINTP + 0x50 + 8 + read-write + 0x0 + 0x7F + + + MINTPU + desc MINTPU + 3 + 0 + read-write + + + MINTPD + desc MINTPD + 6 + 4 + read-write + + + + + HOURTP + desc HOURTP + 0x54 + 8 + read-write + 0x0 + 0x3F + + + HOURTPU + desc HOURTPU + 3 + 0 + read-write + + + HOURTPD + desc HOURTPD + 5 + 4 + read-write + + + + + DAYTP + desc DAYTP + 0x58 + 8 + read-write + 0x0 + 0x3F + + + DAYTPU + desc DAYTPU + 3 + 0 + read-write + + + DAYTPD + desc DAYTPD + 5 + 4 + read-write + + + + + MONTP + desc MONTP + 0x5C + 8 + read-write + 0x0 + 0x1F + + + MONTP + desc MONTP + 4 + 0 + read-write + + + + + + + SDIOC1 + desc SDIOC + 0x40070000 + + 0x0 + 0x54 + + + + BLKSIZE + desc BLKSIZE + 0x4 + 16 + read-write + 0x0 + 0xFFF + + + TBS + desc TBS + 11 + 0 + read-write + + + + + BLKCNT + desc BLKCNT + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + ARG0 + desc ARG0 + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + ARG1 + desc ARG1 + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + TRANSMODE + desc TRANSMODE + 0xC + 16 + read-write + 0x0 + 0x3E + + + BCE + desc BCE + 1 + 1 + read-write + + + ATCEN + desc ATCEN + 3 + 2 + read-write + + + DDIR + desc DDIR + 4 + 4 + read-write + + + MULB + desc MULB + 5 + 5 + read-write + + + + + CMD + desc CMD + 0xE + 16 + read-write + 0x0 + 0x3FFB + + + RESTYP + desc RESTYP + 1 + 0 + read-write + + + CCE + desc CCE + 3 + 3 + read-write + + + ICE + desc ICE + 4 + 4 + read-write + + + DAT + desc DAT + 5 + 5 + read-write + + + TYP + desc TYP + 7 + 6 + read-write + + + IDX + desc IDX + 13 + 8 + read-write + + + + + RESP0 + desc RESP0 + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + RESP1 + desc RESP1 + 0x12 + 16 + read-only + 0x0 + 0xFFFF + + + RESP2 + desc RESP2 + 0x14 + 16 + read-only + 0x0 + 0xFFFF + + + RESP3 + desc RESP3 + 0x16 + 16 + read-only + 0x0 + 0xFFFF + + + RESP4 + desc RESP4 + 0x18 + 16 + read-only + 0x0 + 0xFFFF + + + RESP5 + desc RESP5 + 0x1A + 16 + read-only + 0x0 + 0xFFFF + + + RESP6 + desc RESP6 + 0x1C + 16 + read-only + 0x0 + 0xFFFF + + + RESP7 + desc RESP7 + 0x1E + 16 + read-only + 0x0 + 0xFFFF + + + BUF0 + desc BUF0 + 0x20 + 16 + read-write + 0x0 + 0xFFFF + + + BUF1 + desc BUF1 + 0x22 + 16 + read-write + 0x0 + 0xFFFF + + + PSTAT + desc PSTAT + 0x24 + 32 + read-only + 0x0 + 0x1FF0F07 + + + CIC + desc CIC + 0 + 0 + read-only + + + CID + desc CID + 1 + 1 + read-only + + + DA + desc DA + 2 + 2 + read-only + + + WTA + desc WTA + 8 + 8 + read-only + + + RTA + desc RTA + 9 + 9 + read-only + + + BWE + desc BWE + 10 + 10 + read-only + + + BRE + desc BRE + 11 + 11 + read-only + + + CIN + desc CIN + 16 + 16 + read-only + + + CSS + desc CSS + 17 + 17 + read-only + + + CDL + desc CDL + 18 + 18 + read-only + + + WPL + desc WPL + 19 + 19 + read-only + + + DATL + desc DATL + 23 + 20 + read-only + + + CMDL + desc CMDL + 24 + 24 + read-only + + + + + HOSTCON + desc HOSTCON + 0x28 + 8 + read-write + 0x0 + 0xE6 + + + DW + desc DW + 1 + 1 + read-write + + + HSEN + desc HSEN + 2 + 2 + read-write + + + EXDW + desc EXDW + 5 + 5 + read-write + + + CDTL + desc CDTL + 6 + 6 + read-write + + + CDSS + desc CDSS + 7 + 7 + read-write + + + + + PWRCON + desc PWRCON + 0x29 + 8 + read-write + 0x0 + 0x1 + + + PWON + desc PWON + 0 + 0 + read-write + + + + + BLKGPCON + desc BLKGPCON + 0x2A + 8 + read-write + 0x0 + 0xF + + + SABGR + desc SABGR + 0 + 0 + read-write + + + CR + desc CR + 1 + 1 + read-write + + + RWC + desc RWC + 2 + 2 + read-write + + + IABG + desc IABG + 3 + 3 + read-write + + + + + CLKCON + desc CLKCON + 0x2C + 16 + read-write + 0x2 + 0xFF05 + + + ICE + desc ICE + 0 + 0 + read-write + + + CE + desc CE + 2 + 2 + read-write + + + FS + desc FS + 15 + 8 + read-write + + + + + TOUTCON + desc TOUTCON + 0x2E + 8 + read-write + 0x0 + 0xF + + + DTO + desc DTO + 3 + 0 + read-write + + + + + SFTRST + desc SFTRST + 0x2F + 8 + read-write + 0x0 + 0x7 + + + RSTA + desc RSTA + 0 + 0 + read-write + + + RSTC + desc RSTC + 1 + 1 + read-write + + + RSTD + desc RSTD + 2 + 2 + read-write + + + + + NORINTST + desc NORINTST + 0x30 + 16 + read-write + 0x0 + 0x81F7 + + + CC + desc CC + 0 + 0 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + BGE + desc BGE + 2 + 2 + read-write + + + BWR + desc BWR + 4 + 4 + read-write + + + BRR + desc BRR + 5 + 5 + read-write + + + CIST + desc CIST + 6 + 6 + read-write + + + CRM + desc CRM + 7 + 7 + read-write + + + CINT + desc CINT + 8 + 8 + read-only + + + EI + desc EI + 15 + 15 + read-only + + + + + ERRINTST + desc ERRINTST + 0x32 + 16 + read-write + 0x0 + 0x17F + + + CTOE + desc CTOE + 0 + 0 + read-write + + + CCE + desc CCE + 1 + 1 + read-write + + + CEBE + desc CEBE + 2 + 2 + read-write + + + CIE + desc CIE + 3 + 3 + read-write + + + DTOE + desc DTOE + 4 + 4 + read-write + + + DCE + desc DCE + 5 + 5 + read-write + + + DEBE + desc DEBE + 6 + 6 + read-write + + + ACE + desc ACE + 8 + 8 + read-write + + + + + NORINTSTEN + desc NORINTSTEN + 0x34 + 16 + read-write + 0x0 + 0x1F7 + + + CCEN + desc CCEN + 0 + 0 + read-write + + + TCEN + desc TCEN + 1 + 1 + read-write + + + BGEEN + desc BGEEN + 2 + 2 + read-write + + + BWREN + desc BWREN + 4 + 4 + read-write + + + BRREN + desc BRREN + 5 + 5 + read-write + + + CISTEN + desc CISTEN + 6 + 6 + read-write + + + CRMEN + desc CRMEN + 7 + 7 + read-write + + + CINTEN + desc CINTEN + 8 + 8 + read-write + + + + + ERRINTSTEN + desc ERRINTSTEN + 0x36 + 16 + read-write + 0x0 + 0x17F + + + CTOEEN + desc CTOEEN + 0 + 0 + read-write + + + CCEEN + desc CCEEN + 1 + 1 + read-write + + + CEBEEN + desc CEBEEN + 2 + 2 + read-write + + + CIEEN + desc CIEEN + 3 + 3 + read-write + + + DTOEEN + desc DTOEEN + 4 + 4 + read-write + + + DCEEN + desc DCEEN + 5 + 5 + read-write + + + DEBEEN + desc DEBEEN + 6 + 6 + read-write + + + ACEEN + desc ACEEN + 8 + 8 + read-write + + + + + NORINTSGEN + desc NORINTSGEN + 0x38 + 16 + read-write + 0x0 + 0x1F7 + + + CCSEN + desc CCSEN + 0 + 0 + read-write + + + TCSEN + desc TCSEN + 1 + 1 + read-write + + + BGESEN + desc BGESEN + 2 + 2 + read-write + + + BWRSEN + desc BWRSEN + 4 + 4 + read-write + + + BRRSEN + desc BRRSEN + 5 + 5 + read-write + + + CISTSEN + desc CISTSEN + 6 + 6 + read-write + + + CRMSEN + desc CRMSEN + 7 + 7 + read-write + + + CINTSEN + desc CINTSEN + 8 + 8 + read-write + + + + + ERRINTSGEN + desc ERRINTSGEN + 0x3A + 16 + read-write + 0x0 + 0x17F + + + CTOESEN + desc CTOESEN + 0 + 0 + read-write + + + CCESEN + desc CCESEN + 1 + 1 + read-write + + + CEBESEN + desc CEBESEN + 2 + 2 + read-write + + + CIESEN + desc CIESEN + 3 + 3 + read-write + + + DTOESEN + desc DTOESEN + 4 + 4 + read-write + + + DCESEN + desc DCESEN + 5 + 5 + read-write + + + DEBESEN + desc DEBESEN + 6 + 6 + read-write + + + ACESEN + desc ACESEN + 8 + 8 + read-write + + + + + ATCERRST + desc ATCERRST + 0x3C + 16 + read-only + 0x0 + 0x9F + + + NE + desc NE + 0 + 0 + read-only + + + TOE + desc TOE + 1 + 1 + read-only + + + CE + desc CE + 2 + 2 + read-only + + + EBE + desc EBE + 3 + 3 + read-only + + + IE + desc IE + 4 + 4 + read-only + + + CMDE + desc CMDE + 7 + 7 + read-only + + + + + FEA + desc FEA + 0x50 + 16 + write-only + 0x0 + 0x9F + + + FNE + desc FNE + 0 + 0 + write-only + + + FTOE + desc FTOE + 1 + 1 + write-only + + + FCE + desc FCE + 2 + 2 + write-only + + + FEBE + desc FEBE + 3 + 3 + write-only + + + FIE + desc FIE + 4 + 4 + write-only + + + FCMDE + desc FCMDE + 7 + 7 + write-only + + + + + FEE + desc FEE + 0x52 + 16 + write-only + 0x0 + 0x17F + + + FCTOE + desc FCTOE + 0 + 0 + write-only + + + FCCE + desc FCCE + 1 + 1 + write-only + + + FCEBE + desc FCEBE + 2 + 2 + write-only + + + FCIE + desc FCIE + 3 + 3 + write-only + + + FDTOE + desc FDTOE + 4 + 4 + write-only + + + FDCE + desc FDCE + 5 + 5 + write-only + + + FDEBE + desc FDEBE + 6 + 6 + write-only + + + FACE + desc FACE + 8 + 8 + write-only + + + + + + + SDIOC2 + desc SDIOC + 0x40078400 + + 0x0 + 0x54 + + + + SMC + desc SMC + 0x88000000 + + 0x0 + 0x210 + + + + STSR + desc STSR + 0x0 + 32 + read-only + 0x1 + 0x1 + + + STATUS + desc STATUS + 0 + 0 + read-only + + + + + STCR0 + desc STCR0 + 0x8 + 32 + write-only + 0x0 + 0x4 + + + LPWIR + desc LPWIR + 2 + 2 + write-only + + + + + STCR1 + desc STCR1 + 0xC + 32 + write-only + 0x0 + 0x4 + + + LPWOR + desc LPWOR + 2 + 2 + write-only + + + + + CMDR + desc CMDR + 0x10 + 32 + write-only + 0x0 + 0x3FFFFFF + + + CMDADD + desc CMDADD + 19 + 0 + write-only + + + CRES + desc CRES + 20 + 20 + write-only + + + CMD + desc CMD + 22 + 21 + write-only + + + CMDCHIP + desc CMDCHIP + 25 + 23 + write-only + + + + + TMCR + desc TMCR + 0x14 + 32 + write-only + 0x0 + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + write-only + + + T_WC + desc T_WC + 7 + 4 + write-only + + + T_CEOE + desc T_CEOE + 10 + 8 + write-only + + + T_WP + desc T_WP + 14 + 12 + write-only + + + T_PC + desc T_PC + 18 + 16 + write-only + + + T_TR + desc T_TR + 22 + 20 + write-only + + + + + CPCR + desc CPCR + 0x18 + 32 + write-only + 0x0 + 0x1FFF + + + RSYN + desc RSYN + 0 + 0 + write-only + + + RBL + desc RBL + 3 + 1 + write-only + + + WSYN + desc WSYN + 4 + 4 + write-only + + + WBL + desc WBL + 7 + 5 + write-only + + + MW + desc MW + 9 + 8 + write-only + + + BAAS + desc BAAS + 10 + 10 + write-only + + + ADVS + desc ADVS + 11 + 11 + write-only + + + BLSS + desc BLSS + 12 + 12 + write-only + + + + + RFTR + desc RFTR + 0x20 + 32 + read-write + 0x0 + 0xF + + + REFPRD + desc REFPRD + 3 + 0 + read-write + + + + + TMSR0 + desc TMSR0 + 0x100 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR0 + desc CPSR0 + 0x104 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR1 + desc TMSR1 + 0x120 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR1 + desc CPSR1 + 0x124 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR2 + desc TMSR2 + 0x140 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR2 + desc CPSR2 + 0x144 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR3 + desc TMSR3 + 0x160 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR3 + desc CPSR3 + 0x164 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + BACR + desc BACR + 0x200 + 32 + read-write + 0x300 + 0xC010 + + + MUXMD + desc MUXMD + 4 + 4 + read-write + + + CKSEL + desc CKSEL + 15 + 14 + read-write + + + + + CSCR0 + desc CSCR0 + 0x208 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDMSK0 + desc ADDMSK0 + 7 + 0 + read-write + + + ADDMSK1 + desc ADDMSK1 + 15 + 8 + read-write + + + ADDMSK2 + desc ADDMSK2 + 23 + 16 + read-write + + + ADDMSK3 + desc ADDMSK3 + 31 + 24 + read-write + + + + + CSCR1 + desc CSCR1 + 0x20C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDMAT0 + desc ADDMAT0 + 7 + 0 + read-write + + + ADDMAT1 + desc ADDMAT1 + 15 + 8 + read-write + + + ADDMAT2 + desc ADDMAT2 + 23 + 16 + read-write + + + ADDMAT3 + desc ADDMAT3 + 31 + 24 + read-write + + + + + + + SPI1 + desc SPI + 0x4001C000 + + 0x0 + 0x1C + + + + DR + desc DR + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + 0xFFFB + + + SPIMDS + desc SPIMDS + 0 + 0 + read-write + + + TXMDS + desc TXMDS + 1 + 1 + read-write + + + MSTR + desc MSTR + 3 + 3 + read-write + + + SPLPBK + desc SPLPBK + 4 + 4 + read-write + + + SPLPBK2 + desc SPLPBK2 + 5 + 5 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + CSUSPE + desc CSUSPE + 7 + 7 + read-write + + + EIE + desc EIE + 8 + 8 + read-write + + + TXIE + desc TXIE + 9 + 9 + read-write + + + RXIE + desc RXIE + 10 + 10 + read-write + + + IDIE + desc IDIE + 11 + 11 + read-write + + + MODFE + desc MODFE + 12 + 12 + read-write + + + PATE + desc PATE + 13 + 13 + read-write + + + PAOE + desc PAOE + 14 + 14 + read-write + + + PAE + desc PAE + 15 + 15 + read-write + + + + + CFG1 + desc CFG1 + 0xC + 32 + read-write + 0x10 + 0x77700F43 + + + FTHLV + desc FTHLV + 1 + 0 + read-write + + + SPRDTD + desc SPRDTD + 6 + 6 + read-write + + + SS0PV + desc SS0PV + 8 + 8 + read-write + + + SS1PV + desc SS1PV + 9 + 9 + read-write + + + SS2PV + desc SS2PV + 10 + 10 + read-write + + + SS3PV + desc SS3PV + 11 + 11 + read-write + + + MSSI + desc MSSI + 22 + 20 + read-write + + + MSSDL + desc MSSDL + 26 + 24 + read-write + + + MIDI + desc MIDI + 30 + 28 + read-write + + + + + SR + desc SR + 0x14 + 32 + read-write + 0x20 + 0xBF + + + OVRERF + desc OVRERF + 0 + 0 + read-write + + + IDLNF + desc IDLNF + 1 + 1 + read-only + + + MODFERF + desc MODFERF + 2 + 2 + read-write + + + PERF + desc PERF + 3 + 3 + read-write + + + UDRERF + desc UDRERF + 4 + 4 + read-write + + + TDEF + desc TDEF + 5 + 5 + read-only + + + RDFF + desc RDFF + 7 + 7 + read-only + + + + + CFG2 + desc CFG2 + 0x18 + 32 + read-write + 0xF1D + 0xFFFF + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MBR + desc MBR + 4 + 2 + read-write + + + SSA + desc SSA + 7 + 5 + read-write + + + DSIZE + desc DSIZE + 11 + 8 + read-write + + + LSBF + desc LSBF + 12 + 12 + read-write + + + MIDIE + desc MIDIE + 13 + 13 + read-write + + + MSSDLE + desc MSSDLE + 14 + 14 + read-write + + + MSSIE + desc MSSIE + 15 + 15 + read-write + + + + + + + SPI2 + desc SPI + 0x4001C400 + + 0x0 + 0x1C + + + + SPI3 + desc SPI + 0x4001C800 + + 0x0 + 0x1C + + + + SPI4 + desc SPI + 0x40020000 + + 0x0 + 0x1C + + + + SPI5 + desc SPI + 0x40020400 + + 0x0 + 0x1C + + + + SPI6 + desc SPI + 0x40020800 + + 0x0 + 0x1C + + + + SRAMC + desc SRAMC + 0x40050800 + + 0x0 + 0x14 + + + + WTCR + desc WTCR + 0x0 + 32 + read-write + 0x0 + 0x77777777 + + + SRAM123RWT + desc SRAM123RWT + 2 + 0 + read-write + + + SRAM123WWT + desc SRAM123WWT + 6 + 4 + read-write + + + SRAM4RWT + desc SRAM4RWT + 10 + 8 + read-write + + + SRAM4WWT + desc SRAM4WWT + 14 + 12 + read-write + + + SRAMHRWT + desc SRAMHRWT + 18 + 16 + read-write + + + SRAMHWWT + desc SRAMHWWT + 22 + 20 + read-write + + + SRAMBRWT + desc SRAMBRWT + 26 + 24 + read-write + + + SRAMBWWT + desc SRAMBWWT + 30 + 28 + read-write + + + + + WTPR + desc WTPR + 0x4 + 32 + read-write + 0x0 + 0xFF + + + WTPRC + desc WTPRC + 0 + 0 + read-write + + + WTPRKW + desc WTPRKW + 7 + 1 + read-write + + + + + CKCR + desc CKCR + 0x8 + 32 + read-write + 0x0 + 0xF030001 + + + PYOAD + desc PYOAD + 0 + 0 + read-write + + + ECCOAD + desc ECCOAD + 16 + 16 + read-write + + + BECCOAD + desc BECCOAD + 17 + 17 + read-write + + + ECCMOD + desc ECCMOD + 25 + 24 + read-write + + + BECCMOD + desc BECCMOD + 27 + 26 + read-write + + + + + CKPR + desc CKPR + 0xC + 32 + read-write + 0x0 + 0xFF + + + CKPRC + desc CKPRC + 0 + 0 + read-write + + + CKPRKW + desc CKPRKW + 7 + 1 + read-write + + + + + CKSR + desc CKSR + 0x10 + 32 + read-write + 0x0 + 0x1FF + + + SRAM1_PYERR + desc SRAM1_PYERR + 0 + 0 + read-write + + + SRAM2_PYERR + desc SRAM2_PYERR + 1 + 1 + read-write + + + SRAM3_PYERR + desc SRAM3_PYERR + 2 + 2 + read-write + + + SRAMH_PYERR + desc SRAMH_PYERR + 3 + 3 + read-write + + + SRAM4_1ERR + desc SRAM4_1ERR + 4 + 4 + read-write + + + SRAM4_2ERR + desc SRAM4_2ERR + 5 + 5 + read-write + + + SRAMB_1ERR + desc SRAMB_1ERR + 6 + 6 + read-write + + + SRAMB_2ERR + desc SRAMB_2ERR + 7 + 7 + read-write + + + CACHE_PYERR + desc CACHE_PYERR + 8 + 8 + read-write + + + + + + + SWDT + desc SWDT + 0x40049400 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + TMR01 + desc TMR0 + 0x40024000 + + 0x0 + 0x18 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0xF7F7F7F7 + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + INTENA + desc INTENA + 2 + 2 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNSA + desc SYNSA + 8 + 8 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 9 + read-write + + + ASYNCLKA + desc ASYNCLKA + 10 + 10 + read-write + + + HSTAA + desc HSTAA + 12 + 12 + read-write + + + HSTPA + desc HSTPA + 13 + 13 + read-write + + + HCLEA + desc HCLEA + 14 + 14 + read-write + + + HICPA + desc HICPA + 15 + 15 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + INTENB + desc INTENB + 18 + 18 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNSB + desc SYNSB + 24 + 24 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 25 + read-write + + + ASYNCLKB + desc ASYNCLKB + 26 + 26 + read-write + + + HSTAB + desc HSTAB + 28 + 28 + read-write + + + HSTPB + desc HSTPB + 29 + 29 + read-write + + + HCLEB + desc HCLEB + 30 + 30 + read-write + + + HICPB + desc HICPB + 31 + 31 + read-write + + + + + STFLR + desc STFLR + 0x14 + 32 + read-write + 0x0 + 0x10001 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + + + + + TMR02 + desc TMR0 + 0x40024400 + + 0x0 + 0x18 + + + + TMR21 + desc TMR2 + 0x40024800 + + 0x0 + 0x24 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0x3FFB3FFB + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + SYNSA + desc SYNSA + 3 + 3 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 8 + read-write + + + ASYNCLKA + desc ASYNCLKA + 11 + 10 + read-write + + + SYNCLKAT + desc SYNCLKAT + 13 + 12 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + SYNSB + desc SYNSB + 19 + 19 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 24 + read-write + + + ASYNCLKB + desc ASYNCLKB + 27 + 26 + read-write + + + SYNCLKBT + desc SYNCLKBT + 29 + 28 + read-write + + + + + ICONR + desc ICONR + 0x14 + 32 + read-write + 0x0 + 0x30003 + + + CMENA + desc CMENA + 0 + 0 + read-write + + + OVENA + desc OVENA + 1 + 1 + read-write + + + CMENB + desc CMENB + 16 + 16 + read-write + + + OVENB + desc OVENB + 17 + 17 + read-write + + + + + PCONR + desc PCONR + 0x18 + 32 + read-write + 0x0 + 0x713F713F + + + STACA + desc STACA + 1 + 0 + read-write + + + STPCA + desc STPCA + 3 + 2 + read-write + + + CMPCA + desc CMPCA + 5 + 4 + read-write + + + OUTENA + desc OUTENA + 8 + 8 + read-write + + + NOFIENA + desc NOFIENA + 12 + 12 + read-write + + + NOFICKA + desc NOFICKA + 14 + 13 + read-write + + + STACB + desc STACB + 17 + 16 + read-write + + + STPCB + desc STPCB + 19 + 18 + read-write + + + CMPCB + desc CMPCB + 21 + 20 + read-write + + + OUTENB + desc OUTENB + 24 + 24 + read-write + + + NOFIENB + desc NOFIENB + 28 + 28 + read-write + + + NOFICKB + desc NOFICKB + 30 + 29 + read-write + + + + + HCONR + desc HCONR + 0x1C + 32 + read-write + 0x0 + 0x77777777 + + + HSTAA0 + desc HSTAA0 + 0 + 0 + read-write + + + HSTAA1 + desc HSTAA1 + 1 + 1 + read-write + + + HSTAA2 + desc HSTAA2 + 2 + 2 + read-write + + + HSTPA0 + desc HSTPA0 + 4 + 4 + read-write + + + HSTPA1 + desc HSTPA1 + 5 + 5 + read-write + + + HSTPA2 + desc HSTPA2 + 6 + 6 + read-write + + + HCLEA0 + desc HCLEA0 + 8 + 8 + read-write + + + HCLEA1 + desc HCLEA1 + 9 + 9 + read-write + + + HCLEA2 + desc HCLEA2 + 10 + 10 + read-write + + + HICPA0 + desc HICPA0 + 12 + 12 + read-write + + + HICPA1 + desc HICPA1 + 13 + 13 + read-write + + + HICPA2 + desc HICPA2 + 14 + 14 + read-write + + + HSTAB0 + desc HSTAB0 + 16 + 16 + read-write + + + HSTAB1 + desc HSTAB1 + 17 + 17 + read-write + + + HSTAB2 + desc HSTAB2 + 18 + 18 + read-write + + + HSTPB0 + desc HSTPB0 + 20 + 20 + read-write + + + HSTPB1 + desc HSTPB1 + 21 + 21 + read-write + + + HSTPB2 + desc HSTPB2 + 22 + 22 + read-write + + + HCLEB0 + desc HCLEB0 + 24 + 24 + read-write + + + HCLEB1 + desc HCLEB1 + 25 + 25 + read-write + + + HCLEB2 + desc HCLEB2 + 26 + 26 + read-write + + + HICPB0 + desc HICPB0 + 28 + 28 + read-write + + + HICPB1 + desc HICPB1 + 29 + 29 + read-write + + + HICPB2 + desc HICPB2 + 30 + 30 + read-write + + + + + STFLR + desc STFLR + 0x20 + 32 + read-write + 0x0 + 0x1030003 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + OVFA + desc OVFA + 1 + 1 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + OVFB + desc OVFB + 17 + 17 + read-write + + + + + + + TMR22 + desc TMR2 + 0x40024C00 + + 0x0 + 0x24 + + + + TMR23 + desc TMR2 + 0x40025000 + + 0x0 + 0x24 + + + + TMR24 + desc TMR2 + 0x40025400 + + 0x0 + 0x24 + + + + TMR41 + desc TMR4 + 0x40038000 + + 0x0 + 0xE6 + + + + OCCRUH + desc OCCRUH + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRUL + desc OCCRUL + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVH + desc OCCRVH + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVL + desc OCCRVL + 0xE + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWH + desc OCCRWH + 0x12 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWL + desc OCCRWL + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + OCSRU + desc OCSRU + 0x18 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERU + desc OCERU + 0x1A + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRV + desc OCSRV + 0x1C + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERV + desc OCERV + 0x1E + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRW + desc OCSRW + 0x20 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERW + desc OCERW + 0x22 + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCMRHUH + desc OCMRHUH + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLUL + desc OCMRLUL + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHVH + desc OCMRHVH + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLVL + desc OCMRLVL + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHWH + desc OCMRHWH + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLWL + desc OCMRLWL + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + CPSR + desc CPSR + 0x42 + 16 + read-write + 0xFFFF + 0xFFFF + + + CNTR + desc CNTR + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + CCSR + desc CCSR + 0x48 + 16 + read-write + 0x40 + 0xE3FF + + + CKDIV + desc CKDIV + 3 + 0 + read-write + + + CLEAR + desc CLEAR + 4 + 4 + read-write + + + MODE + desc MODE + 5 + 5 + read-write + + + STOP + desc STOP + 6 + 6 + read-write + + + BUFEN + desc BUFEN + 7 + 7 + read-write + + + IRQPEN + desc IRQPEN + 8 + 8 + read-write + + + IRQPF + desc IRQPF + 9 + 9 + read-write + + + IRQZEN + desc IRQZEN + 13 + 13 + read-write + + + IRQZF + desc IRQZF + 14 + 14 + read-write + + + ECKEN + desc ECKEN + 15 + 15 + read-write + + + + + CVPR + desc CVPR + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + ZIM + desc ZIM + 3 + 0 + read-write + + + PIM + desc PIM + 7 + 4 + read-write + + + ZIC + desc ZIC + 11 + 8 + read-only + + + PIC + desc PIC + 15 + 12 + read-only + + + + + PFSRU + desc PFSRU + 0x82 + 16 + read-write + 0x0 + 0xFFFF + + + PDARU + desc PDARU + 0x84 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRU + desc PDBRU + 0x86 + 16 + read-write + 0x0 + 0xFFFF + + + PFSRV + desc PFSRV + 0x8A + 16 + read-write + 0x0 + 0xFFFF + + + PDARV + desc PDARV + 0x8C + 16 + read-write + 0x0 + 0xFFFF + + + PDBRV + desc PDBRV + 0x8E + 16 + read-write + 0x0 + 0xFFFF + + + PFSRW + desc PFSRW + 0x92 + 16 + read-write + 0x0 + 0xFFFF + + + PDARW + desc PDARW + 0x94 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRW + desc PDBRW + 0x96 + 16 + read-write + 0x0 + 0xFFFF + + + POCRU + desc POCRU + 0x98 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRV + desc POCRV + 0x9C + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRW + desc POCRW + 0xA0 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + RCSR + desc RCSR + 0xA4 + 16 + read-write + 0x0 + 0xFFF7 + + + RTIDU + desc RTIDU + 0 + 0 + read-write + + + RTIDV + desc RTIDV + 1 + 1 + read-write + + + RTIDW + desc RTIDW + 2 + 2 + read-write + + + RTIFU + desc RTIFU + 4 + 4 + read-only + + + RTICU + desc RTICU + 5 + 5 + read-write + + + RTEU + desc RTEU + 6 + 6 + read-write + + + RTSU + desc RTSU + 7 + 7 + read-write + + + RTIFV + desc RTIFV + 8 + 8 + read-only + + + RTICV + desc RTICV + 9 + 9 + read-write + + + RTEV + desc RTEV + 10 + 10 + read-write + + + RTSV + desc RTSV + 11 + 11 + read-write + + + RTIFW + desc RTIFW + 12 + 12 + read-only + + + RTICW + desc RTICW + 13 + 13 + read-write + + + RTEW + desc RTEW + 14 + 14 + read-write + + + RTSW + desc RTSW + 15 + 15 + read-write + + + + + SCCRUH + desc SCCRUH + 0xB2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRUL + desc SCCRUL + 0xB6 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVH + desc SCCRVH + 0xBA + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVL + desc SCCRVL + 0xBE + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWH + desc SCCRWH + 0xC2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWL + desc SCCRWL + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + SCSRUH + desc SCSRUH + 0xC8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUH + desc SCMRUH + 0xCA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRUL + desc SCSRUL + 0xCC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUL + desc SCMRUL + 0xCE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVH + desc SCSRVH + 0xD0 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVH + desc SCMRVH + 0xD2 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVL + desc SCSRVL + 0xD4 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVL + desc SCMRVL + 0xD6 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWH + desc SCSRWH + 0xD8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWH + desc SCMRWH + 0xDA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWL + desc SCSRWL + 0xDC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWL + desc SCMRWL + 0xDE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + PSCR + desc PSCR + 0xE0 + 32 + read-write + 0x5550000 + 0xFFF03FF + + + OEUH + desc OEUH + 0 + 0 + read-write + + + OEUL + desc OEUL + 1 + 1 + read-write + + + OEVH + desc OEVH + 2 + 2 + read-write + + + OEVL + desc OEVL + 3 + 3 + read-write + + + OEWH + desc OEWH + 4 + 4 + read-write + + + OEWL + desc OEWL + 5 + 5 + read-write + + + ODT + desc ODT + 7 + 6 + read-write + + + MOE + desc MOE + 8 + 8 + read-write + + + AOE + desc AOE + 9 + 9 + read-write + + + OSUH + desc OSUH + 17 + 16 + read-write + + + OSUL + desc OSUL + 19 + 18 + read-write + + + OSVH + desc OSVH + 21 + 20 + read-write + + + OSVL + desc OSVL + 23 + 22 + read-write + + + OSWH + desc OSWH + 25 + 24 + read-write + + + OSWL + desc OSWL + 27 + 26 + read-write + + + + + SCER + desc SCER + 0xE4 + 16 + read-write + 0xFF00 + 0xF + + + EVTRS + desc EVTRS + 2 + 0 + read-write + + + PCTS + desc PCTS + 3 + 3 + read-write + + + + + + + TMR42 + desc TMR4 + 0x40038400 + + 0x0 + 0xE6 + + + + TMR43 + desc TMR4 + 0x40038800 + + 0x0 + 0xE6 + + + + TMR61 + desc TMR6 + 0x40018000 + + 0x0 + 0x1A0 + + + + CNTER + desc CNTER + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + UPDAR + desc UPDAR + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PERAR + desc PERAR + 0x40 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERBR + desc PERBR + 0x44 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERCR + desc PERCR + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMAR + desc GCMAR + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMBR + desc GCMBR + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMCR + desc GCMCR + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMDR + desc GCMDR + 0x8C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMER + desc GCMER + 0x90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMFR + desc GCMFR + 0x94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMAR + desc SCMAR + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMBR + desc SCMBR + 0xC4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMCR + desc SCMCR + 0xC8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMDR + desc SCMDR + 0xCC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMER + desc SCMER + 0xD0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMFR + desc SCMFR + 0xD4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTUAR + desc DTUAR + 0x100 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTDAR + desc DTDAR + 0x104 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTUBR + desc DTUBR + 0x108 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTDBR + desc DTDBR + 0x10C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCONR + desc GCONR + 0x140 + 32 + read-write + 0x2 + 0xF01F7 + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + OVSTP + desc OVSTP + 8 + 8 + read-write + + + ZMSKREV + desc ZMSKREV + 16 + 16 + read-write + + + ZMSKPOS + desc ZMSKPOS + 17 + 17 + read-write + + + ZMSKVAL + desc ZMSKVAL + 19 + 18 + read-write + + + + + ICONR + desc ICONR + 0x144 + 32 + read-write + 0x0 + 0xF01FF + + + INTENA + desc INTENA + 0 + 0 + read-write + + + INTENB + desc INTENB + 1 + 1 + read-write + + + INTENC + desc INTENC + 2 + 2 + read-write + + + INTEND + desc INTEND + 3 + 3 + read-write + + + INTENE + desc INTENE + 4 + 4 + read-write + + + INTENF + desc INTENF + 5 + 5 + read-write + + + INTENOVF + desc INTENOVF + 6 + 6 + read-write + + + INTENUDF + desc INTENUDF + 7 + 7 + read-write + + + INTENDTE + desc INTENDTE + 8 + 8 + read-write + + + INTENSAU + desc INTENSAU + 16 + 16 + read-write + + + INTENSAD + desc INTENSAD + 17 + 17 + read-write + + + INTENSBU + desc INTENSBU + 18 + 18 + read-write + + + INTENSBD + desc INTENSBD + 19 + 19 + read-write + + + + + BCONR + desc BCONR + 0x148 + 32 + read-write + 0x0 + 0xFF0FFF + + + BENA + desc BENA + 0 + 0 + read-write + + + BSEA + desc BSEA + 1 + 1 + read-write + + + BTRUA + desc BTRUA + 2 + 2 + read-write + + + BTRDA + desc BTRDA + 3 + 3 + read-write + + + BENB + desc BENB + 4 + 4 + read-write + + + BSEB + desc BSEB + 5 + 5 + read-write + + + BTRUB + desc BTRUB + 6 + 6 + read-write + + + BTRDB + desc BTRDB + 7 + 7 + read-write + + + BENP + desc BENP + 8 + 8 + read-write + + + BSEP + desc BSEP + 9 + 9 + read-write + + + BTRUP + desc BTRUP + 10 + 10 + read-write + + + BTRDP + desc BTRDP + 11 + 11 + read-write + + + BENSPA + desc BENSPA + 16 + 16 + read-write + + + BSESPA + desc BSESPA + 17 + 17 + read-write + + + BTRUSPA + desc BTRUSPA + 18 + 18 + read-write + + + BTRDSPA + desc BTRDSPA + 19 + 19 + read-write + + + BENSPB + desc BENSPB + 20 + 20 + read-write + + + BSESPB + desc BSESPB + 21 + 21 + read-write + + + BTRUSPB + desc BTRUSPB + 22 + 22 + read-write + + + BTRDSPB + desc BTRDSPB + 23 + 23 + read-write + + + + + DCONR + desc DCONR + 0x14C + 32 + read-write + 0x0 + 0xF3 + + + DTCEN + desc DTCEN + 0 + 0 + read-write + + + SEPA + desc SEPA + 1 + 1 + read-write + + + DTBENU + desc DTBENU + 4 + 4 + read-write + + + DTBEND + desc DTBEND + 5 + 5 + read-write + + + DTBTRU + desc DTBTRU + 6 + 6 + read-write + + + DTBTRD + desc DTBTRD + 7 + 7 + read-write + + + + + PCNAR + desc PCNAR + 0x154 + 32 + read-write + 0x0 + 0x93F3FFFF + + + STACA + desc STACA + 1 + 0 + read-write + + + STPCA + desc STPCA + 3 + 2 + read-write + + + OVFCA + desc OVFCA + 5 + 4 + read-write + + + UDFCA + desc UDFCA + 7 + 6 + read-write + + + CMAUCA + desc CMAUCA + 9 + 8 + read-write + + + CMADCA + desc CMADCA + 11 + 10 + read-write + + + CMBUCA + desc CMBUCA + 13 + 12 + read-write + + + CMBDCA + desc CMBDCA + 15 + 14 + read-write + + + FORCA + desc FORCA + 17 + 16 + read-write + + + EMBCA + desc EMBCA + 21 + 20 + read-write + + + EMBRA + desc EMBRA + 23 + 22 + read-write + + + EMBSA + desc EMBSA + 25 + 24 + read-write + + + OUTENA + desc OUTENA + 28 + 28 + read-write + + + CAPMDA + desc CAPMDA + 31 + 31 + read-write + + + + + PCNBR + desc PCNBR + 0x158 + 32 + read-write + 0x0 + 0x93F3FFFF + + + STACB + desc STACB + 1 + 0 + read-write + + + STPCB + desc STPCB + 3 + 2 + read-write + + + OVFCB + desc OVFCB + 5 + 4 + read-write + + + UDFCB + desc UDFCB + 7 + 6 + read-write + + + CMAUCB + desc CMAUCB + 9 + 8 + read-write + + + CMADCB + desc CMADCB + 11 + 10 + read-write + + + CMBUCB + desc CMBUCB + 13 + 12 + read-write + + + CMBDCB + desc CMBDCB + 15 + 14 + read-write + + + FORCB + desc FORCB + 17 + 16 + read-write + + + EMBCB + desc EMBCB + 21 + 20 + read-write + + + EMBRB + desc EMBRB + 23 + 22 + read-write + + + EMBSB + desc EMBSB + 25 + 24 + read-write + + + OUTENB + desc OUTENB + 28 + 28 + read-write + + + CAPMDB + desc CAPMDB + 31 + 31 + read-write + + + + + FCNGR + desc FCNGR + 0x15C + 32 + read-write + 0x0 + 0x77 + + + NOFIENGA + desc NOFIENGA + 0 + 0 + read-write + + + NOFICKGA + desc NOFICKGA + 2 + 1 + read-write + + + NOFIENGB + desc NOFIENGB + 4 + 4 + read-write + + + NOFICKGB + desc NOFICKGB + 6 + 5 + read-write + + + + + VPERR + desc VPERR + 0x160 + 32 + read-write + 0x0 + 0x1F0300 + + + SPPERIA + desc SPPERIA + 8 + 8 + read-write + + + SPPERIB + desc SPPERIB + 9 + 9 + read-write + + + PCNTE + desc PCNTE + 17 + 16 + read-write + + + PCNTS + desc PCNTS + 20 + 18 + read-write + + + + + STFLR + desc STFLR + 0x164 + 32 + read-write + 0x80000000 + 0x80E01FFF + + + CMAF + desc CMAF + 0 + 0 + read-write + + + CMBF + desc CMBF + 1 + 1 + read-write + + + CMCF + desc CMCF + 2 + 2 + read-write + + + CMDF + desc CMDF + 3 + 3 + read-write + + + CMEF + desc CMEF + 4 + 4 + read-write + + + CMFF + desc CMFF + 5 + 5 + read-write + + + OVFF + desc OVFF + 6 + 6 + read-write + + + UDFF + desc UDFF + 7 + 7 + read-write + + + DTEF + desc DTEF + 8 + 8 + read-only + + + CMSAUF + desc CMSAUF + 9 + 9 + read-write + + + CMSADF + desc CMSADF + 10 + 10 + read-write + + + CMSBUF + desc CMSBUF + 11 + 11 + read-write + + + CMSBDF + desc CMSBDF + 12 + 12 + read-write + + + VPERNUM + desc VPERNUM + 23 + 21 + read-only + + + DIRF + desc DIRF + 31 + 31 + read-only + + + + + HSTAR + desc HSTAR + 0x180 + 32 + read-write + 0x0 + 0xFF0F8F + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTA3 + desc HSTA3 + 3 + 3 + read-write + + + STAS + desc STAS + 7 + 7 + read-write + + + HSTA8 + desc HSTA8 + 8 + 8 + read-write + + + HSTA9 + desc HSTA9 + 9 + 9 + read-write + + + HSTA10 + desc HSTA10 + 10 + 10 + read-write + + + HSTA11 + desc HSTA11 + 11 + 11 + read-write + + + HSTA16 + desc HSTA16 + 16 + 16 + read-write + + + HSTA17 + desc HSTA17 + 17 + 17 + read-write + + + HSTA18 + desc HSTA18 + 18 + 18 + read-write + + + HSTA19 + desc HSTA19 + 19 + 19 + read-write + + + HSTA20 + desc HSTA20 + 20 + 20 + read-write + + + HSTA21 + desc HSTA21 + 21 + 21 + read-write + + + HSTA22 + desc HSTA22 + 22 + 22 + read-write + + + HSTA23 + desc HSTA23 + 23 + 23 + read-write + + + + + HSTPR + desc HSTPR + 0x184 + 32 + read-write + 0x0 + 0xFF0F8F + + + HSTP0 + desc HSTP0 + 0 + 0 + read-write + + + HSTP1 + desc HSTP1 + 1 + 1 + read-write + + + HSTP2 + desc HSTP2 + 2 + 2 + read-write + + + HSTP3 + desc HSTP3 + 3 + 3 + read-write + + + STPS + desc STPS + 7 + 7 + read-write + + + HSTP8 + desc HSTP8 + 8 + 8 + read-write + + + HSTP9 + desc HSTP9 + 9 + 9 + read-write + + + HSTP10 + desc HSTP10 + 10 + 10 + read-write + + + HSTP11 + desc HSTP11 + 11 + 11 + read-write + + + HSTP16 + desc HSTP16 + 16 + 16 + read-write + + + HSTP17 + desc HSTP17 + 17 + 17 + read-write + + + HSTP18 + desc HSTP18 + 18 + 18 + read-write + + + HSTP19 + desc HSTP19 + 19 + 19 + read-write + + + HSTP20 + desc HSTP20 + 20 + 20 + read-write + + + HSTP21 + desc HSTP21 + 21 + 21 + read-write + + + HSTP22 + desc HSTP22 + 22 + 22 + read-write + + + HSTP23 + desc HSTP23 + 23 + 23 + read-write + + + + + HCLRR + desc HCLRR + 0x188 + 32 + read-write + 0x0 + 0xFF0F8F + + + HCLE0 + desc HCLE0 + 0 + 0 + read-write + + + HCLE1 + desc HCLE1 + 1 + 1 + read-write + + + HCLE2 + desc HCLE2 + 2 + 2 + read-write + + + HCLE3 + desc HCLE3 + 3 + 3 + read-write + + + CLES + desc CLES + 7 + 7 + read-write + + + HCLE8 + desc HCLE8 + 8 + 8 + read-write + + + HCLE9 + desc HCLE9 + 9 + 9 + read-write + + + HCLE10 + desc HCLE10 + 10 + 10 + read-write + + + HCLE11 + desc HCLE11 + 11 + 11 + read-write + + + HCLE16 + desc HCLE16 + 16 + 16 + read-write + + + HCLE17 + desc HCLE17 + 17 + 17 + read-write + + + HCLE18 + desc HCLE18 + 18 + 18 + read-write + + + HCLE19 + desc HCLE19 + 19 + 19 + read-write + + + HCLE20 + desc HCLE20 + 20 + 20 + read-write + + + HCLE21 + desc HCLE21 + 21 + 21 + read-write + + + HCLE22 + desc HCLE22 + 22 + 22 + read-write + + + HCLE23 + desc HCLE23 + 23 + 23 + read-write + + + + + HUPDR + desc HUPDR + 0x18C + 32 + read-write + 0x0 + 0xFF0F8F + + + HUPD0 + desc HUPD0 + 0 + 0 + read-write + + + HUPD1 + desc HUPD1 + 1 + 1 + read-write + + + HUPD2 + desc HUPD2 + 2 + 2 + read-write + + + HUPD3 + desc HUPD3 + 3 + 3 + read-write + + + UPDS + desc UPDS + 7 + 7 + read-write + + + HUPD8 + desc HUPD8 + 8 + 8 + read-write + + + HUPD9 + desc HUPD9 + 9 + 9 + read-write + + + HUPD10 + desc HUPD10 + 10 + 10 + read-write + + + HUPD11 + desc HUPD11 + 11 + 11 + read-write + + + HUPD16 + desc HUPD16 + 16 + 16 + read-write + + + HUPD17 + desc HUPD17 + 17 + 17 + read-write + + + HUPD18 + desc HUPD18 + 18 + 18 + read-write + + + HUPD19 + desc HUPD19 + 19 + 19 + read-write + + + HUPD20 + desc HUPD20 + 20 + 20 + read-write + + + HUPD21 + desc HUPD21 + 21 + 21 + read-write + + + HUPD22 + desc HUPD22 + 22 + 22 + read-write + + + HUPD23 + desc HUPD23 + 23 + 23 + read-write + + + + + HCPAR + desc HCPAR + 0x190 + 32 + read-write + 0x0 + 0xFF0F0F + + + HCPA0 + desc HCPA0 + 0 + 0 + read-write + + + HCPA1 + desc HCPA1 + 1 + 1 + read-write + + + HCPA2 + desc HCPA2 + 2 + 2 + read-write + + + HCPA3 + desc HCPA3 + 3 + 3 + read-write + + + HCPA8 + desc HCPA8 + 8 + 8 + read-write + + + HCPA9 + desc HCPA9 + 9 + 9 + read-write + + + HCPA10 + desc HCPA10 + 10 + 10 + read-write + + + HCPA11 + desc HCPA11 + 11 + 11 + read-write + + + HCPA16 + desc HCPA16 + 16 + 16 + read-write + + + HCPA17 + desc HCPA17 + 17 + 17 + read-write + + + HCPA18 + desc HCPA18 + 18 + 18 + read-write + + + HCPA19 + desc HCPA19 + 19 + 19 + read-write + + + HCPA20 + desc HCPA20 + 20 + 20 + read-write + + + HCPA21 + desc HCPA21 + 21 + 21 + read-write + + + HCPA22 + desc HCPA22 + 22 + 22 + read-write + + + HCPA23 + desc HCPA23 + 23 + 23 + read-write + + + + + HCPBR + desc HCPBR + 0x194 + 32 + read-write + 0x0 + 0xFF0F0F + + + HCPB0 + desc HCPB0 + 0 + 0 + read-write + + + HCPB1 + desc HCPB1 + 1 + 1 + read-write + + + HCPB2 + desc HCPB2 + 2 + 2 + read-write + + + HCPB3 + desc HCPB3 + 3 + 3 + read-write + + + HCPB8 + desc HCPB8 + 8 + 8 + read-write + + + HCPB9 + desc HCPB9 + 9 + 9 + read-write + + + HCPB10 + desc HCPB10 + 10 + 10 + read-write + + + HCPB11 + desc HCPB11 + 11 + 11 + read-write + + + HCPB16 + desc HCPB16 + 16 + 16 + read-write + + + HCPB17 + desc HCPB17 + 17 + 17 + read-write + + + HCPB18 + desc HCPB18 + 18 + 18 + read-write + + + HCPB19 + desc HCPB19 + 19 + 19 + read-write + + + HCPB20 + desc HCPB20 + 20 + 20 + read-write + + + HCPB21 + desc HCPB21 + 21 + 21 + read-write + + + HCPB22 + desc HCPB22 + 22 + 22 + read-write + + + HCPB23 + desc HCPB23 + 23 + 23 + read-write + + + + + HCUPR + desc HCUPR + 0x198 + 32 + read-write + 0x0 + 0xFF0FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP16 + desc HCUP16 + 16 + 16 + read-write + + + HCUP17 + desc HCUP17 + 17 + 17 + read-write + + + HCUP18 + desc HCUP18 + 18 + 18 + read-write + + + HCUP19 + desc HCUP19 + 19 + 19 + read-write + + + HCUP20 + desc HCUP20 + 20 + 20 + read-write + + + HCUP21 + desc HCUP21 + 21 + 21 + read-write + + + HCUP22 + desc HCUP22 + 22 + 22 + read-write + + + HCUP23 + desc HCUP23 + 23 + 23 + read-write + + + + + HCDOR + desc HCDOR + 0x19C + 32 + read-write + 0x0 + 0xFF0FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO16 + desc HCDO16 + 16 + 16 + read-write + + + HCDO17 + desc HCDO17 + 17 + 17 + read-write + + + HCDO18 + desc HCDO18 + 18 + 18 + read-write + + + HCDO19 + desc HCDO19 + 19 + 19 + read-write + + + HCDO20 + desc HCDO20 + 20 + 20 + read-write + + + HCDO21 + desc HCDO21 + 21 + 21 + read-write + + + HCDO22 + desc HCDO22 + 22 + 22 + read-write + + + HCDO23 + desc HCDO23 + 23 + 23 + read-write + + + + + + + TMR62 + desc TMR6 + 0x40018400 + + 0x0 + 0x1A0 + + + + TMR63 + desc TMR6 + 0x40018800 + + 0x0 + 0x1A0 + + + + TMR64 + desc TMR6 + 0x40018C00 + + 0x0 + 0x1A0 + + + + TMR65 + desc TMR6 + 0x40019000 + + 0x0 + 0x1A0 + + + + TMR66 + desc TMR6 + 0x40019400 + + 0x0 + 0x1A0 + + + + TMR67 + desc TMR6 + 0x40019800 + + 0x0 + 0x1A0 + + + + TMR68 + desc TMR6 + 0x40019C00 + + 0x0 + 0x1A0 + + + + TMR6CR + desc TMR6CR + 0x40018000 + TMR61 + + 0x0 + 0x400 + + + + FCNTR + desc FCNTR + 0x3EC + 32 + read-write + 0x0 + 0x7777 + + + NOFIENTA + desc NOFIENTA + 0 + 0 + read-write + + + NOFICKTA + desc NOFICKTA + 2 + 1 + read-write + + + NOFIENTB + desc NOFIENTB + 4 + 4 + read-write + + + NOFICKTB + desc NOFICKTB + 6 + 5 + read-write + + + NOFIENTC + desc NOFIENTC + 8 + 8 + read-write + + + NOFICKTC + desc NOFICKTC + 10 + 9 + read-write + + + NOFIENTD + desc NOFIENTD + 12 + 12 + read-write + + + NOFICKTD + desc NOFICKTD + 14 + 13 + read-write + + + + + SSTAR + desc SSTAR + 0x3F0 + 32 + read-write + 0x0 + 0xFF + + + SSTA1 + desc SSTA1 + 0 + 0 + read-write + + + SSTA2 + desc SSTA2 + 1 + 1 + read-write + + + SSTA3 + desc SSTA3 + 2 + 2 + read-write + + + SSTA4 + desc SSTA4 + 3 + 3 + read-write + + + SSTA5 + desc SSTA5 + 4 + 4 + read-write + + + SSTA6 + desc SSTA6 + 5 + 5 + read-write + + + SSTA7 + desc SSTA7 + 6 + 6 + read-write + + + SSTA8 + desc SSTA8 + 7 + 7 + read-write + + + + + SSTPR + desc SSTPR + 0x3F4 + 32 + read-write + 0x0 + 0xFF + + + SSTP1 + desc SSTP1 + 0 + 0 + read-write + + + SSTP2 + desc SSTP2 + 1 + 1 + read-write + + + SSTP3 + desc SSTP3 + 2 + 2 + read-write + + + SSTP4 + desc SSTP4 + 3 + 3 + read-write + + + SSTP5 + desc SSTP5 + 4 + 4 + read-write + + + SSTP6 + desc SSTP6 + 5 + 5 + read-write + + + SSTP7 + desc SSTP7 + 6 + 6 + read-write + + + SSTP8 + desc SSTP8 + 7 + 7 + read-write + + + + + SCLRR + desc SCLRR + 0x3F8 + 32 + read-write + 0x0 + 0xFF + + + SCLE1 + desc SCLE1 + 0 + 0 + read-write + + + SCLE2 + desc SCLE2 + 1 + 1 + read-write + + + SCLE3 + desc SCLE3 + 2 + 2 + read-write + + + SCLE4 + desc SCLE4 + 3 + 3 + read-write + + + SCLE5 + desc SCLE5 + 4 + 4 + read-write + + + SCLE6 + desc SCLE6 + 5 + 5 + read-write + + + SCLE7 + desc SCLE7 + 6 + 6 + read-write + + + SCLE8 + desc SCLE8 + 7 + 7 + read-write + + + + + SUPDR + desc SUPDR + 0x3FC + 32 + read-write + 0x0 + 0xFF + + + SUPD1 + desc SUPD1 + 0 + 0 + read-write + + + SUPD2 + desc SUPD2 + 1 + 1 + read-write + + + SUPD3 + desc SUPD3 + 2 + 2 + read-write + + + SUPD4 + desc SUPD4 + 3 + 3 + read-write + + + SUPD5 + desc SUPD5 + 4 + 4 + read-write + + + SUPD6 + desc SUPD6 + 5 + 5 + read-write + + + SUPD7 + desc SUPD7 + 6 + 6 + read-write + + + SUPD8 + desc SUPD8 + 7 + 7 + read-write + + + + + + + TMRA1 + desc TMRA + 0x4003A000 + + 0x0 + 0x150 + + + + CNTER + desc CNTER + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 16 + read-write + 0xFFFF + 0xFFFF + + + PER + desc PER + 15 + 0 + read-write + + + + + CMPAR1 + desc CMPAR1 + 0x40 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR2 + desc CMPAR2 + 0x44 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR3 + desc CMPAR3 + 0x48 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR4 + desc CMPAR4 + 0x4C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + BCSTR + desc BCSTR + 0x80 + 16 + read-write + 0x2 + 0xF1FF + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + SYNST + desc SYNST + 3 + 3 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + OVSTP + desc OVSTP + 8 + 8 + read-write + + + ITENOVF + desc ITENOVF + 12 + 12 + read-write + + + ITENUDF + desc ITENUDF + 13 + 13 + read-write + + + OVFF + desc OVFF + 14 + 14 + read-write + + + UDFF + desc UDFF + 15 + 15 + read-write + + + + + HCONR + desc HCONR + 0x84 + 16 + read-write + 0x0 + 0xF777 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTP0 + desc HSTP0 + 4 + 4 + read-write + + + HSTP1 + desc HSTP1 + 5 + 5 + read-write + + + HSTP2 + desc HSTP2 + 6 + 6 + read-write + + + HCLE0 + desc HCLE0 + 8 + 8 + read-write + + + HCLE1 + desc HCLE1 + 9 + 9 + read-write + + + HCLE2 + desc HCLE2 + 10 + 10 + read-write + + + HCLE3 + desc HCLE3 + 12 + 12 + read-write + + + HCLE4 + desc HCLE4 + 13 + 13 + read-write + + + HCLE5 + desc HCLE5 + 14 + 14 + read-write + + + HCLE6 + desc HCLE6 + 15 + 15 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 16 + read-write + 0x0 + 0x1FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP12 + desc HCUP12 + 12 + 12 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 16 + read-write + 0x0 + 0x1FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO12 + desc HCDO12 + 12 + 12 + read-write + + + + + ICONR + desc ICONR + 0x90 + 16 + read-write + 0x0 + 0xF + + + ITEN1 + desc ITEN1 + 0 + 0 + read-write + + + ITEN2 + desc ITEN2 + 1 + 1 + read-write + + + ITEN3 + desc ITEN3 + 2 + 2 + read-write + + + ITEN4 + desc ITEN4 + 3 + 3 + read-write + + + + + ECONR + desc ECONR + 0x94 + 16 + read-write + 0x0 + 0xF + + + ETEN1 + desc ETEN1 + 0 + 0 + read-write + + + ETEN2 + desc ETEN2 + 1 + 1 + read-write + + + ETEN3 + desc ETEN3 + 2 + 2 + read-write + + + ETEN4 + desc ETEN4 + 3 + 3 + read-write + + + + + FCONR + desc FCONR + 0x98 + 16 + read-write + 0x0 + 0x7707 + + + NOFIENTG + desc NOFIENTG + 0 + 0 + read-write + + + NOFICKTG + desc NOFICKTG + 2 + 1 + read-write + + + NOFIENCA + desc NOFIENCA + 8 + 8 + read-write + + + NOFICKCA + desc NOFICKCA + 10 + 9 + read-write + + + NOFIENCB + desc NOFIENCB + 12 + 12 + read-write + + + NOFICKCB + desc NOFICKCB + 14 + 13 + read-write + + + + + STFLR + desc STFLR + 0x9C + 16 + read-write + 0x0 + 0xF + + + CMPF1 + desc CMPF1 + 0 + 0 + read-write + + + CMPF2 + desc CMPF2 + 1 + 1 + read-write + + + CMPF3 + desc CMPF3 + 2 + 2 + read-write + + + CMPF4 + desc CMPF4 + 3 + 3 + read-write + + + + + BCONR1 + desc BCONR1 + 0xC0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR2 + desc BCONR2 + 0xC8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + CCONR1 + desc CCONR1 + 0x100 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR2 + desc CCONR2 + 0x104 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR3 + desc CCONR3 + 0x108 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR4 + desc CCONR4 + 0x10C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + PCONR1 + desc PCONR1 + 0x140 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR2 + desc PCONR2 + 0x144 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR3 + desc PCONR3 + 0x148 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR4 + desc PCONR4 + 0x14C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + + + TMRA10 + desc TMRA + 0x40027400 + + 0x0 + 0x150 + + + + TMRA11 + desc TMRA + 0x40027800 + + 0x0 + 0x150 + + + + TMRA12 + desc TMRA + 0x40027C00 + + 0x0 + 0x150 + + + + TMRA2 + desc TMRA + 0x4003A400 + + 0x0 + 0x150 + + + + TMRA3 + desc TMRA + 0x4003A800 + + 0x0 + 0x150 + + + + TMRA4 + desc TMRA + 0x4003AC00 + + 0x0 + 0x150 + + + + TMRA5 + desc TMRA + 0x40026000 + + 0x0 + 0x150 + + + + TMRA6 + desc TMRA + 0x40026400 + + 0x0 + 0x150 + + + + TMRA7 + desc TMRA + 0x40026800 + + 0x0 + 0x150 + + + + TMRA8 + desc TMRA + 0x40026C00 + + 0x0 + 0x150 + + + + TMRA9 + desc TMRA + 0x40027000 + + 0x0 + 0x150 + + + + TRNG + desc TRNG + 0x40042000 + + 0x0 + 0x14 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EN + desc EN + 0 + 0 + read-write + + + RUN + desc RUN + 1 + 1 + read-write + + + + + MR + desc MR + 0x4 + 32 + read-write + 0x12 + 0x1D + + + LOAD + desc LOAD + 0 + 0 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + + + DR0 + desc DR0 + 0xC + 32 + read-only + 0x8000000 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x10 + 32 + read-only + 0x8000200 + 0xFFFFFFFF + + + + + USART1 + desc USART + 0x4001CC00 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART10 + desc USART10 + 0x40021C00 + + 0x0 + 0x20 + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x106FB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + BE + desc BE + 4 + 4 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + WKUP + desc WKUP + 9 + 9 + read-only + + + LBD + desc LBD + 10 + 10 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFF00 + 0xFF00 + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xD1EB96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CBE + desc CBE + 21 + 21 + read-write + + + CWKUP + desc CWKUP + 22 + 22 + read-write + + + CLBD + desc CLBD + 23 + 23 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x379FF + + + MPE + desc MPE + 0 + 0 + read-write + + + WKUPIE + desc WKUPIE + 1 + 1 + read-write + + + BEIE + desc BEIE + 2 + 2 + read-write + + + BEE + desc BEE + 3 + 3 + read-write + + + LBDIE + desc LBDIE + 4 + 4 + read-write + + + LBDL + desc LBDL + 5 + 5 + read-write + + + SBKL + desc SBKL + 7 + 6 + read-write + + + WKUPE + desc WKUPE + 8 + 8 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + LINEN + desc LINEN + 14 + 14 + read-write + + + SBK + desc SBK + 16 + 16 + read-write + + + SBKM + desc SBKM + 17 + 17 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0x318 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + LOOP + desc LOOP + 4 + 4 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0xF + + + PSC + desc PSC + 1 + 0 + read-write + + + LBMPSC + desc LBMPSC + 3 + 2 + read-write + + + + + LBMC + desc LBMC + 0x1C + 32 + read-only + 0x0 + 0xFFFF + + + LBMC + desc LBMC + 15 + 0 + read-only + + + + + + + USART2 + desc USART + 0x4001D000 + + 0x0 + 0x1C + + + + USART3 + desc USART + 0x4001D400 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x100EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF10B96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART4 + desc USART + 0x4001D800 + + 0x0 + 0x1C + + + + USART5 + desc USART + 0x4001DC00 + + 0x0 + 0x20 + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x106FB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + BE + desc BE + 4 + 4 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + WKUP + desc WKUP + 9 + 9 + read-only + + + LBD + desc LBD + 10 + 10 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFF00 + 0xFF00 + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xD1EB96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CBE + desc CBE + 21 + 21 + read-write + + + CWKUP + desc CWKUP + 22 + 22 + read-write + + + CLBD + desc CLBD + 23 + 23 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x379FF + + + MPE + desc MPE + 0 + 0 + read-write + + + WKUPIE + desc WKUPIE + 1 + 1 + read-write + + + BEIE + desc BEIE + 2 + 2 + read-write + + + BEE + desc BEE + 3 + 3 + read-write + + + LBDIE + desc LBDIE + 4 + 4 + read-write + + + LBDL + desc LBDL + 5 + 5 + read-write + + + SBKL + desc SBKL + 7 + 6 + read-write + + + WKUPE + desc WKUPE + 8 + 8 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + LINEN + desc LINEN + 14 + 14 + read-write + + + SBK + desc SBK + 16 + 16 + read-write + + + SBKM + desc SBKM + 17 + 17 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0x318 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + LOOP + desc LOOP + 4 + 4 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0xF + + + PSC + desc PSC + 1 + 0 + read-write + + + LBMPSC + desc LBMPSC + 3 + 2 + read-write + + + + + LBMC + desc LBMC + 0x1C + 32 + read-only + 0x0 + 0xFFFF + + + LBMC + desc LBMC + 15 + 0 + read-only + + + + + + + USART6 + desc USART6 + 0x40020C00 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART7 + desc USART + 0x40021000 + + 0x0 + 0x1C + + + + USART8 + desc USART + 0x40021400 + + 0x0 + 0x1C + + + + USART9 + desc USART + 0x40021800 + + 0x0 + 0x1C + + + + USBFS + desc USBFS + 0x40080000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0x1440 + 0x60003C47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFF7CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + LPMINT + desc LPMINT + 27 + 27 + read-write + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xFF7CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + LPMINTM + desc LPMINTM + 27 + 27 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x280 + 0x7FF + + + RXFD + desc RXFD + 10 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x2800280 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80280 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + LPMEN + desc LPMEN + 0 + 0 + read-write + + + LPMACK + desc LPMACK + 1 + 1 + read-write + + + BSEL + desc BSEL + 5 + 2 + read-write + + + REMWAKE + desc REMWAKE + 6 + 6 + read-write + + + L1SSEN + desc L1SSEN + 7 + 7 + read-write + + + BESLTHRS + desc BESLTHRS + 11 + 8 + read-write + + + L1DSEN + desc L1DSEN + 12 + 12 + read-write + + + LPMRSP + desc LPMRSP + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RSMOK + desc L1RSMOK + 16 + 16 + read-only + + + LPMCHIDX + desc LPMCHIDX + 20 + 17 + read-write + + + LPMRCNT + desc LPMRCNT + 23 + 21 + read-write + + + SENDLPM + desc SENDLPM + 24 + 24 + read-write + + + LPMRCNTSTS + desc LPMRCNTSTS + 27 + 25 + read-only + + + ENBSEL + desc ENBSEL + 28 + 28 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x2800500 + 0xFFFFFFFF + + + PTXSA + desc PTXSA + 15 + 0 + read-write + + + PTXFD + desc PTXFD + 31 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x2800500 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x2800780 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x2800A00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x2800C80 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x2800F00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x2801180 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x2801400 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x2801680 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x2801900 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 0x128 + 32 + read-write + 0x2801B80 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF11 + desc DIEPTXF11 + 0x12C + 32 + read-write + 0x2801E00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF12 + desc DIEPTXF12 + 0x130 + 32 + read-write + 0x2802080 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF13 + desc DIEPTXF13 + 0x134 + 32 + read-write + 0x2802300 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF14 + desc DIEPTXF14 + 0x138 + 32 + read-write + 0x2802580 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF15 + desc DIEPTXF15 + 0x13C + 32 + read-write + 0x2802800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80280 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFFF + + + HAINT + desc HAINT + 15 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFFF + + + HAINTM + desc HAINTM + 15 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x61DCF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR12 + desc HCCHAR12 + 0x680 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT12 + desc HCINT12 + 0x688 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK12 + desc HCINTMSK12 + 0x68C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ12 + desc HCTSIZ12 + 0x690 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA12 + desc HCDMA12 + 0x694 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR13 + desc HCCHAR13 + 0x6A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT13 + desc HCINT13 + 0x6A8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK13 + desc HCINTMSK13 + 0x6AC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ13 + desc HCTSIZ13 + 0x6B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA13 + desc HCDMA13 + 0x6B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR14 + desc HCCHAR14 + 0x6C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT14 + desc HCINT14 + 0x6C8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK14 + desc HCINTMSK14 + 0x6CC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ14 + desc HCTSIZ14 + 0x6D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA14 + desc HCDMA14 + 0x6D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR15 + desc HCCHAR15 + 0x6E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT15 + desc HCINT15 + 0x6E8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK15 + desc HCINTMSK15 + 0x6EC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ15 + desc HCTSIZ15 + 0x6F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA15 + desc HCDMA15 + 0x6F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8200000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xF8F + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + SGINAK + desc SGINAK + 7 + 7 + write-only + + + CGINAK + desc CGINAK + 8 + 8 + write-only + + + SGONAK + desc SGONAK + 9 + 9 + write-only + + + CGONAK + desc CGONAK + 10 + 10 + write-only + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0xFFFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + LNSTS + desc LNSTS + 23 + 22 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x207B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + ITTXFEMSK + desc ITTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x1B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINT + desc IEPINT + 15 + 0 + read-write + + + OEPINT + desc OEPINT + 31 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINTM + desc IEPINTM + 15 + 0 + read-write + + + OEPINTM + desc OEPINTM + 31 + 16 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0xFFFF + + + INEPTXFEM + desc INEPTXFEM + 15 + 0 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-write + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ11 + desc DIEPTSIZ11 + 0xA70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT12 + desc DIEPINT12 + 0xA88 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ12 + desc DIEPTSIZ12 + 0xA90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT13 + desc DIEPINT13 + 0xAA8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ13 + desc DIEPTSIZ13 + 0xAB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT14 + desc DIEPINT14 + 0xAC8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ14 + desc DIEPTSIZ14 + 0xAD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA14 + desc DIEPDMA14 + 0xAD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS14 + desc DTXFSTS14 + 0xAD8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL15 + desc DIEPCTL15 + 0xAE0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT15 + desc DIEPINT15 + 0xAE8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ15 + desc DIEPTSIZ15 + 0xAF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-write + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL6 + desc DOEPCTL6 + 0xBC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT6 + desc DOEPINT6 + 0xBC8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ6 + desc DOEPTSIZ6 + 0xBD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA6 + desc DOEPDMA6 + 0xBD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL7 + desc DOEPCTL7 + 0xBE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT7 + desc DOEPINT7 + 0xBE8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ7 + desc DOEPTSIZ7 + 0xBF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA7 + desc DOEPDMA7 + 0xBF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL8 + desc DOEPCTL8 + 0xC00 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT8 + desc DOEPINT8 + 0xC08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ8 + desc DOEPTSIZ8 + 0xC10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA8 + desc DOEPDMA8 + 0xC14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL9 + desc DOEPCTL9 + 0xC20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT9 + desc DOEPINT9 + 0xC28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ9 + desc DOEPTSIZ9 + 0xC30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA9 + desc DOEPDMA9 + 0xC34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL10 + desc DOEPCTL10 + 0xC40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT10 + desc DOEPINT10 + 0xC48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ10 + desc DOEPTSIZ10 + 0xC50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA10 + desc DOEPDMA10 + 0xC54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL11 + desc DOEPCTL11 + 0xC60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT11 + desc DOEPINT11 + 0xC68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ11 + desc DOEPTSIZ11 + 0xC70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA11 + desc DOEPDMA11 + 0xC74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL12 + desc DOEPCTL12 + 0xC80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT12 + desc DOEPINT12 + 0xC88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ12 + desc DOEPTSIZ12 + 0xC90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA12 + desc DOEPDMA12 + 0xC94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL13 + desc DOEPCTL13 + 0xCA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT13 + desc DOEPINT13 + 0xCA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ13 + desc DOEPTSIZ13 + 0xCB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ14 + desc DOEPTSIZ14 + 0xCD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0xE3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + ENL1GTG + desc ENL1GTG + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-write + + + SUSP + desc SUSP + 7 + 7 + read-write + + + + + + + USBHS + desc USBHS + 0x400C0000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0x1410 + 0x63BEBC47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + PHYLPCS + desc PHYLPCS + 15 + 15 + read-write + + + ULFSLS + desc ULFSLS + 17 + 17 + read-write + + + ULPIAR + desc ULPIAR + 18 + 18 + read-write + + + ULPICSM + desc ULPICSM + 19 + 19 + read-write + + + ULPIEVBUSD + desc ULPIEVBUSD + 20 + 20 + read-write + + + ULPIEVBUSI + desc ULPIEVBUSI + 21 + 21 + read-write + + + PCCI + desc PCCI + 23 + 23 + read-write + + + PTCI + desc PTCI + 24 + 24 + read-write + + + ULPIPD + desc ULPIPD + 25 + 25 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFF7CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + LPMINT + desc LPMINT + 27 + 27 + read-write + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xFF7CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + LPMINTM + desc LPMINTM + 27 + 27 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x800 + 0xFFF + + + RXFD + desc RXFD + 11 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x8000800 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80800 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + LPMEN + desc LPMEN + 0 + 0 + read-write + + + LPMACK + desc LPMACK + 1 + 1 + read-write + + + BSEL + desc BSEL + 5 + 2 + read-write + + + REMWAKE + desc REMWAKE + 6 + 6 + read-write + + + L1SSEN + desc L1SSEN + 7 + 7 + read-write + + + BESLTHRS + desc BESLTHRS + 11 + 8 + read-write + + + L1DSEN + desc L1DSEN + 12 + 12 + read-write + + + LPMRSP + desc LPMRSP + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RSMOK + desc L1RSMOK + 16 + 16 + read-only + + + LPMCHIDX + desc LPMCHIDX + 20 + 17 + read-write + + + LPMRCNT + desc LPMRCNT + 23 + 21 + read-write + + + SENDLPM + desc SENDLPM + 24 + 24 + read-write + + + LPMRCNTSTS + desc LPMRCNTSTS + 27 + 25 + read-only + + + ENBSEL + desc ENBSEL + 28 + 28 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x8001000 + 0xFFFFFFFF + + + PTXSA + desc PTXSA + 15 + 0 + read-write + + + PTXFD + desc PTXFD + 31 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x8001000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x8001800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x8002000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x8002800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x8003000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x8003800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x8004000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x8004800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x8005000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 0x128 + 32 + read-write + 0x8005800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF11 + desc DIEPTXF11 + 0x12C + 32 + read-write + 0x8006000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF12 + desc DIEPTXF12 + 0x130 + 32 + read-write + 0x8006800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF13 + desc DIEPTXF13 + 0x134 + 32 + read-write + 0x8007000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF14 + desc DIEPTXF14 + 0x138 + 32 + read-write + 0x8007800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF15 + desc DIEPTXF15 + 0x13C + 32 + read-write + 0x8008000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80800 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFFF + + + HAINT + desc HAINT + 15 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFFF + + + HAINTM + desc HAINTM + 15 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x7FDFF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + POCA + desc POCA + 4 + 4 + read-write + + + POCCHNG + desc POCCHNG + 5 + 5 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PTCTL + desc PTCTL + 16 + 13 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT0 + desc HCSPLT0 + 0x504 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT1 + desc HCSPLT1 + 0x524 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT2 + desc HCSPLT2 + 0x544 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT3 + desc HCSPLT3 + 0x564 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT4 + desc HCSPLT4 + 0x584 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT5 + desc HCSPLT5 + 0x5A4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT6 + desc HCSPLT6 + 0x5C4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT7 + desc HCSPLT7 + 0x5E4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT8 + desc HCSPLT8 + 0x604 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT9 + desc HCSPLT9 + 0x624 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT10 + desc HCSPLT10 + 0x644 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT11 + desc HCSPLT11 + 0x664 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR12 + desc HCCHAR12 + 0x680 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT12 + desc HCSPLT12 + 0x684 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT12 + desc HCINT12 + 0x688 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK12 + desc HCINTMSK12 + 0x68C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ12 + desc HCTSIZ12 + 0x690 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA12 + desc HCDMA12 + 0x694 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR13 + desc HCCHAR13 + 0x6A0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT13 + desc HCSPLT13 + 0x6A4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT13 + desc HCINT13 + 0x6A8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK13 + desc HCINTMSK13 + 0x6AC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ13 + desc HCTSIZ13 + 0x6B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA13 + desc HCDMA13 + 0x6B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR14 + desc HCCHAR14 + 0x6C0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT14 + desc HCSPLT14 + 0x6C4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT14 + desc HCINT14 + 0x6C8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK14 + desc HCINTMSK14 + 0x6CC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ14 + desc HCTSIZ14 + 0x6D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA14 + desc HCDMA14 + 0x6D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR15 + desc HCCHAR15 + 0x6E0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT15 + desc HCSPLT15 + 0x6E4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT15 + desc HCINT15 + 0x6E8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK15 + desc HCINTMSK15 + 0x6EC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ15 + desc HCTSIZ15 + 0x6F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA15 + desc HCDMA15 + 0x6F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8220000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xFFF + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + TCTL + desc TCTL + 6 + 4 + read-write + + + SGINAK + desc SGINAK + 7 + 7 + read-write + + + CGINAK + desc CGINAK + 8 + 8 + read-write + + + SGONAK + desc SGONAK + 9 + 9 + read-write + + + CGONAK + desc CGONAK + 10 + 10 + read-write + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0xFFFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + LNSTS + desc LNSTS + 23 + 22 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x217B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + TTXFEMSK + desc TTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + TXFURM + desc TXFURM + 8 + 8 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x415B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + OPEM + desc OPEM + 8 + 8 + read-write + + + NYETM + desc NYETM + 14 + 14 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINT + desc IEPINT + 15 + 0 + read-write + + + OEPINT + desc OEPINT + 31 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINTM + desc IEPINTM + 15 + 0 + read-write + + + OEPINTM + desc OEPINTM + 31 + 16 + read-write + + + + + DTHRCTL + desc DTHRCTL + 0x830 + 32 + read-write + 0xC100020 + 0xBFF07FF + + + NONISOTHREN + desc NONISOTHREN + 0 + 0 + read-write + + + ISOTHREN + desc ISOTHREN + 1 + 1 + read-write + + + TXTHRLEN + desc TXTHRLEN + 10 + 2 + read-write + + + RXTHREN + desc RXTHREN + 16 + 16 + read-write + + + RXTHRLEN + desc RXTHRLEN + 25 + 17 + read-write + + + ARPEN + desc ARPEN + 27 + 27 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0xFFFF + + + INEPTXFEM + desc INEPTXFEM + 15 + 0 + read-write + + + + + DEACHINT + desc DEACHINT + 0x838 + 32 + read-write + 0x0 + 0x20002 + + + IEP1INT + desc IEP1INT + 1 + 1 + read-write + + + OEP1INT + desc OEP1INT + 17 + 17 + read-write + + + + + DEACHINTMSK + desc DEACHINTMSK + 0x83C + 32 + read-write + 0x0 + 0x20002 + + + IEP1INTM + desc IEP1INTM + 1 + 1 + read-write + + + OEP1INTM + desc OEP1INTM + 17 + 17 + read-write + + + + + DIEPEACHMSK1 + desc DIEPEACHMSK1 + 0x844 + 32 + read-write + 0x0 + 0x217B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + TTXFEMSK + desc TTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + TXFURM + desc TXFURM + 8 + 8 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPEACHMSK1 + desc DOEPEACHMSK1 + 0x884 + 32 + read-write + 0x0 + 0x415B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + OPEM + desc OPEM + 8 + 8 + read-write + + + NYETM + desc NYETM + 14 + 14 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-only + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ11 + desc DIEPTSIZ11 + 0xA70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT12 + desc DIEPINT12 + 0xA88 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ12 + desc DIEPTSIZ12 + 0xA90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT13 + desc DIEPINT13 + 0xAA8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ13 + desc DIEPTSIZ13 + 0xAB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT14 + desc DIEPINT14 + 0xAC8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ14 + desc DIEPTSIZ14 + 0xAD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA14 + desc DIEPDMA14 + 0xAD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS14 + desc DTXFSTS14 + 0xAD8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL15 + desc DIEPCTL15 + 0xAE0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT15 + desc DIEPINT15 + 0xAE8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ15 + desc DIEPTSIZ15 + 0xAF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-only + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL6 + desc DOEPCTL6 + 0xBC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT6 + desc DOEPINT6 + 0xBC8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ6 + desc DOEPTSIZ6 + 0xBD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA6 + desc DOEPDMA6 + 0xBD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL7 + desc DOEPCTL7 + 0xBE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT7 + desc DOEPINT7 + 0xBE8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ7 + desc DOEPTSIZ7 + 0xBF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA7 + desc DOEPDMA7 + 0xBF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL8 + desc DOEPCTL8 + 0xC00 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT8 + desc DOEPINT8 + 0xC08 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ8 + desc DOEPTSIZ8 + 0xC10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA8 + desc DOEPDMA8 + 0xC14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL9 + desc DOEPCTL9 + 0xC20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT9 + desc DOEPINT9 + 0xC28 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ9 + desc DOEPTSIZ9 + 0xC30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA9 + desc DOEPDMA9 + 0xC34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL10 + desc DOEPCTL10 + 0xC40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT10 + desc DOEPINT10 + 0xC48 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ10 + desc DOEPTSIZ10 + 0xC50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA10 + desc DOEPDMA10 + 0xC54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL11 + desc DOEPCTL11 + 0xC60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT11 + desc DOEPINT11 + 0xC68 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ11 + desc DOEPTSIZ11 + 0xC70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA11 + desc DOEPDMA11 + 0xC74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL12 + desc DOEPCTL12 + 0xC80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT12 + desc DOEPINT12 + 0xC88 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ12 + desc DOEPTSIZ12 + 0xC90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA12 + desc DOEPDMA12 + 0xC94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL13 + desc DOEPCTL13 + 0xCA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT13 + desc DOEPINT13 + 0xCA8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ13 + desc DOEPTSIZ13 + 0xCB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ14 + desc DOEPTSIZ14 + 0xCD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0xE3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + ENL1GTG + desc ENL1GTG + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-write + + + SUSP + desc SUSP + 7 + 7 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.mac b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.mac new file mode 100644 index 0000000000..e30bd40aa2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.out b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.out new file mode 100644 index 0000000000..f4a726caf9 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0.out differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0_otp.out b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0_otp.out new file mode 100644 index 0000000000..47da8bd591 Binary files /dev/null and b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F4A0_otp.out differ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf new file mode 100644 index 0000000000..73c070bfb5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0_RAM.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1FFE0000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf new file mode 100644 index 0000000000..735d43311f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xG.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf new file mode 100644 index 0000000000..b47254e04e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F4A0xI.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s new file mode 100644 index 0000000000..716b15682c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s @@ -0,0 +1,970 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/* Target-mcu HC32F4A0 */ +;/****************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + PUBWEAK IRQ032_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ032_Handler + B IRQ032_Handler + + PUBWEAK IRQ033_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ033_Handler + B IRQ033_Handler + + PUBWEAK IRQ034_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ034_Handler + B IRQ034_Handler + + PUBWEAK IRQ035_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ035_Handler + B IRQ035_Handler + + PUBWEAK IRQ036_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ036_Handler + B IRQ036_Handler + + PUBWEAK IRQ037_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ037_Handler + B IRQ037_Handler + + PUBWEAK IRQ038_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ038_Handler + B IRQ038_Handler + + PUBWEAK IRQ039_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ039_Handler + B IRQ039_Handler + + PUBWEAK IRQ040_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ040_Handler + B IRQ040_Handler + + PUBWEAK IRQ041_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ041_Handler + B IRQ041_Handler + + PUBWEAK IRQ042_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ042_Handler + B IRQ042_Handler + + PUBWEAK IRQ043_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ043_Handler + B IRQ043_Handler + + PUBWEAK IRQ044_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ044_Handler + B IRQ044_Handler + + PUBWEAK IRQ045_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ045_Handler + B IRQ045_Handler + + PUBWEAK IRQ046_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ046_Handler + B IRQ046_Handler + + PUBWEAK IRQ047_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ047_Handler + B IRQ047_Handler + + PUBWEAK IRQ048_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ048_Handler + B IRQ048_Handler + + PUBWEAK IRQ049_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ049_Handler + B IRQ049_Handler + + PUBWEAK IRQ050_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ050_Handler + B IRQ050_Handler + + PUBWEAK IRQ051_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ051_Handler + B IRQ051_Handler + + PUBWEAK IRQ052_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ052_Handler + B IRQ052_Handler + + PUBWEAK IRQ053_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ053_Handler + B IRQ053_Handler + + PUBWEAK IRQ054_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ054_Handler + B IRQ054_Handler + + PUBWEAK IRQ055_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ055_Handler + B IRQ055_Handler + + PUBWEAK IRQ056_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ056_Handler + B IRQ056_Handler + + PUBWEAK IRQ057_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ057_Handler + B IRQ057_Handler + + PUBWEAK IRQ058_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ058_Handler + B IRQ058_Handler + + PUBWEAK IRQ059_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ059_Handler + B IRQ059_Handler + + PUBWEAK IRQ060_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ060_Handler + B IRQ060_Handler + + PUBWEAK IRQ061_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ061_Handler + B IRQ061_Handler + + PUBWEAK IRQ062_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ062_Handler + B IRQ062_Handler + + PUBWEAK IRQ063_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ063_Handler + B IRQ063_Handler + + PUBWEAK IRQ064_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ064_Handler + B IRQ064_Handler + + PUBWEAK IRQ065_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ065_Handler + B IRQ065_Handler + + PUBWEAK IRQ066_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ066_Handler + B IRQ066_Handler + + PUBWEAK IRQ067_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ067_Handler + B IRQ067_Handler + + PUBWEAK IRQ068_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ068_Handler + B IRQ068_Handler + + PUBWEAK IRQ069_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ069_Handler + B IRQ069_Handler + + PUBWEAK IRQ070_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ070_Handler + B IRQ070_Handler + + PUBWEAK IRQ071_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ071_Handler + B IRQ071_Handler + + PUBWEAK IRQ072_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ072_Handler + B IRQ072_Handler + + PUBWEAK IRQ073_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ073_Handler + B IRQ073_Handler + + PUBWEAK IRQ074_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ074_Handler + B IRQ074_Handler + + PUBWEAK IRQ075_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ075_Handler + B IRQ075_Handler + + PUBWEAK IRQ076_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ076_Handler + B IRQ076_Handler + + PUBWEAK IRQ077_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ077_Handler + B IRQ077_Handler + + PUBWEAK IRQ078_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ078_Handler + B IRQ078_Handler + + PUBWEAK IRQ079_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ079_Handler + B IRQ079_Handler + + PUBWEAK IRQ080_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ080_Handler + B IRQ080_Handler + + PUBWEAK IRQ081_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ081_Handler + B IRQ081_Handler + + PUBWEAK IRQ082_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ082_Handler + B IRQ082_Handler + + PUBWEAK IRQ083_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ083_Handler + B IRQ083_Handler + + PUBWEAK IRQ084_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ084_Handler + B IRQ084_Handler + + PUBWEAK IRQ085_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ085_Handler + B IRQ085_Handler + + PUBWEAK IRQ086_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ086_Handler + B IRQ086_Handler + + PUBWEAK IRQ087_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ087_Handler + B IRQ087_Handler + + PUBWEAK IRQ088_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ088_Handler + B IRQ088_Handler + + PUBWEAK IRQ089_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ089_Handler + B IRQ089_Handler + + PUBWEAK IRQ090_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ090_Handler + B IRQ090_Handler + + PUBWEAK IRQ091_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ091_Handler + B IRQ091_Handler + + PUBWEAK IRQ092_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ092_Handler + B IRQ092_Handler + + PUBWEAK IRQ093_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ093_Handler + B IRQ093_Handler + + PUBWEAK IRQ094_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ094_Handler + B IRQ094_Handler + + PUBWEAK IRQ095_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ095_Handler + B IRQ095_Handler + + PUBWEAK IRQ096_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ096_Handler + B IRQ096_Handler + + PUBWEAK IRQ097_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ097_Handler + B IRQ097_Handler + + PUBWEAK IRQ098_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ098_Handler + B IRQ098_Handler + + PUBWEAK IRQ099_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ099_Handler + B IRQ099_Handler + + PUBWEAK IRQ100_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ100_Handler + B IRQ100_Handler + + PUBWEAK IRQ101_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ101_Handler + B IRQ101_Handler + + PUBWEAK IRQ102_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ102_Handler + B IRQ102_Handler + + PUBWEAK IRQ103_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ103_Handler + B IRQ103_Handler + + PUBWEAK IRQ104_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ104_Handler + B IRQ104_Handler + + PUBWEAK IRQ105_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ105_Handler + B IRQ105_Handler + + PUBWEAK IRQ106_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ106_Handler + B IRQ106_Handler + + PUBWEAK IRQ107_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ107_Handler + B IRQ107_Handler + + PUBWEAK IRQ108_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ108_Handler + B IRQ108_Handler + + PUBWEAK IRQ109_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ109_Handler + B IRQ109_Handler + + PUBWEAK IRQ110_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ110_Handler + B IRQ110_Handler + + PUBWEAK IRQ111_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ111_Handler + B IRQ111_Handler + + PUBWEAK IRQ112_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ112_Handler + B IRQ112_Handler + + PUBWEAK IRQ113_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ113_Handler + B IRQ113_Handler + + PUBWEAK IRQ114_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ114_Handler + B IRQ114_Handler + + PUBWEAK IRQ115_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ115_Handler + B IRQ115_Handler + + PUBWEAK IRQ116_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ116_Handler + B IRQ116_Handler + + PUBWEAK IRQ117_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ117_Handler + B IRQ117_Handler + + PUBWEAK IRQ118_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ118_Handler + B IRQ118_Handler + + PUBWEAK IRQ119_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ119_Handler + B IRQ119_Handler + + PUBWEAK IRQ120_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ120_Handler + B IRQ120_Handler + + PUBWEAK IRQ121_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ121_Handler + B IRQ121_Handler + + PUBWEAK IRQ122_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ122_Handler + B IRQ122_Handler + + PUBWEAK IRQ123_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ123_Handler + B IRQ123_Handler + + PUBWEAK IRQ124_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ124_Handler + B IRQ124_Handler + + PUBWEAK IRQ125_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ125_Handler + B IRQ125_Handler + + PUBWEAK IRQ126_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ126_Handler + B IRQ126_Handler + + PUBWEAK IRQ127_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ127_Handler + B IRQ127_Handler + + PUBWEAK IRQ128_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ128_Handler + B IRQ128_Handler + + PUBWEAK IRQ129_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ129_Handler + B IRQ129_Handler + + PUBWEAK IRQ130_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ130_Handler + B IRQ130_Handler + + PUBWEAK IRQ131_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ131_Handler + B IRQ131_Handler + + PUBWEAK IRQ132_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ132_Handler + B IRQ132_Handler + + PUBWEAK IRQ133_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ133_Handler + B IRQ133_Handler + + PUBWEAK IRQ134_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ134_Handler + B IRQ134_Handler + + PUBWEAK IRQ135_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ135_Handler + B IRQ135_Handler + + PUBWEAK IRQ136_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ136_Handler + B IRQ136_Handler + + PUBWEAK IRQ137_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ137_Handler + B IRQ137_Handler + + PUBWEAK IRQ138_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ138_Handler + B IRQ138_Handler + + PUBWEAK IRQ139_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ139_Handler + B IRQ139_Handler + + PUBWEAK IRQ140_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ140_Handler + B IRQ140_Handler + + PUBWEAK IRQ141_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ141_Handler + B IRQ141_Handler + + PUBWEAK IRQ142_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ142_Handler + B IRQ142_Handler + + PUBWEAK IRQ143_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ143_Handler + B IRQ143_Handler + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F4A0.svd b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F4A0.svd new file mode 100644 index 0000000000..a8542c60e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F4A0.svd @@ -0,0 +1,102653 @@ + + + HDSC + HDSC + HDSC_HC32F4A0 + ARMCM4 + 1.0 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xC5 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SHCR + desc SHCR + 0x1A + 16 + read-write + 0x18 + 0x7FF + + + SHSST + desc SHSST + 7 + 0 + read-write + + + SHSEL + desc SHSEL + 10 + 8 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + read-write + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + read-write + + + CLREOCBF + desc CLREOCBF + 1 + 1 + read-write + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + read-write + + + + + SYNCCR + desc SYNCCR + 0x4C + 16 + read-write + 0xC00 + 0xFF71 + + + SYNCEN + desc SYNCEN + 0 + 0 + read-write + + + SYNCMD + desc SYNCMD + 6 + 4 + read-write + + + SYNCDLY + desc SYNCDLY + 15 + 8 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + PGACR1 + desc PGACR1 + 0xC0 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGACR2 + desc PGACR2 + 0xC1 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGACR3 + desc PGACR3 + 0xC2 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGAVSSENR + desc PGAVSSENR + 0xC4 + 8 + read-write + 0x0 + 0x7 + + + PGAVSSEN + desc PGAVSSEN + 2 + 0 + read-write + + + + + + + ADC2 + desc ADC2 + 0x40040400 + + 0x0 + 0xC5 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + write-only + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + write-only + + + CLREOCBF + desc CLREOCBF + 1 + 1 + write-only + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + write-only + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + PGACR1 + desc PGACR1 + 0xC0 + 8 + read-write + 0x0 + 0xFF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + PGAGAIN + desc PGAGAIN + 7 + 4 + read-write + + + + + PGAVSSENR + desc PGAVSSENR + 0xC4 + 8 + read-write + 0x0 + 0x1 + + + PGAVSSEN + desc PGAVSSEN + 0 + 0 + read-write + + + + + + + ADC3 + desc ADC3 + 0x40040800 + + 0x0 + 0xB1 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFFF + + + CHSELA + desc CHSELA + 19 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFFF + + + CHSELB + desc CHSELB + 19 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFFF + + + AVCHSEL + desc AVCHSEL + 19 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x44 + 8 + read-only + 0x0 + 0x13 + + + EOCAF + desc EOCAF + 0 + 0 + read-only + + + EOCBF + desc EOCBF + 1 + 1 + read-only + + + SASTPDF + desc SASTPDF + 4 + 4 + read-only + + + + + ICR + desc ICR + 0x45 + 8 + read-write + 0x3 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + ISCLRR + desc ISCLRR + 0x46 + 8 + write-only + 0x0 + 0x13 + + + CLREOCAF + desc CLREOCAF + 0 + 0 + write-only + + + CLREOCBF + desc CLREOCBF + 1 + 1 + write-only + + + CLRSASTPDF + desc CLRSASTPDF + 4 + 4 + write-only + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + DR16 + desc DR16 + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + DR17 + desc DR17 + 0x72 + 16 + read-only + 0x0 + 0xFFFF + + + DR18 + desc DR18 + 0x74 + 16 + read-only + 0x0 + 0xFFFF + + + DR19 + desc DR19 + 0x76 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x377 + + + AWD0EN + desc AWD0EN + 0 + 0 + read-write + + + AWD0IEN + desc AWD0IEN + 1 + 1 + read-write + + + AWD0MD + desc AWD0MD + 2 + 2 + read-write + + + AWD1EN + desc AWD1EN + 4 + 4 + read-write + + + AWD1IEN + desc AWD1IEN + 5 + 5 + read-write + + + AWD1MD + desc AWD1MD + 6 + 6 + read-write + + + AWDCM + desc AWDCM + 9 + 8 + read-write + + + + + AWDSR + desc AWDSR + 0xA2 + 8 + read-only + 0x0 + 0x13 + + + AWD0F + desc AWD0F + 0 + 0 + read-only + + + AWD1F + desc AWD1F + 1 + 1 + read-only + + + AWDCMF + desc AWDCMF + 4 + 4 + read-only + + + + + AWDSCLRR + desc AWDSCLRR + 0xA3 + 8 + write-only + 0x0 + 0x13 + + + CLRAWD0F + desc CLRAWD0F + 0 + 0 + write-only + + + CLRAWD1F + desc CLRAWD1F + 1 + 1 + write-only + + + CLRAWDCMF + desc CLRAWDCMF + 4 + 4 + write-only + + + + + AWD0DR0 + desc AWD0DR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWD0DR1 + desc AWD0DR1 + 0xA6 + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD0CHSR + desc AWD0CHSR + 0xA8 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + AWD1DR0 + desc AWD1DR0 + 0xAC + 16 + read-write + 0x0 + 0xFFFF + + + AWD1DR1 + desc AWD1DR1 + 0xAE + 16 + read-write + 0xFFFF + 0xFFFF + + + AWD1CHSR + desc AWD1CHSR + 0xB0 + 8 + read-write + 0x0 + 0x1F + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + + + + + AES + desc AES + 0x40008000 + + 0x0 + 0x40 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x1B + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 1 + 1 + read-write + + + KEYSIZE + desc KEYSIZE + 4 + 3 + read-write + + + + + DR0 + desc DR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR0 + desc KR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR1 + desc KR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR2 + desc KR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR3 + desc KR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR4 + desc KR4 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR5 + desc KR5 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR6 + desc KR6 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR7 + desc KR7 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + AOS + desc AOS + 0x40010800 + + 0x0 + 0x174 + + + + INTSFTTRG + desc INTSFTTRG + 0x0 + 32 + write-only + 0x0 + 0x1 + + + STRG + desc STRG + 0 + 0 + write-only + + + + + DCU_TRGSEL1 + desc DCU_TRGSEL1 + 0x4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL2 + desc DCU_TRGSEL2 + 0x8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL3 + desc DCU_TRGSEL3 + 0xC + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL4 + desc DCU_TRGSEL4 + 0x10 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL0 + desc DMA1_TRGSEL0 + 0x14 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL1 + desc DMA1_TRGSEL1 + 0x18 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL2 + desc DMA1_TRGSEL2 + 0x1C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL3 + desc DMA1_TRGSEL3 + 0x20 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL4 + desc DMA1_TRGSEL4 + 0x24 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL5 + desc DMA1_TRGSEL5 + 0x28 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL6 + desc DMA1_TRGSEL6 + 0x2C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL7 + desc DMA1_TRGSEL7 + 0x30 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL0 + desc DMA2_TRGSEL0 + 0x34 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL1 + desc DMA2_TRGSEL1 + 0x38 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL2 + desc DMA2_TRGSEL2 + 0x3C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL3 + desc DMA2_TRGSEL3 + 0x40 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL4 + desc DMA2_TRGSEL4 + 0x44 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL5 + desc DMA2_TRGSEL5 + 0x48 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL6 + desc DMA2_TRGSEL6 + 0x4C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL7 + desc DMA2_TRGSEL7 + 0x50 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA_TRGSELRC + desc DMA_TRGSELRC + 0x54 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR0 + desc TMR6_HTSSR0 + 0x58 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR1 + desc TMR6_HTSSR1 + 0x5C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR2 + desc TMR6_HTSSR2 + 0x60 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR3 + desc TMR6_HTSSR3 + 0x64 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR12 + desc PEVNTTRGSR12 + 0x68 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR34 + desc PEVNTTRGSR34 + 0x6C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR0_HTSSR + desc TMR0_HTSSR + 0x70 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR2_HTSSR + desc TMR2_HTSSR + 0x74 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + HASH_ITRGSELA + desc HASH_ITRGSELA + 0x78 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + HASH_ITRGSELB + desc HASH_ITRGSELB + 0x7C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR0 + desc TMRA_HTSSR0 + 0x80 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR1 + desc TMRA_HTSSR1 + 0x84 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR2 + desc TMRA_HTSSR2 + 0x88 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR3 + desc TMRA_HTSSR3 + 0x8C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + OTS_TRG + desc OTS_TRG + 0x90 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR0 + desc ADC1_ITRGSELR0 + 0x94 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR1 + desc ADC1_ITRGSELR1 + 0x98 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR0 + desc ADC2_ITRGSELR0 + 0x9C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR1 + desc ADC2_ITRGSELR1 + 0xA0 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC3_ITRGSELR0 + desc ADC3_ITRGSELR0 + 0xA4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC3_ITRGSELR1 + desc ADC3_ITRGSELR1 + 0xA8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + COMTRG1 + desc COMTRG1 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + COMTRG2 + desc COMTRG2 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + PEVNTDIRR1 + desc PEVNTDIRR1 + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR1 + desc PEVNTIDR1 + 0x104 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR1 + desc PEVNTODR1 + 0x108 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR1 + desc PEVNTORR1 + 0x10C + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR1 + desc PEVNTOSR1 + 0x110 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR1 + desc PEVNTRISR1 + 0x114 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL1 + desc PEVNTFAL1 + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR2 + desc PEVNTDIRR2 + 0x11C + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR2 + desc PEVNTIDR2 + 0x120 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR2 + desc PEVNTODR2 + 0x124 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR2 + desc PEVNTORR2 + 0x128 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR2 + desc PEVNTOSR2 + 0x12C + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR2 + desc PEVNTRISR2 + 0x130 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL2 + desc PEVNTFAL2 + 0x134 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR3 + desc PEVNTDIRR3 + 0x138 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR3 + desc PEVNTIDR3 + 0x13C + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR3 + desc PEVNTODR3 + 0x140 + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR3 + desc PEVNTORR3 + 0x144 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR3 + desc PEVNTOSR3 + 0x148 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR3 + desc PEVNTRISR3 + 0x14C + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL3 + desc PEVNTFAL3 + 0x150 + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTDIRR4 + desc PEVNTDIRR4 + 0x154 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR + desc PDIR + 15 + 0 + read-write + + + + + PEVNTIDR4 + desc PEVNTIDR4 + 0x158 + 32 + read-only + 0x0 + 0xFFFF + + + PIN + desc PIN + 15 + 0 + read-only + + + + + PEVNTODR4 + desc PEVNTODR4 + 0x15C + 32 + read-write + 0x0 + 0xFFFF + + + POUT + desc POUT + 15 + 0 + read-write + + + + + PEVNTORR4 + desc PEVNTORR4 + 0x160 + 32 + read-write + 0x0 + 0xFFFF + + + POR + desc POR + 15 + 0 + read-write + + + + + PEVNTOSR4 + desc PEVNTOSR4 + 0x164 + 32 + read-write + 0x0 + 0xFFFF + + + POS + desc POS + 15 + 0 + read-write + + + + + PEVNTRISR4 + desc PEVNTRISR4 + 0x168 + 32 + read-write + 0x0 + 0xFFFF + + + RIS + desc RIS + 15 + 0 + read-write + + + + + PEVNTFAL4 + desc PEVNTFAL4 + 0x16C + 32 + read-write + 0x0 + 0xFFFF + + + FAL + desc FAL + 15 + 0 + read-write + + + + + PEVNTNFCR + desc PEVNTNFCR + 0x170 + 32 + read-write + 0x0 + 0x7070707 + + + NFEN1 + desc NFEN1 + 0 + 0 + read-write + + + DIVS1 + desc DIVS1 + 2 + 1 + read-write + + + NFEN2 + desc NFEN2 + 8 + 8 + read-write + + + DIVS2 + desc DIVS2 + 10 + 9 + read-write + + + NFEN3 + desc NFEN3 + 16 + 16 + read-write + + + DIVS3 + desc DIVS3 + 18 + 17 + read-write + + + NFEN4 + desc NFEN4 + 24 + 24 + read-write + + + DIVS4 + desc DIVS4 + 26 + 25 + read-write + + + + + + + CAN1 + desc CAN + 0x40009000 + + 0x0 + 0xCA + + + + RBUF + desc RBUF + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TBUF + desc TBUF + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFG_STAT + desc CFG_STAT + 0xA0 + 8 + read-write + 0x80 + 0xFF + + + BUSOFF + desc BUSOFF + 0 + 0 + read-write + + + TACTIVE + desc TACTIVE + 1 + 1 + read-only + + + RACTIVE + desc RACTIVE + 2 + 2 + read-only + + + TSSS + desc TSSS + 3 + 3 + read-write + + + TPSS + desc TPSS + 4 + 4 + read-write + + + LBMI + desc LBMI + 5 + 5 + read-write + + + LBME + desc LBME + 6 + 6 + read-write + + + RESET + desc RESET + 7 + 7 + read-write + + + + + TCMD + desc TCMD + 0xA1 + 8 + read-write + 0x0 + 0xDF + + + TSA + desc TSA + 0 + 0 + read-write + + + TSALL + desc TSALL + 1 + 1 + read-write + + + TSONE + desc TSONE + 2 + 2 + read-write + + + TPA + desc TPA + 3 + 3 + read-write + + + TPE + desc TPE + 4 + 4 + read-write + + + LOM + desc LOM + 6 + 6 + read-write + + + TBSEL + desc TBSEL + 7 + 7 + read-write + + + + + TCTRL + desc TCTRL + 0xA2 + 8 + read-write + 0x90 + 0xF3 + + + TSSTAT + desc TSSTAT + 1 + 0 + read-only + + + TTTBM + desc TTTBM + 4 + 4 + read-write + + + TSMODE + desc TSMODE + 5 + 5 + read-write + + + TSNEXT + desc TSNEXT + 6 + 6 + read-write + + + FD_ISO + desc FD_ISO + 7 + 7 + read-write + + + + + RCTRL + desc RCTRL + 0xA3 + 8 + read-write + 0x0 + 0xFB + + + RSTAT + desc RSTAT + 1 + 0 + read-only + + + RBALL + desc RBALL + 3 + 3 + read-write + + + RREL + desc RREL + 4 + 4 + read-write + + + ROV + desc ROV + 5 + 5 + read-only + + + ROM + desc ROM + 6 + 6 + read-write + + + SACK + desc SACK + 7 + 7 + read-write + + + + + RTIE + desc RTIE + 0xA4 + 8 + read-write + 0xFE + 0xFF + + + TSFF + desc TSFF + 0 + 0 + read-only + + + EIE + desc EIE + 1 + 1 + read-write + + + TSIE + desc TSIE + 2 + 2 + read-write + + + TPIE + desc TPIE + 3 + 3 + read-write + + + RAFIE + desc RAFIE + 4 + 4 + read-write + + + RFIE + desc RFIE + 5 + 5 + read-write + + + ROIE + desc ROIE + 6 + 6 + read-write + + + RIE + desc RIE + 7 + 7 + read-write + + + + + RTIF + desc RTIF + 0xA5 + 8 + read-write + 0x0 + 0xFF + + + AIF + desc AIF + 0 + 0 + read-write + + + EIF + desc EIF + 1 + 1 + read-write + + + TSIF + desc TSIF + 2 + 2 + read-write + + + TPIF + desc TPIF + 3 + 3 + read-write + + + RAFIF + desc RAFIF + 4 + 4 + read-write + + + RFIF + desc RFIF + 5 + 5 + read-write + + + ROIF + desc ROIF + 6 + 6 + read-write + + + RIF + desc RIF + 7 + 7 + read-write + + + + + ERRINT + desc ERRINT + 0xA6 + 8 + read-write + 0x0 + 0xFF + + + BEIF + desc BEIF + 0 + 0 + read-write + + + BEIE + desc BEIE + 1 + 1 + read-write + + + ALIF + desc ALIF + 2 + 2 + read-write + + + ALIE + desc ALIE + 3 + 3 + read-write + + + EPIF + desc EPIF + 4 + 4 + read-write + + + EPIE + desc EPIE + 5 + 5 + read-write + + + EPASS + desc EPASS + 6 + 6 + read-only + + + EWARN + desc EWARN + 7 + 7 + read-only + + + + + LIMIT + desc LIMIT + 0xA7 + 8 + read-write + 0x1B + 0xFF + + + EWL + desc EWL + 3 + 0 + read-write + + + AFWL + desc AFWL + 7 + 4 + read-write + + + + + SBT + desc SBT + 0xA8 + 32 + read-write + 0x1020203 + 0xFF7F7FFF + + + S_SEG_1 + desc S_SEG_1 + 7 + 0 + read-write + + + S_SEG_2 + desc S_SEG_2 + 14 + 8 + read-write + + + S_SJW + desc S_SJW + 22 + 16 + read-write + + + S_PRESC + desc S_PRESC + 31 + 24 + read-write + + + + + FBT + desc FBT + 0xAC + 32 + read-write + 0x1020203 + 0xFF0F0F1F + + + F_SEG_1 + desc F_SEG_1 + 4 + 0 + read-write + + + F_SEG_2 + desc F_SEG_2 + 11 + 8 + read-write + + + F_SJW + desc F_SJW + 19 + 16 + read-write + + + F_PRESC + desc F_PRESC + 31 + 24 + read-write + + + + + EALCAP + desc EALCAP + 0xB0 + 8 + read-only + 0x0 + 0xFF + + + ALC + desc ALC + 4 + 0 + read-only + + + KOER + desc KOER + 7 + 5 + read-only + + + + + TDC + desc TDC + 0xB1 + 8 + read-write + 0x0 + 0xFF + + + SSPOFF + desc SSPOFF + 6 + 0 + read-write + + + TDCEN + desc TDCEN + 7 + 7 + read-write + + + + + RECNT + desc RECNT + 0xB2 + 8 + read-write + 0x0 + 0xFF + + + TECNT + desc TECNT + 0xB3 + 8 + read-write + 0x0 + 0xFF + + + ACFCTRL + desc ACFCTRL + 0xB4 + 8 + read-write + 0x0 + 0x2F + + + ACFADR + desc ACFADR + 3 + 0 + read-write + + + SELMASK + desc SELMASK + 5 + 5 + read-write + + + + + ACFEN + desc ACFEN + 0xB6 + 16 + read-write + 0x1 + 0xFFFF + + + AE_1 + desc AE_1 + 0 + 0 + read-write + + + AE_2 + desc AE_2 + 1 + 1 + read-write + + + AE_3 + desc AE_3 + 2 + 2 + read-write + + + AE_4 + desc AE_4 + 3 + 3 + read-write + + + AE_5 + desc AE_5 + 4 + 4 + read-write + + + AE_6 + desc AE_6 + 5 + 5 + read-write + + + AE_7 + desc AE_7 + 6 + 6 + read-write + + + AE_8 + desc AE_8 + 7 + 7 + read-write + + + AE_9 + desc AE_9 + 8 + 8 + read-write + + + AE_10 + desc AE_10 + 9 + 9 + read-write + + + AE_11 + desc AE_11 + 10 + 10 + read-write + + + AE_12 + desc AE_12 + 11 + 11 + read-write + + + AE_13 + desc AE_13 + 12 + 12 + read-write + + + AE_14 + desc AE_14 + 13 + 13 + read-write + + + AE_15 + desc AE_15 + 14 + 14 + read-write + + + AE_16 + desc AE_16 + 15 + 15 + read-write + + + + + ACF + desc ACF + 0xB8 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + ACODEORAMASK + desc ACODEORAMASK + 28 + 0 + read-write + + + AIDE + desc AIDE + 29 + 29 + read-write + + + AIDEE + desc AIDEE + 30 + 30 + read-write + + + + + TBSLOT + desc TBSLOT + 0xBE + 8 + read-write + 0x0 + 0xFF + + + TBPTR + desc TBPTR + 5 + 0 + read-write + + + TBF + desc TBF + 6 + 6 + read-write + + + TBE + desc TBE + 7 + 7 + read-write + + + + + TTCFG + desc TTCFG + 0xBF + 8 + read-write + 0x90 + 0xFF + + + TTEN + desc TTEN + 0 + 0 + read-write + + + T_PRESC + desc T_PRESC + 2 + 1 + read-write + + + TTIF + desc TTIF + 3 + 3 + read-write + + + TTIE + desc TTIE + 4 + 4 + read-write + + + TEIF + desc TEIF + 5 + 5 + read-write + + + WTIF + desc WTIF + 6 + 6 + read-write + + + WTIE + desc WTIE + 7 + 7 + read-write + + + + + REF_MSG + desc REF_MSG + 0xC0 + 32 + read-write + 0x0 + 0x9FFFFFFF + + + REF_ID + desc REF_ID + 28 + 0 + read-write + + + REF_IDE + desc REF_IDE + 31 + 31 + read-write + + + + + TRG_CFG + desc TRG_CFG + 0xC4 + 16 + read-write + 0x0 + 0xF73F + + + TTPTR + desc TTPTR + 5 + 0 + read-write + + + TTYPE + desc TTYPE + 10 + 8 + read-write + + + TEW + desc TEW + 15 + 12 + read-write + + + + + TT_TRIG + desc TT_TRIG + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + TT_WTRIG + desc TT_WTRIG + 0xC8 + 16 + read-write + 0xFFFF + 0xFFFF + + + + + CAN2 + desc CAN + 0x40078000 + + 0x0 + 0xCA + + + + CMP1 + desc CMP + 0x4004A000 + + 0x0 + 0xA + + + + MDR + desc MDR + 0x0 + 8 + read-write + 0x0 + 0x83 + + + CENB + desc CENB + 0 + 0 + read-write + + + CWDE + desc CWDE + 1 + 1 + read-write + + + CMON + desc CMON + 7 + 7 + read-only + + + + + FIR + desc FIR + 0x1 + 8 + read-write + 0x0 + 0x73 + + + FCKS + desc FCKS + 1 + 0 + read-write + + + EDGS + desc EDGS + 5 + 4 + read-write + + + CIEN + desc CIEN + 6 + 6 + read-write + + + + + OCR + desc OCR + 0x2 + 8 + read-write + 0x0 + 0x1F + + + COEN + desc COEN + 0 + 0 + read-write + + + COPS + desc COPS + 1 + 1 + read-write + + + CPOE + desc CPOE + 2 + 2 + read-write + + + TWOE + desc TWOE + 3 + 3 + read-write + + + TWOL + desc TWOL + 4 + 4 + read-write + + + + + PMSR + desc PMSR + 0x3 + 8 + read-write + 0x0 + 0xFF + + + RVSL + desc RVSL + 3 + 0 + read-write + + + CVSL + desc CVSL + 7 + 4 + read-write + + + + + TWSR + desc TWSR + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + CTWS0 + desc CTWS0 + 0 + 0 + read-write + + + CTWS1 + desc CTWS1 + 1 + 1 + read-write + + + CTWS2 + desc CTWS2 + 2 + 2 + read-write + + + CTWS3 + desc CTWS3 + 3 + 3 + read-write + + + CTWS4 + desc CTWS4 + 4 + 4 + read-write + + + CTWS5 + desc CTWS5 + 5 + 5 + read-write + + + CTWS6 + desc CTWS6 + 6 + 6 + read-write + + + CTWS7 + desc CTWS7 + 7 + 7 + read-write + + + CTWS8 + desc CTWS8 + 8 + 8 + read-write + + + CTWS9 + desc CTWS9 + 9 + 9 + read-write + + + CTWS10 + desc CTWS10 + 10 + 10 + read-write + + + CTWS11 + desc CTWS11 + 11 + 11 + read-write + + + CTWS12 + desc CTWS12 + 12 + 12 + read-write + + + CTWS13 + desc CTWS13 + 13 + 13 + read-write + + + CTWS14 + desc CTWS14 + 14 + 14 + read-write + + + CTWS15 + desc CTWS15 + 15 + 15 + read-write + + + + + TWPR + desc TWPR + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + CTWP0 + desc CTWP0 + 0 + 0 + read-write + + + CTWP1 + desc CTWP1 + 1 + 1 + read-write + + + CTWP2 + desc CTWP2 + 2 + 2 + read-write + + + CTWP3 + desc CTWP3 + 3 + 3 + read-write + + + CTWP4 + desc CTWP4 + 4 + 4 + read-write + + + CTWP5 + desc CTWP5 + 5 + 5 + read-write + + + CTWP6 + desc CTWP6 + 6 + 6 + read-write + + + CTWP7 + desc CTWP7 + 7 + 7 + read-write + + + CTWP8 + desc CTWP8 + 8 + 8 + read-write + + + CTWP9 + desc CTWP9 + 9 + 9 + read-write + + + CTWP10 + desc CTWP10 + 10 + 10 + read-write + + + CTWP11 + desc CTWP11 + 11 + 11 + read-write + + + CTWP12 + desc CTWP12 + 12 + 12 + read-write + + + CTWP13 + desc CTWP13 + 13 + 13 + read-write + + + CTWP14 + desc CTWP14 + 14 + 14 + read-write + + + CTWP15 + desc CTWP15 + 15 + 15 + read-write + + + + + VISR + desc VISR + 0x8 + 16 + read-write + 0x0 + 0x37 + + + P2SL + desc P2SL + 2 + 0 + read-write + + + P3SL + desc P3SL + 5 + 4 + read-write + + + + + + + CMP2 + desc CMP + 0x4004A010 + + 0x0 + 0xA + + + + CMP3 + desc CMP + 0x4004A400 + + 0x0 + 0xA + + + + CMP4 + desc CMP + 0x4004A410 + + 0x0 + 0xA + + + + CMU + desc CMU + 0x4004C400 + + 0x0 + 0x7D08 + + + + XTAL32CR + desc XTAL32CR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + XTAL32STP + desc XTAL32STP + 0 + 0 + read-write + + + + + XTAL32CFGR + desc XTAL32CFGR + 0x4 + 8 + read-write + 0x0 + 0x7 + + + XTAL32DRV + desc XTAL32DRV + 2 + 0 + read-write + + + XTAL32IE + desc XTAL32IE + 3 + 3 + read-write + + + + + XTAL32NFR + desc XTAL32NFR + 0x14 + 8 + read-write + 0x0 + 0x3 + + + XTAL32NF + desc XTAL32NF + 1 + 0 + read-write + + + + + LRCCR + desc LRCCR + 0x1C + 8 + read-write + 0x0 + 0x1 + + + LRCSTP + desc LRCSTP + 0 + 0 + read-write + + + + + RTCLRCCR + desc RTCLRCCR + 0x20 + 8 + read-write + 0x0 + 0x1 + + + RTCLRCSTP + desc RTCLRCSTP + 0 + 0 + read-write + + + + + LRCTRM + desc LRCTRM + 0x24 + 8 + read-write + 0x0 + 0xFF + + + RTCLRCTRM + desc RTCLRCTRM + 0x2C + 8 + read-write + 0x0 + 0xFF + + + XTALCFGR + desc XTALCFGR + 0x878 + 8 + read-write + 0x80 + 0x70 + + + XTALDRV + desc XTALDRV + 5 + 4 + read-write + + + XTALMS + desc XTALMS + 6 + 6 + read-write + + + + + PERICKSEL + desc PERICKSEL + 0x7C10 + 16 + read-write + 0x0 + 0xF + + + PERICKSEL + desc PERICKSEL + 3 + 0 + read-write + + + + + I2SCKSEL + desc I2SCKSEL + 0x7C12 + 16 + read-write + 0xBBBB + 0xFFFF + + + I2S1CKSEL + desc I2S1CKSEL + 3 + 0 + read-write + + + I2S2CKSEL + desc I2S2CKSEL + 7 + 4 + read-write + + + I2S3CKSEL + desc I2S3CKSEL + 11 + 8 + read-write + + + I2S4CKSEL + desc I2S4CKSEL + 15 + 12 + read-write + + + + + CANCKCFGR + desc CANCKCFGR + 0x7C18 + 8 + read-write + 0xDD + 0xFF + + + CAN1CKS + desc CAN1CKS + 3 + 0 + read-write + + + CAN2CKS + desc CAN2CKS + 7 + 4 + read-write + + + + + SCFGR + desc SCFGR + 0x7C20 + 32 + read-write + 0x0 + 0x7777777 + + + PCLK0S + desc PCLK0S + 2 + 0 + read-write + + + PCLK1S + desc PCLK1S + 6 + 4 + read-write + + + PCLK2S + desc PCLK2S + 10 + 8 + read-write + + + PCLK3S + desc PCLK3S + 14 + 12 + read-write + + + PCLK4S + desc PCLK4S + 18 + 16 + read-write + + + EXCKS + desc EXCKS + 22 + 20 + read-write + + + HCLKS + desc HCLKS + 26 + 24 + read-write + + + + + USBCKCFGR + desc USBCKCFGR + 0x7C24 + 8 + read-write + 0x40 + 0xF0 + + + USBCKS + desc USBCKS + 7 + 4 + read-write + + + + + CKSWR + desc CKSWR + 0x7C26 + 8 + read-write + 0x1 + 0x7 + + + CKSW + desc CKSW + 2 + 0 + read-write + + + + + PLLHCR + desc PLLHCR + 0x7C2A + 8 + read-write + 0x1 + 0x1 + + + PLLHOFF + desc PLLHOFF + 0 + 0 + read-write + + + + + PLLACR + desc PLLACR + 0x7C2E + 8 + read-write + 0x1 + 0x1 + + + PLLAOFF + desc PLLAOFF + 0 + 0 + read-write + + + + + XTALCR + desc XTALCR + 0x7C32 + 8 + read-write + 0x1 + 0x1 + + + XTALSTP + desc XTALSTP + 0 + 0 + read-write + + + + + HRCCR + desc HRCCR + 0x7C36 + 8 + read-write + 0x1 + 0x1 + + + HRCSTP + desc HRCSTP + 0 + 0 + read-write + + + + + MRCCR + desc MRCCR + 0x7C38 + 8 + read-write + 0x80 + 0x1 + + + MRCSTP + desc MRCSTP + 0 + 0 + read-write + + + + + OSCSTBSR + desc OSCSTBSR + 0x7C3C + 8 + read-write + 0x0 + 0xE9 + + + HRCSTBF + desc HRCSTBF + 0 + 0 + read-write + + + XTALSTBF + desc XTALSTBF + 3 + 3 + read-write + + + PLLHSTBF + desc PLLHSTBF + 5 + 5 + read-write + + + PLLASTBF + desc PLLASTBF + 6 + 6 + read-write + + + + + MCOCFGR1 + desc MCOCFGR1 + 0x7C3D + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + MCOCFGR2 + desc MCOCFGR2 + 0x7C3E + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + TPIUCKCFGR + desc TPIUCKCFGR + 0x7C3F + 8 + read-write + 0x0 + 0x83 + + + TPIUCKS + desc TPIUCKS + 1 + 0 + read-write + + + TPIUCKOE + desc TPIUCKOE + 7 + 7 + read-write + + + + + XTALSTDCR + desc XTALSTDCR + 0x7C40 + 8 + read-write + 0x0 + 0x87 + + + XTALSTDIE + desc XTALSTDIE + 0 + 0 + read-write + + + XTALSTDRE + desc XTALSTDRE + 1 + 1 + read-write + + + XTALSTDRIS + desc XTALSTDRIS + 2 + 2 + read-write + + + XTALSTDE + desc XTALSTDE + 7 + 7 + read-write + + + + + XTALSTDSR + desc XTALSTDSR + 0x7C41 + 8 + read-write + 0x0 + 0x1 + + + XTALSTDF + desc XTALSTDF + 0 + 0 + read-write + + + + + MRCTRM + desc MRCTRM + 0x7C61 + 8 + read-write + 0x0 + 0xFF + + + HRCTRM + desc HRCTRM + 0x7C62 + 8 + read-write + 0x0 + 0xFF + + + XTALSTBCR + desc XTALSTBCR + 0x7CA2 + 8 + read-write + 0x5 + 0xF + + + XTALSTB + desc XTALSTB + 3 + 0 + read-write + + + + + PLLHCFGR + desc PLLHCFGR + 0x7D00 + 32 + read-write + 0x11101300 + 0xFFF1FF9F + + + PLLHM + desc PLLHM + 1 + 0 + read-write + + + PLLSRC + desc PLLSRC + 7 + 7 + read-write + + + PLLHN + desc PLLHN + 15 + 8 + read-write + + + PLLHR + desc PLLHR + 23 + 20 + read-write + + + PLLHQ + desc PLLHQ + 27 + 24 + read-write + + + PLLHP + desc PLLHP + 31 + 28 + read-write + + + + + PLLACFGR + desc PLLACFGR + 0x7D04 + 32 + read-write + 0x11101300 + 0xFFF1FF1F + + + PLLAM + desc PLLAM + 4 + 0 + read-write + + + PLLAN + desc PLLAN + 16 + 8 + read-write + + + PLLAR + desc PLLAR + 23 + 20 + read-write + + + PLLAQ + desc PLLAQ + 27 + 24 + read-write + + + PLLAP + desc PLLAP + 31 + 28 + read-write + + + + + + + CRC + desc CRC + 0x40008C00 + + 0x0 + 0x100 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x1 + 0x3 + + + CR + desc CR + 0 + 0 + read-write + + + FLAG + desc FLAG + 1 + 1 + read-only + + + + + RESLT + desc RESLT + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT0 + desc DAT0 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT1 + desc DAT1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT2 + desc DAT2 + 0x88 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT3 + desc DAT3 + 0x8C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT4 + desc DAT4 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT5 + desc DAT5 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT6 + desc DAT6 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT7 + desc DAT7 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT8 + desc DAT8 + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT9 + desc DAT9 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT10 + desc DAT10 + 0xA8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT11 + desc DAT11 + 0xAC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT12 + desc DAT12 + 0xB0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT13 + desc DAT13 + 0xB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT14 + desc DAT14 + 0xB8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT15 + desc DAT15 + 0xBC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT16 + desc DAT16 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT17 + desc DAT17 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT18 + desc DAT18 + 0xC8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT19 + desc DAT19 + 0xCC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT20 + desc DAT20 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT21 + desc DAT21 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT22 + desc DAT22 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT23 + desc DAT23 + 0xDC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT24 + desc DAT24 + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT25 + desc DAT25 + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT26 + desc DAT26 + 0xE8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT27 + desc DAT27 + 0xEC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT28 + desc DAT28 + 0xF0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT29 + desc DAT29 + 0xF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT30 + desc DAT30 + 0xF8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAT31 + desc DAT31 + 0xFC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + CTC + desc CTC + 0x40049C00 + + 0x0 + 0xC + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0x3F00F7 + + + REFPSC + desc REFPSC + 2 + 0 + read-write + + + REFCKS + desc REFCKS + 5 + 4 + read-write + + + ERRIE + desc ERRIE + 6 + 6 + read-write + + + CTCEN + desc CTCEN + 7 + 7 + read-write + + + TRMVAL + desc TRMVAL + 21 + 16 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xFFFF00FF + + + OFSVAL + desc OFSVAL + 7 + 0 + read-write + + + RLDVAL + desc RLDVAL + 31 + 16 + read-write + + + + + STR + desc STR + 0x8 + 32 + read-only + 0x0 + 0xF + + + TRIMOK + desc TRIMOK + 0 + 0 + read-only + + + TRMOVF + desc TRMOVF + 1 + 1 + read-only + + + TRMUDF + desc TRMUDF + 2 + 2 + read-only + + + CTCBSY + desc CTCBSY + 3 + 3 + read-only + + + + + + + DAC1 + desc DAC + 0x40041000 + + 0x0 + 0x1E + + + + DADR1 + desc DADR1 + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + DADR2 + desc DADR2 + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + DACR + desc DACR + 0x4 + 16 + read-write + 0x0 + 0x1F07 + + + DAEN + desc DAEN + 0 + 0 + read-write + + + DA1EN + desc DA1EN + 1 + 1 + read-write + + + DA2EN + desc DA2EN + 2 + 2 + read-write + + + ALIGN + desc ALIGN + 8 + 8 + read-write + + + DAAMP1 + desc DAAMP1 + 9 + 9 + read-write + + + DAAMP2 + desc DAAMP2 + 10 + 10 + read-write + + + EXTDSL1 + desc EXTDSL1 + 11 + 11 + read-write + + + EXTDSL2 + desc EXTDSL2 + 12 + 12 + read-write + + + + + DAADPCR + desc DAADPCR + 0x6 + 16 + read-write + 0x0 + 0x8307 + + + ADPSL1 + desc ADPSL1 + 0 + 0 + read-write + + + ADPSL2 + desc ADPSL2 + 1 + 1 + read-write + + + ADPSL3 + desc ADPSL3 + 2 + 2 + read-write + + + DA1SF + desc DA1SF + 8 + 8 + read-only + + + DA2SF + desc DA2SF + 9 + 9 + read-only + + + ADPEN + desc ADPEN + 15 + 15 + read-write + + + + + DAOCR + desc DAOCR + 0x1C + 16 + read-write + 0x0 + 0xC000 + + + DAODIS1 + desc DAODIS1 + 14 + 14 + read-write + + + DAODIS2 + desc DAODIS2 + 15 + 15 + read-write + + + + + + + DAC2 + desc DAC + 0x40041400 + + 0x0 + 0x1E + + + + DBGC + desc DBGC + 0xE0042000 + + 0x0 + 0x2C + + + + AUTHID0 + desc AUTHID0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID1 + desc AUTHID1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID2 + desc AUTHID2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESV0 + desc RESV0 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MCUSTAT + desc MCUSTAT + 0x10 + 32 + read-write + 0x0 + 0x30F + + + AUTH + desc AUTH + 0 + 0 + read-write + + + REMVLOCK + desc REMVLOCK + 1 + 1 + read-write + + + SAFTYLOCK1 + desc SAFTYLOCK1 + 2 + 2 + read-write + + + SAFTYLOCK2 + desc SAFTYLOCK2 + 3 + 3 + read-write + + + CPUSTOP + desc CPUSTOP + 8 + 8 + read-write + + + CPUSLEEP + desc CPUSLEEP + 9 + 9 + read-write + + + + + MCUCTL + desc MCUCTL + 0x14 + 32 + read-write + 0x0 + 0x103 + + + EDBGRQ + desc EDBGRQ + 0 + 0 + read-write + + + RESTART + desc RESTART + 1 + 1 + read-write + + + DIRQ + desc DIRQ + 8 + 8 + read-write + + + + + FMCCTL + desc FMCCTL + 0x18 + 32 + read-write + 0x0 + 0x7 + + + ERASEREQ + desc ERASEREQ + 0 + 0 + read-write + + + ERASEACK + desc ERASEACK + 1 + 1 + read-write + + + ERASEERR + desc ERASEERR + 2 + 2 + read-write + + + + + MCUDBGCSTAT + desc MCUDBGCSTAT + 0x1C + 32 + read-write + 0x0 + 0x3 + + + CDBGPWRUPREQ + desc CDBGPWRUPREQ + 0 + 0 + read-write + + + CDBGPWRUPACK + desc CDBGPWRUPACK + 1 + 1 + read-write + + + + + MCUSTPCTL + desc MCUSTPCTL + 0x20 + 32 + read-write + 0x3B + 0x7FFFFF + + + SWDTSTP + desc SWDTSTP + 0 + 0 + read-write + + + WDTSTP + desc WDTSTP + 1 + 1 + read-write + + + RTCSTP + desc RTCSTP + 2 + 2 + read-write + + + PVD0STP + desc PVD0STP + 3 + 3 + read-write + + + PVD1STP + desc PVD1STP + 4 + 4 + read-write + + + PVD2STP + desc PVD2STP + 5 + 5 + read-write + + + M06STP + desc M06STP + 6 + 6 + read-write + + + M07STP + desc M07STP + 7 + 7 + read-write + + + M08STP + desc M08STP + 8 + 8 + read-write + + + M09STP + desc M09STP + 9 + 9 + read-write + + + M10STP + desc M10STP + 10 + 10 + read-write + + + M11STP + desc M11STP + 11 + 11 + read-write + + + M12STP + desc M12STP + 12 + 12 + read-write + + + M13STP + desc M13STP + 13 + 13 + read-write + + + M14STP + desc M14STP + 14 + 14 + read-write + + + M15STP + desc M15STP + 15 + 15 + read-write + + + M16STP + desc M16STP + 16 + 16 + read-write + + + M17STP + desc M17STP + 17 + 17 + read-write + + + M18STP + desc M18STP + 18 + 18 + read-write + + + M19STP + desc M19STP + 19 + 19 + read-write + + + M20STP + desc M20STP + 20 + 20 + read-write + + + M21STP + desc M21STP + 21 + 21 + read-write + + + M22STP + desc M22STP + 22 + 22 + read-write + + + + + MCUTRACECTL + desc MCUTRACECTL + 0x24 + 32 + read-write + 0x0 + 0x7 + + + TRACEMODE + desc TRACEMODE + 1 + 0 + read-write + + + TRACEIOEN + desc TRACEIOEN + 2 + 2 + read-write + + + + + MCUSTPCTL2 + desc MCUSTPCTL2 + 0x28 + 32 + read-write + 0x0 + 0xFFF + + + M32STP + desc M32STP + 0 + 0 + read-write + + + M33STP + desc M33STP + 1 + 1 + read-write + + + M34STP + desc M34STP + 2 + 2 + read-write + + + M35STP + desc M35STP + 3 + 3 + read-write + + + M36STP + desc M36STP + 4 + 4 + read-write + + + M37STP + desc M37STP + 5 + 5 + read-write + + + M38STP + desc M38STP + 6 + 6 + read-write + + + M39STP + desc M39STP + 7 + 7 + read-write + + + M40STP + desc M40STP + 8 + 8 + read-write + + + M41STP + desc M41STP + 9 + 9 + read-write + + + M42STP + desc M42STP + 10 + 10 + read-write + + + M43STP + desc M43STP + 11 + 11 + read-write + + + + + + + DCU1 + desc DCU + 0x40056000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000013F + + + MODE + desc MODE + 3 + 0 + read-write + + + DATASIZE + desc DATASIZE + 5 + 4 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0xE7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + FLAG_RLD + desc FLAG_RLD + 9 + 9 + read-only + + + FLAG_BTM + desc FLAG_BTM + 10 + 10 + read-only + + + FLAG_TOP + desc FLAG_TOP + 11 + 11 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0xE7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + CLR_RLD + desc CLR_RLD + 9 + 9 + read-write + + + CLR_BTM + desc CLR_BTM + 10 + 10 + read-write + + + CLR_TOP + desc CLR_TOP + 11 + 11 + read-write + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0xFFF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + INT_RLD + desc INT_RLD + 9 + 9 + read-write + + + INT_BTM + desc INT_BTM + 10 + 10 + read-write + + + INT_TOP + desc INT_TOP + 11 + 11 + read-write + + + + + + + DCU2 + desc DCU + 0x40056400 + + 0x0 + 0x1C + + + + DCU3 + desc DCU + 0x40056800 + + 0x0 + 0x1C + + + + DCU4 + desc DCU + 0x40056C00 + + 0x0 + 0x1C + + + + DCU5 + desc DCU + 0x40057000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000013F + + + MODE + desc MODE + 3 + 0 + read-write + + + DATASIZE + desc DATASIZE + 5 + 4 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0x7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0x7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + + + + + DCU6 + desc DCU + 0x40057400 + + 0x0 + 0x1C + + + + DCU7 + desc DCU + 0x40057800 + + 0x0 + 0x1C + + + + DCU8 + desc DCU + 0x40057C00 + + 0x0 + 0x1C + + + + DMA1 + desc DMA + 0x40053000 + + 0x0 + 0x238 + + + + EN + desc EN + 0x0 + 32 + read-write + 0x0 + 0x1 + + + EN + desc EN + 0 + 0 + read-write + + + + + INTSTAT0 + desc INTSTAT0 + 0x4 + 32 + read-only + 0x0 + 0xFF00FF + + + TRNERR + desc TRNERR + 7 + 0 + read-only + + + REQERR + desc REQERR + 23 + 16 + read-only + + + + + INTSTAT1 + desc INTSTAT1 + 0x8 + 32 + read-only + 0x0 + 0xFF00FF + + + TC + desc TC + 7 + 0 + read-only + + + BTC + desc BTC + 23 + 16 + read-only + + + + + INTMASK0 + desc INTMASK0 + 0xC + 32 + read-write + 0x0 + 0xFF00FF + + + MSKTRNERR + desc MSKTRNERR + 7 + 0 + read-write + + + MSKREQERR + desc MSKREQERR + 23 + 16 + read-write + + + + + INTMASK1 + desc INTMASK1 + 0x10 + 32 + read-write + 0x0 + 0xFF00FF + + + MSKTC + desc MSKTC + 7 + 0 + read-write + + + MSKBTC + desc MSKBTC + 23 + 16 + read-write + + + + + INTCLR0 + desc INTCLR0 + 0x14 + 32 + read-write + 0x0 + 0xFF00FF + + + CLRTRNERR + desc CLRTRNERR + 7 + 0 + read-write + + + CLRREQERR + desc CLRREQERR + 23 + 16 + read-write + + + + + INTCLR1 + desc INTCLR1 + 0x18 + 32 + read-write + 0x0 + 0xFF00FF + + + CLRTC + desc CLRTC + 7 + 0 + read-write + + + CLRBTC + desc CLRBTC + 23 + 16 + read-write + + + + + CHEN + desc CHEN + 0x1C + 32 + read-write + 0x0 + 0xFF + + + CHEN + desc CHEN + 7 + 0 + read-write + + + + + REQSTAT + desc REQSTAT + 0x20 + 32 + read-only + 0x0 + 0x80FF + + + CHREQ + desc CHREQ + 7 + 0 + read-only + + + RCFGREQ + desc RCFGREQ + 15 + 15 + read-only + + + + + CHSTAT + desc CHSTAT + 0x24 + 32 + read-only + 0x0 + 0xFF0003 + + + DMAACT + desc DMAACT + 0 + 0 + read-only + + + RCFGACT + desc RCFGACT + 1 + 1 + read-only + + + CHACT + desc CHACT + 23 + 16 + read-only + + + + + RCFGCTL + desc RCFGCTL + 0x2C + 32 + read-write + 0x0 + 0x3F0F03 + + + RCFGEN + desc RCFGEN + 0 + 0 + read-write + + + RCFGLLP + desc RCFGLLP + 1 + 1 + read-write + + + RCFGCHS + desc RCFGCHS + 11 + 8 + read-write + + + SARMD + desc SARMD + 17 + 16 + read-write + + + DARMD + desc DARMD + 19 + 18 + read-write + + + CNTMD + desc CNTMD + 21 + 20 + read-write + + + + + CHENCLR + desc CHENCLR + 0x34 + 32 + read-write + 0x0 + 0xFF + + + CHENCLR + desc CHENCLR + 7 + 0 + read-write + + + + + SAR0 + desc SAR0 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR0 + desc DAR0 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL0 + desc DTCTL0 + 0x48 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT0 + desc RPT0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB0 + desc RPTB0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL0 + desc SNSEQCTL0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB0 + desc SNSEQCTLB0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL0 + desc DNSEQCTL0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB0 + desc DNSEQCTLB0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP0 + desc LLP0 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL0 + desc CHCTL0 + 0x5C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR0 + desc MONSAR0 + 0x60 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR0 + desc MONDAR0 + 0x64 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL0 + desc MONDTCTL0 + 0x68 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT0 + desc MONRPT0 + 0x6C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL0 + desc MONSNSEQCTL0 + 0x70 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL0 + desc MONDNSEQCTL0 + 0x74 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR1 + desc SAR1 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR1 + desc DAR1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL1 + desc DTCTL1 + 0x88 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT1 + desc RPT1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB1 + desc RPTB1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL1 + desc SNSEQCTL1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB1 + desc SNSEQCTLB1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL1 + desc DNSEQCTL1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB1 + desc DNSEQCTLB1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP1 + desc LLP1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL1 + desc CHCTL1 + 0x9C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR1 + desc MONSAR1 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR1 + desc MONDAR1 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL1 + desc MONDTCTL1 + 0xA8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT1 + desc MONRPT1 + 0xAC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL1 + desc MONSNSEQCTL1 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL1 + desc MONDNSEQCTL1 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR2 + desc SAR2 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR2 + desc DAR2 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL2 + desc DTCTL2 + 0xC8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT2 + desc RPT2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB2 + desc RPTB2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL2 + desc SNSEQCTL2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB2 + desc SNSEQCTLB2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL2 + desc DNSEQCTL2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB2 + desc DNSEQCTLB2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP2 + desc LLP2 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL2 + desc CHCTL2 + 0xDC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR2 + desc MONSAR2 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR2 + desc MONDAR2 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL2 + desc MONDTCTL2 + 0xE8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT2 + desc MONRPT2 + 0xEC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL2 + desc MONSNSEQCTL2 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL2 + desc MONDNSEQCTL2 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR3 + desc SAR3 + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR3 + desc DAR3 + 0x104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL3 + desc DTCTL3 + 0x108 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT3 + desc RPT3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB3 + desc RPTB3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL3 + desc SNSEQCTL3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB3 + desc SNSEQCTLB3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL3 + desc DNSEQCTL3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB3 + desc DNSEQCTLB3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP3 + desc LLP3 + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL3 + desc CHCTL3 + 0x11C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR3 + desc MONSAR3 + 0x120 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR3 + desc MONDAR3 + 0x124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL3 + desc MONDTCTL3 + 0x128 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT3 + desc MONRPT3 + 0x12C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL3 + desc MONSNSEQCTL3 + 0x130 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL3 + desc MONDNSEQCTL3 + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR4 + desc SAR4 + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR4 + desc DAR4 + 0x144 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL4 + desc DTCTL4 + 0x148 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT4 + desc RPT4 + 0x14C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB4 + desc RPTB4 + 0x14C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL4 + desc SNSEQCTL4 + 0x150 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB4 + desc SNSEQCTLB4 + 0x150 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL4 + desc DNSEQCTL4 + 0x154 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB4 + desc DNSEQCTLB4 + 0x154 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP4 + desc LLP4 + 0x158 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL4 + desc CHCTL4 + 0x15C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR4 + desc MONSAR4 + 0x160 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR4 + desc MONDAR4 + 0x164 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL4 + desc MONDTCTL4 + 0x168 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT4 + desc MONRPT4 + 0x16C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL4 + desc MONSNSEQCTL4 + 0x170 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL4 + desc MONDNSEQCTL4 + 0x174 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR5 + desc SAR5 + 0x180 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR5 + desc DAR5 + 0x184 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL5 + desc DTCTL5 + 0x188 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT5 + desc RPT5 + 0x18C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB5 + desc RPTB5 + 0x18C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL5 + desc SNSEQCTL5 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB5 + desc SNSEQCTLB5 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL5 + desc DNSEQCTL5 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB5 + desc DNSEQCTLB5 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP5 + desc LLP5 + 0x198 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL5 + desc CHCTL5 + 0x19C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR5 + desc MONSAR5 + 0x1A0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR5 + desc MONDAR5 + 0x1A4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL5 + desc MONDTCTL5 + 0x1A8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT5 + desc MONRPT5 + 0x1AC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL5 + desc MONSNSEQCTL5 + 0x1B0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL5 + desc MONDNSEQCTL5 + 0x1B4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR6 + desc SAR6 + 0x1C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR6 + desc DAR6 + 0x1C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL6 + desc DTCTL6 + 0x1C8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT6 + desc RPT6 + 0x1CC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB6 + desc RPTB6 + 0x1CC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL6 + desc SNSEQCTL6 + 0x1D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB6 + desc SNSEQCTLB6 + 0x1D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL6 + desc DNSEQCTL6 + 0x1D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB6 + desc DNSEQCTLB6 + 0x1D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP6 + desc LLP6 + 0x1D8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL6 + desc CHCTL6 + 0x1DC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR6 + desc MONSAR6 + 0x1E0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR6 + desc MONDAR6 + 0x1E4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL6 + desc MONDTCTL6 + 0x1E8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT6 + desc MONRPT6 + 0x1EC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL6 + desc MONSNSEQCTL6 + 0x1F0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL6 + desc MONDNSEQCTL6 + 0x1F4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR7 + desc SAR7 + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR7 + desc DAR7 + 0x204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL7 + desc DTCTL7 + 0x208 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT7 + desc RPT7 + 0x20C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB7 + desc RPTB7 + 0x20C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL7 + desc SNSEQCTL7 + 0x210 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB7 + desc SNSEQCTLB7 + 0x210 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL7 + desc DNSEQCTL7 + 0x214 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB7 + desc DNSEQCTLB7 + 0x214 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP7 + desc LLP7 + 0x218 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL7 + desc CHCTL7 + 0x21C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR7 + desc MONSAR7 + 0x220 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR7 + desc MONDAR7 + 0x224 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL7 + desc MONDTCTL7 + 0x228 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT7 + desc MONRPT7 + 0x22C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL7 + desc MONSNSEQCTL7 + 0x230 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL7 + desc MONDNSEQCTL7 + 0x234 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + + + DMA2 + desc DMA + 0x40053400 + + 0x0 + 0x238 + + + + DMC + desc DMC + 0x88000400 + + 0x0 + 0x304 + + + + STSR + desc STSR + 0x0 + 32 + read-only + 0x700 + 0xF + + + STATUS + desc STATUS + 1 + 0 + read-only + + + MEMW + desc MEMW + 3 + 2 + read-only + + + + + STCR + desc STCR + 0x4 + 32 + write-only + 0x0 + 0x7 + + + STCTL + desc STCTL + 2 + 0 + write-only + + + + + CMDR + desc CMDR + 0x8 + 32 + write-only + 0x0 + 0x13F3FFF + + + CMDADD + desc CMDADD + 13 + 0 + write-only + + + CMDBA + desc CMDBA + 17 + 16 + write-only + + + CMD + desc CMD + 19 + 18 + write-only + + + CMDCHIP + desc CMDCHIP + 21 + 20 + write-only + + + + + CPCR + desc CPCR + 0xC + 32 + read-write + 0x20040 + 0x307FFF7 + + + COLBS + desc COLBS + 2 + 0 + read-write + + + ROWBS + desc ROWBS + 6 + 4 + read-write + + + APBS + desc APBS + 7 + 7 + read-write + + + CKEDIS + desc CKEDIS + 8 + 8 + read-write + + + CKSTOP + desc CKSTOP + 9 + 9 + read-write + + + CKEDISPRD + desc CKEDISPRD + 15 + 10 + read-write + + + BURST + desc BURST + 18 + 16 + read-write + + + ACTCP + desc ACTCP + 25 + 24 + read-write + + + + + RFTR + desc RFTR + 0x10 + 32 + read-write + 0xA60 + 0x7FFF + + + REFPRD + desc REFPRD + 14 + 0 + read-write + + + + + TMCR_T_CASL + desc TMCR_T_CASL + 0x14 + 32 + read-write + 0x3 + 0x7 + + + T_CASL + desc T_CASL + 2 + 0 + read-write + + + + + TMCR_T_DQSS + desc TMCR_T_DQSS + 0x18 + 32 + read-write + 0x1 + 0x3 + + + T_DQSS + desc T_DQSS + 1 + 0 + read-write + + + + + TMCR_T_MRD + desc TMCR_T_MRD + 0x1C + 32 + read-write + 0x2 + 0x7F + + + T_MRD + desc T_MRD + 6 + 0 + read-write + + + + + TMCR_T_RAS + desc TMCR_T_RAS + 0x20 + 32 + read-write + 0x7 + 0xF + + + T_RAS + desc T_RAS + 3 + 0 + read-write + + + + + TMCR_T_RC + desc TMCR_T_RC + 0x24 + 32 + read-write + 0xB + 0xF + + + T_RC + desc T_RC + 3 + 0 + read-write + + + + + TMCR_T_RCD + desc TMCR_T_RCD + 0x28 + 32 + read-write + 0x35 + 0x77 + + + T_RCD_B + desc T_RCD_B + 2 + 0 + read-write + + + T_RCD_P + desc T_RCD_P + 6 + 4 + read-write + + + + + TMCR_T_RFC + desc TMCR_T_RFC + 0x2C + 32 + read-write + 0x1012 + 0x1F1F + + + T_RFC_B + desc T_RFC_B + 4 + 0 + read-write + + + T_RFC_P + desc T_RFC_P + 12 + 8 + read-write + + + + + TMCR_T_RP + desc TMCR_T_RP + 0x30 + 32 + read-write + 0x35 + 0x77 + + + T_RP_B + desc T_RP_B + 2 + 0 + read-write + + + T_RP_P + desc T_RP_P + 6 + 4 + read-write + + + + + TMCR_T_RRD + desc TMCR_T_RRD + 0x34 + 32 + read-write + 0x2 + 0xF + + + T_RRD + desc T_RRD + 3 + 0 + read-write + + + + + TMCR_T_WR + desc TMCR_T_WR + 0x38 + 32 + read-write + 0x3 + 0x7 + + + T_WR + desc T_WR + 2 + 0 + read-write + + + + + TMCR_T_WTR + desc TMCR_T_WTR + 0x3C + 32 + read-write + 0x2 + 0x7 + + + T_WTR + desc T_WTR + 2 + 0 + read-write + + + + + TMCR_T_XP + desc TMCR_T_XP + 0x40 + 32 + read-write + 0x1 + 0xFF + + + T_XP + desc T_XP + 7 + 0 + read-write + + + + + TMCR_T_XSR + desc TMCR_T_XSR + 0x44 + 32 + read-write + 0xA + 0xFF + + + T_XSR + desc T_XSR + 7 + 0 + read-write + + + + + TMCR_T_ESR + desc TMCR_T_ESR + 0x48 + 32 + read-write + 0x14 + 0xFF + + + T_ESR + desc T_ESR + 7 + 0 + read-write + + + + + CSCR0 + desc CSCR0 + 0x200 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR1 + desc CSCR1 + 0x204 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR2 + desc CSCR2 + 0x208 + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + CSCR3 + desc CSCR3 + 0x20C + 32 + read-write + 0xFF00 + 0x101FFFF + + + ADDMSK + desc ADDMSK + 7 + 0 + read-write + + + ADDMAT + desc ADDMAT + 15 + 8 + read-write + + + BRC + desc BRC + 16 + 16 + read-write + + + + + BACR + desc BACR + 0x300 + 32 + read-write + 0x300 + 0x100C003 + + + DMCMW + desc DMCMW + 1 + 0 + read-write + + + CKSEL + desc CKSEL + 15 + 14 + read-write + + + + + + + DVP + desc DVP + 0x40055800 + + 0x0 + 0x30 + + + + CTR + desc CTR + 0x0 + 32 + read-write + 0x0 + 0x4FFF + + + CAPEN + desc CAPEN + 0 + 0 + read-write + + + CAPMD + desc CAPMD + 1 + 1 + read-write + + + CROPEN + desc CROPEN + 2 + 2 + read-write + + + JPEGEN + desc JPEGEN + 3 + 3 + read-write + + + SWSYNC + desc SWSYNC + 4 + 4 + read-write + + + PIXCKSEL + desc PIXCKSEL + 5 + 5 + read-write + + + HSYNCSEL + desc HSYNCSEL + 6 + 6 + read-write + + + VSYNCSEL + desc VSYNCSEL + 7 + 7 + read-write + + + CAPFRC + desc CAPFRC + 9 + 8 + read-write + + + BITSEL + desc BITSEL + 11 + 10 + read-write + + + DVPEN + desc DVPEN + 14 + 14 + read-write + + + + + DTR + desc DTR + 0x4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + STR + desc STR + 0x8 + 32 + read-write + 0x0 + 0x3F + + + FSF + desc FSF + 0 + 0 + read-write + + + LSF + desc LSF + 1 + 1 + read-write + + + LEF + desc LEF + 2 + 2 + read-write + + + FEF + desc FEF + 3 + 3 + read-write + + + SQUERF + desc SQUERF + 4 + 4 + read-write + + + FIFOERF + desc FIFOERF + 5 + 5 + read-write + + + + + IER + desc IER + 0xC + 32 + read-write + 0x0 + 0x3F + + + FSIEN + desc FSIEN + 0 + 0 + read-write + + + LSIEN + desc LSIEN + 1 + 1 + read-write + + + LEIEN + desc LEIEN + 2 + 2 + read-write + + + FEIEN + desc FEIEN + 3 + 3 + read-write + + + SQUERIEN + desc SQUERIEN + 4 + 4 + read-write + + + FIFOERIEN + desc FIFOERIEN + 5 + 5 + read-write + + + + + DMR + desc DMR + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SSYNDR + desc SSYNDR + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FSDAT + desc FSDAT + 7 + 0 + read-write + + + LSDAT + desc LSDAT + 15 + 8 + read-write + + + LEDAT + desc LEDAT + 23 + 16 + read-write + + + FEDAT + desc FEDAT + 31 + 24 + read-write + + + + + SSYNMR + desc SSYNMR + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FSMSK + desc FSMSK + 7 + 0 + read-write + + + LSMSK + desc LSMSK + 15 + 8 + read-write + + + LEMSK + desc LEMSK + 23 + 16 + read-write + + + FEMSK + desc FEMSK + 31 + 24 + read-write + + + + + CPSFTR + desc CPSFTR + 0x28 + 32 + read-write + 0x0 + 0x3FFF3FFF + + + RSHIFT + desc RSHIFT + 13 + 0 + read-write + + + CSHIFT + desc CSHIFT + 29 + 16 + read-write + + + + + CPSZER + desc CPSZER + 0x2C + 32 + read-write + 0x0 + 0x3FFF3FFF + + + RSIZE + desc RSIZE + 13 + 0 + read-write + + + CSIZE + desc CSIZE + 29 + 16 + read-write + + + + + + + EFM + desc EFM + 0x40010400 + + 0x0 + 0x1B0 + + + + FAPRT + desc FAPRT + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + FAPRT + desc FAPRT + 15 + 0 + read-write + + + + + KEY1 + desc KEY1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KEY2 + desc KEY2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FSTP + desc FSTP + 0x14 + 32 + read-write + 0x0 + 0x3 + + + F0STP + desc F0STP + 0 + 0 + read-write + + + F1STP + desc F1STP + 1 + 1 + read-write + + + + + FRMC + desc FRMC + 0x18 + 32 + read-write + 0x0 + 0xF010F + + + FLWT + desc FLWT + 3 + 0 + read-write + + + LVM + desc LVM + 8 + 8 + read-write + + + ICACHE + desc ICACHE + 16 + 16 + read-write + + + DCACHE + desc DCACHE + 17 + 17 + read-write + + + PREFETE + desc PREFETE + 18 + 18 + read-write + + + CRST + desc CRST + 19 + 19 + read-write + + + + + FWMC + desc FWMC + 0x1C + 32 + read-write + 0x30000 + 0x30107 + + + PEMOD + desc PEMOD + 2 + 0 + read-write + + + BUSHLDCTL + desc BUSHLDCTL + 8 + 8 + read-write + + + KEY1LOCK + desc KEY1LOCK + 16 + 16 + read-write + + + KEY2LOCK + desc KEY2LOCK + 17 + 17 + read-write + + + + + FSR + desc FSR + 0x20 + 32 + read-only + 0x1000100 + 0x13E013F + + + OTPWERR0 + desc OTPWERR0 + 0 + 0 + read-only + + + PRTWERR0 + desc PRTWERR0 + 1 + 1 + read-only + + + PGSZERR0 + desc PGSZERR0 + 2 + 2 + read-only + + + MISMTCH0 + desc MISMTCH0 + 3 + 3 + read-only + + + OPTEND0 + desc OPTEND0 + 4 + 4 + read-only + + + COLERR0 + desc COLERR0 + 5 + 5 + read-only + + + RDY0 + desc RDY0 + 8 + 8 + read-only + + + PRTWERR1 + desc PRTWERR1 + 17 + 17 + read-only + + + PGSZERR1 + desc PGSZERR1 + 18 + 18 + read-only + + + MISMTCH1 + desc MISMTCH1 + 19 + 19 + read-only + + + OPTEND1 + desc OPTEND1 + 20 + 20 + read-only + + + COLERR1 + desc COLERR1 + 21 + 21 + read-only + + + RDY1 + desc RDY1 + 24 + 24 + read-only + + + + + FSCLR + desc FSCLR + 0x24 + 32 + read-write + 0x0 + 0x3E003F + + + OTPWERRCLR0 + desc OTPWERRCLR0 + 0 + 0 + read-write + + + PRTWERRCLR0 + desc PRTWERRCLR0 + 1 + 1 + read-write + + + PGSZERRCLR0 + desc PGSZERRCLR0 + 2 + 2 + read-write + + + MISMTCHCLR0 + desc MISMTCHCLR0 + 3 + 3 + read-write + + + OPTENDCLR0 + desc OPTENDCLR0 + 4 + 4 + read-write + + + COLERRCLR0 + desc COLERRCLR0 + 5 + 5 + read-write + + + PRTWERRCLR1 + desc PRTWERRCLR1 + 17 + 17 + read-write + + + PGSZERRCLR1 + desc PGSZERRCLR1 + 18 + 18 + read-write + + + MISMTCHCLR1 + desc MISMTCHCLR1 + 19 + 19 + read-write + + + OPTENDCLR1 + desc OPTENDCLR1 + 20 + 20 + read-write + + + COLERRCLR1 + desc COLERRCLR1 + 21 + 21 + read-write + + + + + FITE + desc FITE + 0x28 + 32 + read-write + 0x0 + 0x7 + + + PEERRITE + desc PEERRITE + 0 + 0 + read-write + + + OPTENDITE + desc OPTENDITE + 1 + 1 + read-write + + + COLERRITE + desc COLERRITE + 2 + 2 + read-write + + + + + FSWP + desc FSWP + 0x2C + 32 + read-only + 0x0 + 0x1 + + + FSWP + desc FSWP + 0 + 0 + read-only + + + + + CHIPID + desc CHIPID + 0x40 + 32 + read-only + 0x484404A0 + 0xFFFFFFFF + + + UQID0 + desc UQID0 + 0x50 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID1 + desc UQID1 + 0x54 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID2 + desc UQID2 + 0x58 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 15 + 0 + read-write + + + + + MMF_REMCR0 + desc MMF_REMCR0 + 0x104 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + MMF_REMCR1 + desc MMF_REMCR1 + 0x108 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + WLOCK + desc WLOCK + 0x180 + 32 + read-write + 0x0 + 0xFF + + + WLOCK + desc WLOCK + 7 + 0 + read-write + + + + + F0NWPRT0 + desc F0NWPRT0 + 0x190 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT0 + desc F0NWPRT0 + 0 + 0 + read-write + + + F0NWPRT1 + desc F0NWPRT1 + 1 + 1 + read-write + + + F0NWPRT2 + desc F0NWPRT2 + 2 + 2 + read-write + + + F0NWPRT3 + desc F0NWPRT3 + 3 + 3 + read-write + + + F0NWPRT4 + desc F0NWPRT4 + 4 + 4 + read-write + + + F0NWPRT5 + desc F0NWPRT5 + 5 + 5 + read-write + + + F0NWPRT6 + desc F0NWPRT6 + 6 + 6 + read-write + + + F0NWPRT7 + desc F0NWPRT7 + 7 + 7 + read-write + + + F0NWPRT8 + desc F0NWPRT8 + 8 + 8 + read-write + + + F0NWPRT9 + desc F0NWPRT9 + 9 + 9 + read-write + + + F0NWPRT10 + desc F0NWPRT10 + 10 + 10 + read-write + + + F0NWPRT11 + desc F0NWPRT11 + 11 + 11 + read-write + + + F0NWPRT12 + desc F0NWPRT12 + 12 + 12 + read-write + + + F0NWPRT13 + desc F0NWPRT13 + 13 + 13 + read-write + + + F0NWPRT14 + desc F0NWPRT14 + 14 + 14 + read-write + + + F0NWPRT15 + desc F0NWPRT15 + 15 + 15 + read-write + + + F0NWPRT16 + desc F0NWPRT16 + 16 + 16 + read-write + + + F0NWPRT17 + desc F0NWPRT17 + 17 + 17 + read-write + + + F0NWPRT18 + desc F0NWPRT18 + 18 + 18 + read-write + + + F0NWPRT19 + desc F0NWPRT19 + 19 + 19 + read-write + + + F0NWPRT20 + desc F0NWPRT20 + 20 + 20 + read-write + + + F0NWPRT21 + desc F0NWPRT21 + 21 + 21 + read-write + + + F0NWPRT22 + desc F0NWPRT22 + 22 + 22 + read-write + + + F0NWPRT23 + desc F0NWPRT23 + 23 + 23 + read-write + + + F0NWPRT24 + desc F0NWPRT24 + 24 + 24 + read-write + + + F0NWPRT25 + desc F0NWPRT25 + 25 + 25 + read-write + + + F0NWPRT26 + desc F0NWPRT26 + 26 + 26 + read-write + + + F0NWPRT27 + desc F0NWPRT27 + 27 + 27 + read-write + + + F0NWPRT28 + desc F0NWPRT28 + 28 + 28 + read-write + + + F0NWPRT29 + desc F0NWPRT29 + 29 + 29 + read-write + + + F0NWPRT30 + desc F0NWPRT30 + 30 + 30 + read-write + + + F0NWPRT31 + desc F0NWPRT31 + 31 + 31 + read-write + + + + + F0NWPRT1 + desc F0NWPRT1 + 0x194 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT32 + desc F0NWPRT32 + 0 + 0 + read-write + + + F0NWPRT33 + desc F0NWPRT33 + 1 + 1 + read-write + + + F0NWPRT34 + desc F0NWPRT34 + 2 + 2 + read-write + + + F0NWPRT35 + desc F0NWPRT35 + 3 + 3 + read-write + + + F0NWPRT36 + desc F0NWPRT36 + 4 + 4 + read-write + + + F0NWPRT37 + desc F0NWPRT37 + 5 + 5 + read-write + + + F0NWPRT38 + desc F0NWPRT38 + 6 + 6 + read-write + + + F0NWPRT39 + desc F0NWPRT39 + 7 + 7 + read-write + + + F0NWPRT40 + desc F0NWPRT40 + 8 + 8 + read-write + + + F0NWPRT41 + desc F0NWPRT41 + 9 + 9 + read-write + + + F0NWPRT42 + desc F0NWPRT42 + 10 + 10 + read-write + + + F0NWPRT43 + desc F0NWPRT43 + 11 + 11 + read-write + + + F0NWPRT44 + desc F0NWPRT44 + 12 + 12 + read-write + + + F0NWPRT45 + desc F0NWPRT45 + 13 + 13 + read-write + + + F0NWPRT46 + desc F0NWPRT46 + 14 + 14 + read-write + + + F0NWPRT47 + desc F0NWPRT47 + 15 + 15 + read-write + + + F0NWPRT48 + desc F0NWPRT48 + 16 + 16 + read-write + + + F0NWPRT49 + desc F0NWPRT49 + 17 + 17 + read-write + + + F0NWPRT50 + desc F0NWPRT50 + 18 + 18 + read-write + + + F0NWPRT51 + desc F0NWPRT51 + 19 + 19 + read-write + + + F0NWPRT52 + desc F0NWPRT52 + 20 + 20 + read-write + + + F0NWPRT53 + desc F0NWPRT53 + 21 + 21 + read-write + + + F0NWPRT54 + desc F0NWPRT54 + 22 + 22 + read-write + + + F0NWPRT55 + desc F0NWPRT55 + 23 + 23 + read-write + + + F0NWPRT56 + desc F0NWPRT56 + 24 + 24 + read-write + + + F0NWPRT57 + desc F0NWPRT57 + 25 + 25 + read-write + + + F0NWPRT58 + desc F0NWPRT58 + 26 + 26 + read-write + + + F0NWPRT59 + desc F0NWPRT59 + 27 + 27 + read-write + + + F0NWPRT60 + desc F0NWPRT60 + 28 + 28 + read-write + + + F0NWPRT61 + desc F0NWPRT61 + 29 + 29 + read-write + + + F0NWPRT62 + desc F0NWPRT62 + 30 + 30 + read-write + + + F0NWPRT63 + desc F0NWPRT63 + 31 + 31 + read-write + + + + + F0NWPRT2 + desc F0NWPRT2 + 0x198 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT64 + desc F0NWPRT64 + 0 + 0 + read-write + + + F0NWPRT65 + desc F0NWPRT65 + 1 + 1 + read-write + + + F0NWPRT66 + desc F0NWPRT66 + 2 + 2 + read-write + + + F0NWPRT67 + desc F0NWPRT67 + 3 + 3 + read-write + + + F0NWPRT68 + desc F0NWPRT68 + 4 + 4 + read-write + + + F0NWPRT69 + desc F0NWPRT69 + 5 + 5 + read-write + + + F0NWPRT70 + desc F0NWPRT70 + 6 + 6 + read-write + + + F0NWPRT71 + desc F0NWPRT71 + 7 + 7 + read-write + + + F0NWPRT72 + desc F0NWPRT72 + 8 + 8 + read-write + + + F0NWPRT73 + desc F0NWPRT73 + 9 + 9 + read-write + + + F0NWPRT74 + desc F0NWPRT74 + 10 + 10 + read-write + + + F0NWPRT75 + desc F0NWPRT75 + 11 + 11 + read-write + + + F0NWPRT76 + desc F0NWPRT76 + 12 + 12 + read-write + + + F0NWPRT77 + desc F0NWPRT77 + 13 + 13 + read-write + + + F0NWPRT78 + desc F0NWPRT78 + 14 + 14 + read-write + + + F0NWPRT79 + desc F0NWPRT79 + 15 + 15 + read-write + + + F0NWPRT80 + desc F0NWPRT80 + 16 + 16 + read-write + + + F0NWPRT81 + desc F0NWPRT81 + 17 + 17 + read-write + + + F0NWPRT82 + desc F0NWPRT82 + 18 + 18 + read-write + + + F0NWPRT83 + desc F0NWPRT83 + 19 + 19 + read-write + + + F0NWPRT84 + desc F0NWPRT84 + 20 + 20 + read-write + + + F0NWPRT85 + desc F0NWPRT85 + 21 + 21 + read-write + + + F0NWPRT86 + desc F0NWPRT86 + 22 + 22 + read-write + + + F0NWPRT87 + desc F0NWPRT87 + 23 + 23 + read-write + + + F0NWPRT88 + desc F0NWPRT88 + 24 + 24 + read-write + + + F0NWPRT89 + desc F0NWPRT89 + 25 + 25 + read-write + + + F0NWPRT90 + desc F0NWPRT90 + 26 + 26 + read-write + + + F0NWPRT91 + desc F0NWPRT91 + 27 + 27 + read-write + + + F0NWPRT92 + desc F0NWPRT92 + 28 + 28 + read-write + + + F0NWPRT93 + desc F0NWPRT93 + 29 + 29 + read-write + + + F0NWPRT94 + desc F0NWPRT94 + 30 + 30 + read-write + + + F0NWPRT95 + desc F0NWPRT95 + 31 + 31 + read-write + + + + + F0NWPRT3 + desc F0NWPRT3 + 0x19C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F0NWPRT96 + desc F0NWPRT96 + 0 + 0 + read-write + + + F0NWPRT97 + desc F0NWPRT97 + 1 + 1 + read-write + + + F0NWPRT98 + desc F0NWPRT98 + 2 + 2 + read-write + + + F0NWPRT99 + desc F0NWPRT99 + 3 + 3 + read-write + + + F0NWPRT100 + desc F0NWPRT100 + 4 + 4 + read-write + + + F0NWPRT101 + desc F0NWPRT101 + 5 + 5 + read-write + + + F0NWPRT102 + desc F0NWPRT102 + 6 + 6 + read-write + + + F0NWPRT103 + desc F0NWPRT103 + 7 + 7 + read-write + + + F0NWPRT104 + desc F0NWPRT104 + 8 + 8 + read-write + + + F0NWPRT105 + desc F0NWPRT105 + 9 + 9 + read-write + + + F0NWPRT106 + desc F0NWPRT106 + 10 + 10 + read-write + + + F0NWPRT107 + desc F0NWPRT107 + 11 + 11 + read-write + + + F0NWPRT108 + desc F0NWPRT108 + 12 + 12 + read-write + + + F0NWPRT109 + desc F0NWPRT109 + 13 + 13 + read-write + + + F0NWPRT110 + desc F0NWPRT110 + 14 + 14 + read-write + + + F0NWPRT111 + desc F0NWPRT111 + 15 + 15 + read-write + + + F0NWPRT112 + desc F0NWPRT112 + 16 + 16 + read-write + + + F0NWPRT113 + desc F0NWPRT113 + 17 + 17 + read-write + + + F0NWPRT114 + desc F0NWPRT114 + 18 + 18 + read-write + + + F0NWPRT115 + desc F0NWPRT115 + 19 + 19 + read-write + + + F0NWPRT116 + desc F0NWPRT116 + 20 + 20 + read-write + + + F0NWPRT117 + desc F0NWPRT117 + 21 + 21 + read-write + + + F0NWPRT118 + desc F0NWPRT118 + 22 + 22 + read-write + + + F0NWPRT119 + desc F0NWPRT119 + 23 + 23 + read-write + + + F0NWPRT120 + desc F0NWPRT120 + 24 + 24 + read-write + + + F0NWPRT121 + desc F0NWPRT121 + 25 + 25 + read-write + + + F0NWPRT122 + desc F0NWPRT122 + 26 + 26 + read-write + + + F0NWPRT123 + desc F0NWPRT123 + 27 + 27 + read-write + + + F0NWPRT124 + desc F0NWPRT124 + 28 + 28 + read-write + + + F0NWPRT125 + desc F0NWPRT125 + 29 + 29 + read-write + + + F0NWPRT126 + desc F0NWPRT126 + 30 + 30 + read-write + + + F0NWPRT127 + desc F0NWPRT127 + 31 + 31 + read-write + + + + + F1NWPRT0 + desc F1NWPRT0 + 0x1A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT0 + desc F1NWPRT0 + 0 + 0 + read-write + + + F1NWPRT1 + desc F1NWPRT1 + 1 + 1 + read-write + + + F1NWPRT2 + desc F1NWPRT2 + 2 + 2 + read-write + + + F1NWPRT3 + desc F1NWPRT3 + 3 + 3 + read-write + + + F1NWPRT4 + desc F1NWPRT4 + 4 + 4 + read-write + + + F1NWPRT5 + desc F1NWPRT5 + 5 + 5 + read-write + + + F1NWPRT6 + desc F1NWPRT6 + 6 + 6 + read-write + + + F1NWPRT7 + desc F1NWPRT7 + 7 + 7 + read-write + + + F1NWPRT8 + desc F1NWPRT8 + 8 + 8 + read-write + + + F1NWPRT9 + desc F1NWPRT9 + 9 + 9 + read-write + + + F1NWPRT10 + desc F1NWPRT10 + 10 + 10 + read-write + + + F1NWPRT11 + desc F1NWPRT11 + 11 + 11 + read-write + + + F1NWPRT12 + desc F1NWPRT12 + 12 + 12 + read-write + + + F1NWPRT13 + desc F1NWPRT13 + 13 + 13 + read-write + + + F1NWPRT14 + desc F1NWPRT14 + 14 + 14 + read-write + + + F1NWPRT15 + desc F1NWPRT15 + 15 + 15 + read-write + + + F1NWPRT16 + desc F1NWPRT16 + 16 + 16 + read-write + + + F1NWPRT17 + desc F1NWPRT17 + 17 + 17 + read-write + + + F1NWPRT18 + desc F1NWPRT18 + 18 + 18 + read-write + + + F1NWPRT19 + desc F1NWPRT19 + 19 + 19 + read-write + + + F1NWPRT20 + desc F1NWPRT20 + 20 + 20 + read-write + + + F1NWPRT21 + desc F1NWPRT21 + 21 + 21 + read-write + + + F1NWPRT22 + desc F1NWPRT22 + 22 + 22 + read-write + + + F1NWPRT23 + desc F1NWPRT23 + 23 + 23 + read-write + + + F1NWPRT24 + desc F1NWPRT24 + 24 + 24 + read-write + + + F1NWPRT25 + desc F1NWPRT25 + 25 + 25 + read-write + + + F1NWPRT26 + desc F1NWPRT26 + 26 + 26 + read-write + + + F1NWPRT27 + desc F1NWPRT27 + 27 + 27 + read-write + + + F1NWPRT28 + desc F1NWPRT28 + 28 + 28 + read-write + + + F1NWPRT29 + desc F1NWPRT29 + 29 + 29 + read-write + + + F1NWPRT30 + desc F1NWPRT30 + 30 + 30 + read-write + + + F1NWPRT31 + desc F1NWPRT31 + 31 + 31 + read-write + + + + + F1NWPRT1 + desc F1NWPRT1 + 0x1A4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT32 + desc F1NWPRT32 + 0 + 0 + read-write + + + F1NWPRT33 + desc F1NWPRT33 + 1 + 1 + read-write + + + F1NWPRT34 + desc F1NWPRT34 + 2 + 2 + read-write + + + F1NWPRT35 + desc F1NWPRT35 + 3 + 3 + read-write + + + F1NWPRT36 + desc F1NWPRT36 + 4 + 4 + read-write + + + F1NWPRT37 + desc F1NWPRT37 + 5 + 5 + read-write + + + F1NWPRT38 + desc F1NWPRT38 + 6 + 6 + read-write + + + F1NWPRT39 + desc F1NWPRT39 + 7 + 7 + read-write + + + F1NWPRT40 + desc F1NWPRT40 + 8 + 8 + read-write + + + F1NWPRT41 + desc F1NWPRT41 + 9 + 9 + read-write + + + F1NWPRT42 + desc F1NWPRT42 + 10 + 10 + read-write + + + F1NWPRT43 + desc F1NWPRT43 + 11 + 11 + read-write + + + F1NWPRT44 + desc F1NWPRT44 + 12 + 12 + read-write + + + F1NWPRT45 + desc F1NWPRT45 + 13 + 13 + read-write + + + F1NWPRT46 + desc F1NWPRT46 + 14 + 14 + read-write + + + F1NWPRT47 + desc F1NWPRT47 + 15 + 15 + read-write + + + F1NWPRT48 + desc F1NWPRT48 + 16 + 16 + read-write + + + F1NWPRT49 + desc F1NWPRT49 + 17 + 17 + read-write + + + F1NWPRT50 + desc F1NWPRT50 + 18 + 18 + read-write + + + F1NWPRT51 + desc F1NWPRT51 + 19 + 19 + read-write + + + F1NWPRT52 + desc F1NWPRT52 + 20 + 20 + read-write + + + F1NWPRT53 + desc F1NWPRT53 + 21 + 21 + read-write + + + F1NWPRT54 + desc F1NWPRT54 + 22 + 22 + read-write + + + F1NWPRT55 + desc F1NWPRT55 + 23 + 23 + read-write + + + F1NWPRT56 + desc F1NWPRT56 + 24 + 24 + read-write + + + F1NWPRT57 + desc F1NWPRT57 + 25 + 25 + read-write + + + F1NWPRT58 + desc F1NWPRT58 + 26 + 26 + read-write + + + F1NWPRT59 + desc F1NWPRT59 + 27 + 27 + read-write + + + F1NWPRT60 + desc F1NWPRT60 + 28 + 28 + read-write + + + F1NWPRT61 + desc F1NWPRT61 + 29 + 29 + read-write + + + F1NWPRT62 + desc F1NWPRT62 + 30 + 30 + read-write + + + F1NWPRT63 + desc F1NWPRT63 + 31 + 31 + read-write + + + + + F1NWPRT2 + desc F1NWPRT2 + 0x1A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT64 + desc F1NWPRT64 + 0 + 0 + read-write + + + F1NWPRT65 + desc F1NWPRT65 + 1 + 1 + read-write + + + F1NWPRT66 + desc F1NWPRT66 + 2 + 2 + read-write + + + F1NWPRT67 + desc F1NWPRT67 + 3 + 3 + read-write + + + F1NWPRT68 + desc F1NWPRT68 + 4 + 4 + read-write + + + F1NWPRT69 + desc F1NWPRT69 + 5 + 5 + read-write + + + F1NWPRT70 + desc F1NWPRT70 + 6 + 6 + read-write + + + F1NWPRT71 + desc F1NWPRT71 + 7 + 7 + read-write + + + F1NWPRT72 + desc F1NWPRT72 + 8 + 8 + read-write + + + F1NWPRT73 + desc F1NWPRT73 + 9 + 9 + read-write + + + F1NWPRT74 + desc F1NWPRT74 + 10 + 10 + read-write + + + F1NWPRT75 + desc F1NWPRT75 + 11 + 11 + read-write + + + F1NWPRT76 + desc F1NWPRT76 + 12 + 12 + read-write + + + F1NWPRT77 + desc F1NWPRT77 + 13 + 13 + read-write + + + F1NWPRT78 + desc F1NWPRT78 + 14 + 14 + read-write + + + F1NWPRT79 + desc F1NWPRT79 + 15 + 15 + read-write + + + F1NWPRT80 + desc F1NWPRT80 + 16 + 16 + read-write + + + F1NWPRT81 + desc F1NWPRT81 + 17 + 17 + read-write + + + F1NWPRT82 + desc F1NWPRT82 + 18 + 18 + read-write + + + F1NWPRT83 + desc F1NWPRT83 + 19 + 19 + read-write + + + F1NWPRT84 + desc F1NWPRT84 + 20 + 20 + read-write + + + F1NWPRT85 + desc F1NWPRT85 + 21 + 21 + read-write + + + F1NWPRT86 + desc F1NWPRT86 + 22 + 22 + read-write + + + F1NWPRT87 + desc F1NWPRT87 + 23 + 23 + read-write + + + F1NWPRT88 + desc F1NWPRT88 + 24 + 24 + read-write + + + F1NWPRT89 + desc F1NWPRT89 + 25 + 25 + read-write + + + F1NWPRT90 + desc F1NWPRT90 + 26 + 26 + read-write + + + F1NWPRT91 + desc F1NWPRT91 + 27 + 27 + read-write + + + F1NWPRT92 + desc F1NWPRT92 + 28 + 28 + read-write + + + F1NWPRT93 + desc F1NWPRT93 + 29 + 29 + read-write + + + F1NWPRT94 + desc F1NWPRT94 + 30 + 30 + read-write + + + F1NWPRT95 + desc F1NWPRT95 + 31 + 31 + read-write + + + + + F1NWPRT3 + desc F1NWPRT3 + 0x1AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + F1NWPRT96 + desc F1NWPRT96 + 0 + 0 + read-write + + + F1NWPRT97 + desc F1NWPRT97 + 1 + 1 + read-write + + + F1NWPRT98 + desc F1NWPRT98 + 2 + 2 + read-write + + + F1NWPRT99 + desc F1NWPRT99 + 3 + 3 + read-write + + + F1NWPRT100 + desc F1NWPRT100 + 4 + 4 + read-write + + + F1NWPRT101 + desc F1NWPRT101 + 5 + 5 + read-write + + + F1NWPRT102 + desc F1NWPRT102 + 6 + 6 + read-write + + + F1NWPRT103 + desc F1NWPRT103 + 7 + 7 + read-write + + + F1NWPRT104 + desc F1NWPRT104 + 8 + 8 + read-write + + + F1NWPRT105 + desc F1NWPRT105 + 9 + 9 + read-write + + + F1NWPRT106 + desc F1NWPRT106 + 10 + 10 + read-write + + + F1NWPRT107 + desc F1NWPRT107 + 11 + 11 + read-write + + + F1NWPRT108 + desc F1NWPRT108 + 12 + 12 + read-write + + + F1NWPRT109 + desc F1NWPRT109 + 13 + 13 + read-write + + + F1NWPRT110 + desc F1NWPRT110 + 14 + 14 + read-write + + + F1NWPRT111 + desc F1NWPRT111 + 15 + 15 + read-write + + + F1NWPRT112 + desc F1NWPRT112 + 16 + 16 + read-write + + + F1NWPRT113 + desc F1NWPRT113 + 17 + 17 + read-write + + + F1NWPRT114 + desc F1NWPRT114 + 18 + 18 + read-write + + + F1NWPRT115 + desc F1NWPRT115 + 19 + 19 + read-write + + + F1NWPRT116 + desc F1NWPRT116 + 20 + 20 + read-write + + + F1NWPRT117 + desc F1NWPRT117 + 21 + 21 + read-write + + + F1NWPRT118 + desc F1NWPRT118 + 22 + 22 + read-write + + + F1NWPRT119 + desc F1NWPRT119 + 23 + 23 + read-write + + + F1NWPRT120 + desc F1NWPRT120 + 24 + 24 + read-write + + + F1NWPRT121 + desc F1NWPRT121 + 25 + 25 + read-write + + + F1NWPRT122 + desc F1NWPRT122 + 26 + 26 + read-write + + + F1NWPRT123 + desc F1NWPRT123 + 27 + 27 + read-write + + + F1NWPRT124 + desc F1NWPRT124 + 28 + 28 + read-write + + + F1NWPRT125 + desc F1NWPRT125 + 29 + 29 + read-write + + + F1NWPRT126 + desc F1NWPRT126 + 30 + 30 + read-write + + + F1NWPRT127 + desc F1NWPRT127 + 31 + 31 + read-write + + + + + + + EMB0 + desc EMB + 0x40017C00 + + 0x0 + 0x1C + + + + CTL1 + desc CTL1 + 0x0 + 32 + read-write + 0x0 + 0x3CF1FFF + + + CMPEN0 + desc CMPEN0 + 0 + 0 + read-write + + + CMPEN1 + desc CMPEN1 + 1 + 1 + read-write + + + CMPEN2 + desc CMPEN2 + 2 + 2 + read-write + + + CMPEN3 + desc CMPEN3 + 3 + 3 + read-write + + + OSCSTPEN + desc OSCSTPEN + 4 + 4 + read-write + + + PWMSEN0 + desc PWMSEN0 + 5 + 5 + read-write + + + PWMSEN1 + desc PWMSEN1 + 6 + 6 + read-write + + + PWMSEN2 + desc PWMSEN2 + 7 + 7 + read-write + + + PWMSEN3 + desc PWMSEN3 + 8 + 8 + read-write + + + PWMSEN4 + desc PWMSEN4 + 9 + 9 + read-write + + + PWMSEN5 + desc PWMSEN5 + 10 + 10 + read-write + + + PWMSEN6 + desc PWMSEN6 + 11 + 11 + read-write + + + PWMSEN7 + desc PWMSEN7 + 12 + 12 + read-write + + + PORTINEN1 + desc PORTINEN1 + 16 + 16 + read-write + + + PORTINEN2 + desc PORTINEN2 + 17 + 17 + read-write + + + PORTINEN3 + desc PORTINEN3 + 18 + 18 + read-write + + + PORTINEN4 + desc PORTINEN4 + 19 + 19 + read-write + + + INVSEL1 + desc INVSEL1 + 22 + 22 + read-write + + + INVSEL2 + desc INVSEL2 + 23 + 23 + read-write + + + INVSEL3 + desc INVSEL3 + 24 + 24 + read-write + + + INVSEL4 + desc INVSEL4 + 25 + 25 + read-write + + + + + CTL2 + desc CTL2 + 0x4 + 32 + read-write + 0x0 + 0xFFF00FF + + + PWMLV0 + desc PWMLV0 + 0 + 0 + read-write + + + PWMLV1 + desc PWMLV1 + 1 + 1 + read-write + + + PWMLV2 + desc PWMLV2 + 2 + 2 + read-write + + + PWMLV3 + desc PWMLV3 + 3 + 3 + read-write + + + PWMLV4 + desc PWMLV4 + 4 + 4 + read-write + + + PWMLV5 + desc PWMLV5 + 5 + 5 + read-write + + + PWMLV6 + desc PWMLV6 + 6 + 6 + read-write + + + PWMLV7 + desc PWMLV7 + 7 + 7 + read-write + + + NFSEL1 + desc NFSEL1 + 17 + 16 + read-write + + + NFEN1 + desc NFEN1 + 18 + 18 + read-write + + + NFSEL2 + desc NFSEL2 + 20 + 19 + read-write + + + NFEN2 + desc NFEN2 + 21 + 21 + read-write + + + NFSEL3 + desc NFSEL3 + 23 + 22 + read-write + + + NFEN3 + desc NFEN3 + 24 + 24 + read-write + + + NFSEL4 + desc NFSEL4 + 26 + 25 + read-write + + + NFEN4 + desc NFEN4 + 27 + 27 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3CFEE + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + CMPST + desc CMPST + 6 + 6 + read-only + + + OSST + desc OSST + 7 + 7 + read-only + + + PORTINF1 + desc PORTINF1 + 8 + 8 + read-only + + + PORTINF2 + desc PORTINF2 + 9 + 9 + read-only + + + PORTINF3 + desc PORTINF3 + 10 + 10 + read-only + + + PORTINF4 + desc PORTINF4 + 11 + 11 + read-only + + + PORTINST1 + desc PORTINST1 + 14 + 14 + read-only + + + PORTINST2 + desc PORTINST2 + 15 + 15 + read-only + + + PORTINST3 + desc PORTINST3 + 16 + 16 + read-only + + + PORTINST4 + desc PORTINST4 + 17 + 17 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF0E + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + PORTINFCLR1 + desc PORTINFCLR1 + 8 + 8 + write-only + + + PORTINFCLR2 + desc PORTINFCLR2 + 9 + 9 + write-only + + + PORTINFCLR3 + desc PORTINFCLR3 + 10 + 10 + write-only + + + PORTINFCLR4 + desc PORTINFCLR4 + 11 + 11 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF0E + + + PWMSINTEN + desc PWMSINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + PORTINTEN1 + desc PORTINTEN1 + 8 + 8 + read-write + + + PORTINTEN2 + desc PORTINTEN2 + 9 + 9 + read-write + + + PORTINTEN3 + desc PORTINTEN3 + 10 + 10 + read-write + + + PORTINTEN4 + desc PORTINTEN4 + 11 + 11 + read-write + + + + + RLSSEL + desc RLSSEL + 0x18 + 32 + read-write + 0x0 + 0xF0E + + + PWMRSEL + desc PWMRSEL + 1 + 1 + read-write + + + CMPRSEL + desc CMPRSEL + 2 + 2 + read-write + + + OSRSEL + desc OSRSEL + 3 + 3 + read-write + + + PORTINRSEL1 + desc PORTINRSEL1 + 8 + 8 + read-write + + + PORTINRSEL2 + desc PORTINRSEL2 + 9 + 9 + read-write + + + PORTINRSEL3 + desc PORTINRSEL3 + 10 + 10 + read-write + + + PORTINRSEL4 + desc PORTINRSEL4 + 11 + 11 + read-write + + + + + + + EMB1 + desc EMB + 0x40017C20 + + 0x0 + 0x1C + + + + EMB2 + desc EMB + 0x40017C40 + + 0x0 + 0x1C + + + + EMB3 + desc EMB + 0x40017C60 + + 0x0 + 0x1C + + + + EMB4 + desc EMB + 0x40017C80 + + 0x0 + 0x1C + + + + CTL1 + desc CTL1 + 0x0 + 32 + read-write + 0x0 + 0x3CF00FF + + + CMPEN + desc CMPEN + 3 + 0 + read-write + + + OSCSTPEN + desc OSCSTPEN + 4 + 4 + read-write + + + PWMSEN + desc PWMSEN + 7 + 5 + read-write + + + PORTINEN1 + desc PORTINEN1 + 16 + 16 + read-write + + + PORTINEN2 + desc PORTINEN2 + 17 + 17 + read-write + + + PORTINEN3 + desc PORTINEN3 + 18 + 18 + read-write + + + PORTINEN4 + desc PORTINEN4 + 19 + 19 + read-write + + + INVSEL1 + desc INVSEL1 + 22 + 22 + read-write + + + INVSEL2 + desc INVSEL2 + 23 + 23 + read-write + + + INVSEL3 + desc INVSEL3 + 24 + 24 + read-write + + + INVSEL4 + desc INVSEL4 + 25 + 25 + read-write + + + + + CTL2 + desc CTL2 + 0x4 + 32 + read-write + 0x0 + 0xFFF0007 + + + PWMLV + desc PWMLV + 2 + 0 + read-write + + + NFSEL1 + desc NFSEL1 + 17 + 16 + read-write + + + NFEN1 + desc NFEN1 + 18 + 18 + read-write + + + NFSEL2 + desc NFSEL2 + 20 + 19 + read-write + + + NFEN2 + desc NFEN2 + 21 + 21 + read-write + + + NFSEL3 + desc NFSEL3 + 23 + 22 + read-write + + + NFEN3 + desc NFEN3 + 24 + 24 + read-write + + + NFSEL4 + desc NFSEL4 + 26 + 25 + read-write + + + NFEN4 + desc NFEN4 + 27 + 27 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3CFEE + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + CMPST + desc CMPST + 6 + 6 + read-only + + + OSST + desc OSST + 7 + 7 + read-only + + + PORTINF1 + desc PORTINF1 + 8 + 8 + read-only + + + PORTINF2 + desc PORTINF2 + 9 + 9 + read-only + + + PORTINF3 + desc PORTINF3 + 10 + 10 + read-only + + + PORTINF4 + desc PORTINF4 + 11 + 11 + read-only + + + PORTINST1 + desc PORTINST1 + 14 + 14 + read-only + + + PORTINST2 + desc PORTINST2 + 15 + 15 + read-only + + + PORTINST3 + desc PORTINST3 + 16 + 16 + read-only + + + PORTINST4 + desc PORTINST4 + 17 + 17 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF0E + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + PORTINFCLR1 + desc PORTINFCLR1 + 8 + 8 + write-only + + + PORTINFCLR2 + desc PORTINFCLR2 + 9 + 9 + write-only + + + PORTINFCLR3 + desc PORTINFCLR3 + 10 + 10 + write-only + + + PORTINFCLR4 + desc PORTINFCLR4 + 11 + 11 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF0E + + + PWMSINTEN + desc PWMSINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + PORTINTEN1 + desc PORTINTEN1 + 8 + 8 + read-write + + + PORTINTEN2 + desc PORTINTEN2 + 9 + 9 + read-write + + + PORTINTEN3 + desc PORTINTEN3 + 10 + 10 + read-write + + + PORTINTEN4 + desc PORTINTEN4 + 11 + 11 + read-write + + + + + RLSSEL + desc RLSSEL + 0x18 + 32 + read-write + 0x0 + 0xF0E + + + PWMRSEL + desc PWMRSEL + 1 + 1 + read-write + + + CMPRSEL + desc CMPRSEL + 2 + 2 + read-write + + + OSRSEL + desc OSRSEL + 3 + 3 + read-write + + + PORTINRSEL1 + desc PORTINRSEL1 + 8 + 8 + read-write + + + PORTINRSEL2 + desc PORTINRSEL2 + 9 + 9 + read-write + + + PORTINRSEL3 + desc PORTINRSEL3 + 10 + 10 + read-write + + + PORTINRSEL4 + desc PORTINRSEL4 + 11 + 11 + read-write + + + + + + + EMB5 + desc EMB + 0x40017CA0 + + 0x0 + 0x1C + + + + EMB6 + desc EMB + 0x40017CC0 + + 0x0 + 0x1C + + + + ETH + desc ETH + 0x40050000 + + 0x0 + 0x11058 + + + + MAC_IFCONFR + desc MAC_IFCONFR + 0x5410 + 32 + read-write + 0x0 + 0x31 + + + IFSEL + desc IFSEL + 0 + 0 + read-write + + + RCKINV + desc RCKINV + 4 + 4 + read-write + + + TCKINV + desc TCKINV + 5 + 5 + read-write + + + + + MAC_CONFIGR + desc MAC_CONFIGR + 0x10000 + 32 + read-write + 0x8000 + 0x72CF7EFC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + DC + desc DC + 4 + 4 + read-write + + + BL + desc BL + 6 + 5 + read-write + + + ACS + desc ACS + 7 + 7 + read-write + + + DRTY + desc DRTY + 9 + 9 + read-write + + + IPCO + desc IPCO + 10 + 10 + read-write + + + DM + desc DM + 11 + 11 + read-write + + + LM + desc LM + 12 + 12 + read-write + + + DO + desc DO + 13 + 13 + read-write + + + FES + desc FES + 14 + 14 + read-write + + + DCRS + desc DCRS + 16 + 16 + read-write + + + IFG + desc IFG + 19 + 17 + read-write + + + MJB + desc MJB + 22 + 22 + read-write + + + MWD + desc MWD + 23 + 23 + read-write + + + CST + desc CST + 25 + 25 + read-write + + + SAIRC + desc SAIRC + 30 + 28 + read-write + + + + + MAC_FLTCTLR + desc MAC_FLTCTLR + 0x10004 + 32 + read-write + 0x0 + 0x803107FF + + + PR + desc PR + 0 + 0 + read-write + + + HUC + desc HUC + 1 + 1 + read-write + + + HMC + desc HMC + 2 + 2 + read-write + + + DAIF + desc DAIF + 3 + 3 + read-write + + + PMF + desc PMF + 4 + 4 + read-write + + + DBF + desc DBF + 5 + 5 + read-write + + + PCF + desc PCF + 7 + 6 + read-write + + + SAIF + desc SAIF + 8 + 8 + read-write + + + SAF + desc SAF + 9 + 9 + read-write + + + HPF + desc HPF + 10 + 10 + read-write + + + VTFE + desc VTFE + 16 + 16 + read-write + + + IPFE + desc IPFE + 20 + 20 + read-write + + + DNTU + desc DNTU + 21 + 21 + read-write + + + RA + desc RA + 31 + 31 + read-write + + + + + MAC_HASHTHR + desc MAC_HASHTHR + 0x10008 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HTH + desc HTH + 31 + 0 + read-write + + + + + MAC_HASHTLR + desc MAC_HASHTLR + 0x1000C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HTL + desc HTL + 31 + 0 + read-write + + + + + MAC_SMIADDR + desc MAC_SMIADDR + 0x10010 + 32 + read-write + 0x0 + 0xFFFF + + + SMIB + desc SMIB + 0 + 0 + read-write + + + SMIW + desc SMIW + 1 + 1 + read-write + + + SMIC + desc SMIC + 5 + 2 + read-write + + + SMIR + desc SMIR + 10 + 6 + read-write + + + SMIA + desc SMIA + 15 + 11 + read-write + + + + + MAC_SMIDATR + desc MAC_SMIDATR + 0x10014 + 32 + read-write + 0x0 + 0xFFFF + + + SMID + desc SMID + 15 + 0 + read-write + + + + + MAC_FLOCTLR + desc MAC_FLOCTLR + 0x10018 + 32 + read-write + 0x0 + 0xFFFF00BF + + + FCA_BPA + desc FCA_BPA + 0 + 0 + read-write + + + TFE + desc TFE + 1 + 1 + read-write + + + RFE + desc RFE + 2 + 2 + read-write + + + UNP + desc UNP + 3 + 3 + read-write + + + PLT + desc PLT + 5 + 4 + read-write + + + DZPQ + desc DZPQ + 7 + 7 + read-write + + + PAUSET + desc PAUSET + 31 + 16 + read-write + + + + + MAC_VTAFLTR + desc MAC_VTAFLTR + 0x1001C + 32 + read-write + 0x0 + 0x10BFFFF + + + VLFLT + desc VLFLT + 15 + 0 + read-write + + + VTAL + desc VTAL + 16 + 16 + read-write + + + VTIM + desc VTIM + 17 + 17 + read-write + + + VTHM + desc VTHM + 19 + 19 + read-write + + + + + MAC_MACSTSR + desc MAC_MACSTSR + 0x10024 + 32 + read-only + 0x0 + 0x37F0377 + + + MREA + desc MREA + 0 + 0 + read-only + + + MRS + desc MRS + 2 + 1 + read-only + + + RFWA + desc RFWA + 4 + 4 + read-only + + + RFRS + desc RFRS + 6 + 5 + read-only + + + RFFL + desc RFFL + 9 + 8 + read-only + + + MTEA + desc MTEA + 16 + 16 + read-only + + + MTS + desc MTS + 18 + 17 + read-only + + + MTP + desc MTP + 19 + 19 + read-only + + + TFRS + desc TFRS + 21 + 20 + read-only + + + TFWA + desc TFWA + 22 + 22 + read-only + + + TFNE + desc TFNE + 24 + 24 + read-only + + + TFF + desc TFF + 25 + 25 + read-only + + + + + MAC_RTWKFFR + desc MAC_RTWKFFR + 0x10028 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WKUPFRMFT + desc WKUPFRMFT + 31 + 0 + read-write + + + + + MAC_PMTCTLR + desc MAC_PMTCTLR + 0x1002C + 32 + read-write + 0x0 + 0x87000667 + + + PWDN + desc PWDN + 0 + 0 + read-write + + + MPEN + desc MPEN + 1 + 1 + read-write + + + WKEN + desc WKEN + 2 + 2 + read-write + + + MPFR + desc MPFR + 5 + 5 + read-only + + + WKFR + desc WKFR + 6 + 6 + read-only + + + GLUB + desc GLUB + 9 + 9 + read-write + + + RTWKTR + desc RTWKTR + 10 + 10 + read-write + + + RTWKPT + desc RTWKPT + 26 + 24 + read-only + + + RTWKFR + desc RTWKFR + 31 + 31 + read-write + + + + + MAC_INTSTSR + desc MAC_INTSTSR + 0x10038 + 32 + read-only + 0x0 + 0x278 + + + PMTIS + desc PMTIS + 3 + 3 + read-only + + + MMCIS + desc MMCIS + 4 + 4 + read-only + + + MMCRXIS + desc MMCRXIS + 5 + 5 + read-only + + + MMCTXIS + desc MMCTXIS + 6 + 6 + read-only + + + TSPIS + desc TSPIS + 9 + 9 + read-only + + + + + MAC_INTMSKR + desc MAC_INTMSKR + 0x1003C + 32 + read-write + 0x0 + 0x208 + + + PMTIM + desc PMTIM + 3 + 3 + read-write + + + TSPIM + desc TSPIM + 9 + 9 + read-write + + + + + MAC_MACADHR0 + desc MAC_MACADHR0 + 0x10040 + 32 + read-write + 0x8000FFFF + 0x8000FFFF + + + ADDRH0 + desc ADDRH0 + 15 + 0 + read-write + + + AE0 + desc AE0 + 31 + 31 + read-only + + + + + MAC_MACADLR0 + desc MAC_MACADLR0 + 0x10044 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL0 + desc ADDRL0 + 31 + 0 + read-write + + + + + MAC_MACADHR1 + desc MAC_MACADHR1 + 0x10048 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH1 + desc ADDRH1 + 15 + 0 + read-write + + + MBC1 + desc MBC1 + 29 + 24 + read-write + + + SA1 + desc SA1 + 30 + 30 + read-write + + + AE1 + desc AE1 + 31 + 31 + read-write + + + + + MAC_MACADLR1 + desc MAC_MACADLR1 + 0x1004C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL1 + desc ADDRL1 + 31 + 0 + read-write + + + + + MAC_MACADHR2 + desc MAC_MACADHR2 + 0x10050 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH2 + desc ADDRH2 + 15 + 0 + read-write + + + MBC2 + desc MBC2 + 29 + 24 + read-write + + + SA2 + desc SA2 + 30 + 30 + read-write + + + AE2 + desc AE2 + 31 + 31 + read-write + + + + + MAC_MACADLR2 + desc MAC_MACADLR2 + 0x10054 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL2 + desc ADDRL2 + 31 + 0 + read-write + + + + + MAC_MACADHR3 + desc MAC_MACADHR3 + 0x10058 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH3 + desc ADDRH3 + 15 + 0 + read-write + + + MBC3 + desc MBC3 + 29 + 24 + read-write + + + SA3 + desc SA3 + 30 + 30 + read-write + + + AE3 + desc AE3 + 31 + 31 + read-write + + + + + MAC_MACADLR3 + desc MAC_MACADLR3 + 0x1005C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL3 + desc ADDRL3 + 31 + 0 + read-write + + + + + MAC_MACADHR4 + desc MAC_MACADHR4 + 0x10060 + 32 + read-write + 0xFFFF + 0xFF00FFFF + + + ADDRH4 + desc ADDRH4 + 15 + 0 + read-write + + + MBC4 + desc MBC4 + 29 + 24 + read-write + + + SA4 + desc SA4 + 30 + 30 + read-write + + + AE4 + desc AE4 + 31 + 31 + read-write + + + + + MAC_MACADLR4 + desc MAC_MACADLR4 + 0x10064 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRL4 + desc ADDRL4 + 31 + 0 + read-write + + + + + MMC_MMCCTLR + desc MMC_MMCCTLR + 0x10100 + 32 + read-write + 0x0 + 0x3F + + + CRST + desc CRST + 0 + 0 + read-write + + + COS + desc COS + 1 + 1 + read-write + + + ROR + desc ROR + 2 + 2 + read-write + + + MCF + desc MCF + 3 + 3 + read-write + + + MCPSET + desc MCPSET + 4 + 4 + read-write + + + MCPSEL + desc MCPSEL + 5 + 5 + read-write + + + + + MMC_REVSTSR + desc MMC_REVSTSR + 0x10104 + 32 + read-only + 0x0 + 0x10E00F8 + + + RXBGIS + desc RXBGIS + 3 + 3 + read-only + + + RXMGIS + desc RXMGIS + 4 + 4 + read-only + + + RXCEIS + desc RXCEIS + 5 + 5 + read-only + + + RXAEIS + desc RXAEIS + 6 + 6 + read-only + + + RXREIS + desc RXREIS + 7 + 7 + read-only + + + RXUGIS + desc RXUGIS + 17 + 17 + read-only + + + RXLEIS + desc RXLEIS + 18 + 18 + read-only + + + RXOEIS + desc RXOEIS + 19 + 19 + read-only + + + + + MMC_TRSSTSR + desc MMC_TRSSTSR + 0x10108 + 32 + read-only + 0x0 + 0x16F000C + + + TXBGIS + desc TXBGIS + 2 + 2 + read-only + + + TXMGIS + desc TXMGIS + 3 + 3 + read-only + + + TXDEEIS + desc TXDEEIS + 16 + 16 + read-only + + + TXLCEIS + desc TXLCEIS + 17 + 17 + read-only + + + TXECEIS + desc TXECEIS + 18 + 18 + read-only + + + TXCAEIS + desc TXCAEIS + 19 + 19 + read-only + + + TXUGIS + desc TXUGIS + 21 + 21 + read-only + + + TXEDEIS + desc TXEDEIS + 22 + 22 + read-only + + + + + MMC_RITCTLR + desc MMC_RITCTLR + 0x1010C + 32 + read-write + 0x0 + 0x10E00F8 + + + RXBGIM + desc RXBGIM + 3 + 3 + read-write + + + RXMGIM + desc RXMGIM + 4 + 4 + read-write + + + RXCEIM + desc RXCEIM + 5 + 5 + read-write + + + RXAEIM + desc RXAEIM + 6 + 6 + read-write + + + RXREIM + desc RXREIM + 7 + 7 + read-write + + + RXUGIM + desc RXUGIM + 17 + 17 + read-write + + + RXLEIM + desc RXLEIM + 18 + 18 + read-write + + + RXOEIM + desc RXOEIM + 19 + 19 + read-write + + + + + MMC_TITCTLR + desc MMC_TITCTLR + 0x10110 + 32 + read-write + 0x0 + 0x16F000C + + + TXBGIM + desc TXBGIM + 2 + 2 + read-write + + + TXMGIM + desc TXMGIM + 3 + 3 + read-write + + + TXDEEIM + desc TXDEEIM + 16 + 16 + read-write + + + TXLCEIM + desc TXLCEIM + 17 + 17 + read-write + + + TXECEIM + desc TXECEIM + 18 + 18 + read-write + + + TXCAEIM + desc TXCAEIM + 19 + 19 + read-write + + + TXUGIM + desc TXUGIM + 21 + 21 + read-write + + + TXEDEIM + desc TXEDEIM + 22 + 22 + read-write + + + + + MMC_TXBRGFR + desc MMC_TXBRGFR + 0x1011C + 32 + read-only + 0x0 + 0xFFFF + + + TXBRGCNT + desc TXBRGCNT + 15 + 0 + read-only + + + + + MMC_TXMUGFR + desc MMC_TXMUGFR + 0x10120 + 32 + read-only + 0x0 + 0xFFFF + + + TXMUGCNT + desc TXMUGCNT + 15 + 0 + read-only + + + + + MMC_TXDEEFR + desc MMC_TXDEEFR + 0x10154 + 32 + read-only + 0x0 + 0xFFFF + + + TXDEECNT + desc TXDEECNT + 15 + 0 + read-only + + + + + MMC_TXLCEFR + desc MMC_TXLCEFR + 0x10158 + 32 + read-only + 0x0 + 0xFFFF + + + TXLCECNT + desc TXLCECNT + 15 + 0 + read-only + + + + + MMC_TXECEFR + desc MMC_TXECEFR + 0x1015C + 32 + read-only + 0x0 + 0xFFFF + + + TXECECNT + desc TXECECNT + 15 + 0 + read-only + + + + + MMC_TXCAEFR + desc MMC_TXCAEFR + 0x10160 + 32 + read-only + 0x0 + 0xFFFF + + + TXCAECNT + desc TXCAECNT + 15 + 0 + read-only + + + + + MMC_TXUNGFR + desc MMC_TXUNGFR + 0x10168 + 32 + read-only + 0x0 + 0xFFFF + + + TXUNGCNT + desc TXUNGCNT + 15 + 0 + read-only + + + + + MMC_TXEDEFR + desc MMC_TXEDEFR + 0x1016C + 32 + read-only + 0x0 + 0xFFFF + + + TXEDECNT + desc TXEDECNT + 15 + 0 + read-only + + + + + MMC_RXBRGFR + desc MMC_RXBRGFR + 0x1018C + 32 + read-only + 0x0 + 0xFFFF + + + RXBRGCNT + desc RXBRGCNT + 15 + 0 + read-only + + + + + MMC_RXMUGFR + desc MMC_RXMUGFR + 0x10190 + 32 + read-only + 0x0 + 0xFFFF + + + RXMUGCNT + desc RXMUGCNT + 15 + 0 + read-only + + + + + MMC_RXCREFR + desc MMC_RXCREFR + 0x10194 + 32 + read-only + 0x0 + 0xFFFF + + + RXCRECNT + desc RXCRECNT + 15 + 0 + read-only + + + + + MMC_RXALEFR + desc MMC_RXALEFR + 0x10198 + 32 + read-only + 0x0 + 0xFFFF + + + RXALECNT + desc RXALECNT + 15 + 0 + read-only + + + + + MMC_RXRUEFR + desc MMC_RXRUEFR + 0x1019C + 32 + read-only + 0x0 + 0xFFFF + + + RXRUECNT + desc RXRUECNT + 15 + 0 + read-only + + + + + MMC_RXUNGFR + desc MMC_RXUNGFR + 0x101C4 + 32 + read-only + 0x0 + 0xFFFF + + + RXUNGCNT + desc RXUNGCNT + 15 + 0 + read-only + + + + + MMC_RXLEEFR + desc MMC_RXLEEFR + 0x101C8 + 32 + read-only + 0x0 + 0xFFFF + + + RXLEECNT + desc RXLEECNT + 15 + 0 + read-only + + + + + MMC_RXOREFR + desc MMC_RXOREFR + 0x101CC + 32 + read-only + 0x0 + 0xFFFF + + + RXORECNT + desc RXORECNT + 15 + 0 + read-only + + + + + MAC_L34CTLR + desc MAC_L34CTLR + 0x10400 + 32 + read-write + 0x0 + 0x13DFFFD + + + L3PEN + desc L3PEN + 0 + 0 + read-write + + + L3SAM + desc L3SAM + 2 + 2 + read-write + + + L3SAIM + desc L3SAIM + 3 + 3 + read-write + + + L3DAM + desc L3DAM + 4 + 4 + read-write + + + L3DAIM + desc L3DAIM + 5 + 5 + read-write + + + L3HSBM + desc L3HSBM + 10 + 6 + read-write + + + L3HDBM + desc L3HDBM + 15 + 11 + read-write + + + L4PEN + desc L4PEN + 16 + 16 + read-write + + + L4SPM + desc L4SPM + 18 + 18 + read-write + + + L4SPIM + desc L4SPIM + 19 + 19 + read-write + + + L4DPM + desc L4DPM + 20 + 20 + read-write + + + L4DPIM + desc L4DPIM + 21 + 21 + read-write + + + + + MAC_L4PORTR + desc MAC_L4PORTR + 0x10404 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L4SPVAL + desc L4SPVAL + 15 + 0 + read-write + + + L4DPVAL + desc L4DPVAL + 31 + 16 + read-write + + + + + MAC_L3ADDRR0 + desc MAC_L3ADDRR0 + 0x10410 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR0 + desc L3ADDR0 + 31 + 0 + read-write + + + + + MAC_L3ADDRR1 + desc MAC_L3ADDRR1 + 0x10414 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR2 + desc L3ADDR2 + 31 + 0 + read-write + + + + + MAC_L3ADDRR2 + desc MAC_L3ADDRR2 + 0x10418 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR2 + desc L3ADDR2 + 31 + 0 + read-write + + + + + MAC_L3ADDRR3 + desc MAC_L3ADDRR3 + 0x1041C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + L3ADDR3 + desc L3ADDR3 + 31 + 0 + read-write + + + + + MAC_VTACTLR + desc MAC_VTACTLR + 0x10584 + 32 + read-write + 0x0 + 0x107FFFF + + + VLANV + desc VLANV + 15 + 0 + read-write + + + VLANC + desc VLANC + 17 + 16 + read-write + + + VLANS + desc VLANS + 18 + 18 + read-write + + + + + MAC_VLAHTBR + desc MAC_VLAHTBR + 0x10588 + 32 + read-write + 0x0 + 0xFFFF + + + VLHT + desc VLHT + 15 + 0 + read-write + + + + + PTP_TSPCTLR + desc PTP_TSPCTLR + 0x10700 + 32 + read-write + 0x2000 + 0x107FF3F + + + TSPEN + desc TSPEN + 0 + 0 + read-write + + + TSPUPSEL + desc TSPUPSEL + 1 + 1 + read-write + + + TSPINI + desc TSPINI + 2 + 2 + read-write + + + TSPUP + desc TSPUP + 3 + 3 + read-write + + + TSPINT + desc TSPINT + 4 + 4 + read-write + + + TSPADUP + desc TSPADUP + 5 + 5 + read-write + + + TSPEALL + desc TSPEALL + 8 + 8 + read-write + + + TSPSSR + desc TSPSSR + 9 + 9 + read-write + + + TSPVER + desc TSPVER + 10 + 10 + read-write + + + TSPOVETH + desc TSPOVETH + 11 + 11 + read-write + + + TSPOVIPV6 + desc TSPOVIPV6 + 12 + 12 + read-write + + + TSPOVIPV4 + desc TSPOVIPV4 + 13 + 13 + read-write + + + TSPMTSEL + desc TSPMTSEL + 17 + 14 + read-write + + + TSPADF + desc TSPADF + 18 + 18 + read-write + + + + + PTP_TSPNSAR + desc PTP_TSPNSAR + 0x10704 + 32 + read-write + 0x0 + 0xFF + + + TSPNSEADD + desc TSPNSEADD + 7 + 0 + read-write + + + + + PTP_TMSSECR + desc PTP_TMSSECR + 0x10708 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TSPSYSSEC + desc TSPSYSSEC + 31 + 0 + read-only + + + + + PTP_TMSNSER + desc PTP_TMSNSER + 0x1070C + 32 + read-only + 0x0 + 0x7FFFFFFF + + + TSPSYSNSEC + desc TSPSYSNSEC + 30 + 0 + read-only + + + + + PTP_TMUSECR + desc PTP_TMUSECR + 0x10710 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPUPSEC + desc TSPUPSEC + 31 + 0 + read-write + + + + + PTP_TMUNSER + desc PTP_TMUNSER + 0x10714 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPUPNSEC + desc TSPUPNSEC + 30 + 0 + read-write + + + TSPUPNS + desc TSPUPNS + 31 + 31 + read-write + + + + + PTP_TSPADDR + desc PTP_TSPADDR + 0x10718 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPADD + desc TSPADD + 31 + 0 + read-write + + + + + PTP_TMTSECR0 + desc PTP_TMTSECR0 + 0x1071C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPTAGSEC0 + desc TSPTAGSEC0 + 31 + 0 + read-write + + + + + PTP_TMTNSER0 + desc PTP_TMTNSER0 + 0x10720 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + TSPTAGNSEC0 + desc TSPTAGNSEC0 + 30 + 0 + read-write + + + + + PTP_TSPSTSR + desc PTP_TSPSTSR + 0x10728 + 32 + read-only + 0x0 + 0x3B + + + TSOVF + desc TSOVF + 0 + 0 + read-only + + + TSTAR0 + desc TSTAR0 + 1 + 1 + read-only + + + TSERR0 + desc TSERR0 + 3 + 3 + read-only + + + TSTAR1 + desc TSTAR1 + 4 + 4 + read-only + + + TSERR1 + desc TSERR1 + 5 + 5 + read-only + + + + + PTP_PPSCTLR + desc PTP_PPSCTLR + 0x1072C + 32 + read-write + 0x0 + 0x677F + + + PPSFRE0 + desc PPSFRE0 + 3 + 0 + read-write + + + PPSOMD + desc PPSOMD + 4 + 4 + read-write + + + TT0SEL + desc TT0SEL + 6 + 5 + read-write + + + PPSFRE1 + desc PPSFRE1 + 10 + 8 + read-write + + + TT1SEL + desc TT1SEL + 14 + 13 + read-write + + + + + PTP_TMTSECR1 + desc PTP_TMTSECR1 + 0x10780 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPTAGSEC1 + desc TSPTAGSEC1 + 31 + 0 + read-write + + + + + PTP_TMTNSER1 + desc PTP_TMTNSER1 + 0x10784 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + TSPTAGNSEC1 + desc TSPTAGNSEC1 + 30 + 0 + read-write + + + + + DMA_BUSMODR + desc DMA_BUSMODR + 0x11000 + 32 + read-write + 0x20101 + 0xFFFFFFF + + + SWR + desc SWR + 0 + 0 + read-write + + + DMAA + desc DMAA + 1 + 1 + read-write + + + DSL + desc DSL + 6 + 2 + read-write + + + DSEN + desc DSEN + 7 + 7 + read-write + + + TPBL + desc TPBL + 13 + 8 + read-write + + + PRAT + desc PRAT + 15 + 14 + read-write + + + FBST + desc FBST + 16 + 16 + read-write + + + RPBL + desc RPBL + 22 + 17 + read-write + + + SPBL + desc SPBL + 23 + 23 + read-write + + + M8PBL + desc M8PBL + 24 + 24 + read-write + + + AAL + desc AAL + 25 + 25 + read-write + + + MBST + desc MBST + 26 + 26 + read-write + + + TXPR + desc TXPR + 27 + 27 + read-write + + + + + DMA_TXPOLLR + desc DMA_TXPOLLR + 0x11004 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TXPOLL + desc TXPOLL + 31 + 0 + read-write + + + + + DMA_RXPOLLR + desc DMA_RXPOLLR + 0x11008 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RXPOLL + desc RXPOLL + 31 + 0 + read-write + + + + + DMA_RXDLADR + desc DMA_RXDLADR + 0x1100C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RXDLAD + desc RXDLAD + 31 + 0 + read-write + + + + + DMA_TXDLADR + desc DMA_TXDLADR + 0x11010 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TXDLAD + desc TXDLAD + 31 + 0 + read-write + + + + + DMA_DMASTSR + desc DMA_DMASTSR + 0x11014 + 32 + read-write + 0x0 + 0x3BFFE7FF + + + TIS + desc TIS + 0 + 0 + read-write + + + TSS + desc TSS + 1 + 1 + read-write + + + TUS + desc TUS + 2 + 2 + read-write + + + TJS + desc TJS + 3 + 3 + read-write + + + OVS + desc OVS + 4 + 4 + read-write + + + UNS + desc UNS + 5 + 5 + read-write + + + RIS + desc RIS + 6 + 6 + read-write + + + RUS + desc RUS + 7 + 7 + read-write + + + RSS + desc RSS + 8 + 8 + read-write + + + RWS + desc RWS + 9 + 9 + read-write + + + ETS + desc ETS + 10 + 10 + read-write + + + FBS + desc FBS + 13 + 13 + read-write + + + ERS + desc ERS + 14 + 14 + read-write + + + AIS + desc AIS + 15 + 15 + read-write + + + NIS + desc NIS + 16 + 16 + read-write + + + RSTS + desc RSTS + 19 + 17 + read-only + + + TSTS + desc TSTS + 22 + 20 + read-only + + + EBUS + desc EBUS + 25 + 23 + read-only + + + MMCS + desc MMCS + 27 + 27 + read-only + + + PMTS + desc PMTS + 28 + 28 + read-only + + + PTPS + desc PTPS + 29 + 29 + read-only + + + + + DMA_OPRMODR + desc DMA_OPRMODR + 0x11018 + 32 + read-write + 0x0 + 0x731E0FE + + + STR + desc STR + 1 + 1 + read-write + + + OSF + desc OSF + 2 + 2 + read-write + + + RTC + desc RTC + 4 + 3 + read-write + + + DGF + desc DGF + 5 + 5 + read-write + + + FUF + desc FUF + 6 + 6 + read-write + + + FEF + desc FEF + 7 + 7 + read-write + + + STT + desc STT + 13 + 13 + read-write + + + TTC + desc TTC + 16 + 14 + read-write + + + FTF + desc FTF + 20 + 20 + read-write + + + TSF + desc TSF + 21 + 21 + read-write + + + DFRF + desc DFRF + 24 + 24 + read-write + + + RSF + desc RSF + 25 + 25 + read-write + + + DTCOE + desc DTCOE + 26 + 26 + read-write + + + + + DMA_INTENAR + desc DMA_INTENAR + 0x1101C + 32 + read-write + 0x0 + 0x101E7FF + + + TIE + desc TIE + 0 + 0 + read-write + + + TSE + desc TSE + 1 + 1 + read-write + + + TUE + desc TUE + 2 + 2 + read-write + + + TJE + desc TJE + 3 + 3 + read-write + + + OVE + desc OVE + 4 + 4 + read-write + + + UNE + desc UNE + 5 + 5 + read-write + + + RIE + desc RIE + 6 + 6 + read-write + + + RUE + desc RUE + 7 + 7 + read-write + + + RSE + desc RSE + 8 + 8 + read-write + + + RWE + desc RWE + 9 + 9 + read-write + + + ETE + desc ETE + 10 + 10 + read-write + + + FBE + desc FBE + 13 + 13 + read-write + + + ERE + desc ERE + 14 + 14 + read-write + + + AIE + desc AIE + 15 + 15 + read-write + + + NIE + desc NIE + 16 + 16 + read-write + + + + + DMA_RFRCNTR + desc DMA_RFRCNTR + 0x11020 + 32 + read-only + 0x0 + 0x1FFFFFFF + + + UNACNT + desc UNACNT + 15 + 0 + read-only + + + UNAOVF + desc UNAOVF + 16 + 16 + read-only + + + OVFCNT + desc OVFCNT + 27 + 17 + read-only + + + OVFOVF + desc OVFOVF + 28 + 28 + read-only + + + + + DMA_REVWDTR + desc DMA_REVWDTR + 0x11024 + 32 + read-write + 0x0 + 0xFF + + + RIWT + desc RIWT + 7 + 0 + read-write + + + + + DMA_CHTXDER + desc DMA_CHTXDER + 0x11048 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHTXDE + desc CHTXDE + 31 + 0 + read-only + + + + + DMA_CHRXDER + desc DMA_CHRXDER + 0x1104C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHRXDE + desc CHRXDE + 31 + 0 + read-only + + + + + DMA_CHTXBFR + desc DMA_CHTXBFR + 0x11050 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHTXBF + desc CHTXBF + 31 + 0 + read-only + + + + + DMA_CHRXBFR + desc DMA_CHRXBFR + 0x11054 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CHRXBF + desc CHRXBF + 31 + 0 + read-only + + + + + + + FCM + desc FCM + 0x40048400 + + 0x0 + 0x24 + + + + LVR + desc LVR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + LVR + desc LVR + 15 + 0 + read-write + + + + + UVR + desc UVR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + UVR + desc UVR + 15 + 0 + read-write + + + + + CNTR + desc CNTR + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + CNTR + desc CNTR + 15 + 0 + read-only + + + + + STR + desc STR + 0xC + 32 + read-write + 0x0 + 0x1 + + + START + desc START + 0 + 0 + read-write + + + + + MCCR + desc MCCR + 0x10 + 32 + read-write + 0x0 + 0xF3 + + + MDIVS + desc MDIVS + 1 + 0 + read-write + + + MCKS + desc MCKS + 7 + 4 + read-write + + + + + RCCR + desc RCCR + 0x14 + 32 + read-write + 0x0 + 0xB3FB + + + RDIVS + desc RDIVS + 1 + 0 + read-write + + + RCKS + desc RCKS + 6 + 3 + read-write + + + INEXS + desc INEXS + 7 + 7 + read-write + + + DNFS + desc DNFS + 9 + 8 + read-write + + + EDGES + desc EDGES + 13 + 12 + read-write + + + EXREFE + desc EXREFE + 15 + 15 + read-write + + + + + RIER + desc RIER + 0x18 + 32 + read-write + 0x0 + 0x97 + + + ERRIE + desc ERRIE + 0 + 0 + read-write + + + MENDIE + desc MENDIE + 1 + 1 + read-write + + + OVFIE + desc OVFIE + 2 + 2 + read-write + + + ERRINTRS + desc ERRINTRS + 4 + 4 + read-write + + + ERRE + desc ERRE + 7 + 7 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-only + 0x0 + 0x7 + + + ERRF + desc ERRF + 0 + 0 + read-only + + + MENDF + desc MENDF + 1 + 1 + read-only + + + OVF + desc OVF + 2 + 2 + read-only + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0x7 + + + ERRFCLR + desc ERRFCLR + 0 + 0 + write-only + + + MENDFCLR + desc MENDFCLR + 1 + 1 + write-only + + + OVFCLR + desc OVFCLR + 2 + 2 + write-only + + + + + + + FMAC1 + desc FMAC + 0x40058000 + + 0x0 + 0x64 + + + + ENR + desc ENR + 0x0 + 32 + read-write + 0x0 + 0x1 + + + FMACEN + desc FMACEN + 0 + 0 + read-write + + + + + CTR + desc CTR + 0x4 + 32 + read-write + 0x10 + 0x1F1F + + + STAGE_NUM + desc STAGE_NUM + 4 + 0 + read-write + + + SHIFT + desc SHIFT + 12 + 8 + read-write + + + + + IER + desc IER + 0x8 + 32 + read-write + 0x0 + 0x1 + + + INTEN + desc INTEN + 0 + 0 + read-write + + + + + DTR + desc DTR + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + DIN + desc DIN + 15 + 0 + read-write + + + + + RTR0 + desc RTR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RTR1 + desc RTR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + STR + desc STR + 0x18 + 32 + read-write + 0x0 + 0x80000000 + + + READY + desc READY + 31 + 31 + read-write + + + + + COR0 + desc COR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR1 + desc COR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR2 + desc COR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR3 + desc COR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR4 + desc COR4 + 0x30 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR5 + desc COR5 + 0x34 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR6 + desc COR6 + 0x38 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR7 + desc COR7 + 0x3C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR8 + desc COR8 + 0x40 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR9 + desc COR9 + 0x44 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR10 + desc COR10 + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR11 + desc COR11 + 0x4C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR12 + desc COR12 + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR13 + desc COR13 + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR14 + desc COR14 + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR15 + desc COR15 + 0x5C + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + COR16 + desc COR16 + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + CIN + desc CIN + 15 + 0 + read-write + + + + + + + FMAC2 + desc FMAC + 0x40058400 + + 0x0 + 0x64 + + + + FMAC3 + desc FMAC + 0x40058800 + + 0x0 + 0x64 + + + + FMAC4 + desc FMAC + 0x40058C00 + + 0x0 + 0x64 + + + + GPIO + desc GPIO + 0x40053800 + + 0x0 + 0x638 + + + + PIDRA + desc PIDRA + 0x0 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRA + desc PODRA + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERA + desc POERA + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRA + desc POSRA + 0x8 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRA + desc PORRA + 0xA + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRA + desc POTRA + 0xC + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRB + desc PIDRB + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRB + desc PODRB + 0x14 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERB + desc POERB + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRB + desc POSRB + 0x18 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRB + desc PORRB + 0x1A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRB + desc POTRB + 0x1C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRC + desc PIDRC + 0x20 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRC + desc PODRC + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERC + desc POERC + 0x26 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRC + desc POSRC + 0x28 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRC + desc PORRC + 0x2A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRC + desc POTRC + 0x2C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRD + desc PIDRD + 0x30 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRD + desc PODRD + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERD + desc POERD + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRD + desc POSRD + 0x38 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRD + desc PORRD + 0x3A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRD + desc POTRD + 0x3C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRE + desc PIDRE + 0x40 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRE + desc PODRE + 0x44 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERE + desc POERE + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRE + desc POSRE + 0x48 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRE + desc PORRE + 0x4A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRE + desc POTRE + 0x4C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRF + desc PIDRF + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRF + desc PODRF + 0x54 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERF + desc POERF + 0x56 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRF + desc POSRF + 0x58 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRF + desc PORRF + 0x5A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRF + desc POTRF + 0x5C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRG + desc PIDRG + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRG + desc PODRG + 0x64 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERG + desc POERG + 0x66 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRG + desc POSRG + 0x68 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRG + desc PORRG + 0x6A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRG + desc POTRG + 0x6C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRH + desc PIDRH + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRH + desc PODRH + 0x74 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERH + desc POERH + 0x76 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRH + desc POSRH + 0x78 + 16 + write-only + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + POS14 + desc POS14 + 14 + 14 + write-only + + + POS15 + desc POS15 + 15 + 15 + write-only + + + + + PORRH + desc PORRH + 0x7A + 16 + write-only + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + POR14 + desc POR14 + 14 + 14 + write-only + + + POR15 + desc POR15 + 15 + 15 + write-only + + + + + POTRH + desc POTRH + 0x7C + 16 + write-only + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + POT14 + desc POT14 + 14 + 14 + write-only + + + POT15 + desc POT15 + 15 + 15 + write-only + + + + + PIDRI + desc PIDRI + 0x80 + 16 + read-only + 0x0 + 0x3FFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + + + PODRI + desc PODRI + 0x84 + 16 + read-write + 0x0 + 0x3FFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + + + POERI + desc POERI + 0x86 + 16 + read-write + 0x0 + 0x3FFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + + + POSRI + desc POSRI + 0x88 + 16 + write-only + 0x0 + 0x3FFF + + + POS00 + desc POS00 + 0 + 0 + write-only + + + POS01 + desc POS01 + 1 + 1 + write-only + + + POS02 + desc POS02 + 2 + 2 + write-only + + + POS03 + desc POS03 + 3 + 3 + write-only + + + POS04 + desc POS04 + 4 + 4 + write-only + + + POS05 + desc POS05 + 5 + 5 + write-only + + + POS06 + desc POS06 + 6 + 6 + write-only + + + POS07 + desc POS07 + 7 + 7 + write-only + + + POS08 + desc POS08 + 8 + 8 + write-only + + + POS09 + desc POS09 + 9 + 9 + write-only + + + POS10 + desc POS10 + 10 + 10 + write-only + + + POS11 + desc POS11 + 11 + 11 + write-only + + + POS12 + desc POS12 + 12 + 12 + write-only + + + POS13 + desc POS13 + 13 + 13 + write-only + + + + + PORRI + desc PORRI + 0x8A + 16 + write-only + 0x0 + 0x3FFF + + + POR00 + desc POR00 + 0 + 0 + write-only + + + POR01 + desc POR01 + 1 + 1 + write-only + + + POR02 + desc POR02 + 2 + 2 + write-only + + + POR03 + desc POR03 + 3 + 3 + write-only + + + POR04 + desc POR04 + 4 + 4 + write-only + + + POR05 + desc POR05 + 5 + 5 + write-only + + + POR06 + desc POR06 + 6 + 6 + write-only + + + POR07 + desc POR07 + 7 + 7 + write-only + + + POR08 + desc POR08 + 8 + 8 + write-only + + + POR09 + desc POR09 + 9 + 9 + write-only + + + POR10 + desc POR10 + 10 + 10 + write-only + + + POR11 + desc POR11 + 11 + 11 + write-only + + + POR12 + desc POR12 + 12 + 12 + write-only + + + POR13 + desc POR13 + 13 + 13 + write-only + + + + + POTRI + desc POTRI + 0x8C + 16 + write-only + 0x0 + 0x3FFF + + + POT00 + desc POT00 + 0 + 0 + write-only + + + POT01 + desc POT01 + 1 + 1 + write-only + + + POT02 + desc POT02 + 2 + 2 + write-only + + + POT03 + desc POT03 + 3 + 3 + write-only + + + POT04 + desc POT04 + 4 + 4 + write-only + + + POT05 + desc POT05 + 5 + 5 + write-only + + + POT06 + desc POT06 + 6 + 6 + write-only + + + POT07 + desc POT07 + 7 + 7 + write-only + + + POT08 + desc POT08 + 8 + 8 + write-only + + + POT09 + desc POT09 + 9 + 9 + write-only + + + POT10 + desc POT10 + 10 + 10 + write-only + + + POT11 + desc POT11 + 11 + 11 + write-only + + + POT12 + desc POT12 + 12 + 12 + write-only + + + POT13 + desc POT13 + 13 + 13 + write-only + + + + + PSPCR + desc PSPCR + 0x3F4 + 16 + read-write + 0x1F + 0x1F + + + SPFE + desc SPFE + 4 + 0 + read-write + + + + + PCCR + desc PCCR + 0x3F8 + 16 + read-write + 0x1000 + 0x703F + + + BFSEL + desc BFSEL + 5 + 0 + read-write + + + RDWT + desc RDWT + 14 + 12 + read-write + + + + + PINAER + desc PINAER + 0x3FA + 16 + read-write + 0x0 + 0x1FF + + + PINAE + desc PINAE + 8 + 0 + read-write + + + + + PWPR + desc PWPR + 0x3FC + 16 + read-write + 0x0 + 0xFF01 + + + WE + desc WE + 0 + 0 + read-write + + + WP + desc WP + 15 + 8 + write-only + + + + + PCRA0 + desc PCRA0 + 0x400 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA0 + desc PFSRA0 + 0x402 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA1 + desc PCRA1 + 0x404 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA1 + desc PFSRA1 + 0x406 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA2 + desc PCRA2 + 0x408 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA2 + desc PFSRA2 + 0x40A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA3 + desc PCRA3 + 0x40C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA3 + desc PFSRA3 + 0x40E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA4 + desc PCRA4 + 0x410 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA4 + desc PFSRA4 + 0x412 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA5 + desc PCRA5 + 0x414 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA5 + desc PFSRA5 + 0x416 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA6 + desc PCRA6 + 0x418 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA6 + desc PFSRA6 + 0x41A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA7 + desc PCRA7 + 0x41C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA7 + desc PFSRA7 + 0x41E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA8 + desc PCRA8 + 0x420 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA8 + desc PFSRA8 + 0x422 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA9 + desc PCRA9 + 0x424 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA9 + desc PFSRA9 + 0x426 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA10 + desc PCRA10 + 0x428 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA10 + desc PFSRA10 + 0x42A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA11 + desc PCRA11 + 0x42C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA11 + desc PFSRA11 + 0x42E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA12 + desc PCRA12 + 0x430 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA12 + desc PFSRA12 + 0x432 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA13 + desc PCRA13 + 0x434 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA13 + desc PFSRA13 + 0x436 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA14 + desc PCRA14 + 0x438 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA14 + desc PFSRA14 + 0x43A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA15 + desc PCRA15 + 0x43C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA15 + desc PFSRA15 + 0x43E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB0 + desc PCRB0 + 0x440 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB0 + desc PFSRB0 + 0x442 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB1 + desc PCRB1 + 0x444 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB1 + desc PFSRB1 + 0x446 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB2 + desc PCRB2 + 0x448 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB2 + desc PFSRB2 + 0x44A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB3 + desc PCRB3 + 0x44C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB3 + desc PFSRB3 + 0x44E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB4 + desc PCRB4 + 0x450 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB4 + desc PFSRB4 + 0x452 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB5 + desc PCRB5 + 0x454 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB5 + desc PFSRB5 + 0x456 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB6 + desc PCRB6 + 0x458 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB6 + desc PFSRB6 + 0x45A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB7 + desc PCRB7 + 0x45C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB7 + desc PFSRB7 + 0x45E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB8 + desc PCRB8 + 0x460 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB8 + desc PFSRB8 + 0x462 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB9 + desc PCRB9 + 0x464 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB9 + desc PFSRB9 + 0x466 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB10 + desc PCRB10 + 0x468 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB10 + desc PFSRB10 + 0x46A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB11 + desc PCRB11 + 0x46C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB11 + desc PFSRB11 + 0x46E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB12 + desc PCRB12 + 0x470 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB12 + desc PFSRB12 + 0x472 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB13 + desc PCRB13 + 0x474 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB13 + desc PFSRB13 + 0x476 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB14 + desc PCRB14 + 0x478 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB14 + desc PFSRB14 + 0x47A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB15 + desc PCRB15 + 0x47C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB15 + desc PFSRB15 + 0x47E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC0 + desc PCRC0 + 0x480 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC0 + desc PFSRC0 + 0x482 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC1 + desc PCRC1 + 0x484 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC1 + desc PFSRC1 + 0x486 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC2 + desc PCRC2 + 0x488 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC2 + desc PFSRC2 + 0x48A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC3 + desc PCRC3 + 0x48C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC3 + desc PFSRC3 + 0x48E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC4 + desc PCRC4 + 0x490 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC4 + desc PFSRC4 + 0x492 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC5 + desc PCRC5 + 0x494 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC5 + desc PFSRC5 + 0x496 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC6 + desc PCRC6 + 0x498 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC6 + desc PFSRC6 + 0x49A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC7 + desc PCRC7 + 0x49C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC7 + desc PFSRC7 + 0x49E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC8 + desc PCRC8 + 0x4A0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC8 + desc PFSRC8 + 0x4A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC9 + desc PCRC9 + 0x4A4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC9 + desc PFSRC9 + 0x4A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC10 + desc PCRC10 + 0x4A8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC10 + desc PFSRC10 + 0x4AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC11 + desc PCRC11 + 0x4AC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC11 + desc PFSRC11 + 0x4AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC12 + desc PCRC12 + 0x4B0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC12 + desc PFSRC12 + 0x4B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC13 + desc PCRC13 + 0x4B4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC13 + desc PFSRC13 + 0x4B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC14 + desc PCRC14 + 0x4B8 + 16 + read-write + 0x8100 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC14 + desc PFSRC14 + 0x4BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC15 + desc PCRC15 + 0x4BC + 16 + read-write + 0x8100 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC15 + desc PFSRC15 + 0x4BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD0 + desc PCRD0 + 0x4C0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD0 + desc PFSRD0 + 0x4C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD1 + desc PCRD1 + 0x4C4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD1 + desc PFSRD1 + 0x4C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD2 + desc PCRD2 + 0x4C8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD2 + desc PFSRD2 + 0x4CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD3 + desc PCRD3 + 0x4CC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD3 + desc PFSRD3 + 0x4CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD4 + desc PCRD4 + 0x4D0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD4 + desc PFSRD4 + 0x4D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD5 + desc PCRD5 + 0x4D4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD5 + desc PFSRD5 + 0x4D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD6 + desc PCRD6 + 0x4D8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD6 + desc PFSRD6 + 0x4DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD7 + desc PCRD7 + 0x4DC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD7 + desc PFSRD7 + 0x4DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD8 + desc PCRD8 + 0x4E0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD8 + desc PFSRD8 + 0x4E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD9 + desc PCRD9 + 0x4E4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD9 + desc PFSRD9 + 0x4E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD10 + desc PCRD10 + 0x4E8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD10 + desc PFSRD10 + 0x4EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD11 + desc PCRD11 + 0x4EC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD11 + desc PFSRD11 + 0x4EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD12 + desc PCRD12 + 0x4F0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD12 + desc PFSRD12 + 0x4F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD13 + desc PCRD13 + 0x4F4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD13 + desc PFSRD13 + 0x4F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD14 + desc PCRD14 + 0x4F8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD14 + desc PFSRD14 + 0x4FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD15 + desc PCRD15 + 0x4FC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD15 + desc PFSRD15 + 0x4FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE0 + desc PCRE0 + 0x500 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE0 + desc PFSRE0 + 0x502 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE1 + desc PCRE1 + 0x504 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE1 + desc PFSRE1 + 0x506 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE2 + desc PCRE2 + 0x508 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE2 + desc PFSRE2 + 0x50A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE3 + desc PCRE3 + 0x50C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE3 + desc PFSRE3 + 0x50E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE4 + desc PCRE4 + 0x510 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE4 + desc PFSRE4 + 0x512 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE5 + desc PCRE5 + 0x514 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE5 + desc PFSRE5 + 0x516 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE6 + desc PCRE6 + 0x518 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE6 + desc PFSRE6 + 0x51A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE7 + desc PCRE7 + 0x51C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE7 + desc PFSRE7 + 0x51E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE8 + desc PCRE8 + 0x520 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE8 + desc PFSRE8 + 0x522 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE9 + desc PCRE9 + 0x524 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE9 + desc PFSRE9 + 0x526 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE10 + desc PCRE10 + 0x528 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE10 + desc PFSRE10 + 0x52A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE11 + desc PCRE11 + 0x52C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE11 + desc PFSRE11 + 0x52E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE12 + desc PCRE12 + 0x530 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE12 + desc PFSRE12 + 0x532 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE13 + desc PCRE13 + 0x534 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE13 + desc PFSRE13 + 0x536 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE14 + desc PCRE14 + 0x538 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE14 + desc PFSRE14 + 0x53A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE15 + desc PCRE15 + 0x53C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE15 + desc PFSRE15 + 0x53E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF0 + desc PCRF0 + 0x540 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF0 + desc PFSRF0 + 0x542 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF1 + desc PCRF1 + 0x544 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF1 + desc PFSRF1 + 0x546 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF2 + desc PCRF2 + 0x548 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF2 + desc PFSRF2 + 0x54A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF3 + desc PCRF3 + 0x54C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF3 + desc PFSRF3 + 0x54E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF4 + desc PCRF4 + 0x550 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF4 + desc PFSRF4 + 0x552 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF5 + desc PCRF5 + 0x554 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF5 + desc PFSRF5 + 0x556 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF6 + desc PCRF6 + 0x558 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF6 + desc PFSRF6 + 0x55A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF7 + desc PCRF7 + 0x55C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF7 + desc PFSRF7 + 0x55E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF8 + desc PCRF8 + 0x560 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF8 + desc PFSRF8 + 0x562 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF9 + desc PCRF9 + 0x564 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF9 + desc PFSRF9 + 0x566 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF10 + desc PCRF10 + 0x568 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF10 + desc PFSRF10 + 0x56A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF11 + desc PCRF11 + 0x56C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF11 + desc PFSRF11 + 0x56E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF12 + desc PCRF12 + 0x570 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF12 + desc PFSRF12 + 0x572 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF13 + desc PCRF13 + 0x574 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF13 + desc PFSRF13 + 0x576 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF14 + desc PCRF14 + 0x578 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF14 + desc PFSRF14 + 0x57A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRF15 + desc PCRF15 + 0x57C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRF15 + desc PFSRF15 + 0x57E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG0 + desc PCRG0 + 0x580 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG0 + desc PFSRG0 + 0x582 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG1 + desc PCRG1 + 0x584 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG1 + desc PFSRG1 + 0x586 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG2 + desc PCRG2 + 0x588 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG2 + desc PFSRG2 + 0x58A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG3 + desc PCRG3 + 0x58C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG3 + desc PFSRG3 + 0x58E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG4 + desc PCRG4 + 0x590 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG4 + desc PFSRG4 + 0x592 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG5 + desc PCRG5 + 0x594 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG5 + desc PFSRG5 + 0x596 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG6 + desc PCRG6 + 0x598 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG6 + desc PFSRG6 + 0x59A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG7 + desc PCRG7 + 0x59C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG7 + desc PFSRG7 + 0x59E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG8 + desc PCRG8 + 0x5A0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG8 + desc PFSRG8 + 0x5A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG9 + desc PCRG9 + 0x5A4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG9 + desc PFSRG9 + 0x5A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG10 + desc PCRG10 + 0x5A8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG10 + desc PFSRG10 + 0x5AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG11 + desc PCRG11 + 0x5AC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG11 + desc PFSRG11 + 0x5AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG12 + desc PCRG12 + 0x5B0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG12 + desc PFSRG12 + 0x5B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG13 + desc PCRG13 + 0x5B4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG13 + desc PFSRG13 + 0x5B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG14 + desc PCRG14 + 0x5B8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG14 + desc PFSRG14 + 0x5BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRG15 + desc PCRG15 + 0x5BC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRG15 + desc PFSRG15 + 0x5BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH0 + desc PCRH0 + 0x5C0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH0 + desc PFSRH0 + 0x5C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH1 + desc PCRH1 + 0x5C4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH1 + desc PFSRH1 + 0x5C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH2 + desc PCRH2 + 0x5C8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH2 + desc PFSRH2 + 0x5CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH3 + desc PCRH3 + 0x5CC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH3 + desc PFSRH3 + 0x5CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH4 + desc PCRH4 + 0x5D0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH4 + desc PFSRH4 + 0x5D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH5 + desc PCRH5 + 0x5D4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH5 + desc PFSRH5 + 0x5D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH6 + desc PCRH6 + 0x5D8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH6 + desc PFSRH6 + 0x5DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH7 + desc PCRH7 + 0x5DC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH7 + desc PFSRH7 + 0x5DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH8 + desc PCRH8 + 0x5E0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH8 + desc PFSRH8 + 0x5E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH9 + desc PCRH9 + 0x5E4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH9 + desc PFSRH9 + 0x5E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH10 + desc PCRH10 + 0x5E8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH10 + desc PFSRH10 + 0x5EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH11 + desc PCRH11 + 0x5EC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH11 + desc PFSRH11 + 0x5EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH12 + desc PCRH12 + 0x5F0 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH12 + desc PFSRH12 + 0x5F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH13 + desc PCRH13 + 0x5F4 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH13 + desc PFSRH13 + 0x5F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH14 + desc PCRH14 + 0x5F8 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH14 + desc PFSRH14 + 0x5FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH15 + desc PCRH15 + 0x5FC + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH15 + desc PFSRH15 + 0x5FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI0 + desc PCRI0 + 0x600 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI0 + desc PFSRI0 + 0x602 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI1 + desc PCRI1 + 0x604 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI1 + desc PFSRI1 + 0x606 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI2 + desc PCRI2 + 0x608 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI2 + desc PFSRI2 + 0x60A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI3 + desc PCRI3 + 0x60C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI3 + desc PFSRI3 + 0x60E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI4 + desc PCRI4 + 0x610 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI4 + desc PFSRI4 + 0x612 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI5 + desc PCRI5 + 0x614 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI5 + desc PFSRI5 + 0x616 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI6 + desc PCRI6 + 0x618 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI6 + desc PFSRI6 + 0x61A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI7 + desc PCRI7 + 0x61C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI7 + desc PFSRI7 + 0x61E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI8 + desc PCRI8 + 0x620 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI8 + desc PFSRI8 + 0x622 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI9 + desc PCRI9 + 0x624 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI9 + desc PFSRI9 + 0x626 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI10 + desc PCRI10 + 0x628 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI10 + desc PFSRI10 + 0x62A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI11 + desc PCRI11 + 0x62C + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI11 + desc PFSRI11 + 0x62E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI12 + desc PCRI12 + 0x630 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI12 + desc PFSRI12 + 0x632 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRI13 + desc PCRI13 + 0x634 + 16 + read-write + 0x0 + 0xD777 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + CINSEL + desc CINSEL + 10 + 10 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRI13 + desc PFSRI13 + 0x636 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + + + HASH + desc HASH + 0x40008400 + + 0x0 + 0x80 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0xC777 + + + START + desc START + 0 + 0 + read-write + + + FST_GRP + desc FST_GRP + 1 + 1 + read-write + + + KMSG_END + desc KMSG_END + 2 + 2 + read-write + + + MODE + desc MODE + 5 + 4 + read-write + + + LKEY + desc LKEY + 6 + 6 + read-write + + + BUSY + desc BUSY + 8 + 8 + read-write + + + CYC_END + desc CYC_END + 9 + 9 + read-write + + + HMAC_END + desc HMAC_END + 10 + 10 + read-write + + + HCIE + desc HCIE + 14 + 14 + read-write + + + HEIE + desc HEIE + 15 + 15 + read-write + + + + + HR7 + desc HR7 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR6 + desc HR6 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR5 + desc HR5 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR4 + desc HR4 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR3 + desc HR3 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR2 + desc HR2 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR1 + desc HR1 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR0 + desc HR0 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR15 + desc DR15 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR14 + desc DR14 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR13 + desc DR13 + 0x48 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR12 + desc DR12 + 0x4C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR11 + desc DR11 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR10 + desc DR10 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR9 + desc DR9 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR8 + desc DR8 + 0x5C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR7 + desc DR7 + 0x60 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR6 + desc DR6 + 0x64 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR5 + desc DR5 + 0x68 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR4 + desc DR4 + 0x6C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x70 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR0 + desc DR0 + 0x7C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + HRPWM + desc HRPWM + 0x4003C000 + + 0x0 + 0x58 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR5 + desc CR5 + 0x10 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR6 + desc CR6 + 0x14 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR7 + desc CR7 + 0x18 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR8 + desc CR8 + 0x1C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR9 + desc CR9 + 0x20 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR10 + desc CR10 + 0x24 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR11 + desc CR11 + 0x28 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR12 + desc CR12 + 0x2C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR13 + desc CR13 + 0x30 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR14 + desc CR14 + 0x34 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR15 + desc CR15 + 0x38 + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CR16 + desc CR16 + 0x3C + 32 + read-write + 0x0 + 0xE000FFFF + + + NSEL + desc NSEL + 7 + 0 + read-write + + + PSEL + desc PSEL + 15 + 8 + read-write + + + NE + desc NE + 29 + 29 + read-write + + + PE + desc PE + 30 + 30 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + CALCR0 + desc CALCR0 + 0x50 + 32 + read-write + 0x0 + 0x90FF + + + CALCODE + desc CALCODE + 7 + 0 + read-write + + + ENDF + desc ENDF + 12 + 12 + read-write + + + CALEN + desc CALEN + 15 + 15 + read-write + + + + + CALCR1 + desc CALCR1 + 0x54 + 32 + read-write + 0x0 + 0x90FF + + + CALCODE + desc CALCODE + 7 + 0 + read-write + + + ENDF + desc ENDF + 12 + 12 + read-write + + + CALEN + desc CALEN + 15 + 15 + read-write + + + + + + + I2C1 + desc I2C + 0x4004E000 + + 0x0 + 0x34 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x40 + 0x87DF + + + PE + desc PE + 0 + 0 + read-write + + + SMBUS + desc SMBUS + 1 + 1 + read-write + + + SMBALRTEN + desc SMBALRTEN + 2 + 2 + read-write + + + SMBDEFAULTEN + desc SMBDEFAULTEN + 3 + 3 + read-write + + + SMBHOSTEN + desc SMBHOSTEN + 4 + 4 + read-write + + + GCEN + desc GCEN + 6 + 6 + read-write + + + RESTART + desc RESTART + 7 + 7 + read-write + + + START + desc START + 8 + 8 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + ACK + desc ACK + 10 + 10 + read-write + + + SWRST + desc SWRST + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF052DF + + + STARTIE + desc STARTIE + 0 + 0 + read-write + + + SLADDR0IE + desc SLADDR0IE + 1 + 1 + read-write + + + SLADDR1IE + desc SLADDR1IE + 2 + 2 + read-write + + + TENDIE + desc TENDIE + 3 + 3 + read-write + + + STOPIE + desc STOPIE + 4 + 4 + read-write + + + RFULLIE + desc RFULLIE + 6 + 6 + read-write + + + TEMPTYIE + desc TEMPTYIE + 7 + 7 + read-write + + + ARLOIE + desc ARLOIE + 9 + 9 + read-write + + + NACKIE + desc NACKIE + 12 + 12 + read-write + + + TMOUTIE + desc TMOUTIE + 14 + 14 + read-write + + + GENCALLIE + desc GENCALLIE + 20 + 20 + read-write + + + SMBDEFAULTIE + desc SMBDEFAULTIE + 21 + 21 + read-write + + + SMBHOSTIE + desc SMBHOSTIE + 22 + 22 + read-write + + + SMBALRTIE + desc SMBALRTIE + 23 + 23 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x6 + 0x87 + + + TMOUTEN + desc TMOUTEN + 0 + 0 + read-write + + + LTMOUT + desc LTMOUT + 1 + 1 + read-write + + + HTMOUT + desc HTMOUT + 2 + 2 + read-write + + + FACKEN + desc FACKEN + 7 + 7 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x300307 + 0x400 + + + BUSWAIT + desc BUSWAIT + 10 + 10 + read-write + + + + + SLR0 + desc SLR0 + 0x10 + 32 + read-write + 0x1000 + 0x93FF + + + SLADDR0 + desc SLADDR0 + 9 + 0 + read-write + + + SLADDR0EN + desc SLADDR0EN + 12 + 12 + read-write + + + ADDRMOD0 + desc ADDRMOD0 + 15 + 15 + read-write + + + + + SLR1 + desc SLR1 + 0x14 + 32 + read-write + 0x0 + 0x93FF + + + SLADDR1 + desc SLADDR1 + 9 + 0 + read-write + + + SLADDR1EN + desc SLADDR1EN + 12 + 12 + read-write + + + ADDRMOD1 + desc ADDRMOD1 + 15 + 15 + read-write + + + + + SLTR + desc SLTR + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TOUTLOW + desc TOUTLOW + 15 + 0 + read-write + + + TOUTHIGH + desc TOUTHIGH + 31 + 16 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-write + 0x0 + 0xF756DF + + + STARTF + desc STARTF + 0 + 0 + read-write + + + SLADDR0F + desc SLADDR0F + 1 + 1 + read-write + + + SLADDR1F + desc SLADDR1F + 2 + 2 + read-write + + + TENDF + desc TENDF + 3 + 3 + read-write + + + STOPF + desc STOPF + 4 + 4 + read-write + + + RFULLF + desc RFULLF + 6 + 6 + read-write + + + TEMPTYF + desc TEMPTYF + 7 + 7 + read-write + + + ARLOF + desc ARLOF + 9 + 9 + read-write + + + ACKRF + desc ACKRF + 10 + 10 + read-write + + + NACKF + desc NACKF + 12 + 12 + read-write + + + TMOUTF + desc TMOUTF + 14 + 14 + read-write + + + MSL + desc MSL + 16 + 16 + read-write + + + BUSY + desc BUSY + 17 + 17 + read-write + + + TRA + desc TRA + 18 + 18 + read-write + + + GENCALLF + desc GENCALLF + 20 + 20 + read-write + + + SMBDEFAULTF + desc SMBDEFAULTF + 21 + 21 + read-write + + + SMBHOSTF + desc SMBHOSTF + 22 + 22 + read-write + + + SMBALRTF + desc SMBALRTF + 23 + 23 + read-write + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0xF052DF + + + STARTFCLR + desc STARTFCLR + 0 + 0 + write-only + + + SLADDR0FCLR + desc SLADDR0FCLR + 1 + 1 + write-only + + + SLADDR1FCLR + desc SLADDR1FCLR + 2 + 2 + write-only + + + TENDFCLR + desc TENDFCLR + 3 + 3 + write-only + + + STOPFCLR + desc STOPFCLR + 4 + 4 + write-only + + + RFULLFCLR + desc RFULLFCLR + 6 + 6 + write-only + + + TEMPTYFCLR + desc TEMPTYFCLR + 7 + 7 + write-only + + + ARLOFCLR + desc ARLOFCLR + 9 + 9 + write-only + + + NACKFCLR + desc NACKFCLR + 12 + 12 + write-only + + + TMOUTFCLR + desc TMOUTFCLR + 14 + 14 + write-only + + + GENCALLFCLR + desc GENCALLFCLR + 20 + 20 + write-only + + + SMBDEFAULTFCLR + desc SMBDEFAULTFCLR + 21 + 21 + write-only + + + SMBHOSTFCLR + desc SMBHOSTFCLR + 22 + 22 + write-only + + + SMBALRTFCLR + desc SMBALRTFCLR + 23 + 23 + write-only + + + + + DTR + desc DTR + 0x24 + 8 + write-only + 0xFF + 0xFF + + + DT + desc DT + 7 + 0 + write-only + + + + + DRR + desc DRR + 0x28 + 8 + read-only + 0x0 + 0xFF + + + DR + desc DR + 7 + 0 + read-only + + + + + CCR + desc CCR + 0x2C + 32 + read-write + 0x1F1F + 0x71F1F + + + SLOWW + desc SLOWW + 4 + 0 + read-write + + + SHIGHW + desc SHIGHW + 12 + 8 + read-write + + + FREQ + desc FREQ + 18 + 16 + read-write + + + + + FLTR + desc FLTR + 0x30 + 32 + read-write + 0x10 + 0x33 + + + DNF + desc DNF + 1 + 0 + read-write + + + DNFEN + desc DNFEN + 4 + 4 + read-write + + + ANFEN + desc ANFEN + 5 + 5 + read-write + + + + + + + I2C2 + desc I2C + 0x4004E400 + + 0x0 + 0x34 + + + + I2C3 + desc I2C + 0x4004E800 + + 0x0 + 0x34 + + + + I2C4 + desc I2C + 0x4004EC00 + + 0x0 + 0x34 + + + + I2C5 + desc I2C + 0x4004F000 + + 0x0 + 0x34 + + + + I2C6 + desc I2C + 0x4004F400 + + 0x0 + 0x34 + + + + I2S1 + desc I2S + 0x4001E000 + + 0x0 + 0x1C + + + + CTRL + desc CTRL + 0x0 + 32 + read-write + 0x2200 + 0x1FF77FF + + + TXE + desc TXE + 0 + 0 + read-write + + + TXIE + desc TXIE + 1 + 1 + read-write + + + RXE + desc RXE + 2 + 2 + read-write + + + RXIE + desc RXIE + 3 + 3 + read-write + + + EIE + desc EIE + 4 + 4 + read-write + + + WMS + desc WMS + 5 + 5 + read-write + + + ODD + desc ODD + 6 + 6 + read-write + + + MCKOE + desc MCKOE + 7 + 7 + read-write + + + TXBIRQWL + desc TXBIRQWL + 10 + 8 + read-write + + + RXBIRQWL + desc RXBIRQWL + 14 + 12 + read-write + + + FIFOR + desc FIFOR + 16 + 16 + read-write + + + CODECRC + desc CODECRC + 17 + 17 + read-write + + + I2SPLLSEL + desc I2SPLLSEL + 18 + 18 + read-write + + + SDOE + desc SDOE + 19 + 19 + read-write + + + LRCKOE + desc LRCKOE + 20 + 20 + read-write + + + CKOE + desc CKOE + 21 + 21 + read-write + + + DUPLEX + desc DUPLEX + 22 + 22 + read-write + + + CLKSEL + desc CLKSEL + 23 + 23 + read-write + + + SRST + desc SRST + 24 + 24 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-only + 0x14 + 0x3F + + + TXBA + desc TXBA + 0 + 0 + read-only + + + RXBA + desc RXBA + 1 + 1 + read-only + + + TXBE + desc TXBE + 2 + 2 + read-only + + + TXBF + desc TXBF + 3 + 3 + read-only + + + RXBE + desc RXBE + 4 + 4 + read-only + + + RXBF + desc RXBF + 5 + 5 + read-only + + + + + ER + desc ER + 0x8 + 32 + read-write + 0x0 + 0x3 + + + TXERR + desc TXERR + 0 + 0 + read-write + + + RXERR + desc RXERR + 1 + 1 + read-write + + + + + CFGR + desc CFGR + 0xC + 32 + read-write + 0x0 + 0x3F + + + I2SSTD + desc I2SSTD + 1 + 0 + read-write + + + DATLEN + desc DATLEN + 3 + 2 + read-write + + + CHLEN + desc CHLEN + 4 + 4 + read-write + + + PCMSYNC + desc PCMSYNC + 5 + 5 + read-write + + + + + TXBUF + desc TXBUF + 0x10 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + RXBUF + desc RXBUF + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PR + desc PR + 0x18 + 32 + read-write + 0x2 + 0xFF + + + I2SDIV + desc I2SDIV + 7 + 0 + read-write + + + + + + + I2S2 + desc I2S + 0x4001E400 + + 0x0 + 0x1C + + + + I2S3 + desc I2S + 0x40022000 + + 0x0 + 0x1C + + + + I2S4 + desc I2S + 0x40022400 + + 0x0 + 0x1C + + + + ICG + desc ICG + 0x00000400 + + 0x0 + 0x10 + + + + ICG0 + desc ICG0 + 0x0 + 32 + read-only + 0xFFFFFFFF + 0x1FFF1FFF + + + SWDTAUTS + desc SWDTAUTS + 0 + 0 + read-only + + + SWDTITS + desc SWDTITS + 1 + 1 + read-only + + + SWDTPERI + desc SWDTPERI + 3 + 2 + read-only + + + SWDTCKS + desc SWDTCKS + 7 + 4 + read-only + + + SWDTWDPT + desc SWDTWDPT + 11 + 8 + read-only + + + SWDTSLPOFF + desc SWDTSLPOFF + 12 + 12 + read-only + + + WDTAUTS + desc WDTAUTS + 16 + 16 + read-only + + + WDTITS + desc WDTITS + 17 + 17 + read-only + + + WDTPERI + desc WDTPERI + 19 + 18 + read-only + + + WDTCKS + desc WDTCKS + 23 + 20 + read-only + + + WDTWDPT + desc WDTWDPT + 27 + 24 + read-only + + + WDTSLPOFF + desc WDTSLPOFF + 28 + 28 + read-only + + + + + ICG1 + desc ICG1 + 0x4 + 32 + read-only + 0xFFFFFFFF + 0x70101 + + + HRCFREQSEL + desc HRCFREQSEL + 0 + 0 + read-only + + + HRCSTOP + desc HRCSTOP + 8 + 8 + read-only + + + BOR_LEV + desc BOR_LEV + 17 + 16 + read-only + + + BORDIS + desc BORDIS + 18 + 18 + read-only + + + + + ICG2 + desc ICG2 + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFF + + + BGO1M + desc BGO1M + 23 + 0 + read-only + + + + + ICG3 + desc ICG3 + 0xC + 32 + read-only + 0xFFFFFFFF + 0xFFFF + + + DBUSPRT + desc DBUSPRT + 15 + 0 + read-only + + + + + + + INTC + desc INTC + 0x40051000 + + 0x0 + 0x2B4 + + + + NOCCR + desc NOCCR + 0x0 + 32 + read-write + 0x0 + 0x3000 + + + NOCSEL + desc NOCSEL + 13 + 12 + read-write + + + + + NMIENR + desc NMIENR + 0x4 + 32 + read-write + 0x0 + 0xF2E + + + SWDTENR + desc SWDTENR + 1 + 1 + read-write + + + PVD1ENR + desc PVD1ENR + 2 + 2 + read-write + + + PVD2ENR + desc PVD2ENR + 3 + 3 + read-write + + + XTALSTPENR + desc XTALSTPENR + 5 + 5 + read-write + + + REPENR + desc REPENR + 8 + 8 + read-write + + + RECCENR + desc RECCENR + 9 + 9 + read-write + + + BUSMENR + desc BUSMENR + 10 + 10 + read-write + + + WDTENR + desc WDTENR + 11 + 11 + read-write + + + + + NMIFR + desc NMIFR + 0x8 + 32 + read-write + 0x0 + 0xF2E + + + SWDTFR + desc SWDTFR + 1 + 1 + read-write + + + PVD1FR + desc PVD1FR + 2 + 2 + read-write + + + PVD2FR + desc PVD2FR + 3 + 3 + read-write + + + XTALSTPFR + desc XTALSTPFR + 5 + 5 + read-write + + + REPFR + desc REPFR + 8 + 8 + read-write + + + RECCFR + desc RECCFR + 9 + 9 + read-write + + + BUSMFR + desc BUSMFR + 10 + 10 + read-write + + + WDTFR + desc WDTFR + 11 + 11 + read-write + + + + + NMICFR + desc NMICFR + 0xC + 32 + read-write + 0x0 + 0xF2E + + + SWDTCFR + desc SWDTCFR + 1 + 1 + read-write + + + PVD1CFR + desc PVD1CFR + 2 + 2 + read-write + + + PVD2CFR + desc PVD2CFR + 3 + 3 + read-write + + + XTALSTPCFR + desc XTALSTPCFR + 5 + 5 + read-write + + + REPCFR + desc REPCFR + 8 + 8 + read-write + + + RECCCFR + desc RECCCFR + 9 + 9 + read-write + + + BUSMCFR + desc BUSMCFR + 10 + 10 + read-write + + + WDTCFR + desc WDTCFR + 11 + 11 + read-write + + + + + EIRQCR0 + desc EIRQCR0 + 0x10 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR1 + desc EIRQCR1 + 0x14 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR2 + desc EIRQCR2 + 0x18 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR3 + desc EIRQCR3 + 0x1C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR4 + desc EIRQCR4 + 0x20 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR5 + desc EIRQCR5 + 0x24 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR6 + desc EIRQCR6 + 0x28 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR7 + desc EIRQCR7 + 0x2C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR8 + desc EIRQCR8 + 0x30 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR9 + desc EIRQCR9 + 0x34 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR10 + desc EIRQCR10 + 0x38 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR11 + desc EIRQCR11 + 0x3C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR12 + desc EIRQCR12 + 0x40 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR13 + desc EIRQCR13 + 0x44 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR14 + desc EIRQCR14 + 0x48 + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + EIRQCR15 + desc EIRQCR15 + 0x4C + 32 + read-write + 0x0 + 0x80B3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + NOCEN + desc NOCEN + 15 + 15 + read-write + + + + + WUPEN + desc WUPEN + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + EIRQWUEN + desc EIRQWUEN + 15 + 0 + read-write + + + SWDTWUEN + desc SWDTWUEN + 16 + 16 + read-write + + + PVD1WUEN + desc PVD1WUEN + 17 + 17 + read-write + + + PVD2WUEN + desc PVD2WUEN + 18 + 18 + read-write + + + CMPWUEN + desc CMPWUEN + 19 + 19 + read-write + + + WKTMWUEN + desc WKTMWUEN + 20 + 20 + read-write + + + RTCALMWUEN + desc RTCALMWUEN + 21 + 21 + read-write + + + RTCPRDWUEN + desc RTCPRDWUEN + 22 + 22 + read-write + + + TMR0GCMWUEN + desc TMR0GCMWUEN + 23 + 23 + read-write + + + TMR2GCMWUEN + desc TMR2GCMWUEN + 24 + 24 + read-write + + + TMR2OVFWUEN + desc TMR2OVFWUEN + 25 + 25 + read-write + + + RXWUEN + desc RXWUEN + 26 + 26 + read-write + + + USHWUEN + desc USHWUEN + 27 + 27 + read-write + + + USFWUEN + desc USFWUEN + 28 + 28 + read-write + + + ETHWUEN + desc ETHWUEN + 29 + 29 + read-write + + + + + EIRQFR + desc EIRQFR + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQFR0 + desc EIRQFR0 + 0 + 0 + read-write + + + EIRQFR1 + desc EIRQFR1 + 1 + 1 + read-write + + + EIRQFR2 + desc EIRQFR2 + 2 + 2 + read-write + + + EIRQFR3 + desc EIRQFR3 + 3 + 3 + read-write + + + EIRQFR4 + desc EIRQFR4 + 4 + 4 + read-write + + + EIRQFR5 + desc EIRQFR5 + 5 + 5 + read-write + + + EIRQFR6 + desc EIRQFR6 + 6 + 6 + read-write + + + EIRQFR7 + desc EIRQFR7 + 7 + 7 + read-write + + + EIRQFR8 + desc EIRQFR8 + 8 + 8 + read-write + + + EIRQFR9 + desc EIRQFR9 + 9 + 9 + read-write + + + EIRQFR10 + desc EIRQFR10 + 10 + 10 + read-write + + + EIRQFR11 + desc EIRQFR11 + 11 + 11 + read-write + + + EIRQFR12 + desc EIRQFR12 + 12 + 12 + read-write + + + EIRQFR13 + desc EIRQFR13 + 13 + 13 + read-write + + + EIRQFR14 + desc EIRQFR14 + 14 + 14 + read-write + + + EIRQFR15 + desc EIRQFR15 + 15 + 15 + read-write + + + + + EIRQCFR + desc EIRQCFR + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQCFR0 + desc EIRQCFR0 + 0 + 0 + read-write + + + EIRQCFR1 + desc EIRQCFR1 + 1 + 1 + read-write + + + EIRQCFR2 + desc EIRQCFR2 + 2 + 2 + read-write + + + EIRQCFR3 + desc EIRQCFR3 + 3 + 3 + read-write + + + EIRQCFR4 + desc EIRQCFR4 + 4 + 4 + read-write + + + EIRQCFR5 + desc EIRQCFR5 + 5 + 5 + read-write + + + EIRQCFR6 + desc EIRQCFR6 + 6 + 6 + read-write + + + EIRQCFR7 + desc EIRQCFR7 + 7 + 7 + read-write + + + EIRQCFR8 + desc EIRQCFR8 + 8 + 8 + read-write + + + EIRQCFR9 + desc EIRQCFR9 + 9 + 9 + read-write + + + EIRQCFR10 + desc EIRQCFR10 + 10 + 10 + read-write + + + EIRQCFR11 + desc EIRQCFR11 + 11 + 11 + read-write + + + EIRQCFR12 + desc EIRQCFR12 + 12 + 12 + read-write + + + EIRQCFR13 + desc EIRQCFR13 + 13 + 13 + read-write + + + EIRQCFR14 + desc EIRQCFR14 + 14 + 14 + read-write + + + EIRQCFR15 + desc EIRQCFR15 + 15 + 15 + read-write + + + + + SEL0 + desc SEL0 + 0x5C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL1 + desc SEL1 + 0x60 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL2 + desc SEL2 + 0x64 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL3 + desc SEL3 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL4 + desc SEL4 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL5 + desc SEL5 + 0x70 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL6 + desc SEL6 + 0x74 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL7 + desc SEL7 + 0x78 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL8 + desc SEL8 + 0x7C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL9 + desc SEL9 + 0x80 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL10 + desc SEL10 + 0x84 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL11 + desc SEL11 + 0x88 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL12 + desc SEL12 + 0x8C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL13 + desc SEL13 + 0x90 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL14 + desc SEL14 + 0x94 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL15 + desc SEL15 + 0x98 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL16 + desc SEL16 + 0x9C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL17 + desc SEL17 + 0xA0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL18 + desc SEL18 + 0xA4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL19 + desc SEL19 + 0xA8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL20 + desc SEL20 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL21 + desc SEL21 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL22 + desc SEL22 + 0xB4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL23 + desc SEL23 + 0xB8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL24 + desc SEL24 + 0xBC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL25 + desc SEL25 + 0xC0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL26 + desc SEL26 + 0xC4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL27 + desc SEL27 + 0xC8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL28 + desc SEL28 + 0xCC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL29 + desc SEL29 + 0xD0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL30 + desc SEL30 + 0xD4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL31 + desc SEL31 + 0xD8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL32 + desc SEL32 + 0xDC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL46 + desc SEL46 + 0x114 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL47 + desc SEL47 + 0x118 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL48 + desc SEL48 + 0x11C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL49 + desc SEL49 + 0x120 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL50 + desc SEL50 + 0x124 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL51 + desc SEL51 + 0x128 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL52 + desc SEL52 + 0x12C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL53 + desc SEL53 + 0x130 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL54 + desc SEL54 + 0x134 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL55 + desc SEL55 + 0x138 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL56 + desc SEL56 + 0x13C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL57 + desc SEL57 + 0x140 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL58 + desc SEL58 + 0x144 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL59 + desc SEL59 + 0x148 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL60 + desc SEL60 + 0x14C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL61 + desc SEL61 + 0x150 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL62 + desc SEL62 + 0x154 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL63 + desc SEL63 + 0x158 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL64 + desc SEL64 + 0x15C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL65 + desc SEL65 + 0x160 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL66 + desc SEL66 + 0x164 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL67 + desc SEL67 + 0x168 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL68 + desc SEL68 + 0x16C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL69 + desc SEL69 + 0x170 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL70 + desc SEL70 + 0x174 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL71 + desc SEL71 + 0x178 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL72 + desc SEL72 + 0x17C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL73 + desc SEL73 + 0x180 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL74 + desc SEL74 + 0x184 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL75 + desc SEL75 + 0x188 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL76 + desc SEL76 + 0x18C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL77 + desc SEL77 + 0x190 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL78 + desc SEL78 + 0x194 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL79 + desc SEL79 + 0x198 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL80 + desc SEL80 + 0x19C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL81 + desc SEL81 + 0x1A0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL82 + desc SEL82 + 0x1A4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL83 + desc SEL83 + 0x1A8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL84 + desc SEL84 + 0x1AC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL85 + desc SEL85 + 0x1B0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL86 + desc SEL86 + 0x1B4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL87 + desc SEL87 + 0x1B8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL88 + desc SEL88 + 0x1BC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL89 + desc SEL89 + 0x1C0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL90 + desc SEL90 + 0x1C4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL91 + desc SEL91 + 0x1C8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL92 + desc SEL92 + 0x1CC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL93 + desc SEL93 + 0x1D0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL94 + desc SEL94 + 0x1D4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL95 + desc SEL95 + 0x1D8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL96 + desc SEL96 + 0x1DC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL97 + desc SEL97 + 0x1E0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL98 + desc SEL98 + 0x1E4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL99 + desc SEL99 + 0x1E8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL100 + desc SEL100 + 0x1EC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL101 + desc SEL101 + 0x1F0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL102 + desc SEL102 + 0x1F4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL103 + desc SEL103 + 0x1F8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL104 + desc SEL104 + 0x1FC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL105 + desc SEL105 + 0x200 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL106 + desc SEL106 + 0x204 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL107 + desc SEL107 + 0x208 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL108 + desc SEL108 + 0x20C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL109 + desc SEL109 + 0x210 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL110 + desc SEL110 + 0x214 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL111 + desc SEL111 + 0x218 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL112 + desc SEL112 + 0x21C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL113 + desc SEL113 + 0x220 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL114 + desc SEL114 + 0x224 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL115 + desc SEL115 + 0x228 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL122 + desc SEL122 + 0x244 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL123 + desc SEL123 + 0x248 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL124 + desc SEL124 + 0x24C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL125 + desc SEL125 + 0x250 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL126 + desc SEL126 + 0x254 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL127 + desc SEL127 + 0x258 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + VSSEL128 + desc VSSEL128 + 0x25C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL129 + desc VSSEL129 + 0x260 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL130 + desc VSSEL130 + 0x264 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL131 + desc VSSEL131 + 0x268 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL132 + desc VSSEL132 + 0x26C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL133 + desc VSSEL133 + 0x270 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL134 + desc VSSEL134 + 0x274 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL135 + desc VSSEL135 + 0x278 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL136 + desc VSSEL136 + 0x27C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL137 + desc VSSEL137 + 0x280 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL138 + desc VSSEL138 + 0x284 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL139 + desc VSSEL139 + 0x288 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL140 + desc VSSEL140 + 0x28C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL141 + desc VSSEL141 + 0x290 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL142 + desc VSSEL142 + 0x294 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL143 + desc VSSEL143 + 0x298 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + SWIER + desc SWIER + 0x29C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SWIE0 + desc SWIE0 + 0 + 0 + read-write + + + SWIE1 + desc SWIE1 + 1 + 1 + read-write + + + SWIE2 + desc SWIE2 + 2 + 2 + read-write + + + SWIE3 + desc SWIE3 + 3 + 3 + read-write + + + SWIE4 + desc SWIE4 + 4 + 4 + read-write + + + SWIE5 + desc SWIE5 + 5 + 5 + read-write + + + SWIE6 + desc SWIE6 + 6 + 6 + read-write + + + SWIE7 + desc SWIE7 + 7 + 7 + read-write + + + SWIE8 + desc SWIE8 + 8 + 8 + read-write + + + SWIE9 + desc SWIE9 + 9 + 9 + read-write + + + SWIE10 + desc SWIE10 + 10 + 10 + read-write + + + SWIE11 + desc SWIE11 + 11 + 11 + read-write + + + SWIE12 + desc SWIE12 + 12 + 12 + read-write + + + SWIE13 + desc SWIE13 + 13 + 13 + read-write + + + SWIE14 + desc SWIE14 + 14 + 14 + read-write + + + SWIE15 + desc SWIE15 + 15 + 15 + read-write + + + SWIE16 + desc SWIE16 + 16 + 16 + read-write + + + SWIE17 + desc SWIE17 + 17 + 17 + read-write + + + SWIE18 + desc SWIE18 + 18 + 18 + read-write + + + SWIE19 + desc SWIE19 + 19 + 19 + read-write + + + SWIE20 + desc SWIE20 + 20 + 20 + read-write + + + SWIE21 + desc SWIE21 + 21 + 21 + read-write + + + SWIE22 + desc SWIE22 + 22 + 22 + read-write + + + SWIE23 + desc SWIE23 + 23 + 23 + read-write + + + SWIE24 + desc SWIE24 + 24 + 24 + read-write + + + SWIE25 + desc SWIE25 + 25 + 25 + read-write + + + SWIE26 + desc SWIE26 + 26 + 26 + read-write + + + SWIE27 + desc SWIE27 + 27 + 27 + read-write + + + SWIE28 + desc SWIE28 + 28 + 28 + read-write + + + SWIE29 + desc SWIE29 + 29 + 29 + read-write + + + SWIE30 + desc SWIE30 + 30 + 30 + read-write + + + SWIE31 + desc SWIE31 + 31 + 31 + read-write + + + + + EVTER + desc EVTER + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + EVTE0 + desc EVTE0 + 0 + 0 + read-write + + + EVTE1 + desc EVTE1 + 1 + 1 + read-write + + + EVTE2 + desc EVTE2 + 2 + 2 + read-write + + + EVTE3 + desc EVTE3 + 3 + 3 + read-write + + + EVTE4 + desc EVTE4 + 4 + 4 + read-write + + + EVTE5 + desc EVTE5 + 5 + 5 + read-write + + + EVTE6 + desc EVTE6 + 6 + 6 + read-write + + + EVTE7 + desc EVTE7 + 7 + 7 + read-write + + + EVTE8 + desc EVTE8 + 8 + 8 + read-write + + + EVTE9 + desc EVTE9 + 9 + 9 + read-write + + + EVTE10 + desc EVTE10 + 10 + 10 + read-write + + + EVTE11 + desc EVTE11 + 11 + 11 + read-write + + + EVTE12 + desc EVTE12 + 12 + 12 + read-write + + + EVTE13 + desc EVTE13 + 13 + 13 + read-write + + + EVTE14 + desc EVTE14 + 14 + 14 + read-write + + + EVTE15 + desc EVTE15 + 15 + 15 + read-write + + + EVTE16 + desc EVTE16 + 16 + 16 + read-write + + + EVTE17 + desc EVTE17 + 17 + 17 + read-write + + + EVTE18 + desc EVTE18 + 18 + 18 + read-write + + + EVTE19 + desc EVTE19 + 19 + 19 + read-write + + + EVTE20 + desc EVTE20 + 20 + 20 + read-write + + + EVTE21 + desc EVTE21 + 21 + 21 + read-write + + + EVTE22 + desc EVTE22 + 22 + 22 + read-write + + + EVTE23 + desc EVTE23 + 23 + 23 + read-write + + + EVTE24 + desc EVTE24 + 24 + 24 + read-write + + + EVTE25 + desc EVTE25 + 25 + 25 + read-write + + + EVTE26 + desc EVTE26 + 26 + 26 + read-write + + + EVTE27 + desc EVTE27 + 27 + 27 + read-write + + + EVTE28 + desc EVTE28 + 28 + 28 + read-write + + + EVTE29 + desc EVTE29 + 29 + 29 + read-write + + + EVTE30 + desc EVTE30 + 30 + 30 + read-write + + + EVTE31 + desc EVTE31 + 31 + 31 + read-write + + + + + IER + desc IER + 0x2A4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IER0 + desc IER0 + 0 + 0 + read-write + + + IER1 + desc IER1 + 1 + 1 + read-write + + + IER2 + desc IER2 + 2 + 2 + read-write + + + IER3 + desc IER3 + 3 + 3 + read-write + + + IER4 + desc IER4 + 4 + 4 + read-write + + + IER5 + desc IER5 + 5 + 5 + read-write + + + IER6 + desc IER6 + 6 + 6 + read-write + + + IER7 + desc IER7 + 7 + 7 + read-write + + + IER8 + desc IER8 + 8 + 8 + read-write + + + IER9 + desc IER9 + 9 + 9 + read-write + + + IER10 + desc IER10 + 10 + 10 + read-write + + + IER11 + desc IER11 + 11 + 11 + read-write + + + IER12 + desc IER12 + 12 + 12 + read-write + + + IER13 + desc IER13 + 13 + 13 + read-write + + + IER14 + desc IER14 + 14 + 14 + read-write + + + IER15 + desc IER15 + 15 + 15 + read-write + + + IER16 + desc IER16 + 16 + 16 + read-write + + + IER17 + desc IER17 + 17 + 17 + read-write + + + IER18 + desc IER18 + 18 + 18 + read-write + + + IER19 + desc IER19 + 19 + 19 + read-write + + + IER20 + desc IER20 + 20 + 20 + read-write + + + IER21 + desc IER21 + 21 + 21 + read-write + + + IER22 + desc IER22 + 22 + 22 + read-write + + + IER23 + desc IER23 + 23 + 23 + read-write + + + IER24 + desc IER24 + 24 + 24 + read-write + + + IER25 + desc IER25 + 25 + 25 + read-write + + + IER26 + desc IER26 + 26 + 26 + read-write + + + IER27 + desc IER27 + 27 + 27 + read-write + + + IER28 + desc IER28 + 28 + 28 + read-write + + + IER29 + desc IER29 + 29 + 29 + read-write + + + IER30 + desc IER30 + 30 + 30 + read-write + + + IER31 + desc IER31 + 31 + 31 + read-write + + + + + + + KEYSCAN + desc KEYSCAN + 0x40050C00 + + 0x0 + 0xC + + + + SCR + desc SCR + 0x0 + 32 + read-write + 0x0 + 0xFF37FFFF + + + KEYINSEL + desc KEYINSEL + 15 + 0 + read-write + + + KEYOUTSEL + desc KEYOUTSEL + 18 + 16 + read-write + + + CKSEL + desc CKSEL + 21 + 20 + read-write + + + T_LLEVEL + desc T_LLEVEL + 28 + 24 + read-write + + + T_HIZ + desc T_HIZ + 31 + 29 + read-write + + + + + SER + desc SER + 0x4 + 32 + read-write + 0x0 + 0x1 + + + SEN + desc SEN + 0 + 0 + read-write + + + + + SSR + desc SSR + 0x8 + 32 + read-write + 0x0 + 0x7 + + + INDEX + desc INDEX + 2 + 0 + read-write + + + + + + + MAU + desc MAU + 0x40055000 + + 0x0 + 0x18 + + + + CSR + desc CSR + 0x0 + 32 + read-write + 0x0 + 0x1F0B + + + START + desc START + 0 + 0 + read-write + + + INTEN + desc INTEN + 1 + 1 + read-write + + + BUSY + desc BUSY + 3 + 3 + read-write + + + SHIFT + desc SHIFT + 12 + 8 + read-write + + + + + DTR0 + desc DTR0 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RTR0 + desc RTR0 + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + SQRT_DOUT + desc SQRT_DOUT + 16 + 0 + read-write + + + + + DTR1 + desc DTR1 + 0x10 + 32 + read-write + 0x0 + 0xFFF + + + SIN_DIN + desc SIN_DIN + 11 + 0 + read-write + + + + + RTR1 + desc RTR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + SIN_DOUT + desc SIN_DOUT + 15 + 0 + read-write + + + + + + + MPU + desc MPU + 0x40050000 + ETH + + 0x0 + 0xA0 + + + + RGD0 + desc RGD0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD1 + desc RGD1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD2 + desc RGD2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD3 + desc RGD3 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD4 + desc RGD4 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD5 + desc RGD5 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD6 + desc RGD6 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD7 + desc RGD7 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD8 + desc RGD8 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD9 + desc RGD9 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD10 + desc RGD10 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD11 + desc RGD11 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD12 + desc RGD12 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD13 + desc RGD13 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD14 + desc RGD14 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD15 + desc RGD15 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + SR + desc SR + 0x40 + 32 + read-only + 0x0 + 0x1F + + + SMPU1EAF + desc SMPU1EAF + 0 + 0 + read-only + + + SMPU2EAF + desc SMPU2EAF + 1 + 1 + read-only + + + FMPUEAF + desc FMPUEAF + 2 + 2 + read-only + + + HMPUEAF + desc HMPUEAF + 3 + 3 + read-only + + + EMPUEAF + desc EMPUEAF + 4 + 4 + read-only + + + + + ECLR + desc ECLR + 0x44 + 32 + write-only + 0x0 + 0x1F + + + SMPU1ECLR + desc SMPU1ECLR + 0 + 0 + write-only + + + SMPU2ECLR + desc SMPU2ECLR + 1 + 1 + write-only + + + FMPUECLR + desc FMPUECLR + 2 + 2 + write-only + + + HMPUECLR + desc HMPUECLR + 3 + 3 + write-only + + + EMPUECLR + desc EMPUECLR + 4 + 4 + write-only + + + + + WP + desc WP + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + MPUWE + desc MPUWE + 0 + 0 + read-write + + + WKEY + desc WKEY + 15 + 1 + write-only + + + + + IPPR + desc IPPR + 0x4C + 32 + read-write + 0x0 + 0xBFFFF3FF + + + AESRDP + desc AESRDP + 0 + 0 + read-write + + + AESWRP + desc AESWRP + 1 + 1 + read-write + + + HASHRDP + desc HASHRDP + 2 + 2 + read-write + + + HASHWRP + desc HASHWRP + 3 + 3 + read-write + + + TRNGRDP + desc TRNGRDP + 4 + 4 + read-write + + + TRNGWRP + desc TRNGWRP + 5 + 5 + read-write + + + CRCRDP + desc CRCRDP + 6 + 6 + read-write + + + CRCWRP + desc CRCWRP + 7 + 7 + read-write + + + EFMRDP + desc EFMRDP + 8 + 8 + read-write + + + EFMWRP + desc EFMWRP + 9 + 9 + read-write + + + WDTRDP + desc WDTRDP + 12 + 12 + read-write + + + WDTWRP + desc WDTWRP + 13 + 13 + read-write + + + SWDTRDP + desc SWDTRDP + 14 + 14 + read-write + + + SWDTWRP + desc SWDTWRP + 15 + 15 + read-write + + + BKSRAMRDP + desc BKSRAMRDP + 16 + 16 + read-write + + + BKSRAMWRP + desc BKSRAMWRP + 17 + 17 + read-write + + + RTCRDP + desc RTCRDP + 18 + 18 + read-write + + + RTCWRP + desc RTCWRP + 19 + 19 + read-write + + + DMPURDP + desc DMPURDP + 20 + 20 + read-write + + + DMPUWRP + desc DMPUWRP + 21 + 21 + read-write + + + SRAMCRDP + desc SRAMCRDP + 22 + 22 + read-write + + + SRAMCWRP + desc SRAMCWRP + 23 + 23 + read-write + + + INTCRDP + desc INTCRDP + 24 + 24 + read-write + + + INTCWRP + desc INTCWRP + 25 + 25 + read-write + + + SYSCRDP + desc SYSCRDP + 26 + 26 + read-write + + + SYSCWRP + desc SYSCWRP + 27 + 27 + read-write + + + MSTPRDP + desc MSTPRDP + 28 + 28 + read-write + + + MSPTWRP + desc MSPTWRP + 29 + 29 + read-write + + + BUSERRE + desc BUSERRE + 31 + 31 + read-write + + + + + S1RGE + desc S1RGE + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0E + desc S1RG0E + 0 + 0 + read-write + + + S1RG1E + desc S1RG1E + 1 + 1 + read-write + + + S1RG2E + desc S1RG2E + 2 + 2 + read-write + + + S1RG3E + desc S1RG3E + 3 + 3 + read-write + + + S1RG4E + desc S1RG4E + 4 + 4 + read-write + + + S1RG5E + desc S1RG5E + 5 + 5 + read-write + + + S1RG6E + desc S1RG6E + 6 + 6 + read-write + + + S1RG7E + desc S1RG7E + 7 + 7 + read-write + + + S1RG8E + desc S1RG8E + 8 + 8 + read-write + + + S1RG9E + desc S1RG9E + 9 + 9 + read-write + + + S1RG10E + desc S1RG10E + 10 + 10 + read-write + + + S1RG11E + desc S1RG11E + 11 + 11 + read-write + + + S1RG12E + desc S1RG12E + 12 + 12 + read-write + + + S1RG13E + desc S1RG13E + 13 + 13 + read-write + + + S1RG14E + desc S1RG14E + 14 + 14 + read-write + + + S1RG15E + desc S1RG15E + 15 + 15 + read-write + + + + + S1RGWP + desc S1RGWP + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0WP + desc S1RG0WP + 0 + 0 + read-write + + + S1RG1WP + desc S1RG1WP + 1 + 1 + read-write + + + S1RG2WP + desc S1RG2WP + 2 + 2 + read-write + + + S1RG3WP + desc S1RG3WP + 3 + 3 + read-write + + + S1RG4WP + desc S1RG4WP + 4 + 4 + read-write + + + S1RG5WP + desc S1RG5WP + 5 + 5 + read-write + + + S1RG6WP + desc S1RG6WP + 6 + 6 + read-write + + + S1RG7WP + desc S1RG7WP + 7 + 7 + read-write + + + S1RG8WP + desc S1RG8WP + 8 + 8 + read-write + + + S1RG9WP + desc S1RG9WP + 9 + 9 + read-write + + + S1RG10WP + desc S1RG10WP + 10 + 10 + read-write + + + S1RG11WP + desc S1RG11WP + 11 + 11 + read-write + + + S1RG12WP + desc S1RG12WP + 12 + 12 + read-write + + + S1RG13WP + desc S1RG13WP + 13 + 13 + read-write + + + S1RG14WP + desc S1RG14WP + 14 + 14 + read-write + + + S1RG15WP + desc S1RG15WP + 15 + 15 + read-write + + + + + S1RGRP + desc S1RGRP + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + S1RG0RP + desc S1RG0RP + 0 + 0 + read-write + + + S1RG1RP + desc S1RG1RP + 1 + 1 + read-write + + + S1RG2RP + desc S1RG2RP + 2 + 2 + read-write + + + S1RG3RP + desc S1RG3RP + 3 + 3 + read-write + + + S1RG4RP + desc S1RG4RP + 4 + 4 + read-write + + + S1RG5RP + desc S1RG5RP + 5 + 5 + read-write + + + S1RG6RP + desc S1RG6RP + 6 + 6 + read-write + + + S1RG7RP + desc S1RG7RP + 7 + 7 + read-write + + + S1RG8RP + desc S1RG8RP + 8 + 8 + read-write + + + S1RG9RP + desc S1RG9RP + 9 + 9 + read-write + + + S1RG10RP + desc S1RG10RP + 10 + 10 + read-write + + + S1RG11RP + desc S1RG11RP + 11 + 11 + read-write + + + S1RG12RP + desc S1RG12RP + 12 + 12 + read-write + + + S1RG13RP + desc S1RG13RP + 13 + 13 + read-write + + + S1RG14RP + desc S1RG14RP + 14 + 14 + read-write + + + S1RG15RP + desc S1RG15RP + 15 + 15 + read-write + + + + + S1CR + desc S1CR + 0x5C + 32 + read-write + 0x0 + 0x8F + + + SMPU1BRP + desc SMPU1BRP + 0 + 0 + read-write + + + SMPU1BWP + desc SMPU1BWP + 1 + 1 + read-write + + + SMPU1ACT + desc SMPU1ACT + 3 + 2 + read-write + + + SMPU1E + desc SMPU1E + 7 + 7 + read-write + + + + + S2RGE + desc S2RGE + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0E + desc S2RG0E + 0 + 0 + read-write + + + S2RG1E + desc S2RG1E + 1 + 1 + read-write + + + S2RG2E + desc S2RG2E + 2 + 2 + read-write + + + S2RG3E + desc S2RG3E + 3 + 3 + read-write + + + S2RG4E + desc S2RG4E + 4 + 4 + read-write + + + S2RG5E + desc S2RG5E + 5 + 5 + read-write + + + S2RG6E + desc S2RG6E + 6 + 6 + read-write + + + S2RG7E + desc S2RG7E + 7 + 7 + read-write + + + S2RG8E + desc S2RG8E + 8 + 8 + read-write + + + S2RG9E + desc S2RG9E + 9 + 9 + read-write + + + S2RG10E + desc S2RG10E + 10 + 10 + read-write + + + S2RG11E + desc S2RG11E + 11 + 11 + read-write + + + S2RG12E + desc S2RG12E + 12 + 12 + read-write + + + S2RG13E + desc S2RG13E + 13 + 13 + read-write + + + S2RG14E + desc S2RG14E + 14 + 14 + read-write + + + S2RG15E + desc S2RG15E + 15 + 15 + read-write + + + + + S2RGWP + desc S2RGWP + 0x64 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0WP + desc S2RG0WP + 0 + 0 + read-write + + + S2RG1WP + desc S2RG1WP + 1 + 1 + read-write + + + S2RG2WP + desc S2RG2WP + 2 + 2 + read-write + + + S2RG3WP + desc S2RG3WP + 3 + 3 + read-write + + + S2RG4WP + desc S2RG4WP + 4 + 4 + read-write + + + S2RG5WP + desc S2RG5WP + 5 + 5 + read-write + + + S2RG6WP + desc S2RG6WP + 6 + 6 + read-write + + + S2RG7WP + desc S2RG7WP + 7 + 7 + read-write + + + S2RG8WP + desc S2RG8WP + 8 + 8 + read-write + + + S2RG9WP + desc S2RG9WP + 9 + 9 + read-write + + + S2RG10WP + desc S2RG10WP + 10 + 10 + read-write + + + S2RG11WP + desc S2RG11WP + 11 + 11 + read-write + + + S2RG12WP + desc S2RG12WP + 12 + 12 + read-write + + + S2RG13WP + desc S2RG13WP + 13 + 13 + read-write + + + S2RG14WP + desc S2RG14WP + 14 + 14 + read-write + + + S2RG15WP + desc S2RG15WP + 15 + 15 + read-write + + + + + S2RGRP + desc S2RGRP + 0x68 + 32 + read-write + 0x0 + 0xFFFF + + + S2RG0RP + desc S2RG0RP + 0 + 0 + read-write + + + S2RG1RP + desc S2RG1RP + 1 + 1 + read-write + + + S2RG2RP + desc S2RG2RP + 2 + 2 + read-write + + + S2RG3RP + desc S2RG3RP + 3 + 3 + read-write + + + S2RG4RP + desc S2RG4RP + 4 + 4 + read-write + + + S2RG5RP + desc S2RG5RP + 5 + 5 + read-write + + + S2RG6RP + desc S2RG6RP + 6 + 6 + read-write + + + S2RG7RP + desc S2RG7RP + 7 + 7 + read-write + + + S2RG8RP + desc S2RG8RP + 8 + 8 + read-write + + + S2RG9RP + desc S2RG9RP + 9 + 9 + read-write + + + S2RG10RP + desc S2RG10RP + 10 + 10 + read-write + + + S2RG11RP + desc S2RG11RP + 11 + 11 + read-write + + + S2RG12RP + desc S2RG12RP + 12 + 12 + read-write + + + S2RG13RP + desc S2RG13RP + 13 + 13 + read-write + + + S2RG14RP + desc S2RG14RP + 14 + 14 + read-write + + + S2RG15RP + desc S2RG15RP + 15 + 15 + read-write + + + + + S2CR + desc S2CR + 0x6C + 32 + read-write + 0x0 + 0x8F + + + SMPU2BRP + desc SMPU2BRP + 0 + 0 + read-write + + + SMPU2BWP + desc SMPU2BWP + 1 + 1 + read-write + + + SMPU2ACT + desc SMPU2ACT + 3 + 2 + read-write + + + SMPU2E + desc SMPU2E + 7 + 7 + read-write + + + + + FRGE + desc FRGE + 0x70 + 32 + read-write + 0x0 + 0xFF + + + FRG0E + desc FRG0E + 0 + 0 + read-write + + + FRG1E + desc FRG1E + 1 + 1 + read-write + + + FRG2E + desc FRG2E + 2 + 2 + read-write + + + FRG3E + desc FRG3E + 3 + 3 + read-write + + + FRG4E + desc FRG4E + 4 + 4 + read-write + + + FRG5E + desc FRG5E + 5 + 5 + read-write + + + FRG6E + desc FRG6E + 6 + 6 + read-write + + + FRG7E + desc FRG7E + 7 + 7 + read-write + + + + + FRGWP + desc FRGWP + 0x74 + 32 + read-write + 0x0 + 0xFF + + + FRG0WP + desc FRG0WP + 0 + 0 + read-write + + + FRG1WP + desc FRG1WP + 1 + 1 + read-write + + + FRG2WP + desc FRG2WP + 2 + 2 + read-write + + + FRG3WP + desc FRG3WP + 3 + 3 + read-write + + + FRG4WP + desc FRG4WP + 4 + 4 + read-write + + + FRG5WP + desc FRG5WP + 5 + 5 + read-write + + + FRG6WP + desc FRG6WP + 6 + 6 + read-write + + + FRG7WP + desc FRG7WP + 7 + 7 + read-write + + + + + FRGRP + desc FRGRP + 0x78 + 32 + read-write + 0x0 + 0xFF + + + FRG0RP + desc FRG0RP + 0 + 0 + read-write + + + FRG1RP + desc FRG1RP + 1 + 1 + read-write + + + FRG2RP + desc FRG2RP + 2 + 2 + read-write + + + FRG3RP + desc FRG3RP + 3 + 3 + read-write + + + FRG4RP + desc FRG4RP + 4 + 4 + read-write + + + FRG5RP + desc FRG5RP + 5 + 5 + read-write + + + FRG6RP + desc FRG6RP + 6 + 6 + read-write + + + FRG7RP + desc FRG7RP + 7 + 7 + read-write + + + + + FCR + desc FCR + 0x7C + 32 + read-write + 0x0 + 0x8F + + + FMPUBRP + desc FMPUBRP + 0 + 0 + read-write + + + FMPUBWP + desc FMPUBWP + 1 + 1 + read-write + + + FMPUACT + desc FMPUACT + 3 + 2 + read-write + + + FMPUE + desc FMPUE + 7 + 7 + read-write + + + + + HRGE + desc HRGE + 0x80 + 32 + read-write + 0x0 + 0xFF + + + HRG0E + desc HRG0E + 0 + 0 + read-write + + + HRG1E + desc HRG1E + 1 + 1 + read-write + + + HRG2E + desc HRG2E + 2 + 2 + read-write + + + HRG3E + desc HRG3E + 3 + 3 + read-write + + + HRG4E + desc HRG4E + 4 + 4 + read-write + + + HRG5E + desc HRG5E + 5 + 5 + read-write + + + HRG6E + desc HRG6E + 6 + 6 + read-write + + + HRG7E + desc HRG7E + 7 + 7 + read-write + + + + + HRGWP + desc HRGWP + 0x84 + 32 + read-write + 0x0 + 0xFF + + + HRG0WP + desc HRG0WP + 0 + 0 + read-write + + + HRG1WP + desc HRG1WP + 1 + 1 + read-write + + + HRG2WP + desc HRG2WP + 2 + 2 + read-write + + + HRG3WP + desc HRG3WP + 3 + 3 + read-write + + + HRG4WP + desc HRG4WP + 4 + 4 + read-write + + + HRG5WP + desc HRG5WP + 5 + 5 + read-write + + + HRG6WP + desc HRG6WP + 6 + 6 + read-write + + + HRG7WP + desc HRG7WP + 7 + 7 + read-write + + + + + HRGRP + desc HRGRP + 0x88 + 32 + read-write + 0x0 + 0xFF + + + HRG0RP + desc HRG0RP + 0 + 0 + read-write + + + HRG1RP + desc HRG1RP + 1 + 1 + read-write + + + HRG2RP + desc HRG2RP + 2 + 2 + read-write + + + HRG3RP + desc HRG3RP + 3 + 3 + read-write + + + HRG4RP + desc HRG4RP + 4 + 4 + read-write + + + HRG5RP + desc HRG5RP + 5 + 5 + read-write + + + HRG6RP + desc HRG6RP + 6 + 6 + read-write + + + HRG7RP + desc HRG7RP + 7 + 7 + read-write + + + + + HCR + desc HCR + 0x8C + 32 + read-write + 0x0 + 0x8F + + + HMPUBRP + desc HMPUBRP + 0 + 0 + read-write + + + HMPUBWP + desc HMPUBWP + 1 + 1 + read-write + + + HMPUACT + desc HMPUACT + 3 + 2 + read-write + + + HMPUE + desc HMPUE + 7 + 7 + read-write + + + + + ERGE + desc ERGE + 0x90 + 32 + read-write + 0x0 + 0xFF + + + ERG0E + desc ERG0E + 0 + 0 + read-write + + + ERG1E + desc ERG1E + 1 + 1 + read-write + + + ERG2E + desc ERG2E + 2 + 2 + read-write + + + ERG3E + desc ERG3E + 3 + 3 + read-write + + + ERG4E + desc ERG4E + 4 + 4 + read-write + + + ERG5E + desc ERG5E + 5 + 5 + read-write + + + ERG6E + desc ERG6E + 6 + 6 + read-write + + + ERG7E + desc ERG7E + 7 + 7 + read-write + + + + + ERGWP + desc ERGWP + 0x94 + 32 + read-write + 0x0 + 0xFF + + + ERG0WP + desc ERG0WP + 0 + 0 + read-write + + + ERG1WP + desc ERG1WP + 1 + 1 + read-write + + + ERG2WP + desc ERG2WP + 2 + 2 + read-write + + + ERG3WP + desc ERG3WP + 3 + 3 + read-write + + + ERG4WP + desc ERG4WP + 4 + 4 + read-write + + + ERG5WP + desc ERG5WP + 5 + 5 + read-write + + + ERG6WP + desc ERG6WP + 6 + 6 + read-write + + + ERG7WP + desc ERG7WP + 7 + 7 + read-write + + + + + ERGRP + desc ERGRP + 0x98 + 32 + read-write + 0x0 + 0xFF + + + ERG0RP + desc ERG0RP + 0 + 0 + read-write + + + ERG1RP + desc ERG1RP + 1 + 1 + read-write + + + ERG2RP + desc ERG2RP + 2 + 2 + read-write + + + ERG3RP + desc ERG3RP + 3 + 3 + read-write + + + ERG4RP + desc ERG4RP + 4 + 4 + read-write + + + ERG5RP + desc ERG5RP + 5 + 5 + read-write + + + ERG6RP + desc ERG6RP + 6 + 6 + read-write + + + ERG7RP + desc ERG7RP + 7 + 7 + read-write + + + + + ECR + desc ECR + 0x9C + 32 + read-write + 0x0 + 0x8F + + + EMPUBRP + desc EMPUBRP + 0 + 0 + read-write + + + EMPUBWP + desc EMPUBWP + 1 + 1 + read-write + + + EMPUACT + desc EMPUACT + 3 + 2 + read-write + + + EMPUE + desc EMPUE + 7 + 7 + read-write + + + + + + + NFC + desc NFC + 0x88100000 + + 0x0 + 0x8180 + + + + DATR_BASE + desc DATR_BASE + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CMDR + desc CMDR + 0x8000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CMD + desc CMD + 7 + 0 + read-write + + + ARG + desc ARG + 31 + 8 + read-write + + + + + IDXR0 + desc IDXR0 + 0x8004 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IENR + desc IENR + 0x8030 + 32 + read-write + 0x0 + 0xFFD3 + + + ECCEUEN + desc ECCEUEN + 0 + 0 + read-write + + + ECCECEN + desc ECCECEN + 1 + 1 + read-write + + + ECCCEN + desc ECCCEN + 4 + 4 + read-write + + + ECCEEN + desc ECCEEN + 6 + 6 + read-write + + + ECCDIS + desc ECCDIS + 7 + 7 + read-write + + + RBEN + desc RBEN + 15 + 8 + read-write + + + + + ISTR + desc ISTR + 0x8034 + 32 + read-write + 0x0 + 0xFF53 + + + ECCEUST + desc ECCEUST + 0 + 0 + read-write + + + ECCECST + desc ECCECST + 1 + 1 + read-write + + + ECCCST + desc ECCCST + 4 + 4 + read-write + + + ECCEST + desc ECCEST + 6 + 6 + read-write + + + RBST + desc RBST + 15 + 8 + read-write + + + + + IRSR + desc IRSR + 0x8038 + 32 + read-write + 0x0 + 0xFF53 + + + ECCEURS + desc ECCEURS + 0 + 0 + read-write + + + ECCECRS + desc ECCECRS + 1 + 1 + read-write + + + ECCCRS + desc ECCCRS + 4 + 4 + read-write + + + ECCERS + desc ECCERS + 6 + 6 + read-write + + + RBRS + desc RBRS + 15 + 8 + read-write + + + + + IDXR1 + desc IDXR1 + 0x8048 + 32 + read-write + 0x0 + 0xFF + + + IDX1 + desc IDX1 + 7 + 0 + read-write + + + + + TMCR0 + desc TMCR0 + 0x804C + 32 + read-write + 0x3030202 + 0xFFFFFFFF + + + TS + desc TS + 7 + 0 + read-write + + + TWP + desc TWP + 15 + 8 + read-write + + + TRP + desc TRP + 23 + 16 + read-write + + + TH + desc TH + 31 + 24 + read-write + + + + + TMCR1 + desc TMCR1 + 0x8050 + 32 + read-write + 0x28080303 + 0xFFFFFFFF + + + TWH + desc TWH + 7 + 0 + read-write + + + TRH + desc TRH + 15 + 8 + read-write + + + TRR + desc TRR + 23 + 16 + read-write + + + TWB + desc TWB + 31 + 24 + read-write + + + + + BACR + desc BACR + 0x8054 + 32 + read-write + 0x2187 + 0xFF3FCF + + + SIZE + desc SIZE + 2 + 0 + read-write + + + B16BIT + desc B16BIT + 3 + 3 + read-write + + + BANK + desc BANK + 7 + 6 + read-write + + + PAGE + desc PAGE + 9 + 8 + read-write + + + WP + desc WP + 10 + 10 + read-write + + + ECCM + desc ECCM + 12 + 11 + read-write + + + RAC + desc RAC + 13 + 13 + read-write + + + SCS + desc SCS + 23 + 16 + read-write + + + + + TMCR2 + desc TMCR2 + 0x805C + 32 + read-write + 0x3050D03 + 0xFFFFFFFF + + + TCCS + desc TCCS + 7 + 0 + read-write + + + TWTR + desc TWTR + 15 + 8 + read-write + + + TRTW + desc TRTW + 23 + 16 + read-write + + + TADL + desc TADL + 31 + 24 + read-write + + + + + ECCR0 + desc ECCR0 + 0x8060 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR1 + desc ECCR1 + 0x8064 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR2 + desc ECCR2 + 0x8068 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR3 + desc ECCR3 + 0x806C + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR4 + desc ECCR4 + 0x8070 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR5 + desc ECCR5 + 0x8074 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECCR6 + desc ECCR6 + 0x8078 + 32 + read-only + 0x0 + 0x3FFF + + + ERRLOC + desc ERRLOC + 11 + 0 + read-only + + + SE + desc SE + 12 + 12 + read-only + + + ME + desc ME + 13 + 13 + read-only + + + + + ECC_STAT + desc ECC_STAT + 0x807C + 32 + read-only + 0x0 + 0xFFFF + + + ERRSEC + desc ERRSEC + 15 + 0 + read-only + + + + + ECC_SYND0_0 + desc ECC_SYND0_0 + 0x8080 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND0_1 + desc ECC_SYND0_1 + 0x8084 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND0_2 + desc ECC_SYND0_2 + 0x8088 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND0_3 + desc ECC_SYND0_3 + 0x808C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND1_0 + desc ECC_SYND1_0 + 0x8090 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND1_1 + desc ECC_SYND1_1 + 0x8094 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND1_2 + desc ECC_SYND1_2 + 0x8098 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND1_3 + desc ECC_SYND1_3 + 0x809C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND2_0 + desc ECC_SYND2_0 + 0x80A0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND2_1 + desc ECC_SYND2_1 + 0x80A4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND2_2 + desc ECC_SYND2_2 + 0x80A8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND2_3 + desc ECC_SYND2_3 + 0x80AC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND3_0 + desc ECC_SYND3_0 + 0x80B0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND3_1 + desc ECC_SYND3_1 + 0x80B4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND3_2 + desc ECC_SYND3_2 + 0x80B8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND3_3 + desc ECC_SYND3_3 + 0x80BC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND4_0 + desc ECC_SYND4_0 + 0x80C0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND4_1 + desc ECC_SYND4_1 + 0x80C4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND4_2 + desc ECC_SYND4_2 + 0x80C8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND4_3 + desc ECC_SYND4_3 + 0x80CC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND5_0 + desc ECC_SYND5_0 + 0x80D0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND5_1 + desc ECC_SYND5_1 + 0x80D4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND5_2 + desc ECC_SYND5_2 + 0x80D8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND5_3 + desc ECC_SYND5_3 + 0x80DC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND6_0 + desc ECC_SYND6_0 + 0x80E0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND6_1 + desc ECC_SYND6_1 + 0x80E4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + RESV + desc RESV + 31 + 31 + read-write + + + + + ECC_SYND6_2 + desc ECC_SYND6_2 + 0x80E8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND6_3 + desc ECC_SYND6_3 + 0x80EC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND7_0 + desc ECC_SYND7_0 + 0x80F0 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND7_1 + desc ECC_SYND7_1 + 0x80F4 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND7_2 + desc ECC_SYND7_2 + 0x80F8 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND7_3 + desc ECC_SYND7_3 + 0x80FC + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND8_0 + desc ECC_SYND8_0 + 0x8100 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND8_1 + desc ECC_SYND8_1 + 0x8104 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND8_2 + desc ECC_SYND8_2 + 0x8108 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND8_3 + desc ECC_SYND8_3 + 0x810C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND9_0 + desc ECC_SYND9_0 + 0x8110 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND9_1 + desc ECC_SYND9_1 + 0x8114 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND9_2 + desc ECC_SYND9_2 + 0x8118 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND9_3 + desc ECC_SYND9_3 + 0x811C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND10_0 + desc ECC_SYND10_0 + 0x8120 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND10_1 + desc ECC_SYND10_1 + 0x8124 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND10_2 + desc ECC_SYND10_2 + 0x8128 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND10_3 + desc ECC_SYND10_3 + 0x812C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND11_0 + desc ECC_SYND11_0 + 0x8130 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND11_1 + desc ECC_SYND11_1 + 0x8134 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND11_2 + desc ECC_SYND11_2 + 0x8138 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND11_3 + desc ECC_SYND11_3 + 0x813C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND12_0 + desc ECC_SYND12_0 + 0x8140 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND12_1 + desc ECC_SYND12_1 + 0x8144 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND12_2 + desc ECC_SYND12_2 + 0x8148 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND12_3 + desc ECC_SYND12_3 + 0x814C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND13_0 + desc ECC_SYND13_0 + 0x8150 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND13_1 + desc ECC_SYND13_1 + 0x8154 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND13_2 + desc ECC_SYND13_2 + 0x8158 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND13_3 + desc ECC_SYND13_3 + 0x815C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND14_0 + desc ECC_SYND14_0 + 0x8160 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND14_1 + desc ECC_SYND14_1 + 0x8164 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND14_2 + desc ECC_SYND14_2 + 0x8168 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND14_3 + desc ECC_SYND14_3 + 0x816C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + ECC_SYND15_0 + desc ECC_SYND15_0 + 0x8170 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S1 + desc S1 + 12 + 0 + read-only + + + S2 + desc S2 + 28 + 16 + read-only + + + + + ECC_SYND15_1 + desc ECC_SYND15_1 + 0x8174 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S3 + desc S3 + 12 + 0 + read-only + + + S4 + desc S4 + 28 + 16 + read-only + + + + + ECC_SYND15_2 + desc ECC_SYND15_2 + 0x8178 + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S5 + desc S5 + 12 + 0 + read-only + + + S6 + desc S6 + 28 + 16 + read-only + + + + + ECC_SYND15_3 + desc ECC_SYND15_3 + 0x817C + 32 + read-only + 0x0 + 0x1FFF1FFF + + + S7 + desc S7 + 12 + 0 + read-only + + + S8 + desc S8 + 28 + 16 + read-only + + + + + + + OTS + desc OTS + 0x40010600 + + 0x0 + 0x3A20C + + + + PDR1 + desc PDR1 + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + PDR2 + desc PDR2 + 0xF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + PDR3 + desc PDR3 + 0xF8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TSPD1 + desc TSPD1 + 15 + 0 + read-write + + + TSPD2 + desc TSPD2 + 31 + 16 + read-write + + + + + CTL + desc CTL + 0x3A200 + 16 + read-write + 0x0 + 0xF + + + OTSST + desc OTSST + 0 + 0 + read-write + + + OTSCK + desc OTSCK + 1 + 1 + read-write + + + OTSIE + desc OTSIE + 2 + 2 + read-write + + + TSSTP + desc TSSTP + 3 + 3 + read-write + + + + + DR1 + desc DR1 + 0x3A202 + 16 + read-write + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x3A204 + 16 + read-write + 0x0 + 0xFFFF + + + ECR + desc ECR + 0x3A206 + 16 + read-write + 0x0 + 0xFFFF + + + LPR + desc LPR + 0x3A208 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + TSOFS + desc TSOFS + 7 + 0 + read-only + + + TSSLP + desc TSSLP + 31 + 8 + read-only + + + + + + + PERIC + desc PERIC + 0x40055400 + + 0x0 + 0x2C + + + + USB_SYCTLREG + desc USB_SYCTLREG + 0x0 + 32 + read-write + 0x0 + 0x7070703 + + + USBFS_DFB + desc USBFS_DFB + 0 + 0 + read-write + + + USBFS_SOFEN + desc USBFS_SOFEN + 1 + 1 + read-write + + + USBHS_DFB + desc USBHS_DFB + 8 + 8 + read-write + + + USBHS_SOFEN + desc USBHS_SOFEN + 9 + 9 + read-write + + + USBHS_FSPHYE + desc USBHS_FSPHYE + 10 + 10 + read-write + + + USBFS_NFS + desc USBFS_NFS + 17 + 16 + read-write + + + USBFS_NFE + desc USBFS_NFE + 18 + 18 + read-write + + + USBHS_NFS + desc USBHS_NFS + 25 + 24 + read-write + + + USBHS_NFE + desc USBHS_NFE + 26 + 26 + read-write + + + + + SDIOC_SYCTLREG + desc SDIOC_SYCTLREG + 0x4 + 32 + read-write + 0x0 + 0xA + + + SELMMC1 + desc SELMMC1 + 1 + 1 + read-write + + + SELMMC2 + desc SELMMC2 + 3 + 3 + read-write + + + + + NFC_STCR + desc NFC_STCR + 0x8 + 32 + read-write + 0x0 + 0x1 + + + OPENP + desc OPENP + 0 + 0 + read-write + + + + + NFC_ENAR + desc NFC_ENAR + 0xC + 32 + read-write + 0x0 + 0x4 + + + NFCEN + desc NFCEN + 2 + 2 + read-write + + + + + SMC_ENAR + desc SMC_ENAR + 0xC + 32 + read-write + 0x0 + 0x2 + + + SMCEN + desc SMCEN + 1 + 1 + read-write + + + + + DMC_ENAR + desc DMC_ENAR + 0xC + 32 + read-write + 0x0 + 0x1 + + + DMCEN + desc DMCEN + 0 + 0 + read-write + + + + + USART1_NFC + desc USART1_NFC + 0x1C + 32 + read-write + 0x0 + 0x7 + + + USASRT1_NFS + desc USASRT1_NFS + 1 + 0 + read-write + + + USART1_NFE + desc USART1_NFE + 2 + 2 + read-write + + + + + NFC_STSR + desc NFC_STSR + 0x28 + 32 + read-only + 0x0 + 0x1FF + + + CHIP_BUSY + desc CHIP_BUSY + 7 + 0 + read-only + + + PECC + desc PECC + 8 + 8 + read-only + + + + + + + PWC + desc PWC + 0x40048000 + + 0x0 + 0xC400 + + + + FCG0 + desc FCG0 + 0x0 + 32 + read-write + 0xFFFFFA0E + 0xFFFFE4F1 + + + SRAMH + desc SRAMH + 0 + 0 + read-write + + + SRAM1 + desc SRAM1 + 4 + 4 + read-write + + + SRAM2 + desc SRAM2 + 5 + 5 + read-write + + + SRAM3 + desc SRAM3 + 6 + 6 + read-write + + + SRAM4 + desc SRAM4 + 7 + 7 + read-write + + + SRAMB + desc SRAMB + 10 + 10 + read-write + + + KEY + desc KEY + 13 + 13 + read-write + + + DMA1 + desc DMA1 + 14 + 14 + read-write + + + DMA2 + desc DMA2 + 15 + 15 + read-write + + + FCM + desc FCM + 16 + 16 + read-write + + + AOS + desc AOS + 17 + 17 + read-write + + + CTC + desc CTC + 18 + 18 + read-write + + + MAU + desc MAU + 19 + 19 + read-write + + + AES + desc AES + 20 + 20 + read-write + + + HASH + desc HASH + 21 + 21 + read-write + + + TRNG + desc TRNG + 22 + 22 + read-write + + + CRC + desc CRC + 23 + 23 + read-write + + + DCU1 + desc DCU1 + 24 + 24 + read-write + + + DCU2 + desc DCU2 + 25 + 25 + read-write + + + DCU3 + desc DCU3 + 26 + 26 + read-write + + + DCU4 + desc DCU4 + 27 + 27 + read-write + + + DCU5 + desc DCU5 + 28 + 28 + read-write + + + DCU6 + desc DCU6 + 29 + 29 + read-write + + + DCU7 + desc DCU7 + 30 + 30 + read-write + + + DCU8 + desc DCU8 + 31 + 31 + read-write + + + + + FCG1 + desc FCG1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFF + + + CAN1 + desc CAN1 + 0 + 0 + read-write + + + CAN2 + desc CAN2 + 1 + 1 + read-write + + + ETHMAC + desc ETHMAC + 2 + 2 + read-write + + + QSPI + desc QSPI + 3 + 3 + read-write + + + I2C1 + desc I2C1 + 4 + 4 + read-write + + + I2C2 + desc I2C2 + 5 + 5 + read-write + + + I2C3 + desc I2C3 + 6 + 6 + read-write + + + I2C4 + desc I2C4 + 7 + 7 + read-write + + + I2C5 + desc I2C5 + 8 + 8 + read-write + + + I2C6 + desc I2C6 + 9 + 9 + read-write + + + SDIOC1 + desc SDIOC1 + 10 + 10 + read-write + + + SDIOC2 + desc SDIOC2 + 11 + 11 + read-write + + + I2S1 + desc I2S1 + 12 + 12 + read-write + + + I2S2 + desc I2S2 + 13 + 13 + read-write + + + I2S3 + desc I2S3 + 14 + 14 + read-write + + + I2S4 + desc I2S4 + 15 + 15 + read-write + + + SPI1 + desc SPI1 + 16 + 16 + read-write + + + SPI2 + desc SPI2 + 17 + 17 + read-write + + + SPI3 + desc SPI3 + 18 + 18 + read-write + + + SPI4 + desc SPI4 + 19 + 19 + read-write + + + SPI5 + desc SPI5 + 20 + 20 + read-write + + + SPI6 + desc SPI6 + 21 + 21 + read-write + + + USBFS + desc USBFS + 22 + 22 + read-write + + + USBHS + desc USBHS + 23 + 23 + read-write + + + FMAC1 + desc FMAC1 + 24 + 24 + read-write + + + FMAC2 + desc FMAC2 + 25 + 25 + read-write + + + FMAC3 + desc FMAC3 + 26 + 26 + read-write + + + FMAC4 + desc FMAC4 + 27 + 27 + read-write + + + + + FCG2 + desc FCG2 + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFBFFF + + + TMR6_1 + desc TMR6_1 + 0 + 0 + read-write + + + TMR6_2 + desc TMR6_2 + 1 + 1 + read-write + + + TMR6_3 + desc TMR6_3 + 2 + 2 + read-write + + + TMR6_4 + desc TMR6_4 + 3 + 3 + read-write + + + TMR6_5 + desc TMR6_5 + 4 + 4 + read-write + + + TMR6_6 + desc TMR6_6 + 5 + 5 + read-write + + + TMR6_7 + desc TMR6_7 + 6 + 6 + read-write + + + TMR6_8 + desc TMR6_8 + 7 + 7 + read-write + + + TMR4_1 + desc TMR4_1 + 8 + 8 + read-write + + + TMR4_2 + desc TMR4_2 + 9 + 9 + read-write + + + TMR4_3 + desc TMR4_3 + 10 + 10 + read-write + + + HRPWM + desc HRPWM + 11 + 11 + read-write + + + TMR0_1 + desc TMR0_1 + 12 + 12 + read-write + + + TMR0_2 + desc TMR0_2 + 13 + 13 + read-write + + + EMB + desc EMB + 15 + 15 + read-write + + + TMR2_1 + desc TMR2_1 + 16 + 16 + read-write + + + TMR2_2 + desc TMR2_2 + 17 + 17 + read-write + + + TMR2_3 + desc TMR2_3 + 18 + 18 + read-write + + + TMR2_4 + desc TMR2_4 + 19 + 19 + read-write + + + TMRA_1 + desc TMRA_1 + 20 + 20 + read-write + + + TMRA_2 + desc TMRA_2 + 21 + 21 + read-write + + + TMRA_3 + desc TMRA_3 + 22 + 22 + read-write + + + TMRA_4 + desc TMRA_4 + 23 + 23 + read-write + + + TMRA_5 + desc TMRA_5 + 24 + 24 + read-write + + + TMRA_6 + desc TMRA_6 + 25 + 25 + read-write + + + TMRA_7 + desc TMRA_7 + 26 + 26 + read-write + + + TMRA_8 + desc TMRA_8 + 27 + 27 + read-write + + + TMRA_9 + desc TMRA_9 + 28 + 28 + read-write + + + TMRA_10 + desc TMRA_10 + 29 + 29 + read-write + + + TMRA_11 + desc TMRA_11 + 30 + 30 + read-write + + + TMRA_12 + desc TMRA_12 + 31 + 31 + read-write + + + + + FCG3 + desc FCG3 + 0xC + 32 + read-write + 0xFFFFFFFF + 0x3FF7933F + + + ADC1 + desc ADC1 + 0 + 0 + read-write + + + ADC2 + desc ADC2 + 1 + 1 + read-write + + + ADC3 + desc ADC3 + 2 + 2 + read-write + + + CMBIAS + desc CMBIAS + 3 + 3 + read-write + + + DAC1 + desc DAC1 + 4 + 4 + read-write + + + DAC2 + desc DAC2 + 5 + 5 + read-write + + + CMP1 + desc CMP1 + 8 + 8 + read-write + + + CMP2 + desc CMP2 + 9 + 9 + read-write + + + OTS + desc OTS + 12 + 12 + read-write + + + DVP + desc DVP + 15 + 15 + read-write + + + SMC + desc SMC + 16 + 16 + read-write + + + DMC + desc DMC + 17 + 17 + read-write + + + NFC + desc NFC + 18 + 18 + read-write + + + USART1 + desc USART1 + 20 + 20 + read-write + + + USART2 + desc USART2 + 21 + 21 + read-write + + + USART3 + desc USART3 + 22 + 22 + read-write + + + USART4 + desc USART4 + 23 + 23 + read-write + + + USART5 + desc USART5 + 24 + 24 + read-write + + + USART6 + desc USART6 + 25 + 25 + read-write + + + USART7 + desc USART7 + 26 + 26 + read-write + + + USART8 + desc USART8 + 27 + 27 + read-write + + + USART9 + desc USART9 + 28 + 28 + read-write + + + USART10 + desc USART10 + 29 + 29 + read-write + + + + + FCG0PC + desc FCG0PC + 0x10 + 32 + read-write + 0x0 + 0xFFFF0001 + + + PRT0 + desc PRT0 + 0 + 0 + read-write + + + FCG0PCWE + desc FCG0PCWE + 31 + 16 + write-only + + + + + VBATRSTR + desc VBATRSTR + 0x4430 + 8 + read-write + 0x0 + 0xFF + + + VBATCR + desc VBATCR + 0x4440 + 8 + read-write + 0x0 + 0x8F + + + VBTRSD + desc VBTRSD + 0 + 0 + read-write + + + RAMVALID + desc RAMVALID + 1 + 1 + read-write + + + RAMPDF + desc RAMPDF + 2 + 2 + read-write + + + VBATDIVMONE + desc VBATDIVMONE + 3 + 3 + read-write + + + CSDIS + desc CSDIS + 7 + 7 + read-write + + + + + WKTC0 + desc WKTC0 + 0x4450 + 8 + read-write + 0x0 + 0xFF + + + WKTMCMP + desc WKTMCMP + 7 + 0 + read-write + + + + + WKTC1 + desc WKTC1 + 0x4454 + 8 + read-write + 0x0 + 0xF + + + WKTMCMP + desc WKTMCMP + 3 + 0 + read-write + + + + + WKTC2 + desc WKTC2 + 0x4458 + 8 + read-write + 0x0 + 0xF0 + + + WKOVF + desc WKOVF + 4 + 4 + read-write + + + WKCKS + desc WKCKS + 6 + 5 + read-write + + + WKTCE + desc WKTCE + 7 + 7 + read-write + + + + + BKR0 + desc BKR0 + 0x4600 + 8 + read-write + 0x0 + 0xFF + + + BKR1 + desc BKR1 + 0x4604 + 8 + read-write + 0x0 + 0xFF + + + BKR2 + desc BKR2 + 0x4608 + 8 + read-write + 0x0 + 0xFF + + + BKR3 + desc BKR3 + 0x460C + 8 + read-write + 0x0 + 0xFF + + + BKR4 + desc BKR4 + 0x4610 + 8 + read-write + 0x0 + 0xFF + + + BKR5 + desc BKR5 + 0x4614 + 8 + read-write + 0x0 + 0xFF + + + BKR6 + desc BKR6 + 0x4618 + 8 + read-write + 0x0 + 0xFF + + + BKR7 + desc BKR7 + 0x461C + 8 + read-write + 0x0 + 0xFF + + + BKR8 + desc BKR8 + 0x4620 + 8 + read-write + 0x0 + 0xFF + + + BKR9 + desc BKR9 + 0x4624 + 8 + read-write + 0x0 + 0xFF + + + BKR10 + desc BKR10 + 0x4628 + 8 + read-write + 0x0 + 0xFF + + + BKR11 + desc BKR11 + 0x462C + 8 + read-write + 0x0 + 0xFF + + + BKR12 + desc BKR12 + 0x4630 + 8 + read-write + 0x0 + 0xFF + + + BKR13 + desc BKR13 + 0x4634 + 8 + read-write + 0x0 + 0xFF + + + BKR14 + desc BKR14 + 0x4638 + 8 + read-write + 0x0 + 0xFF + + + BKR15 + desc BKR15 + 0x463C + 8 + read-write + 0x0 + 0xFF + + + BKR16 + desc BKR16 + 0x4640 + 8 + read-write + 0x0 + 0xFF + + + BKR17 + desc BKR17 + 0x4644 + 8 + read-write + 0x0 + 0xFF + + + BKR18 + desc BKR18 + 0x4648 + 8 + read-write + 0x0 + 0xFF + + + BKR19 + desc BKR19 + 0x464C + 8 + read-write + 0x0 + 0xFF + + + BKR20 + desc BKR20 + 0x4650 + 8 + read-write + 0x0 + 0xFF + + + BKR21 + desc BKR21 + 0x4654 + 8 + read-write + 0x0 + 0xFF + + + BKR22 + desc BKR22 + 0x4658 + 8 + read-write + 0x0 + 0xFF + + + BKR23 + desc BKR23 + 0x465C + 8 + read-write + 0x0 + 0xFF + + + BKR24 + desc BKR24 + 0x4660 + 8 + read-write + 0x0 + 0xFF + + + BKR25 + desc BKR25 + 0x4664 + 8 + read-write + 0x0 + 0xFF + + + BKR26 + desc BKR26 + 0x4668 + 8 + read-write + 0x0 + 0xFF + + + BKR27 + desc BKR27 + 0x466C + 8 + read-write + 0x0 + 0xFF + + + BKR28 + desc BKR28 + 0x4670 + 8 + read-write + 0x0 + 0xFF + + + BKR29 + desc BKR29 + 0x4674 + 8 + read-write + 0x0 + 0xFF + + + BKR30 + desc BKR30 + 0x4678 + 8 + read-write + 0x0 + 0xFF + + + BKR31 + desc BKR31 + 0x467C + 8 + read-write + 0x0 + 0xFF + + + BKR32 + desc BKR32 + 0x4680 + 8 + read-write + 0x0 + 0xFF + + + BKR33 + desc BKR33 + 0x4684 + 8 + read-write + 0x0 + 0xFF + + + BKR34 + desc BKR34 + 0x4688 + 8 + read-write + 0x0 + 0xFF + + + BKR35 + desc BKR35 + 0x468C + 8 + read-write + 0x0 + 0xFF + + + BKR36 + desc BKR36 + 0x4690 + 8 + read-write + 0x0 + 0xFF + + + BKR37 + desc BKR37 + 0x4694 + 8 + read-write + 0x0 + 0xFF + + + BKR38 + desc BKR38 + 0x4698 + 8 + read-write + 0x0 + 0xFF + + + BKR39 + desc BKR39 + 0x469C + 8 + read-write + 0x0 + 0xFF + + + BKR40 + desc BKR40 + 0x46A0 + 8 + read-write + 0x0 + 0xFF + + + BKR41 + desc BKR41 + 0x46A4 + 8 + read-write + 0x0 + 0xFF + + + BKR42 + desc BKR42 + 0x46A8 + 8 + read-write + 0x0 + 0xFF + + + BKR43 + desc BKR43 + 0x46AC + 8 + read-write + 0x0 + 0xFF + + + BKR44 + desc BKR44 + 0x46B0 + 8 + read-write + 0x0 + 0xFF + + + BKR45 + desc BKR45 + 0x46B4 + 8 + read-write + 0x0 + 0xFF + + + BKR46 + desc BKR46 + 0x46B8 + 8 + read-write + 0x0 + 0xFF + + + BKR47 + desc BKR47 + 0x46BC + 8 + read-write + 0x0 + 0xFF + + + BKR48 + desc BKR48 + 0x46C0 + 8 + read-write + 0x0 + 0xFF + + + BKR49 + desc BKR49 + 0x46C4 + 8 + read-write + 0x0 + 0xFF + + + BKR50 + desc BKR50 + 0x46C8 + 8 + read-write + 0x0 + 0xFF + + + BKR51 + desc BKR51 + 0x46CC + 8 + read-write + 0x0 + 0xFF + + + BKR52 + desc BKR52 + 0x46D0 + 8 + read-write + 0x0 + 0xFF + + + BKR53 + desc BKR53 + 0x46D4 + 8 + read-write + 0x0 + 0xFF + + + BKR54 + desc BKR54 + 0x46D8 + 8 + read-write + 0x0 + 0xFF + + + BKR55 + desc BKR55 + 0x46DC + 8 + read-write + 0x0 + 0xFF + + + BKR56 + desc BKR56 + 0x46E0 + 8 + read-write + 0x0 + 0xFF + + + BKR57 + desc BKR57 + 0x46E4 + 8 + read-write + 0x0 + 0xFF + + + BKR58 + desc BKR58 + 0x46E8 + 8 + read-write + 0x0 + 0xFF + + + BKR59 + desc BKR59 + 0x46EC + 8 + read-write + 0x0 + 0xFF + + + BKR60 + desc BKR60 + 0x46F0 + 8 + read-write + 0x0 + 0xFF + + + BKR61 + desc BKR61 + 0x46F4 + 8 + read-write + 0x0 + 0xFF + + + BKR62 + desc BKR62 + 0x46F8 + 8 + read-write + 0x0 + 0xFF + + + BKR63 + desc BKR63 + 0x46FC + 8 + read-write + 0x0 + 0xFF + + + BKR64 + desc BKR64 + 0x4700 + 8 + read-write + 0x0 + 0xFF + + + BKR65 + desc BKR65 + 0x4704 + 8 + read-write + 0x0 + 0xFF + + + BKR66 + desc BKR66 + 0x4708 + 8 + read-write + 0x0 + 0xFF + + + BKR67 + desc BKR67 + 0x470C + 8 + read-write + 0x0 + 0xFF + + + BKR68 + desc BKR68 + 0x4710 + 8 + read-write + 0x0 + 0xFF + + + BKR69 + desc BKR69 + 0x4714 + 8 + read-write + 0x0 + 0xFF + + + BKR70 + desc BKR70 + 0x4718 + 8 + read-write + 0x0 + 0xFF + + + BKR71 + desc BKR71 + 0x471C + 8 + read-write + 0x0 + 0xFF + + + BKR72 + desc BKR72 + 0x4720 + 8 + read-write + 0x0 + 0xFF + + + BKR73 + desc BKR73 + 0x4724 + 8 + read-write + 0x0 + 0xFF + + + BKR74 + desc BKR74 + 0x4728 + 8 + read-write + 0x0 + 0xFF + + + BKR75 + desc BKR75 + 0x472C + 8 + read-write + 0x0 + 0xFF + + + BKR76 + desc BKR76 + 0x4730 + 8 + read-write + 0x0 + 0xFF + + + BKR77 + desc BKR77 + 0x4734 + 8 + read-write + 0x0 + 0xFF + + + BKR78 + desc BKR78 + 0x4738 + 8 + read-write + 0x0 + 0xFF + + + BKR79 + desc BKR79 + 0x473C + 8 + read-write + 0x0 + 0xFF + + + BKR80 + desc BKR80 + 0x4740 + 8 + read-write + 0x0 + 0xFF + + + BKR81 + desc BKR81 + 0x4744 + 8 + read-write + 0x0 + 0xFF + + + BKR82 + desc BKR82 + 0x4748 + 8 + read-write + 0x0 + 0xFF + + + BKR83 + desc BKR83 + 0x474C + 8 + read-write + 0x0 + 0xFF + + + BKR84 + desc BKR84 + 0x4750 + 8 + read-write + 0x0 + 0xFF + + + BKR85 + desc BKR85 + 0x4754 + 8 + read-write + 0x0 + 0xFF + + + BKR86 + desc BKR86 + 0x4758 + 8 + read-write + 0x0 + 0xFF + + + BKR87 + desc BKR87 + 0x475C + 8 + read-write + 0x0 + 0xFF + + + BKR88 + desc BKR88 + 0x4760 + 8 + read-write + 0x0 + 0xFF + + + BKR89 + desc BKR89 + 0x4764 + 8 + read-write + 0x0 + 0xFF + + + BKR90 + desc BKR90 + 0x4768 + 8 + read-write + 0x0 + 0xFF + + + BKR91 + desc BKR91 + 0x476C + 8 + read-write + 0x0 + 0xFF + + + BKR92 + desc BKR92 + 0x4770 + 8 + read-write + 0x0 + 0xFF + + + BKR93 + desc BKR93 + 0x4774 + 8 + read-write + 0x0 + 0xFF + + + BKR94 + desc BKR94 + 0x4778 + 8 + read-write + 0x0 + 0xFF + + + BKR95 + desc BKR95 + 0x477C + 8 + read-write + 0x0 + 0xFF + + + BKR96 + desc BKR96 + 0x4780 + 8 + read-write + 0x0 + 0xFF + + + BKR97 + desc BKR97 + 0x4784 + 8 + read-write + 0x0 + 0xFF + + + BKR98 + desc BKR98 + 0x4788 + 8 + read-write + 0x0 + 0xFF + + + BKR99 + desc BKR99 + 0x478C + 8 + read-write + 0x0 + 0xFF + + + BKR100 + desc BKR100 + 0x4790 + 8 + read-write + 0x0 + 0xFF + + + BKR101 + desc BKR101 + 0x4794 + 8 + read-write + 0x0 + 0xFF + + + BKR102 + desc BKR102 + 0x4798 + 8 + read-write + 0x0 + 0xFF + + + BKR103 + desc BKR103 + 0x479C + 8 + read-write + 0x0 + 0xFF + + + BKR104 + desc BKR104 + 0x47A0 + 8 + read-write + 0x0 + 0xFF + + + BKR105 + desc BKR105 + 0x47A4 + 8 + read-write + 0x0 + 0xFF + + + BKR106 + desc BKR106 + 0x47A8 + 8 + read-write + 0x0 + 0xFF + + + BKR107 + desc BKR107 + 0x47AC + 8 + read-write + 0x0 + 0xFF + + + BKR108 + desc BKR108 + 0x47B0 + 8 + read-write + 0x0 + 0xFF + + + BKR109 + desc BKR109 + 0x47B4 + 8 + read-write + 0x0 + 0xFF + + + BKR110 + desc BKR110 + 0x47B8 + 8 + read-write + 0x0 + 0xFF + + + BKR111 + desc BKR111 + 0x47BC + 8 + read-write + 0x0 + 0xFF + + + BKR112 + desc BKR112 + 0x47C0 + 8 + read-write + 0x0 + 0xFF + + + BKR113 + desc BKR113 + 0x47C4 + 8 + read-write + 0x0 + 0xFF + + + BKR114 + desc BKR114 + 0x47C8 + 8 + read-write + 0x0 + 0xFF + + + BKR115 + desc BKR115 + 0x47CC + 8 + read-write + 0x0 + 0xFF + + + BKR116 + desc BKR116 + 0x47D0 + 8 + read-write + 0x0 + 0xFF + + + BKR117 + desc BKR117 + 0x47D4 + 8 + read-write + 0x0 + 0xFF + + + BKR118 + desc BKR118 + 0x47D8 + 8 + read-write + 0x0 + 0xFF + + + BKR119 + desc BKR119 + 0x47DC + 8 + read-write + 0x0 + 0xFF + + + BKR120 + desc BKR120 + 0x47E0 + 8 + read-write + 0x0 + 0xFF + + + BKR121 + desc BKR121 + 0x47E4 + 8 + read-write + 0x0 + 0xFF + + + BKR122 + desc BKR122 + 0x47E8 + 8 + read-write + 0x0 + 0xFF + + + BKR123 + desc BKR123 + 0x47EC + 8 + read-write + 0x0 + 0xFF + + + BKR124 + desc BKR124 + 0x47F0 + 8 + read-write + 0x0 + 0xFF + + + BKR125 + desc BKR125 + 0x47F4 + 8 + read-write + 0x0 + 0xFF + + + BKR126 + desc BKR126 + 0x47F8 + 8 + read-write + 0x0 + 0xFF + + + BKR127 + desc BKR127 + 0x47FC + 8 + read-write + 0x0 + 0xFF + + + PWRC0 + desc PWRC0 + 0x4C00 + 8 + read-write + 0x0 + 0xBB + + + PDMDS + desc PDMDS + 1 + 0 + read-write + + + IORTN + desc IORTN + 5 + 4 + read-write + + + PWDN + desc PWDN + 7 + 7 + read-write + + + + + PWRC1 + desc PWRC1 + 0x4C04 + 8 + read-write + 0x0 + 0xCF + + + VPLLSD + desc VPLLSD + 1 + 0 + read-write + + + VHRCSD + desc VHRCSD + 2 + 2 + read-write + + + PDTS + desc PDTS + 3 + 3 + read-write + + + STPDAS + desc STPDAS + 7 + 6 + read-write + + + + + PWRC2 + desc PWRC2 + 0x4C08 + 8 + read-write + 0xFF + 0x3F + + + DDAS + desc DDAS + 3 + 0 + read-write + + + DVS + desc DVS + 5 + 4 + read-write + + + + + PWRC3 + desc PWRC3 + 0x4C0C + 8 + read-write + 0xFF + 0xFF + + + DDAS + desc DDAS + 7 + 0 + read-write + + + + + PWRC4 + desc PWRC4 + 0x4C10 + 8 + read-write + 0x0 + 0xD3 + + + VBATREFSEL + desc VBATREFSEL + 0 + 0 + read-write + + + VBATME + desc VBATME + 1 + 1 + read-write + + + VBATMON + desc VBATMON + 4 + 4 + read-write + + + ADBUFS + desc ADBUFS + 6 + 6 + read-write + + + ADBUFE + desc ADBUFE + 7 + 7 + read-write + + + + + PVDCR0 + desc PVDCR0 + 0x4C14 + 8 + read-write + 0x0 + 0x61 + + + EXVCCINEN + desc EXVCCINEN + 0 + 0 + read-write + + + PVD1EN + desc PVD1EN + 5 + 5 + read-write + + + PVD2EN + desc PVD2EN + 6 + 6 + read-write + + + + + PVDCR1 + desc PVDCR1 + 0x4C18 + 8 + read-write + 0x0 + 0x77 + + + PVD1IRE + desc PVD1IRE + 0 + 0 + read-write + + + PVD1IRS + desc PVD1IRS + 1 + 1 + read-write + + + PVD1CMPOE + desc PVD1CMPOE + 2 + 2 + read-write + + + PVD2IRE + desc PVD2IRE + 4 + 4 + read-write + + + PVD2IRS + desc PVD2IRS + 5 + 5 + read-write + + + PVD2CMPOE + desc PVD2CMPOE + 6 + 6 + read-write + + + + + PVDFCR + desc PVDFCR + 0x4C1C + 8 + read-write + 0x11 + 0x77 + + + PVD1NFDIS + desc PVD1NFDIS + 0 + 0 + read-write + + + PVD1NFCKS + desc PVD1NFCKS + 2 + 1 + read-write + + + PVD2NFDIS + desc PVD2NFDIS + 4 + 4 + read-write + + + PVD2NFCKS + desc PVD2NFCKS + 6 + 5 + read-write + + + + + PVDLCR + desc PVDLCR + 0x4C20 + 8 + read-write + 0x0 + 0x77 + + + PVD1LVL + desc PVD1LVL + 2 + 0 + read-write + + + PVD2LVL + desc PVD2LVL + 6 + 4 + read-write + + + + + PDWKE0 + desc PDWKE0 + 0x4C28 + 8 + read-write + 0x0 + 0xFF + + + WKE00 + desc WKE00 + 0 + 0 + read-write + + + WKE01 + desc WKE01 + 1 + 1 + read-write + + + WKE02 + desc WKE02 + 2 + 2 + read-write + + + WKE03 + desc WKE03 + 3 + 3 + read-write + + + WKE10 + desc WKE10 + 4 + 4 + read-write + + + WKE11 + desc WKE11 + 5 + 5 + read-write + + + WKE12 + desc WKE12 + 6 + 6 + read-write + + + WKE13 + desc WKE13 + 7 + 7 + read-write + + + + + PDWKE1 + desc PDWKE1 + 0x4C2C + 8 + read-write + 0x0 + 0xFF + + + WKE20 + desc WKE20 + 0 + 0 + read-write + + + WKE21 + desc WKE21 + 1 + 1 + read-write + + + WKE22 + desc WKE22 + 2 + 2 + read-write + + + WKE23 + desc WKE23 + 3 + 3 + read-write + + + WKE30 + desc WKE30 + 4 + 4 + read-write + + + WKE31 + desc WKE31 + 5 + 5 + read-write + + + WKE32 + desc WKE32 + 6 + 6 + read-write + + + WKE33 + desc WKE33 + 7 + 7 + read-write + + + + + PDWKE2 + desc PDWKE2 + 0x4C30 + 8 + read-write + 0x0 + 0xF3 + + + VD1WKE + desc VD1WKE + 0 + 0 + read-write + + + VD2WKE + desc VD2WKE + 1 + 1 + read-write + + + RTCPRDWKE + desc RTCPRDWKE + 4 + 4 + read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0x4C34 + 8 + read-write + 0x0 + 0x3F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0x4C38 + 8 + read-write + 0x0 + 0x3F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0x4C3C + 8 + read-write + 0x0 + 0xF8 + + + RXD0WKF + desc RXD0WKF + 3 + 3 + read-write + + + RTCPRDWKF + desc RTCPRDWKF + 4 + 4 + read-write + + + RTCALMWKF + desc RTCALMWKF + 5 + 5 + read-write + + + WKTMWKF + desc WKTMWKF + 7 + 7 + read-write + + + + + RAMPC0 + desc RAMPC0 + 0x4CE0 + 32 + read-write + 0x0 + 0x7FF + + + RAMPDC0 + desc RAMPDC0 + 0 + 0 + read-write + + + RAMPDC1 + desc RAMPDC1 + 1 + 1 + read-write + + + RAMPDC2 + desc RAMPDC2 + 2 + 2 + read-write + + + RAMPDC3 + desc RAMPDC3 + 3 + 3 + read-write + + + RAMPDC4 + desc RAMPDC4 + 4 + 4 + read-write + + + RAMPDC5 + desc RAMPDC5 + 5 + 5 + read-write + + + RAMPDC6 + desc RAMPDC6 + 6 + 6 + read-write + + + RAMPDC7 + desc RAMPDC7 + 7 + 7 + read-write + + + RAMPDC8 + desc RAMPDC8 + 8 + 8 + read-write + + + RAMPDC9 + desc RAMPDC9 + 9 + 9 + read-write + + + RAMPDC10 + desc RAMPDC10 + 10 + 10 + read-write + + + + + RAMOPM + desc RAMOPM + 0x4CE4 + 16 + read-write + 0x8043 + 0xFFFF + + + PRAMLPC + desc PRAMLPC + 0x4CE8 + 32 + read-write + 0x0 + 0x3FF + + + PRAMPDC0 + desc PRAMPDC0 + 0 + 0 + read-write + + + PRAMPDC1 + desc PRAMPDC1 + 1 + 1 + read-write + + + PRAMPDC2 + desc PRAMPDC2 + 2 + 2 + read-write + + + PRAMPDC3 + desc PRAMPDC3 + 3 + 3 + read-write + + + PRAMPDC4 + desc PRAMPDC4 + 4 + 4 + read-write + + + PRAMPDC5 + desc PRAMPDC5 + 5 + 5 + read-write + + + PRAMPDC6 + desc PRAMPDC6 + 6 + 6 + read-write + + + PRAMPDC7 + desc PRAMPDC7 + 7 + 7 + read-write + + + PRAMPDC8 + desc PRAMPDC8 + 8 + 8 + read-write + + + PRAMPDC9 + desc PRAMPDC9 + 9 + 9 + read-write + + + + + PVDICR + desc PVDICR + 0x4CF0 + 8 + read-write + 0x0 + 0x77 + + + PVD1NMIS + desc PVD1NMIS + 0 + 0 + read-write + + + PVD1EDGS + desc PVD1EDGS + 2 + 1 + read-write + + + PVD2NMIS + desc PVD2NMIS + 4 + 4 + read-write + + + PVD2EDGS + desc PVD2EDGS + 6 + 5 + read-write + + + + + PVDDSR + desc PVDDSR + 0x4CF4 + 8 + read-write + 0x11 + 0x33 + + + PVD1MON + desc PVD1MON + 0 + 0 + read-write + + + PVD1DETFLG + desc PVD1DETFLG + 1 + 1 + read-write + + + PVD2MON + desc PVD2MON + 4 + 4 + read-write + + + PVD2DETFLG + desc PVD2DETFLG + 5 + 5 + read-write + + + + + STPMCR + desc STPMCR + 0xC00C + 16 + read-write + 0x0 + 0xC003 + + + FLNWT + desc FLNWT + 0 + 0 + read-write + + + CKSMRC + desc CKSMRC + 1 + 1 + read-write + + + EXBUSOE + desc EXBUSOE + 14 + 14 + read-write + + + STOP + desc STOP + 15 + 15 + read-write + + + + + FPRC + desc FPRC + 0xC3FE + 16 + read-write + 0x0 + 0xFF0F + + + FPRCB0 + desc FPRCB0 + 0 + 0 + read-write + + + FPRCB1 + desc FPRCB1 + 1 + 1 + read-write + + + FPRCB2 + desc FPRCB2 + 2 + 2 + read-write + + + FPRCB3 + desc FPRCB3 + 3 + 3 + read-write + + + FPRCWE + desc FPRCWE + 15 + 8 + read-write + + + + + + + QSPI + desc QSPI + 0x9C000000 + + 0x0 + 0x808 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x3F0000 + 0x3F3FFF + + + MDSEL + desc MDSEL + 2 + 0 + read-write + + + PFE + desc PFE + 3 + 3 + read-write + + + PFSAE + desc PFSAE + 4 + 4 + read-write + + + DCOME + desc DCOME + 5 + 5 + read-write + + + XIPE + desc XIPE + 6 + 6 + read-write + + + SPIMD3 + desc SPIMD3 + 7 + 7 + read-write + + + IPRSL + desc IPRSL + 9 + 8 + read-write + + + APRSL + desc APRSL + 11 + 10 + read-write + + + DPRSL + desc DPRSL + 13 + 12 + read-write + + + DIV + desc DIV + 21 + 16 + read-write + + + + + CSCR + desc CSCR + 0x4 + 32 + read-write + 0xF + 0x3F + + + SSHW + desc SSHW + 3 + 0 + read-write + + + SSNW + desc SSNW + 5 + 4 + read-write + + + + + FCR + desc FCR + 0x8 + 32 + read-write + 0x80B3 + 0x8F77 + + + AWSL + desc AWSL + 1 + 0 + read-write + + + FOUR_BIC + desc FOUR_BIC + 2 + 2 + read-write + + + SSNHD + desc SSNHD + 4 + 4 + read-write + + + SSNLD + desc SSNLD + 5 + 5 + read-write + + + WPOL + desc WPOL + 6 + 6 + read-write + + + DMCYCN + desc DMCYCN + 11 + 8 + read-write + + + DUTY + desc DUTY + 15 + 15 + read-write + + + + + SR + desc SR + 0xC + 32 + read-write + 0x8000 + 0xDFC1 + + + BUSY + desc BUSY + 0 + 0 + read-write + + + XIPF + desc XIPF + 6 + 6 + read-write + + + RAER + desc RAER + 7 + 7 + read-write + + + PFNUM + desc PFNUM + 12 + 8 + read-write + + + PFFUL + desc PFFUL + 14 + 14 + read-write + + + PFAN + desc PFAN + 15 + 15 + read-write + + + + + DCOM + desc DCOM + 0x10 + 32 + read-write + 0x0 + 0xFF + + + DCOM + desc DCOM + 7 + 0 + read-write + + + + + CCMD + desc CCMD + 0x14 + 32 + read-write + 0x0 + 0xFF + + + RIC + desc RIC + 7 + 0 + read-write + + + + + XCMD + desc XCMD + 0x18 + 32 + read-write + 0xFF + 0xFF + + + XIPMC + desc XIPMC + 7 + 0 + read-write + + + + + SR2 + desc SR2 + 0x24 + 32 + write-only + 0x0 + 0x80 + + + RAERCLR + desc RAERCLR + 7 + 7 + write-only + + + + + EXAR + desc EXAR + 0x804 + 32 + read-write + 0x0 + 0xFC000000 + + + EXADR + desc EXADR + 31 + 26 + read-write + + + + + + + RMU + desc RMU + 0x4004CC00 + + 0x0 + 0x100 + + + + PRSTCR0 + desc PRSTCR0 + 0xF8 + 8 + read-write + 0x40 + 0x20 + + + LKUPREN + desc LKUPREN + 5 + 5 + read-write + + + + + RSTF0 + desc RSTF0 + 0xFC + 32 + read-write + 0x2 + 0xC0007FFF + + + PORF + desc PORF + 0 + 0 + read-write + + + PINRF + desc PINRF + 1 + 1 + read-write + + + BORF + desc BORF + 2 + 2 + read-write + + + PVD1RF + desc PVD1RF + 3 + 3 + read-write + + + PVD2RF + desc PVD2RF + 4 + 4 + read-write + + + WDRF + desc WDRF + 5 + 5 + read-write + + + SWDRF + desc SWDRF + 6 + 6 + read-write + + + PDRF + desc PDRF + 7 + 7 + read-write + + + SWRF + desc SWRF + 8 + 8 + read-write + + + MPUERF + desc MPUERF + 9 + 9 + read-write + + + RAPERF + desc RAPERF + 10 + 10 + read-write + + + RAECRF + desc RAECRF + 11 + 11 + read-write + + + CKFERF + desc CKFERF + 12 + 12 + read-write + + + XTALERF + desc XTALERF + 13 + 13 + read-write + + + LKUPRF + desc LKUPRF + 14 + 14 + read-write + + + MULTIRF + desc MULTIRF + 30 + 30 + read-write + + + CLRF + desc CLRF + 31 + 31 + read-write + + + + + + + RTC + desc RTC + 0x4004C000 + + 0x0 + 0x60 + + + + CR0 + desc CR0 + 0x0 + 8 + read-write + 0x0 + 0x1 + + + RESET + desc RESET + 0 + 0 + read-write + + + + + CR1 + desc CR1 + 0x4 + 8 + read-write + 0x0 + 0xEF + + + PRDS + desc PRDS + 2 + 0 + read-write + + + AMPM + desc AMPM + 3 + 3 + read-write + + + ONEHZOE + desc ONEHZOE + 5 + 5 + read-write + + + ONEHZSEL + desc ONEHZSEL + 6 + 6 + read-write + + + START + desc START + 7 + 7 + read-write + + + + + CR2 + desc CR2 + 0x8 + 8 + read-write + 0x0 + 0xEF + + + RWREQ + desc RWREQ + 0 + 0 + read-write + + + RWEN + desc RWEN + 1 + 1 + read-write + + + PRDF + desc PRDF + 2 + 2 + read-write + + + ALMF + desc ALMF + 3 + 3 + read-write + + + PRDIE + desc PRDIE + 5 + 5 + read-write + + + ALMIE + desc ALMIE + 6 + 6 + read-write + + + ALME + desc ALME + 7 + 7 + read-write + + + + + CR3 + desc CR3 + 0xC + 8 + read-write + 0x0 + 0x90 + + + LRCEN + desc LRCEN + 4 + 4 + read-write + + + RCKSEL + desc RCKSEL + 7 + 7 + read-write + + + + + SEC + desc SEC + 0x10 + 8 + read-write + 0x0 + 0x7F + + + SECU + desc SECU + 3 + 0 + read-write + + + SECD + desc SECD + 6 + 4 + read-write + + + + + MIN + desc MIN + 0x14 + 8 + read-write + 0x0 + 0x7F + + + MINU + desc MINU + 3 + 0 + read-write + + + MIND + desc MIND + 6 + 4 + read-write + + + + + HOUR + desc HOUR + 0x18 + 8 + read-write + 0x12 + 0x3F + + + HOURU + desc HOURU + 3 + 0 + read-write + + + HOURD + desc HOURD + 5 + 4 + read-write + + + + + WEEK + desc WEEK + 0x1C + 8 + read-write + 0x0 + 0x7 + + + WEEK + desc WEEK + 2 + 0 + read-write + + + + + DAY + desc DAY + 0x20 + 8 + read-write + 0x0 + 0x3F + + + DAYU + desc DAYU + 3 + 0 + read-write + + + DAYD + desc DAYD + 5 + 4 + read-write + + + + + MON + desc MON + 0x24 + 8 + read-write + 0x0 + 0x1F + + + MON + desc MON + 4 + 0 + read-write + + + + + YEAR + desc YEAR + 0x28 + 8 + read-write + 0x0 + 0xFF + + + YEARU + desc YEARU + 3 + 0 + read-write + + + YEARD + desc YEARD + 7 + 4 + read-write + + + + + ALMMIN + desc ALMMIN + 0x2C + 8 + read-write + 0x12 + 0x7F + + + ALMMINU + desc ALMMINU + 3 + 0 + read-write + + + ALMMIND + desc ALMMIND + 6 + 4 + read-write + + + + + ALMHOUR + desc ALMHOUR + 0x30 + 8 + read-write + 0x0 + 0x3F + + + ALMHOURU + desc ALMHOURU + 3 + 0 + read-write + + + ALMHOURD + desc ALMHOURD + 5 + 4 + read-write + + + + + ALMWEEK + desc ALMWEEK + 0x34 + 8 + read-write + 0x0 + 0x7F + + + ALMWEEK + desc ALMWEEK + 6 + 0 + read-write + + + + + ERRCRH + desc ERRCRH + 0x38 + 8 + read-write + 0x0 + 0x81 + + + COMP8 + desc COMP8 + 0 + 0 + read-write + + + COMPEN + desc COMPEN + 7 + 7 + read-write + + + + + ERRCRL + desc ERRCRL + 0x3C + 8 + read-write + 0x0 + 0xFF + + + COMP + desc COMP + 7 + 0 + read-write + + + + + TPCR0 + desc TPCR0 + 0x40 + 8 + read-write + 0x0 + 0xFF + + + TPCT0 + desc TPCT0 + 1 + 0 + read-write + + + TPNF0 + desc TPNF0 + 3 + 2 + read-write + + + TPRSTE0 + desc TPRSTE0 + 4 + 4 + read-write + + + TPIE0 + desc TPIE0 + 5 + 5 + read-write + + + TSTPE0 + desc TSTPE0 + 6 + 6 + read-write + + + TPEN0 + desc TPEN0 + 7 + 7 + read-write + + + + + TPCR1 + desc TPCR1 + 0x44 + 8 + read-write + 0x0 + 0xFF + + + TPCT1 + desc TPCT1 + 1 + 0 + read-write + + + TPNF1 + desc TPNF1 + 3 + 2 + read-write + + + TPRSTE1 + desc TPRSTE1 + 4 + 4 + read-write + + + TPIE1 + desc TPIE1 + 5 + 5 + read-write + + + TSTPE1 + desc TSTPE1 + 6 + 6 + read-write + + + TPEN1 + desc TPEN1 + 7 + 7 + read-write + + + + + TPSR + desc TPSR + 0x48 + 8 + read-write + 0x0 + 0x7 + + + TPF0 + desc TPF0 + 0 + 0 + read-write + + + TPF1 + desc TPF1 + 1 + 1 + read-write + + + TPOVF + desc TPOVF + 2 + 2 + read-write + + + + + SECTP + desc SECTP + 0x4C + 8 + read-write + 0x0 + 0x7F + + + SECTPU + desc SECTPU + 3 + 0 + read-write + + + SECTPD + desc SECTPD + 6 + 4 + read-write + + + + + MINTP + desc MINTP + 0x50 + 8 + read-write + 0x0 + 0x7F + + + MINTPU + desc MINTPU + 3 + 0 + read-write + + + MINTPD + desc MINTPD + 6 + 4 + read-write + + + + + HOURTP + desc HOURTP + 0x54 + 8 + read-write + 0x0 + 0x3F + + + HOURTPU + desc HOURTPU + 3 + 0 + read-write + + + HOURTPD + desc HOURTPD + 5 + 4 + read-write + + + + + DAYTP + desc DAYTP + 0x58 + 8 + read-write + 0x0 + 0x3F + + + DAYTPU + desc DAYTPU + 3 + 0 + read-write + + + DAYTPD + desc DAYTPD + 5 + 4 + read-write + + + + + MONTP + desc MONTP + 0x5C + 8 + read-write + 0x0 + 0x1F + + + MONTP + desc MONTP + 4 + 0 + read-write + + + + + + + SDIOC1 + desc SDIOC + 0x40070000 + + 0x0 + 0x54 + + + + BLKSIZE + desc BLKSIZE + 0x4 + 16 + read-write + 0x0 + 0xFFF + + + TBS + desc TBS + 11 + 0 + read-write + + + + + BLKCNT + desc BLKCNT + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + ARG0 + desc ARG0 + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + ARG1 + desc ARG1 + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + TRANSMODE + desc TRANSMODE + 0xC + 16 + read-write + 0x0 + 0x3E + + + BCE + desc BCE + 1 + 1 + read-write + + + ATCEN + desc ATCEN + 3 + 2 + read-write + + + DDIR + desc DDIR + 4 + 4 + read-write + + + MULB + desc MULB + 5 + 5 + read-write + + + + + CMD + desc CMD + 0xE + 16 + read-write + 0x0 + 0x3FFB + + + RESTYP + desc RESTYP + 1 + 0 + read-write + + + CCE + desc CCE + 3 + 3 + read-write + + + ICE + desc ICE + 4 + 4 + read-write + + + DAT + desc DAT + 5 + 5 + read-write + + + TYP + desc TYP + 7 + 6 + read-write + + + IDX + desc IDX + 13 + 8 + read-write + + + + + RESP0 + desc RESP0 + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + RESP1 + desc RESP1 + 0x12 + 16 + read-only + 0x0 + 0xFFFF + + + RESP2 + desc RESP2 + 0x14 + 16 + read-only + 0x0 + 0xFFFF + + + RESP3 + desc RESP3 + 0x16 + 16 + read-only + 0x0 + 0xFFFF + + + RESP4 + desc RESP4 + 0x18 + 16 + read-only + 0x0 + 0xFFFF + + + RESP5 + desc RESP5 + 0x1A + 16 + read-only + 0x0 + 0xFFFF + + + RESP6 + desc RESP6 + 0x1C + 16 + read-only + 0x0 + 0xFFFF + + + RESP7 + desc RESP7 + 0x1E + 16 + read-only + 0x0 + 0xFFFF + + + BUF0 + desc BUF0 + 0x20 + 16 + read-write + 0x0 + 0xFFFF + + + BUF1 + desc BUF1 + 0x22 + 16 + read-write + 0x0 + 0xFFFF + + + PSTAT + desc PSTAT + 0x24 + 32 + read-only + 0x0 + 0x1FF0F07 + + + CIC + desc CIC + 0 + 0 + read-only + + + CID + desc CID + 1 + 1 + read-only + + + DA + desc DA + 2 + 2 + read-only + + + WTA + desc WTA + 8 + 8 + read-only + + + RTA + desc RTA + 9 + 9 + read-only + + + BWE + desc BWE + 10 + 10 + read-only + + + BRE + desc BRE + 11 + 11 + read-only + + + CIN + desc CIN + 16 + 16 + read-only + + + CSS + desc CSS + 17 + 17 + read-only + + + CDL + desc CDL + 18 + 18 + read-only + + + WPL + desc WPL + 19 + 19 + read-only + + + DATL + desc DATL + 23 + 20 + read-only + + + CMDL + desc CMDL + 24 + 24 + read-only + + + + + HOSTCON + desc HOSTCON + 0x28 + 8 + read-write + 0x0 + 0xE6 + + + DW + desc DW + 1 + 1 + read-write + + + HSEN + desc HSEN + 2 + 2 + read-write + + + EXDW + desc EXDW + 5 + 5 + read-write + + + CDTL + desc CDTL + 6 + 6 + read-write + + + CDSS + desc CDSS + 7 + 7 + read-write + + + + + PWRCON + desc PWRCON + 0x29 + 8 + read-write + 0x0 + 0x1 + + + PWON + desc PWON + 0 + 0 + read-write + + + + + BLKGPCON + desc BLKGPCON + 0x2A + 8 + read-write + 0x0 + 0xF + + + SABGR + desc SABGR + 0 + 0 + read-write + + + CR + desc CR + 1 + 1 + read-write + + + RWC + desc RWC + 2 + 2 + read-write + + + IABG + desc IABG + 3 + 3 + read-write + + + + + CLKCON + desc CLKCON + 0x2C + 16 + read-write + 0x2 + 0xFF05 + + + ICE + desc ICE + 0 + 0 + read-write + + + CE + desc CE + 2 + 2 + read-write + + + FS + desc FS + 15 + 8 + read-write + + + + + TOUTCON + desc TOUTCON + 0x2E + 8 + read-write + 0x0 + 0xF + + + DTO + desc DTO + 3 + 0 + read-write + + + + + SFTRST + desc SFTRST + 0x2F + 8 + read-write + 0x0 + 0x7 + + + RSTA + desc RSTA + 0 + 0 + read-write + + + RSTC + desc RSTC + 1 + 1 + read-write + + + RSTD + desc RSTD + 2 + 2 + read-write + + + + + NORINTST + desc NORINTST + 0x30 + 16 + read-write + 0x0 + 0x81F7 + + + CC + desc CC + 0 + 0 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + BGE + desc BGE + 2 + 2 + read-write + + + BWR + desc BWR + 4 + 4 + read-write + + + BRR + desc BRR + 5 + 5 + read-write + + + CIST + desc CIST + 6 + 6 + read-write + + + CRM + desc CRM + 7 + 7 + read-write + + + CINT + desc CINT + 8 + 8 + read-only + + + EI + desc EI + 15 + 15 + read-only + + + + + ERRINTST + desc ERRINTST + 0x32 + 16 + read-write + 0x0 + 0x17F + + + CTOE + desc CTOE + 0 + 0 + read-write + + + CCE + desc CCE + 1 + 1 + read-write + + + CEBE + desc CEBE + 2 + 2 + read-write + + + CIE + desc CIE + 3 + 3 + read-write + + + DTOE + desc DTOE + 4 + 4 + read-write + + + DCE + desc DCE + 5 + 5 + read-write + + + DEBE + desc DEBE + 6 + 6 + read-write + + + ACE + desc ACE + 8 + 8 + read-write + + + + + NORINTSTEN + desc NORINTSTEN + 0x34 + 16 + read-write + 0x0 + 0x1F7 + + + CCEN + desc CCEN + 0 + 0 + read-write + + + TCEN + desc TCEN + 1 + 1 + read-write + + + BGEEN + desc BGEEN + 2 + 2 + read-write + + + BWREN + desc BWREN + 4 + 4 + read-write + + + BRREN + desc BRREN + 5 + 5 + read-write + + + CISTEN + desc CISTEN + 6 + 6 + read-write + + + CRMEN + desc CRMEN + 7 + 7 + read-write + + + CINTEN + desc CINTEN + 8 + 8 + read-write + + + + + ERRINTSTEN + desc ERRINTSTEN + 0x36 + 16 + read-write + 0x0 + 0x17F + + + CTOEEN + desc CTOEEN + 0 + 0 + read-write + + + CCEEN + desc CCEEN + 1 + 1 + read-write + + + CEBEEN + desc CEBEEN + 2 + 2 + read-write + + + CIEEN + desc CIEEN + 3 + 3 + read-write + + + DTOEEN + desc DTOEEN + 4 + 4 + read-write + + + DCEEN + desc DCEEN + 5 + 5 + read-write + + + DEBEEN + desc DEBEEN + 6 + 6 + read-write + + + ACEEN + desc ACEEN + 8 + 8 + read-write + + + + + NORINTSGEN + desc NORINTSGEN + 0x38 + 16 + read-write + 0x0 + 0x1F7 + + + CCSEN + desc CCSEN + 0 + 0 + read-write + + + TCSEN + desc TCSEN + 1 + 1 + read-write + + + BGESEN + desc BGESEN + 2 + 2 + read-write + + + BWRSEN + desc BWRSEN + 4 + 4 + read-write + + + BRRSEN + desc BRRSEN + 5 + 5 + read-write + + + CISTSEN + desc CISTSEN + 6 + 6 + read-write + + + CRMSEN + desc CRMSEN + 7 + 7 + read-write + + + CINTSEN + desc CINTSEN + 8 + 8 + read-write + + + + + ERRINTSGEN + desc ERRINTSGEN + 0x3A + 16 + read-write + 0x0 + 0x17F + + + CTOESEN + desc CTOESEN + 0 + 0 + read-write + + + CCESEN + desc CCESEN + 1 + 1 + read-write + + + CEBESEN + desc CEBESEN + 2 + 2 + read-write + + + CIESEN + desc CIESEN + 3 + 3 + read-write + + + DTOESEN + desc DTOESEN + 4 + 4 + read-write + + + DCESEN + desc DCESEN + 5 + 5 + read-write + + + DEBESEN + desc DEBESEN + 6 + 6 + read-write + + + ACESEN + desc ACESEN + 8 + 8 + read-write + + + + + ATCERRST + desc ATCERRST + 0x3C + 16 + read-only + 0x0 + 0x9F + + + NE + desc NE + 0 + 0 + read-only + + + TOE + desc TOE + 1 + 1 + read-only + + + CE + desc CE + 2 + 2 + read-only + + + EBE + desc EBE + 3 + 3 + read-only + + + IE + desc IE + 4 + 4 + read-only + + + CMDE + desc CMDE + 7 + 7 + read-only + + + + + FEA + desc FEA + 0x50 + 16 + write-only + 0x0 + 0x9F + + + FNE + desc FNE + 0 + 0 + write-only + + + FTOE + desc FTOE + 1 + 1 + write-only + + + FCE + desc FCE + 2 + 2 + write-only + + + FEBE + desc FEBE + 3 + 3 + write-only + + + FIE + desc FIE + 4 + 4 + write-only + + + FCMDE + desc FCMDE + 7 + 7 + write-only + + + + + FEE + desc FEE + 0x52 + 16 + write-only + 0x0 + 0x17F + + + FCTOE + desc FCTOE + 0 + 0 + write-only + + + FCCE + desc FCCE + 1 + 1 + write-only + + + FCEBE + desc FCEBE + 2 + 2 + write-only + + + FCIE + desc FCIE + 3 + 3 + write-only + + + FDTOE + desc FDTOE + 4 + 4 + write-only + + + FDCE + desc FDCE + 5 + 5 + write-only + + + FDEBE + desc FDEBE + 6 + 6 + write-only + + + FACE + desc FACE + 8 + 8 + write-only + + + + + + + SDIOC2 + desc SDIOC + 0x40078400 + + 0x0 + 0x54 + + + + SMC + desc SMC + 0x88000000 + + 0x0 + 0x210 + + + + STSR + desc STSR + 0x0 + 32 + read-only + 0x1 + 0x1 + + + STATUS + desc STATUS + 0 + 0 + read-only + + + + + STCR0 + desc STCR0 + 0x8 + 32 + write-only + 0x0 + 0x4 + + + LPWIR + desc LPWIR + 2 + 2 + write-only + + + + + STCR1 + desc STCR1 + 0xC + 32 + write-only + 0x0 + 0x4 + + + LPWOR + desc LPWOR + 2 + 2 + write-only + + + + + CMDR + desc CMDR + 0x10 + 32 + write-only + 0x0 + 0x3FFFFFF + + + CMDADD + desc CMDADD + 19 + 0 + write-only + + + CRES + desc CRES + 20 + 20 + write-only + + + CMD + desc CMD + 22 + 21 + write-only + + + CMDCHIP + desc CMDCHIP + 25 + 23 + write-only + + + + + TMCR + desc TMCR + 0x14 + 32 + write-only + 0x0 + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + write-only + + + T_WC + desc T_WC + 7 + 4 + write-only + + + T_CEOE + desc T_CEOE + 10 + 8 + write-only + + + T_WP + desc T_WP + 14 + 12 + write-only + + + T_PC + desc T_PC + 18 + 16 + write-only + + + T_TR + desc T_TR + 22 + 20 + write-only + + + + + CPCR + desc CPCR + 0x18 + 32 + write-only + 0x0 + 0x1FFF + + + RSYN + desc RSYN + 0 + 0 + write-only + + + RBL + desc RBL + 3 + 1 + write-only + + + WSYN + desc WSYN + 4 + 4 + write-only + + + WBL + desc WBL + 7 + 5 + write-only + + + MW + desc MW + 9 + 8 + write-only + + + BAAS + desc BAAS + 10 + 10 + write-only + + + ADVS + desc ADVS + 11 + 11 + write-only + + + BLSS + desc BLSS + 12 + 12 + write-only + + + + + RFTR + desc RFTR + 0x20 + 32 + read-write + 0x0 + 0xF + + + REFPRD + desc REFPRD + 3 + 0 + read-write + + + + + TMSR0 + desc TMSR0 + 0x100 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR0 + desc CPSR0 + 0x104 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR1 + desc TMSR1 + 0x120 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR1 + desc CPSR1 + 0x124 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR2 + desc TMSR2 + 0x140 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR2 + desc CPSR2 + 0x144 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + TMSR3 + desc TMSR3 + 0x160 + 32 + read-only + 0x1263CC + 0x17777FF + + + T_RC + desc T_RC + 3 + 0 + read-only + + + T_WC + desc T_WC + 7 + 4 + read-only + + + T_CEOE + desc T_CEOE + 10 + 8 + read-only + + + T_WP + desc T_WP + 14 + 12 + read-only + + + T_PC + desc T_PC + 18 + 16 + read-only + + + T_TR + desc T_TR + 22 + 20 + read-only + + + + + CPSR3 + desc CPSR3 + 0x164 + 32 + read-only + 0xFF0A00 + 0xFFFF1FFF + + + RSYN + desc RSYN + 0 + 0 + read-only + + + RBL + desc RBL + 3 + 1 + read-only + + + WSYN + desc WSYN + 4 + 4 + read-only + + + WBL + desc WBL + 7 + 5 + read-only + + + MW + desc MW + 9 + 8 + read-only + + + BAAS + desc BAAS + 10 + 10 + read-only + + + ADVS + desc ADVS + 11 + 11 + read-only + + + BLSS + desc BLSS + 12 + 12 + read-only + + + ADDMSK + desc ADDMSK + 23 + 16 + read-only + + + ADDMAT + desc ADDMAT + 31 + 24 + read-only + + + + + BACR + desc BACR + 0x200 + 32 + read-write + 0x300 + 0xC010 + + + MUXMD + desc MUXMD + 4 + 4 + read-write + + + CKSEL + desc CKSEL + 15 + 14 + read-write + + + + + CSCR0 + desc CSCR0 + 0x208 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDMSK0 + desc ADDMSK0 + 7 + 0 + read-write + + + ADDMSK1 + desc ADDMSK1 + 15 + 8 + read-write + + + ADDMSK2 + desc ADDMSK2 + 23 + 16 + read-write + + + ADDMSK3 + desc ADDMSK3 + 31 + 24 + read-write + + + + + CSCR1 + desc CSCR1 + 0x20C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDMAT0 + desc ADDMAT0 + 7 + 0 + read-write + + + ADDMAT1 + desc ADDMAT1 + 15 + 8 + read-write + + + ADDMAT2 + desc ADDMAT2 + 23 + 16 + read-write + + + ADDMAT3 + desc ADDMAT3 + 31 + 24 + read-write + + + + + + + SPI1 + desc SPI + 0x4001C000 + + 0x0 + 0x1C + + + + DR + desc DR + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + 0xFFFB + + + SPIMDS + desc SPIMDS + 0 + 0 + read-write + + + TXMDS + desc TXMDS + 1 + 1 + read-write + + + MSTR + desc MSTR + 3 + 3 + read-write + + + SPLPBK + desc SPLPBK + 4 + 4 + read-write + + + SPLPBK2 + desc SPLPBK2 + 5 + 5 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + CSUSPE + desc CSUSPE + 7 + 7 + read-write + + + EIE + desc EIE + 8 + 8 + read-write + + + TXIE + desc TXIE + 9 + 9 + read-write + + + RXIE + desc RXIE + 10 + 10 + read-write + + + IDIE + desc IDIE + 11 + 11 + read-write + + + MODFE + desc MODFE + 12 + 12 + read-write + + + PATE + desc PATE + 13 + 13 + read-write + + + PAOE + desc PAOE + 14 + 14 + read-write + + + PAE + desc PAE + 15 + 15 + read-write + + + + + CFG1 + desc CFG1 + 0xC + 32 + read-write + 0x10 + 0x77700F43 + + + FTHLV + desc FTHLV + 1 + 0 + read-write + + + SPRDTD + desc SPRDTD + 6 + 6 + read-write + + + SS0PV + desc SS0PV + 8 + 8 + read-write + + + SS1PV + desc SS1PV + 9 + 9 + read-write + + + SS2PV + desc SS2PV + 10 + 10 + read-write + + + SS3PV + desc SS3PV + 11 + 11 + read-write + + + MSSI + desc MSSI + 22 + 20 + read-write + + + MSSDL + desc MSSDL + 26 + 24 + read-write + + + MIDI + desc MIDI + 30 + 28 + read-write + + + + + SR + desc SR + 0x14 + 32 + read-write + 0x20 + 0xBF + + + OVRERF + desc OVRERF + 0 + 0 + read-write + + + IDLNF + desc IDLNF + 1 + 1 + read-only + + + MODFERF + desc MODFERF + 2 + 2 + read-write + + + PERF + desc PERF + 3 + 3 + read-write + + + UDRERF + desc UDRERF + 4 + 4 + read-write + + + TDEF + desc TDEF + 5 + 5 + read-only + + + RDFF + desc RDFF + 7 + 7 + read-only + + + + + CFG2 + desc CFG2 + 0x18 + 32 + read-write + 0xF1D + 0xFFFF + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MBR + desc MBR + 4 + 2 + read-write + + + SSA + desc SSA + 7 + 5 + read-write + + + DSIZE + desc DSIZE + 11 + 8 + read-write + + + LSBF + desc LSBF + 12 + 12 + read-write + + + MIDIE + desc MIDIE + 13 + 13 + read-write + + + MSSDLE + desc MSSDLE + 14 + 14 + read-write + + + MSSIE + desc MSSIE + 15 + 15 + read-write + + + + + + + SPI2 + desc SPI + 0x4001C400 + + 0x0 + 0x1C + + + + SPI3 + desc SPI + 0x4001C800 + + 0x0 + 0x1C + + + + SPI4 + desc SPI + 0x40020000 + + 0x0 + 0x1C + + + + SPI5 + desc SPI + 0x40020400 + + 0x0 + 0x1C + + + + SPI6 + desc SPI + 0x40020800 + + 0x0 + 0x1C + + + + SRAMC + desc SRAMC + 0x40050800 + + 0x0 + 0x14 + + + + WTCR + desc WTCR + 0x0 + 32 + read-write + 0x0 + 0x77777777 + + + SRAM123RWT + desc SRAM123RWT + 2 + 0 + read-write + + + SRAM123WWT + desc SRAM123WWT + 6 + 4 + read-write + + + SRAM4RWT + desc SRAM4RWT + 10 + 8 + read-write + + + SRAM4WWT + desc SRAM4WWT + 14 + 12 + read-write + + + SRAMHRWT + desc SRAMHRWT + 18 + 16 + read-write + + + SRAMHWWT + desc SRAMHWWT + 22 + 20 + read-write + + + SRAMBRWT + desc SRAMBRWT + 26 + 24 + read-write + + + SRAMBWWT + desc SRAMBWWT + 30 + 28 + read-write + + + + + WTPR + desc WTPR + 0x4 + 32 + read-write + 0x0 + 0xFF + + + WTPRC + desc WTPRC + 0 + 0 + read-write + + + WTPRKW + desc WTPRKW + 7 + 1 + read-write + + + + + CKCR + desc CKCR + 0x8 + 32 + read-write + 0x0 + 0xF030001 + + + PYOAD + desc PYOAD + 0 + 0 + read-write + + + ECCOAD + desc ECCOAD + 16 + 16 + read-write + + + BECCOAD + desc BECCOAD + 17 + 17 + read-write + + + ECCMOD + desc ECCMOD + 25 + 24 + read-write + + + BECCMOD + desc BECCMOD + 27 + 26 + read-write + + + + + CKPR + desc CKPR + 0xC + 32 + read-write + 0x0 + 0xFF + + + CKPRC + desc CKPRC + 0 + 0 + read-write + + + CKPRKW + desc CKPRKW + 7 + 1 + read-write + + + + + CKSR + desc CKSR + 0x10 + 32 + read-write + 0x0 + 0x1FF + + + SRAM1_PYERR + desc SRAM1_PYERR + 0 + 0 + read-write + + + SRAM2_PYERR + desc SRAM2_PYERR + 1 + 1 + read-write + + + SRAM3_PYERR + desc SRAM3_PYERR + 2 + 2 + read-write + + + SRAMH_PYERR + desc SRAMH_PYERR + 3 + 3 + read-write + + + SRAM4_1ERR + desc SRAM4_1ERR + 4 + 4 + read-write + + + SRAM4_2ERR + desc SRAM4_2ERR + 5 + 5 + read-write + + + SRAMB_1ERR + desc SRAMB_1ERR + 6 + 6 + read-write + + + SRAMB_2ERR + desc SRAMB_2ERR + 7 + 7 + read-write + + + CACHE_PYERR + desc CACHE_PYERR + 8 + 8 + read-write + + + + + + + SWDT + desc SWDT + 0x40049400 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + TMR01 + desc TMR0 + 0x40024000 + + 0x0 + 0x18 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0xF7F7F7F7 + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + INTENA + desc INTENA + 2 + 2 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNSA + desc SYNSA + 8 + 8 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 9 + read-write + + + ASYNCLKA + desc ASYNCLKA + 10 + 10 + read-write + + + HSTAA + desc HSTAA + 12 + 12 + read-write + + + HSTPA + desc HSTPA + 13 + 13 + read-write + + + HCLEA + desc HCLEA + 14 + 14 + read-write + + + HICPA + desc HICPA + 15 + 15 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + INTENB + desc INTENB + 18 + 18 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNSB + desc SYNSB + 24 + 24 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 25 + read-write + + + ASYNCLKB + desc ASYNCLKB + 26 + 26 + read-write + + + HSTAB + desc HSTAB + 28 + 28 + read-write + + + HSTPB + desc HSTPB + 29 + 29 + read-write + + + HCLEB + desc HCLEB + 30 + 30 + read-write + + + HICPB + desc HICPB + 31 + 31 + read-write + + + + + STFLR + desc STFLR + 0x14 + 32 + read-write + 0x0 + 0x10001 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + + + + + TMR02 + desc TMR0 + 0x40024400 + + 0x0 + 0x18 + + + + TMR21 + desc TMR2 + 0x40024800 + + 0x0 + 0x24 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0x3FFB3FFB + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + SYNSA + desc SYNSA + 3 + 3 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 8 + read-write + + + ASYNCLKA + desc ASYNCLKA + 11 + 10 + read-write + + + SYNCLKAT + desc SYNCLKAT + 13 + 12 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + SYNSB + desc SYNSB + 19 + 19 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 24 + read-write + + + ASYNCLKB + desc ASYNCLKB + 27 + 26 + read-write + + + SYNCLKBT + desc SYNCLKBT + 29 + 28 + read-write + + + + + ICONR + desc ICONR + 0x14 + 32 + read-write + 0x0 + 0x30003 + + + CMENA + desc CMENA + 0 + 0 + read-write + + + OVENA + desc OVENA + 1 + 1 + read-write + + + CMENB + desc CMENB + 16 + 16 + read-write + + + OVENB + desc OVENB + 17 + 17 + read-write + + + + + PCONR + desc PCONR + 0x18 + 32 + read-write + 0x0 + 0x713F713F + + + STACA + desc STACA + 1 + 0 + read-write + + + STPCA + desc STPCA + 3 + 2 + read-write + + + CMPCA + desc CMPCA + 5 + 4 + read-write + + + OUTENA + desc OUTENA + 8 + 8 + read-write + + + NOFIENA + desc NOFIENA + 12 + 12 + read-write + + + NOFICKA + desc NOFICKA + 14 + 13 + read-write + + + STACB + desc STACB + 17 + 16 + read-write + + + STPCB + desc STPCB + 19 + 18 + read-write + + + CMPCB + desc CMPCB + 21 + 20 + read-write + + + OUTENB + desc OUTENB + 24 + 24 + read-write + + + NOFIENB + desc NOFIENB + 28 + 28 + read-write + + + NOFICKB + desc NOFICKB + 30 + 29 + read-write + + + + + HCONR + desc HCONR + 0x1C + 32 + read-write + 0x0 + 0x77777777 + + + HSTAA0 + desc HSTAA0 + 0 + 0 + read-write + + + HSTAA1 + desc HSTAA1 + 1 + 1 + read-write + + + HSTAA2 + desc HSTAA2 + 2 + 2 + read-write + + + HSTPA0 + desc HSTPA0 + 4 + 4 + read-write + + + HSTPA1 + desc HSTPA1 + 5 + 5 + read-write + + + HSTPA2 + desc HSTPA2 + 6 + 6 + read-write + + + HCLEA0 + desc HCLEA0 + 8 + 8 + read-write + + + HCLEA1 + desc HCLEA1 + 9 + 9 + read-write + + + HCLEA2 + desc HCLEA2 + 10 + 10 + read-write + + + HICPA0 + desc HICPA0 + 12 + 12 + read-write + + + HICPA1 + desc HICPA1 + 13 + 13 + read-write + + + HICPA2 + desc HICPA2 + 14 + 14 + read-write + + + HSTAB0 + desc HSTAB0 + 16 + 16 + read-write + + + HSTAB1 + desc HSTAB1 + 17 + 17 + read-write + + + HSTAB2 + desc HSTAB2 + 18 + 18 + read-write + + + HSTPB0 + desc HSTPB0 + 20 + 20 + read-write + + + HSTPB1 + desc HSTPB1 + 21 + 21 + read-write + + + HSTPB2 + desc HSTPB2 + 22 + 22 + read-write + + + HCLEB0 + desc HCLEB0 + 24 + 24 + read-write + + + HCLEB1 + desc HCLEB1 + 25 + 25 + read-write + + + HCLEB2 + desc HCLEB2 + 26 + 26 + read-write + + + HICPB0 + desc HICPB0 + 28 + 28 + read-write + + + HICPB1 + desc HICPB1 + 29 + 29 + read-write + + + HICPB2 + desc HICPB2 + 30 + 30 + read-write + + + + + STFLR + desc STFLR + 0x20 + 32 + read-write + 0x0 + 0x1030003 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + OVFA + desc OVFA + 1 + 1 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + OVFB + desc OVFB + 17 + 17 + read-write + + + + + + + TMR22 + desc TMR2 + 0x40024C00 + + 0x0 + 0x24 + + + + TMR23 + desc TMR2 + 0x40025000 + + 0x0 + 0x24 + + + + TMR24 + desc TMR2 + 0x40025400 + + 0x0 + 0x24 + + + + TMR41 + desc TMR4 + 0x40038000 + + 0x0 + 0xE6 + + + + OCCRUH + desc OCCRUH + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRUL + desc OCCRUL + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVH + desc OCCRVH + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVL + desc OCCRVL + 0xE + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWH + desc OCCRWH + 0x12 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWL + desc OCCRWL + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + OCSRU + desc OCSRU + 0x18 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERU + desc OCERU + 0x1A + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRV + desc OCSRV + 0x1C + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERV + desc OCERV + 0x1E + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRW + desc OCSRW + 0x20 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERW + desc OCERW + 0x22 + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCMRHUH + desc OCMRHUH + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLUL + desc OCMRLUL + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHVH + desc OCMRHVH + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLVL + desc OCMRLVL + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHWH + desc OCMRHWH + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLWL + desc OCMRLWL + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + CPSR + desc CPSR + 0x42 + 16 + read-write + 0xFFFF + 0xFFFF + + + CNTR + desc CNTR + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + CCSR + desc CCSR + 0x48 + 16 + read-write + 0x40 + 0xE3FF + + + CKDIV + desc CKDIV + 3 + 0 + read-write + + + CLEAR + desc CLEAR + 4 + 4 + read-write + + + MODE + desc MODE + 5 + 5 + read-write + + + STOP + desc STOP + 6 + 6 + read-write + + + BUFEN + desc BUFEN + 7 + 7 + read-write + + + IRQPEN + desc IRQPEN + 8 + 8 + read-write + + + IRQPF + desc IRQPF + 9 + 9 + read-write + + + IRQZEN + desc IRQZEN + 13 + 13 + read-write + + + IRQZF + desc IRQZF + 14 + 14 + read-write + + + ECKEN + desc ECKEN + 15 + 15 + read-write + + + + + CVPR + desc CVPR + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + ZIM + desc ZIM + 3 + 0 + read-write + + + PIM + desc PIM + 7 + 4 + read-write + + + ZIC + desc ZIC + 11 + 8 + read-only + + + PIC + desc PIC + 15 + 12 + read-only + + + + + PFSRU + desc PFSRU + 0x82 + 16 + read-write + 0x0 + 0xFFFF + + + PDARU + desc PDARU + 0x84 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRU + desc PDBRU + 0x86 + 16 + read-write + 0x0 + 0xFFFF + + + PFSRV + desc PFSRV + 0x8A + 16 + read-write + 0x0 + 0xFFFF + + + PDARV + desc PDARV + 0x8C + 16 + read-write + 0x0 + 0xFFFF + + + PDBRV + desc PDBRV + 0x8E + 16 + read-write + 0x0 + 0xFFFF + + + PFSRW + desc PFSRW + 0x92 + 16 + read-write + 0x0 + 0xFFFF + + + PDARW + desc PDARW + 0x94 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRW + desc PDBRW + 0x96 + 16 + read-write + 0x0 + 0xFFFF + + + POCRU + desc POCRU + 0x98 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRV + desc POCRV + 0x9C + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRW + desc POCRW + 0xA0 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + RCSR + desc RCSR + 0xA4 + 16 + read-write + 0x0 + 0xFFF7 + + + RTIDU + desc RTIDU + 0 + 0 + read-write + + + RTIDV + desc RTIDV + 1 + 1 + read-write + + + RTIDW + desc RTIDW + 2 + 2 + read-write + + + RTIFU + desc RTIFU + 4 + 4 + read-only + + + RTICU + desc RTICU + 5 + 5 + read-write + + + RTEU + desc RTEU + 6 + 6 + read-write + + + RTSU + desc RTSU + 7 + 7 + read-write + + + RTIFV + desc RTIFV + 8 + 8 + read-only + + + RTICV + desc RTICV + 9 + 9 + read-write + + + RTEV + desc RTEV + 10 + 10 + read-write + + + RTSV + desc RTSV + 11 + 11 + read-write + + + RTIFW + desc RTIFW + 12 + 12 + read-only + + + RTICW + desc RTICW + 13 + 13 + read-write + + + RTEW + desc RTEW + 14 + 14 + read-write + + + RTSW + desc RTSW + 15 + 15 + read-write + + + + + SCCRUH + desc SCCRUH + 0xB2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRUL + desc SCCRUL + 0xB6 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVH + desc SCCRVH + 0xBA + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVL + desc SCCRVL + 0xBE + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWH + desc SCCRWH + 0xC2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWL + desc SCCRWL + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + SCSRUH + desc SCSRUH + 0xC8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUH + desc SCMRUH + 0xCA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRUL + desc SCSRUL + 0xCC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUL + desc SCMRUL + 0xCE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVH + desc SCSRVH + 0xD0 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVH + desc SCMRVH + 0xD2 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVL + desc SCSRVL + 0xD4 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVL + desc SCMRVL + 0xD6 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWH + desc SCSRWH + 0xD8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWH + desc SCMRWH + 0xDA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWL + desc SCSRWL + 0xDC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWL + desc SCMRWL + 0xDE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + PSCR + desc PSCR + 0xE0 + 32 + read-write + 0x5550000 + 0xFFF03FF + + + OEUH + desc OEUH + 0 + 0 + read-write + + + OEUL + desc OEUL + 1 + 1 + read-write + + + OEVH + desc OEVH + 2 + 2 + read-write + + + OEVL + desc OEVL + 3 + 3 + read-write + + + OEWH + desc OEWH + 4 + 4 + read-write + + + OEWL + desc OEWL + 5 + 5 + read-write + + + ODT + desc ODT + 7 + 6 + read-write + + + MOE + desc MOE + 8 + 8 + read-write + + + AOE + desc AOE + 9 + 9 + read-write + + + OSUH + desc OSUH + 17 + 16 + read-write + + + OSUL + desc OSUL + 19 + 18 + read-write + + + OSVH + desc OSVH + 21 + 20 + read-write + + + OSVL + desc OSVL + 23 + 22 + read-write + + + OSWH + desc OSWH + 25 + 24 + read-write + + + OSWL + desc OSWL + 27 + 26 + read-write + + + + + SCER + desc SCER + 0xE4 + 16 + read-write + 0xFF00 + 0xF + + + EVTRS + desc EVTRS + 2 + 0 + read-write + + + PCTS + desc PCTS + 3 + 3 + read-write + + + + + + + TMR42 + desc TMR4 + 0x40038400 + + 0x0 + 0xE6 + + + + TMR43 + desc TMR4 + 0x40038800 + + 0x0 + 0xE6 + + + + TMR61 + desc TMR6 + 0x40018000 + + 0x0 + 0x1A0 + + + + CNTER + desc CNTER + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + UPDAR + desc UPDAR + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PERAR + desc PERAR + 0x40 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERBR + desc PERBR + 0x44 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERCR + desc PERCR + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMAR + desc GCMAR + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMBR + desc GCMBR + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMCR + desc GCMCR + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMDR + desc GCMDR + 0x8C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMER + desc GCMER + 0x90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCMFR + desc GCMFR + 0x94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMAR + desc SCMAR + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMBR + desc SCMBR + 0xC4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMCR + desc SCMCR + 0xC8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMDR + desc SCMDR + 0xCC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMER + desc SCMER + 0xD0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SCMFR + desc SCMFR + 0xD4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTUAR + desc DTUAR + 0x100 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTDAR + desc DTDAR + 0x104 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTUBR + desc DTUBR + 0x108 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DTDBR + desc DTDBR + 0x10C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GCONR + desc GCONR + 0x140 + 32 + read-write + 0x2 + 0xF01F7 + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + OVSTP + desc OVSTP + 8 + 8 + read-write + + + ZMSKREV + desc ZMSKREV + 16 + 16 + read-write + + + ZMSKPOS + desc ZMSKPOS + 17 + 17 + read-write + + + ZMSKVAL + desc ZMSKVAL + 19 + 18 + read-write + + + + + ICONR + desc ICONR + 0x144 + 32 + read-write + 0x0 + 0xF01FF + + + INTENA + desc INTENA + 0 + 0 + read-write + + + INTENB + desc INTENB + 1 + 1 + read-write + + + INTENC + desc INTENC + 2 + 2 + read-write + + + INTEND + desc INTEND + 3 + 3 + read-write + + + INTENE + desc INTENE + 4 + 4 + read-write + + + INTENF + desc INTENF + 5 + 5 + read-write + + + INTENOVF + desc INTENOVF + 6 + 6 + read-write + + + INTENUDF + desc INTENUDF + 7 + 7 + read-write + + + INTENDTE + desc INTENDTE + 8 + 8 + read-write + + + INTENSAU + desc INTENSAU + 16 + 16 + read-write + + + INTENSAD + desc INTENSAD + 17 + 17 + read-write + + + INTENSBU + desc INTENSBU + 18 + 18 + read-write + + + INTENSBD + desc INTENSBD + 19 + 19 + read-write + + + + + BCONR + desc BCONR + 0x148 + 32 + read-write + 0x0 + 0xFF0FFF + + + BENA + desc BENA + 0 + 0 + read-write + + + BSEA + desc BSEA + 1 + 1 + read-write + + + BTRUA + desc BTRUA + 2 + 2 + read-write + + + BTRDA + desc BTRDA + 3 + 3 + read-write + + + BENB + desc BENB + 4 + 4 + read-write + + + BSEB + desc BSEB + 5 + 5 + read-write + + + BTRUB + desc BTRUB + 6 + 6 + read-write + + + BTRDB + desc BTRDB + 7 + 7 + read-write + + + BENP + desc BENP + 8 + 8 + read-write + + + BSEP + desc BSEP + 9 + 9 + read-write + + + BTRUP + desc BTRUP + 10 + 10 + read-write + + + BTRDP + desc BTRDP + 11 + 11 + read-write + + + BENSPA + desc BENSPA + 16 + 16 + read-write + + + BSESPA + desc BSESPA + 17 + 17 + read-write + + + BTRUSPA + desc BTRUSPA + 18 + 18 + read-write + + + BTRDSPA + desc BTRDSPA + 19 + 19 + read-write + + + BENSPB + desc BENSPB + 20 + 20 + read-write + + + BSESPB + desc BSESPB + 21 + 21 + read-write + + + BTRUSPB + desc BTRUSPB + 22 + 22 + read-write + + + BTRDSPB + desc BTRDSPB + 23 + 23 + read-write + + + + + DCONR + desc DCONR + 0x14C + 32 + read-write + 0x0 + 0xF3 + + + DTCEN + desc DTCEN + 0 + 0 + read-write + + + SEPA + desc SEPA + 1 + 1 + read-write + + + DTBENU + desc DTBENU + 4 + 4 + read-write + + + DTBEND + desc DTBEND + 5 + 5 + read-write + + + DTBTRU + desc DTBTRU + 6 + 6 + read-write + + + DTBTRD + desc DTBTRD + 7 + 7 + read-write + + + + + PCNAR + desc PCNAR + 0x154 + 32 + read-write + 0x0 + 0x93F3FFFF + + + STACA + desc STACA + 1 + 0 + read-write + + + STPCA + desc STPCA + 3 + 2 + read-write + + + OVFCA + desc OVFCA + 5 + 4 + read-write + + + UDFCA + desc UDFCA + 7 + 6 + read-write + + + CMAUCA + desc CMAUCA + 9 + 8 + read-write + + + CMADCA + desc CMADCA + 11 + 10 + read-write + + + CMBUCA + desc CMBUCA + 13 + 12 + read-write + + + CMBDCA + desc CMBDCA + 15 + 14 + read-write + + + FORCA + desc FORCA + 17 + 16 + read-write + + + EMBCA + desc EMBCA + 21 + 20 + read-write + + + EMBRA + desc EMBRA + 23 + 22 + read-write + + + EMBSA + desc EMBSA + 25 + 24 + read-write + + + OUTENA + desc OUTENA + 28 + 28 + read-write + + + CAPMDA + desc CAPMDA + 31 + 31 + read-write + + + + + PCNBR + desc PCNBR + 0x158 + 32 + read-write + 0x0 + 0x93F3FFFF + + + STACB + desc STACB + 1 + 0 + read-write + + + STPCB + desc STPCB + 3 + 2 + read-write + + + OVFCB + desc OVFCB + 5 + 4 + read-write + + + UDFCB + desc UDFCB + 7 + 6 + read-write + + + CMAUCB + desc CMAUCB + 9 + 8 + read-write + + + CMADCB + desc CMADCB + 11 + 10 + read-write + + + CMBUCB + desc CMBUCB + 13 + 12 + read-write + + + CMBDCB + desc CMBDCB + 15 + 14 + read-write + + + FORCB + desc FORCB + 17 + 16 + read-write + + + EMBCB + desc EMBCB + 21 + 20 + read-write + + + EMBRB + desc EMBRB + 23 + 22 + read-write + + + EMBSB + desc EMBSB + 25 + 24 + read-write + + + OUTENB + desc OUTENB + 28 + 28 + read-write + + + CAPMDB + desc CAPMDB + 31 + 31 + read-write + + + + + FCNGR + desc FCNGR + 0x15C + 32 + read-write + 0x0 + 0x77 + + + NOFIENGA + desc NOFIENGA + 0 + 0 + read-write + + + NOFICKGA + desc NOFICKGA + 2 + 1 + read-write + + + NOFIENGB + desc NOFIENGB + 4 + 4 + read-write + + + NOFICKGB + desc NOFICKGB + 6 + 5 + read-write + + + + + VPERR + desc VPERR + 0x160 + 32 + read-write + 0x0 + 0x1F0300 + + + SPPERIA + desc SPPERIA + 8 + 8 + read-write + + + SPPERIB + desc SPPERIB + 9 + 9 + read-write + + + PCNTE + desc PCNTE + 17 + 16 + read-write + + + PCNTS + desc PCNTS + 20 + 18 + read-write + + + + + STFLR + desc STFLR + 0x164 + 32 + read-write + 0x80000000 + 0x80E01FFF + + + CMAF + desc CMAF + 0 + 0 + read-write + + + CMBF + desc CMBF + 1 + 1 + read-write + + + CMCF + desc CMCF + 2 + 2 + read-write + + + CMDF + desc CMDF + 3 + 3 + read-write + + + CMEF + desc CMEF + 4 + 4 + read-write + + + CMFF + desc CMFF + 5 + 5 + read-write + + + OVFF + desc OVFF + 6 + 6 + read-write + + + UDFF + desc UDFF + 7 + 7 + read-write + + + DTEF + desc DTEF + 8 + 8 + read-only + + + CMSAUF + desc CMSAUF + 9 + 9 + read-write + + + CMSADF + desc CMSADF + 10 + 10 + read-write + + + CMSBUF + desc CMSBUF + 11 + 11 + read-write + + + CMSBDF + desc CMSBDF + 12 + 12 + read-write + + + VPERNUM + desc VPERNUM + 23 + 21 + read-only + + + DIRF + desc DIRF + 31 + 31 + read-only + + + + + HSTAR + desc HSTAR + 0x180 + 32 + read-write + 0x0 + 0xFF0F8F + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTA3 + desc HSTA3 + 3 + 3 + read-write + + + STAS + desc STAS + 7 + 7 + read-write + + + HSTA8 + desc HSTA8 + 8 + 8 + read-write + + + HSTA9 + desc HSTA9 + 9 + 9 + read-write + + + HSTA10 + desc HSTA10 + 10 + 10 + read-write + + + HSTA11 + desc HSTA11 + 11 + 11 + read-write + + + HSTA16 + desc HSTA16 + 16 + 16 + read-write + + + HSTA17 + desc HSTA17 + 17 + 17 + read-write + + + HSTA18 + desc HSTA18 + 18 + 18 + read-write + + + HSTA19 + desc HSTA19 + 19 + 19 + read-write + + + HSTA20 + desc HSTA20 + 20 + 20 + read-write + + + HSTA21 + desc HSTA21 + 21 + 21 + read-write + + + HSTA22 + desc HSTA22 + 22 + 22 + read-write + + + HSTA23 + desc HSTA23 + 23 + 23 + read-write + + + + + HSTPR + desc HSTPR + 0x184 + 32 + read-write + 0x0 + 0xFF0F8F + + + HSTP0 + desc HSTP0 + 0 + 0 + read-write + + + HSTP1 + desc HSTP1 + 1 + 1 + read-write + + + HSTP2 + desc HSTP2 + 2 + 2 + read-write + + + HSTP3 + desc HSTP3 + 3 + 3 + read-write + + + STPS + desc STPS + 7 + 7 + read-write + + + HSTP8 + desc HSTP8 + 8 + 8 + read-write + + + HSTP9 + desc HSTP9 + 9 + 9 + read-write + + + HSTP10 + desc HSTP10 + 10 + 10 + read-write + + + HSTP11 + desc HSTP11 + 11 + 11 + read-write + + + HSTP16 + desc HSTP16 + 16 + 16 + read-write + + + HSTP17 + desc HSTP17 + 17 + 17 + read-write + + + HSTP18 + desc HSTP18 + 18 + 18 + read-write + + + HSTP19 + desc HSTP19 + 19 + 19 + read-write + + + HSTP20 + desc HSTP20 + 20 + 20 + read-write + + + HSTP21 + desc HSTP21 + 21 + 21 + read-write + + + HSTP22 + desc HSTP22 + 22 + 22 + read-write + + + HSTP23 + desc HSTP23 + 23 + 23 + read-write + + + + + HCLRR + desc HCLRR + 0x188 + 32 + read-write + 0x0 + 0xFF0F8F + + + HCLE0 + desc HCLE0 + 0 + 0 + read-write + + + HCLE1 + desc HCLE1 + 1 + 1 + read-write + + + HCLE2 + desc HCLE2 + 2 + 2 + read-write + + + HCLE3 + desc HCLE3 + 3 + 3 + read-write + + + CLES + desc CLES + 7 + 7 + read-write + + + HCLE8 + desc HCLE8 + 8 + 8 + read-write + + + HCLE9 + desc HCLE9 + 9 + 9 + read-write + + + HCLE10 + desc HCLE10 + 10 + 10 + read-write + + + HCLE11 + desc HCLE11 + 11 + 11 + read-write + + + HCLE16 + desc HCLE16 + 16 + 16 + read-write + + + HCLE17 + desc HCLE17 + 17 + 17 + read-write + + + HCLE18 + desc HCLE18 + 18 + 18 + read-write + + + HCLE19 + desc HCLE19 + 19 + 19 + read-write + + + HCLE20 + desc HCLE20 + 20 + 20 + read-write + + + HCLE21 + desc HCLE21 + 21 + 21 + read-write + + + HCLE22 + desc HCLE22 + 22 + 22 + read-write + + + HCLE23 + desc HCLE23 + 23 + 23 + read-write + + + + + HUPDR + desc HUPDR + 0x18C + 32 + read-write + 0x0 + 0xFF0F8F + + + HUPD0 + desc HUPD0 + 0 + 0 + read-write + + + HUPD1 + desc HUPD1 + 1 + 1 + read-write + + + HUPD2 + desc HUPD2 + 2 + 2 + read-write + + + HUPD3 + desc HUPD3 + 3 + 3 + read-write + + + UPDS + desc UPDS + 7 + 7 + read-write + + + HUPD8 + desc HUPD8 + 8 + 8 + read-write + + + HUPD9 + desc HUPD9 + 9 + 9 + read-write + + + HUPD10 + desc HUPD10 + 10 + 10 + read-write + + + HUPD11 + desc HUPD11 + 11 + 11 + read-write + + + HUPD16 + desc HUPD16 + 16 + 16 + read-write + + + HUPD17 + desc HUPD17 + 17 + 17 + read-write + + + HUPD18 + desc HUPD18 + 18 + 18 + read-write + + + HUPD19 + desc HUPD19 + 19 + 19 + read-write + + + HUPD20 + desc HUPD20 + 20 + 20 + read-write + + + HUPD21 + desc HUPD21 + 21 + 21 + read-write + + + HUPD22 + desc HUPD22 + 22 + 22 + read-write + + + HUPD23 + desc HUPD23 + 23 + 23 + read-write + + + + + HCPAR + desc HCPAR + 0x190 + 32 + read-write + 0x0 + 0xFF0F0F + + + HCPA0 + desc HCPA0 + 0 + 0 + read-write + + + HCPA1 + desc HCPA1 + 1 + 1 + read-write + + + HCPA2 + desc HCPA2 + 2 + 2 + read-write + + + HCPA3 + desc HCPA3 + 3 + 3 + read-write + + + HCPA8 + desc HCPA8 + 8 + 8 + read-write + + + HCPA9 + desc HCPA9 + 9 + 9 + read-write + + + HCPA10 + desc HCPA10 + 10 + 10 + read-write + + + HCPA11 + desc HCPA11 + 11 + 11 + read-write + + + HCPA16 + desc HCPA16 + 16 + 16 + read-write + + + HCPA17 + desc HCPA17 + 17 + 17 + read-write + + + HCPA18 + desc HCPA18 + 18 + 18 + read-write + + + HCPA19 + desc HCPA19 + 19 + 19 + read-write + + + HCPA20 + desc HCPA20 + 20 + 20 + read-write + + + HCPA21 + desc HCPA21 + 21 + 21 + read-write + + + HCPA22 + desc HCPA22 + 22 + 22 + read-write + + + HCPA23 + desc HCPA23 + 23 + 23 + read-write + + + + + HCPBR + desc HCPBR + 0x194 + 32 + read-write + 0x0 + 0xFF0F0F + + + HCPB0 + desc HCPB0 + 0 + 0 + read-write + + + HCPB1 + desc HCPB1 + 1 + 1 + read-write + + + HCPB2 + desc HCPB2 + 2 + 2 + read-write + + + HCPB3 + desc HCPB3 + 3 + 3 + read-write + + + HCPB8 + desc HCPB8 + 8 + 8 + read-write + + + HCPB9 + desc HCPB9 + 9 + 9 + read-write + + + HCPB10 + desc HCPB10 + 10 + 10 + read-write + + + HCPB11 + desc HCPB11 + 11 + 11 + read-write + + + HCPB16 + desc HCPB16 + 16 + 16 + read-write + + + HCPB17 + desc HCPB17 + 17 + 17 + read-write + + + HCPB18 + desc HCPB18 + 18 + 18 + read-write + + + HCPB19 + desc HCPB19 + 19 + 19 + read-write + + + HCPB20 + desc HCPB20 + 20 + 20 + read-write + + + HCPB21 + desc HCPB21 + 21 + 21 + read-write + + + HCPB22 + desc HCPB22 + 22 + 22 + read-write + + + HCPB23 + desc HCPB23 + 23 + 23 + read-write + + + + + HCUPR + desc HCUPR + 0x198 + 32 + read-write + 0x0 + 0xFF0FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP16 + desc HCUP16 + 16 + 16 + read-write + + + HCUP17 + desc HCUP17 + 17 + 17 + read-write + + + HCUP18 + desc HCUP18 + 18 + 18 + read-write + + + HCUP19 + desc HCUP19 + 19 + 19 + read-write + + + HCUP20 + desc HCUP20 + 20 + 20 + read-write + + + HCUP21 + desc HCUP21 + 21 + 21 + read-write + + + HCUP22 + desc HCUP22 + 22 + 22 + read-write + + + HCUP23 + desc HCUP23 + 23 + 23 + read-write + + + + + HCDOR + desc HCDOR + 0x19C + 32 + read-write + 0x0 + 0xFF0FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO16 + desc HCDO16 + 16 + 16 + read-write + + + HCDO17 + desc HCDO17 + 17 + 17 + read-write + + + HCDO18 + desc HCDO18 + 18 + 18 + read-write + + + HCDO19 + desc HCDO19 + 19 + 19 + read-write + + + HCDO20 + desc HCDO20 + 20 + 20 + read-write + + + HCDO21 + desc HCDO21 + 21 + 21 + read-write + + + HCDO22 + desc HCDO22 + 22 + 22 + read-write + + + HCDO23 + desc HCDO23 + 23 + 23 + read-write + + + + + + + TMR62 + desc TMR6 + 0x40018400 + + 0x0 + 0x1A0 + + + + TMR63 + desc TMR6 + 0x40018800 + + 0x0 + 0x1A0 + + + + TMR64 + desc TMR6 + 0x40018C00 + + 0x0 + 0x1A0 + + + + TMR65 + desc TMR6 + 0x40019000 + + 0x0 + 0x1A0 + + + + TMR66 + desc TMR6 + 0x40019400 + + 0x0 + 0x1A0 + + + + TMR67 + desc TMR6 + 0x40019800 + + 0x0 + 0x1A0 + + + + TMR68 + desc TMR6 + 0x40019C00 + + 0x0 + 0x1A0 + + + + TMR6CR + desc TMR6CR + 0x40018000 + TMR61 + + 0x0 + 0x400 + + + + FCNTR + desc FCNTR + 0x3EC + 32 + read-write + 0x0 + 0x7777 + + + NOFIENTA + desc NOFIENTA + 0 + 0 + read-write + + + NOFICKTA + desc NOFICKTA + 2 + 1 + read-write + + + NOFIENTB + desc NOFIENTB + 4 + 4 + read-write + + + NOFICKTB + desc NOFICKTB + 6 + 5 + read-write + + + NOFIENTC + desc NOFIENTC + 8 + 8 + read-write + + + NOFICKTC + desc NOFICKTC + 10 + 9 + read-write + + + NOFIENTD + desc NOFIENTD + 12 + 12 + read-write + + + NOFICKTD + desc NOFICKTD + 14 + 13 + read-write + + + + + SSTAR + desc SSTAR + 0x3F0 + 32 + read-write + 0x0 + 0xFF + + + SSTA1 + desc SSTA1 + 0 + 0 + read-write + + + SSTA2 + desc SSTA2 + 1 + 1 + read-write + + + SSTA3 + desc SSTA3 + 2 + 2 + read-write + + + SSTA4 + desc SSTA4 + 3 + 3 + read-write + + + SSTA5 + desc SSTA5 + 4 + 4 + read-write + + + SSTA6 + desc SSTA6 + 5 + 5 + read-write + + + SSTA7 + desc SSTA7 + 6 + 6 + read-write + + + SSTA8 + desc SSTA8 + 7 + 7 + read-write + + + + + SSTPR + desc SSTPR + 0x3F4 + 32 + read-write + 0x0 + 0xFF + + + SSTP1 + desc SSTP1 + 0 + 0 + read-write + + + SSTP2 + desc SSTP2 + 1 + 1 + read-write + + + SSTP3 + desc SSTP3 + 2 + 2 + read-write + + + SSTP4 + desc SSTP4 + 3 + 3 + read-write + + + SSTP5 + desc SSTP5 + 4 + 4 + read-write + + + SSTP6 + desc SSTP6 + 5 + 5 + read-write + + + SSTP7 + desc SSTP7 + 6 + 6 + read-write + + + SSTP8 + desc SSTP8 + 7 + 7 + read-write + + + + + SCLRR + desc SCLRR + 0x3F8 + 32 + read-write + 0x0 + 0xFF + + + SCLE1 + desc SCLE1 + 0 + 0 + read-write + + + SCLE2 + desc SCLE2 + 1 + 1 + read-write + + + SCLE3 + desc SCLE3 + 2 + 2 + read-write + + + SCLE4 + desc SCLE4 + 3 + 3 + read-write + + + SCLE5 + desc SCLE5 + 4 + 4 + read-write + + + SCLE6 + desc SCLE6 + 5 + 5 + read-write + + + SCLE7 + desc SCLE7 + 6 + 6 + read-write + + + SCLE8 + desc SCLE8 + 7 + 7 + read-write + + + + + SUPDR + desc SUPDR + 0x3FC + 32 + read-write + 0x0 + 0xFF + + + SUPD1 + desc SUPD1 + 0 + 0 + read-write + + + SUPD2 + desc SUPD2 + 1 + 1 + read-write + + + SUPD3 + desc SUPD3 + 2 + 2 + read-write + + + SUPD4 + desc SUPD4 + 3 + 3 + read-write + + + SUPD5 + desc SUPD5 + 4 + 4 + read-write + + + SUPD6 + desc SUPD6 + 5 + 5 + read-write + + + SUPD7 + desc SUPD7 + 6 + 6 + read-write + + + SUPD8 + desc SUPD8 + 7 + 7 + read-write + + + + + + + TMRA1 + desc TMRA + 0x4003A000 + + 0x0 + 0x150 + + + + CNTER + desc CNTER + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 16 + read-write + 0xFFFF + 0xFFFF + + + PER + desc PER + 15 + 0 + read-write + + + + + CMPAR1 + desc CMPAR1 + 0x40 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR2 + desc CMPAR2 + 0x44 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR3 + desc CMPAR3 + 0x48 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR4 + desc CMPAR4 + 0x4C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + BCSTR + desc BCSTR + 0x80 + 16 + read-write + 0x2 + 0xF1FF + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + SYNST + desc SYNST + 3 + 3 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + OVSTP + desc OVSTP + 8 + 8 + read-write + + + ITENOVF + desc ITENOVF + 12 + 12 + read-write + + + ITENUDF + desc ITENUDF + 13 + 13 + read-write + + + OVFF + desc OVFF + 14 + 14 + read-write + + + UDFF + desc UDFF + 15 + 15 + read-write + + + + + HCONR + desc HCONR + 0x84 + 16 + read-write + 0x0 + 0xF777 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTP0 + desc HSTP0 + 4 + 4 + read-write + + + HSTP1 + desc HSTP1 + 5 + 5 + read-write + + + HSTP2 + desc HSTP2 + 6 + 6 + read-write + + + HCLE0 + desc HCLE0 + 8 + 8 + read-write + + + HCLE1 + desc HCLE1 + 9 + 9 + read-write + + + HCLE2 + desc HCLE2 + 10 + 10 + read-write + + + HCLE3 + desc HCLE3 + 12 + 12 + read-write + + + HCLE4 + desc HCLE4 + 13 + 13 + read-write + + + HCLE5 + desc HCLE5 + 14 + 14 + read-write + + + HCLE6 + desc HCLE6 + 15 + 15 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 16 + read-write + 0x0 + 0x1FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP12 + desc HCUP12 + 12 + 12 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 16 + read-write + 0x0 + 0x1FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO12 + desc HCDO12 + 12 + 12 + read-write + + + + + ICONR + desc ICONR + 0x90 + 16 + read-write + 0x0 + 0xF + + + ITEN1 + desc ITEN1 + 0 + 0 + read-write + + + ITEN2 + desc ITEN2 + 1 + 1 + read-write + + + ITEN3 + desc ITEN3 + 2 + 2 + read-write + + + ITEN4 + desc ITEN4 + 3 + 3 + read-write + + + + + ECONR + desc ECONR + 0x94 + 16 + read-write + 0x0 + 0xF + + + ETEN1 + desc ETEN1 + 0 + 0 + read-write + + + ETEN2 + desc ETEN2 + 1 + 1 + read-write + + + ETEN3 + desc ETEN3 + 2 + 2 + read-write + + + ETEN4 + desc ETEN4 + 3 + 3 + read-write + + + + + FCONR + desc FCONR + 0x98 + 16 + read-write + 0x0 + 0x7707 + + + NOFIENTG + desc NOFIENTG + 0 + 0 + read-write + + + NOFICKTG + desc NOFICKTG + 2 + 1 + read-write + + + NOFIENCA + desc NOFIENCA + 8 + 8 + read-write + + + NOFICKCA + desc NOFICKCA + 10 + 9 + read-write + + + NOFIENCB + desc NOFIENCB + 12 + 12 + read-write + + + NOFICKCB + desc NOFICKCB + 14 + 13 + read-write + + + + + STFLR + desc STFLR + 0x9C + 16 + read-write + 0x0 + 0xF + + + CMPF1 + desc CMPF1 + 0 + 0 + read-write + + + CMPF2 + desc CMPF2 + 1 + 1 + read-write + + + CMPF3 + desc CMPF3 + 2 + 2 + read-write + + + CMPF4 + desc CMPF4 + 3 + 3 + read-write + + + + + BCONR1 + desc BCONR1 + 0xC0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR2 + desc BCONR2 + 0xC8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + CCONR1 + desc CCONR1 + 0x100 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR2 + desc CCONR2 + 0x104 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR3 + desc CCONR3 + 0x108 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR4 + desc CCONR4 + 0x10C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + PCONR1 + desc PCONR1 + 0x140 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR2 + desc PCONR2 + 0x144 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR3 + desc PCONR3 + 0x148 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR4 + desc PCONR4 + 0x14C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + + + TMRA10 + desc TMRA + 0x40027400 + + 0x0 + 0x150 + + + + TMRA11 + desc TMRA + 0x40027800 + + 0x0 + 0x150 + + + + TMRA12 + desc TMRA + 0x40027C00 + + 0x0 + 0x150 + + + + TMRA2 + desc TMRA + 0x4003A400 + + 0x0 + 0x150 + + + + TMRA3 + desc TMRA + 0x4003A800 + + 0x0 + 0x150 + + + + TMRA4 + desc TMRA + 0x4003AC00 + + 0x0 + 0x150 + + + + TMRA5 + desc TMRA + 0x40026000 + + 0x0 + 0x150 + + + + TMRA6 + desc TMRA + 0x40026400 + + 0x0 + 0x150 + + + + TMRA7 + desc TMRA + 0x40026800 + + 0x0 + 0x150 + + + + TMRA8 + desc TMRA + 0x40026C00 + + 0x0 + 0x150 + + + + TMRA9 + desc TMRA + 0x40027000 + + 0x0 + 0x150 + + + + TRNG + desc TRNG + 0x40042000 + + 0x0 + 0x14 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EN + desc EN + 0 + 0 + read-write + + + RUN + desc RUN + 1 + 1 + read-write + + + + + MR + desc MR + 0x4 + 32 + read-write + 0x12 + 0x1D + + + LOAD + desc LOAD + 0 + 0 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + + + DR0 + desc DR0 + 0xC + 32 + read-only + 0x8000000 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x10 + 32 + read-only + 0x8000200 + 0xFFFFFFFF + + + + + USART1 + desc USART + 0x4001CC00 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART10 + desc USART10 + 0x40021C00 + + 0x0 + 0x20 + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x106FB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + BE + desc BE + 4 + 4 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + WKUP + desc WKUP + 9 + 9 + read-only + + + LBD + desc LBD + 10 + 10 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFF00 + 0xFF00 + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xD1EB96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CBE + desc CBE + 21 + 21 + read-write + + + CWKUP + desc CWKUP + 22 + 22 + read-write + + + CLBD + desc CLBD + 23 + 23 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x379FF + + + MPE + desc MPE + 0 + 0 + read-write + + + WKUPIE + desc WKUPIE + 1 + 1 + read-write + + + BEIE + desc BEIE + 2 + 2 + read-write + + + BEE + desc BEE + 3 + 3 + read-write + + + LBDIE + desc LBDIE + 4 + 4 + read-write + + + LBDL + desc LBDL + 5 + 5 + read-write + + + SBKL + desc SBKL + 7 + 6 + read-write + + + WKUPE + desc WKUPE + 8 + 8 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + LINEN + desc LINEN + 14 + 14 + read-write + + + SBK + desc SBK + 16 + 16 + read-write + + + SBKM + desc SBKM + 17 + 17 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0x318 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + LOOP + desc LOOP + 4 + 4 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0xF + + + PSC + desc PSC + 1 + 0 + read-write + + + LBMPSC + desc LBMPSC + 3 + 2 + read-write + + + + + LBMC + desc LBMC + 0x1C + 32 + read-only + 0x0 + 0xFFFF + + + LBMC + desc LBMC + 15 + 0 + read-only + + + + + + + USART2 + desc USART + 0x4001D000 + + 0x0 + 0x1C + + + + USART3 + desc USART + 0x4001D400 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x100EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF10B96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART4 + desc USART + 0x4001D800 + + 0x0 + 0x1C + + + + USART5 + desc USART + 0x4001DC00 + + 0x0 + 0x20 + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x106FB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + BE + desc BE + 4 + 4 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + WKUP + desc WKUP + 9 + 9 + read-only + + + LBD + desc LBD + 10 + 10 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFF00 + 0xFF00 + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xD1EB96FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CBE + desc CBE + 21 + 21 + read-write + + + CWKUP + desc CWKUP + 22 + 22 + read-write + + + CLBD + desc CLBD + 23 + 23 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x379FF + + + MPE + desc MPE + 0 + 0 + read-write + + + WKUPIE + desc WKUPIE + 1 + 1 + read-write + + + BEIE + desc BEIE + 2 + 2 + read-write + + + BEE + desc BEE + 3 + 3 + read-write + + + LBDIE + desc LBDIE + 4 + 4 + read-write + + + LBDL + desc LBDL + 5 + 5 + read-write + + + SBKL + desc SBKL + 7 + 6 + read-write + + + WKUPE + desc WKUPE + 8 + 8 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + LINEN + desc LINEN + 14 + 14 + read-write + + + SBK + desc SBK + 16 + 16 + read-write + + + SBKM + desc SBKM + 17 + 17 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0x318 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + LOOP + desc LOOP + 4 + 4 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0xF + + + PSC + desc PSC + 1 + 0 + read-write + + + LBMPSC + desc LBMPSC + 3 + 2 + read-write + + + + + LBMC + desc LBMC + 0x1C + 32 + read-only + 0x0 + 0xFFFF + + + LBMC + desc LBMC + 15 + 0 + read-only + + + + + + + USART6 + desc USART6 + 0x40020C00 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART7 + desc USART + 0x40021000 + + 0x0 + 0x1C + + + + USART8 + desc USART + 0x40021400 + + 0x0 + 0x1C + + + + USART9 + desc USART + 0x40021800 + + 0x0 + 0x1C + + + + USBFS + desc USBFS + 0x40080000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0x1440 + 0x60003C47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFF7CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + LPMINT + desc LPMINT + 27 + 27 + read-write + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xFF7CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + LPMINTM + desc LPMINTM + 27 + 27 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x280 + 0x7FF + + + RXFD + desc RXFD + 10 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x2800280 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80280 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + LPMEN + desc LPMEN + 0 + 0 + read-write + + + LPMACK + desc LPMACK + 1 + 1 + read-write + + + BSEL + desc BSEL + 5 + 2 + read-write + + + REMWAKE + desc REMWAKE + 6 + 6 + read-write + + + L1SSEN + desc L1SSEN + 7 + 7 + read-write + + + BESLTHRS + desc BESLTHRS + 11 + 8 + read-write + + + L1DSEN + desc L1DSEN + 12 + 12 + read-write + + + LPMRSP + desc LPMRSP + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RSMOK + desc L1RSMOK + 16 + 16 + read-only + + + LPMCHIDX + desc LPMCHIDX + 20 + 17 + read-write + + + LPMRCNT + desc LPMRCNT + 23 + 21 + read-write + + + SENDLPM + desc SENDLPM + 24 + 24 + read-write + + + LPMRCNTSTS + desc LPMRCNTSTS + 27 + 25 + read-only + + + ENBSEL + desc ENBSEL + 28 + 28 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x2800500 + 0xFFFFFFFF + + + PTXSA + desc PTXSA + 15 + 0 + read-write + + + PTXFD + desc PTXFD + 31 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x2800500 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x2800780 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x2800A00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x2800C80 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x2800F00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x2801180 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x2801400 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x2801680 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x2801900 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 0x128 + 32 + read-write + 0x2801B80 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF11 + desc DIEPTXF11 + 0x12C + 32 + read-write + 0x2801E00 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF12 + desc DIEPTXF12 + 0x130 + 32 + read-write + 0x2802080 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF13 + desc DIEPTXF13 + 0x134 + 32 + read-write + 0x2802300 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF14 + desc DIEPTXF14 + 0x138 + 32 + read-write + 0x2802580 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF15 + desc DIEPTXF15 + 0x13C + 32 + read-write + 0x2802800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80280 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFFF + + + HAINT + desc HAINT + 15 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFFF + + + HAINTM + desc HAINTM + 15 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x61DCF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR12 + desc HCCHAR12 + 0x680 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT12 + desc HCINT12 + 0x688 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK12 + desc HCINTMSK12 + 0x68C + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ12 + desc HCTSIZ12 + 0x690 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA12 + desc HCDMA12 + 0x694 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR13 + desc HCCHAR13 + 0x6A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT13 + desc HCINT13 + 0x6A8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK13 + desc HCINTMSK13 + 0x6AC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ13 + desc HCTSIZ13 + 0x6B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA13 + desc HCDMA13 + 0x6B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR14 + desc HCCHAR14 + 0x6C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT14 + desc HCINT14 + 0x6C8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK14 + desc HCINTMSK14 + 0x6CC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ14 + desc HCTSIZ14 + 0x6D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA14 + desc HCDMA14 + 0x6D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR15 + desc HCCHAR15 + 0x6E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT15 + desc HCINT15 + 0x6E8 + 32 + read-write + 0x0 + 0x7BF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK15 + desc HCINTMSK15 + 0x6EC + 32 + read-write + 0x0 + 0x7BF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ15 + desc HCTSIZ15 + 0x6F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA15 + desc HCDMA15 + 0x6F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8200000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xF8F + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + SGINAK + desc SGINAK + 7 + 7 + write-only + + + CGINAK + desc CGINAK + 8 + 8 + write-only + + + SGONAK + desc SGONAK + 9 + 9 + write-only + + + CGONAK + desc CGONAK + 10 + 10 + write-only + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0xFFFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + LNSTS + desc LNSTS + 23 + 22 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x207B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + ITTXFEMSK + desc ITTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x1B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINT + desc IEPINT + 15 + 0 + read-write + + + OEPINT + desc OEPINT + 31 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINTM + desc IEPINTM + 15 + 0 + read-write + + + OEPINTM + desc OEPINTM + 31 + 16 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0xFFFF + + + INEPTXFEM + desc INEPTXFEM + 15 + 0 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-write + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ11 + desc DIEPTSIZ11 + 0xA70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT12 + desc DIEPINT12 + 0xA88 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ12 + desc DIEPTSIZ12 + 0xA90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT13 + desc DIEPINT13 + 0xAA8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ13 + desc DIEPTSIZ13 + 0xAB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT14 + desc DIEPINT14 + 0xAC8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ14 + desc DIEPTSIZ14 + 0xAD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA14 + desc DIEPDMA14 + 0xAD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS14 + desc DTXFSTS14 + 0xAD8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL15 + desc DIEPCTL15 + 0xAE0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT15 + desc DIEPINT15 + 0xAE8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ15 + desc DIEPTSIZ15 + 0xAF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x280 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-write + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL6 + desc DOEPCTL6 + 0xBC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT6 + desc DOEPINT6 + 0xBC8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ6 + desc DOEPTSIZ6 + 0xBD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA6 + desc DOEPDMA6 + 0xBD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL7 + desc DOEPCTL7 + 0xBE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT7 + desc DOEPINT7 + 0xBE8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ7 + desc DOEPTSIZ7 + 0xBF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA7 + desc DOEPDMA7 + 0xBF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL8 + desc DOEPCTL8 + 0xC00 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT8 + desc DOEPINT8 + 0xC08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ8 + desc DOEPTSIZ8 + 0xC10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA8 + desc DOEPDMA8 + 0xC14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL9 + desc DOEPCTL9 + 0xC20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT9 + desc DOEPINT9 + 0xC28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ9 + desc DOEPTSIZ9 + 0xC30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA9 + desc DOEPDMA9 + 0xC34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL10 + desc DOEPCTL10 + 0xC40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT10 + desc DOEPINT10 + 0xC48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ10 + desc DOEPTSIZ10 + 0xC50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA10 + desc DOEPDMA10 + 0xC54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL11 + desc DOEPCTL11 + 0xC60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT11 + desc DOEPINT11 + 0xC68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ11 + desc DOEPTSIZ11 + 0xC70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA11 + desc DOEPDMA11 + 0xC74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL12 + desc DOEPCTL12 + 0xC80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT12 + desc DOEPINT12 + 0xC88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ12 + desc DOEPTSIZ12 + 0xC90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA12 + desc DOEPDMA12 + 0xC94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL13 + desc DOEPCTL13 + 0xCA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT13 + desc DOEPINT13 + 0xCA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ13 + desc DOEPTSIZ13 + 0xCB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ14 + desc DOEPTSIZ14 + 0xCD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0xE3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + ENL1GTG + desc ENL1GTG + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-write + + + SUSP + desc SUSP + 7 + 7 + read-write + + + + + + + USBHS + desc USBHS + 0x400C0000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0x1410 + 0x63BEBC47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + PHYLPCS + desc PHYLPCS + 15 + 15 + read-write + + + ULFSLS + desc ULFSLS + 17 + 17 + read-write + + + ULPIAR + desc ULPIAR + 18 + 18 + read-write + + + ULPICSM + desc ULPICSM + 19 + 19 + read-write + + + ULPIEVBUSD + desc ULPIEVBUSD + 20 + 20 + read-write + + + ULPIEVBUSI + desc ULPIEVBUSI + 21 + 21 + read-write + + + PCCI + desc PCCI + 23 + 23 + read-write + + + PTCI + desc PTCI + 24 + 24 + read-write + + + ULPIPD + desc ULPIPD + 25 + 25 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFF7CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + LPMINT + desc LPMINT + 27 + 27 + read-write + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xFF7CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + LPMINTM + desc LPMINTM + 27 + 27 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x800 + 0xFFF + + + RXFD + desc RXFD + 11 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x8000800 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80800 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + LPMEN + desc LPMEN + 0 + 0 + read-write + + + LPMACK + desc LPMACK + 1 + 1 + read-write + + + BSEL + desc BSEL + 5 + 2 + read-write + + + REMWAKE + desc REMWAKE + 6 + 6 + read-write + + + L1SSEN + desc L1SSEN + 7 + 7 + read-write + + + BESLTHRS + desc BESLTHRS + 11 + 8 + read-write + + + L1DSEN + desc L1DSEN + 12 + 12 + read-write + + + LPMRSP + desc LPMRSP + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RSMOK + desc L1RSMOK + 16 + 16 + read-only + + + LPMCHIDX + desc LPMCHIDX + 20 + 17 + read-write + + + LPMRCNT + desc LPMRCNT + 23 + 21 + read-write + + + SENDLPM + desc SENDLPM + 24 + 24 + read-write + + + LPMRCNTSTS + desc LPMRCNTSTS + 27 + 25 + read-only + + + ENBSEL + desc ENBSEL + 28 + 28 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x8001000 + 0xFFFFFFFF + + + PTXSA + desc PTXSA + 15 + 0 + read-write + + + PTXFD + desc PTXFD + 31 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x8001000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x8001800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x8002000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x8002800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x8003000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x8003800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x8004000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x8004800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x8005000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 0x128 + 32 + read-write + 0x8005800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF11 + desc DIEPTXF11 + 0x12C + 32 + read-write + 0x8006000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF12 + desc DIEPTXF12 + 0x130 + 32 + read-write + 0x8006800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF13 + desc DIEPTXF13 + 0x134 + 32 + read-write + 0x8007000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF14 + desc DIEPTXF14 + 0x138 + 32 + read-write + 0x8007800 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + DIEPTXF15 + desc DIEPTXF15 + 0x13C + 32 + read-write + 0x8008000 + 0xFFFFFFFF + + + INEPTXSA + desc INEPTXSA + 15 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 31 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80800 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFFF + + + HAINT + desc HAINT + 15 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFFF + + + HAINTM + desc HAINTM + 15 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x7FDFF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + POCA + desc POCA + 4 + 4 + read-write + + + POCCHNG + desc POCCHNG + 5 + 5 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PTCTL + desc PTCTL + 16 + 13 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT0 + desc HCSPLT0 + 0x504 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT1 + desc HCSPLT1 + 0x524 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT2 + desc HCSPLT2 + 0x544 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT3 + desc HCSPLT3 + 0x564 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT4 + desc HCSPLT4 + 0x584 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT5 + desc HCSPLT5 + 0x5A4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT6 + desc HCSPLT6 + 0x5C4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT7 + desc HCSPLT7 + 0x5E4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT8 + desc HCSPLT8 + 0x604 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT9 + desc HCSPLT9 + 0x624 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT10 + desc HCSPLT10 + 0x644 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT11 + desc HCSPLT11 + 0x664 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR12 + desc HCCHAR12 + 0x680 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT12 + desc HCSPLT12 + 0x684 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT12 + desc HCINT12 + 0x688 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK12 + desc HCINTMSK12 + 0x68C + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ12 + desc HCTSIZ12 + 0x690 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA12 + desc HCDMA12 + 0x694 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR13 + desc HCCHAR13 + 0x6A0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT13 + desc HCSPLT13 + 0x6A4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT13 + desc HCINT13 + 0x6A8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK13 + desc HCINTMSK13 + 0x6AC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ13 + desc HCTSIZ13 + 0x6B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA13 + desc HCDMA13 + 0x6B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR14 + desc HCCHAR14 + 0x6C0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT14 + desc HCSPLT14 + 0x6C4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT14 + desc HCINT14 + 0x6C8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK14 + desc HCINTMSK14 + 0x6CC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ14 + desc HCTSIZ14 + 0x6D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA14 + desc HCDMA14 + 0x6D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR15 + desc HCCHAR15 + 0x6E0 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + MC + desc MC + 21 + 20 + read-write + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT15 + desc HCSPLT15 + 0x6E4 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPLSPLT + desc COMPLSPLT + 16 + 16 + read-write + + + SPLITEN + desc SPLITEN + 31 + 31 + read-write + + + + + HCINT15 + desc HCINT15 + 0x6E8 + 32 + read-write + 0x0 + 0x7FF + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK15 + desc HCINTMSK15 + 0x6EC + 32 + read-write + 0x0 + 0x7FF + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + AHBERRM + desc AHBERRM + 2 + 2 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + NYETM + desc NYETM + 6 + 6 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ15 + desc HCTSIZ15 + 0x6F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + DOPING + desc DOPING + 31 + 31 + read-write + + + + + HCDMA15 + desc HCDMA15 + 0x6F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8220000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xFFF + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + TCTL + desc TCTL + 6 + 4 + read-write + + + SGINAK + desc SGINAK + 7 + 7 + read-write + + + CGINAK + desc CGINAK + 8 + 8 + read-write + + + SGONAK + desc SGONAK + 9 + 9 + read-write + + + CGONAK + desc CGONAK + 10 + 10 + read-write + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0xFFFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + LNSTS + desc LNSTS + 23 + 22 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x217B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + TTXFEMSK + desc TTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + TXFURM + desc TXFURM + 8 + 8 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x415B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + OPEM + desc OPEM + 8 + 8 + read-write + + + NYETM + desc NYETM + 14 + 14 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINT + desc IEPINT + 15 + 0 + read-write + + + OEPINT + desc OEPINT + 31 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IEPINTM + desc IEPINTM + 15 + 0 + read-write + + + OEPINTM + desc OEPINTM + 31 + 16 + read-write + + + + + DTHRCTL + desc DTHRCTL + 0x830 + 32 + read-write + 0xC100020 + 0xBFF07FF + + + NONISOTHREN + desc NONISOTHREN + 0 + 0 + read-write + + + ISOTHREN + desc ISOTHREN + 1 + 1 + read-write + + + TXTHRLEN + desc TXTHRLEN + 10 + 2 + read-write + + + RXTHREN + desc RXTHREN + 16 + 16 + read-write + + + RXTHRLEN + desc RXTHRLEN + 25 + 17 + read-write + + + ARPEN + desc ARPEN + 27 + 27 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0xFFFF + + + INEPTXFEM + desc INEPTXFEM + 15 + 0 + read-write + + + + + DEACHINT + desc DEACHINT + 0x838 + 32 + read-write + 0x0 + 0x20002 + + + IEP1INT + desc IEP1INT + 1 + 1 + read-write + + + OEP1INT + desc OEP1INT + 17 + 17 + read-write + + + + + DEACHINTMSK + desc DEACHINTMSK + 0x83C + 32 + read-write + 0x0 + 0x20002 + + + IEP1INTM + desc IEP1INTM + 1 + 1 + read-write + + + OEP1INTM + desc OEP1INTM + 17 + 17 + read-write + + + + + DIEPEACHMSK1 + desc DIEPEACHMSK1 + 0x844 + 32 + read-write + 0x0 + 0x217B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + TTXFEMSK + desc TTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + TXFURM + desc TXFURM + 8 + 8 + read-write + + + NAKM + desc NAKM + 13 + 13 + read-write + + + + + DOEPEACHMSK1 + desc DOEPEACHMSK1 + 0x884 + 32 + read-write + 0x0 + 0x415B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + OPEM + desc OPEM + 8 + 8 + read-write + + + NYETM + desc NYETM + 14 + 14 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-only + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ11 + desc DIEPTSIZ11 + 0xA70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT12 + desc DIEPINT12 + 0xA88 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ12 + desc DIEPTSIZ12 + 0xA90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT13 + desc DIEPINT13 + 0xAA8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ13 + desc DIEPTSIZ13 + 0xAB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT14 + desc DIEPINT14 + 0xAC8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ14 + desc DIEPTSIZ14 + 0xAD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA14 + desc DIEPDMA14 + 0xAD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS14 + desc DTXFSTS14 + 0xAD8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL15 + desc DIEPCTL15 + 0xAE0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT15 + desc DIEPINT15 + 0xAE8 + 32 + read-write + 0x80 + 0x39DB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + TXFIFOUDRN + desc TXFIFOUDRN + 8 + 8 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BERR + desc BERR + 12 + 12 + read-write + + + NAK + desc NAK + 13 + 13 + read-write + + + + + DIEPTSIZ15 + desc DIEPTSIZ15 + 0xAF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MCNT + desc MCNT + 30 + 29 + read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-only + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL6 + desc DOEPCTL6 + 0xBC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT6 + desc DOEPINT6 + 0xBC8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ6 + desc DOEPTSIZ6 + 0xBD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA6 + desc DOEPDMA6 + 0xBD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL7 + desc DOEPCTL7 + 0xBE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT7 + desc DOEPINT7 + 0xBE8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ7 + desc DOEPTSIZ7 + 0xBF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA7 + desc DOEPDMA7 + 0xBF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL8 + desc DOEPCTL8 + 0xC00 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT8 + desc DOEPINT8 + 0xC08 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ8 + desc DOEPTSIZ8 + 0xC10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA8 + desc DOEPDMA8 + 0xC14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL9 + desc DOEPCTL9 + 0xC20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT9 + desc DOEPINT9 + 0xC28 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ9 + desc DOEPTSIZ9 + 0xC30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA9 + desc DOEPDMA9 + 0xC34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL10 + desc DOEPCTL10 + 0xC40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT10 + desc DOEPINT10 + 0xC48 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ10 + desc DOEPTSIZ10 + 0xC50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA10 + desc DOEPDMA10 + 0xC54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL11 + desc DOEPCTL11 + 0xC60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT11 + desc DOEPINT11 + 0xC68 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ11 + desc DOEPTSIZ11 + 0xC70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA11 + desc DOEPDMA11 + 0xC74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL12 + desc DOEPCTL12 + 0xC80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT12 + desc DOEPINT12 + 0xC88 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ12 + desc DOEPTSIZ12 + 0xC90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA12 + desc DOEPDMA12 + 0xC94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL13 + desc DOEPCTL13 + 0xCA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT13 + desc DOEPINT13 + 0xCA8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ13 + desc DOEPTSIZ13 + 0xCB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ14 + desc DOEPTSIZ14 + 0xCD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0x405B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + NYET + desc NYET + 14 + 14 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID_STUPCNT + desc RXDPID_STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0xE3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + ENL1GTG + desc ENL1GTG + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-write + + + SUSP + desc SUSP + 7 + 7 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c new file mode 100644 index 0000000000..b0121ba884 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c @@ -0,0 +1,241 @@ +/** + ******************************************************************************* + * @file system_hc32f4a0.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +#include "hc32_ll_def.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F4A0_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F4A0_System_Local_Macros HC32F4A0 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif + +/* Re-define main function */ +#ifndef RE_DEFINE_MAIN +#define RE_DEFINE_MAIN (1) /*!< Non-zero value to re-define main function. */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +#if defined (ROM_EXT_QSPI) + SystemInit_QspiMem(); +#endif /* ROM_EXT_QSPI */ + /* Configure the Vector Table relocation */ + SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use PLLH */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS; + pllp = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS; + pllm = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS; + if (0UL == bCM_CMU->PLLHCFGR_b.PLLSRC) { /* use external high speed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +#if (RE_DEFINE_MAIN) +#if (defined (__CC_ARM) || defined (__CLANG_ARM)) || \ + (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemCoreClockUpdate(); + $Super$$main(); + return 0; +} +#elif defined (__ICCARM__) +extern int32_t main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +int __low_level_init(void) +{ + /* call IAR table copy function. */ + __iar_data_init3(); + SystemCoreClockUpdate(); + main(); + return 0; +} +#endif +#endif /* RE_DEFINE_MAIN */ + +#if defined (ROM_EXT_QSPI) +/** + * @brief Initialize the QSPI memory. + * @param None + * @retval None + */ +__WEAKDEF void SystemInit_QspiMem(void) +{ + /* QSPI configure */ + CM_GPIO->PWPR = 0xA501U; + /* High driver */ + CM_GPIO->PCRC7 = 0x0120U; + CM_GPIO->PCRC6 = 0x0120U; + CM_GPIO->PCRB13 = 0x0120U; + CM_GPIO->PCRB12 = 0x0120U; + CM_GPIO->PCRB10 = 0x0120U; + CM_GPIO->PCRB2 = 0x0120U; + /* Set function */ + CM_GPIO->PFSRC7 = 0x0012U; + CM_GPIO->PFSRC6 = 0x0012U; + CM_GPIO->PFSRB13 = 0x0012U; + CM_GPIO->PFSRB12 = 0x0012U; + CM_GPIO->PFSRB10 = 0x0012U; + CM_GPIO->PFSRB2 = 0x0012U; + /* qspi configure */ + CM_PWC->FCG1 &= ~0x00000008UL; + CM_QSPI->CR = 0x0002000D; + CM_QSPI->CSCR = 0x00000001; + CM_QSPI->FCR = 0x00008332; + /* XIP */ + CM_QSPI->XCMD = 0x20; + CM_QSPI->CR |= QSPI_CR_XIPE; +} +#endif /* ROM_EXT_QSPI */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_common_tables.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_common_tables.h new file mode 100644 index 0000000000..721b18dd2d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_common_tables.h @@ -0,0 +1,517 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_const_structs.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_const_structs.h new file mode 100644 index 0000000000..83984c40cd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_const_structs.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_helium_utils.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_helium_utils.h new file mode 100644 index 0000000000..7609d329f0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_helium_utils.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * $Date: 09. September 2019 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) + + +#include "arm_common_tables.h" + +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#endif diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_math.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_math.h new file mode 100644 index 0000000000..48bee62cd9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_math.h @@ -0,0 +1,8970 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * + * Here is the list of pre-built libraries : + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M7, A5 are tested. + * + * + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * There is also a work in progress cmake build. The README file is giving more details. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_FLOAT16: + * + * Float16 implementations of some algorithms (Requires MVE extension). + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static __attribute__((inline)) +#define __STATIC_INLINE static __attribute__((inline)) +#pragma GCC diagnostic ignored "-Wunused-function" +#pragma GCC diagnostic ignored "-Wattributes" + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MAX ((float16_t)FLT_MAX) +#endif + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MIN (-(float16_t)FLT_MAX) +#endif + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMAX ((float16_t)FLT_MAX) +#endif + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMIN ((float16_t)0.0) +#endif + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) +#include +#endif + +#if defined (ARM_MATH_HELIUM) + #define ARM_MATH_MVEF + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_MVEF) + #define ARM_MATH_MVEI + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) +#include +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macros for complex numbers + */ + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; +#endif + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; +#endif + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; +#endif + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (val & 0x0FFFF); + (*pQ15)[1] = (val >> 16) & 0x0FFFF; +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = val & 0x0FFFF; + pQ15[1] = val >> 16; +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = val & 0x0FF; + (*pQ7)[1] = (val >> 8) & 0x0FF; + (*pQ7)[2] = (val >> 16) & 0x0FF; + (*pQ7)[3] = (val >> 24) & 0x0FF; + +#endif + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_mve_tables.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_mve_tables.h new file mode 100644 index 0000000000..4d2c135ac6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_mve_tables.h @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 08. January 2020 + * $Revision: V1.7.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + + #include "arm_math.h" + + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_vec_math.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_vec_math.h new file mode 100644 index 0000000000..0ce9464bcb --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/arm_vec_math.h @@ -0,0 +1,372 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 15. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cachel1_armv7.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cachel1_armv7.h new file mode 100644 index 0000000000..d2c3e2291f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armcc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armcc.h new file mode 100644 index 0000000000..237ff6ec3e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang.h new file mode 100644 index 0000000000..90de9dbf8f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..0e5c7349d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_compiler.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_gcc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_iccarm.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_version.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_version.h new file mode 100644 index 0000000000..2f048e4552 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv81mml.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv81mml.h new file mode 100644 index 0000000000..1ad19e215a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mbl.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mbl.h new file mode 100644 index 0000000000..932d3d188b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mml.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mml.h new file mode 100644 index 0000000000..71f000bcad --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0.h new file mode 100644 index 0000000000..6441ff3419 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0plus.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0plus.h new file mode 100644 index 0000000000..4e7179a614 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm1.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm23.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm23.h new file mode 100644 index 0000000000..55fff99509 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm3.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm3.h new file mode 100644 index 0000000000..24453a8863 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm33.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm33.h new file mode 100644 index 0000000000..13359be3ed --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm35p.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm35p.h new file mode 100644 index 0000000000..6a5f6ad147 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm35p.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm4.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm4.h new file mode 100644 index 0000000000..4e0e886697 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm55.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm55.h new file mode 100644 index 0000000000..6efaa3f842 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm55.h @@ -0,0 +1,4215 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm7.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm7.h new file mode 100644 index 0000000000..e1c31c275d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_cm7.h @@ -0,0 +1,2362 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc000.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc000.h new file mode 100644 index 0000000000..dbc755fff3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc300.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc300.h new file mode 100644 index 0000000000..e8914ba601 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv7.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv7.h new file mode 100644 index 0000000000..791a8dae65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv8.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv8.h new file mode 100644 index 0000000000..ef44ad01df --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/pmu_armv8.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/pmu_armv8.h new file mode 100644 index 0000000000..dbd39d20c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/tz_context.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h new file mode 100644 index 0000000000..c8bfbd921f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h @@ -0,0 +1,369 @@ +/** + ******************************************************************************* + * @file hc32_ll.h + * @brief This file contains HC32 Series Device Driver Library file call + * management. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_H__ +#define __HC32_LL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_Global + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Global_Macros LL Global Macros + * @{ + */ + +/** + * @defgroup Peripheral_Register_WP_Local_Macros Peripheral Register Write Protection Local Macros + * @{ + */ +#define LL_PERIPH_EFM (1UL << 0U) +#define LL_PERIPH_FCG (1UL << 1U) +#define LL_PERIPH_GPIO (1UL << 2U) +#define LL_PERIPH_INTC (1UL << 3U) +#define LL_PERIPH_LVD (1UL << 4U) +#define LL_PERIPH_MPU (1UL << 5U) +#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U) +#define LL_PERIPH_SRAM (1UL << 7U) +#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \ + LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU) +/** + * @} + */ + +/* Defined use Device Driver Library */ +#if !defined (USE_DDL_DRIVER) +/** + * @brief Comment the line below if you will not use the Device Driver Library. + * In this case, the application code will be based on direct access to + * peripherals registers. + */ +/* #define USE_DDL_DRIVER */ +#endif /* USE_DDL_DRIVER */ + +/** +* @defgroup HC32_Series_DDL_Version HC32 Series Device Driver Library Version +* @{ +*/ +#define HC32_DDL_VER_MAIN 0x01U /*!< [31:24] main version */ +#define HC32_DDL_VER_SUB1 0x00U /*!< [23:16] sub1 version */ +#define HC32_DDL_VER_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_VER_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_VER ((HC32_DDL_VER_MAIN << 24) | (HC32_DDL_VER_SUB1 << 16) | \ + (HC32_DDL_VER_SUB2 << 8 ) | (HC32_DDL_VER_PATCH)) +/** + * @} + */ + +/** +* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version +* @{ +*/ +#define HC32_DDL_REV_MAIN 0x02U /*!< [31:24] main version */ +#define HC32_DDL_REV_SUB1 0x00U /*!< [23:16] sub1 version */ +#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \ + (HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH)) +/** + * @} + */ + +/** + * @} + */ + +/* Use Device Driver Library */ +#if defined (USE_DDL_DRIVER) + +/** + * @brief Include peripheral module's header file + */ +#if (LL_ADC_ENABLE == DDL_ON) +#include "hc32_ll_adc.h" +#endif /* LL_ADC_ENABLE */ + +#if (LL_AES_ENABLE == DDL_ON) +#include "hc32_ll_aes.h" +#endif /* LL_AES_ENABLE */ + +#if (LL_AOS_ENABLE == DDL_ON) +#include "hc32_ll_aos.h" +#endif /* LL_AOS_ENABLE */ + +#if (LL_CAN_ENABLE == DDL_ON) +#include "hc32_ll_can.h" +#endif /* LL_CAN_ENABLE */ + +#if (LL_CLK_ENABLE == DDL_ON) +#include "hc32_ll_clk.h" +#endif /* LL_CLK_ENABLE */ + +#if (LL_CMP_ENABLE == DDL_ON) +#include "hc32_ll_cmp.h" +#endif /* LL_CMP_ENABLE */ + +#if (LL_CRC_ENABLE == DDL_ON) +#include "hc32_ll_crc.h" +#endif /* LL_CRC_ENABLE */ + +#if (LL_CTC_ENABLE == DDL_ON) +#include "hc32_ll_ctc.h" +#endif /* LL_CTC_ENABLE */ + +#if (LL_DAC_ENABLE == DDL_ON) +#include "hc32_ll_dac.h" +#endif /* LL_DAC_ENABLE */ + +#if (LL_DCU_ENABLE == DDL_ON) +#include "hc32_ll_dcu.h" +#endif /* LL_DCU_ENABLE */ + +#if (LL_DMA_ENABLE == DDL_ON) +#include "hc32_ll_dma.h" +#endif /* LL_DMA_ENABLE */ + +#if (LL_DMC_ENABLE == DDL_ON) +#include "hc32_ll_dmc.h" +#endif /* LL_DMC_ENABLE */ + +#if (LL_DVP_ENABLE == DDL_ON) +#include "hc32_ll_dvp.h" +#endif /* LL_DVP_ENABLE */ + +#if (LL_EFM_ENABLE == DDL_ON) +#include "hc32_ll_efm.h" +#endif /* LL_EFM_ENABLE */ + +#if (LL_EMB_ENABLE == DDL_ON) +#include "hc32_ll_emb.h" +#endif /* LL_EMB_ENABLE */ + +#if (LL_ETH_ENABLE == DDL_ON) +#include "hc32_ll_eth.h" +#endif /* LL_ETH_ENABLE */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +#include "hc32_ll_event_port.h" +#endif /* LL_EVENT_PORT_ENABLE */ + +#if (LL_FCG_ENABLE == DDL_ON) +#include "hc32_ll_fcg.h" +#endif /* LL_FCG_ENABLE */ + +#if (LL_FCM_ENABLE == DDL_ON) +#include "hc32_ll_fcm.h" +#endif /* LL_FCM_ENABLE */ + +#if (LL_FMAC_ENABLE == DDL_ON) +#include "hc32_ll_fmac.h" +#endif /* LL_FMAC_ENABLE */ + +#if (LL_GPIO_ENABLE == DDL_ON) +#include "hc32_ll_gpio.h" +#endif /* LL_GPIO_ENABLE */ + +#if (LL_HASH_ENABLE == DDL_ON) +#include "hc32_ll_hash.h" +#endif /* LL_HASH_ENABLE */ + +#if (LL_HRPWM_ENABLE == DDL_ON) +#include "hc32_ll_hrpwm.h" +#endif /* LL_HRPWM_ENABLE */ + +#if (LL_I2C_ENABLE == DDL_ON) +#include "hc32_ll_i2c.h" +#endif /* LL_I2C_ENABLE */ + +#if (LL_I2S_ENABLE == DDL_ON) +#include "hc32_ll_i2s.h" +#endif /* LL_I2S_ENABLE */ + +#if (LL_ICG_ENABLE == DDL_ON) +#include "hc32_ll_icg.h" +#endif /* LL_ICG_ENABLE */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32_ll_interrupts.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +#include "hc32f4a0_ll_interrupts_share.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32_ll_keyscan.h" +#endif /* LL_KEYSCAN_ENABLE */ + +#if (LL_MAU_ENABLE == DDL_ON) +#include "hc32_ll_mau.h" +#endif /* LL_MAU_ENABLE */ + +#if (LL_MPU_ENABLE == DDL_ON) +#include "hc32_ll_mpu.h" +#endif /* LL_MPU_ENABLE */ + +#if (LL_NFC_ENABLE == DDL_ON) +#include "hc32_ll_nfc.h" +#endif /* LL_NFC_ENABLE */ + +#if (LL_OTS_ENABLE == DDL_ON) +#include "hc32_ll_ots.h" +#endif /* LL_OTS_ENABLE */ + +#if (LL_PWC_ENABLE == DDL_ON) +#include "hc32_ll_pwc.h" +#endif /* LL_PWC_ENABLE */ + +#if (LL_QSPI_ENABLE == DDL_ON) +#include "hc32_ll_qspi.h" +#endif /* LL_QSPI_ENABLE */ + +#if (LL_RMU_ENABLE == DDL_ON) +#include "hc32_ll_rmu.h" +#endif /* LL_RMU_ENABLE */ + +#if (LL_RTC_ENABLE == DDL_ON) +#include "hc32_ll_rtc.h" +#endif /* LL_RTC_ENABLE */ + +#if (LL_SDIOC_ENABLE == DDL_ON) +#include "hc32_ll_sdioc.h" +#endif /* LL_SDIOC_ENABLE */ + +#if (LL_SMC_ENABLE == DDL_ON) +#include "hc32_ll_smc.h" +#endif /* LL_SMC_ENABLE */ + +#if (LL_SPI_ENABLE == DDL_ON) +#include "hc32_ll_spi.h" +#endif /* LL_SPI_ENABLE */ + +#if (LL_SRAM_ENABLE == DDL_ON) +#include "hc32_ll_sram.h" +#endif /* LL_SRAM_ENABLE */ + +#if (LL_SWDT_ENABLE == DDL_ON) +#include "hc32_ll_swdt.h" +#endif /* LL_SWDT_ENABLE */ + +#if (LL_TMR0_ENABLE == DDL_ON) +#include "hc32_ll_tmr0.h" +#endif /* LL_TMR0_ENABLE */ + +#if (LL_TMR2_ENABLE == DDL_ON) +#include "hc32_ll_tmr2.h" +#endif /* LL_TMR2_ENABLE */ + +#if (LL_TMR4_ENABLE == DDL_ON) +#include "hc32_ll_tmr4.h" +#endif /* LL_TMR4_ENABLE */ + +#if (LL_TMR6_ENABLE == DDL_ON) +#include "hc32_ll_tmr6.h" +#endif /* LL_TMR6_ENABLE */ + +#if (LL_TMRA_ENABLE == DDL_ON) +#include "hc32_ll_tmra.h" +#endif /* LL_TMRA_ENABLE */ + +#if (LL_TRNG_ENABLE == DDL_ON) +#include "hc32_ll_trng.h" +#endif /* LL_TRNG_ENABLE */ + +#if (LL_USART_ENABLE == DDL_ON) +#include "hc32_ll_usart.h" +#endif /* LL_USART_ENABLE */ + +#if (LL_UTILITY_ENABLE == DDL_ON) +#include "hc32_ll_utility.h" +#endif /* LL_UTILITY_ENABLE */ + +#if (LL_USB_ENABLE == DDL_ON) +#include "hc32_ll_usb.h" +#endif /* LL_USB_ENABLE */ + +#if (LL_WDT_ENABLE == DDL_ON) +#include "hc32_ll_wdt.h" +#endif /* LL_WDT_ENABLE */ + +#endif /* USE_DDL_DRIVER */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup LL_Global_Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral); +void LL_PERIPH_WP(uint32_t u32Peripheral); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h new file mode 100644 index 0000000000..f227715b26 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h @@ -0,0 +1,518 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.h + * @brief This file contains all the functions prototypes of the ADC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ADC_H__ +#define __HC32_LL_ADC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ADC + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Types ADC Global Types + * @{ + */ +/** + * @brief Structure definition of analog watchdog(AWD) configuration. + */ +typedef struct { + uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_AWD_Mode */ + uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */ + uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */ +} stc_adc_awd_config_t; + +/** + * @brief Structure definition of ADC initialization. + */ +typedef struct { + uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode. + This parameter can be a value of @ref ADC_Scan_Mode */ + uint16_t u16Resolution; /*!< Specifies the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t u16DataAlign; /*!< Specifies ADC data alignment. + This parameter can be a value of @ref ADC_Data_Align */ +} stc_adc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Macros ADC Global Macros + * @{ + */ + +/** + * @defgroup ADC_Sequence ADC Sequence + * @{ + */ +#define ADC_SEQ_A (0U) /*!< ADC sequence A. */ +#define ADC_SEQ_B (1U) /*!< ADC sequence B. */ +/** + * @} + */ + +/** + * @defgroup ADC_Channel ADC Channel + * @{ + */ +#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, ADC2 and ADC3. */ +#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, ADC2 and ADC3. */ +#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, ADC2 and ADC3. */ +#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, ADC2 and ADC3. */ +#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1 and ADC2, PF6 for ADC3. */ +#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1 and ADC2, PF7 for ADC3. */ +#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1 and ADC2, PF8 for ADC3. */ +#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1 and ADC2, PF9 for ADC3. */ +#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1 and ADC2, PF10 for ADC3. */ +#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1 and ADC2, PF3 for ADC3. */ +#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, ADC2 and ADC3. */ +#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, ADC2 and ADC3. */ +#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, ADC2 and ADC3. */ +#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, ADC2 and ADC3. */ +#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1 and ADC2, PF4 for ADC3. */ +#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1 and ADC2, PF5 for ADC3. */ +#define ADC_CH16 (16U) /*!< Default input pin: PH2 for ADC3, NOT support ADC1 and ADC2. */ +#define ADC_CH17 (17U) /*!< Default input pin: PH3 for ADC3, NOT support ADC1 and ADC2. */ +#define ADC_CH18 (18U) /*!< Default input pin: PH4 for ADC3, NOT support ADC1 and ADC2. */ +#define ADC_CH19 (19U) /*!< Default input pin: PH5 for ADC3, NOT support ADC1 and ADC2. */ +#define ADC_EXT_CH (ADC_CH15) /*!< ADC1, ADC2 and ADC3: analog input source can be external analog pin, + or internal reference voltage, or VBAT/2. */ +/** + * @} + */ + +/** + * @defgroup ADC_Scan_Mode ADC Scan Convert Mode + * @{ + */ +#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */ +#define ADC_MD_SEQA_CONT (ADC_CR0_MS_0) /*!< Sequence A continuous. Sequence B is disabled. */ +#define ADC_MD_SEQA_SEQB_SINGLESHOT (ADC_CR0_MS_1) /*!< Sequence A and B both single shot. */ +#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (ADC_CR0_MS) /*!< Sequence A continuous and sequence B single shot. */ +/** + * @} + */ + +/** + * @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */ +#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */ +#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */ +#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */ +/** + * @} + */ + +/** + * @defgroup ADC_Average_Count ADC Average Count + * @{ + */ +#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */ +#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */ +#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */ +#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */ +#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */ +#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */ +#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */ +#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */ +/** + * @} + */ + +/** + * @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode + * @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel. + * @{ + */ +#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */ +#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */ +/** + * @} + */ + +/** + * @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection + * @{ + */ +#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */ +#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR0(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR1(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_ITRGSELR0 and register ADCx_ITRGSELR1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Int_Type ADC Interrupt Type + * @{ + */ +#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */ +#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */ +#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Ext_Ch_Analog_Src ADC Extended Channel Analog Source + * @{ + */ +#define ADC_EXTCH_EXTERN_ANALOG_PIN (0x0U) /*!< The analog source of extended channel is external analog input pin. */ +#define ADC_EXTCH_INTERN_ANALOG_SRC (ADC_EXCHSELR_EXCHSEL) /*!< The analog source of extended channel is internal analog signal. */ +/** + * @} + */ + +/** + * @defgroup ADC_Status_Flag ADC Status Flag + * @{ + */ +#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */ +#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */ +#define ADC_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */ +#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB | ADC_FLAG_NESTED) +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Unit ADC Synchronous Unit + * @{ + */ +#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */ +#define ADC_SYNC_ADC1_ADC2_ADC3 (ADC_SYNCCR_SYNCMD_0) /*!< ADC1, ADC2 and ADC3 work synchronously. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Mode ADC Synchronous Mode + * @{ + */ +#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan once. */ +#define ADC_SYNC_SINGLE_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan once. */ +#define ADC_SYNC_CYCLIC_DELAY_TRIG (ADC_SYNCCR_SYNCMD_2) /*!< Cyclic delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan cyclicly(keep scaning till you stop them). */ +#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_2 | \ + ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan cyclicly(keep scaning till you stop them). */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit + * @{ + */ +#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */ +#define ADC_AWD1 (1U) /*!< ADC analog watchdog 1. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type + * @{ + */ +#define ADC_AWD_INT_AWD0 (ADC_AWDCR_AWD0IEN) /*!< Interrupt of AWD0. */ +#define ADC_AWD_INT_AWD1 (ADC_AWDCR_AWD1IEN) /*!< Interrupt of AWD1. */ +#define ADC_AWD_INT_ALL (ADC_AWD_INT_AWD0 | ADC_AWD_INT_AWD1) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */ +#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Comb_Mode ADC AWD(Analog Watchdog) Combination Mode + * @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and + * the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel + * of AWD1 is converted after the channel conversion of AWD0 ends. + * @{ + */ +#define ADC_AWD_COMB_INVD (0U) /*!< Combination mode is invalid. */ +#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag + * @{ + */ +#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */ +#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */ +#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */ +#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | ADC_AWD_FLAG_AWD1 | ADC_AWD_FLAG_COMB) +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Unit ADC PGA Unit + * @{ + */ +#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input pin is ADC123_IN0. */ +#define ADC_PGA2 (1U) /*!< PGA2, belongs to ADC1. Input pin is ADC123_IN1. */ +#define ADC_PGA3 (2U) /*!< PGA3, belongs to ADC1. Input pin is ADC123_IN2. */ +#define ADC_PGA4 (3U) /*!< PGA4, belongs to ADC2. Input pin is ADC12_IN6. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Gain ADC PGA Gain Factor + * @{ + */ +#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */ +#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */ +#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */ +#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */ +#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */ +#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */ +#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */ +#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */ +#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */ +#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */ +#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */ +#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */ +#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */ +#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */ +#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_VSS ADC PGA VSS + * @{ + */ +#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */ +#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */ +/** + * @} + */ + +/** + * @defgroup ADC_Remap_Pin ADC Remap Pin + * @{ + */ +#define ADC12_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC1 and ADC2 */ +#define ADC12_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC1 and ADC2 */ +#define ADC12_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC1 and ADC2 */ +#define ADC12_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC1 and ADC2 */ +#define ADC12_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1 and ADC2 */ +#define ADC12_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1 and ADC2 */ +#define ADC12_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1 and ADC2 */ +#define ADC12_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1 and ADC2 */ +#define ADC12_PIN_PB0 (8U) /*!< ADC12_IN8(PB0): default channel is ADC_CH8 of ADC1 and ADC2 */ +#define ADC12_PIN_PB1 (9U) /*!< ADC12_IN9(PB1): default channel is ADC_CH9 of ADC1 and ADC2 */ +#define ADC12_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC1 and ADC2 */ +#define ADC12_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC1 and ADC2 */ +#define ADC12_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC1 and ADC2 */ +#define ADC12_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC1 and ADC2 */ +#define ADC12_PIN_PC4 (14U) /*!< ADC12_IN14(PC4): default channel is ADC_CH14 of ADC1 and ADC2 */ +#define ADC12_PIN_PC5 (15U) /*!< ADC12_IN15(PC5): default channel is ADC_CH15 of ADC1 and ADC2 */ + +#define ADC3_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC3 */ +#define ADC3_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC3 */ +#define ADC3_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC3 */ +#define ADC3_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC3 */ +#define ADC3_PIN_PF6 (4U) /*!< ADC3_IN4(PF6): default channel is ADC_CH4 of ADC3 */ +#define ADC3_PIN_PF7 (5U) /*!< ADC3_IN5(PF7): default channel is ADC_CH5 of ADC3 */ +#define ADC3_PIN_PF8 (6U) /*!< ADC3_IN6(PF8): default channel is ADC_CH6 of ADC3 */ +#define ADC3_PIN_PF9 (7U) /*!< ADC3_IN7(PF9): default channel is ADC_CH7 of ADC3 */ +#define ADC3_PIN_PF10 (8U) /*!< ADC3_IN8(PF10): default channel is ADC_CH8 of ADC3 */ +#define ADC3_PIN_PF3 (9U) /*!< ADC3_IN9(PF3): default channel is ADC_CH9 of ADC3 */ +#define ADC3_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC3 */ +#define ADC3_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC3 */ +#define ADC3_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC3 */ +#define ADC3_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC3 */ +#define ADC3_PIN_PF4 (14U) /*!< ADC3_IN14(PF4): default channel is ADC_CH14 of ADC3 */ +#define ADC3_PIN_PF5 (15U) /*!< ADC3_IN15(PF5): default channel is ADC_CH15 of ADC3 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ADC_Global_Functions + * @{ + */ +/******************************************************************************* + Basic features + ******************************************************************************/ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit); +void ADC_DeInit(CM_ADC_TypeDef *ADCx); +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit); +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState); + +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime); + +/* Conversion data average calculation function. */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount); +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState); + +/* Extended channel. */ +void ADC_SetExtChSrc(CM_ADC_TypeDef *ADCx, uint8_t u8ExtChSrc); + +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel); +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState); + +void ADC_Start(CM_ADC_TypeDef *ADCx); +void ADC_Stop(CM_ADC_TypeDef *ADCx); + +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); + +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag); + +/******************************************************************************* + Advanced features + ******************************************************************************/ +/* Channel remap. */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin); +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx); + +/* Sync mode. */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay); +void ADC_SyncModeCmd(en_functional_state_t enNewState); + +/* Analog watchdog */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd); +/* Combination mode. */ +void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode); + +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode); +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit); +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold); +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); + +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState); +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState); +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag); +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag); + +/* Sample hold */ +void ADC_SH_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8SampleTime); +void ADC_SH_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState); + +/* PGA */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss); +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState); + +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState); +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode); + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h new file mode 100644 index 0000000000..93f0ee10ca --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h @@ -0,0 +1,115 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.h + * @brief This file contains all the functions prototypes of the AES driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AES_H__ +#define __HC32_LL_AES_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AES + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Global_Macros AES Global Macros + * @{ + */ + +/** + * @defgroup AES_Key_Size AES Key Size + * @{ + */ +#define AES_KEY_SIZE_16BYTE (16U) +#define AES_KEY_SIZE_24BYTE (24U) +#define AES_KEY_SIZE_32BYTE (32U) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AES_Global_Functions + * @{ + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext); + +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext); +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h new file mode 100644 index 0000000000..676c9b6bf1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h @@ -0,0 +1,187 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.h + * @brief This file contains all the functions prototypes of the AOS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AOS_H__ +#define __HC32_LL_AOS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AOS + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Macros AOS Global Macros + * @{ + */ + +/** + * @defgroup AOS_Trigger_Select AOS Trigger Select + * @{ + */ +#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1) +#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2) +#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3) +#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4) +#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0) +#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1) +#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2) +#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3) +#define AOS_DMA1_4 (uint32_t)(&CM_AOS->DMA1_TRGSEL4) +#define AOS_DMA1_5 (uint32_t)(&CM_AOS->DMA1_TRGSEL5) +#define AOS_DMA1_6 (uint32_t)(&CM_AOS->DMA1_TRGSEL6) +#define AOS_DMA1_7 (uint32_t)(&CM_AOS->DMA1_TRGSEL7) +#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0) +#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1) +#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2) +#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3) +#define AOS_DMA2_4 (uint32_t)(&CM_AOS->DMA2_TRGSEL4) +#define AOS_DMA2_5 (uint32_t)(&CM_AOS->DMA2_TRGSEL5) +#define AOS_DMA2_6 (uint32_t)(&CM_AOS->DMA2_TRGSEL6) +#define AOS_DMA2_7 (uint32_t)(&CM_AOS->DMA2_TRGSEL7) +#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_TRGSELRC) +#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_HTSSR0) +#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_HTSSR1) +#define AOS_TMR6_2 (uint32_t)(&CM_AOS->TMR6_HTSSR2) +#define AOS_TMR6_3 (uint32_t)(&CM_AOS->TMR6_HTSSR3) +#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNTTRGSR12) +#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNTTRGSR34) +#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_HTSSR) +#define AOS_TMR2 (uint32_t)(&CM_AOS->TMR2_HTSSR) +#define AOS_HASH_A (uint32_t)(&CM_AOS->HASH_ITRGSELA) +#define AOS_HASH_B (uint32_t)(&CM_AOS->HASH_ITRGSELB) +#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_HTSSR0) +#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_HTSSR1) +#define AOS_TMRA_2 (uint32_t)(&CM_AOS->TMRA_HTSSR2) +#define AOS_TMRA_3 (uint32_t)(&CM_AOS->TMRA_HTSSR3) +#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRG) +#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_ITRGSELR0) +#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_ITRGSELR1) +#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_ITRGSELR0) +#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_ITRGSELR1) +#define AOS_ADC3_0 (uint32_t)(&CM_AOS->ADC3_ITRGSELR0) +#define AOS_ADC3_1 (uint32_t)(&CM_AOS->ADC3_ITRGSELR1) +#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRG1) +#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID + * @{ + */ +#define AOS_COMM_TRIG1 (1UL << 30U) +#define AOS_COMM_TRIG2 (1UL << 31U) +#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask + * @{ + */ +#define AOS_TRIG_SEL_MASK (0x1FFUL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AOS_Global_Functions + * @{ + */ + +/** + * @brief AOS software trigger. + * @param None + * @retval None + */ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET); +} + +void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState); +void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent); + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AOS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h new file mode 100644 index 0000000000..93ab8eaeb2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h @@ -0,0 +1,717 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.h + * @brief This file contains all the functions prototypes of the CAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CAN_H__ +#define __HC32_LL_CAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CAN + * @{ + */ +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Types CAN Global Types + * @{ + */ +/** + * @brief CAN bit time configuration structure. + * @note 1. TQ = u32Prescaler / CANClock. + * @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + * @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + * @note 4. See user manual of the target MCU and ISO11898-1 for more details. + */ +typedef struct { + uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */ + uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + u32TimeSeg1 Contains synchronization segment, + propagation time segment and phase buffer segment 1. */ + uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + Phase buffer segment 2. */ + uint32_t u32SJW; /*!< Synchronization Jump Width. + Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. */ +} stc_can_bit_time_config_t; + +/** + * @brief CAN acceptance filter configuration structure. + */ +typedef struct { + uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */ + uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */ +} stc_can_filter_config_t; + +/* CAN-FD structure */ +/** + * @brief CAN-FD configuration structure. + */ +typedef struct { + stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of flexible data-rate bit. */ + uint8_t u8Mode; /*!< CAN-FD mode, Bosch CAN-FD or ISO 11898-1:2015 CAN-FD. + This parameter can be a value of @ref CAN_FD_Mode */ + uint8_t u8TDC; /*!< Enable or disable Transmitter Delay Compensation. + This parameter can be a value of @ref CAN_FD_TDC_En */ + uint8_t u8SSPOffset; /*!< Specifies Secondary Sample Point offset. + The transmitter delay plus u8SSPOffset defines the time of the secondary sample point for TDC. + u8SSPOffset is given as a number of TQ. Range is [0, 127] */ +} stc_canfd_config_t; + +/** + * @brief TTCAN configuration structure. + */ +typedef struct { + uint32_t u32RefMsgID; /*!< Reference message identifier. */ + uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit. + '1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while + '0' to set it as a standard ID. */ + uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT. + This parameter can be a value of @ref TTCAN_NTU_Prescaler */ + uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode. + This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */ + uint16_t u16TriggerType; /*!< Trigger type of TTCAN. + This parameter can be a value of @ref TTCAN_Trigger_Type */ + uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */ + uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */ + uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */ +} stc_can_ttc_config_t; + +/** + * @brief CAN initialization structure. + */ +typedef struct { + stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */ + stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that + contains the configuration informations for the acceptance filters. */ + uint16_t u16FilterSelect; /*!< Selects acceptance filters. + This parameter can be values of @ref CAN_Acceptance_Filter */ + uint8_t u8WorkMode; /*!< Specifies the work mode of CAN. + This parameter can be a value of @ref CAN_Work_Mode */ + uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB. + This parameter can be a value of @ref PTB_SingleShot_Tx_En */ + uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB. + This parameter can be a value of @ref STB_SingleShot_Tx_En */ + uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB. + This parameter can be a value of @ref CAN_STB_Prio_Mode_En + NOTE: A frame in the PTB has always the highest priority regardless of the ID. */ + uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8]. + Each CAN unit has 8 receive buffers. When the number of received frames reaches + the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred + if it was enabled. */ + uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15]. + Error warning limit = (u8ErrorWarnLimit + 1) * 8. */ + uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error). + This parameter can be a value of @ref CAN_Rx_All_En */ + uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received. + This parameter can be a value of @ref CAN_Rx_Ovf_Mode */ + uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge. + This parameter can be a value of @ref CAN_Self_ACK_En */ + /* CAN-FD configuration */ + stc_canfd_config_t *pstcCanFd; /*!< Pointer to a CAN-FD configuration structure. @ref stc_canfd_config_t + Set it to NULL if not needed CAN-FD. */ + + stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t + Set it to NULL if not needed TTCAN. */ +} stc_can_init_t; + +/** + * @brief CAN error information structure. + */ +typedef struct { + uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */ + uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */ + uint8_t u8RxErrorCount; /*!< Receive error count. */ + uint8_t u8TxErrorCount; /*!< Transmit error count. */ +} stc_can_error_info_t; + +/** + * @brief CAN TX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be a 1 or 0. */ + uint32_t RSVD: 24; /*!< Reserved bits. */ + }; + }; + uint8_t au8Data[64U]; /*!< TX data payload. */ +} stc_can_tx_frame_t; + +/** + * @brief CAN RX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be 1 or 0. */ + uint32_t RSVD: 4; /*!< Reserved bits. */ + uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */ + uint32_t ERRT: 3; /*!< Error type. */ + uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */ + }; + }; + uint8_t au8Data[64U]; /*!< RX data payload. */ +} stc_can_rx_frame_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Macros CAN Global Macros + * @{ + */ + +/** + * @defgroup CAN_Work_Mode CAN Work Mode + * @{ + */ +#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */ +#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */ +#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing. + It is forbidden to respond to received frames and error frames, + but data can be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type + * @{ + */ +#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */ +#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */ +/** + * @} + */ + +/** + * @defgroup CAN_Data_Length_Code CAN Data Length Code + * @{ + */ +#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */ +#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */ +#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */ +#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */ +#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */ +#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */ +#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */ +#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */ +#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */ +/* More DLC for CAN-FD. */ +#define CAN_DLC12 (0x9U) /*!< CAN FD: the size of data field is 12 bytes. */ +#define CAN_DLC16 (0xAU) /*!< CAN FD: the size of data field is 16 bytes. */ +#define CAN_DLC20 (0xBU) /*!< CAN FD: the size of data field is 20 bytes. */ +#define CAN_DLC24 (0xCU) /*!< CAN FD: the size of data field is 24 bytes. */ +#define CAN_DLC32 (0xDU) /*!< CAN FD: the size of data field is 32 bytes. */ +#define CAN_DLC48 (0xEU) /*!< CAN FD: the size of data field is 48 bytes. */ +#define CAN_DLC64 (0xFU) /*!< CAN FD: the size of data field is 64 bytes. */ +/** + * @} + */ + +/** + * @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control + * @{ + */ +#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */ +#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control + * @{ + */ +#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */ +#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Request CAN Transmission Request + * @{ + */ +#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */ +#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */ +#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */ +/** + * @} + */ + +/** + * @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control + * @note A frame in the PTB has always the highest priority regardless of the ID. + * @{ + */ +#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */ +#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status + * @{ + */ +#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty. + TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + PTB and STB are both empty. */ +#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full; + TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */ +#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full; + TTEN == 1 && TTTBM == 1: reserved value. */ +#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full; + TTEN == 1 && TTTBM == 1: PTB and STB are both full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status + * @{ + */ +#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */ +#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */ +#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */ +#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_All_En CAN Receive All Frames + * @{ + */ +#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */ +#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode + * @{ + */ +#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */ +#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */ +/** + * @} + */ + +/** + * @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control + * @{ + */ +#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */ +#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */ +/** + * @} + */ + +/** + * @defgroup CAN_Interrupt_Type CAN Interrupt Type + * @{ + */ +#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */ +#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */ +#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */ +#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */ +#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */ +#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error inetrrupt. */ +#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */ +#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */ + +#define CAN_INT_ALL (CAN_INT_ERR_INT | \ + CAN_INT_STB_TX | \ + CAN_INT_PTB_TX | \ + CAN_INT_RX_BUF_WARN | \ + CAN_INT_RX_BUF_FULL | \ + CAN_INT_RX_OVERRUN | \ + CAN_INT_RX | \ + CAN_INT_BUS_ERR | \ + CAN_INT_ARBITR_LOST | \ + CAN_INT_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_Status_Flag CAN Status Flag + * @{ + */ +#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */ +#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */ +#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */ +#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */ +#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full. + TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/ +#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */ +#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */ +#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */ +#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */ +#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */ +#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */ +#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */ +#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */ +#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */ +#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */ +#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */ + +#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \ + CAN_FLAG_TX_GOING | \ + CAN_FLAG_RX_GOING | \ + CAN_FLAG_RX_BUF_OVF | \ + CAN_FLAG_TX_BUF_FULL | \ + CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_TEC_REC_WARN) + +#define CAN_FLAG_CLR_ALL (CAN_FLAG_RX_BUF_OVF | \ + CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_ID_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */ +#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */ +#define CAN_ID_EXT (CAN_ACF_AIDEE | \ + CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */ +/** + * @} + */ + +/** + * @defgroup CAN_Err_Type CAN Error Type + * @{ + */ +#define CAN_ERR_NONE (0U) /*!< No error. */ +#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */ +#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */ +#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */ +#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */ +#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */ +#define CAN_ERR_OTHER (0x6U) /*!< Error is other error. + Dominant bits after own error flag, received active Error Flag too long, + dominant bit during Passive-Error-Flag after ACK error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Acceptance_Filter CAN Acceptance Filter + * @{ + */ +#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */ +#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */ +#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */ +#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */ +#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */ +#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */ +#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */ +#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */ +#define CAN_FILTER9 (CAN_ACFEN_AE_9) /*!< Acceptance filter 9 select bit. */ +#define CAN_FILTER10 (CAN_ACFEN_AE_10) /*!< Acceptance filter 10 select bit. */ +#define CAN_FILTER11 (CAN_ACFEN_AE_11) /*!< Acceptance filter 11 select bit. */ +#define CAN_FILTER12 (CAN_ACFEN_AE_12) /*!< Acceptance filter 12 select bit. */ +#define CAN_FILTER13 (CAN_ACFEN_AE_13) /*!< Acceptance filter 13 select bit. */ +#define CAN_FILTER14 (CAN_ACFEN_AE_14) /*!< Acceptance filter 14 select bit. */ +#define CAN_FILTER15 (CAN_ACFEN_AE_15) /*!< Acceptance filter 15 select bit. */ +#define CAN_FILTER16 (CAN_ACFEN_AE_16) /*!< Acceptance filter 16 select bit. */ +#define CAN_FILTER_ALL (0xFFFFU) +/** + * @} + */ + +/** + * @defgroup CAN_FD_Mode CAN-FD Mode + * @{ + */ +#define CAN_FD_MD_BOSCH (0x0U) /*!< Bosch CAN FD (non-ISO) mode. */ +#define CAN_FD_MD_ISO (CAN_TCTRL_FD_ISO) /*!< ISO CAN FD mode (ISO 11898-1:2015). */ +/** + * @} + */ + +/** + * @defgroup CAN_FD_TDC_En CAN-FD TDC Function Control + * @{ + */ +#define CAN_FD_TDC_DISABLE (0x0U) /*!< Disable transmitter delay compensation. */ +#define CAN_FD_TDC_ENABLE (CAN_TDC_TDCEN) /*!< Enable transmitter delay compensation. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode + * @{ + */ +#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */ +#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and + TRG_CFG.TTPTR(for data transmission). */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection + * @{ + */ +#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */ +#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */ +#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */ +#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State + * @{ + */ +#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty". + TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. + If a transmission from this slot is active, then TBE stays set as long as either the + transmission completes or after a transmission error or arbitration loss the transmission + is not active any more. If both TBF and TBE are set, then TBE wins. */ +#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled". + TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1. + If both TBF and TBE are set, then TBE wins. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type + * @{ + */ +#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */ +#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */ +#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \ + CAN_TTC_INT_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_Status_Flag TTCAN Status Flag + * @{ + */ +#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */ +#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */ +#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */ + +#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \ + CAN_TTC_FLAG_TRIG_ERR | \ + CAN_TTC_FLAG_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler + * @{ + */ +#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */ +#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */ +#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */ +#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Trigger_Type TTCAN Trigger Type + * @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled. + * @{ + */ +#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */ +#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */ +#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */ +#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \ + CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */ +#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CAN_Global_Functions + * @{ + */ +/* Classical CAN */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit); +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit); +void CAN_DeInit(CM_CAN_TypeDef *CANx); +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState); +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx); +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest); +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType); +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx); + +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag); +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag); +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx); +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr); +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx); +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx); +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState); +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit); +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit); + +int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd); + +/* TTCAN */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc); +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc); +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState); +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState); + +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag); +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag); +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx); + +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType); +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow); +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime); +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime); + +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx); + +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc); + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h new file mode 100644 index 0000000000..4c0e85a00f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h @@ -0,0 +1,779 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.h + * @brief This file contains all the functions prototypes of the CLK driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CLK_H__ +#define __HC32_LL_CLK_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CLK + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Types CLK Global Types + * @{ + */ +/** + * @brief CLK XTAL configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< The new state of the XTAL. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8Drv; /*!< The XTAL drive ability. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8StableTime; /*!< The XTAL stable time selection. + This parameter can be a value of @ref CLK_XTAL_Config */ +} stc_clock_xtal_init_t; + +/** + * @brief CLK XTAL fault detect configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Specifies the new state of XTALSTD. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Mode; /*!< Specifies the XTALSTD mode. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ +} stc_clock_xtalstd_init_t; + +/** + * @brief CLK XTAL32 configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Xtal32 new state, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Drv; /*!< Xtal32 drive capacity setting, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Filter; /*!< Xtal32 noise filter setting, + @ref CLK_XTAL32_Config for details */ +} stc_clock_xtal32_init_t; + +/** + * @brief CLK clock frequency configuration structure definition + */ +typedef struct { + union { + uint32_t SCFGR; /*!< clock frequency config register */ + struct { + uint32_t PCLK0S : 3; /*!< PCLK0 */ + uint32_t resvd0 : 1; /*!< reserved */ + uint32_t PCLK1S : 3; /*!< PCLK1 */ + uint32_t resvd1 : 1; /*!< reserved */ + uint32_t PCLK2S : 3; /*!< PCLK2 */ + uint32_t resvd2 : 1; /*!< reserved */ + uint32_t PCLK3S : 3; /*!< PCLK3 */ + uint32_t resvd3 : 1; /*!< reserved */ + uint32_t PCLK4S : 3; /*!< PCLK4 */ + uint32_t resvd4 : 1; /*!< reserved */ + uint32_t EXCKS : 3; /*!< EXCLK */ + uint32_t resvd5 : 1; /*!< reserved */ + uint32_t HCLKS : 3; /*!< HCLK */ + uint32_t resvd6 : 5; /*!< reserved */ + } SCFGR_f; + }; +} stc_clock_scale_t; + +/** + * @brief CLK PLL configuration structure definition + * @note PLL for MPLL while HC32F460,HC32F451,HC32F452 + * PLL for PLLH while HC32F4A0 + */ +typedef struct { + uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */ + union { + uint32_t PLLCFGR; /*!< PLL config register */ + struct { + uint32_t PLLM : 2; /*!< PLL M divide */ + uint32_t resvd0 : 5; /*!< reserved */ + uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */ + uint32_t PLLN : 8; /*! PLLH N multi- */ + uint32_t resvd1 : 4; /*! reserved */ + uint32_t PLLR : 4; /*!< PLL R divide */ + uint32_t PLLQ : 4; /*!< PLL Q divide */ + uint32_t PLLP : 4; /*!< PLL P divide */ + } PLLCFGR_f; + }; +} stc_clock_pll_init_t; + +/** + * @brief CLK PLLx configuration structure definition + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +typedef struct { + uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */ + union { + uint32_t PLLCFGR; /*!< PLLx config register */ + struct { + uint32_t PLLM : 5; /*!< PLLx M divide */ + uint32_t resvd0 : 3; /*!< reserved */ + uint32_t PLLN : 9; /*!< PLLx N multi- */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLLx R divide */ + uint32_t PLLQ : 4; /*!< PLLx Q divide */ + uint32_t PLLP : 4; /*!< PLLx P divide */ + } PLLCFGR_f; + }; +} stc_clock_pllx_init_t; + +/** + * @brief CLK bus frequency structure definition + */ +typedef struct { + uint32_t u32SysclkFreq; /*!< System clock frequency. */ + uint32_t u32HclkFreq; /*!< Hclk frequency. */ + + uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */ + uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */ + uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */ + uint32_t u32ExclkFreq; /*!< Exclk frequency. */ + uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */ + uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */ +} stc_clock_freq_t; + +/** + * @brief CLK PLL clock frequency structure definition + */ +typedef struct { + uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */ + uint32_t u32PllVco; /*!< PLL vco clock frequency. */ + uint32_t u32PllP; /*!< PLLp clock frequency. */ + uint32_t u32PllQ; /*!< PLLq clock frequency. */ + uint32_t u32PllR; /*!< PLLr clock frequency. */ + uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */ + uint32_t u32PllxVco; /*!< pllx vco clock frequency. */ + uint32_t u32PllxP; /*!< pllxp clock frequency. */ + uint32_t u32PllxQ; /*!< pllxq clock frequency. */ + uint32_t u32PllxR; /*!< pllxr clock frequency. */ +} stc_pll_clock_freq_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Macros CLK Global Macros + * @{ + */ +/** + * @defgroup CLK_PLLx_State CLK PLLx State + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + * @{ + */ +#define CLK_PLLX_OFF (0x01U) +#define CLK_PLLX_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_PLL_Config PLL Config + * @{ + */ +/** + * @brief PLL function config. + */ +#define CLK_PLL_OFF (0x01U) +#define CLK_PLL_ON (0x00U) + +/** + * @brief PLL/A source clock selection. + */ +#define CLK_PLL_SRC_XTAL (0x00UL) +#define CLK_PLL_SRC_HRC (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Config XTAL Config + * @{ + */ +/** + * @brief XTAL function config. + */ +#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP) +#define CLK_XTAL_ON (0x00U) + +/** + * @brief XTAL driver ability + * @note HC32F451/HC32F452 | | | + * @note HC32F4A0/HC32F460 | | | + * @note HC32F472 | HC32M423/HC32M424 | HC32M120/HC32F120/HC32F160 | + * High: [20~25] | [20~24] | [20] | + * Mid: [16~20) | [16~20) | [10~20) | + * Low: (8~16) | (8~16) | (4~10) | + * ULow: [4~8] | [4~8] | [4] | + */ +#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS) + +/** + * @brief XTAL mode selection osc or exclk + */ +#define CLK_XTAL_MD_OSC (0x00U) +#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS) + +/** + * @brief XTAL stable time selection. + * @note a cycle of stable counter = a cycle of LRC divide by 8 + */ +#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */ +#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */ +#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */ +#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */ +#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */ +#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */ +#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */ +#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */ +#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */ + +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_Config XTALSTD Config + * @{ + */ + +/** + * @brief XTAL error detection on or off + */ +#define CLK_XTALSTD_OFF (0x00U) +#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE) + +/** + * @brief XTALSTD mode selection + */ +#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS) +#define CLK_XTALSTD_MD_INT (0x00U) + +/** + * @brief XTALSTD reset on or off + */ +#define CLK_XTALSTD_RST_OFF (0x00U) +#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE) + +/** + * @brief XTALSTD interrupt on or off + */ +#define CLK_XTALSTD_INT_OFF (0x00U) +#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Config XTAL32 Config + * @{ + */ +/** + * @brief XTAL32 function config. + */ +#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP) +#define CLK_XTAL32_ON (0x00U) + +/** + * @brief XTAL32 driver ability. + */ +#define CLK_XTAL32_DRV_MID (0x00U) +#define CLK_XTAL32_DRV_HIGH (0x01U) + +/** + * @brief XTAL32 filtering selection. + */ +#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */ +#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */ +#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */ +/** + * @} + */ + +/** + * @defgroup CLK_HRC_Config HRC Config + * @{ + */ +#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP) +#define CLK_HRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_HrcFreq_Sel Hrc Freqency Selection + * @{ + */ + +/** + * @} + */ + +/** + * @defgroup CLK_STB_Flag CLK Stable Flags + * @{ + */ +#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF) +#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF) +#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_PLLHSTBF) +#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_PLLASTBF) +#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \ + CMU_OSCSTBSR_PLLASTBF | CMU_OSCSTBSR_PLLHSTBF) + +/** + * @} + */ + +/** + * @defgroup CLK_System_Clock_Source System Clock Source + * @{ + */ +#define CLK_SYSCLK_SRC_HRC (0x00U) +#define CLK_SYSCLK_SRC_MRC (0x01U) +#define CLK_SYSCLK_SRC_LRC (0x02U) +#define CLK_SYSCLK_SRC_XTAL (0x03U) +#define CLK_SYSCLK_SRC_XTAL32 (0x04U) +#define CLK_SYSCLK_SRC_PLL (0x05U) + +/** + * @} + */ + +/** + * @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection + * @{ + */ +#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S) +#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S) +#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S) +#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S) +#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S) +#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS) +#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS) +#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \ + CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK) + +/** + * @} + */ + +/** + * @defgroup CLK_Clock_Divider Clock Divider + * @{ + */ + +/** + * @defgroup CLK_System_Clock_Divider System Clock Divider + * @{ + */ +#define CLK_SYSCLK_DIV1 (0x00U) +#define CLK_SYSCLK_DIV2 (0x01U) +#define CLK_SYSCLK_DIV4 (0x02U) +#define CLK_SYSCLK_DIV8 (0x03U) +#define CLK_SYSCLK_DIV16 (0x04U) +#define CLK_SYSCLK_DIV32 (0x05U) +#define CLK_SYSCLK_DIV64 (0x06U) +/** + * @} + */ + +/** + * @defgroup CLK_HCLK_Divider CLK HCLK Divider + * @{ + */ +#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider + * @{ + */ +#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider + * @{ + */ +#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider + * @{ + */ +#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_EXCLK_Divider CLK EXCLK Divider + * @{ + */ +#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider + * @{ + */ +#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider + * @{ + */ +#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup CLK_USBCLK_Sel CLK USB Clock Selection + * @{ + */ +#define CLK_USBCLK_SYSCLK_DIV2 (0x01U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV3 (0x02U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV4 (0x03U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV5 (0x04U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV6 (0x05U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV7 (0x06U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV8 (0x07U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLQ (0x08U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLR (0x09U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXP (0x0AU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXQ (0x0BU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXR (0x0CU << CMU_USBCKCFGR_USBCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_CANCLK_Sel CLK CAN Clock Selection + * @{ + */ +#define CLK_CANCLK_SYSCLK_DIV2 (0x01U) +#define CLK_CANCLK_SYSCLK_DIV3 (0x02U) +#define CLK_CANCLK_SYSCLK_DIV4 (0x03U) +#define CLK_CANCLK_SYSCLK_DIV5 (0x04U) +#define CLK_CANCLK_SYSCLK_DIV6 (0x05U) +#define CLK_CANCLK_SYSCLK_DIV7 (0x06U) +#define CLK_CANCLK_SYSCLK_DIV8 (0x07U) +#define CLK_CANCLK_PLLQ (0x08U) +#define CLK_CANCLK_PLLR (0x09U) +#define CLK_CANCLK_PLLXP (0x0AU) +#define CLK_CANCLK_PLLXQ (0x0BU) +#define CLK_CANCLK_PLLXR (0x0CU) +#define CLK_CANCLK_XTAL (0x0DU) +/** + * @} + */ + +/** + * @defgroup CLK_CAN_Sel CLK CAN Channel Selection + * @{ + */ +#define CLK_CAN1 (0x01U) +#define CLK_CAN2 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection + * @note ADC,I2S,DAC,TRANG + * @{ + */ +#define CLK_PERIPHCLK_PCLK (0x0000U) /* PCLK2 is used for ADC clock, \ + PCLK1 is used for I2S clock, \ + PCLK4 is used for DAC/TRANG clock */ +#define CLK_PERIPHCLK_PLLQ (0x0008U) +#define CLK_PERIPHCLK_PLLR (0x0009U) +#define CLK_PERIPHCLK_PLLXP (0x000AU) +#define CLK_PERIPHCLK_PLLXQ (0x000BU) +#define CLK_PERIPHCLK_PLLXR (0x000CU) + +/** + * @} + */ + +/** + * @defgroup CLK_I2S_Sel CLK I2S Channel Selection + * @{ + */ +#define CLK_I2S1 (0x00U) +#define CLK_I2S2 (0x01U) +#define CLK_I2S3 (0x02U) +#define CLK_I2S4 (0x03U) +/** + * @} + */ + +/** + * @defgroup CLK_TPIU_Divider TPIU clock divider + * @{ + */ +#define CLK_TPIUCLK_DIV1 (0x00U) +#define CLK_TPIUCLK_DIV2 (0x01U) +#define CLK_TPIUCLK_DIV4 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select + * @{ + */ +#define CLK_MCO1 (0x00U) +#define CLK_MCO2 (0x01U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source + * @{ + */ +#define CLK_MCO_SRC_HRC (0x00U) +#define CLK_MCO_SRC_MRC (0x01U) +#define CLK_MCO_SRC_LRC (0x02U) +#define CLK_MCO_SRC_XTAL (0x03U) +#define CLK_MCO_SRC_XTAL32 (0x04U) +#define CLK_MCO_SRC_PLLP (0x06U) +#define CLK_MCO_SRC_PLLXP (0x07U) +#define CLK_MCO_SRC_PLLQ (0x08U) +#define CLK_MCO_SRC_PLLXQ (0x09U) +#define CLK_MCO_SRC_PLLXR (0x0AU) +#define CLK_MCO_SRC_HCLK (0x0BU) + +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler + * @{ + */ +#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CLK_Global_Functions + * @{ + */ + +int32_t CLK_HrcCmd(en_functional_state_t enNewState); + +int32_t CLK_MrcCmd(en_functional_state_t enNewState); + +int32_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t i8TrimVal); +void CLK_MrcTrim(int8_t i8TrimVal); +void CLK_LrcTrim(int8_t i8TrimVal); +void CLK_RtcLrcTrim(int8_t i8TrimVal); + +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalCmd(en_functional_state_t enNewState); + +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit); +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit); +void CLK_ClearXtalStdStatus(void); +en_flag_status_t CLK_GetXtalStdStatus(void); + +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_Xtal32InputCmd(en_functional_state_t enNewState); + +void CLK_SetPLLSrc(uint32_t u32PllSrc); +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLCmd(en_functional_state_t enNewState); +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq); + +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxCmd(en_functional_state_t enNewState); + +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div); +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag); + +void CLK_SetSysClockSrc(uint8_t u8Src); +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div); +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq); +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock); + +void CLK_SetPeriClockSrc(uint16_t u16Src); + +void CLK_SetUSBClockSrc(uint8_t u8Src); +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src); + +void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src); + +void CLK_TpiuClockCmd(en_functional_state_t enNewState); +void CLK_SetTpiuClockDiv(uint8_t u8Div); + +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h new file mode 100644 index 0000000000..db15b7e04b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h @@ -0,0 +1,435 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.h + * @brief Head file for CMP module. + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CMP_H__ +#define __HC32_LL_CMP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CMP + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CMP_Global_Types CMP Global Types + * @{ + */ + +/** + * @brief CMP normal mode configuration structure + */ +typedef struct { + uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */ + uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_init_t; + +/** + * @brief CMP window mode configuration structure + */ +typedef struct { + uint8_t u8WinVolLow; /*!< CMP reference low voltage for window mode @ref CMP_Window_Low_Select */ + uint8_t u8WinVolHigh; /*!< CMP reference high voltage for window mode @ref CMP_Window_High_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_window_init_t; + +/** + * @brief CMP blank window function configuration structure + */ +typedef struct { + uint16_t u16Src; /*!< blank window source select, + can be any combination of @ref CMP_BlankWindow_Src */ + uint8_t u8ValidLevel; /*!< Blank window valid level @ref CMP_BlankWindow_Valid_Level */ + uint8_t u8OutLevel; /*!< CMP output level when blank window valid @ref CMP_BlankWindow_output_Level */ +} stc_cmp_blankwindow_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Macros CMP Global Macros + * @{ + */ + +#define VISR_OFFSET (8U) + +/** + * @defgroup CMP_Window_Mode_Unit CMP Window Mode Unit + * @{ + */ +#define CMP_WIN_CMP12 (0x01U) +#define CMP_WIN_CMP34 (0x02U) + +/** + * @} + */ + +/** + * @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input + * @{ + */ +#define CMP_POSITIVE_NONE (0x0U) + +/* Select positive input for CMP1 */ +#define CMP1_POSITIVE_PGA1_BP (CMP_PMSR_CVSL_0) /*!< Select PGA1_BP */ +#define CMP1_POSITIVE_PGA1 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select PGA1 */ +#define CMP1_POSITIVE_PGA2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select PGA2 */ +#define CMP1_POSITIVE_CMP1_INP2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_2 << VISR_OFFSET)) /*!< Select CMP1_INP2 */ +#define CMP1_POSITIVE_CMP1_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P3SL_0 << VISR_OFFSET)) /*!< Select CMP1_INP3 */ +#define CMP1_POSITIVE_CMP2_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P3SL_1 << VISR_OFFSET)) /*!< Select CMP2_INP3 */ +#define CMP1_POSITIVE_CMP1_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP1_INP4 */ +/* Select positive input for CMP2 */ +#define CMP2_POSITIVE_PGA2_BP (CMP_PMSR_CVSL_0) /*!< Select PGA2_BP */ +#define CMP2_POSITIVE_PGA2 (CMP_PMSR_CVSL_1) /*!< Select PGA2 */ +#define CMP2_POSITIVE_CMP2_INP3 (CMP_PMSR_CVSL_2) /*!< Select CMP2_INP3 */ +#define CMP2_POSITIVE_CMP2_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP2_INP4 */ +/* Select positive input for CMP3 */ +#define CMP3_POSITIVE_PGA3_BP (CMP_PMSR_CVSL_0) /*!< Select PGA3_BP */ +#define CMP3_POSITIVE_PGA3 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select PGA3 */ +#define CMP3_POSITIVE_PGA4 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select PGA4_BP */ +#define CMP3_POSITIVE_CMP3_INP2 ((CMP_PMSR_CVSL_1) | (CMP_VISR_P2SL_2 << VISR_OFFSET)) /*!< Select CMP3_INP2 */ +#define CMP3_POSITIVE_CMP3_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P2SL_0 << VISR_OFFSET)) /*!< Select CMP3_INP3 */ +#define CMP3_POSITIVE_CMP4_INP3 ((CMP_PMSR_CVSL_2) | (CMP_VISR_P2SL_1 << VISR_OFFSET)) /*!< Select CMP4_INP3 */ +#define CMP3_POSITIVE_CMP3_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP3_INP4 */ +/* Select positive input for CMP4 */ +#define CMP4_POSITIVE_PGA4_BP (CMP_PMSR_CVSL_0) /*!< Select PGA4_BP */ +#define CMP4_POSITIVE_PGA4 (CMP_PMSR_CVSL_1) /*!< Select PGA4 */ +#define CMP4_POSITIVE_CMP4_INP3 (CMP_PMSR_CVSL_2) /*!< Select CMP4_INP3 */ +#define CMP4_POSITIVE_CMP4_INP4 (CMP_PMSR_CVSL_3) /*!< Select CMP4_INP4 */ + +/** + * @} + */ + +/** + * @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input + * @{ + */ +#define CMP_NEGATIVE_NONE (0x0U) + +/* Select negative input for CMP1 */ +#define CMP1_NEGATIVE_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */ +#define CMP1_NEGATIVE_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */ +#define CMP1_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP1_NEGATIVE_CMP1_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP1_INM4 */ +/* Select negative input for CMP2 */ +#define CMP2_NEGATIVE_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */ +#define CMP2_NEGATIVE_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */ +#define CMP2_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP2_NEGATIVE_CMP2_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP2_INM4 */ +/* Select negative input for CMP3 */ +#define CMP3_NEGATIVE_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */ +#define CMP3_NEGATIVE_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */ +#define CMP3_NEGATIVE_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP3_NEGATIVE_CMP3_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP3_INM4 */ +/* Select negative input for CMP4 */ +#define CMP4_NEGATIVE_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */ +#define CMP4_NEGATIVE_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */ +#define CMP4_NEGATIVE_CMP4_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP4_INM3 */ +#define CMP4_NEGATIVE_CMP4_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP4_INM4 */ + +/** + * @} + */ + +/** + * @defgroup CMP_Window_Low_Select CMP Window Mode Window Low Voltage + * @{ + */ +#define CMP_WIN_LOW_NONE (0x0U) +/* Select input for window mode CMP_WIN_CMP12 */ +#define CMP12_WIN_LOW_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */ +#define CMP12_WIN_LOW_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */ +#define CMP12_WIN_LOW_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP12_WIN_LOW_CMP1_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP1_INM4 */ +/* Select input for window mode CMP_WIN_CMP34 */ +#define CMP34_WIN_LOW_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */ +#define CMP34_WIN_LOW_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */ +#define CMP34_WIN_LOW_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP34_WIN_LOW_CMP3_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP3_INM4 */ + +/** + * @} + */ + +/** + * @defgroup CMP_Window_High_Select CMP Window Mode Window High Voltage + * @{ + */ +#define CMP_WIN_HIGH_NONE (0x0U) +/* Select input for window mode CMP_WIN_CMP12 */ +#define CMP12_WIN_HIGH_DAC1_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC1_OUT1 */ +#define CMP12_WIN_HIGH_DAC1_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC1_OUT2 */ +#define CMP12_WIN_HIGH_CMP123_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP123_INM3 */ +#define CMP12_WIN_HIGH_CMP2_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP2_INM4 */ +/* Select input for window mode CMP_WIN_CMP34 */ +#define CMP34_WIN_HIGH_DAC2_OUT1 (CMP_PMSR_RVSL_0) /*!< DAC voltage DAC2_OUT1 */ +#define CMP34_WIN_HIGH_DAC2_OUT2 (CMP_PMSR_RVSL_1) /*!< DAC voltage DAC2_OUT2 */ +#define CMP34_WIN_HIGH_CMP4_INM3 (CMP_PMSR_RVSL_2) /*!< Pin CMP4_INM3 */ +#define CMP34_WIN_HIGH_CMP4_INM4 (CMP_PMSR_RVSL_3) /*!< Pin CMP4_INM4 */ + +/** + * @} + */ + +/** + * @defgroup CMP_Out_Polarity_Select CMP Output Polarity + * @{ + */ +#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */ +#define CMP_OUT_INVT_ON (CMP_OCR_COPS) /*!< CMP output level reverse */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge + * @{ + */ +#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */ + +#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */ +#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */ +#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */ + +/** + * @} + */ + +/** + * @defgroup CMP_Out_Filter CMP Output Filter Configuration + * @{ + */ +#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */ + +#define CMP_OUT_FILTER_CLK (1U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV8 (2U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV32 (3U << CMP_FIR_FCKS_POS) + +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Src CMP Output blank window Function Control Signal + * @{ + */ +/* CMP1 blank window signal */ +#define CMP1_BLANKWIN_TMRA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_1_PWM1 for CMP1 */ +#define CMP1_BLANKWIN_TMRA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_1_PWM2 for CMP1 */ +#define CMP1_BLANKWIN_TMRA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_1_PWM3 for CMP1 */ +#define CMP1_BLANKWIN_TMRA_2_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_2_PWM1 for CMP1 */ +#define CMP1_BLANKWIN_TMRA_2_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_2_PWM2 for CMP1 */ +#define CMP1_BLANKWIN_TMRA_2_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_2_PWM3 for CMP1 */ +#define CMP1_BLANKWIN_TMR6_1_PWMA (CMP_TWSR_CTWS6) /*!< Select TMR6_1_PWMA for CMP1 */ +#define CMP1_BLANKWIN_TMR6_2_PWMA (CMP_TWSR_CTWS7) /*!< Select TMR6_2_PWMA for CMP1 */ +#define CMP1_BLANKWIN_TMR6_3_PWMA (CMP_TWSR_CTWS8) /*!< Select TMR6_3_PWMA for CMP1 */ +#define CMP1_BLANKWIN_TMR6_4_PWMA (CMP_TWSR_CTWS9) /*!< Select TMR6_4_PWMA for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_1_OUH for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_1_OUL for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_1_OVH for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_1_OVL for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_1_OWH for CMP1 */ +#define CMP1_BLANKWIN_TMR4_1_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_1_OWL for CMP1 */ +/* CMP2 blank window signal */ +#define CMP2_BLANKWIN_TMRA_3_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_3_PWM1 for CMP2 */ +#define CMP2_BLANKWIN_TMRA_3_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_3_PWM2 for CMP2 */ +#define CMP2_BLANKWIN_TMRA_3_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_3_PWM3 for CMP2 */ +#define CMP2_BLANKWIN_TMRA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_4_PWM1 for CMP2 */ +#define CMP2_BLANKWIN_TMRA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_4_PWM2 for CMP2 */ +#define CMP2_BLANKWIN_TMRA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_4_PWM3 for CMP2 */ +#define CMP2_BLANKWIN_TMR6_5_PWMA (CMP_TWSR_CTWS6) /*!< Select TMR6_5_PWMA for CMP2 */ +#define CMP2_BLANKWIN_TMR6_6_PWMA (CMP_TWSR_CTWS7) /*!< Select TMR6_6_PWMA for CMP2 */ +#define CMP2_BLANKWIN_TMR6_7_PWMA (CMP_TWSR_CTWS8) /*!< Select TMR6_7_PWMA for CMP2 */ +#define CMP2_BLANKWIN_TMR6_8_PWMA (CMP_TWSR_CTWS9) /*!< Select TMR6_8_PWMA for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_2_OUH for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_2_OUL for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_2_OVH for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_2_OVL for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_2_OWH for CMP2 */ +#define CMP2_BLANKWIN_TMR4_2_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_2_OWL for CMP2 */ +/* CMP3 blank window signal */ +#define CMP3_BLANKWIN_TMRA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_1_PWM1 for CMP3 */ +#define CMP3_BLANKWIN_TMRA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_1_PWM2 for CMP3 */ +#define CMP3_BLANKWIN_TMRA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_1_PWM3 for CMP3 */ +#define CMP3_BLANKWIN_TMRA_3_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_3_PWM1 for CMP3 */ +#define CMP3_BLANKWIN_TMRA_3_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_3_PWM2 for CMP3 */ +#define CMP3_BLANKWIN_TMRA_3_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_3_PWM3 for CMP3 */ +#define CMP3_BLANKWIN_TMR6_1_PWMB (CMP_TWSR_CTWS6) /*!< Select TMR6_1_PWMB for CMP3 */ +#define CMP3_BLANKWIN_TMR6_2_PWMB (CMP_TWSR_CTWS7) /*!< Select TMR6_2_PWMB for CMP3 */ +#define CMP3_BLANKWIN_TMR6_3_PWMB (CMP_TWSR_CTWS8) /*!< Select TMR6_3_PWMB for CMP3 */ +#define CMP3_BLANKWIN_TMR6_4_PWMB (CMP_TWSR_CTWS9) /*!< Select TMR6_4_PWMB for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_3_OUH for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_3_OUL for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_3_OVH for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_3_OVL for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_3_OWH for CMP3 */ +#define CMP3_BLANKWIN_TMR4_3_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_3_OWL for CMP3 */ +/* CMP4 blank window signal */ +#define CMP4_BLANKWIN_TMRA_2_PWM1 (CMP_TWSR_CTWS0) /*!< Select TMRA_2_PWM1 for CMP4 */ +#define CMP4_BLANKWIN_TMRA_2_PWM2 (CMP_TWSR_CTWS1) /*!< Select TMRA_2_PWM2 for CMP4 */ +#define CMP4_BLANKWIN_TMRA_2_PWM3 (CMP_TWSR_CTWS2) /*!< Select TMRA_2_PWM3 for CMP3 */ +#define CMP4_BLANKWIN_TMRA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Select TMRA_4_PWM1 for CMP4 */ +#define CMP4_BLANKWIN_TMRA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Select TMRA_4_PWM2 for CMP4 */ +#define CMP4_BLANKWIN_TMRA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Select TMRA_4_PWM3 for CMP4 */ +#define CMP4_BLANKWIN_TMR6_5_PWMB (CMP_TWSR_CTWS6) /*!< Select TMR6_5_PWMB for CMP4 */ +#define CMP4_BLANKWIN_TMR6_6_PWMB (CMP_TWSR_CTWS7) /*!< Select TMR6_6_PWMB for CMP4 */ +#define CMP4_BLANKWIN_TMR6_7_PWMB (CMP_TWSR_CTWS8) /*!< Select TMR6_7_PWMB for CMP4 */ +#define CMP4_BLANKWIN_TMR6_8_PWMB (CMP_TWSR_CTWS9) /*!< Select TMR6_8_PWMB for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OUH (CMP_TWSR_CTWS10) /*!< Select TMR4_4_OUH for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OUL (CMP_TWSR_CTWS11) /*!< Select TMR4_4_OUL for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OVH (CMP_TWSR_CTWS12) /*!< Select TMR4_4_OVH for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OVL (CMP_TWSR_CTWS13) /*!< Select TMR4_4_OVL for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OWH (CMP_TWSR_CTWS14) /*!< Select TMR4_4_OWH for CMP4 */ +#define CMP4_BLANKWIN_TMR4_3_OWL (CMP_TWSR_CTWS15) /*!< Select TMR4_4_OWL for CMP4 */ + +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Valid_Level CMP Blank Window Valid Level + * @{ + */ +#define CMP_BLANKWIN_VALID_LVL_LOW (0U) /*!< Blank window valid level is low */ +#define CMP_BLANKWIN_VALID_LVL_HIGH (1U) /*!< Blank window valid level is high */ +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_output_Level CMP Output Level When Blank Windows Valid + * @{ + */ +#define CMP_BLANKWIN_OUTPUT_LVL_LOW (0U) /*!< Output low when blank windows valid */ +#define CMP_BLANKWIN_OUTPUT_LVL_HIGH (CMP_OCR_TWOL) /*!< Output high when blank windows valid */ +/** + * @} + */ + +/** + * @defgroup CMP_8BitDAC_Adc_Ref_Switch CMP 8 bit DAC ADC Reference Voltage Switch + * @{ + */ +/** + * @} + */ + +/** + * @defgroup CMP_8Bit_Dac_Ch CMP 8 bit DAC Channel + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CMP_Global_Functions + * @{ + */ + +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit); +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit); +void CMP_DeInit(CM_CMP_TypeDef *CMPx); + +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx); +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter); +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity); +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput); +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput); + +int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit); +int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit); + +void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc); +int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowInit); +void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h new file mode 100644 index 0000000000..1f45fc81bf --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h @@ -0,0 +1,161 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.h + * @brief This file contains all the functions prototypes of the CRC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CRC_H__ +#define __HC32_LL_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CRC + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Types CRC Global Types + * @{ + */ + +/** + * @brief CRC initialization structure definition + */ +typedef struct { + uint32_t u32Protocol; /*!< Specifies CRC Protocol. + This parameter can be a value of @ref CRC_Protocol_Control_Bit */ + uint32_t u32InitValue; /*!< Specifies initial CRC value and value upper 16 bit is ignored when using CRC16. + This parameter can be a value of @ref CRC_Initial_Value */ +} stc_crc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Macros CRC Global Macros + * @{ + */ + +/** + * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit + * @note: - CRC16 polynomial is X^16 + X^12 + X^5 + 1 + * - CRC32 polynomial is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + \ + * X^10 + X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 + * @{ + */ +#define CRC_CRC16 (0x0UL) +#define CRC_CRC32 (CRC_CR_CR) +/** + * @} + */ + +/** + * @defgroup CRC_Initial_Value CRC Initial Value + * @{ + */ +#define CRC16_INIT_VALUE (0xFFFFUL) +#define CRC32_INIT_VALUE (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CRC_Global_Functions + * @{ + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit); +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit); +void CRC_DeInit(void); + +en_flag_status_t CRC_GetResultStatus(void); + +uint32_t CRC_AccumulateData8(const uint8_t au8Data[], uint32_t u32Len); +uint32_t CRC_AccumulateData16(const uint16_t au16Data[], uint32_t u32Len); +uint32_t CRC_AccumulateData32(const uint32_t au32Data[], uint32_t u32Len); + +uint32_t CRC_CalculateData8(uint32_t u32InitValue, const uint8_t au8Data[], uint32_t u32Len); +uint32_t CRC_CalculateData16(uint32_t u32InitValue, const uint16_t au16Data[], uint32_t u32Len); +uint32_t CRC_CalculateData32(uint32_t u32InitValue, const uint32_t au32Data[], uint32_t u32Len); + +en_flag_status_t CRC_CheckData8(uint32_t u32InitValue, const uint8_t au8Data[], + uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CheckData16(uint32_t u32InitValue, const uint16_t au16Data[], + uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CheckData32(uint32_t u32InitValue, const uint32_t au32Data[], + uint32_t u32Len, uint32_t u32ExpectValue); + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h new file mode 100644 index 0000000000..80a69be3ee --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h @@ -0,0 +1,198 @@ +/** + ******************************************************************************* + * @file hc32_ll_ctc.h + * @brief This file contains all the functions prototypes of the Clock Trimming + * Controller(CTC) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CTC_H__ +#define __HC32_LL_CTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CTC + * @{ + */ + +#if (LL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Types CTC Global Types + * @{ + */ + +/** + * @brief CTC continuous trim initialization structure definition + */ +typedef struct { + uint32_t u32RefClockFreq; /*!< Reference clock frequency + This parameter should refer user manual recommended values */ + uint32_t u32RefClockSrc; /*!< Reference clock source selection + This parameter can be a value of @ref CTC_Continuous_Trim_Reference_Clock_Source */ + uint32_t u32RefClockDiv; /*!< Reference clock division + This parameter can be a value of @ref CTC_Reference_Clock_Division */ + float32_t f32TolerantErrRate; /*!< CTC tolerance deviation + This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */ + uint8_t u8TrimValue; /*!< CTC TRMVAL value + This parameter can be a value between Min_Data=0 and Max_Data=0x3F */ +} stc_ctc_ct_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Macros CTC Global Macros + * @{ + */ + +/** + * @defgroup CTC_Continuous_Trim_Reference_Clock_Source CTC Continuous Trim Reference Clock Source + * @{ + */ +#define CTC_REF_CLK_SRC_CTCREF (0UL) /*!< Clock source: CTCREF */ +#define CTC_REF_CLK_SRC_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */ +#define CTC_REF_CLK_SRC_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */ +/** + * @} + */ + +/** + * @defgroup CTC_Flag CTC Flag + * @{ + */ +#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */ +#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */ +#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */ +#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */ +#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OVF | CTC_FLAG_TRIM_UDF | \ + CTC_FLAG_TRIM_OK | CTC_FLAG_BUSY) +/** + * @} + */ + +/** + * @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division + * @{ + */ +#define CTC_REF_CLK_DIV8 (0UL) /*!< REFCLK/8 */ +#define CTC_REF_CLK_DIV32 (1UL) /*!< REFCLK/32 */ +#define CTC_REF_CLK_DIV128 (2UL) /*!< REFCLK/128 */ +#define CTC_REF_CLK_DIV256 (3UL) /*!< REFCLK/256 */ +#define CTC_REF_CLK_DIV512 (4UL) /*!< REFCLK/512 */ +#define CTC_REF_CLK_DIV1024 (5UL) /*!< REFCLK/1024 */ +#define CTC_REF_CLK_DIV2048 (6UL) /*!< REFCLK/2048 */ +#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CTC_Global_Functions + * @{ + */ + +/** + * @brief Start CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Start(void) +{ + SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN); +} + +/** + * @brief Stop CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Stop(void) +{ + CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN); +} + +int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit); +int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit); + +int32_t CTC_DeInit(void); +void CTC_IntCmd(en_functional_state_t enNewState); +en_flag_status_t CTC_GetStatus(uint32_t u32Flag); +void CTC_SetTrimValue(uint8_t u8TrimValue); +uint8_t CTC_GetTrimValue(void); +void CTC_SetReloadValue(uint16_t u16ReloadValue); +uint16_t CTC_GetReloadValue(void); +void CTC_SetOffsetValue(uint8_t u8OffsetValue); +uint8_t CTC_GetOffsetValue(void); + +/** + * @} + */ + +#endif /* LL_CTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h new file mode 100644 index 0000000000..764aec7025 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h @@ -0,0 +1,191 @@ +/** + ******************************************************************************* + * @file hc32_ll_dac.h + * @brief This file contains all the functions prototypes of the DAC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DAC_H__ +#define __HC32_LL_DAC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DAC + * @{ + */ + +#if (LL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DAC_Global_Types DAC Global Types + * @{ + */ + +/** + * @brief Structure definition of DAC initialization. + */ +typedef struct { + uint16_t u16Src; /*!< Data source to be converted + This parameter can be a value of @ref DAC_DATA_SRC */ + en_functional_state_t enOutput; /*!< Enable or disable analog output + This parameter can be a value of @ref en_functional_state_t */ +} stc_dac_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Macros DAC Global Macros + * @{ + */ + +/** + * @defgroup DAC_CH DAC channel + * @{ + */ +#define DAC_CH1 (0U) +#define DAC_CH2 (1U) +/** + * @} + */ + +/** + * @defgroup DAC_DATA_SRC DAC data source + * @{ + */ +#define DAC_DATA_SRC_DATAREG (0U) +#define DAC_DATA_SRC_DCU (DAC_DACR_EXTDSL1) +/** + * @} + */ + +/** + * @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern + * @{ + */ +#define DAC_DATA_ALIGN_L (DAC_DACR_ALIGN) +#define DAC_DATA_ALIGN_R (0U) +/** + * @} + */ + +/** + * @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern + * @{ + */ +/** + * @} + */ + +#define DAC_DATAREG_VALUE_MAX (4096UL) + +/** + * @defgroup DAC_ADP_SELECT DAC ADCx priority select + * @{ + */ +#define DAC_ADP_SELECT_ADC1 (DAC_DAADPCR_ADPSL1) +#define DAC_ADP_SELECT_ADC2 (DAC_DAADPCR_ADPSL2) +#define DAC_ADP_SELECT_ADC3 (DAC_DAADPCR_ADPSL3) +#define DAC_ADP_SELECT_ALL (DAC_DAADPCR_ADPSL1 | DAC_DAADPCR_ADPSL2 | DAC_DAADPCR_ADPSL3) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DAC_Global_Functions + * @{ + */ + +int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit); +int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit); +void DAC_DeInit(CM_DAC_TypeDef *DACx); + +void DAC_SetDataSrc(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src); +void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align); +void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +int32_t DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState); +void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState); + +int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch); +int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch); +void DAC_StartDualCh(CM_DAC_TypeDef *DACx); +void DAC_StopDualCh(CM_DAC_TypeDef *DACx); + +void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data); +void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2); +int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch); + +/** + * @} + */ + +#endif /* LL_DAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DAC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h new file mode 100644 index 0000000000..81edf77f50 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h @@ -0,0 +1,297 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.h + * @brief This file contains all the functions prototypes of the DCU(Data + * Computing Unit) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DCU_H__ +#define __HC32_LL_DCU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DCU + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Types DCU Global Types + * @{ + */ + +/** + * @brief DCU initialization structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies DCU operation. + This parameter can be a value of @ref DCU_Mode */ + uint32_t u32DataWidth; /*!< Specifies DCU data width. + This parameter can be a value of @ref DCU_Data_Width */ +} stc_dcu_init_t; + +/** + * @brief DCU wave output configure structure definition + */ +typedef struct { + uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + uint32_t u32Step; /*!< Defines the increasing/decreasing step. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ +} stc_dcu_wave_config_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Macros DCU Global Macros + * @{ + */ + +/** + * @defgroup DCU_Data_Width DCU Data Width + * @{ + */ +#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */ +#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */ +#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */ +/** + * @} + */ + +/** + * @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition + * @{ + */ +#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */ +#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Mode DCU Mode + * @{ + */ +#define DCU_MD_INVD (0UL) /*!< DCU invalid */ +#define DCU_MD_ADD (1UL) /*!< DCU add operation */ +#define DCU_MD_SUB (2UL) /*!< DCU sub operation */ +#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */ +#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */ +#define DCU_MD_CMP (5UL) /*!< DCU compare */ +#define DCU_MD_TRIANGLE_WAVE (8UL) /*!< DCU triangle wave output mode */ +#define DCU_MD_SAWTOOTH_WAVE_INC (9UL) /*!< DCU increasing sawtooth wave output mode */ +#define DCU_MD_SAWTOOTH_WAVE_DEC (10UL) /*!< DCU decreasing sawtooth wave output mode */ +/** + * @} + */ + +/** + * @defgroup DCU_Flag DCU Flag + * @{ + */ +#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */ +#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */ +#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */ +#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */ +#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */ +#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */ +#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */ +#define DCU_FLAG_SAWTOOTH_WAVE_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */ +#define DCU_FLAG_TRIANGLE_WAVE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_FLAG_TRIANGLE_WAVE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */ + +#define DCU_FLAG_ALL (0x00000E7FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Category DCU Category + * @{ + */ +#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */ +#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */ +#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */ +#define DCU_CATEGORY_WAVE (3UL) /*!< DCU wave mode(sawtooth/triangle wave) */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Type DCU Interrupt Type + * @{ + */ +/** + * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt + * @{ + * @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode + */ +#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTSEL_INT_LS2) /*!< DCU DATA0 < DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTSEL_INT_EQ2) /*!< DCU DATA0 = DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTSEL_INT_GT2) /*!< DCU DATA0 > DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTSEL_INT_LS1) /*!< DCU DATA0 < DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTSEL_INT_EQ1) /*!< DCU DATA0 = DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTSEL_INT_GT1) /*!< DCU DATA0 > DATA1 interrupt */ +#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \ + DCU_INT_CMP_DATA0_EQ_DATA2 | \ + DCU_INT_CMP_DATA0_GT_DATA2 | \ + DCU_INT_CMP_DATA0_LT_DATA1 | \ + DCU_INT_CMP_DATA0_EQ_DATA1 | \ + DCU_INT_CMP_DATA0_GT_DATA1) +/** + * @} + */ + +/** + * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt + * @{ + */ +#define DCU_INT_CMP_WIN_INSIDE (DCU_INTSEL_INT_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */ +#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTSEL_INT_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */ +#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE) +/** + * @} + */ + +/** + * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt + * @{ + */ +#define DCU_INT_OP_CARRY (DCU_INTSEL_INT_OP) /*!< DCU addition overflow or subtraction underflow interrupt */ +/** + * @} + */ + +/** + * @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt + * @{ + */ +#define DCU_INT_SAWTOOTH_WAVE_RELOAD (DCU_INTSEL_INT_RLD) /*!< DCU sawtooth wave mode reload interrupt */ +#define DCU_INT_TRIANGLE_WAVE_BOTTOM (DCU_INTSEL_INT_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_INT_TRIANGLE_WAVE_TOP (DCU_INTSEL_INT_TOP) /*!< DCU triangle wave mode top interrupt */ +#define DCU_INT_WAVE_MD_ALL (DCU_INT_TRIANGLE_WAVE_TOP | \ + DCU_INT_TRIANGLE_WAVE_BOTTOM | \ + DCU_INT_SAWTOOTH_WAVE_RELOAD) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup DCU_Data_Register_Index DCU Data Register Index + * @{ + */ +#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */ +#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */ +#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DCU_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit); +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit); +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx); + +int32_t DCU_WaveConfig(CM_DCU_TypeDef *DCUx, const stc_dcu_wave_config_t *pstcWaveconfig); + +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode); +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth); +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond); + +/* Interrupt and flag management functions */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState); +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Read and write functions */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data); +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data); +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data); + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h new file mode 100644 index 0000000000..8d849f87bb --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h @@ -0,0 +1,378 @@ +/** + ******************************************************************************* + * @file hc32_ll_def.h + * @brief This file contains LL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DEF_H__ +#define __HC32_LL_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +/** + * @addtogroup LL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Types LL Common Global Types + * @{ + */ + +/** + * @brief Single precision floating point number (4 byte) + */ +typedef float float32_t; + +/** + * @brief Double precision floating point number (8 byte) + */ +typedef double float64_t; + +/** + * @brief Function pointer type to void/void function + */ +typedef void (*func_ptr_t)(void); + +/** + * @brief Functional state + */ +typedef enum { + DISABLE = 0U, + ENABLE = 1U, +} en_functional_state_t; + +/** + * @brief Flag status + */ +typedef enum { + RESET = 0U, + SET = 1U, +} en_flag_status_t, en_int_status_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Macros LL Common Global Macros + * @{ + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifndef __UNUSED +#define __UNUSED __attribute__((unused)) +#endif /* __UNUSED */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned(4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT +#endif /* __NO_INIT */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned (4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) +/* Usage: __RAM_FUNC void foo(void) */ +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __weak +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE _Pragma("optimize = no_inline") +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __ramfunc +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __align(4) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __NO_INIT +#define __NO_INIT +#endif /* __NO_INIT */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +/* Suppress warning message: extended constant initialiser used */ +#pragma diag_suppress 1296 +#else +#error "unsupported compiler!!" +#endif +/** + * @} + */ + +/** + * @defgroup Extend_Macros Extend Macros + * @{ + */ +/* Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U)) + +/* BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU)) + +/* Returns the dimension of an array */ +#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0]))) + +/* Returns the minimum value out of two values */ +#define LL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +/* Returns the maximum value out of two values */ +#define LL_MAX(x, y) ((x) > (y) ? (x) : (y)) +/** + * @} + */ + +/** + * @defgroup Check_Parameters_Validity Check Parameters Validity + * @{ + */ + +/* Check Functional State */ +#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE)) + +/** + * @defgroup Check_Address_Align_Validity Check Address Align Validity + * @{ + */ +#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL))) +#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL)) +#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup Peripheral_Bit_Band Peripheral Bit Band + * @{ + */ +#define __PERIPH_BIT_BAND_BASE (0x42000000UL) +#define __PERIPH_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE) +#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup Generic_Error_Codes Generic Error Codes + * @{ + */ +#define LL_OK (0) /*!< No error */ +#define LL_ERR (-1) /*!< Non-specific error code */ +#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */ +#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */ +#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */ +#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */ +#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */ +#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */ +#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */ +#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */ +#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */ +/** + * @} + */ + +/** + * @defgroup Chip_Module_Switch Chip Module Switch + * @{ + */ +#define DDL_ON (1U) +#define DDL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Bit_Mask_Macros Bit Mask Macros + * @{ + */ +#define BIT_MASK_00 (1UL << 0U) +#define BIT_MASK_01 (1UL << 1U) +#define BIT_MASK_02 (1UL << 2U) +#define BIT_MASK_03 (1UL << 3U) +#define BIT_MASK_04 (1UL << 4U) +#define BIT_MASK_05 (1UL << 5U) +#define BIT_MASK_06 (1UL << 6U) +#define BIT_MASK_07 (1UL << 7U) +#define BIT_MASK_08 (1UL << 8U) +#define BIT_MASK_09 (1UL << 9U) +#define BIT_MASK_10 (1UL << 10U) +#define BIT_MASK_11 (1UL << 11U) +#define BIT_MASK_12 (1UL << 12U) +#define BIT_MASK_13 (1UL << 13U) +#define BIT_MASK_14 (1UL << 14U) +#define BIT_MASK_15 (1UL << 15U) +#define BIT_MASK_16 (1UL << 16U) +#define BIT_MASK_17 (1UL << 17U) +#define BIT_MASK_18 (1UL << 18U) +#define BIT_MASK_19 (1UL << 19U) +#define BIT_MASK_20 (1UL << 20U) +#define BIT_MASK_21 (1UL << 21U) +#define BIT_MASK_22 (1UL << 22U) +#define BIT_MASK_23 (1UL << 23U) +#define BIT_MASK_24 (1UL << 24U) +#define BIT_MASK_25 (1UL << 25U) +#define BIT_MASK_26 (1UL << 26U) +#define BIT_MASK_27 (1UL << 27U) +#define BIT_MASK_28 (1UL << 28U) +#define BIT_MASK_29 (1UL << 29U) +#define BIT_MASK_30 (1UL << 30U) +#define BIT_MASK_31 (1UL << 31U) +/** + * @} + */ + +/** + * @defgroup Register_Macros Register Macros + * @{ + */ +#define RW_MEM8(addr) (*(volatile uint8_t *)(addr)) +#define RW_MEM16(addr) (*(volatile uint16_t *)(addr)) +#define RW_MEM32(addr) (*(volatile uint32_t *)(addr)) + +#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT)) +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT))) +#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT))))) +#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT))))) +#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define READ_REG_BIT(REG, BIT) ((REG) & (BIT)) +#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT))) +#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT))) +#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT))) + +#define CLR_REG(REG) ((REG) = (0U)) +#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U))) +#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U))) +#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL))) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define READ_REG(REG) (REG) +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK))))) +#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK))))) +#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK))))) +#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK))))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h new file mode 100644 index 0000000000..66f2933ee0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h @@ -0,0 +1,620 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.h + * @brief This file contains all the functions prototypes of the DMA driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DMA_H__ +#define __HC32_LL_DMA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DMA + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Types DMA Global Types + * @{ + */ + +/** + * @brief DMA basic configuration + */ +typedef struct { + uint32_t u32IntEn; /*!< Specifies the DMA interrupt function. + This parameter can be a value of @ref DMA_Int_Config */ + uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */ + uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */ + uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width. + This parameter can be a value of @ref DMA_DataWidth_Sel */ + uint32_t u32BlockSize; /*!< Specifies the DMA block size. */ + uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */ + uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode. + This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */ + uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode. + This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */ +} stc_dma_init_t; + +/** + * @brief DMA repeat mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */ +} stc_dma_repeat_init_t; + +/** + * @brief DMA non-sequence mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */ + uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */ + uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */ +} stc_dma_nonseq_init_t; + +/** + * @brief DMA Link List Pointer (LLP) mode configuration + */ +typedef struct { + uint32_t u32State; /*!< Specifies the DMA LLP function. + This parameter can be a value of @ref DMA_Llp_En */ + uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ. + This parameter can be a value of @ref DMA_Llp_Mode */ + uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */ +} stc_dma_llp_init_t; + +/** + * @brief DMA re-config function configuration + */ +typedef struct { + uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode. + This parameter can be a value of @ref DMA_Reconfig_Count_Sel */ + uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode. + This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */ + uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode. + This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */ +} stc_dma_reconfig_init_t; + +/** + * @brief Dma LLP(linked list pointer) descriptor structure definition + */ +typedef struct { + uint32_t SARx; /*!< LLP source address */ + uint32_t DARx; /*!< LLP destination address */ + uint32_t DTCTLx; /*!< LLP transfer count and block size */ + uint32_t RPTx; /*!< LLP source & destination repeat size */ + uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */ + uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */ + uint32_t LLPx; /*!< LLP next list pointer */ + uint32_t CHCTLx; /*!< LLP channel control */ +} stc_dma_llp_descriptor_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Macros DMA Global Macros + * @{ + */ + +/** + * @defgroup DMA_Channel_selection DMA Channel Position selection + * @{ + */ +#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */ +#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */ + +#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */ +#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */ + +#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */ +#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */ +#define DMA_CH6 (0x06U) /*!< DMA Channel 6 */ +#define DMA_CH7 (0x07U) /*!< DMA Channel 7 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection + * @{ + */ +#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */ +#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */ +#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */ + +#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */ +#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */ + +#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */ +#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */ +#define DMA_MX_CH6 (0x40UL) /*!< DMA Channel 6 position */ +#define DMA_MX_CH7 (0x80UL) /*!< DMA Channel 7 position */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection + * @{ + */ +#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */ +#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */ + +#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */ +#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */ + +#define DMA_FLAG_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error flag CH.4 */ +#define DMA_FLAG_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error flag CH.5 */ +#define DMA_FLAG_REQ_ERR_CH6 (DMA_INTSTAT0_REQERR_6) /*!< DMA request error flag CH.6 */ +#define DMA_FLAG_REQ_ERR_CH7 (DMA_INTSTAT0_REQERR_7) /*!< DMA request error flag CH.7 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection + * @{ + */ +#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */ +#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */ + +#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */ +#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */ + +#define DMA_FLAG_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error flag CH.4 */ +#define DMA_FLAG_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error flag CH.5 */ +#define DMA_FLAG_TRANS_ERR_CH6 (DMA_INTSTAT0_TRNERR_6) /*!< DMA transfer error flag CH.6 */ +#define DMA_FLAG_TRANS_ERR_CH7 (DMA_INTSTAT0_TRNERR_7) /*!< DMA transfer error flag CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection + * @{ + */ +#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */ +#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */ + +#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */ +#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */ + +#define DMA_FLAG_BTC_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed flag CH.4 */ +#define DMA_FLAG_BTC_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed flag CH.5 */ +#define DMA_FLAG_BTC_CH6 (DMA_INTSTAT1_BTC_6) /*!< DMA block transfer completed flag CH.6 */ +#define DMA_FLAG_BTC_CH7 (DMA_INTSTAT1_BTC_7) /*!< DMA block transfer completed flag CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection + * @{ + */ +#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */ +#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */ + +#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */ +#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */ + +#define DMA_FLAG_TC_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed flag CH.4 */ +#define DMA_FLAG_TC_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed flag CH.5 */ +#define DMA_FLAG_TC_CH6 (DMA_INTSTAT1_TC_6) /*!< DMA transfer completed flag CH.6 */ +#define DMA_FLAG_TC_CH7 (DMA_INTSTAT1_TC_7) /*!< DMA transfer completed flag CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection + * @{ + */ +#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */ +#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */ + +#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */ +#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */ + +#define DMA_INT_REQ_ERR_CH4 (DMA_INTMASK0_MSKREQERR_4) /*!< DMA request error interrupt CH.4 */ +#define DMA_INT_REQ_ERR_CH5 (DMA_INTMASK0_MSKREQERR_5) /*!< DMA request error interrupt CH.5 */ +#define DMA_INT_REQ_ERR_CH6 (DMA_INTMASK0_MSKREQERR_6) /*!< DMA request error interrupt CH.6 */ +#define DMA_INT_REQ_ERR_CH7 (DMA_INTMASK0_MSKREQERR_7) /*!< DMA request error interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection + * @{ + */ +#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */ +#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */ + +#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */ +#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */ + +#define DMA_INT_TRANS_ERR_CH4 (DMA_INTMASK0_MSKTRNERR_4) /*!< DMA transfer error interrupt CH.4 */ +#define DMA_INT_TRANS_ERR_CH5 (DMA_INTMASK0_MSKTRNERR_5) /*!< DMA transfer error interrupt CH.5 */ +#define DMA_INT_TRANS_ERR_CH6 (DMA_INTMASK0_MSKTRNERR_6) /*!< DMA transfer error interrupt CH.6 */ +#define DMA_INT_TRANS_ERR_CH7 (DMA_INTMASK0_MSKTRNERR_7) /*!< DMA transfer error interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection + * @{ + */ +#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */ +#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */ + +#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */ +#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */ + +#define DMA_INT_BTC_CH4 (DMA_INTMASK1_MSKBTC_4) /*!< DMA block transfer completed interrupt CH.4 */ +#define DMA_INT_BTC_CH5 (DMA_INTMASK1_MSKBTC_5) /*!< DMA block transfer completed interrupt CH.5 */ +#define DMA_INT_BTC_CH6 (DMA_INTMASK1_MSKBTC_6) /*!< DMA block transfer completed interrupt CH.6 */ +#define DMA_INT_BTC_CH7 (DMA_INTMASK1_MSKBTC_7) /*!< DMA block transfer completed interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection + * @{ + */ +#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */ +#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */ + +#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */ +#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */ + +#define DMA_INT_TC_CH4 (DMA_INTMASK1_MSKTC_4) /*!< DMA transfer completed interrupt CH.4 */ +#define DMA_INT_TC_CH5 (DMA_INTMASK1_MSKTC_5) /*!< DMA transfer completed interrupt CH.5 */ +#define DMA_INT_TC_CH6 (DMA_INTMASK1_MSKTC_6) /*!< DMA transfer completed interrupt CH.6 */ +#define DMA_INT_TC_CH7 (DMA_INTMASK1_MSKTC_7) /*!< DMA transfer completed interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_FlagMsk_Sel DMA flag mask selection + * @{ + */ +#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */ +#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */ +/** + * @} + */ + +/** + * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection + * @{ + */ +#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */ +#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Req_Status_Sel DMA request status + * @{ + */ +#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */ +#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */ +#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */ +#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */ +#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */ + +#define DMA_STAT_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */ +#define DMA_STAT_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */ +#define DMA_STAT_REQ_CH6 (DMA_REQSTAT_CHREQ_6) /*!< DMA request from CH.6 */ +#define DMA_STAT_REQ_CH7 (DMA_REQSTAT_CHREQ_7) /*!< DMA request from CH.7 */ + +#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Trans_Status_Sel DMA transfer status + * @{ + */ +#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */ +#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */ +#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */ + +#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */ +#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */ + +#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */ + +#define DMA_STAT_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */ +#define DMA_STAT_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */ +#define DMA_STAT_TRANS_CH6 (DMA_CHSTAT_CHACT_6) /*!< DMA transfer status of CH.6 */ +#define DMA_STAT_TRANS_CH7 (DMA_CHSTAT_CHACT_7) /*!< DMA transfer status of CH.7 */ + +#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT) +/** + * @} + */ + +/** + * @defgroup DMA_DataWidth_Sel DMA transfer data width + * @{ + */ +#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */ +#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */ +#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable + * @{ + */ +#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */ + +#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete + * @{ + */ +#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transfering complete */ + +#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transfering complete */ + +/** + * @} + */ + +/** + * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode + * @{ + */ +#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */ + +#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */ +#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */ + +/** + * @} + */ + +/** + * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode + * @{ + */ +#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */ +#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */ +#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Config DMA interrupt function config + * @{ + */ +#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */ +#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Repeat_Config DMA repeat mode function config + * @{ + */ +#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */ +#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */ +#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */ +#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config + * @{ + */ +#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */ +#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */ +#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */ +#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection + * @{ + */ +#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */ +#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */ +#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection + * @{ + */ +#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */ +#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */ +#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection + * @{ + */ +#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */ +#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */ +#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DMA_Global_Functions + * @{ + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); + +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState); +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); + +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count); +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); + +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); + +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); + +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit); +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit); +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit); +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit); + +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit); + +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit); +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit); + +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit); +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit); +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DMA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dmc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dmc.h new file mode 100644 index 0000000000..3e619fe058 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dmc.h @@ -0,0 +1,416 @@ +/** + ******************************************************************************* + * @file hc32_ll_dmc.h + * @brief This file contains all the functions prototypes of the EXMC_DMC + * (External Memory Controller: Dynamic Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DMC_H__ +#define __HC32_LL_DMC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EXMC + * @{ + */ + +/** + * @addtogroup LL_DMC + * @{ + */ + +#if (LL_DMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Types EXMC_DMC Global Types + * @{ + */ + +/** + * @brief EXMC_DMC Chip Configuration Structure definition + */ +typedef struct { + uint32_t u32AddrMask; /*!< Defines the address mask. + This parameter can be a value of @ref EXMC_DMC_Mask_Address. */ + uint32_t u32AddrMatch; /*!< Defines the address match. + This parameter can be a value between Min_Data = 0x80 and Max_Data = 0x87 */ + uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode. + This parameter can be a value of @ref EXMC_DMC_Address_Decode_Mode. */ +} stc_exmc_dmc_chip_config_t; + +/** + * @brief EXMC_DMC Initialization Structure definition + */ +typedef struct { + uint32_t u32SampleClock; /*!< DMC sample clock. + This parameter can be a value of @ref EXMC_DMC_Sample_Clock. */ + uint32_t u32MemoryWidth; /*!< DMC memory width. + This parameter can be a value of @ref EXMC_DMC_Memory_Width. */ + uint32_t u32RefreshPeriod; /*!< DMC memory refresh period. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */ + uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */ + uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address. + This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */ + uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin. + This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */ + uint32_t u32MemClockSel; /*!< Defines the memory clock selection. + This parameter can be a value of @ref EXMC_DMC_Clock_Selection */ + uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection. + This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */ + uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period. + This parameter can be a value between Min_Data = 0x00 and Max_Data = 0x3F */ + uint32_t u32MemBurst; /*!< Defines the number of data accesses. + This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */ + uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips. + This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */ + struct { + uint8_t u8CASL; /*!< Defines the CAS latency in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8DQSS; /*!< Defines the DQSS in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 3 */ + uint8_t u8MRD; /*!< Defines the the mode register command time in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */ + uint8_t u8RAS; /*!< Defines the RAS in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8RC; /*!< Defines the RC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8RCD_B; /*!< Defines the RCD base value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8RCD_P; /*!< Defines the RCD append value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8RFC_B; /*!< Defines the RFC base value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */ + uint8_t u8RFC_P; /*!< Defines the RFC append value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */ + uint8_t u8RP_B; /*!< Defines the RP base value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8RP_P; /*!< Defines the RP append value in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8RRD; /*!< Defines the RRD in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8WR; /*!< Defines the WR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8WTR; /*!< Defines the WTR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8XP; /*!< Defines the XP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint8_t u8XSR; /*!< Defines the XSR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint8_t u8ESR; /*!< Defines the ESR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + } stcTimingConfig; +} stc_exmc_dmc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Macros EXMC_DMC Global Macros + * @{ + */ + +/** + * @defgroup EXMC_DMC_Memory_Width EXMC_DMC Memory Width + * @{ + */ +#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL) +#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Chip EXMC_DMC Chip + * @{ + */ +#define EXMC_DMC_CHIP0 (0UL) /*!< Chip 0 */ +#define EXMC_DMC_CHIP1 (1UL) /*!< Chip 1 */ +#define EXMC_DMC_CHIP2 (2UL) /*!< Chip 2 */ +#define EXMC_DMC_CHIP3 (3UL) /*!< Chip 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Bank EXMC_DMC Bank + * @{ + */ +#define EXMC_DMC_BANK0 (0UL) /*!< Bank 0 */ +#define EXMC_DMC_BANK1 (1UL) /*!< Bank 1 */ +#define EXMC_DMC_BANK2 (2UL) /*!< Bank 2 */ +#define EXMC_DMC_BANK3 (3UL) /*!< Bank 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Current_Status EXMC_DMC Current Status + * @{ + */ +#define EXMC_DMC_CURR_STATUS_CONFIG (0UL) +#define EXMC_DMC_CURR_STATUS_RDY (DMC_STSR_STATUS_0) +#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1) +#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Control_State EXMC_DMC Control State + * @{ + */ +#define EXMC_DMC_CTRL_STATE_GO (0UL) +#define EXMC_DMC_CTRL_STATE_SLEEP (1UL) +#define EXMC_DMC_CTRL_STATE_WAKEUP (2UL) +#define EXMC_DMC_CTRL_STATE_PAUSE (3UL) +#define EXMC_DMC_CTRL_STATE_CONFIG (4UL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Command EXMC_DMC Command + * @{ + */ +#define EXMC_DMC_CMD_PRECHARGE_ALL (0UL) /*!< Precharge all */ +#define EXMC_DMC_CMD_AUTO_REFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */ +#define EXMC_DMC_CMD_MDREG_CONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */ +#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Address_Decode_Mode EXMC_DMC Address Decode Mode + * @{ + */ +#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */ +#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Column_Bits_Number EXMC_DMC Column Bits Number + * @{ + */ +#define EXMC_DMC_COLUMN_BITS_NUM8 (0UL) +#define EXMC_DMC_COLUMN_BITS_NUM9 (1UL << DMC_CPCR_COLBS_POS) +#define EXMC_DMC_COLUMN_BITS_NUM10 (2UL << DMC_CPCR_COLBS_POS) +#define EXMC_DMC_COLUMN_BITS_NUM11 (3UL << DMC_CPCR_COLBS_POS) +#define EXMC_DMC_COLUMN_BITS_NUM12 (4UL << DMC_CPCR_COLBS_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Row_Bits_Number EXMC_DMC Row Bits Number + * @{ + */ +#define EXMC_DMC_ROW_BITS_NUM11 (0UL) +#define EXMC_DMC_ROW_BITS_NUM12 (1UL << DMC_CPCR_ROWBS_POS) +#define EXMC_DMC_ROW_BITS_NUM13 (2UL << DMC_CPCR_ROWBS_POS) +#define EXMC_DMC_ROW_BITS_NUM14 (3UL << DMC_CPCR_ROWBS_POS) +#define EXMC_DMC_ROW_BITS_NUM15 (4UL << DMC_CPCR_ROWBS_POS) +#define EXMC_DMC_ROW_BITS_NUM16 (5UL << DMC_CPCR_ROWBS_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC_DMC Auto Pre-charge Pin + * @{ + */ +#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS) +#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_CKE_Output_Selection EXMC_DMC CKE Output Selection + * @{ + */ +#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL) +#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Clock_Selection EXMC_DMC Clock Selection + * @{ + */ +#define EXMC_DMC_CLK_NORMAL_OUTPUT (0UL) +#define EXMC_DMC_CLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Memory_Burst EXMC_DMC Memory Burst + * @{ + */ +#define EXMC_DMC_BURST_1BEAT (0UL) +#define EXMC_DMC_BURST_2BEAT (1UL << DMC_CPCR_BURST_POS) +#define EXMC_DMC_BURST_4BEAT (2UL << DMC_CPCR_BURST_POS) +#define EXMC_DMC_BURST_8BEAT (3UL << DMC_CPCR_BURST_POS) +#define EXMC_DMC_BURST_16BEAT (4UL << DMC_CPCR_BURST_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC_DMC Auto Refresh + * @{ + */ +#define EXMC_DMC_AUTO_REFRESH_1CHIP (0UL) +#define EXMC_DMC_AUTO_REFRESH_2CHIPS (DMC_CPCR_ACTCP_0) +#define EXMC_DMC_AUTO_REFRESH_3CHIPS (DMC_CPCR_ACTCP_1) +#define EXMC_DMC_AUTO_REFRESH_4CHIPS (DMC_CPCR_ACTCP) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Mask_Address EXMC_DMC Mask Address + * @{ + */ +#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL) +#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL) +#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL) +#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Address_Space EXMC_DMC Address Space + * @{ + */ +#define EXMC_DMC_ADDR_MIN (0x80000000UL) +#define EXMC_DMC_ADDR_MAX (0x87FFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Sample_Clock EXMC_DMC Sample Clock + * @{ + */ +#define EXMC_DMC_SAMPLE_CLK_INTERNCLK (0UL) +#define EXMC_DMC_SAMPLE_CLK_INTERNCLK_INVT (DMC_BACR_CKSEL_0) +#define EXMC_DMC_SAMPLE_CLK_EXTCLK (DMC_BACR_CKSEL_1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_DMC_Global_Functions + * @{ + */ + +/** + * @brief Get DMC status. + * @param None + * @retval Returned value can be one of the macros group @ref EXMC_DMC_Current_Status + * - EXMC_DMC_CURR_STATUS_CONFIG: Configure status + * - EXMC_DMC_CURR_STATUS_RDY: Ready status + * - EXMC_DMC_CURR_STATUS_PAUSED: Pause status + * - EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status + */ +__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void) +{ + return READ_REG32_BIT(CM_DMC->STSR, DMC_STSR_STATUS); +} + +/* Initialization and configuration EXMC_DMC functions */ +int32_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcDmcInit); +int32_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcDmcInit); +void EXMC_DMC_DeInit(void); + +void EXMC_DMC_Cmd(en_functional_state_t enNewState); +void EXMC_DMC_SetState(uint32_t u32State); + +int32_t EXMC_DMC_ChipConfig(uint32_t u32Chip, const stc_exmc_dmc_chip_config_t *pstcChipConfig); +uint32_t EXMC_DMC_GetChipStartAddr(uint32_t u32Chip); +uint32_t EXMC_DMC_GetChipEndAddr(uint32_t u32Chip); +void EXMC_DMC_SetCommand(uint32_t u32Chip, uint32_t u32Bank, uint32_t u32Cmd, uint32_t u32Addr); + +/** + * @} + */ + +#endif /* LL_DMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DMC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dvp.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dvp.h new file mode 100644 index 0000000000..706d0a9229 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dvp.h @@ -0,0 +1,296 @@ +/** + ******************************************************************************* + * @file hc32_ll_dvp.h + * @brief This file contains all the functions prototypes of the DVP(Digital + * Video Processor) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DVP_H__ +#define __HC32_LL_DVP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DVP + * @{ + */ + +#if (LL_DVP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Types DVP Global Types + * @{ + */ + +/** + * @brief DVP Initialization Structure definition + */ +typedef struct { + uint32_t u32SyncMode; /*!< The DVP sync mode. + This parameter can be a value of @ref DVP_Sync_Mode. */ + uint32_t u32DataWidth; /*!< The DVP data interface width. + This parameter can be a value of @ref DVP_Data_Width. */ + uint32_t u32CaptureMode; /*!< The DVP capture mode. + This parameter can be a value of @ref DVP_Capture_Mode. */ + uint32_t u32CaptureFreq; /*!< The DVP capture frequency. + This parameter can be a value of @ref DVP_Capture_Frequency. */ + uint32_t u32PIXCLKPolarity; /*!< The DVP_PIXCLK Polarity. + This parameter can be a value of @ref DVP_PIXCLK_Polarity. */ + uint32_t u32HSYNCPolarity; /*!< The DVP_HSYNC Polarity. + This parameter can be a value of @ref DVP_HSYNC_Polarity. */ + uint32_t u32VSYNCPolarity; /*!< The DVP_VSYNC Polarity. + This parameter can be a value of @ref DVP_VSYNC_Polarity. */ +} stc_dvp_init_t; + +/** + * @brief DVP Crop Window Configure definition + */ +typedef struct { + uint16_t u16RowStartLine; /*!< The DVP window row start line. + This parameter can be a value between 0x00 and 0x3FFF */ + uint16_t u16ColoumStartLine; /*!< The DVP window coloum start line. + This parameter can be a value between 0x00 and 0x3FFF */ + uint16_t u16RowLineSize; /*!< The DVP window row line size. + This parameter can be a value between 0x04 and 0x3FFF */ + uint16_t u16ColoumLineSize; /*!< The DVP window coloum line size. + This parameter can be a value between 0x00 and 0x3FFF */ +} stc_dvp_crop_window_config_t; + +/** + * @brief DVP Software Sync Code definition + */ +typedef struct { + uint8_t u8FrameStartSyncCode; /*!< The sync code of the frame start delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint8_t u8LineStartSyncCode; /*!< The sync code of the line start delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint8_t u8LineEndSyncCode; /*!< The sync code of the line end delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint8_t u8FrameEndSyncCode; /*!< The sync code of the frame end delimiter. + This parameter can be a value between 0x00 and 0xFF */ +} stc_dvp_sw_sync_code_t; + +/** + * @brief DVP Software Mask Code definition + */ +typedef struct { + uint8_t u8FrameStartMaskCode; /*!< The mask code of the frame start delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint8_t u8LineStartMaskCode; /*!< The mask code of the line start delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint8_t u8LineEndMaskCode; /*!< The mask code of the line end delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint8_t u8FrameEndMaskCode; /*!< The mask code of the frame end delimiter. + This parameter can be a value between between 0x00 and 0xFF */ +} stc_dvp_sw_mask_code_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Macros DVP Global Macros + * @{ + */ + +/** + * @defgroup DVP_Capture_Mode DVP Capture Mode + * @{ + */ +#define DVP_CAPT_MD_CONTINUOS_FRAME (0UL) +#define DVP_CAPT_MD_SINGLE_FRAME (DVP_CTR_CAPMD) +/** + * @} + */ + +/** + * @defgroup DVP_Sync_Mode DVP Sync Mode + * @{ + */ +#define DVP_SYNC_MD_HW (0UL) /*!< Hardware sync */ +#define DVP_SYNC_MD_SW (DVP_CTR_SWSYNC) /*!< Software sync */ +/** + * @} + */ + +/** + * @defgroup DVP_PIXCLK_Polarity DVP PIXCLK Polarity + * @{ + */ +#define DVP_PIXCLK_FALLING (0UL) /*!< DVP_PIXCLK active on Falling edge */ +#define DVP_PIXCLK_RISING (DVP_CTR_PIXCKSEL) /*!< DVP_PIXCLK active on Rising edge */ +/** + * @} + */ + +/** + * @defgroup DVP_HSYNC_Polarity DVP HSYNC Polarity + * @{ + */ +#define DVP_HSYNC_LOW (0UL) /*!< DVP_HSYNC active Low */ +#define DVP_HSYNC_HIGH (DVP_CTR_HSYNCSEL) /*!< DVP_HSYNC active High */ +/** + * @} + */ + +/** + * @defgroup DVP_VSYNC_Polarity DVP VSYNC Polarity + * @{ + */ +#define DVP_VSYNC_LOW (0UL) /*!< DVP_VSYNC active Low */ +#define DVP_VSYNC_HIGH (DVP_CTR_VSYNCSEL) /*!< DVP_VSYNC active High */ +/** + * @} + */ + +/** + * @defgroup DVP_Capture_Frequency DVP Capture Frequency + * @{ + */ +#define DVP_CAPT_FREQ_ALL_FRAME (0UL) /*!< All frames are captured */ +#define DVP_CAPT_FREQ_ONT_TIME_2FRAME (DVP_CTR_CAPFRC_0) /*!< One frame per 2 frames captured */ +#define DVP_CAPT_FREQ_ONT_TIME_4FRAME (DVP_CTR_CAPFRC_1) /*!< One frame per 4 frames captured */ +/** + * @} + */ + +/** + * @defgroup DVP_Data_Width DVP Data Width + * @{ + */ +#define DVP_DATA_WIDTH_8BIT (0UL) /*!< DVP captures 8-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_10BIT (DVP_CTR_BITSEL_0) /*!< DVP captures 10-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_12BIT (DVP_CTR_BITSEL_1) /*!< DVP captures 12-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_14BIT (DVP_CTR_BITSEL) /*!< DVP captures 14-bit data on every DVP_PIXCLK clock */ +/** + * @} + */ + +/** + * @defgroup DVP_Flag DVP Flag + * @{ + */ +#define DVP_FLAG_FRAME_START (DVP_STR_FSF) /*!< Frame start flag */ +#define DVP_FLAG_LINE_START (DVP_STR_LSF) /*!< Line start flag */ +#define DVP_FLAG_LINE_END (DVP_STR_LEF) /*!< Line end flag */ +#define DVP_FLAG_FRAME_END (DVP_STR_FEF) /*!< Frame end flag */ +#define DVP_FLAG_FIFO_OVF (DVP_STR_FIFOERF) /*!< FIFO overflow error flag */ +#define DVP_FLAG_SYNC_ERR (DVP_STR_SQUERF) /*!< Sync error flag */ +#define DVP_FLAG_ALL (DVP_FLAG_SYNC_ERR | \ + DVP_FLAG_FIFO_OVF | \ + DVP_FLAG_LINE_END | \ + DVP_FLAG_LINE_START | \ + DVP_FLAG_FRAME_END | \ + DVP_FLAG_FRAME_START) +/** + * @} + */ + +/** + * @defgroup DVP_Interrupt DVP Interrupt + * @{ + */ +#define DVP_INT_FRAME_START (DVP_IER_FSIEN) /*!< Frame start interrupt */ +#define DVP_INT_LINE_START (DVP_IER_LSIEN) /*!< Line start interrupt */ +#define DVP_INT_LINE_END (DVP_IER_LEIEN) /*!< Line end interrupt */ +#define DVP_INT_FRAME_END (DVP_IER_FEIEN) /*!< Frame end interrupt */ +#define DVP_INT_FIFO_OVF (DVP_IER_FIFOERIEN) /*!< FIFO overflow error interrupt */ +#define DVP_INT_SYNC_ERR (DVP_IER_SQUERIEN) /*!< Sync error interrupt */ +#define DVP_INT_ALL (DVP_INT_SYNC_ERR | \ + DVP_INT_FIFO_OVF | \ + DVP_INT_LINE_END | \ + DVP_INT_LINE_START | \ + DVP_INT_FRAME_END | \ + DVP_INT_FRAME_START) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DVP_Global_Functions + * @{ + */ +int32_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit); +int32_t DVP_Init(const stc_dvp_init_t *pstcDvpInit); +void DVP_DeInit(void); + +void DVP_Cmd(en_functional_state_t enNewState); +void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void DVP_CropCmd(en_functional_state_t enNewState); +void DVP_JPEGCmd(en_functional_state_t enNewState); +void DVP_CaptrueCmd(en_functional_state_t enNewState); +en_flag_status_t DVP_GetStatus(uint32_t u32Flag); +void DVP_ClearStatus(uint32_t u32Flag); +int32_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode); +int32_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode); +int32_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig); +/** + * @} + */ + +#endif /* LL_DVP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DVP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h new file mode 100644 index 0000000000..2de7132451 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h @@ -0,0 +1,680 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.h + * @brief This file contains all the functions prototypes of the EFM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EFM_H__ +#define __HC32_LL_EFM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EFM + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Types EFM Global Types + * @{ + */ +/** + * @brief EFM unique ID definition + */ +typedef struct { + uint32_t u32UniqueID0; /*!< unique ID 0. */ + uint32_t u32UniqueID1; /*!< unique ID 1. */ + uint32_t u32UniqueID2; /*!< unique ID 2. */ +} stc_efm_unique_id_t; + +typedef struct { + uint32_t u32State; + uint32_t u32Addr; + uint32_t u32Size; +} stc_efm_remap_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Macros EFM Global Macros + * @{ + */ +/** + * @defgroup EFM_Address EFM Address Area + * @{ + */ +#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */ + +#define EFM_END_ADDR (0x001FFFFFUL) /*!< Flash end address */ +#define EFM_OTP_START_ADDR1 (0x00000000UL) /*!< OTP start address */ +#define EFM_OTP_END_ADDR1 (0x0001FFFFUL) +#define EFM_OTP_START_ADDR (0x03000000UL) +#define EFM_OTP_END_ADDR (0x030017FFUL) /*!< OTP end address */ +#define EFM_OTP_LOCK_ADDR_START (0x03001800UL) /*!< OTP lock address */ +#define EFM_OTP_LOCK_ADDR_END (0x03001AD7UL) /*!< OTP lock address */ +#define EFM_OTP_ENABLE_ADDR (0x03001AD8UL) +#define EFM_FLASH_1_START_ADDR (0x00100000UL) + +/** + * @} + */ + +/** + * @defgroup EFM_Chip_Sel EFM Chip Selection + * @{ + */ +#define EFM_CHIP0 (EFM_FSTP_F0STP) +#define EFM_CHIP1 (EFM_FSTP_F1STP) +#define EFM_CHIP_ALL (EFM_FSTP_F0STP | EFM_FSTP_F1STP) + +/** + * @} + */ + +/** + * @defgroup EFM_Bus_Status EFM Bus Status + * @{ + */ +#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */ +#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */ +/** + * @} + */ + +/** + * @defgroup EFM_Wait_Cycle EFM Wait Cycle + * @{ + */ + +#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */ +#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */ + +#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */ +#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */ +#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */ +#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */ +#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */ +#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */ +#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */ +#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */ +#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */ +#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */ +#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */ +#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */ +#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */ +#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */ +/** + * @} + */ + +/** + * @defgroup EFM_Swap_Address EFM Swap Address + * @{ + */ +#define EFM_SWAP_ADDR (0x03002000UL) +#define EFM_SWAP_DATA (0x005A5A5AUL) +/** + * @} + */ + +/** + * @defgroup EFM_WriteLock_Sel EFM Write Protect Lock Selection + * @{ + */ +#define EFM_WRLOCK0 (EFM_WLOCK_WLOCK_0) /*!< F0NWPRT0 controlled sector lock */ +#define EFM_WRLOCK1 (EFM_WLOCK_WLOCK_1) /*!< F0NWPRT1 controlled sector lock */ +#define EFM_WRLOCK2 (EFM_WLOCK_WLOCK_2) /*!< F0NWPRT2 controlled sector lock */ +#define EFM_WRLOCK3 (EFM_WLOCK_WLOCK_3) /*!< F0NWPRT3 controlled sector lock */ +#define EFM_WRLOCK4 (EFM_WLOCK_WLOCK_4) /*!< F1NWPRT0 controlled sector lock */ +#define EFM_WRLOCK5 (EFM_WLOCK_WLOCK_5) /*!< F1NWPRT1 controlled sector lock */ +#define EFM_WRLOCK6 (EFM_WLOCK_WLOCK_6) /*!< F1NWPRT2 controlled sector lock */ +#define EFM_WRLOCK7 (EFM_WLOCK_WLOCK_7) /*!< F1NWPRT3 controlled sector lock */ +/** + * @} + */ + +/** + * @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection + * @{ + */ +#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */ +#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */ +#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */ +#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */ +#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */ + +#define EFM_MD_ERASE_ONE_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< A flash Chip erase mode */ +#define EFM_MD_ERASE_ALL_CHIP (0x6UL << EFM_FWMC_PEMOD_POS) /*!< All chip erase mode */ + +/** + * @} + */ + +/** + * @defgroup EFM_Flag_Sel EFM Flag Selection + * @{ + */ +#define EFM_FLAG_OTPWERR (EFM_FSR_OTPWERR0) /*!< EFM Flash0 otp Programming/erase error flag. */ +#define EFM_FLAG_PEPRTERR (EFM_FSR_PRTWERR0) /*!< EFM Flash0 write protect address error flag. */ +#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR0) /*!< EFM Flash0 programming size error flag. */ +#define EFM_FLAG_PGMISMTCH (EFM_FSR_MISMTCH0) /*!< EFM Flash0 programming missing match error flag. */ +#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND0) /*!< EFM Flash0 end of operation flag. */ +#define EFM_FLAG_COLERR (EFM_FSR_COLERR0) /*!< EFM Flash0 read collide error flag. */ +#define EFM_FLAG_RDY (EFM_FSR_RDY0) /*!< EFM Flash0 ready flag. */ +#define EFM_FLAG_PEPRTERR1 (EFM_FSR_PRTWERR1) /*!< EFM Flash1 write protect address error flag. */ +#define EFM_FLAG_PGSZERR1 (EFM_FSR_PGSZERR1) /*!< EFM Flash1 programming size error flag. */ +#define EFM_FLAG_PGMISMTCH1 (EFM_FSR_MISMTCH1) /*!< EFM Flash1 programming missing match error flag. */ +#define EFM_FLAG_OPTEND1 (EFM_FSR_OPTEND1) /*!< EFM Flash1 end of operation flag. */ +#define EFM_FLAG_COLERR1 (EFM_FSR_COLERR1) /*!< EFM Flash1 read collide error flag. */ +#define EFM_FLAG_RDY1 (EFM_FSR_RDY1) /*!< EFM Flash1 ready flag. */ + +#define EFM_FLAG_ALL (EFM_FLAG_OTPWERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | EFM_FLAG_PGMISMTCH | \ + EFM_FLAG_OPTEND | EFM_FLAG_COLERR | EFM_FLAG_PEPRTERR1 | EFM_FLAG_PGSZERR1 | \ + EFM_FLAG_OPTEND1 | EFM_FLAG_COLERR1 | EFM_FLAG_RDY | EFM_FLAG_PGMISMTCH1 | \ + EFM_FLAG_RDY1) + +/** + * @} + */ + +/** + * @defgroup EFM_Interrupt_Sel EFM Interrupt Selection + * @{ + */ +#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */ +#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */ +#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */ + +#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE) +/** + * @} + */ + +/** + * @defgroup EFM_Keys EFM Keys + * @{ + */ +#define EFM_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REG_UNLOCK_KEY2 (0x3210UL) +#define EFM_REG_LOCK_KEY (0x0000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Size EFM Sector Size + * @{ + */ +#define SECTOR_SIZE (0x2000UL) + +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Address EFM Sector Address + * @{ + */ +#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Base_Address EFM Otp Base Address + * @{ + */ +#define EFM_OTP_BASE1_ADDR (0x00000000UL) +#define EFM_OTP_BASE1_SIZE (0x2000UL) +#define EFM_OTP_BASE1_OFFSET (0UL) +#define EFM_OTP_BASE2_ADDR (0x03000000UL) +#define EFM_OTP_BASE2_SIZE (0x800UL) +#define EFM_OTP_BASE2_OFFSET (16UL) +#define EFM_OTP_BASE3_ADDR (0x03001000UL) +#define EFM_OTP_BASE3_SIZE (0x100UL) +#define EFM_OTP_BASE3_OFFSET (18UL) +#define EFM_OTP_BASE4_ADDR (0x03001400UL) +#define EFM_OTP_BASE4_SIZE (0x10UL) +#define EFM_OTP_BASE4_OFFSET (22UL) +#define EFM_OTP_BASE5_ADDR (0x03001600UL) +#define EFM_OTP_BASE5_SIZE (0x04UL) +#define EFM_OTP_BASE5_OFFSET (54UL) +#define EFM_OTP_LOCK_ADDR (0x03001800UL) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Address EFM Otp Address + * @{ + */ +#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) + +#define EFM_OTP_BLOCK15 (EFM_OTP_BASE1_ADDR + ((15UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) + +#define EFM_OTP_BLOCK16 (EFM_OTP_BASE2_ADDR + ((16UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK17 (EFM_OTP_BASE2_ADDR + ((17UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE)) + +#define EFM_OTP_BLOCK18 (EFM_OTP_BASE3_ADDR + ((18UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE)) +#define EFM_OTP_BLOCK19 (EFM_OTP_BASE3_ADDR + ((19UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE)) +#define EFM_OTP_BLOCK20 (EFM_OTP_BASE3_ADDR + ((20UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE)) +#define EFM_OTP_BLOCK21 (EFM_OTP_BASE3_ADDR + ((21UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE)) + +#define EFM_OTP_BLOCK22 (EFM_OTP_BASE4_ADDR + ((22UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK23 (EFM_OTP_BASE4_ADDR + ((23UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK24 (EFM_OTP_BASE4_ADDR + ((24UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK25 (EFM_OTP_BASE4_ADDR + ((25UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK26 (EFM_OTP_BASE4_ADDR + ((26UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK27 (EFM_OTP_BASE4_ADDR + ((27UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK28 (EFM_OTP_BASE4_ADDR + ((28UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK29 (EFM_OTP_BASE4_ADDR + ((29UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK30 (EFM_OTP_BASE4_ADDR + ((30UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK31 (EFM_OTP_BASE4_ADDR + ((31UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK32 (EFM_OTP_BASE4_ADDR + ((32UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK33 (EFM_OTP_BASE4_ADDR + ((33UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK34 (EFM_OTP_BASE4_ADDR + ((34UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK35 (EFM_OTP_BASE4_ADDR + ((35UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK36 (EFM_OTP_BASE4_ADDR + ((36UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK37 (EFM_OTP_BASE4_ADDR + ((37UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK38 (EFM_OTP_BASE4_ADDR + ((38UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK39 (EFM_OTP_BASE4_ADDR + ((39UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK40 (EFM_OTP_BASE4_ADDR + ((40UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK41 (EFM_OTP_BASE4_ADDR + ((41UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK42 (EFM_OTP_BASE4_ADDR + ((42UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK43 (EFM_OTP_BASE4_ADDR + ((43UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK44 (EFM_OTP_BASE4_ADDR + ((44UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK45 (EFM_OTP_BASE4_ADDR + ((45UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK46 (EFM_OTP_BASE4_ADDR + ((46UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK47 (EFM_OTP_BASE4_ADDR + ((47UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK48 (EFM_OTP_BASE4_ADDR + ((48UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK49 (EFM_OTP_BASE4_ADDR + ((49UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK50 (EFM_OTP_BASE4_ADDR + ((50UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK51 (EFM_OTP_BASE4_ADDR + ((51UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK52 (EFM_OTP_BASE4_ADDR + ((52UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) +#define EFM_OTP_BLOCK53 (EFM_OTP_BASE4_ADDR + ((53UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE)) + +#define EFM_OTP_BLOCK54 (EFM_OTP_BASE5_ADDR + ((54UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK55 (EFM_OTP_BASE5_ADDR + ((55UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK56 (EFM_OTP_BASE5_ADDR + ((56UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK57 (EFM_OTP_BASE5_ADDR + ((57UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK58 (EFM_OTP_BASE5_ADDR + ((58UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK59 (EFM_OTP_BASE5_ADDR + ((59UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK60 (EFM_OTP_BASE5_ADDR + ((60UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK61 (EFM_OTP_BASE5_ADDR + ((61UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK62 (EFM_OTP_BASE5_ADDR + ((62UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK63 (EFM_OTP_BASE5_ADDR + ((63UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK64 (EFM_OTP_BASE5_ADDR + ((64UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK65 (EFM_OTP_BASE5_ADDR + ((65UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK66 (EFM_OTP_BASE5_ADDR + ((66UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK67 (EFM_OTP_BASE5_ADDR + ((67UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK68 (EFM_OTP_BASE5_ADDR + ((68UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK69 (EFM_OTP_BASE5_ADDR + ((69UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK70 (EFM_OTP_BASE5_ADDR + ((70UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK71 (EFM_OTP_BASE5_ADDR + ((71UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK72 (EFM_OTP_BASE5_ADDR + ((72UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK73 (EFM_OTP_BASE5_ADDR + ((73UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK74 (EFM_OTP_BASE5_ADDR + ((74UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK75 (EFM_OTP_BASE5_ADDR + ((75UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK76 (EFM_OTP_BASE5_ADDR + ((76UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK77 (EFM_OTP_BASE5_ADDR + ((77UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK78 (EFM_OTP_BASE5_ADDR + ((78UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK79 (EFM_OTP_BASE5_ADDR + ((79UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK80 (EFM_OTP_BASE5_ADDR + ((80UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK81 (EFM_OTP_BASE5_ADDR + ((81UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK82 (EFM_OTP_BASE5_ADDR + ((82UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK83 (EFM_OTP_BASE5_ADDR + ((83UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK84 (EFM_OTP_BASE5_ADDR + ((84UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK85 (EFM_OTP_BASE5_ADDR + ((85UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK86 (EFM_OTP_BASE5_ADDR + ((86UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK87 (EFM_OTP_BASE5_ADDR + ((87UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK88 (EFM_OTP_BASE5_ADDR + ((88UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK89 (EFM_OTP_BASE5_ADDR + ((89UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK90 (EFM_OTP_BASE5_ADDR + ((90UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK91 (EFM_OTP_BASE5_ADDR + ((91UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK92 (EFM_OTP_BASE5_ADDR + ((92UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK93 (EFM_OTP_BASE5_ADDR + ((93UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK94 (EFM_OTP_BASE5_ADDR + ((94UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK95 (EFM_OTP_BASE5_ADDR + ((95UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK96 (EFM_OTP_BASE5_ADDR + ((96UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK97 (EFM_OTP_BASE5_ADDR + ((97UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK98 (EFM_OTP_BASE5_ADDR + ((98UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK99 (EFM_OTP_BASE5_ADDR + ((99UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK100 (EFM_OTP_BASE5_ADDR + ((100UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK101 (EFM_OTP_BASE5_ADDR + ((101UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK102 (EFM_OTP_BASE5_ADDR + ((102UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK103 (EFM_OTP_BASE5_ADDR + ((103UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK104 (EFM_OTP_BASE5_ADDR + ((104UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK105 (EFM_OTP_BASE5_ADDR + ((105UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK106 (EFM_OTP_BASE5_ADDR + ((106UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK107 (EFM_OTP_BASE5_ADDR + ((107UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK108 (EFM_OTP_BASE5_ADDR + ((108UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK109 (EFM_OTP_BASE5_ADDR + ((109UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK110 (EFM_OTP_BASE5_ADDR + ((110UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK111 (EFM_OTP_BASE5_ADDR + ((111UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK112 (EFM_OTP_BASE5_ADDR + ((112UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK113 (EFM_OTP_BASE5_ADDR + ((113UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK114 (EFM_OTP_BASE5_ADDR + ((114UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK115 (EFM_OTP_BASE5_ADDR + ((115UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK116 (EFM_OTP_BASE5_ADDR + ((116UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK117 (EFM_OTP_BASE5_ADDR + ((117UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK118 (EFM_OTP_BASE5_ADDR + ((118UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK119 (EFM_OTP_BASE5_ADDR + ((119UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK120 (EFM_OTP_BASE5_ADDR + ((120UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK121 (EFM_OTP_BASE5_ADDR + ((121UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK122 (EFM_OTP_BASE5_ADDR + ((122UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK123 (EFM_OTP_BASE5_ADDR + ((123UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK124 (EFM_OTP_BASE5_ADDR + ((124UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK125 (EFM_OTP_BASE5_ADDR + ((125UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK126 (EFM_OTP_BASE5_ADDR + ((126UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK127 (EFM_OTP_BASE5_ADDR + ((127UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK128 (EFM_OTP_BASE5_ADDR + ((128UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK129 (EFM_OTP_BASE5_ADDR + ((129UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK130 (EFM_OTP_BASE5_ADDR + ((130UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK131 (EFM_OTP_BASE5_ADDR + ((131UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK132 (EFM_OTP_BASE5_ADDR + ((132UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK133 (EFM_OTP_BASE5_ADDR + ((133UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK134 (EFM_OTP_BASE5_ADDR + ((134UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK135 (EFM_OTP_BASE5_ADDR + ((135UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK136 (EFM_OTP_BASE5_ADDR + ((136UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK137 (EFM_OTP_BASE5_ADDR + ((137UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK138 (EFM_OTP_BASE5_ADDR + ((138UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK139 (EFM_OTP_BASE5_ADDR + ((139UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK140 (EFM_OTP_BASE5_ADDR + ((140UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK141 (EFM_OTP_BASE5_ADDR + ((141UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK142 (EFM_OTP_BASE5_ADDR + ((142UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK143 (EFM_OTP_BASE5_ADDR + ((143UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK144 (EFM_OTP_BASE5_ADDR + ((144UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK145 (EFM_OTP_BASE5_ADDR + ((145UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK146 (EFM_OTP_BASE5_ADDR + ((146UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK147 (EFM_OTP_BASE5_ADDR + ((147UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK148 (EFM_OTP_BASE5_ADDR + ((148UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK149 (EFM_OTP_BASE5_ADDR + ((149UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK150 (EFM_OTP_BASE5_ADDR + ((150UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK151 (EFM_OTP_BASE5_ADDR + ((151UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK152 (EFM_OTP_BASE5_ADDR + ((152UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK153 (EFM_OTP_BASE5_ADDR + ((153UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK154 (EFM_OTP_BASE5_ADDR + ((154UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK155 (EFM_OTP_BASE5_ADDR + ((155UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK156 (EFM_OTP_BASE5_ADDR + ((156UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK157 (EFM_OTP_BASE5_ADDR + ((157UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK158 (EFM_OTP_BASE5_ADDR + ((158UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK159 (EFM_OTP_BASE5_ADDR + ((159UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK160 (EFM_OTP_BASE5_ADDR + ((160UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK161 (EFM_OTP_BASE5_ADDR + ((161UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK162 (EFM_OTP_BASE5_ADDR + ((162UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK163 (EFM_OTP_BASE5_ADDR + ((163UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK164 (EFM_OTP_BASE5_ADDR + ((164UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK165 (EFM_OTP_BASE5_ADDR + ((165UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK166 (EFM_OTP_BASE5_ADDR + ((166UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK167 (EFM_OTP_BASE5_ADDR + ((167UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK168 (EFM_OTP_BASE5_ADDR + ((168UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK169 (EFM_OTP_BASE5_ADDR + ((169UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK170 (EFM_OTP_BASE5_ADDR + ((170UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK171 (EFM_OTP_BASE5_ADDR + ((171UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK172 (EFM_OTP_BASE5_ADDR + ((172UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK173 (EFM_OTP_BASE5_ADDR + ((173UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK174 (EFM_OTP_BASE5_ADDR + ((174UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK175 (EFM_OTP_BASE5_ADDR + ((175UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK176 (EFM_OTP_BASE5_ADDR + ((176UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK177 (EFM_OTP_BASE5_ADDR + ((177UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK178 (EFM_OTP_BASE5_ADDR + ((178UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK179 (EFM_OTP_BASE5_ADDR + ((179UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK180 (EFM_OTP_BASE5_ADDR + ((180UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +#define EFM_OTP_BLOCK181 (EFM_OTP_BASE5_ADDR + ((181UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address + * @note x at range of 0~14 while HC32F460, HC32F451, HC32F452 + * x at range of 0~181 while HC32F4A0, HC32F472 + * @{ + */ +#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */ +/** + * @} + */ + +#define EFM_REMAP_REG_LOCK_KEY (0x0000UL) +#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL) + +/** + * @defgroup EFM_Remap_State EFM remap function state + * @{ + */ +#define EFM_REMAP_OFF (0UL) +#define EFM_REMAP_ON EFM_MMF_REMCR_EN +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Size EFM remap size definition + * @note refer to chip user manual for details size spec. + * @{ + */ +#define EFM_REMAP_4K (12UL) +#define EFM_REMAP_8K (13UL) +#define EFM_REMAP_16K (14UL) +#define EFM_REMAP_32K (15UL) +#define EFM_REMAP_64K (16UL) +#define EFM_REMAP_128K (17UL) +#define EFM_REMAP_256K (18UL) +#define EFM_REMAP_512K (19UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Index EFM remap index + * @{ + */ +#define EFM_REMAP_IDX0 (0U) +#define EFM_REMAP_IDX1 (1U) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_BaseAddr EFM remap base address + * @{ + */ +#define EFM_REMAP_BASE_ADDR0 (0x2000000UL) +#define EFM_REMAP_BASE_ADDR1 (0x2080000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Region EFM remap ROM/RAM region + * @{ + */ +#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR + +#define EFM_REMAP_RAM_START_ADDR (0x1FFE0000UL) +#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL) +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EFM_Global_Functions + * @{ + */ + +/** + * @brief EFM Protect Unlock. + * @param None + * @retval None + */ + +__STATIC_INLINE void EFM_REG_Unlock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM Protect Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REG_Lock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY); +} + +/** + * @brief EFM remap Unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Unlock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM remap Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Lock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY); +} + +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState); +void EFM_FWMC_Cmd(en_functional_state_t enNewState); +void EFM_SetBusStatus(uint32_t u32Status); +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState); +void EFM_ClearStatus(uint32_t u32Flag); +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle); +int32_t EFM_SetOperateMode(uint32_t u32Mode); +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen); +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_SectorErase(uint32_t u32Addr); +int32_t EFM_ChipErase(uint8_t u8Chip); + +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag); +en_flag_status_t EFM_GetStatus(uint32_t u32Flag); +void EFM_GetUID(stc_efm_unique_id_t *pstcUID); + +void EFM_DataCacheResetCmd(en_functional_state_t enNewState); +void EFM_PrefetchCmd(en_functional_state_t enNewState); +void EFM_DCacheCmd(en_functional_state_t enNewState); +void EFM_ICacheCmd(en_functional_state_t enNewState); + +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState); +int32_t EFM_SwapCmd(en_functional_state_t enNewState); +en_flag_status_t EFM_GetSwapStatus(void); +int32_t EFM_OTP_Lock(uint32_t u32Addr); + +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit); +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit); +void EFM_REMAP_DeInit(void); +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState); +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr); +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size); + +uint32_t EFM_GetCID(void); +void EFM_OTP_WP_Unlock(void); +void EFM_OTP_WP_Lock(void); +int32_t EFM_OTP_Enable(void); +void EFM_SectorProtectRegLock(uint32_t u32RegLock); +void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState); +void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h new file mode 100644 index 0000000000..0820edd9e4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h @@ -0,0 +1,509 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.h + * @brief This file contains all the functions prototypes of the EMB + * (Emergency Brake) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EMB_H__ +#define __HC32_LL_EMB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EMB + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Types EMB Global Types + * @{ + */ + +/** + * @brief EMB monitor OSC failure configuration + */ +typedef struct { + uint32_t u32OscState; /*!< Enable or disable EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Selection */ +} stc_emb_monitor_osc_t; + +/** + * @brief EMB monitor EMB port configuration + */ +typedef struct { + uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function + This parameter can be a value of EMB_Port_Selection */ + uint32_t u32PortLevel; /*!< EMB detect port level + This parameter can be a value of EMB_Detect_Port_Level */ + uint32_t u32PortFilterDiv; /*!< EMB port filter division + This parameter can be a value of EMB_Port_Filter_Clock_Division */ + uint32_t u32PortFilterState; /*!< EMB port filter division + This parameter can be a value of EMB_Port_Filter_Selection */ +} stc_emb_monitor_port_config_t; + +/** + * @brief EMB monitor TMR4 or TMR6 PWM configuration + */ +typedef struct { + uint32_t u32PwmState; /*!< Enable or disable EMB detect TMR4/6 PWM channel same phase function + This parameter can be a value of EMB_TMR4_PWM_Selection or EMB_TMR6_PWM_Selection */ + uint32_t u32PwmLevel; /*!< Detect TMR4/6 PWM channel polarity level + This parameter can be a value of EMB_Detect_TMR4_PWM_Level or EMB_Detect_TMR6_PWM_Level */ +} stc_emb_monitor_tmr_pwm_t; + +/** + * @brief EMB monitor port in configuration + */ +typedef struct { + stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort2; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort3; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort4; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ +} stc_emb_monitor_port_t; + +/** + * @brief EMB monitor CMP configuration + */ +typedef struct { + uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp4State; /*!< Enable or disable EMB detect CMP4 result function + This parameter can be a value of @ref EMB_CMP_Selection */ +} stc_emb_monitor_cmp_t; + +/** + * @brief EMB monitor TMR4 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr4_t; + +/** + * @brief EMB monitor TMR6 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_4; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_5; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_6; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_7; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_8; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr6_t; + +/** + * @brief EMB control TMR4 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr4_t structure */ +} stc_emb_tmr4_init_t; + +/** + * @brief EMB control TMR6 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr6_t structure */ +} stc_emb_tmr6_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Macros EMB Global Macros + * @{ + */ + +/** + * @defgroup EMB_CMP_Selection EMB CMP Selection + * @{ + */ +#define EMB_CMP1_DISABLE (0UL) +#define EMB_CMP2_DISABLE (0UL) +#define EMB_CMP3_DISABLE (0UL) +#define EMB_CMP4_DISABLE (0UL) + +#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN0) +#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN1) +#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN2) +#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN3) +/** + * @} + */ + +/** + * @defgroup EMB_OSC_Selection EMB OSC Selection + * @{ + */ +#define EMB_OSC_DISABLE (0UL) + +#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN) +/** + * @} + */ + +/** + * @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection + * @{ + */ +#define EMB_TMR4_PWM_W_DISABLE (0UL) +#define EMB_TMR4_PWM_V_DISABLE (0UL) +#define EMB_TMR4_PWM_U_DISABLE (0UL) + +#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN0) +#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN1) +#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV0) +#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV1) +#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection + * @{ + */ +#define EMB_TMR6_1_PWM_DISABLE (0UL) +#define EMB_TMR6_2_PWM_DISABLE (0UL) +#define EMB_TMR6_3_PWM_DISABLE (0UL) +#define EMB_TMR6_4_PWM_DISABLE (0UL) +#define EMB_TMR6_5_PWM_DISABLE (0UL) +#define EMB_TMR6_6_PWM_DISABLE (0UL) +#define EMB_TMR6_7_PWM_DISABLE (0UL) +#define EMB_TMR6_8_PWM_DISABLE (0UL) +#define EMB_TMR6_9_PWM_DISABLE (0UL) +#define EMB_TMR6_10_PWM_DISABLE (0UL) + +#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN0) +#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN1) +#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL1_PWMSEN2) +#define EMB_TMR6_4_PWM_ENABLE (EMB_CTL1_PWMSEN3) +#define EMB_TMR6_5_PWM_ENABLE (EMB_CTL1_PWMSEN4) +#define EMB_TMR6_6_PWM_ENABLE (EMB_CTL1_PWMSEN5) +#define EMB_TMR6_7_PWM_ENABLE (EMB_CTL1_PWMSEN6) +#define EMB_TMR6_8_PWM_ENABLE (EMB_CTL1_PWMSEN7) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_PWM_Level EMB TMR6 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_9_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_10_PWM_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV0) +#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV1) +#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_CTL2_PWMLV2) +#define EMB_DETECT_TMR6_4_PWM_BOTH_HIGH (EMB_CTL2_PWMLV3) +#define EMB_DETECT_TMR6_5_PWM_BOTH_HIGH (EMB_CTL2_PWMLV4) +#define EMB_DETECT_TMR6_6_PWM_BOTH_HIGH (EMB_CTL2_PWMLV5) +#define EMB_DETECT_TMR6_7_PWM_BOTH_HIGH (EMB_CTL2_PWMLV6) +#define EMB_DETECT_TMR6_8_PWM_BOTH_HIGH (EMB_CTL2_PWMLV7) +#define EMB_DETECT_TMR6_9_PWM_BOTH_HIGH (EMB_CTL2_PWMLV8) +#define EMB_DETECT_TMR6_10_PWM_BOTH_HIGH (EMB_CTL2_PWMLV9) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Selection EMB Port Selection + * @{ + */ +#define EMB_PORT1_DISABLE (0UL) +#define EMB_PORT2_DISABLE (0UL) +#define EMB_PORT3_DISABLE (0UL) +#define EMB_PORT4_DISABLE (0UL) +#define EMB_PORT5_DISABLE (0UL) +#define EMB_PORT6_DISABLE (0UL) + +#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1) +#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2) +#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3) +#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN4) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port_Level EMB Detect Port Level + * @{ + */ +#define EMB_PORT1_DETECT_LVL_HIGH (0UL) +#define EMB_PORT2_DETECT_LVL_HIGH (0UL) +#define EMB_PORT3_DETECT_LVL_HIGH (0UL) +#define EMB_PORT4_DETECT_LVL_HIGH (0UL) +#define EMB_PORT5_DETECT_LVL_HIGH (0UL) +#define EMB_PORT6_DETECT_LVL_HIGH (0UL) + +#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL1_INVSEL1) +#define EMB_PORT2_DETECT_LVL_LOW (EMB_CTL1_INVSEL2) +#define EMB_PORT3_DETECT_LVL_LOW (EMB_CTL1_INVSEL3) +#define EMB_PORT4_DETECT_LVL_LOW (EMB_CTL1_INVSEL4) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection + * @{ + */ +#define EMB_PORT1_FILTER_DISABLE (0UL) +#define EMB_PORT2_FILTER_DISABLE (0UL) +#define EMB_PORT3_FILTER_DISABLE (0UL) +#define EMB_PORT4_FILTER_DISABLE (0UL) +#define EMB_PORT5_FILTER_DISABLE (0UL) +#define EMB_PORT6_FILTER_DISABLE (0UL) + +#define EMB_PORT1_FILTER_ENABLE (EMB_CTL2_NFEN1) +#define EMB_PORT2_FILTER_ENABLE (EMB_CTL2_NFEN2) +#define EMB_PORT3_FILTER_ENABLE (EMB_CTL2_NFEN3) +#define EMB_PORT4_FILTER_ENABLE (EMB_CTL2_NFEN4) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division + * @{ + */ +#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL1_POS) + +#define EMB_PORT2_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL2_POS) + +#define EMB_PORT3_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL3_POS) + +#define EMB_PORT4_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL4_POS) +/** + * @} + */ + +/** + * @defgroup EMB_Flag_State EMB Flag State + * @{ + */ +#define EMB_FLAG_PWMS (EMB_STAT_PWMSF) +#define EMB_FLAG_CMP (EMB_STAT_CMPF) +#define EMB_FLAG_OSC (EMB_STAT_OSF) +#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1) +#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2) +#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3) +#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4) +#define EMB_STAT_PWMS (EMB_STAT_PWMST) +#define EMB_STAT_CMP (EMB_STAT_CMPST) +#define EMB_STAT_OSC (EMB_STAT_OSST) +#define EMB_STAT_PORT1 (EMB_STAT_PORTINST1) +#define EMB_STAT_PORT2 (EMB_STAT_PORTINST2) +#define EMB_STAT_PORT3 (EMB_STAT_PORTINST3) +#define EMB_STAT_PORT4 (EMB_STAT_PORTINST4) +#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_OSC | EMB_FLAG_PORT1 | \ + EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4 | EMB_STAT_PWMS | \ + EMB_STAT_CMP | EMB_STAT_OSC | EMB_STAT_PORT1 | EMB_STAT_PORT2 | \ + EMB_STAT_PORT3 | EMB_STAT_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Interrupt EMB Interrupt + * @{ + */ +#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN) +#define EMB_INT_CMP (EMB_INTEN_CMPINTEN) +#define EMB_INT_OSC (EMB_INTEN_OSINTEN) +#define EMB_INT_PORT1 (EMB_INTEN_PORTINTEN1) +#define EMB_INT_PORT2 (EMB_INTEN_PORTINTEN2) +#define EMB_INT_PORT3 (EMB_INTEN_PORTINTEN3) +#define EMB_INT_PORT4 (EMB_INTEN_PORTINTEN4) +#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_OSC | \ + EMB_INT_PORT1 | EMB_INT_PORT2 | EMB_INT_PORT3 | EMB_INT_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Release_TMR_PWM_Condition EMB Release TMR PWM Condition + * @{ + */ +#define EMB_RELEASE_PWM_COND_FLAG_ZERO (0UL) +#define EMB_RELEASE_PWM_COND_STAT_ZERO (1UL) +/** + * @} + */ + +/** + * @defgroup EMB_Monitor_Event EMB Monitor Event + * @{ + */ +#define EMB_EVT_PWMS (EMB_RLSSEL_PWMRSEL) +#define EMB_EVT_CMP (EMB_RLSSEL_CMPRSEL) +#define EMB_EVT_OSC (EMB_RLSSEL_OSRSEL) +#define EMB_EVT_PORT1 (EMB_RLSSEL_PORTINRSEL1) +#define EMB_EVT_PORT2 (EMB_RLSSEL_PORTINRSEL2) +#define EMB_EVT_PORT3 (EMB_RLSSEL_PORTINRSEL3) +#define EMB_EVT_PORT4 (EMB_RLSSEL_PORTINRSEL4) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EMB_Global_Functions + * @{ + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit); +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit); + +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit); +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit); + +void EMB_DeInit(CM_EMB_TypeDef *EMBx); +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState); +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState); + +void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond); + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_eth.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_eth.h new file mode 100644 index 0000000000..60109a39df --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_eth.h @@ -0,0 +1,2459 @@ +/** + ******************************************************************************* + * @file hc32_ll_eth.h + * @brief This file contains all the Macro Definitions of the ETH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ETH_H__ +#define __HC32_LL_ETH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ETH + * @{ + */ + +#if (LL_ETH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Types ETH Global Types + * @{ + */ + +/** + * @brief ETH Common Initialization Structure Definition + */ +typedef struct { + uint16_t u16AutoNego; /*!< Specifies the Auto Negotiation mode for the external PHY. + This parameter can be a value of @ref ETH_Auto_Negotiation */ + uint16_t u16PhyAddr; /*!< Specifies the Ethernet PHY address. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ + uint8_t au8MacAddr[6]; /*!< Specifies the MAC Address of used Hardware */ + uint32_t u32Interface; /*!< Specifies the media interface. + This parameter can be a value of @ref ETH_Interface */ + uint32_t u32Speed; /*!< Specifies the Ethernet speed. + This parameter can be a value of @ref ETH_Speed */ + uint32_t u32DuplexMode; /*!< Specifies the MAC duplex mode. + This parameter can be a value of @ref ETH_Duplex_Mode */ + uint32_t u32ChecksumMode; /*!< Specifies the checksum check by hardware or by software. + This parameter can be a value of @ref ETH_Checksum_Mode */ + uint32_t u32ReceiveMode; /*!< Specifies the Ethernet Rx mode. + This parameter can be a value of @ref ETH_Receive_Mode */ +} stc_eth_comm_init_t; + +/** + * @brief ETH MAC Initialization Structure Definition + */ +typedef struct { + uint32_t u32TxClockPolarity; /*!< Specifies the Tx clock polarity. + This parameter can be a value of @ref ETH_TX_CLK_POLARITY */ + uint32_t u32RxClockPolarity; /*!< Specifies the Rx/Ref clock polarity. + This parameter can be a value of @ref ETH_RX_CLK_POLARITY */ + uint32_t u32SrcAddrMode; /*!< Specifies the Source Address Insert or Replace Mode. + This parameter can be a value of @ref ETH_SRC_ADDR_Mode */ + uint32_t u32TypeFrameStripFCS; /*!< Specifies the validity of stripping FCS for type frame. + This parameter can be a value of @ref ETH_TypeFrame_Strip_FCS */ + uint32_t u32Watchdog; /*!< Specifies the validity of the Watchdog timer. + This parameter can be a value of @ref ETH_Watchdog */ + uint32_t u32Jabber; /*!< Specifies the validity of the Jabber timer. + This parameter can be a value of @ref ETH_Jabber */ + uint32_t u32InterframeGap; /*!< Specifies the minimum gap between frames during transmission. + This parameter can be a value of @ref ETH_Interframe_Gap */ + uint32_t u32CarrierSense; /*!< Specifies the validity of the Carrier Sense (Half-Duplex mode). + This parameter can be a value of @ref ETH_Carrier_Sense */ + uint32_t u32ReceiveOwn; /*!< Specifies the validity of the Receive Own (Half-Duplex mode). + This parameter can be a value of @ref ETH_Receive_Own */ + uint32_t u32ChecksumOffload; /*!< Specifies the validity of the IPv4 checksum Offload. + This parameter can be a value of @ref ETH_Checksum_Offload */ + uint32_t u32RetryTrans; /*!< Specifies the validity of the MAC attempt to retry Transmit (Half-Duplex mode). + This parameter can be a value of @ref ETH_Retry_Transmit */ + uint32_t u32AutoStripPadFCS; /*!< Specifies the validity of the Automatic Stripping Pad/FCS of MAC. + This parameter can be a value of @ref ETH_Auto_Strip_Pad_FCS */ + uint32_t u32BackOffLimit; /*!< Specifies the BackOff limit value (Half-Duplex mode). + This parameter can be a value of @ref ETH_Back_Off_Limit */ + uint32_t u32DeferralCheck; /*!< Specifies the validity of the deferral check (Half-Duplex mode). + This parameter can be a value of @ref ETH_Deferral_Check */ + uint16_t u16PauseTime; /*!< Specifies the Pause Time in the transmit control frame. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + uint32_t u32ZeroQuantaPause; /*!< Specifies the validity of the automatic generation Zero-Quanta Pause Control frame. + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + uint32_t u32PauseLowThreshold; /*!< Specifies the PAUSE Frame threshold. + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + uint32_t u32UnicastPauseFrame; /*!< Specifies the validity of the detection unicast Pause frame. + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + uint32_t u32ReceiveFlowControl; /*!< Specifies the validity of the decoding function that receive Pause frame. + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + uint32_t u32TransFlowControl; /*!< Specifies the validity of the MAC transmit Pause frame (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode). + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + uint32_t u32ReceiveAll; /*!< Specifies the validity of the all frames reception by the MAC (No filtering). + This parameter can be a value of @ref ETH_Receive_All */ + uint32_t u32DropNotTcpUdp; /*!< Specifies the validity of Dropping all IP datagram without TCP/UDP field. + This parameter can be a value of @ref ETH_Drop_Not_TcpUdp */ + uint32_t u32VlanTagFilter; /*!< Specifies the validity of the VLAN Tag Filter. + This parameter can be a value of @ref ETH_VLAN_Tag_Filter */ + uint32_t u32SrcAddrFilter; /*!< Specifies the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + uint32_t u32PassControlFrame; /*!< Specifies the forwarding mode of the control frame. + This parameter can be a value of @ref ETH_Pass_Control_Frame */ + uint32_t u32BroadcastFrame; /*!< Specifies the validity of the reception Broadcast Frame. + This parameter can be a value of @ref ETH_Reception_Broadcast_Frame */ + uint32_t u32DestAddrFilter; /*!< Specifies the destination filter mode for both unicast and multicast frame. + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + uint32_t u32MulticastFrameFilter; /*!< Specifies the Multicast Frame filter mode. + This parameter can be a value of @ref ETH_Multicast_Frame_Filter */ + uint32_t u32UnicastFrameFilter; /*!< Specifies the Unicast Frame filter mode. + This parameter can be a value of @ref ETH_Unicast_Frame_Filter */ + uint32_t u32PromiscuousMode; /*!< Specifies the validity of the Promiscuous Mode. + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + uint32_t u32HashTableHigh; /*!< Specifies the higher 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t u32HashTableLow; /*!< Specifies the lower 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t u32TxVlanMode; /*!< Specifies the VLAN insert mode in Transmit frame. + This parameter can be a value of @ref ETH_Tx_VLAN_Insert_Mode */ + uint16_t u16TxVlanTag; /*!< Specifies the VLAN tag value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + uint32_t u32RxVlanFilter; /*!< Specifies the VLAN filter mode in Receive frame. + This parameter can be a value of @ref ETH_Rx_VLAN_Filter */ + uint32_t u32RxVlanCompare; /*!< Specifies the bits for compare VLAN tag. + This parameter can be a value of @ref ETH_Rx_VLAN_Compare */ + uint16_t u16RxVlanTag; /*!< Specifies the VLAN tag value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + uint16_t u16RxVlanHashTable; /*!< Specifies the lower 16 bits of VLAN Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ +} stc_eth_mac_init_t; + +/** + * @brief ETH DMA Initialization Structure Definition + */ +typedef struct { + uint32_t u32BurstMode; /*!< Specifies the AHB Master interface burst transmission Mode. + This parameter can be a value of @ref ETH_Burst_Mode */ + uint32_t u32AddrAlign; /*!< Specifies the validity of the Address Align. + This parameter can be a value of @ref ETH_Address_Align */ + uint32_t u32RxBurstLen; /*!< Specifies the maximum number of beats to be transferred in one Rx DMA transaction. + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + uint32_t u32TxBurstLen; /*!< Specifies the maximum number of beats to be transferred in one Tx DMA transaction. + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + uint32_t u32EnhanceDesc; /*!< Specifies the validity of the enhance descriptor format. + This parameter can be a value of @ref ETH_DMA_Enhance_Descriptor */ + uint32_t u32DescSkipLen; /*!< Specifies the number of word to skip between two unchain descriptors (Ring mode) + This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ + uint32_t u32Arbitration; /*!< Specifies the DMA Tx/Rx arbitration. + This parameter can be a value of @ref ETH_DMA_Arbitration */ + uint32_t u32DropChecksumErrorFrame; /*!< Specifies the validity of Dropping TCP/IP Checksum Error Frame. + This parameter can be a value of @ref ETH_Drop_TCPIP_Checksum_Error_Frame */ + uint32_t u32ReceiveStoreForward; /*!< Specifies the validity of the Receive store and forward mode. + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + uint32_t u32FlushReceiveFrame; /*!< Specifies the validity of the flushing receive frame. + This parameter can be a value of @ref ETH_Flush_Receive_Frame */ + uint32_t u32TransStoreForward; /*!< Specifies the validity of the Transmit store and forward mode. + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + uint32_t u32TransThreshold; /*!< Specifies the Transmit Threshold. + This parameter can be a value of @ref ETH_Transmit_Threshold */ + uint32_t u32ForwardErrorFrame; /*!< Specifies the validity of the forward erroneous frame. + This parameter can be a value of @ref ETH_Forward_Error_Frame */ + uint32_t u32ForwardUndersizeFrame; /*!< Specifies the validity of the Rx FIFO to forward Un dersize frame. + This parameter can be a value of @ref ETH_Forward_Undersize_Good_Frame */ + uint32_t u32DropJumboFrame; /*!< Specifies the validity of Dropping jumbo Frame. + This parameter can be a value of @ref ETH_Drop_Jumbo_Frame */ + uint32_t u32ReceiveThreshold; /*!< Specifies the threshold level of the Receive FIFO. + This parameter can be a value of @ref ETH_Receive_Threshold */ + uint32_t u32SecFrameOperate; /*!< Specifies the validity of the Operate on second frame mode. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ +} stc_eth_dma_init_t; + +/** + * @brief ETH MMC Initialization Structure Definition + */ +typedef struct { + uint32_t u32PresetMode; /*!< Specifies the MMC Counter preset mode. + This parameter can be a value of @ref ETH_MMC_Counter_Preset_Mode */ + uint32_t u32ReadReset; /*!< Specifies the validity of the MMC Reset on read. + This parameter can be a value of @ref ETH_MMC_Read_Reset */ + uint32_t u32Reload; /*!< Specifies the validity of the MMC Counter reload. + This parameter can be a value of @ref ETH_MMC_Counter_Reload */ +} stc_eth_mmc_init_t; + +/** + * @brief ETH PTP Initialization Structure Definition + */ +typedef struct { + uint32_t u32DestAddrFilter; /*!< Specifies the validity of the Destination address filter for the PTP frame. + This parameter can be a value of @ref ETH_PTP_Frame_Dest_Addr_Filter */ + uint32_t u32SnapDatagramType; /*!< Specifies the PTP snapshot datagram type. + This parameter can be a value of @ref ETH_PTP_Snapshot_Datagram_Type */ + uint32_t u32SnapFrameType; /*!< Specifies the PTP snapshot frame type. + This parameter can be any combination of @ref ETH_PTP_Snapshot_Frame_Type */ + uint32_t u32DatagramVersion; /*!< Specifies the PTP datagram version. + This parameter can be a value of @ref ETH_PTP_Datagram_Version */ + uint32_t u32SubsecScale; /*!< Specifies the PTP Time Stamp subsecond scale. + This parameter can be a value of @ref ETH_PTP_Subsecond_Scale */ + uint32_t u32CalibMode; /*!< Specifies the PTP Time Stamp calibration mode. + This parameter can be a value of @ref ETH_PTP_Calibration_Mode */ + uint32_t u32BasicAddend; /*!< Specifies the PTP Time Stamp Basic addend. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint8_t u8SubsecAddend; /*!< Specifies the PTP Time Stamp Subsecond addend. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ + uint32_t u32SecInitValue; /*!< Specifies the PTP Time Stamp Second Initial value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t u32SubsecInitValue; /*!< Specifies the PTP Time Stamp Subsecond Initial value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0x7FFFFFFF */ +} stc_eth_ptp_init_t; + +/** + * @brief ETH PPS Configuration Structure Definition + */ +typedef struct { + uint32_t u32TriggerFunc; /*!< Specifies the arrival time trigger the function. + This parameter can be a value of @ref ETH_PPS_Trigger_Function */ + uint32_t u32OutputMode; /*!< Specifies the PPS output mode. + This parameter can be a value of @ref ETH_PPS_Output_Mode */ + uint32_t u32OutputFreq; /*!< Specifies the PPS outout frequency. + This parameter can be any combination of @ref ETH_PPS_Output_Frequency */ + uint32_t u32SecValue; /*!< Specifies the PPS Target Time for Second. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t u32SubsecValue; /*!< Specifies the PPS Target Time for Subsecond. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0x7FFFFFFF */ +} stc_eth_pps_config_t; + +/** + * @brief ETH DMA Descriptor Structure Definition + */ +typedef struct { + __IO uint32_t u32ControlStatus; /*!< Control and Status */ + uint32_t u32ControlBufSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t u32Buf1Addr; /*!< Buffer1 address pointer */ + uint32_t u32Buf2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + /*!< Enhance DMA Descriptors */ + __IO uint32_t u32ExtendStatus; /*!< Extend status */ + uint32_t Reserved; /*!< Reserved */ + uint32_t u32TimestampLow; /*!< Time Stamp Low value for transmit and receive */ + uint32_t u32TimestampHigh; /*!< Time Stamp High value for transmit and receive */ +} stc_eth_dma_desc_t; + +/** + * @brief ETH DMA Received Frame Structure Definition + */ +typedef struct { + stc_eth_dma_desc_t *pstcFSDesc; /*!< First Segment Rx Desc */ + stc_eth_dma_desc_t *pstcLSDesc; /*!< Last Segment Rx Desc */ + uint32_t u32SegCount; /*!< Segment count */ + uint32_t u32Len; /*!< Frame length */ + uint32_t u32Buf; /*!< Frame buffer */ +} stc_eth_dma_rx_frame_t; + +/** + * @brief ETH Initialization Structure Definition + */ +typedef struct { + stc_eth_mac_init_t stcMacInit; /*!< Ethernet MAC Initialization */ + stc_eth_dma_init_t stcDmaInit; /*!< Ethernet DMA Initialization */ +} stc_eth_init_t; + +/** + * @brief ETH Handle Structure Definition + */ +typedef struct { + stc_eth_comm_init_t stcCommInit; /*!< ETH Common Initialization */ + stc_eth_dma_desc_t *stcRxDesc; /*!< Rx descriptor to Get */ + stc_eth_dma_desc_t *stcTxDesc; /*!< Tx descriptor to Set */ + stc_eth_dma_rx_frame_t stcRxFrame; /*!< last Rx frame */ +} stc_eth_handle_t; + +/** + * @brief ETH MAC Address Configuration Structure Definition + */ +typedef struct { + uint32_t u32MacAddrFilter; /*!< Specifies the MAC Address filter mode. + This parameter can be a value of @ref ETH_MAC_Address_Filter */ + uint32_t u32MacAddrMask; /*!< Specifies the MAC Address filter Mask. + This parameter can be a value of @ref ETH_MAC_Address_Filter_Mask */ + uint8_t au8MacAddr[6]; /*!< Specifies the MAC Address of used Hardware */ +} stc_eth_mac_addr_config_t; + +/** + * @brief ETH L3L4 Filter Configuration Structure Definition + */ +typedef struct { + uint32_t u32DestPortFilter; /*!< Specifies the L4 Destination port filter mode. + This parameter can be a value of @ref ETH_L4_Dest_Port_Filter */ + uint32_t u32SrcPortFilter; /*!< Specifies the L4 Source port filter mode. + This parameter can be a value of @ref ETH_L4_Source_Port_Filter */ + uint32_t u32PortFilterProtocol; /*!< Specifies the L4 protocol for port filter operation. + This parameter can be a value of @ref ETH_L4_Port_Filter_Protocol */ + uint16_t u16DestProtFilterValue; /*!< Specifies the L4 Destination port filter value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + uint16_t u16SrcProtFilterValue; /*!< Specifies the L4 Source port filter value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + uint32_t u32Ip4DestAddrFilterMask; /*!< Specifies the L3 Destination Address filter mask in IPv4. + This parameter can be a value of @ref ETH_L3_Dest_Addr_Filter_Mask */ + uint32_t u32Ip4SrcAddrFilterMask; /*!< Specifies the L3 Source Address filter Mask in IPv4. + This parameter can be a value of @ref ETH_L3_Source_Addr_Filter_Mask */ + uint32_t u32Ip6AddrFilterMask; /*!< Specifies the L3 Destination/Source Address filter Mask in IPv6. + This parameter can be a value of @ref ETH_L3_Dest_Source_Addr_Filter_Mask */ + uint32_t u32DestAddrFilter; /*!< Specifies the L3 Destination Address filter mode. + This parameter can be a value of @ref ETH_L3_Dest_Addr_Filter */ + uint32_t u32SrcAddrFilter; /*!< Specifies the L3 Source Address filter mode. + This parameter can be a value of @ref ETH_L3_Source_Addr_Filter */ + uint32_t u32AddrFilterProtocol; /*!< Specifies the L3 protocol for address filter operation. + This parameter can be a value of @ref ETH_L3_Addr_Filter_Protocol */ + uint32_t u32Ip4DestAddrFilterValue; /*!< Specifies the L3 Destination Address filter value in IPv4. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t u32Ip4SrcAddrFilterValue; /*!< Specifies the L3 Source Address filter value in IPv4. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + uint32_t au32Ip6AddrFilterValue[4]; /*!< Specifies the L3 Destination/Source Address filter value in IPv6. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ +} stc_eth_l3l4_filter_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Macros ETH Global Macros + * @{ + */ + +/** + * @defgroup ETH_Buffer_Define ETH Buffer Define + * @{ + */ +#define ETH_MAX_PACKET_SIZE (1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_PAYLOAD + ETH_CRC */ +#define ETH_HEADER (14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC (4U) /*!< Ethernet CRC */ +#define ETH_EXTRA (2U) /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG (4U) /*!< Optional 802.1Q VLAN Tag */ +#define ETH_MIN_PAYLOAD (46U) /*!< Ethernet minimum payload size */ +#define ETH_MAX_PAYLOAD (1500U) /*!< Ethernet maximum payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD (9000U) /*!< Jumbo frame payload size */ + +/* In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE and the total count of the + driver transmit buffers ETH_TX_BUF_NUM. + The configured value for ETH_TX_BUF_SIZE and ETH_TX_BUF_NUM are only provided as example, they can be reconfigured + in the application layer to fit the application needs */ + +/* Configure the transmit buffer size for each Ethernet driver */ +#ifndef ETH_TX_BUF_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* Configure the number of Ethernet driver transmit buffers (in a chained linked list)*/ +#ifndef ETH_TX_BUF_NUM +#define ETH_TX_BUF_NUM (4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + +/* In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE and the total count of the + driver receive buffers ETH_RX_BUF_NUM. + The configured value for ETH_RX_BUF_SIZE and ETH_RX_BUF_NUM are only provided as example, they can be reconfigured + in the application layer to fit the application needs */ + +/* Configure the receive buffer size for each Ethernet driver */ +#ifndef ETH_RX_BUF_SIZE +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* Configure the number of Ethernet drive receive buffers (in a chained linked list)*/ +#ifndef ETH_RX_BUF_NUM +#define ETH_RX_BUF_NUM (4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +/** + * @} + */ + +/** + * @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/* + Normal DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | TTSE(25) | CTRL[24:18] | TTSS(17) | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | CTRL[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + ----------------------------------------------------------------------------------------------- + */ +/** + * @brief Bit definition of TDES0 register + */ +#define ETH_DMA_TXDESC_OWN (0x80000000UL) /*!< OWN bit */ +#define ETH_DMA_TXDESC_IOC (0x40000000UL) /*!< Interrupt on Completion */ +#define ETH_DMA_TXDESC_TLS (0x20000000UL) /*!< Transmit Last Segment */ +#define ETH_DMA_TXDESC_TFS (0x10000000UL) /*!< Transmit First Segment */ +#define ETH_DMA_TXDESC_DCRC (0x08000000UL) /*!< Disable CRC */ +#define ETH_DMA_TXDESC_DPAD (0x04000000UL) /*!< Disable Padding */ +#define ETH_DMA_TXDESC_TTSE (0x02000000UL) /*!< Transmit Time Stamp Enable */ +#define ETH_DMA_TXDESC_CRCR (0x01000000UL) /*!< CRC Replace Control */ +#define ETH_DMA_TXDESC_CIC (0x00C00000UL) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMA_TXDESC_CIC_BYPASS (0x00000000UL) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMA_TXDESC_CIC_IPV4_HEADER (0x00400000UL) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMA_TXDESC_CIC_TCPUDPICMP_SEGMENT (0x00800000UL) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMA_TXDESC_CIC_TCPUDPICMP_FULL (0x00C00000UL) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMA_TXDESC_TER (0x00200000UL) /*!< Transmit End of Ring */ +#define ETH_DMA_TXDESC_TSAC (0x00100000UL) /*!< Second Address Chained */ +#define ETH_DMA_TXDESC_VLANC (0x000C0000UL) /*!< VLAN Insertion Control: 4 cases */ +#define ETH_DMA_TXDESC_VLANC_BYPASS (0x00000000UL) /*!< Do Nothing: VLAN Insertion is bypassed */ +#define ETH_DMA_TXDESC_VLANC_REMOVE_TAG (0x00040000UL) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_DMA_TXDESC_VLANC_INSERT_TAG (0x00080000UL) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_DMA_TXDESC_VLANC_REPLACE_TAG (0x000C0000UL) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +#define ETH_DMA_TXDESC_TTSS (0x00020000UL) /*!< Tx Time Stamp Status */ +#define ETH_DMA_TXDESC_IHE (0x00010000UL) /*!< IP Header Error */ +#define ETH_DMA_TXDESC_ETSUM (0x00008000UL) /*!< Tx Error summary: OR of the following bits: IHE || JTE || FFF || TPCE || LOCE || NCE || TLCE || ECE || EDE || UDE */ +#define ETH_DMA_TXDESC_JTE (0x00004000UL) /*!< Jabber Timeout Error */ +#define ETH_DMA_TXDESC_FFF (0x00002000UL) /*!< Frame Flushed */ +#define ETH_DMA_TXDESC_TPCE (0x00001000UL) /*!< Payload Checksum Error */ +#define ETH_DMA_TXDESC_LOCE (0x00000800UL) /*!< Loss Carrier Error */ +#define ETH_DMA_TXDESC_NCE (0x00000400UL) /*!< No Carrier Error */ +#define ETH_DMA_TXDESC_TLCE (0x00000200UL) /*!< Late Collision Error */ +#define ETH_DMA_TXDESC_ECE (0x00000100UL) /*!< Excessive Collision Error */ +#define ETH_DMA_TXDESC_VLF (0x00000080UL) /*!< VLAN Frame */ +#define ETH_DMA_TXDESC_COC (0x00000078UL) /*!< Collision Count */ +#define ETH_DMA_TXDESC_EDE (0x00000004UL) /*!< Excessive Deferral Error */ +#define ETH_DMA_TXDESC_UDE (0x00000002UL) /*!< Underflow Error */ +#define ETH_DMA_TXDESC_DEE (0x00000001UL) /*!< Deferred Error */ +#define ETH_DMA_TXDESC_STATUS_ALL (ETH_DMA_TXDESC_OWN | ETH_DMA_TXDESC_IOC | ETH_DMA_TXDESC_TLS | \ + ETH_DMA_TXDESC_DPAD | ETH_DMA_TXDESC_DCRC | ETH_DMA_TXDESC_TFS | \ + ETH_DMA_TXDESC_TTSE | ETH_DMA_TXDESC_CRCR | ETH_DMA_TXDESC_TER | \ + ETH_DMA_TXDESC_TSAC | ETH_DMA_TXDESC_TTSS | ETH_DMA_TXDESC_IHE | \ + ETH_DMA_TXDESC_ETSUM |ETH_DMA_TXDESC_JTE | ETH_DMA_TXDESC_FFF | \ + ETH_DMA_TXDESC_TPCE | ETH_DMA_TXDESC_LOCE | ETH_DMA_TXDESC_NCE | \ + ETH_DMA_TXDESC_TLCE | ETH_DMA_TXDESC_ECE | ETH_DMA_TXDESC_VLF | \ + ETH_DMA_TXDESC_EDE | ETH_DMA_TXDESC_UDE | ETH_DMA_TXDESC_DEE) + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMA_TXDESC_SAIRC (0xE0000000UL) /*!< Source Address Insertion or Replace Control: 5 cases */ +#define ETH_DMA_TXDESC_SAIRC_BYPASS (0x00000000UL) /*!< Do Nothing: Source Address Insertion or Replace Control is bypassed */ +#define ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR0 (0x20000000UL) /*!< Insert address value in MAC address register 0 into transmit frame as source address */ +#define ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR0 (0x40000000UL) /*!< Replace source address in transmit frame with address value in MAC address register 0 */ +#define ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR1 (0xA0000000UL) /*!< Insert address value in MAC address register 1 into transmit frame as source address */ +#define ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR1 (0xC0000000UL) /*!< Replace source address in transmit frame with address value in MAC address register 1 */ +#define ETH_DMA_TXDESC_TBS2 (0x1FFF0000UL) /*!< Transmit Buffer2 Size */ +#define ETH_DMA_TXDESC_TBS1 (0x00001FFFUL) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMA_TXDESC_TBAP1 (0xFFFFFFFFUL) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMA_TXDESC_TBAP2 (0xFFFFFFFFUL) /*!< Buffer2 Address Pointer */ + +/* + Enhance DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES4 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + TDES5 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------- + */ +/** + * @brief Bit definition of TDES6 register + */ +#define ETH_DMA_TXDESC_TTSL (0xFFFFFFFFUL) /*!< Transmit Time Stamp Low */ + +/** + * @brief Bit definition of TDES7 register + */ +#define ETH_DMA_TXDESC_TTSH (0xFFFFFFFFUL) /*!< Transmit Time Stamp High */ + +/** + * @} + */ + +/** + * @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/* + Normal DMA Rx Descriptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ +/** + * @brief Bit definition of RDES0 register + */ +#define ETH_DMA_RXDESC_OWN (0x80000000UL) /*!< OWN bit */ +#define ETH_DMA_RXDESC_DAF (0x40000000UL) /*!< Destination Address Filter Fail for the received frame */ +#define ETH_DMA_RXDESC_FRAL (0x3FFF0000UL) /*!< Receive frame length */ +#define ETH_DMA_RXDESC_ERSUM (0x00008000UL) /*!< Rx Error summary: OR of the following bits: DPE || OVE || IPE_TSPA_GF || RLCE || WTE || REE || CRE in RDES0, or IPPE || IPHE in RDES4 */ +#define ETH_DMA_RXDESC_DPE (0x00004000UL) /*!< Descriptor Error: no more descriptors for receive frame */ +#define ETH_DMA_RXDESC_SAF (0x00002000UL) /*!< Source address Filter Fail for the received frame */ +#define ETH_DMA_RXDESC_LEE (0x00001000UL) /*!< Length Error: Frame size not matching with length field */ +#define ETH_DMA_RXDESC_OVE (0x00000800UL) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMA_RXDESC_VLAT (0x00000400UL) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMA_RXDESC_RFS (0x00000200UL) /*!< First descriptor */ +#define ETH_DMA_RXDESC_RLS (0x00000100UL) /*!< Last descriptor */ +#define ETH_DMA_RXDESC_IPE_TSPA_GF (0x00000080UL) /*!< COE Error or Time stamp valid or jumbo frame */ +#define ETH_DMA_RXDESC_RLCE (0x00000040UL) /*!< Late collision Error */ +#define ETH_DMA_RXDESC_FRAT (0x00000020UL) /*!< Frame type: Ethernet or PTP */ +#define ETH_DMA_RXDESC_WTE (0x00000010UL) /*!< Receive Watchdog Timeout */ +#define ETH_DMA_RXDESC_REE (0x00000008UL) /*!< Receive error: error reported by PHY RX_ER */ +#define ETH_DMA_RXDESC_DBE (0x00000004UL) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMA_RXDESC_CRE (0x00000002UL) /*!< CRC error */ +#define ETH_DMA_RXDESC_DAS_ESA (0x00000001UL) /*!< MAC Address Filter/Status bit extension */ +#define ETH_DMA_RXDESC_STATUS_ALL (ETH_DMA_RXDESC_OWN | ETH_DMA_RXDESC_DAF | ETH_DMA_RXDESC_ERSUM | \ + ETH_DMA_RXDESC_DPE | ETH_DMA_RXDESC_CRE | ETH_DMA_RXDESC_LEE | \ + ETH_DMA_RXDESC_OVE | ETH_DMA_RXDESC_VLAT | ETH_DMA_RXDESC_RFS | \ + ETH_DMA_RXDESC_RLS | ETH_DMA_RXDESC_SAF | ETH_DMA_RXDESC_RLCE | \ + ETH_DMA_RXDESC_WTE | ETH_DMA_RXDESC_FRAT | ETH_DMA_RXDESC_REE | \ + ETH_DMA_RXDESC_DBE | ETH_DMA_RXDESC_DAS_ESA | \ + ETH_DMA_RXDESC_IPE_TSPA_GF) + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMA_RXDESC_DIC (0x80000000UL) /*!< Disable Interrupt on Completion */ +#define ETH_DMA_RXDESC_RBS2 (0x1FFF0000UL) /*!< Receive Buffer2 Size */ +#define ETH_DMA_RXDESC_RER (0x00008000UL) /*!< Receive End of Ring */ +#define ETH_DMA_RXDESC_RSAC (0x00004000UL) /*!< Second Address Chained */ +#define ETH_DMA_RXDESC_RBS1 (0x00001FFFUL) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMA_RXDESC_RBAP1 (0xFFFFFFFFUL) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMA_RXDESC_RBAP2 (0xFFFFFFFFUL) /*!< Buffer2 Address Pointer */ + +/* + Enhance DMA Rx Descriptor + ----------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:26] | Extend Status [25:24] | Reserved[23:15] | Extend Status [14:0] | + ----------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------- +*/ +/** + * @brief Bit definition of RDES4 register + */ +#define ETH_DMA_RXDESC_L4FMS (0x02000000UL) /*!< L4 Port Filter Status */ +#define ETH_DMA_RXDESC_L3FMS (0x01000000UL) /*!< L3 Address Filter Status */ +#define ETH_DMA_RXDESC_TSPD (0x00004000UL) /*!< Discard Time Stamp */ +#define ETH_DMA_RXDESC_PTPV (0x00002000UL) /*!< PTP Version */ +#define ETH_DMA_RXDESC_PTPFT (0x00001000UL) /*!< PTP Frame Type */ +#define ETH_DMA_RXDESC_MTP (0x00000F00UL) /*!< PTP Datagram Type */ +#define ETH_DMA_RXDESC_MTP_NONE (0x00000000UL) /*!< No PTP messages */ +#define ETH_DMA_RXDESC_MTP_SYNC (0x00000100UL) /*!< SYNC message (all clock types) */ +#define ETH_DMA_RXDESC_MTP_FOLLOW_UP (0x00000200UL) /*!< Follow_Up message (all clock types) */ +#define ETH_DMA_RXDESC_MTP_DELAY_REQ (0x00000300UL) /*!< Delay_Req message (all clock types) */ +#define ETH_DMA_RXDESC_MTP_DELAY_RESP (0x00000400UL) /*!< Delay_Resp message (all clock types) */ +#define ETH_DMA_RXDESC_MTP_PDELAY_REQ (0x00000500UL) /*!< Pdelay_Req message (peer-to-peer transparent clock) */ +#define ETH_DMA_RXDESC_MTP_PDELAY_RESP (0x00000600UL) /*!< Pdelay_Resp message (peer-to-peer transparent clock) */ +#define ETH_DMA_RXDESC_MTP_PDELAY_RESP_FOLLOW_UP (0x00000700UL) /*!< Pdelay_Resp_Follow_Up message (peer-to-peer transparent clock) */ +#define ETH_DMA_RXDESC_MTP_ANNOUNCE (0x00000800UL) /*!< Announce message (Ordinary or Boundary clock) */ +#define ETH_DMA_RXDESC_MTP_MANAGEMENT (0x00000900UL) /*!< Management message (Ordinary or Boundary clock) */ +#define ETH_DMA_RXDESC_MTP_SIGNALING (0x00000A00UL) /*!< Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMA_RXDESC_MTP_DEFAULT (0x00000F00UL) /*!< Default Datagram Type */ +#define ETH_DMA_RXDESC_IPV6DR (0x00000080UL) /*!< IPv6 Packet Received */ +#define ETH_DMA_RXDESC_IPV4DR (0x00000040UL) /*!< IPv4 Packet Received */ +#define ETH_DMA_RXDESC_IPCB (0x00000020UL) /*!< COE engine Bypassed */ +#define ETH_DMA_RXDESC_IPPE (0x00000010UL) /*!< IP Payload Error */ +#define ETH_DMA_RXDESC_IPHE (0x00000008UL) /*!< IP Header Error */ +#define ETH_DMA_RXDESC_IPPT (0x00000007UL) /*!< IP Payload Type: 4 cases */ +#define ETH_DMA_RXDESC_IPPT_UNKNOWN (0x00000000UL) /*!< Unknown */ +#define ETH_DMA_RXDESC_IPPT_UDP (0x00000001UL) /*!< UDP */ +#define ETH_DMA_RXDESC_IPPT_TCP (0x00000002UL) /*!< TCP */ +#define ETH_DMA_RXDESC_IPPT_ICMP (0x00000003UL) /*!< ICMP */ +#define ETH_DMA_RXDESC_EXTEND_STATUS_ALL (ETH_DMA_RXDESC_L4FMS | ETH_DMA_RXDESC_L3FMS | \ + ETH_DMA_RXDESC_TSPD | ETH_DMA_RXDESC_PTPV | \ + ETH_DMA_RXDESC_PTPFT | ETH_DMA_RXDESC_IPV6DR | \ + ETH_DMA_RXDESC_IPV4DR | ETH_DMA_RXDESC_IPCB | \ + ETH_DMA_RXDESC_IPPE | ETH_DMA_RXDESC_IPHE) + +/** + * @brief Bit definition of RDES6 register + */ +#define ETH_DMA_RXDESC_RTSL (0xFFFFFFFFUL) /*!< Receive Time Stamp Low */ + +/** + * @brief Bit definition of RDES7 register + */ +#define ETH_DMA_RXDESC_RTSH (0xFFFFFFFFUL) /*!< Receive Time Stamp High */ + +/** + * @} + */ + +/** + * @defgroup ETH_Auto_Negotiation ETH Auto Negotiation + * @{ + */ +#define ETH_AUTO_NEGO_DISABLE (0x0000U) +#define ETH_AUTO_NEGO_ENABLE (0x0001U) +/** + * @} + */ + +/** + * @defgroup ETH_Interface ETH Interface + * @{ + */ +#define ETH_MAC_IF_MII (0UL) +#define ETH_MAC_IF_RMII (ETH_MAC_IFCONFR_IFSEL) +/** + * @} + */ + +/** + * @defgroup ETH_Speed ETH Speed + * @{ + */ +#define ETH_MAC_SPEED_10M (0UL) +#define ETH_MAC_SPEED_100M (ETH_MAC_CONFIGR_FES) +/** + * @} + */ + +/** + * @defgroup ETH_Duplex_Mode ETH Duplex Mode + * @{ + */ +#define ETH_MAC_DUPLEX_MD_HALF (0UL) +#define ETH_MAC_DUPLEX_MD_FULL (ETH_MAC_CONFIGR_DM) +/** + * @} + */ + +/** + * @defgroup ETH_Checksum_Mode ETH Checksum Mode + * @{ + */ +#define ETH_MAC_CHECKSUM_MD_SW (0UL) +#define ETH_MAC_CHECKSUM_MD_HW (0x00000001UL) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Mode ETH Receive Mode + * @{ + */ +#define ETH_RX_MD_POLLING (0UL) +#define ETH_RX_MD_INT (0x00000001UL) +/** + * @} + */ + +/** + * @defgroup ETH_TX_CLK_POLARITY ETH TX Clock Polarity + * @{ + */ +#define ETH_MAC_TX_CLK_POLARITY_KEEP (0UL) +#define ETH_MAC_TX_CLK_POLARITY_INVERSE (ETH_MAC_IFCONFR_TCKINV) +/** + * @} + */ + +/** + * @defgroup ETH_RX_CLK_POLARITY ETH RX Clock Polarity + * @{ + */ +#define ETH_MAC_RX_CLK_POLARITY_KEEP (0UL) +#define ETH_MAC_RX_CLK_POLARITY_INVERSE (ETH_MAC_IFCONFR_RCKINV) +/** + * @} + */ + +/** + * @defgroup ETH_SRC_ADDR_Mode ETH Source Address Mode + * @{ + */ +#define ETH_MAC_SRC_ADDR_MD_BY_DMA_TXDESC (0UL) /*!< Configure the Insert mode by Tx Descriptor of DMA */ +#define ETH_MAC_SRC_ADDR_MD_INSTER_MACADDR0 (0x02UL << ETH_MAC_CONFIGR_SAIRC_POS) /*!< Insert address value in MAC address register 0 into transmit frame as source address */ +#define ETH_MAC_SRC_ADDR_MD_REPLACE_MACADDR0 (0x03UL << ETH_MAC_CONFIGR_SAIRC_POS) /*!< Replace source address in transmit frame with address value in MAC address register 0 */ +#define ETH_MAC_SRC_ADDR_MD_INSTER_MACADDR1 (0x06UL << ETH_MAC_CONFIGR_SAIRC_POS) /*!< Insert address value in MAC address register 1 into transmit frame as source address */ +#define ETH_MAC_SRC_ADDR_MD_REPLACE_MACADDR1 (0x07UL << ETH_MAC_CONFIGR_SAIRC_POS) /*!< Replace source address in transmit frame with address value in MAC address register 1 */ +/** + * @} + */ + +/** + * @defgroup ETH_TypeFrame_Strip_FCS ETH Type Frame Strip FCS + * @{ + */ +#define ETH_MAC_TYPE_FRAME_STRIP_FCS_DISABLE (0UL) +#define ETH_MAC_TYPE_FRAME_STRIP_FCS_ENABLE (ETH_MAC_CONFIGR_CST) +/** + * @} + */ + +/** + * @defgroup ETH_Watchdog ETH Watchdog + * @{ + */ +#define ETH_MAC_WATCHDOG_DISABLE (ETH_MAC_CONFIGR_MWD) +#define ETH_MAC_WATCHDOG_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Jabber ETH Jabber + * @{ + */ +#define ETH_MAC_JABBER_DISABLE (ETH_MAC_CONFIGR_MJB) +#define ETH_MAC_JABBER_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Interframe_Gap ETH Interframe Gap + * @{ + */ +#define ETH_MAC_INTERFRAME_GAP_96BIT (0UL) +#define ETH_MAC_INTERFRAME_GAP_88BIT (0x01UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_80BIT (0x02UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_72BIT (0x03UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_64BIT (0x04UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_56BIT (0x05UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_48BIT (0x06UL << ETH_MAC_CONFIGR_IFG_POS) +#define ETH_MAC_INTERFRAME_GAP_40BIT (0x07UL << ETH_MAC_CONFIGR_IFG_POS) +/** + * @} + */ + +/** + * @defgroup ETH_Carrier_Sense ETH Carrier Sense + * @{ + */ +#define ETH_MAC_CARRIER_SENSE_DISABLE (ETH_MAC_CONFIGR_DCRS) +#define ETH_MAC_CARRIER_SENSE_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Own ETH Receive Own + * @{ + */ +#define ETH_MAC_RX_OWN_DISABLE (ETH_MAC_CONFIGR_DO) +#define ETH_MAC_RX_OWN_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Checksum_Offload ETH Checksum Offload + * @{ + */ +#define ETH_MAC_CHECKSUM_OFFLOAD_DISABLE (0UL) +#define ETH_MAC_CHECKSUM_OFFLOAD_ENABLE (ETH_MAC_CONFIGR_IPCO) +/** + * @} + */ + +/** + * @defgroup ETH_Retry_Transmit ETH Retry Transmit + * @{ + */ +#define ETH_MAC_RETRY_TRANS_DISABLE (ETH_MAC_CONFIGR_DRTY) +#define ETH_MAC_RETRY_TRANS_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Auto_Strip_Pad_FCS ETH Auto Strip Pad FCS + * @{ + */ +#define ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE (0UL) +#define ETH_MAC_AUTO_STRIP_PAD_FCS_ENABLE (ETH_MAC_CONFIGR_ACS) +/** + * @} + */ + +/** + * @defgroup ETH_Back_Off_Limit ETH Back Off Limit + * @{ + */ +#define ETH_MAC_BACKOFF_LIMIT10 (0UL) +#define ETH_MAC_BACKOFF_LIMIT8 (ETH_MAC_CONFIGR_BL_0) +#define ETH_MAC_BACKOFF_LIMIT4 (ETH_MAC_CONFIGR_BL_1) +#define ETH_MAC_BACKOFF_LIMIT1 (ETH_MAC_CONFIGR_BL) +/** + * @} + */ + +/** + * @defgroup ETH_Deferral_Check ETH Deferral Check + * @{ + */ +#define ETH_MAC_DEFERRAL_CHECK_DISABLE (0UL) +#define ETH_MAC_DEFERRAL_CHECK_ENABLE (ETH_MAC_CONFIGR_DC) +/** + * @} + */ + +/** + * @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause + * @{ + */ +#define ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE (ETH_MAC_FLOCTLR_DZPQ) +#define ETH_MAC_ZERO_QUANTA_PAUSE_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold + * @{ + */ +#define ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS4 (0UL) /*!< Pause time minus 4 slot times */ +#define ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS28 (ETH_MAC_FLOCTLR_PLT_0) /*!< Pause time minus 28 slot times */ +#define ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS144 (ETH_MAC_FLOCTLR_PLT_1) /*!< Pause time minus 144 slot times */ +#define ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS256 (ETH_MAC_FLOCTLR_PLT) /*!< Pause time minus 256 slot times */ +/** + * @} + */ + +/** + * @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect + * @{ + */ +#define ETH_MAC_UNICAST_PAUSE_FRAME_DETECT_DISABLE (0UL) +#define ETH_MAC_UNICAST_PAUSE_FRAME_DETECT_ENABLE (ETH_MAC_FLOCTLR_UNP) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control + * @{ + */ +#define ETH_MAC_RX_FLOW_CTRL_DISABLE (0UL) +#define ETH_MAC_RX_FLOW_CTRL_ENABLE (ETH_MAC_FLOCTLR_RFE) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control + * @{ + */ +#define ETH_MAC_TRANS_FLOW_CTRL_DISABLE (0UL) +#define ETH_MAC_TRANS_FLOW_CTRL_ENABLE (ETH_MAC_FLOCTLR_TFE) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_All ETH Receive All + * @{ + */ +#define ETH_MAC_RX_ALL_DISABLE (0UL) +#define ETH_MAC_RX_ALL_ENABLE (ETH_MAC_FLTCTLR_RA) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_Not_TcpUdp ETH Drop Not TcpUdp + * @{ + */ +#define ETH_MAC_DROP_NOT_TCPUDP_DISABLE (0UL) +#define ETH_MAC_DROP_NOT_TCPUDP_ENABLE (ETH_MAC_FLTCTLR_DNTU) +/** + * @} + */ + +/** + * @defgroup ETH_VLAN_Tag_Filter ETH VLAN Tag Filter + * @{ + */ +#define ETH_MAC_VLAN_TAG_FILTER_DISABLE (0UL) +#define ETH_MAC_VLAN_TAG_FILTER_ENABLE (ETH_MAC_FLTCTLR_VTFE) +/** + * @} + */ + +/** + * @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter + * @{ + */ +#define ETH_MAC_SRC_ADDR_FILTER_DISABLE (0UL) +#define ETH_MAC_SRC_ADDR_FILTER_NORMAL (ETH_MAC_FLTCTLR_SAF) +#define ETH_MAC_SRC_ADDR_FILTER_INVERSE (ETH_MAC_FLTCTLR_SAF | ETH_MAC_FLTCTLR_SAIF) +/** + * @} + */ + +/** + * @defgroup ETH_Pass_Control_Frame ETH Pass Control Frame + * @{ + */ +#define ETH_MAC_PASS_CTRL_FRAME_BLOCK_ALL (0UL) /*!< MAC filter all control frame from reaching the application */ +#define ETH_MAC_PASS_CTRL_FRAME_FORWARD_NOT_PAUSE (ETH_MAC_FLTCTLR_PCF_0) /*!< MAC forward all control frame except pause control frame to application even if they fail the address filter */ +#define ETH_MAC_PASS_CTRL_FRAME_FORWARD_ALL (ETH_MAC_FLTCTLR_PCF_1) /*!< MAC forward all control frame to application even if they fail the address filter */ +#define ETH_MAC_PASS_CTRL_FRAME_FORWARD_PASS_FILTER (ETH_MAC_FLTCTLR_PCF) /*!< MAC forward control frame that pass the address filter. */ +/** + * @} + */ + +/** + * @defgroup ETH_Reception_Broadcast_Frame ETH Reception Broadcast Frame + * @{ + */ +#define ETH_MAC_RX_BROADCAST_FRAME_DISABLE (ETH_MAC_FLTCTLR_DBF) +#define ETH_MAC_RX_BROADCAST_FRAME_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter + * @{ + */ +#define ETH_MAC_DEST_ADDR_FILTER_NORMAL (0UL) +#define ETH_MAC_DEST_ADDR_FILTER_INVERSE (ETH_MAC_FLTCTLR_DAIF) +/** + * @} + */ + +/** + * @defgroup ETH_Multicast_Frame_Filter ETH Multicast Frame Filter + * @{ + */ +#define ETH_MAC_MULTICAST_FRAME_FILTER_NONE (ETH_MAC_FLTCTLR_PMF) +#define ETH_MAC_MULTICAST_FRAME_FILTER_PERFECT (0UL) +#define ETH_MAC_MULTICAST_FRAME_FILTER_HASHTABLE (ETH_MAC_FLTCTLR_HMC) +#define ETH_MAC_MULTICAST_FRAME_FILTER_PERFECT_HASHTABLE (ETH_MAC_FLTCTLR_HPF | ETH_MAC_FLTCTLR_HMC) +/** + * @} + */ + +/** + * @defgroup ETH_Unicast_Frame_Filter ETH Unicast Frame Filter + * @{ + */ +#define ETH_MAC_UNICAST_FRAME_FILTER_PERFECT (0UL) +#define ETH_MAC_UNICAST_FRAME_FILTER_HASHTABLE (ETH_MAC_FLTCTLR_HUC) +#define ETH_MAC_UNICAST_FRAME_FILTER_PERFECT_HASHTABLE (ETH_MAC_FLTCTLR_HPF | ETH_MAC_FLTCTLR_HUC) +/** + * @} + */ + +/** + * @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode + * @{ + */ +#define ETH_MAC_PROMISCUOUS_MD_DISABLE (0UL) +#define ETH_MAC_PROMISCUOUS_MD_ENABLE (ETH_MAC_FLTCTLR_PR) +/** + * @} + */ + +/** + * @defgroup ETH_Tx_VLAN_Insert_Mode ETH Tx VLAN Insert Mode + * @{ + */ +#define ETH_MAC_TXVLAN_MD_BY_DMA_TXDESC (0UL) /*!< Configure the Tx VLAN mode by Tx Descriptor of DMA */ +#define ETH_MAC_TXVLAN_MD_BYPASS (ETH_MAC_VTACTLR_VLANS) /*!< Do Nothing: VLAN Insertion is bypassed */ +#define ETH_MAC_TXVLAN_MD_REMOVE_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC_0) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_MAC_TXVLAN_MD_INSERT_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC_1) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_MAC_TXVLAN_MD_REPLACE_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +/** + * @} + */ + +/** + * @defgroup ETH_Rx_VLAN_Filter ETH Rx VLAN Filter + * @{ + */ +#define ETH_MAC_RXVLAN_FILTER_NORMAL (0UL) +#define ETH_MAC_RXVLAN_FILTER_INVERSE (ETH_MAC_VTAFLTR_VTIM) +#define ETH_MAC_RXVLAN_FILTER_NORMAL_HASHTABLE (ETH_MAC_VTAFLTR_VTHM) +#define ETH_MAC_RXVLAN_FILTER_INVERSE_HASHTABLE (ETH_MAC_VTAFLTR_VTHM | ETH_MAC_VTAFLTR_VTIM) +/** + * @} + */ + +/** + * @defgroup ETH_Rx_VLAN_Compare ETH Rx VLAN Compare + * @{ + */ +#define ETH_MAC_RXVLAN_CMP_16BIT (0UL) +#define ETH_MAC_RXVLAN_CMP_12BIT (ETH_MAC_VTAFLTR_VTAL) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Dest_Port_Filter ETH L4 Dest Port Filter + * @{ + */ +#define ETH_MAC_L4_DEST_PORT_FILTER_DISABLE (0UL) +#define ETH_MAC_L4_DEST_PORT_FILTER_NORMAL (ETH_MAC_L34CTLR_L4DPM) +#define ETH_MAC_L4_DEST_PORT_FILTER_INVERSE (ETH_MAC_L34CTLR_L4DPIM | ETH_MAC_L34CTLR_L4DPM) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Source_Port_Filter ETH L4 Source Port Filter + * @{ + */ +#define ETH_MAC_L4_SRC_PORT_FILTER_DISABLE (0UL) +#define ETH_MAC_L4_SRC_PORT_FILTER_NORMAL (ETH_MAC_L34CTLR_L4SPM) +#define ETH_MAC_L4_SRC_PORT_FILTER_INVERSE (ETH_MAC_L34CTLR_L4SPIM | ETH_MAC_L34CTLR_L4SPM) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Port_Filter_Protocol ETH L4 Port Filter Protocol + * @{ + */ +#define ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP (0UL) /*!< Port filter for TCP frame */ +#define ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP (ETH_MAC_L34CTLR_L4PEN) /*!< Port filter for UDP frame */ +/** + * @} + */ + +/** + * @defgroup ETH_L3_Dest_Addr_Filter_Mask ETH L3 Destination Addr Filter Mask + * @note The following definitions apply to IPv4. + * @{ + */ +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT0 (0x01UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT1_0 (0x02UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT2_0 (0x03UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT3_0 (0x04UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT4_0 (0x05UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT5_0 (0x06UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT6_0 (0x07UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT7_0 (0x08UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT8_0 (0x09UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT9_0 (0x0AUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT10_0 (0x0BUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT11_0 (0x0CUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT12_0 (0x0DUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT13_0 (0x0EUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT14_0 (0x0FUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT15_0 (0x10UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT16_0 (0x11UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT17_0 (0x12UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT18_0 (0x13UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT19_0 (0x14UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT20_0 (0x15UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT21_0 (0x16UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT22_0 (0x17UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT23_0 (0x18UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT24_0 (0x19UL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT25_0 (0x1AUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT26_0 (0x1BUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT27_0 (0x1CUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT28_0 (0x1DUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT29_0 (0x1EUL << ETH_MAC_L34CTLR_L3HDBM_POS) +#define ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT30_0 (0x1FUL << ETH_MAC_L34CTLR_L3HDBM_POS) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Source_Addr_Filter_Mask ETH L3 Source Addr Filter Mask + * @note The following definitions apply to IPv4 + * @{ + */ +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT0 (0x01UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT1_0 (0x02UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT2_0 (0x03UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT3_0 (0x04UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT4_0 (0x05UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT5_0 (0x06UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT6_0 (0x07UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT7_0 (0x08UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT8_0 (0x09UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT9_0 (0x0AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT10_0 (0x0BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT11_0 (0x0CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT12_0 (0x0DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT13_0 (0x0EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT14_0 (0x0FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT15_0 (0x10UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT16_0 (0x11UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT17_0 (0x12UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT18_0 (0x13UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT19_0 (0x14UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT20_0 (0x15UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT21_0 (0x16UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT22_0 (0x17UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT23_0 (0x18UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT24_0 (0x19UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT25_0 (0x1AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT26_0 (0x1BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT27_0 (0x1CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT28_0 (0x1DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT29_0 (0x1EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT30_0 (0x1FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Dest_Source_Addr_Filter_Mask ETH L3 Destination Source Address Filter Mask + * @note The following definitions apply to IPv6. + * @{ + */ +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT0 (0x01UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT1_0 (0x02UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT2_0 (0x03UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT3_0 (0x04UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT4_0 (0x05UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT5_0 (0x06UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT6_0 (0x07UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT7_0 (0x08UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT8_0 (0x09UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT9_0 (0x0AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT10_0 (0x0BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT11_0 (0x0CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT12_0 (0x0DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT13_0 (0x0EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT14_0 (0x0FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT15_0 (0x10UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT16_0 (0x11UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT17_0 (0x12UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT18_0 (0x13UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT19_0 (0x14UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT20_0 (0x15UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT21_0 (0x16UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT22_0 (0x17UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT23_0 (0x18UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT24_0 (0x19UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT25_0 (0x1AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT26_0 (0x1BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT27_0 (0x1CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT28_0 (0x1DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT29_0 (0x1EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT30_0 (0x1FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT31_0 (0x20UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT32_0 (0x21UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT33_0 (0x22UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT34_0 (0x23UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT35_0 (0x24UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT36_0 (0x25UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT37_0 (0x26UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT38_0 (0x27UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT39_0 (0x28UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT40_0 (0x29UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT41_0 (0x2AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT42_0 (0x2BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT43_0 (0x2CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT44_0 (0x2DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT45_0 (0x2EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT46_0 (0x2FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT47_0 (0x30UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT48_0 (0x31UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT49_0 (0x32UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT50_0 (0x33UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT51_0 (0x34UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT52_0 (0x35UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT53_0 (0x36UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT54_0 (0x37UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT55_0 (0x38UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT56_0 (0x39UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT57_0 (0x3AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT58_0 (0x3BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT59_0 (0x3CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT60_0 (0x3DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT61_0 (0x3EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT62_0 (0x3FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT63_0 (0x40UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT64_0 (0x41UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT65_0 (0x42UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT66_0 (0x43UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT67_0 (0x44UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT68_0 (0x45UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT69_0 (0x46UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT70_0 (0x47UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT71_0 (0x48UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT72_0 (0x49UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT73_0 (0x4AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT74_0 (0x4BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT75_0 (0x4CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT76_0 (0x4DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT77_0 (0x4EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT78_0 (0x4FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT79_0 (0x50UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT80_0 (0x51UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT81_0 (0x52UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT82_0 (0x53UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT83_0 (0x54UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT84_0 (0x55UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT85_0 (0x56UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT86_0 (0x57UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT87_0 (0x58UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT88_0 (0x59UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT89_0 (0x5AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT90_0 (0x5BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT91_0 (0x5CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT92_0 (0x5DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT93_0 (0x5EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT94_0 (0x5FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT95_0 (0x60UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT96_0 (0x61UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT97_0 (0x62UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT98_0 (0x63UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT99_0 (0x64UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT100_0 (0x65UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT101_0 (0x66UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT102_0 (0x67UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT103_0 (0x68UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT104_0 (0x69UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT105_0 (0x6AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT106_0 (0x6BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT107_0 (0x6CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT108_0 (0x6DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT109_0 (0x6EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT110_0 (0x6FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT111_0 (0x70UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT112_0 (0x71UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT113_0 (0x72UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT114_0 (0x73UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT115_0 (0x74UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT116_0 (0x75UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT117_0 (0x76UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT118_0 (0x77UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT119_0 (0x78UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT120_0 (0x79UL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT121_0 (0x7AUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT122_0 (0x7BUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT123_0 (0x7CUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT124_0 (0x7DUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT125_0 (0x7EUL << ETH_MAC_L34CTLR_L3HSBM_POS) +#define ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT126_0 (0x7FUL << ETH_MAC_L34CTLR_L3HSBM_POS) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Dest_Addr_Filter ETH L3 Destination Addr Filter + * @{ + */ +#define ETH_MAC_L3_DEST_ADDR_FILTER_DISABLE (0UL) +#define ETH_MAC_L3_DEST_ADDR_FILTER_NORMAL (ETH_MAC_L34CTLR_L3DAM) +#define ETH_MAC_L3_DEST_ADDR_FILTER_INVERSE (ETH_MAC_L34CTLR_L3DAIM | ETH_MAC_L34CTLR_L3DAM) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Source_Addr_Filter ETH L3 Source Addr Filter + * @{ + */ +#define ETH_MAC_L3_SRC_ADDR_FILTER_DISABLE (0UL) +#define ETH_MAC_L3_SRC_ADDR_FILTER_NORMAL (ETH_MAC_L34CTLR_L3SAM) +#define ETH_MAC_L3_SRC_ADDR_FILTER_INVERSE (ETH_MAC_L34CTLR_L3SAIM | ETH_MAC_L34CTLR_L3SAM) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Addr_Filter_Protocol ETH L3 Addr Filter Protocol + * @{ + */ +#define ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4 (0UL) /*!< Ip Address filter for IPv4 */ +#define ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6 (ETH_MAC_L34CTLR_L3PEN) /*!< Ip Address filter for IPv6 */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Index ETH MAC Address Index + * @{ + */ +#define ETH_MAC_ADDR_IDX0 (0x00000000UL) +#define ETH_MAC_ADDR_IDX1 (0x00000008UL) +#define ETH_MAC_ADDR_IDX2 (0x00000010UL) +#define ETH_MAC_ADDR_IDX3 (0x00000018UL) +#define ETH_MAC_ADDR_IDX4 (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Filter ETH MAC Address Filter + * @note The parameter is invalid in ETH_MAC_ADDR_IDX0. + * @{ + */ +#define ETH_MAC_ADDR_FILTER_DISABLE (0UL) /*!< Disable perfect filter with MAC address. */ +#define ETH_MAC_ADDR_FILTER_PERFECT_DEST_ADDR (ETH_MAC_MACADHR1_AE1) /*!< Filter the Destination address of the received frame with MAC address. */ +#define ETH_MAC_ADDR_FILTER_PERFECT_SRC_ADDR (ETH_MAC_MACADHR1_AE1 | ETH_MAC_MACADHR1_SA1) /*!< Filter the source address of the received frame with MAC address. */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Filter_Mask ETH MAC Address Filter Mask + * @note The parameter is invalid in ETH_MAC_ADDR_IDX0. + * @{ + */ +#define ETH_MAC_ADDR_MASK_DISABLE (0UL) /*!< Disable MAC Address Mask */ +#define ETH_MAC_ADDR_MASK_BYTE6 (ETH_MAC_MACADHR1_MBC1_5) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDR_MASK_BYTE5 (ETH_MAC_MACADHR1_MBC1_4) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDR_MASK_BYTE4 (ETH_MAC_MACADHR1_MBC1_3) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDR_MASK_BYTE3 (ETH_MAC_MACADHR1_MBC1_2) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDR_MASK_BYTE2 (ETH_MAC_MACADHR1_MBC1_1) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDR_MASK_BYTE1 (ETH_MAC_MACADHR1_MBC1_0) /*!< Mask MAC Address low reg bits [7:0] */ +#define ETH_MAC_ADDR_MASK_ALL (ETH_MAC_MACADHR1_MBC1) /*!< Mask MAC Address low reg bits [31:0] and low high bits [15:0] */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_INT_Flag ETH MAC Interrupt Flag + * @{ + */ +#define ETH_MAC_INT_FLAG_TSPIS (ETH_MAC_INTSTSR_TSPIS) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_INT_FLAG_MMCTXIS (ETH_MAC_INTSTSR_MMCTXIS) /*!< MMC transmit flag */ +#define ETH_MAC_INT_FLAG_MMCRXIS (ETH_MAC_INTSTSR_MMCRXIS) /*!< MMC receive flag */ +#define ETH_MAC_INT_FLAG_MMCIS (ETH_MAC_INTSTSR_MMCIS) /*!< MMC flag (on MAC) */ +#define ETH_MAC_INT_FLAG_PMTIS (ETH_MAC_INTSTSR_PMTIS) /*!< PMT flag (on MAC) */ +#define ETH_MAC_INT_FLAG_ALL (ETH_MAC_INT_FLAG_TSPIS | ETH_MAC_INT_FLAG_MMCTXIS | \ + ETH_MAC_INT_FLAG_MMCRXIS | ETH_MAC_INT_FLAG_MMCIS | \ + ETH_MAC_INT_FLAG_PMTIS) +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Interrupt ETH MAC Interrupt + * @{ + */ +#define ETH_MAC_INT_TSPIM (ETH_MAC_INTMSKR_TSPIM) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_INT_PMTIM (ETH_MAC_INTMSKR_PMTIM) /*!< PMT interrupt (on MAC) */ +#define ETH_MAC_INT_ALL (ETH_MAC_INT_TSPIM | ETH_MAC_INT_PMTIM) +/** + * @} + */ + +/** + * @defgroup ETH_Burst_Mode ETH Burst Mode + * @{ + */ +#define ETH_DMA_BURST_MD_NORMAL (0UL) /*!< DMA master interface only use SINGLE and INCR access type */ +#define ETH_DMA_BURST_MD_FIXED (ETH_DMA_BUSMODR_FBST) /*!< DMA master interface use SINGLE and INCR, INCR8, INCR16 access type */ +#define ETH_DMA_BURST_MD_MIXED (ETH_DMA_BUSMODR_MBST) /*!< DMA master interface will start all burst transmission with INCR length greater than 16 */ +/** + * @} + */ + +/** + * @defgroup ETH_Address_Align ETH Address Align + * @{ + */ +#define ETH_DMA_ADDR_ALIGN_DISABLE (0UL) +#define ETH_DMA_ADDR_ALIGN_ENABLE (ETH_DMA_BUSMODR_AAL) +/** + * @} + */ + +/** + * @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length + * @{ + */ +#define ETH_DMA_RX_BURST_LEN_1BEAT (ETH_DMA_BUSMODR_RPBL_0) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_DMA_RX_BURST_LEN_2BEAT (ETH_DMA_BUSMODR_RPBL_1) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_DMA_RX_BURST_LEN_4BEAT (ETH_DMA_BUSMODR_RPBL_2) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMA_RX_BURST_LEN_8BEAT (ETH_DMA_BUSMODR_RPBL_3) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMA_RX_BURST_LEN_16BEAT (ETH_DMA_BUSMODR_RPBL_4) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMA_RX_BURST_LEN_32BEAT (ETH_DMA_BUSMODR_RPBL_5) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_8BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_0) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_16BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_1) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_32BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_2) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_64BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_3) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_128BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_4) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMA_RX_BURST_LEN_8XPBL_256BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_5) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 256 */ +/** + * @} + */ + +/** + * @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length + * @{ + */ +#define ETH_DMA_TX_BURST_LEN_1BEAT (ETH_DMA_BUSMODR_TPBL_0) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_DMA_TX_BURST_LEN_2BEAT (ETH_DMA_BUSMODR_TPBL_1) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_DMA_TX_BURST_LEN_4BEAT (ETH_DMA_BUSMODR_TPBL_2) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMA_TX_BURST_LEN_8BEAT (ETH_DMA_BUSMODR_TPBL_3) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMA_TX_BURST_LEN_16BEAT (ETH_DMA_BUSMODR_TPBL_4) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMA_TX_BURST_LEN_32BEAT (ETH_DMA_BUSMODR_TPBL_5) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_8BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_0) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_16BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_1) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_32BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_2) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_64BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_3) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_128BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_4) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMA_TX_BURST_LEN_8XPBL_256BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_5) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 256 */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Enhance_Descriptor ETH DMA Enhance Descriptor + * @{ + */ +#define ETH_DMA_ENHANCE_DESC_DISABLE (0UL) +#define ETH_DMA_ENHANCE_DESC_ENABLE (ETH_DMA_BUSMODR_DSEN) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Arbitration ETH DMA Arbitration + * @{ + */ +#define ETH_DMA_ARBITRATION_LOOP_RXTX_1_1 (0UL) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_2_1 (ETH_DMA_BUSMODR_PRAT_0) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_3_1 (ETH_DMA_BUSMODR_PRAT_1) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_4_1 (ETH_DMA_BUSMODR_PRAT) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_1_1 (ETH_DMA_BUSMODR_TXPR) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_2_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT_0) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_3_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT_1) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_4_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT) +#define ETH_DMA_ARBITRATION_FIXED_RX_PRIOR_TX (ETH_DMA_BUSMODR_DMAA) +#define ETH_DMA_ARBITRATION_FIXED_TX_PRIOR_RX (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_DMAA) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_TCPIP_Checksum_Error_Frame ETH Drop TCPIP Checksum Error Frame + * @{ + */ +#define ETH_DMA_DROP_CHECKSUM_ERR_FRAME_DISABLE (ETH_DMA_OPRMODR_DTCOE) +#define ETH_DMA_DROP_CHECKSUM_ERR_FRAME_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward + * @{ + */ +#define ETH_DMA_RX_STORE_FORWARD_DISABLE (0UL) +#define ETH_DMA_RX_STORE_FORWARD_ENABLE (ETH_DMA_OPRMODR_RSF) +/** + * @} + */ + +/** + * @defgroup ETH_Flush_Receive_Frame ETH Flush Receive Frame + * @{ + */ +#define ETH_DMA_FLUSH_RX_FRAME_DISABLE (ETH_DMA_OPRMODR_DFRF) +#define ETH_DMA_FLUSH_RX_FRAME_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward + * @{ + */ +#define ETH_DMA_TRANS_STORE_FORWARD_DISABLE (0UL) +#define ETH_DMA_TRANS_STORE_FORWARD_ENABLE (ETH_DMA_OPRMODR_TSF) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Threshold ETH Transmit Threshold + * @{ + */ +#define ETH_DMA_TRANS_THRESHOLD_64BYTE (0UL) /*!< Threshold level of the Transmit FIFO is 64 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_128BYTE (0x01UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 128 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_192BYTE (0x02UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 192 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_256BYTE (0x03UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 256 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_40BYTE (0x04UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 40 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_32BYTE (0x05UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 32 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_24BYTE (0x06UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 24 Bytes */ +#define ETH_DMA_TRANS_THRESHOLD_16BYTE (0x07UL << ETH_DMA_OPRMODR_TTC_POS) /*!< Threshold level of the Transmit FIFO is 16 Bytes */ +/** + * @} + */ + +/** + * @defgroup ETH_Forward_Error_Frame ETH Forward Error Frame + * @{ + */ +#define ETH_DMA_FORWARD_ERR_FRAME_DISABLE (0UL) +#define ETH_DMA_FORWARD_ERR_FRAME_ENABLE (ETH_DMA_OPRMODR_FEF) +/** + * @} + */ + +/** + * @defgroup ETH_Forward_Undersize_Good_Frame ETH Forward Undersize Good Frame + * @{ + */ +#define ETH_DMA_FORWARD_UNDERSIZE_FRAME_DISABLE (0UL) +#define ETH_DMA_FORWARD_UNDERSIZE_FRAME_ENABLE (ETH_DMA_OPRMODR_FUF) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_Jumbo_Frame ETH Drop Jumbo Frame + * @{ + */ +#define ETH_DMA_DROP_JUMBO_FRAME_DISABLE (0UL) +#define ETH_DMA_DROP_JUMBO_FRAME_ENABLE (ETH_DMA_OPRMODR_DGF) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Threshold ETH Receive Threshold + * @{ + */ +#define ETH_DMA_RX_THRESHOLD_64BYTE (0UL) /*!< Threshold level of the Receive FIFO is 64 Bytes */ +#define ETH_DMA_RX_THRESHOLD_32BYTE (ETH_DMA_OPRMODR_RTC_0) /*!< Threshold level of the Receive FIFO is 32 Bytes */ +#define ETH_DMA_RX_THRESHOLD_96BYTE (ETH_DMA_OPRMODR_RTC_1) /*!< Threshold level of the Receive FIFO is 96 Bytes */ +#define ETH_DMA_RX_THRESHOLD_128BYTE (ETH_DMA_OPRMODR_RTC) /*!< Threshold level of the Receive FIFO is 128 Bytes */ +/** + * @} + */ + +/** + * @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate + * @{ + */ +#define ETH_DMA_SEC_FRAME_OPERA_DISABLE (0UL) +#define ETH_DMA_SEC_FRAME_OPERA_ENABLE (ETH_DMA_OPRMODR_OSF) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Flag ETH DMA Flag + * @{ + */ +#define ETH_DMA_FLAG_PTPS (ETH_DMA_DMASTSR_PTPS) /*!< Time-stamp trigger status */ +#define ETH_DMA_FLAG_PMTS (ETH_DMA_DMASTSR_PMTS) /*!< PMT trigger status */ +#define ETH_DMA_FLAG_MMCS (ETH_DMA_DMASTSR_MMCS) /*!< MMC trigger status */ +#define ETH_DMA_FLAG_EBUS (ETH_DMA_DMASTSR_EBUS) /*!< Error state bits */ +#define ETH_DMA_FLAG_TSTS (ETH_DMA_DMASTSR_TSTS) /*!< Transmit state */ +#define ETH_DMA_FLAG_RSTS (ETH_DMA_DMASTSR_RSTS) /*!< Receive state */ +#define ETH_DMA_FLAG_NIS (ETH_DMA_DMASTSR_NIS) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS (ETH_DMA_DMASTSR_AIS) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ERS (ETH_DMA_DMASTSR_ERS) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBS (ETH_DMA_DMASTSR_FBS) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ETS (ETH_DMA_DMASTSR_ETS) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWS (ETH_DMA_DMASTSR_RWS) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RSS (ETH_DMA_DMASTSR_RSS) /*!< Receive stopped flag */ +#define ETH_DMA_FLAG_RUS (ETH_DMA_DMASTSR_RUS) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_RIS (ETH_DMA_DMASTSR_RIS) /*!< Receive flag */ +#define ETH_DMA_FLAG_UNS (ETH_DMA_DMASTSR_UNS) /*!< Transmit Underflow flag */ +#define ETH_DMA_FLAG_OVS (ETH_DMA_DMASTSR_OVS) /*!< Receive Overflow flag */ +#define ETH_DMA_FLAG_TJS (ETH_DMA_DMASTSR_TJS) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TUS (ETH_DMA_DMASTSR_TUS) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TSS (ETH_DMA_DMASTSR_TSS) /*!< Transmit stopped flag */ +#define ETH_DMA_FLAG_TIS (ETH_DMA_DMASTSR_TIS) /*!< Transmit interrupt flag */ +#define ETH_DMA_FLAG_ALL (ETH_DMA_FLAG_PTPS | ETH_DMA_FLAG_PMTS | ETH_DMA_FLAG_MMCS | \ + ETH_DMA_FLAG_NIS | ETH_DMA_FLAG_AIS | ETH_DMA_FLAG_ERS | \ + ETH_DMA_FLAG_FBS | ETH_DMA_FLAG_ETS | ETH_DMA_FLAG_RWS | \ + ETH_DMA_FLAG_RSS | ETH_DMA_FLAG_RUS | ETH_DMA_FLAG_RIS | \ + ETH_DMA_FLAG_UNS | ETH_DMA_FLAG_OVS | ETH_DMA_FLAG_TJS | \ + ETH_DMA_FLAG_TUS | ETH_DMA_FLAG_TSS | ETH_DMA_FLAG_TIS) +#define ETH_DMA_FLAG_CLR_ALL (ETH_DMA_FLAG_NIS | ETH_DMA_FLAG_AIS | ETH_DMA_FLAG_ERS | \ + ETH_DMA_FLAG_FBS | ETH_DMA_FLAG_ETS | ETH_DMA_FLAG_RWS | \ + ETH_DMA_FLAG_RSS | ETH_DMA_FLAG_RUS | ETH_DMA_FLAG_RIS | \ + ETH_DMA_FLAG_UNS | ETH_DMA_FLAG_OVS | ETH_DMA_FLAG_TJS | \ + ETH_DMA_FLAG_TUS | ETH_DMA_FLAG_TSS | ETH_DMA_FLAG_TIS) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Error_State ETH DMA Error State + * @{ + */ +#define ETH_DMA_ERR_STATE_RX_WR_DATA (0UL) /*!< RxDMA generates error while writing data */ +#define ETH_DMA_ERR_STATE_TX_RD_DATA (0x03UL << ETH_DMA_DMASTSR_EBUS_POS) /*!< TxDMA generates error while reading data */ +#define ETH_DMA_ERR_STATE_RX_WR_DESC (0x04UL << ETH_DMA_DMASTSR_EBUS_POS) /*!< RxDMA generates error while writing descriptor */ +#define ETH_DMA_ERR_STATE_TX_WR_DESC (0x05UL << ETH_DMA_DMASTSR_EBUS_POS) /*!< TxDMA generates error while writing descriptor */ +#define ETH_DMA_ERR_STATE_RX_RD_DESC (0x06UL << ETH_DMA_DMASTSR_EBUS_POS) /*!< RxDMA generates error while reading descriptor */ +#define ETH_DMA_ERR_STATE_TX_RD_DESC (0x07UL << ETH_DMA_DMASTSR_EBUS_POS) /*!< TxDMA generates error while reading descriptor */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Transmit_State ETH DMA Transmit State + * @{ + */ +#define ETH_DMA_TRANS_STATE_STOPPED (0UL) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANS_STATE_FETCHING (0x01UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Running - Fetching the Tx descriptor */ +#define ETH_DMA_TRANS_STATE_WAITING (0x02UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Running - Waiting for status */ +#define ETH_DMA_TRANS_STATE_READING (0x03UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Running - Reading the data from host memory */ +#define ETH_DMA_TRANS_STATE_WRITING (0x04UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Running - Writing the time stamp */ +#define ETH_DMA_TRANS_STATE_SUSPENDED (0x06UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANS_STATE_CLOSING (0x07UL << ETH_DMA_DMASTSR_TSTS_POS) /*!< Running - Closing Rx descriptor */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Receive_State ETH DMA Receive State + * @{ + */ +#define ETH_DMA_RX_STATE_STOPPED (0UL) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RX_STATE_FETCHING (0x01UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Running - Fetching the Rx descriptor */ +#define ETH_DMA_RX_STATE_WAITING (0x03UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Running - Waiting for packet */ +#define ETH_DMA_RX_STATE_SUSPENDED (0x04UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RX_STATE_CLOSING (0x05UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Running - Closing descriptor */ +#define ETH_DMA_RX_STATE_WRITING (0x06UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Running - Writing the time stamp */ +#define ETH_DMA_RX_STATE_QUEUING (0x07UL << ETH_DMA_DMASTSR_RSTS_POS) /*!< Running - Queuing the receive frame into host memory */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Interrupt ETH DMA Interrupt + * @{ + */ +#define ETH_DMA_INT_NIE (ETH_DMA_INTENAR_NIE) /*!< Normal interrupt summary */ +#define ETH_DMA_INT_AIE (ETH_DMA_INTENAR_AIE) /*!< Abnormal interrupt summary */ +#define ETH_DMA_INT_ERE (ETH_DMA_INTENAR_ERE) /*!< Early receive interrupt */ +#define ETH_DMA_INT_FBE (ETH_DMA_INTENAR_FBE) /*!< Fatal bus error interrupt */ +#define ETH_DMA_INT_ETE (ETH_DMA_INTENAR_ETE) /*!< Early transmit interrupt */ +#define ETH_DMA_INT_RWE (ETH_DMA_INTENAR_RWE) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_INT_RSE (ETH_DMA_INTENAR_RSE) /*!< Receive process stopped interrupt */ +#define ETH_DMA_INT_RUE (ETH_DMA_INTENAR_RUE) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_INT_RIE (ETH_DMA_INTENAR_RIE) /*!< Receive interrupt */ +#define ETH_DMA_INT_UNE (ETH_DMA_INTENAR_UNE) /*!< Transmit Underflow interrupt */ +#define ETH_DMA_INT_OVE (ETH_DMA_INTENAR_OVE) /*!< Receive Overflow interrupt */ +#define ETH_DMA_INT_TJE (ETH_DMA_INTENAR_TJE) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_INT_TUE (ETH_DMA_INTENAR_TUE) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_INT_TSE (ETH_DMA_INTENAR_TSE) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_INT_TIE (ETH_DMA_INTENAR_TIE) /*!< Transmit interrupt */ +#define ETH_DMA_INT_ALL (ETH_DMA_INT_NIE | ETH_DMA_INT_AIE | ETH_DMA_INT_ERE | \ + ETH_DMA_INT_FBE | ETH_DMA_INT_ETE | ETH_DMA_INT_RWE | \ + ETH_DMA_INT_RSE | ETH_DMA_INT_RUE | ETH_DMA_INT_RIE | \ + ETH_DMA_INT_UNE | ETH_DMA_INT_OVE | ETH_DMA_INT_TJE | \ + ETH_DMA_INT_TUE | ETH_DMA_INT_TSE | ETH_DMA_INT_TIE) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Overflow ETH DMA Overflow + * @{ + */ +#define ETH_DMA_OVF_RXFIFO_CNT (ETH_DMA_RFRCNTR_OVFOVF) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVF_MISS_FRAME_CNT (ETH_DMA_RFRCNTR_UNAOVF) /*!< Overflow bit for miss frame counter */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Descriptor_Own ETH DMA Descriptor Own + * @{ + */ +#define ETH_DMA_DESC_OWN_CPU (0UL) /*!< The descriptor is owned by CPU */ +#define ETH_DMA_DESC_OWN_DMA (ETH_DMA_TXDESC_OWN) /*!< The descriptor is owned by DMA */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Descriptor_Buffer ETH DMA Descriptor Buffer + * @{ + */ +#define ETH_DMA_DESC_BUF1 (0x00UL) /*!< DMA Descriptor Buffer1 */ +#define ETH_DMA_DESC_BUF2 (0x01UL) /*!< DMA Descriptor Buffer2 */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control + * @{ + */ +#define ETH_DMA_TXDESC_CHECKSUM_BYPASS (ETH_DMA_TXDESC_CIC_BYPASS) /*!< Checksum Engine is bypassed */ +#define ETH_DMA_TXDESC_CHECKSUM_IPV4_HEADER (ETH_DMA_TXDESC_CIC_IPV4_HEADER) /*!< IPv4 header checksum insertion */ +#define ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_SEGMENT (ETH_DMA_TXDESC_CIC_TCPUDPICMP_SEGMENT) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_FULL (ETH_DMA_TXDESC_CIC_TCPUDPICMP_FULL) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_VLAN_Insertion_Control ETH DMA Tx Descriptor VLAN Insertion Control + * @{ + */ +#define ETH_DMA_TXDESC_VLAN_BYPASS (ETH_DMA_TXDESC_VLANC_BYPASS) /*!< VLAN Insertion is bypassed */ +#define ETH_DMA_TXDESC_VLAN_REMOVE_TAG (ETH_DMA_TXDESC_VLANC_REMOVE_TAG) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_DMA_TXDESC_VLAN_INSERT_TAG (ETH_DMA_TXDESC_VLANC_INSERT_TAG) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_DMA_TXDESC_VLAN_REPLACE_TAG (ETH_DMA_TXDESC_VLANC_REPLACE_TAG) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_SA_Insertion_Control ETH DMA Tx Descriptor SA Insertion Control + * @{ + */ +#define ETH_DMA_TXDESC_SRC_ADDR_BYPASS (ETH_DMA_TXDESC_SAIRC_BYPASS) /*!< Source Address Insertion or Replace Control is bypassed */ +#define ETH_DMA_TXDESC_SRC_ADDR_INSTER_MACADDR0 (ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR0) /*!< Insert address value in MAC address register 0 into transmit frame as source address */ +#define ETH_DMA_TXDESC_SRC_ADDR_REPLACE_MACADDR0 (ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR0) /*!< Replace source address in transmit frame with address value in MAC address register 0 */ +#define ETH_DMA_TXDESC_SRC_ADDR_INSTER_MACADDR1 (ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR1) /*!< Insert address value in MAC address register 1 into transmit frame as source address */ +#define ETH_DMA_TXDESC_SRC_ADDR_REPLACE_MACADDR1 (ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR1) /*!< Replace source address in transmit frame with address value in MAC address register 1 */ +/** + * @} + */ + +/** + * @defgroup ETH_PMT_Flag ETH PMT Flag + * @{ + */ +#define ETH_PMT_FLAG_RTWKFR (ETH_MAC_PMTCTLR_RTWKFR) /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WKFR (ETH_MAC_PMTCTLR_WKFR) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPFR (ETH_MAC_PMTCTLR_MPFR) /*!< Magic Packet Received */ +#define ETH_PMT_FLAG_ALL (ETH_PMT_FLAG_RTWKFR | ETH_PMT_FLAG_WKFR | ETH_PMT_FLAG_MPFR) +/** + * @} + */ + +/** + * @defgroup ETH_PMT_Wakeup_Source ETH PMT Wakeup Source + * @{ + */ +#define ETH_PMT_WAKEUP_SRC_GLOBAL_UNICAST (ETH_MAC_PMTCTLR_GLUB) /*!< Global unicast */ +#define ETH_PMT_WAKEUP_SRC_WAKEUP_FRAME (ETH_MAC_PMTCTLR_WKEN) /*!< Wake-Up Frame */ +#define ETH_PMT_WAKEUP_SRC_MAGIC_PACKET (ETH_MAC_PMTCTLR_MPEN) /*!< Magic Packet */ +#define ETH_PMT_WAKEUP_SRC_ALL (ETH_PMT_WAKEUP_SRC_GLOBAL_UNICAST | \ + ETH_PMT_WAKEUP_SRC_WAKEUP_FRAME | \ + ETH_PMT_WAKEUP_SRC_MAGIC_PACKET) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Counter_Preset_Mode ETH MMC Counter Preset Mode + * @{ + */ +#define ETH_MMC_CNT_PRESET_MD_DISABLE (0UL) /*!< Disable preset */ +#define ETH_MMC_CNT_PRESET_MD_HALF_VALUE (ETH_MMC_MMCCTLR_MCPSET) /*!< Half-Value preset: 0x7FF0 */ +#define ETH_MMC_CNT_PRESET_MD_FULL_VALUE (ETH_MMC_MMCCTLR_MCPSEL | ETH_MMC_MMCCTLR_MCPSET) /*!< Full-Value preset: 0xFFF0 */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Read_Reset ETH MMC Read Reset + * @{ + */ +#define ETH_MMC_RD_RST_DISABLE (0UL) +#define ETH_MMC_RD_RST_ENABLE (ETH_MMC_MMCCTLR_ROR) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Counter_Reload ETH MMC Counter Reload + * @{ + */ +#define ETH_MMC_CNT_RELOAD_DISABLE (ETH_MMC_MMCCTLR_COS) +#define ETH_MMC_CNT_RELOAD_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Tx_Flag ETH MMC Tx Flag + * @{ + */ +#define ETH_MMC_FLAG_TXEDEIS (ETH_MMC_TRSSTSR_TXEDEIS) /*!< When Tx excessive deferral error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXUGIS (ETH_MMC_TRSSTSR_TXUGIS) /*!< When Tx unicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXCAEIS (ETH_MMC_TRSSTSR_TXCAEIS) /*!< When Tx carrier error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXECEIS (ETH_MMC_TRSSTSR_TXECEIS) /*!< When Tx excessive collision error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXLCEIS (ETH_MMC_TRSSTSR_TXLCEIS) /*!< When Tx deferral collision error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXDEEIS (ETH_MMC_TRSSTSR_TXDEEIS) /*!< When Tx deferral error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXMGIS (ETH_MMC_TRSSTSR_TXMGIS) /*!< When Tx multicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXBGIS (ETH_MMC_TRSSTSR_TXBGIS) /*!< When Tx broadcast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TX_ALL (ETH_MMC_FLAG_TXEDEIS | ETH_MMC_FLAG_TXUGIS | \ + ETH_MMC_FLAG_TXCAEIS | ETH_MMC_FLAG_TXECEIS | \ + ETH_MMC_FLAG_TXLCEIS | ETH_MMC_FLAG_TXDEEIS | \ + ETH_MMC_FLAG_TXMGIS | ETH_MMC_FLAG_TXBGIS) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Rx_Flag ETH MMC Rx Flag + * @{ + */ +#define ETH_MMC_FLAG_RXOEIS (ETH_MMC_REVSTSR_RXOEIS) /*!< When Rx out of scope error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXLEIS (ETH_MMC_REVSTSR_RXLEIS) /*!< When Rx length error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXUGIS (ETH_MMC_REVSTSR_RXUGIS) /*!< When Rx unicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXREIS (ETH_MMC_REVSTSR_RXREIS) /*!< When Rx short error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXAEIS (ETH_MMC_REVSTSR_RXAEIS) /*!< When Rx alignment error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXCEIS (ETH_MMC_REVSTSR_RXCEIS) /*!< When Rx crc error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXMGIS (ETH_MMC_REVSTSR_RXMGIS) /*!< When Rx multicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXBGIS (ETH_MMC_REVSTSR_RXBGIS) /*!< When Rx broadcast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RX_ALL (ETH_MMC_FLAG_RXOEIS | ETH_MMC_FLAG_RXLEIS | ETH_MMC_FLAG_RXUGIS | \ + ETH_MMC_FLAG_RXREIS | ETH_MMC_FLAG_RXAEIS | ETH_MMC_FLAG_RXCEIS | \ + ETH_MMC_FLAG_RXMGIS | ETH_MMC_FLAG_RXBGIS) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Tx_Interrupt ETH MMC Tx Interrupt + * @{ + */ +#define ETH_MMC_INT_TXEDEIM (ETH_MMC_TITCTLR_TXEDEIM) /*!< Tx excessive deferral error frame interrupt */ +#define ETH_MMC_INT_TXUGIM (ETH_MMC_TITCTLR_TXUGIM) /*!< Tx unicast good frame interrupt */ +#define ETH_MMC_INT_TXCAEIM (ETH_MMC_TITCTLR_TXCAEIM) /*!< Tx carrier error frame interrupt */ +#define ETH_MMC_INT_TXECEIM (ETH_MMC_TITCTLR_TXECEIM) /*!< Tx excessive collision error frame interrupt */ +#define ETH_MMC_INT_TXLCEIM (ETH_MMC_TITCTLR_TXLCEIM) /*!< Tx deferral collision error frame interrupt */ +#define ETH_MMC_INT_TXDEEIM (ETH_MMC_TITCTLR_TXDEEIM) /*!< Tx deferral error frame interrupt */ +#define ETH_MMC_INT_TXMGIM (ETH_MMC_TITCTLR_TXMGIM) /*!< Tx multicast good frame interrupt */ +#define ETH_MMC_INT_TXBGIM (ETH_MMC_TITCTLR_TXBGIM) /*!< Tx broadcast good frame interrupt */ +#define ETH_MMC_INT_TX_ALL (ETH_MMC_INT_TXEDEIM | ETH_MMC_INT_TXUGIM | ETH_MMC_INT_TXCAEIM | \ + ETH_MMC_INT_TXECEIM | ETH_MMC_INT_TXLCEIM | ETH_MMC_INT_TXDEEIM | \ + ETH_MMC_INT_TXMGIM | ETH_MMC_INT_TXBGIM) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Rx_Interrupt ETH MMC Rx Interrupt + * @{ + */ +#define ETH_MMC_INT_RXOEIM (ETH_MMC_RITCTLR_RXOEIM) /*!< Rx out of scope error frame interrupt */ +#define ETH_MMC_INT_RXLEIM (ETH_MMC_RITCTLR_RXLEIM) /*!< Rx length error frame interrupt */ +#define ETH_MMC_INT_RXUGIM (ETH_MMC_RITCTLR_RXUGIM) /*!< Rx unicast good frame interrupt */ +#define ETH_MMC_INT_RXREIM (ETH_MMC_RITCTLR_RXREIM) /*!< Rx short error frame interrupt */ +#define ETH_MMC_INT_RXAEIM (ETH_MMC_RITCTLR_RXAEIM) /*!< Rx alignment error frame interrupt */ +#define ETH_MMC_INT_RXCEIM (ETH_MMC_RITCTLR_RXCEIM) /*!< Rx crc error frame interrupt */ +#define ETH_MMC_INT_RXMGIM (ETH_MMC_RITCTLR_RXMGIM) /*!< Rx multicast good frame interrupt */ +#define ETH_MMC_INT_RXBGIM (ETH_MMC_RITCTLR_RXBGIM) /*!< Rx broadcast good frame interrupt */ +#define ETH_MMC_INT_RX_ALL (ETH_MMC_INT_RXOEIM | ETH_MMC_INT_RXLEIM | ETH_MMC_INT_RXUGIM | \ + ETH_MMC_INT_RXREIM | ETH_MMC_INT_RXAEIM | ETH_MMC_INT_RXCEIM | \ + ETH_MMC_INT_RXMGIM | ETH_MMC_INT_RXBGIM) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Statistical_Register ETH MMC Statistical Register + * @{ + */ +#define ETH_MMC_REG_TXBRGFR (0x011CU) /*!< Tx broadcast good frame Statistical Register */ +#define ETH_MMC_REG_TXMUGFR (0x0120U) /*!< Tx multicast good frame Statistical Register */ +#define ETH_MMC_REG_TXDEEFR (0x0154U) /*!< Tx deferral error frame Statistical Register */ +#define ETH_MMC_REG_TXLCEFR (0x0158U) /*!< Tx deferral collision error frame Statistical Register */ +#define ETH_MMC_REG_TXECEFR (0x015CU) /*!< Tx excessive collision error frame Statistical Register */ +#define ETH_MMC_REG_TXCAEFR (0x0160U) /*!< Tx carrier error frame Statistical Register */ +#define ETH_MMC_REG_TXUNGFR (0x0168U) /*!< Tx unicast good frame Statistical Register */ +#define ETH_MMC_REG_TXEDEFR (0x016CU) /*!< Tx excessive deferral error frame Statistical Register */ +#define ETH_MMC_REG_RXBRGFR (0x018CU) /*!< Rx broadcast good frame Statistical Register */ +#define ETH_MMC_REG_RXMUGFR (0x0190U) /*!< Rx multicast good frame Statistical Register */ +#define ETH_MMC_REG_RXCREFR (0x0194U) /*!< Rx crc error frame Statistical Register */ +#define ETH_MMC_REG_RXALEFR (0x0198U) /*!< Rx alignment error frame Statistical Register */ +#define ETH_MMC_REG_RXRUEFR (0x019CU) /*!< Rx short error frame Statistical Register */ +#define ETH_MMC_REG_RXUNGFR (0x01C4U) /*!< Rx unicast good frame Statistical Register */ +#define ETH_MMC_REG_RXLEEFR (0x01C8U) /*!< Rx length error frame Statistical Register */ +#define ETH_MMC_REG_RXOREFR (0x01CCU) /*!< Rx out of scope error frame Statistical Register */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Frame_Dest_Addr_Filter ETH PTP Frame Destination Address Filter + * @{ + */ +#define ETH_PTP_DEST_ADDR_FILTER_DISABLE (0x00800000UL) +#define ETH_PTP_DEST_ADDR_FILTER_ENABLE (ETH_PTP_TSPCTLR_TSPADF) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Snapshot_Datagram_Type ETH PTP Snapshot Datagram Type + * @{ + */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY (0UL) /*!< SYNC Follow_Up Delay_Req Delay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC (0x01UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< SYNC */ +#define ETH_PTP_DATAGRAM_TYPE_DELAY (0x03UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< Delay_Req */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY (0x04UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< SYNC Follow_Up Delay_Req Delay_Resp Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY (0x05UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< SYNC Pdelay_Req Pdelay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY (0x07UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< Delay_Req Pdelay_Req Pdelay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY (0x08UL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< SYNC Delay_Req */ +#define ETH_PTP_DATAGRAM_TYPE_PDELAY (0x0CUL << ETH_PTP_TSPCTLR_TSPMTSEL_POS) /*!< Pdelay_Req Pdelay_Resp */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Snapshot_Frame_Type ETH PTP Snapshot Frame Type + * @{ + */ +#define ETH_PTP_FRAME_TYPE_IPV4_FRAME (ETH_PTP_TSPCTLR_TSPOVIPV4) /*!< Time stamp snapshot for IPv4 frame */ +#define ETH_PTP_FRAME_TYPE_IPV6_FRAME (ETH_PTP_TSPCTLR_TSPOVIPV6) /*!< Time stamp snapshot for IPv6 frame */ +#define ETH_PTP_FRAME_TYPE_ETH_FRAME (ETH_PTP_TSPCTLR_TSPOVETH) /*!< Time stamp snapshot for PTP over ethernet frame */ +#define ETH_PTP_FRAME_TYPE_RX_FRAME (ETH_PTP_TSPCTLR_TSPEALL) /*!< Time stamp snapshot for all received frame */ +#define ETH_PTP_FRAME_TYPE_ALL (ETH_PTP_FRAME_TYPE_IPV4_FRAME | \ + ETH_PTP_FRAME_TYPE_IPV6_FRAME | \ + ETH_PTP_FRAME_TYPE_ETH_FRAME | \ + ETH_PTP_FRAME_TYPE_RX_FRAME) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Datagram_Version ETH PTP Datagram Version + * @{ + */ +#define ETH_PTP_DATAGRAM_VER_IEEE1588V1 (0UL) +#define ETH_PTP_DATAGRAM_VER_IEEE1588V2 (ETH_PTP_TSPCTLR_TSPVER) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Subsecond_Scale ETH PTP Subsecond Scale + * @{ + */ +#define ETH_PTP_SUBSEC_SCALE_HEX (0UL) /*!< The Second register increase 1 when SubSecond count to 0x7FFFFFFFH */ +#define ETH_PTP_SUBSEC_SCALE_DEC (ETH_PTP_TSPCTLR_TSPSSR) /*!< The Second register increase 1 when SubSecond count to 0x3B9AC9FFH */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Calibration_Mode ETH PTP Calibration Mode + * @{ + */ +#define ETH_PTP_CALIB_MD_COARSE (0UL) /*!< Coarse calibration */ +#define ETH_PTP_CALIB_MD_FINE (ETH_PTP_TSPCTLR_TSPUPSEL) /*!< Fine calibration */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Time_Update_Sign ETH PTP Time Update Sign + * @{ + */ +#define ETH_PTP_TIME_UPDATE_SIGN_MINUS (0UL) /*!< Minus for update register value */ +#define ETH_PTP_TIME_UPDATE_SIGN_PLUS (ETH_PTP_TMUNSER_TSPUPNS) /*!< Plus for update register value */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Flag ETH PTP Flag + * @{ + */ +#define ETH_PTP_FLAG_TSERR1 (ETH_PTP_TSPSTSR_TSERR1) /*!< Target time 1 error */ +#define ETH_PTP_FLAG_TSTAR1 (ETH_PTP_TSPSTSR_TSTAR1) /*!< Target time 1 reached */ +#define ETH_PTP_FLAG_TSERR0 (ETH_PTP_TSPSTSR_TSERR0) /*!< Target time 0 error */ +#define ETH_PTP_FLAG_TSTAR0 (ETH_PTP_TSPSTSR_TSTAR0) /*!< Target time 0 reached */ +#define ETH_PTP_FLAG_TSOVF (ETH_PTP_TSPSTSR_TSOVF) /*!< System time overflow */ +#define ETH_PTP_FLAG_ALL (ETH_PTP_FLAG_TSERR1 | ETH_PTP_FLAG_TSTAR1 | ETH_PTP_FLAG_TSERR0 | \ + ETH_PTP_FLAG_TSTAR0 | ETH_PTP_FLAG_TSOVF) +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Channel ETH PPS Channel + * @{ + */ +#define ETH_PPS_CH0 (0x00U) +#define ETH_PPS_CH1 (0x01U) +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Trigger_Function ETH PPS Trigger Function + * @{ + */ +#define ETH_PPS_TRIG_FUNC_INT_EVT (0UL) /*!< The Target register is used only for interrupt output event */ +#define ETH_PPS_TRIG_FUNC_INT_PPS_EVT (ETH_PTP_PPSCTLR_TT0SEL_1) /*!< The Target register is used for interrupt out event and PPS single output event */ +#define ETH_PPS_TRIG_FUNC_PPS_EVT (ETH_PTP_PPSCTLR_TT0SEL) /*!< The Target register is used for PPS single output event */ +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Output_Mode ETH PPS Output Mode + * @note PPS1(ETH_PPS_CH1) only supports single output mode(ETH_PPS_OUTPUT_MD_ONCE). + * @{ + */ +#define ETH_PPS_OUTPUT_MD_CONTINUE (0UL) /*!< Continuous output mode */ +#define ETH_PPS_OUTPUT_MD_ONCE (ETH_PTP_PPSCTLR_PPSOMD) /*!< Once output mode */ +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Output_Frequency ETH PPS Output Frequency + * @note PPS1(ETH_PPS_CH1) only supports generate a pulse(ETH_PPS_OUTPUT_ONE_PULSE). + * @{ + */ +#define ETH_PPS_OUTPUT_FREQ_1HZ (0UL) /*!< Ouput pulse is 1HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_2HZ (0x01UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 2HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_4HZ (0x02UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 4HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_8HZ (0x03UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 8HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_16HZ (0x04UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 16HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_32HZ (0x05UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 32HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_64HZ (0x06UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 64HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_128HZ (0x07UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 128HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_256HZ (0x08UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 256HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_512HZ (0x09UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 512HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_1024HZ (0x0AUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 1024HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_2048HZ (0x0BUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 2048HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_4096HZ (0x0CUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 4096HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_8192HZ (0x0DUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 8192HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_16384HZ (0x0EUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 16384HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_32768HZ (0x0FUL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< Ouput pulse is 32768HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_ONE_PULSE (0x01UL << ETH_PTP_PPSCTLR_PPSFRE0_POS) /*!< One pulse is generated in single ouput mode */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ETH_Global_Functions + * @{ + */ + +/** + * @brief Generate MAC pause control frame. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_MAC_GeneratePauseCtrlFrame(void) +{ + WRITE_REG32(bCM_ETH->MAC_FLOCTLR_b.FCA_BPA, ENABLE); +} + +/** + * @brief Get MAC flow control status. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +__STATIC_INLINE en_flag_status_t ETH_MAC_GetFlowControlStatus(void) +{ + return ((en_flag_status_t)READ_REG32(bCM_ETH->MAC_FLOCTLR_b.FCA_BPA)); +} + +/** + * @brief Resume the DMA Transmit. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_DMA_ResumeTrans(void) +{ + WRITE_REG32(CM_ETH->DMA_TXPOLLR, 0U); +} + +/** + * @brief Resume the DMA Receive. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_DMA_ResumeReceive(void) +{ + WRITE_REG32(CM_ETH->DMA_RXPOLLR, 0U); +} + +/** + * @brief Get DMA error status. + * @param None + * @retval uint32_t The new DMA error status + * The error status may be one of the following values: + * - ETH_DMA_ERR_STATE_RX_WR_DATA: TxDMA generates error while reading descriptor + * - ETH_DMA_ERR_STATE_TX_RD_DATA: TxDMA generates error while reading descriptor + * - ETH_DMA_ERR_STATE_RX_WR_DESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERR_STATE_TX_WR_DESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERR_STATE_RX_RD_DESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERR_STATE_TX_RD_DESC: TxDMA generates error while reading descriptor + */ +__STATIC_INLINE uint32_t ETH_DMA_GetErrorStatus(void) +{ + return (READ_REG32_BIT(CM_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_EBUS)); +} + +/** + * @brief Get DMA transmit status. + * @param None + * @retval uint32_t The new DMA transmit status + * The transmit status may be one of the following values: + * - ETH_DMA_TRANS_STATE_STOPPED: Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TRANS_STATE_FETCHING: Running - Fetching the Tx descriptor + * - ETH_DMA_TRANS_STATE_WAITING: Running - Waiting for status + * - ETH_DMA_TRANS_STATE_READING: Running - Reading the data from host memory + * - ETH_DMA_TRANS_STATE_WRITING: Running - Writing the time stamp + * - ETH_DMA_TRANS_STATE_SUSPENDED: Suspended - Tx Descriptor unavailable + * - ETH_DMA_TRANS_STATE_CLOSING: Running - Closing Rx descriptor + */ +__STATIC_INLINE uint32_t ETH_DMA_GetTransStatus(void) +{ + return (READ_REG32_BIT(CM_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_TSTS)); +} + +/** + * @brief Get DMA receive status. + * @param None + * @retval uint32_t The new DMA receive status + * The receive status may be one of the following values: + * - ETH_DMA_RX_STATE_STOPPED: Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_RX_STATE_FETCHING: Running - Fetching the Rx descriptor + * - ETH_DMA_RX_STATE_WAITING: Running - Waiting for packet + * - ETH_DMA_RX_STATE_SUSPENDED: Suspended - Rx Descriptor unavailable + * - ETH_DMA_RX_STATE_CLOSING: Running - Closing descriptor + * - ETH_DMA_RX_STATE_WRITING: Running - Writing the time stamp + * - ETH_DMA_RX_STATE_QUEUING: Running - Queuing the receive frame into host memory + */ +__STATIC_INLINE uint32_t ETH_DMA_GetReceiveStatus(void) +{ + return (READ_REG32_BIT(CM_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_RSTS)); +} + +/** + * @brief Get DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval uint32_t Rx Overflow Missed Frame Counter value + */ +__STATIC_INLINE uint32_t ETH_DMA_GetOvfMissFrameCount(void) +{ + return ((READ_REG32_BIT(CM_ETH->DMA_RFRCNTR, ETH_DMA_RFRCNTR_OVFCNT)) >> ETH_DMA_RFRCNTR_OVFCNT_POS); +} + +/** + * @brief Get DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval uint32_t Buffer Unavailable Missed Frame Counter value + */ +__STATIC_INLINE uint32_t ETH_DMA_GetBufUnavailableMissFrameCount(void) +{ + return (READ_REG32_BIT(CM_ETH->DMA_RFRCNTR, ETH_DMA_RFRCNTR_UNACNT)); +} + +/** + * @brief Get DMA current Tx descriptor start address. + * @param None + * @retval uint32_t Transmit descriptor start address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurrentTxDescAddr(void) +{ + return (READ_REG32(CM_ETH->DMA_CHTXDER)); +} + +/** + * @brief Get DMA current Rx descriptor start address. + * @param None + * @retval uint32_t Receive descriptor start address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurrentRxDescAddr(void) +{ + return (READ_REG32(CM_ETH->DMA_CHRXDER)); +} + +/** + * @brief Get DMA current Tx buffer address. + * @param None + * @retval uint32_t Transmit buffer address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurrentTxBufAddr(void) +{ + return (READ_REG32(CM_ETH->DMA_CHTXBFR)); +} + +/** + * @brief Get DMA current Rx buffer address. + * @param None + * @retval uint32_t Receive buffer address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurrentRxBufAddr(void) +{ + return (READ_REG32(CM_ETH->DMA_CHRXBFR)); +} + +/** + * @brief Get PMT wakeup frame filter register pointer index. + * @param None + * @retval uint8_t Filter register pointer index. + */ +__STATIC_INLINE uint8_t ETH_PMT_GetWakeupFramePointerIndex(void) +{ + return ((uint8_t)(READ_REG32_BIT(CM_ETH->MAC_PMTCTLR, ETH_MAC_PMTCTLR_RTWKPT) >> ETH_MAC_PMTCTLR_RTWKPT_POS)); +} + +/** + * @brief Get PTP snapshot frame type. + * @param None + * @retval uint32_t Receive frame type + */ +__STATIC_INLINE uint32_t ETH_PTP_GetSnapFrameType(void) +{ + return (READ_REG32_BIT(CM_ETH->PTP_TSPCTLR, ETH_PTP_FRAME_TYPE_ALL)); +} + +int32_t ETH_DeInit(void); +int32_t ETH_Init(stc_eth_handle_t *pstcEthHandle, stc_eth_init_t *pstcEthInit); +int32_t ETH_CommStructInit(stc_eth_comm_init_t *pstcCommInit); +int32_t ETH_StructInit(stc_eth_init_t *pstcEthInit); +int32_t ETH_Start(void); +int32_t ETH_Stop(void); + +/* PHY Functions */ +int32_t ETH_PHY_WriteReg(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t u16Value); +int32_t ETH_PHY_ReadReg(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t *pu16Value); +int32_t ETH_PHY_LoopBackCmd(stc_eth_handle_t *pstcEthHandle, en_functional_state_t enNewState); + +/* MAC Functions */ +void ETH_MAC_DeInit(void); +int32_t ETH_MAC_Init(stc_eth_handle_t *pstcEthHandle, const stc_eth_mac_init_t *pstcMacInit); +int32_t ETH_MAC_StructInit(stc_eth_mac_init_t *pstcMacInit); +void ETH_MAC_SetDuplexSpeed(uint32_t u32Mode, uint32_t u32Speed); +void ETH_MAC_SetHashTable(uint32_t u32HashHigh, uint32_t u32HashLow); +void ETH_MAC_SetTxVlanTagValue(uint16_t u16TxTag); +void ETH_MAC_SetRxVlanTagValue(uint16_t u16RxTag); +void ETH_MAC_SetRxVlanHashTable(uint16_t u16HashValue); +void ETH_MAC_LoopBackCmd(en_functional_state_t enNewState); +void ETH_MAC_GeneratePauseCtrlFrame(void); +void ETH_MAC_BackPressureCmd(en_functional_state_t enNewState); +void ETH_MAC_TransCmd(en_functional_state_t enNewState); +void ETH_MAC_ReceiveCmd(en_functional_state_t enNewState); +void ETH_MAC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t ETH_MAC_GetIntStatus(uint32_t u32Flag); +en_flag_status_t ETH_MAC_GetFlowControlStatus(void); + +/* MAC Address Functions */ +void ETH_MACADDR_DeInit(uint32_t u32Index); +int32_t ETH_MACADDR_Init(uint32_t u32Index, const stc_eth_mac_addr_config_t *pstcMacAddrInit); +int32_t ETH_MACADDR_StructInit(stc_eth_mac_addr_config_t *pstcMacAddrInit); +int32_t ETH_MACADDR_SetAddr(uint32_t u32Index, uint8_t au8Addr[]); +int32_t ETH_MACADDR_GetAddr(uint32_t u32Index, uint8_t au8Addr[]); +void ETH_MACADDR_SetFilterMode(uint32_t u32Index, uint32_t u32Mode); +void ETH_MACADDR_SetFilterMask(uint32_t u32Index, uint32_t u32Mask); + +/* MAC L3L4 Filter Functions */ +void ETH_MAC_L3L4FilterDeInit(void); +int32_t ETH_MAC_L3L4FilterInit(const stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit); +int32_t ETH_MAC_L3L4FilterStructInit(stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit); +void ETH_MAC_L3L4FilterCmd(en_functional_state_t enNewState); +void ETH_MAC_SetPortFilterProtocol(uint32_t u32Protocol); +void ETH_MAC_SetDestPortFilterValue(uint16_t u16Port); +void ETH_MAC_SetSrcPortFilterValue(uint16_t u16Port); +void ETH_MAC_SetAddrFilterProtocol(uint32_t u32Protocol); +void ETH_MAC_SetIpv4DestAddrFilterValue(uint32_t u32Addr); +void ETH_MAC_SetIpv4SrcAddrFilterValue(uint32_t u32Addr); +int32_t ETH_MAC_SetIpv6AddrFilterValue(const uint32_t au32Addr[]); + +/* DMA Functions */ +void ETH_DMA_DeInit(void); +int32_t ETH_DMA_Init(const stc_eth_dma_init_t *pstcDmaInit); +int32_t ETH_DMA_StructInit(stc_eth_dma_init_t *pstcDmaInit); +int32_t ETH_DMA_SoftwareReset(void); +void ETH_DMA_ResumeTrans(void); +void ETH_DMA_ResumeReceive(void); +void ETH_DMA_SetTransPriorityRatio(uint32_t u32Ratio); +void ETH_DMA_SetRxWatchdogCounter(uint8_t u8Value); +int32_t ETH_DMA_FlushTransFIFO(void); +void ETH_DMA_TransCmd(en_functional_state_t enNewState); +void ETH_DMA_ReceiveCmd(en_functional_state_t enNewState); +void ETH_DMA_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t ETH_DMA_GetStatus(uint32_t u32Flag); +void ETH_DMA_ClearStatus(uint32_t u32Flag); +uint32_t ETH_DMA_GetErrorStatus(void); +uint32_t ETH_DMA_GetTransStatus(void); +uint32_t ETH_DMA_GetReceiveStatus(void); +en_flag_status_t ETH_DMA_GetOvfStatus(uint32_t u32Flag); +uint32_t ETH_DMA_GetOvfMissFrameCount(void); +uint32_t ETH_DMA_GetBufUnavailableMissFrameCount(void); +uint32_t ETH_DMA_GetCurrentTxDescAddr(void); +uint32_t ETH_DMA_GetCurrentRxDescAddr(void); +uint32_t ETH_DMA_GetCurrentTxBufAddr(void); +uint32_t ETH_DMA_GetCurrentRxBufAddr(void); + +/* DMA descriptor Functions */ +int32_t ETH_DMA_TxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcTxDescTab[], + const uint8_t au8TxBuf[], uint32_t u32TxBufCnt); +int32_t ETH_DMA_RxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcRxDescTab[], + const uint8_t au8RxBuf[], uint32_t u32RxBufCnt); +int32_t ETH_DMA_SetTransFrame(stc_eth_handle_t *pstcEthHandle, uint32_t u32FrameLen); +int32_t ETH_DMA_GetReceiveFrame(stc_eth_handle_t *pstcEthHandle); +int32_t ETH_DMA_GetReceiveFrame_Int(stc_eth_handle_t *pstcEthHandle); +int32_t ETH_DMA_SetTxDescOwn(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Owner); +int32_t ETH_DMA_SetTxDescBufSize(stc_eth_dma_desc_t *pstcTxDesc, uint8_t u8BufNum, uint32_t u32BufSize); +int32_t ETH_DMA_TxDescChecksumInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32ChecksumMode); +int32_t ETH_DMA_TxDescVlanInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32VlanMode); +int32_t ETH_DMA_TxDescSrcAddrInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Mode); +int32_t ETH_DMA_TxDescCrcCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState); +int32_t ETH_DMA_TxDescPadCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState); +int32_t ETH_DMA_TxDescTimestamp(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState); +int32_t ETH_DMA_TxDescReplaceCrcCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState); +int32_t ETH_DMA_TxDescIntCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState); +en_flag_status_t ETH_DMA_GetTxDescStatus(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Flag); +int32_t ETH_DMA_GetTxDescCollisionCount(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32Count); +int32_t ETH_DMA_GetTxDescTimeStamp(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32High, uint32_t *pu32Low); +int32_t ETH_DMA_SetRxDescOwn(stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Owner); +int32_t ETH_DMA_RxDescIntCmd(stc_eth_dma_desc_t *pstcRxDesc, en_functional_state_t enNewState); +en_flag_status_t ETH_DMA_GetRxDescStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag); +en_flag_status_t ETH_DMA_GetRxDescExtendStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag); +int32_t ETH_DMA_GetRxDescPayloadType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32PayloadType); +int32_t ETH_DMA_GetRxDescDatagramType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32DatagramType); +int32_t ETH_DMA_GetRxDescFrameLen(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32FrameLen); +int32_t ETH_DMA_GetRxDescBufSize(const stc_eth_dma_desc_t *pstcRxDesc, uint8_t u8BufNum, uint32_t *pu32BufSize); +int32_t ETH_DMA_GetRxDescTimeStamp(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32High, uint32_t *pu32Low); + +/* MAC PMT Functions */ +int32_t ETH_PMT_ResetWakeupFramePointer(void); +int32_t ETH_PMT_WriteWakeupFrameReg(const uint32_t au32RegBuf[]); +void ETH_PMT_ForwardWakeupFrameCmd(en_functional_state_t enNewState); +void ETH_PMT_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +int32_t ETH_PMT_EnterPowerDown(void); +en_flag_status_t ETH_PMT_GetStatus(uint32_t u32Flag); +uint8_t ETH_PMT_GetWakeupFramePointerIndex(void); + +/* MMC Functions */ +int32_t ETH_MMC_DeInit(void); +int32_t ETH_MMC_Init(const stc_eth_mmc_init_t *pstcMmcInit); +int32_t ETH_MMC_StructInit(stc_eth_mmc_init_t *pstcMmcInit); +int32_t ETH_MMC_CounterReset(void); +void ETH_MMC_ResetAfterReadCmd(en_functional_state_t enNewState); +void ETH_MMC_Cmd(en_functional_state_t enNewState); +void ETH_MMC_TxIntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void ETH_MMC_RxIntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t ETH_MMC_GetTxStatus(uint32_t u32Flag); +en_flag_status_t ETH_MMC_GetRxStatus(uint32_t u32Flag); +uint32_t ETH_MMC_GetReg(uint32_t u32Reg); + +/* PTP Functions */ +void ETH_PTP_DeInit(void); +int32_t ETH_PTP_Init(const stc_eth_ptp_init_t *pstcPtpInit); +int32_t ETH_PTP_StructInit(stc_eth_ptp_init_t *pstcPtpInit); +void ETH_PTP_SetSnapDatagramType(uint32_t u32DatagramType); +void ETH_PTP_SetSnapFrameType(uint32_t u32FrameType); +uint32_t ETH_PTP_GetSnapFrameType(void); +void ETH_PTP_SetCalibMode(uint32_t u32CalibMode); +int32_t ETH_PTP_UpdateBasicAddend(void); +int32_t ETH_PTP_UpdateSysTime(void); +int32_t ETH_PTP_SysTimeInit(void); +int32_t ETH_PTP_GetSysTime(uint32_t *pu32Sec, uint32_t *pu32Subsec); +void ETH_PTP_SetBasicAddend(uint32_t u32BasicAddend, uint8_t u8SubsecAddend); +int32_t ETH_PTP_GetBasicAddend(uint32_t *pu32BasicAddend, uint8_t *pu8SubsecAddend); +void ETH_PTP_SetUpdateTime(uint32_t u32Sign, uint32_t u32Sec, uint32_t u32Subsec); +void ETH_PTP_Cmd(en_functional_state_t enNewState); +void ETH_PTP_IntCmd(en_functional_state_t enNewState); +en_flag_status_t ETH_PTP_GetStatus(uint32_t u32Flag); + +/* PTP PPS Functions */ +void ETH_PPS_DeInit(uint8_t u8Ch); +int32_t ETH_PPS_Init(uint8_t u8Ch, const stc_eth_pps_config_t *pstcPpsInit); +int32_t ETH_PPS_StructInit(stc_eth_pps_config_t *pstcPpsInit); +void ETH_PPS_SetTargetTime(uint8_t u8Ch, uint32_t u32Sec, uint32_t u32Subsec); +void ETH_PPS_SetTriggerFunc(uint8_t u8Ch, uint32_t u32Func); +void ETH_PPS_SetPps0OutputMode(uint32_t u32Mode); +void ETH_PPS_SetPps0OutputFreq(uint32_t u32Freq); + +/** + * @} + */ + +#endif /* LL_ETH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ETH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h new file mode 100644 index 0000000000..55b6b1ae10 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h @@ -0,0 +1,233 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.h + * @brief This file contains all the functions prototypes of the Event Port + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EVENT_PORT_H__ +#define __HC32_LL_EVENT_PORT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EVENT_PORT + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EP_Global_Types Event Port Global Types + * @{ + */ + +/** + * @brief Event Pin Set and Reset enumeration + */ +typedef enum { + EVT_PIN_RESET = 0U, /*!< Pin reset */ + EVT_PIN_SET = 1U /*!< Pin set */ +} en_ep_state_t; + +typedef struct { + uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */ + en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */ + uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */ + uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */ + uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */ +} stc_ep_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Global_Macros Event Port Global Macros + * @{ + */ + +/** + * @defgroup EP_Port_source EP Port Source + * @{ + */ +#define EVT_PORT_1 (0U) /*!< Event port 1 */ +#define EVT_PORT_2 (1U) /*!< Event port 2 */ +#define EVT_PORT_3 (2U) /*!< Event port 3 */ +#define EVT_PORT_4 (3U) /*!< Event port 4 */ +/** + * @} + */ + +/** + * @defgroup EP_pins_define EP Pin Source + * @{ + */ +#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */ +#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */ +#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */ +#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */ +#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */ +#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */ +#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */ +#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */ +#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */ +#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */ +#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */ +#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */ +#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */ +#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */ +#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */ +#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */ +#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */ +#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */ +/** + * @} + */ + +/** + * @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection + * @{ + */ +#define EP_DIR_IN (0UL) /*!< EP input */ +#define EP_DIR_OUT (1UL) /*!< EP output */ +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Sel Event Port Filter Function Selection + * @{ + */ +#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */ + +#define EP_FILTER_ON (1UL) /*!< EP filter function ON */ + +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection + * @{ + */ +#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */ +#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */ +#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */ +#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */ + +/** + * @} + */ + +/** + * @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection + * @{ + */ +#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */ +#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */ +#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */ +#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */ + +/** + * @} + */ + +/** + * @defgroup EP_TriggerOps_Sel Event Port Operation + * @{ + */ +#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */ +#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */ +#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */ +#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EP_Global_Functions + * @{ + */ +void EP_DeInit(void); +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit); + +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit); +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge); +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops); +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadInputPort(uint8_t u8EventPort); +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadOutputPort(uint8_t u8EventPort); +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir); + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h new file mode 100644 index 0000000000..8fd129b4f0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h @@ -0,0 +1,254 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.h + * @brief This file contains all the functions prototypes of the FCG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCG_H__ +#define __HC32_LL_FCG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCG + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Macros FCG Global Macros + * @{ + */ +/** + * @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral + * @{ + */ +#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH) +#define FCG0_PERIPH_SRAM1 (PWC_FCG0_SRAM1) +#define FCG0_PERIPH_SRAM2 (PWC_FCG0_SRAM2) +#define FCG0_PERIPH_SRAM3 (PWC_FCG0_SRAM3) +#define FCG0_PERIPH_SRAM4 (PWC_FCG0_SRAM4) +#define FCG0_PERIPH_SRAMB (PWC_FCG0_SRAMB) +#define FCG0_PERIPH_KEY (PWC_FCG0_KEY) +#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1) +#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2) +#define FCG0_PERIPH_FCM (PWC_FCG0_FCM) +#define FCG0_PERIPH_AOS (PWC_FCG0_AOS) +#define FCG0_PERIPH_CTC (PWC_FCG0_CTC) +#define FCG0_PERIPH_MAU (PWC_FCG0_MAU) +#define FCG0_PERIPH_AES (PWC_FCG0_AES) +#define FCG0_PERIPH_HASH (PWC_FCG0_HASH) +#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG) +#define FCG0_PERIPH_CRC (PWC_FCG0_CRC) +#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1) +#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2) +#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3) +#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4) +#define FCG0_PERIPH_DCU5 (PWC_FCG0_DCU5) +#define FCG0_PERIPH_DCU6 (PWC_FCG0_DCU6) +#define FCG0_PERIPH_DCU7 (PWC_FCG0_DCU7) +#define FCG0_PERIPH_DCU8 (PWC_FCG0_DCU8) +/** + * @} + */ + +/** + * @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral + * @{ + */ +#define FCG1_PERIPH_CAN1 (PWC_FCG1_CAN1) +#define FCG1_PERIPH_CAN2 (PWC_FCG1_CAN2) +#define FCG1_PERIPH_ETHMAC (PWC_FCG1_ETHMAC) +#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI) +#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1) +#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2) +#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3) +#define FCG1_PERIPH_I2C4 (PWC_FCG1_I2C4) +#define FCG1_PERIPH_I2C5 (PWC_FCG1_I2C5) +#define FCG1_PERIPH_I2C6 (PWC_FCG1_I2C6) +#define FCG1_PERIPH_SDIOC1 (PWC_FCG1_SDIOC1) +#define FCG1_PERIPH_SDIOC2 (PWC_FCG1_SDIOC2) +#define FCG1_PERIPH_I2S1 (PWC_FCG1_I2S1) +#define FCG1_PERIPH_I2S2 (PWC_FCG1_I2S2) +#define FCG1_PERIPH_I2S3 (PWC_FCG1_I2S3) +#define FCG1_PERIPH_I2S4 (PWC_FCG1_I2S4) +#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1) +#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2) +#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3) +#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4) +#define FCG1_PERIPH_SPI5 (PWC_FCG1_SPI5) +#define FCG1_PERIPH_SPI6 (PWC_FCG1_SPI6) +#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS) +#define FCG1_PERIPH_USBHS (PWC_FCG1_USBHS) +#define FCG1_PERIPH_FMAC1 (PWC_FCG1_FMAC1) +#define FCG1_PERIPH_FMAC2 (PWC_FCG1_FMAC2) +#define FCG1_PERIPH_FMAC3 (PWC_FCG1_FMAC3) +#define FCG1_PERIPH_FMAC4 (PWC_FCG1_FMAC4) +/** + * @} + */ + +/** + * @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral + * @{ + */ +#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TMR6_1) +#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TMR6_2) +#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TMR6_3) +#define FCG2_PERIPH_TMR6_4 (PWC_FCG2_TMR6_4) +#define FCG2_PERIPH_TMR6_5 (PWC_FCG2_TMR6_5) +#define FCG2_PERIPH_TMR6_6 (PWC_FCG2_TMR6_6) +#define FCG2_PERIPH_TMR6_7 (PWC_FCG2_TMR6_7) +#define FCG2_PERIPH_TMR6_8 (PWC_FCG2_TMR6_8) +#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TMR4_1) +#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TMR4_2) +#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TMR4_3) +#define FCG2_PERIPH_HRPWM (PWC_FCG2_HRPWM) +#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TMR0_1) +#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TMR0_2) +#define FCG2_PERIPH_EMB (PWC_FCG2_EMB) +#define FCG2_PERIPH_TMR2_1 (PWC_FCG2_TMR2_1) +#define FCG2_PERIPH_TMR2_2 (PWC_FCG2_TMR2_2) +#define FCG2_PERIPH_TMR2_3 (PWC_FCG2_TMR2_3) +#define FCG2_PERIPH_TMR2_4 (PWC_FCG2_TMR2_4) +#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TMRA_1) +#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TMRA_2) +#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TMRA_3) +#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TMRA_4) +#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TMRA_5) +#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TMRA_6) +#define FCG2_PERIPH_TMRA_7 (PWC_FCG2_TMRA_7) +#define FCG2_PERIPH_TMRA_8 (PWC_FCG2_TMRA_8) +#define FCG2_PERIPH_TMRA_9 (PWC_FCG2_TMRA_9) +#define FCG2_PERIPH_TMRA_10 (PWC_FCG2_TMRA_10) +#define FCG2_PERIPH_TMRA_11 (PWC_FCG2_TMRA_11) +#define FCG2_PERIPH_TMRA_12 (PWC_FCG2_TMRA_12) +/** + * @} + */ + +/** + * @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral + * @{ + */ +#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1) +#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2) +#define FCG3_PERIPH_ADC3 (PWC_FCG3_ADC3) +#define FCG3_PERIPH_CMBIAS (PWC_FCG3_CMBIAS) +#define FCG3_PERIPH_DAC1 (PWC_FCG3_DAC1) +#define FCG3_PERIPH_DAC2 (PWC_FCG3_DAC2) +#define FCG3_PERIPH_CMP1_2 (PWC_FCG3_CMP1) +#define FCG3_PERIPH_CMP3_4 (PWC_FCG3_CMP2) +#define FCG3_PERIPH_OTS (PWC_FCG3_OTS) +#define FCG3_PERIPH_DVP (PWC_FCG3_DVP) +#define FCG3_PERIPH_SMC (PWC_FCG3_SMC) +#define FCG3_PERIPH_DMC (PWC_FCG3_DMC) +#define FCG3_PERIPH_NFC (PWC_FCG3_NFC) +#define FCG3_PERIPH_USART1 (PWC_FCG3_USART1) +#define FCG3_PERIPH_USART2 (PWC_FCG3_USART2) +#define FCG3_PERIPH_USART3 (PWC_FCG3_USART3) +#define FCG3_PERIPH_USART4 (PWC_FCG3_USART4) +#define FCG3_PERIPH_USART5 (PWC_FCG3_USART5) +#define FCG3_PERIPH_USART6 (PWC_FCG3_USART6) +#define FCG3_PERIPH_USART7 (PWC_FCG3_USART7) +#define FCG3_PERIPH_USART8 (PWC_FCG3_USART8) +#define FCG3_PERIPH_USART9 (PWC_FCG3_USART9) +#define FCG3_PERIPH_USART10 (PWC_FCG3_USART10) +/** + * @} + */ + +/** + * @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask + * @{ + */ +#define FCG_FCG0_PERIPH_MASK (0xFFFFE4F1UL) +#define FCG_FCG1_PERIPH_MASK (0x0FFFFFFFUL) +#define FCG_FCG2_PERIPH_MASK (0xFFFFBFFFUL) +#define FCG_FCG3_PERIPH_MASK (0x3FF7933FUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCG_Global_Functions + * @{ + */ + +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); + +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h new file mode 100644 index 0000000000..fbba2e1c50 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h @@ -0,0 +1,294 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.h + * @brief This file contains all the functions prototypes of the FCM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCM_H__ +#define __HC32_LL_FCM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCM + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Types FCM Global Types + * @{ + */ +/** + * @brief FCM Init structure definition + */ +typedef struct { + uint16_t u16LowerLimit; /*!< FCM lower limit value */ + uint16_t u16UpperLimit; /*!< FCM upper limit value */ + uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */ + uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */ + uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */ + uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */ + uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */ + uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */ + uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */ + uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */ +} stc_fcm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Macros FCM Global Macros + * @{ + */ + +/** + * @defgroup FCM_Target_Clock_Src FCM Target Clock Source + * @{ + */ +#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PLLAP (0x06UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_RTCLRC (0x09UL << FCM_MCCR_MCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Target_Clock_Div FCM Target Clock Division + * @{ + */ +#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config + * @{ + */ +#define FCM_EXT_REF_OFF (0x00UL) +#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge + * @{ + */ +#define FCM_REF_CLK_RISING (0x00UL) +#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0) +#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1) +/** + * @} + */ + +/** + * @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config + * @{ + */ +#define FCM_DIG_FILTER_OFF (0x00UL) +#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0) +#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1) +#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Src FCM Feference Clock Source + * @{ + */ +#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PLLAP (0x16UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_RTCLRC (0x19UL << FCM_RCCR_RCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division + * @{ + */ +#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config + * @{ + */ +#define FCM_ERR_RST_OFF (0x00UL) +#define FCM_ERR_RST_ON (FCM_RIER_ERRE) +/** + * @} + */ + +/** + * @defgroup FCM_Exception_Type FCM Exception Type + * @{ + */ +#define FCM_EXP_TYPE_INT (0x00UL) +#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS) +/** + * @} + */ + +/** + * @defgroup FCM_Int_Type FCM Interrupt Type + * @{ + */ +#define FCM_INT_OVF (FCM_RIER_OVFIE) +#define FCM_INT_END (FCM_RIER_MENDIE) +#define FCM_INT_ERR (FCM_RIER_ERRIE) +/** + * @} + */ + +/** + * @defgroup FCM_Flag_Sel FCM Status Flag Selection + * @{ + */ +#define FCM_FLAG_ERR (FCM_SR_ERRF) +#define FCM_FLAG_END (FCM_SR_MENDF) +#define FCM_FLAG_OVF (FCM_SR_OVF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCM_Global_Functions + * @{ + */ + +/** + * @brief Set FCM upper limit value. + * @param u16Limit + * @retval None. + */ +__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->UVR, u16Limit); +} + +/** + * @brief Set FCM lower limit value. + * @param u16Limit + * @retval None + */ +__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->LVR, u16Limit); +} + +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit); +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit); +void FCM_DeInit(void); +uint16_t FCM_GetCountValue(void); +void FCM_SetUpperLimit(uint16_t u16Limit); +void FCM_SetLowerLimit(uint16_t u16Limit); +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div); +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div); +en_flag_status_t FCM_GetStatus(uint32_t u32Flag); +void FCM_ClearStatus(uint32_t u32Flag); +void FCM_ResetCmd(en_functional_state_t enNewState); +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void FCM_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fmac.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fmac.h new file mode 100644 index 0000000000..8775a61b29 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fmac.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file hc32_ll_fmac.h + * @brief This file contains all the functions prototypes of the FMAC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FMAC_H__ +#define __HC32_LL_FMAC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FMAC + * @{ + */ + +#if (LL_FMAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FMAC_Global_Types FMAC Global Types + * @{ + */ + +/** + * @brief FMAC configuration structure + */ +typedef struct { + uint32_t u32Stage; /*!< FMAC filter stage number config. + This parameter can be a value of @ref FMAC_Filter_Stage.*/ + uint32_t u32Shift; /*!< FMAC filter result right shift bits. + This parameter can be a value of @ref FMAC_Filter_Shift.*/ + int16_t *pi16Factor; /*!< FMAC filter factor config. FIR factor array */ + uint32_t u32IntCmd; /*!< Enable or disable FMAC interrupt. + This parameter can be a value of @ref FMAC_Interrupt_Selection.*/ +} stc_fmac_init_t; + +/** + * @brief FMAC result definition + */ +typedef struct { + uint32_t u32ResultHigh; /*!< The high value of the result. */ + uint32_t u32ResultLow; /*!< The low value of the result. */ +} stc_fmac_result_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup FMAC_Global_Macros FMAC Global Macros + * @{ + */ + +/** + * @defgroup FMAC_Interrupt_Selection FMAC Interrupt Selection + * @{ + */ +#define FMAC_INT_ENABLE (FMAC_IER_INTEN) +#define FMAC_INT_DISABLE (0x0UL) +/** + * @} + */ + +/** + * @defgroup FMAC_Filter_Shift FMAC Filter Shift + * @{ + */ +#define FMAC_FIR_SHIFT_0BIT (0U) +#define FMAC_FIR_SHIFT_1BIT (1U) +#define FMAC_FIR_SHIFT_2BIT (2U) +#define FMAC_FIR_SHIFT_3BIT (3U) +#define FMAC_FIR_SHIFT_4BIT (4U) +#define FMAC_FIR_SHIFT_5BIT (5U) +#define FMAC_FIR_SHIFT_6BIT (6U) +#define FMAC_FIR_SHIFT_7BIT (7U) +#define FMAC_FIR_SHIFT_8BIT (8U) +#define FMAC_FIR_SHIFT_9BIT (9U) +#define FMAC_FIR_SHIFT_10BIT (10U) +#define FMAC_FIR_SHIFT_11BIT (11U) +#define FMAC_FIR_SHIFT_12BIT (12U) +#define FMAC_FIR_SHIFT_13BIT (13U) +#define FMAC_FIR_SHIFT_14BIT (14U) +#define FMAC_FIR_SHIFT_15BIT (15U) +#define FMAC_FIR_SHIFT_16BIT (16U) +#define FMAC_FIR_SHIFT_17BIT (17U) +#define FMAC_FIR_SHIFT_18BIT (18U) +#define FMAC_FIR_SHIFT_19BIT (19U) +#define FMAC_FIR_SHIFT_20BIT (20U) +#define FMAC_FIR_SHIFT_21BIT (21U) +/** + * @} + */ + +/** + * @defgroup FMAC_Filter_Stage FMAC Filter Stage + * @{ + */ +#define FMAC_FIR_STAGE_0 (0U) +#define FMAC_FIR_STAGE_1 (1U) +#define FMAC_FIR_STAGE_2 (2U) +#define FMAC_FIR_STAGE_3 (3U) +#define FMAC_FIR_STAGE_4 (4U) +#define FMAC_FIR_STAGE_5 (5U) +#define FMAC_FIR_STAGE_6 (6U) +#define FMAC_FIR_STAGE_7 (7U) +#define FMAC_FIR_STAGE_8 (8U) +#define FMAC_FIR_STAGE_9 (9U) +#define FMAC_FIR_STAGE_10 (10U) +#define FMAC_FIR_STAGE_11 (11U) +#define FMAC_FIR_STAGE_12 (12U) +#define FMAC_FIR_STAGE_13 (13U) +#define FMAC_FIR_STAGE_14 (14U) +#define FMAC_FIR_STAGE_15 (15U) +#define FMAC_FIR_STAGE_16 (16U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FMAC_Global_Functions + * @{ + */ +int32_t FMAC_StructInit(stc_fmac_init_t *pstcFmacInit); +void FMAC_DeInit(CM_FMAC_TypeDef *FMACx); +int32_t FMAC_Init(CM_FMAC_TypeDef *FMACx, const stc_fmac_init_t *pstcFmacInit); +void FMAC_Cmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState); +void FMAC_SetResultShift(CM_FMAC_TypeDef *FMACx, uint32_t u32ShiftNum); +void FMAC_SetStageFactor(CM_FMAC_TypeDef *FMACx, uint32_t u32FilterStage, int16_t *pi16Factor); +void FMAC_IntCmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState); +void FMAC_FIRInput(CM_FMAC_TypeDef *FMACx, int16_t i16Factor); +en_flag_status_t FMAC_GetStatus(const CM_FMAC_TypeDef *FMACx); +int32_t FMAC_GetResult(const CM_FMAC_TypeDef *FMACx, stc_fmac_result_t *pstcResult); +/** + * @} + */ + +#endif /* LL_FMAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FMAC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h new file mode 100644 index 0000000000..e5a5a74b50 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h @@ -0,0 +1,485 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.h + * @brief This file contains all the functions prototypes of the GPIO driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_GPIO_H__ +#define __HC32_LL_GPIO_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_GPIO + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Types GPIO Global Types + * @{ + */ + +/** + * @brief GPIO Pin Set and Reset enumeration + */ +typedef enum { + PIN_RESET = 0U, /*!< Pin reset */ + PIN_SET = 1U /*!< Pin set */ +} en_pin_state_t; + +/** + * @brief GPIO Init structure definition + */ +typedef struct { + uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */ + uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */ + uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */ + uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */ + uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */ + uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel */ + uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */ + uint16_t u16PinInputType; /*!< Input type setting, @ref GPIO_PinInType_Sel */ + uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */ +} stc_gpio_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Macros GPIO Global Macros + * @{ + */ + +/** + * @defgroup GPIO_Pins_Define GPIO Pin Source + * @{ + */ +#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */ +#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */ +#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */ +#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */ +#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */ +#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */ +#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */ +#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */ + +#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */ +#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */ +#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */ +#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */ +#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */ +#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */ +#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */ +#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */ + +/** + * @} + */ + +/** + * @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product + * @{ + */ +#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/ +#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/ +#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/ +#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/ +#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/ +#define GPIO_PIN_F_ALL (0xFFFFU) /*!< Pin F all*/ +#define GPIO_PIN_G_ALL (0xFFFFU) /*!< Pin G all*/ +#define GPIO_PIN_H_ALL (0xFFFFU) /*!< Pin H all*/ +#define GPIO_PIN_I_ALL (0x3FFFU) /*!< Pin I all*/ + +/** + * @} + */ + +/** + * @defgroup GPIO_Port_Source GPIO Port Source + * @{ + */ +#define GPIO_PORT_A (0x00U) /*!< Port A selected */ +#define GPIO_PORT_B (0x01U) /*!< Port B selected */ +#define GPIO_PORT_C (0x02U) /*!< Port C selected */ +#define GPIO_PORT_D (0x03U) /*!< Port D selected */ +#define GPIO_PORT_E (0x04U) /*!< Port E selected */ +#define GPIO_PORT_F (0x05U) /*!< Port F selected */ +#define GPIO_PORT_G (0x06U) /*!< Port G selected */ +#define GPIO_PORT_H (0x07U) /*!< Port H selected */ +#define GPIO_PORT_I (0x08U) /*!< Port I selected */ + +/** + * @} + */ + +/** + * @defgroup GPIO_Function_Sel GPIO Function Selection + * @{ + */ +#define GPIO_FUNC_0 (0U) +#define GPIO_FUNC_1 (1U) +#define GPIO_FUNC_2 (2U) +#define GPIO_FUNC_3 (3U) +#define GPIO_FUNC_4 (4U) +#define GPIO_FUNC_5 (5U) +#define GPIO_FUNC_6 (6U) +#define GPIO_FUNC_7 (7U) + +#define GPIO_FUNC_8 (8U) +#define GPIO_FUNC_9 (9U) +#define GPIO_FUNC_10 (10U) +#define GPIO_FUNC_11 (11U) +#define GPIO_FUNC_12 (12U) +#define GPIO_FUNC_13 (13U) +#define GPIO_FUNC_14 (14U) +#define GPIO_FUNC_15 (15U) + +#define GPIO_FUNC_16 (16U) +#define GPIO_FUNC_17 (17U) +#define GPIO_FUNC_18 (18U) +#define GPIO_FUNC_19 (19U) +#define GPIO_FUNC_20 (20U) + +#define GPIO_FUNC_32 (32U) +#define GPIO_FUNC_33 (33U) +#define GPIO_FUNC_34 (34U) +#define GPIO_FUNC_35 (35U) +#define GPIO_FUNC_36 (36U) +#define GPIO_FUNC_37 (37U) +#define GPIO_FUNC_38 (38U) +#define GPIO_FUNC_39 (39U) +#define GPIO_FUNC_40 (40U) +#define GPIO_FUNC_41 (41U) +#define GPIO_FUNC_42 (42U) +#define GPIO_FUNC_43 (43U) +#define GPIO_FUNC_44 (44U) +#define GPIO_FUNC_45 (45U) +#define GPIO_FUNC_46 (46U) +#define GPIO_FUNC_47 (47U) +#define GPIO_FUNC_48 (48U) +#define GPIO_FUNC_49 (49U) +#define GPIO_FUNC_50 (50U) +#define GPIO_FUNC_51 (51U) +#define GPIO_FUNC_52 (52U) +#define GPIO_FUNC_53 (53U) +#define GPIO_FUNC_54 (54U) +#define GPIO_FUNC_55 (55U) +#define GPIO_FUNC_56 (56U) +#define GPIO_FUNC_57 (57U) +#define GPIO_FUNC_58 (58U) +#define GPIO_FUNC_59 (59U) + +#define GPIO_FUNC_60 (60U) +#define GPIO_FUNC_61 (61U) +#define GPIO_FUNC_62 (62U) +#define GPIO_FUNC_63 (63U) +/** + * @} + */ + +/** + * @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection + * @{ + */ +#define GPIO_PIN_TCK (0x01U) +#define GPIO_PIN_TMS (0x02U) +#define GPIO_PIN_TDO (0x04U) +#define GPIO_PIN_TDI (0x08U) +#define GPIO_PIN_TRST (0x10U) +#define GPIO_PIN_DEBUG_JTAG (0x1FU) + +#define GPIO_PIN_SWCLK (0x01U) +#define GPIO_PIN_SWDIO (0x02U) +#define GPIO_PIN_SWO (0x04U) +#define GPIO_PIN_DEBUG_SWD (0x07U) +#define GPIO_PIN_DEBUG (0x1FU) + +/** + * @} + */ + +/** + * @defgroup GPIO_Hprwm_Pin_Sel GPIO Hrpwm Pin Selection + * @{ + */ +/** + * @} + */ + +/** + * @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection + * @{ + */ +#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS) + +#define GPIO_RD_WAIT4 (0x04U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT5 (0x05U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT6 (0x06U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT7 (0x07U << GPIO_PCCR_RDWT_POS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection + * @{ + */ +#define PIN_STAT_RST (0U) +#define PIN_STAT_SET (GPIO_PCR_POUT) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection + * @{ + */ +#define PIN_DIR_IN (0U) +#define PIN_DIR_OUT (GPIO_PCR_POUTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection + * @{ + */ +#define PIN_OUT_TYPE_CMOS (0U) +#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection + * @{ + */ +#define PIN_LOW_DRV (0U) +#define PIN_MID_DRV (GPIO_PCR_DRV_0) +#define PIN_HIGH_DRV (GPIO_PCR_DRV_1) + +/** + * @} + */ + +/** + * @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection + * @{ + */ +#define PIN_LATCH_OFF (0U) +#define PIN_LATCH_ON (GPIO_PCR_LTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection + * @{ + */ +#define PIN_PU_OFF (0U) +#define PIN_PU_ON (GPIO_PCR_PUU) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPD_Sel GPIO Pin Internal Pull-Down Resistor Selection + * @{ + */ +#define PIN_PD_OFF (0U) +#define PIN_PD_ON (GPIO_PCR_PUD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInputSw_Sel GPIO Pin Input Switch Resistor Selection + * @{ + */ +#define PIN_IN_SW_OFF (0U) +#define PIN_IN_SW_ON (GPIO_PCR_PINAE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection + * @{ + */ +#define PIN_INVT_OFF (0U) +#define PIN_INVT_ON (GPIO_PCR_INVE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInType_Sel GPIO Pin Input Type Selection + * @{ + */ +#define PIN_IN_TYPE_SMT (0U) +#define PIN_IN_TYPE_CMOS (GPIO_PCR_CINSEL) +/** + * @} + */ + +/** + * @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection + * @{ + */ +#define PIN_EXTINT_OFF (0U) +#define PIN_EXTINT_ON (GPIO_PCR_INTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection + * @{ + */ +#define PIN_ATTR_DIGITAL (0U) +#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable + * @{ + */ +#define PIN_SUBFUNC_DISABLE (0U) +#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE) +/** + * @} + */ + +/** + * @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key + * @{ + */ +#define GPIO_REG_LOCK_KEY (0xA500U) +#define GPIO_REG_UNLOCK_KEY (0xA501U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GPIO_Global_Functions + * @{ + */ +/** + * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Lock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY); +} + +/** + * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Unlock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY); +} + +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit); +void GPIO_DeInit(void); +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit); +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState); +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func); +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_SetSubFunc(uint8_t u8Func); +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait); +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState); +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadInputPort(uint8_t u8Port); +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadOutputPort(uint8_t u8Port); +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal); +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin); + +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h new file mode 100644 index 0000000000..08cfa67f5e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h @@ -0,0 +1,214 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.h + * @brief This file contains all the functions prototypes of the HASH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_HASH_H__ +#define __HC32_LL_HASH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HASH + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Global_Macros HASH Global Macros + * @{ + */ + +/** + * @defgroup HASH_Mode HASH Mode + * @{ + */ +#define HASH_MD_SHA256 (0x0UL) /*!< SHA256 operating mode */ +#define HASH_MD_HMAC (HASH_CR_MODE_0) /*!< HMAC operating mode */ +/** + * @} + */ + +/** + * @defgroup HASH_Key_Size_Mode HASH Key Size Mode + * @{ + */ +#define HASH_KEY_MD_SHORT_SIZE (0x0UL) /*!< Key length <= 64 Bytes */ +#define HASH_KEY_MD_LONG_SIZE (HASH_CR_LKEY) /*!< Key length > 64 Bytes */ +/** + * @} + */ + +/** + * @defgroup HASH_Interrupt HASH Interrupt + * @{ + */ +#define HASH_INT_GRP (HASH_CR_HEIE) /*!< A set of data operations complete interrupt */ +#define HASH_INT_ALL_CPLT (HASH_CR_HCIE) /*!< All data operations complete interrupt */ +#define HASH_INT_ALL (HASH_INT_GRP | HASH_INT_ALL_CPLT) +/** + * @} + */ + +/** + * @defgroup HASH_Msg_Group HASH Messages Group + * @{ + */ +#define HASH_MSG_GRP_FIRST (HASH_CR_FST_GRP) /*!< The first group of messages or keys */ +#define HASH_MSG_GRP_END (HASH_CR_KMSG_END) /*!< The last group of messages or keys */ +#define HASH_MSG_GRP_ONLY_ONE (HASH_CR_FST_GRP | \ + HASH_CR_KMSG_END) /*!< Only one set of message or key */ +/** + * @} + */ + +/** + * @defgroup HASH_Status_Flag HASH Status Flag + * @{ + */ +#define HASH_FLAG_START (HASH_CR_START) /*!< Operation in progress */ +#define HASH_FLAG_BUSY (HASH_CR_BUSY) /*!< HASH in operation */ +#define HASH_FLAG_CYC_END (HASH_CR_CYC_END) /*!< key or message operation completed */ +#define HASH_FLAG_HMAC_END (HASH_CR_HMAC_END) /*!< HMAC operation completed */ +#define HASH_FLAG_ALL (HASH_FLAG_START | HASH_FLAG_BUSY | \ + HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END) +#define HASH_FLAG_CLR_ALL (HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END) +/** + * @} + */ + +/** + * @defgroup HASH_Trigger_Event HASH Trigger Event + * @{ + */ +#define HASH_TRIG_EVT_DMA1_TC0 (EVT_SRC_DMA1_TC0) /*!< Select the DMA1 ch0 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC1 (EVT_SRC_DMA1_TC1) /*!< Select the DMA1 ch1 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC2 (EVT_SRC_DMA1_TC2) /*!< Select the DMA1 ch2 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC3 (EVT_SRC_DMA1_TC3) /*!< Select the DMA1 ch3 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC4 (EVT_SRC_DMA1_TC4) /*!< Select the DMA1 ch4 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC5 (EVT_SRC_DMA1_TC5) /*!< Select the DMA1 ch5 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC6 (EVT_SRC_DMA1_TC6) /*!< Select the DMA1 ch6 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_TC7 (EVT_SRC_DMA1_TC7) /*!< Select the DMA1 ch7 transfer complete*/ +#define HASH_TRIG_EVT_DMA1_BTC0 (EVT_SRC_DMA1_BTC0) /*!< Select the DMA1 ch0 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC1 (EVT_SRC_DMA1_BTC1) /*!< Select the DMA1 ch1 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC2 (EVT_SRC_DMA1_BTC2) /*!< Select the DMA1 ch2 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC3 (EVT_SRC_DMA1_BTC3) /*!< Select the DMA1 ch3 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC4 (EVT_SRC_DMA1_BTC4) /*!< Select the DMA1 ch4 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC5 (EVT_SRC_DMA1_BTC5) /*!< Select the DMA1 ch5 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC6 (EVT_SRC_DMA1_BTC6) /*!< Select the DMA1 ch6 block transfer complete */ +#define HASH_TRIG_EVT_DMA1_BTC7 (EVT_SRC_DMA1_BTC7) /*!< Select the DMA1 ch7 block transfer complete */ + +#define HASH_TRIG_EVT_DMA2_TC0 (EVT_SRC_DMA2_TC0) /*!< Select the DMA2 ch0 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC1 (EVT_SRC_DMA2_TC1) /*!< Select the DMA2 ch1 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC2 (EVT_SRC_DMA2_TC2) /*!< Select the DMA2 ch2 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC3 (EVT_SRC_DMA2_TC3) /*!< Select the DMA2 ch3 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC4 (EVT_SRC_DMA2_TC4) /*!< Select the DMA2 ch4 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC5 (EVT_SRC_DMA2_TC5) /*!< Select the DMA2 ch5 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC6 (EVT_SRC_DMA2_TC6) /*!< Select the DMA2 ch6 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_TC7 (EVT_SRC_DMA2_TC7) /*!< Select the DMA2 ch7 transfer complete*/ +#define HASH_TRIG_EVT_DMA2_BTC0 (EVT_SRC_DMA2_BTC0) /*!< Select the DMA2 ch0 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC1 (EVT_SRC_DMA2_BTC1) /*!< Select the DMA2 ch1 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC2 (EVT_SRC_DMA2_BTC2) /*!< Select the DMA2 ch2 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC3 (EVT_SRC_DMA2_BTC3) /*!< Select the DMA2 ch3 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC4 (EVT_SRC_DMA2_BTC4) /*!< Select the DMA2 ch4 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC5 (EVT_SRC_DMA2_BTC5) /*!< Select the DMA2 ch5 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC6 (EVT_SRC_DMA2_BTC6) /*!< Select the DMA2 ch6 block transfer complete */ +#define HASH_TRIG_EVT_DMA2_BTC7 (EVT_SRC_DMA2_BTC7) /*!< Select the DMA2 ch7 block transfer complete */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HASH_Global_Functions + * @{ + */ + +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest); + +int32_t HASH_HMAC_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, + const uint8_t *pu8Key, uint32_t u32KeySize, + uint8_t *pu8MsgDigest); + +int32_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState); +en_flag_status_t HASH_GetStatus(uint32_t u32Flag); +int32_t HASH_ClearStatus(uint32_t u32Flag); + +int32_t HASH_SetMode(uint32_t u32HashMode); +int32_t HASH_SetKeySizeMode(uint32_t u32SizeMode); +int32_t HASH_SetMsgGroup(uint32_t u32MsgGroup); +int32_t HASH_Start(void); +void HASH_GetMsgDigest(uint8_t *pu8MsgDigest); + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hrpwm.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hrpwm.h new file mode 100644 index 0000000000..b81337a2e4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hrpwm.h @@ -0,0 +1,139 @@ +/** + ******************************************************************************* + * @file hc32_ll_hrpwm.h + * @brief Head file for HRPWM module. + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_HRPWM_H__ +#define __HC32_LL_HRPWM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HRPWM + * @{ + */ + +#if (LL_HRPWM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HRPWM_Global_Macros HRPWM Global Macros + * @{ + */ + +#define HRPWM_CH_MIN (1UL) +#define HRPWM_CH_MAX (16UL) + +#define HRPWM_CH_DELAY_NUM_MIN (1U) +#define HRPWM_CH_DELAY_NUM_MAX (256U) + +/** + * @defgroup HRPWM_Calibrate_Unit_Define HRPWM Calibrate Unit Define + * @{ + */ +#define HRPWM_CAL_UNIT0 (0x00UL) +#define HRPWM_CAL_UNIT1 (0x01UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HRPWM_Global_Functions + * @{ + */ +/* HRPWM Judge the condition of calibration function */ +en_functional_state_t HRPWM_CondConfirm(void); + +/* Process for getting HRPWM Calibrate function code */ +int32_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t *pu8Code); + +/* HRPWM Calibrate function enable or disable for specified unit */ +void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState); +/* HRPWM Calibrate function status get for specified unit */ +en_functional_state_t HRPWM_GetCalibrateState(uint32_t u32Unit); +/* HRPWM Calibrate code get for specified unit */ +uint8_t HRPWM_GetCalibrateCode(uint32_t u32Unit); + +/* HRPWM function enable or disable for specified channel */ +void HRPWM_ChCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM positive edge adjust enable or disable for specified channel */ +void HRPWM_ChPositiveAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM negative edge adjust enable or disable for specified channel */ +void HRPWM_ChNegativeAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM positive edge adjust delay counts configration for specified channel */ +void HRPWM_ChPositiveAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum); +/* HRPWM negative edge adjust delay counts configration for specified channel */ +void HRPWM_ChNegativeAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum); + +/** + * @} + */ + +#endif /* LL_HRPWM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_HRPWM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h new file mode 100644 index 0000000000..961719119e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h @@ -0,0 +1,319 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.h + * @brief This file contains all the functions prototypes of the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2C_H__ +#define __HC32_LL_I2C_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2C + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2C_Global_Types I2C Global Types + * @{ + */ + +/** + * @brief I2c configuration structure + */ +typedef struct { + uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */ + uint32_t u32Baudrate; /*!< I2C baudrate config */ + uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */ +} stc_i2c_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Macros I2C Global Macros + * @{ + */ + +/** + * @defgroup I2C_Trans_Dir I2C Transfer Direction + * @{ + */ +#define I2C_DIR_TX (0x0U) +#define I2C_DIR_RX (0x1U) +/** + * @} + */ + +/** + * @defgroup I2C_Addr_Config I2C Address Configurate + * @{ + */ +#define I2C_ADDR_DISABLE (0U) +#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN) +#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN) +/** + * @} + */ + +/** + * @defgroup I2C_Clock_Division I2C Clock Division + * @{ + */ +#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */ +#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */ +#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */ +#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */ +#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */ +#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */ +#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */ +#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */ +/** + * @} + */ + +/** + * @defgroup I2C_Address_Num I2C Address Number + * @{ + */ +#define I2C_ADDR0 (0UL) +#define I2C_ADDR1 (1UL) +/** + * @} + */ + +/** + * @defgroup I2C_Ack_Config I2C ACK Configurate + * @{ + */ +#define I2C_ACK (0UL) /*!< Send ACK after date receive */ +#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */ +/** + * @} + */ + +/** + * @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configurate + * @{ + */ +#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN) +#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN) +#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN) +#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** + * @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock + * @{ + */ +#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */ +#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */ +#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */ +#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */ +/** + * @} + */ + +/** + * @defgroup I2C_Flag I2C Flag + * @{ + */ +#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */ +#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */ +#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */ +#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */ +#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */ +#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */ +#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */ +#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */ +#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */ +#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */ +#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */ +#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */ +#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */ +#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */ +#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */ +#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */ +#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */ +#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */ + +#define I2C_FLAG_CLR_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 \ + | I2C_FLAG_TX_CPLT | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY \ + | I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF \ + | I2C_FLAG_GENERAL_CALL | I2C_FLAG_SMBUS_DEFAULT_MATCH \ + | I2C_FLAG_SMBUS_HOST_MATCH | I2C_FLAG_SMBUS_ALARM_MATCH) +#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_TX_CPLT \ + | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY | I2C_FLAG_ARBITRATE_FAIL\ + | I2C_FLAG_ACKR | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF | I2C_FLAG_MASTER \ + | I2C_FLAG_BUSY | I2C_FLAG_TRA | I2C_FLAG_GENERAL_CALL \ + | I2C_FLAG_SMBUS_DEFAULT_MATCH | I2C_FLAG_SMBUS_HOST_MATCH \ + | I2C_FLAG_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @defgroup I2C_Int_Flag I2C Interrupt Flag Bits + * @{ + */ +#define I2C_INT_START (I2C_CR2_STARTIE) +#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE) +#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE) +#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE) +#define I2C_INT_STOP (I2C_CR2_STOPIE) +#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE) +#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE) +#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE) +#define I2C_INT_NACK (I2C_CR2_NACKIE) +#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE) +#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE) +#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE) +#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE) +#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE) + +#define I2C_INT_ALL (I2C_INT_START | I2C_INT_MATCH_ADDR0 | I2C_INT_MATCH_ADDR1 | I2C_INT_TX_CPLT \ + | I2C_INT_STOP | I2C_INT_RX_FULL | I2C_INT_TX_EMPTY | I2C_INT_ARBITRATE_FAIL \ + | I2C_INT_NACK | I2C_INT_TMOUTIE | I2C_INT_GENERAL_CALL \ + | I2C_INT_SMBUS_DEFAULT_MATCH | I2C_INT_SMBUS_HOST_MATCH \ + | I2C_INT_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2C_Global_Functions + * @{ + */ + +/* Initialization and Configuration **********************************/ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit); +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_DeInit(CM_I2C_TypeDef *I2Cx); +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr); +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState); +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock); +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Start/Restart/Stop ************************************************/ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx); + +/* Status management *************************************************/ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); + +/* Data transfer ************************************ ***************/ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx); +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig); + +/* Time out function *************************************************/ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH); +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL); +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +/* High level functions for reference ********************************/ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h new file mode 100644 index 0000000000..fa4eca272e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h @@ -0,0 +1,347 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.h + * @brief This file contains all the functions prototypes of the I2S driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2S_H__ +#define __HC32_LL_I2S_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2S + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Types I2S Global Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S. + This parameter can be a value of @ref I2S_Clock_Source */ + uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S. + This parameter can be a value of @ref I2S_Mode */ + uint32_t u32Protocol; /*!< Specifies the communication protocol of I2S. + This parameter can be a value of @ref I2S_Protocol */ + uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication. + This parameter can be a value of @ref I2S_Trans_Mode */ + uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t u32ChWidth; /*!< Specifies the channel length for the I2S communication. + This parameter can be a value of @ref I2S_Channel_Length */ + uint32_t u32DataWidth; /*!< Specifies the data length for the I2S communication. + This parameter can be a value of @ref I2S_Data_Length */ + uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S. + This parameter can be a value of @ref I2S_MCK_Output */ + uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO. + This parameter can be a value of @ref I2S_Trans_Level */ + uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO. + This parameter can be a value of @ref I2S_Receive_Level */ +} stc_i2s_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Macros I2S Global Macros + * @{ + */ + +/** + * @defgroup I2S_External_Clock_Frequency I2S External Clock Frequency + * @{ + */ +#ifndef I2S_EXT_CLK_FREQ +#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */ +#endif /* I2S_EXT_CLK_FREQ */ +/** + * @} + */ + +/** + * @defgroup I2S_Clock_Source I2S Clock Source + * @{ + */ +#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */ +#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */ +/** + * @} + */ + +/** + * @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MD_MASTER (0UL) /*!< Master mode */ +#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Protocol I2S Communication Protocol + * @{ + */ +#define I2S_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */ +#define I2S_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */ +#define I2S_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */ +#define I2S_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */ +#define I2S_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Mode I2S Transfer Mode + * @{ + */ +#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */ +#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */ +#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */ +#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */ +#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */ +#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */ +#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */ +#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */ +#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */ +#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */ +#define I2S_AUDIO_FREQ_DEFAULT (2UL) +/** + * @} + */ + +/** + * @defgroup I2S_Channel_Length I2S Channel Length + * @{ + */ +#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */ +#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_Data_Length I2S Data Length + * @{ + */ +#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */ +#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */ +#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_MCK_Output I2S MCK Output + * @{ + */ +#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */ +#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Level I2S Transfer Level + * @{ + */ +#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */ +#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */ +#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */ + +#define I2S_TRANS_LVL3 (0x03UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 3 */ +#define I2S_TRANS_LVL4 (0x04UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 4 */ +/** + * @} + */ + +/** + * @defgroup I2S_Receive_Level I2S Receive Level + * @{ + */ +#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */ +#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */ +#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */ + +#define I2S_RECEIVE_LVL3 (0x03UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 3 */ +#define I2S_RECEIVE_LVL4 (0x04UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 4 */ +/** + * @} + */ + +/** + * @defgroup I2S_Com_Func I2S Communication Function + * @{ + */ +#define I2S_FUNC_TX (I2S_CTRL_TXE) /*!< Transfer function */ +#define I2S_FUNC_RX (I2S_CTRL_RXE) /*!< Receive function */ +#define I2S_FUNC_ALL (I2S_FUNC_TX | I2S_FUNC_RX) +/** + * @} + */ + +/** + * @defgroup I2S_Reset_Type I2S Reset Type + * @{ + */ +#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */ +#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */ + +#define I2S_RST_TYPE_SW (I2S_CTRL_SRST) /*!< I2S software reset */ +#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO | I2S_RST_TYPE_SW) +/** + * @} + */ + +/** + * @defgroup I2S_Interrupt I2S Interrupt + * @{ + */ +#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */ +#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */ +#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */ +#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR) +/** + * @} + */ + +/** + * @defgroup I2S_Flag I2S Flag + * @{ + */ +#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */ +#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */ +#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */ +#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */ +#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */ +#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */ +#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */ +#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */ +#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \ + I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \ + I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +#define I2S_FLAG_CLR_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2S_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx); +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit); +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit); +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type); +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode); +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol); +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq); +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState); +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data); +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx); +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/* Interrupt and flag management functions */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h new file mode 100644 index 0000000000..0cee1693f7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h @@ -0,0 +1,465 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.h + * @brief This file contains all the Macro Definitions of the ICG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ICG_H__ +#define __HC32_LL_ICG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ICG + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Global_Macros ICG Global Macros + * @{ + */ + +/** + * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State + * @{ + */ +#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */ +#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type + * @{ + */ +#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period + * @{ + */ +#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division + * @{ + */ +#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */ +#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */ +#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */ +#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */ +#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */ +#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range + * @{ + */ +#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */ +#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */ +#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */ +#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */ +#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */ +#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */ +#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode + * @{ + */ +#define ICG_SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */ +#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/* WDT function */ +/** + * @defgroup ICG_WDT_Reset_State ICG WDT Reset State + * @{ + */ +#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */ +#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type + * @{ + */ +#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Count_Period ICG WDT Count Period + * @{ + */ +#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS + +#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */ +#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */ +#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division + * @{ + */ +#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS + +#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */ +#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */ +#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */ +#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */ +#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */ +#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */ +#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */ +#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range + * @{ + */ +#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS + +#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */ +#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */ +#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */ +#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */ +#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */ +#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */ +#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode + * @{ + */ +#define ICG_WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/* NMI Pin function */ + +/* BOR function */ +/** + * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold + * @{ + */ +#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */ +#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */ +#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */ +#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Reset_State ICG BOR Reset State + * @{ + */ +#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */ +#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select + * @{ + */ + +#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */ +#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Reset_State ICG HRC Reset State + * @{ + */ +#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */ +#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */ +/** + * @} + */ + +/* LVD function */ + +/* Core lockup function */ + +/* Flash function */ +/** + * @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State + * @{ + */ +#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */ +#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */ +/** + * @} + */ + +/** + * @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State + * @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF + * @{ + */ +#define ICG_FLASH_PROTECT_RST_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */ +#define ICG_FLASH_PROTECT_RST_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Configuration ICG Register Configuration + * @{ + */ + +/** + ******************************************************************************* + * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* SWDT register config */ +#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_STOP) +#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST) +#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD65536) +#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV2048) +#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT) +#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP) + +/* SWDT register value */ +#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \ + ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* WDT register config */ +#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP) +#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST) +#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536) +#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192) +#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT) +#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP) + +/* WDT register value */ +#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \ + ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration + * @{ + ******************************************************************************* + */ +/* BOR register config */ +#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3) +#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE) + +/* BOR register value */ +#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration + * @{ + ******************************************************************************* + */ +/* HRC register config */ +#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M) +#define ICG_RB_HRC_STOP (ICG_HRC_RST_STOP) + +/* HRC register value */ +#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration + * @{ + ******************************************************************************* + */ +/* FLASH Bank register value */ +#define ICG_REG_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration + * @{ + ******************************************************************************* + */ +/* FLASH Read Protect register value */ +#define ICG_REG_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RST_DISABLE) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Value ICG Register Value + * @{ + */ +/* ICG register value */ +#ifndef ICG_REG_CFG0_CONST +#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL) +#endif +#ifndef ICG_REG_CFG1_CONST +#define ICG_REG_CFG1_CONST (ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0xFFF8FEFEUL) +#endif +#ifndef ICG_REG_CFG2_CONST +#define ICG_REG_CFG2_CONST (ICG_REG_FLASH_BANK_CONFIG | 0xFF000000UL) +#endif +#ifndef ICG_REG_CFG3_CONST +#define ICG_REG_CFG3_CONST (ICG_REG_FLASH_PROTECT_CONFIG | 0xFFFF0000UL) +#endif +/* ICG reserved value */ +#define ICG_REG_RESV_CONST (0xFFFFFFFFUL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h new file mode 100644 index 0000000000..c6d0e1a490 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h @@ -0,0 +1,591 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_INTERRUPTS_H__ +#define __HC32_LL_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Types INTC Global Types + * @{ + */ + +/** + * @brief Interrupt registration structure definition + */ +typedef struct { + en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */ + IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */ + func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */ +} stc_irq_signin_config_t; + +/** + * @brief NMI initialize configuration structure definition + */ +typedef struct { + uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */ +} stc_nmi_init_t; + +/** + * @brief EXTINT initialize configuration structure definition + */ +typedef struct { + uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */ + uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */ + uint32_t u32FilterB; /*!< NMI, ExtInt filter B function setting, @ref NMI_EXTINT_FilterBClock_Sel for details */ + uint32_t u32FilterBClock; /*!< NMI, ExtInt filter B time, @ref NMI_EXTINT_FilterBTim_Sel for details */ +} stc_extint_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Macros INTC Global Macros + * @{ + */ +/** + * @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15 + * @{ + */ +#define DDL_IRQ_PRIO_00 (0U) +#define DDL_IRQ_PRIO_01 (1U) +#define DDL_IRQ_PRIO_02 (2U) +#define DDL_IRQ_PRIO_03 (3U) +#define DDL_IRQ_PRIO_04 (4U) +#define DDL_IRQ_PRIO_05 (5U) +#define DDL_IRQ_PRIO_06 (6U) +#define DDL_IRQ_PRIO_07 (7U) +#define DDL_IRQ_PRIO_08 (8U) +#define DDL_IRQ_PRIO_09 (9U) +#define DDL_IRQ_PRIO_10 (10U) +#define DDL_IRQ_PRIO_11 (11U) +#define DDL_IRQ_PRIO_12 (12U) +#define DDL_IRQ_PRIO_13 (13U) +#define DDL_IRQ_PRIO_14 (14U) +#define DDL_IRQ_PRIO_15 (15U) + +#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15) + +/** + * @} + */ + +/** + * @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection + * @{ + */ +#define NMI_SRC_SWDT (INTC_NMIFR_SWDTFR) +#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1FR) +#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2FR) +#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPFR) +#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_REPFR) +#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCFR) +#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSMFR) +#define NMI_SRC_WDT (INTC_NMIFR_WDTFR) +#define NMI_SRC_ALL (NMI_SRC_SWDT | NMI_SRC_LVD1 | NMI_SRC_LVD2 | \ + NMI_SRC_XTAL | NMI_SRC_BUS_ERR | NMI_SRC_SRAM_PARITY | \ + NMI_SRC_WDT | NMI_SRC_SRAM_ECC) + +/** + * @} + */ + +/** + * @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection + * @{ + */ +#define EXTINT_CH00 (1UL << 0U) +#define EXTINT_CH01 (1UL << 1U) +#define EXTINT_CH02 (1UL << 2U) +#define EXTINT_CH03 (1UL << 3U) +#define EXTINT_CH04 (1UL << 4U) +#define EXTINT_CH05 (1UL << 5U) +#define EXTINT_CH06 (1UL << 6U) +#define EXTINT_CH07 (1UL << 7U) +#define EXTINT_CH08 (1UL << 8U) +#define EXTINT_CH09 (1UL << 9U) +#define EXTINT_CH10 (1UL <<10U) +#define EXTINT_CH11 (1UL <<11U) +#define EXTINT_CH12 (1UL <<12U) +#define EXTINT_CH13 (1UL <<13U) +#define EXTINT_CH14 (1UL <<14U) +#define EXTINT_CH15 (1UL <<15U) +#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \ + EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \ + EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \ + EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15) +/** + * @} + */ + +/** + * @defgroup INT_Channel_Sel Interrupt Channel Selection + * @{ + */ +#define INTC_INT0 INTC_IER_IER0 +#define INTC_INT1 INTC_IER_IER1 +#define INTC_INT2 INTC_IER_IER2 +#define INTC_INT3 INTC_IER_IER3 +#define INTC_INT4 INTC_IER_IER4 +#define INTC_INT5 INTC_IER_IER5 +#define INTC_INT6 INTC_IER_IER6 +#define INTC_INT7 INTC_IER_IER7 +#define INTC_INT8 INTC_IER_IER8 +#define INTC_INT9 INTC_IER_IER9 +#define INTC_INT10 INTC_IER_IER10 +#define INTC_INT11 INTC_IER_IER11 +#define INTC_INT12 INTC_IER_IER12 +#define INTC_INT13 INTC_IER_IER13 +#define INTC_INT14 INTC_IER_IER14 +#define INTC_INT15 INTC_IER_IER15 +#define INTC_INT16 INTC_IER_IER16 +#define INTC_INT17 INTC_IER_IER17 +#define INTC_INT18 INTC_IER_IER18 +#define INTC_INT19 INTC_IER_IER19 +#define INTC_INT20 INTC_IER_IER20 +#define INTC_INT21 INTC_IER_IER21 +#define INTC_INT22 INTC_IER_IER22 +#define INTC_INT23 INTC_IER_IER23 +#define INTC_INT24 INTC_IER_IER24 +#define INTC_INT25 INTC_IER_IER25 +#define INTC_INT26 INTC_IER_IER26 +#define INTC_INT27 INTC_IER_IER27 +#define INTC_INT28 INTC_IER_IER28 +#define INTC_INT29 INTC_IER_IER29 +#define INTC_INT30 INTC_IER_IER30 +#define INTC_INT31 INTC_IER_IER31 +#define INTC_INT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup INTC_Event_Channel_Sel Event Channel Selection + * @{ + */ +#define INTC_EVT0 INTC_EVTER_EVTE0 +#define INTC_EVT1 INTC_EVTER_EVTE1 +#define INTC_EVT2 INTC_EVTER_EVTE2 +#define INTC_EVT3 INTC_EVTER_EVTE3 +#define INTC_EVT4 INTC_EVTER_EVTE4 +#define INTC_EVT5 INTC_EVTER_EVTE5 +#define INTC_EVT6 INTC_EVTER_EVTE6 +#define INTC_EVT7 INTC_EVTER_EVTE7 +#define INTC_EVT8 INTC_EVTER_EVTE8 +#define INTC_EVT9 INTC_EVTER_EVTE9 +#define INTC_EVT10 INTC_EVTER_EVTE10 +#define INTC_EVT11 INTC_EVTER_EVTE11 +#define INTC_EVT12 INTC_EVTER_EVTE12 +#define INTC_EVT13 INTC_EVTER_EVTE13 +#define INTC_EVT14 INTC_EVTER_EVTE14 +#define INTC_EVT15 INTC_EVTER_EVTE15 +#define INTC_EVT16 INTC_EVTER_EVTE16 +#define INTC_EVT17 INTC_EVTER_EVTE17 +#define INTC_EVT18 INTC_EVTER_EVTE18 +#define INTC_EVT19 INTC_EVTER_EVTE19 +#define INTC_EVT20 INTC_EVTER_EVTE20 +#define INTC_EVT21 INTC_EVTER_EVTE21 +#define INTC_EVT22 INTC_EVTER_EVTE22 +#define INTC_EVT23 INTC_EVTER_EVTE23 +#define INTC_EVT24 INTC_EVTER_EVTE24 +#define INTC_EVT25 INTC_EVTER_EVTE25 +#define INTC_EVT26 INTC_EVTER_EVTE26 +#define INTC_EVT27 INTC_EVTER_EVTE27 +#define INTC_EVT28 INTC_EVTER_EVTE28 +#define INTC_EVT29 INTC_EVTER_EVTE29 +#define INTC_EVT30 INTC_EVTER_EVTE30 +#define INTC_EVT31 INTC_EVTER_EVTE31 +#define INTC_EVT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection + * @{ + */ +#define SWINT_CH00 INTC_SWIER_SWIE0 +#define SWINT_CH01 INTC_SWIER_SWIE1 +#define SWINT_CH02 INTC_SWIER_SWIE2 +#define SWINT_CH03 INTC_SWIER_SWIE3 +#define SWINT_CH04 INTC_SWIER_SWIE4 +#define SWINT_CH05 INTC_SWIER_SWIE5 +#define SWINT_CH06 INTC_SWIER_SWIE6 +#define SWINT_CH07 INTC_SWIER_SWIE7 +#define SWINT_CH08 INTC_SWIER_SWIE8 +#define SWINT_CH09 INTC_SWIER_SWIE9 +#define SWINT_CH10 INTC_SWIER_SWIE10 +#define SWINT_CH11 INTC_SWIER_SWIE11 +#define SWINT_CH12 INTC_SWIER_SWIE12 +#define SWINT_CH13 INTC_SWIER_SWIE13 +#define SWINT_CH14 INTC_SWIER_SWIE14 +#define SWINT_CH15 INTC_SWIER_SWIE15 +#define SWINT_CH16 INTC_SWIER_SWIE16 +#define SWINT_CH17 INTC_SWIER_SWIE17 +#define SWINT_CH18 INTC_SWIER_SWIE18 +#define SWINT_CH19 INTC_SWIER_SWIE19 +#define SWINT_CH20 INTC_SWIER_SWIE20 +#define SWINT_CH21 INTC_SWIER_SWIE21 +#define SWINT_CH22 INTC_SWIER_SWIE22 +#define SWINT_CH23 INTC_SWIER_SWIE23 +#define SWINT_CH24 INTC_SWIER_SWIE24 +#define SWINT_CH25 INTC_SWIER_SWIE25 +#define SWINT_CH26 INTC_SWIER_SWIE26 +#define SWINT_CH27 INTC_SWIER_SWIE27 +#define SWINT_CH28 INTC_SWIER_SWIE28 +#define SWINT_CH29 INTC_SWIER_SWIE29 +#define SWINT_CH30 INTC_SWIER_SWIE30 +#define SWINT_CH31 INTC_SWIER_SWIE31 +#define SWINT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection + * @{ + */ +#define EXTINT_FILTER_OFF (0UL) +#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN + +/** + * @} + */ + +/** + * @defgroup NMI_EXTINT_FilterBClock_Sel External Interrupt Filter B Function Selection + * @{ + */ +#define NMI_EXTINT_FILTER_B_OFF (0UL) +#define NMI_EXTINT_FILTER_B_ON INTC_EIRQCR_NOCEN +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection + * @{ + */ +#define EXTINT_FCLK_DIV1 (0UL) +#define EXTINT_FCLK_DIV8 INTC_EIRQCR_EISMPCLK_0 +#define EXTINT_FCLK_DIV32 INTC_EIRQCR_EISMPCLK_1 +#define EXTINT_FCLK_DIV64 INTC_EIRQCR_EISMPCLK + +/** + * @} + */ + +/** + * @defgroup NMI_EXTINT_FilterBTim_Sel External Interrupt Filter B Time Selection + * @{ + */ +#define NMI_EXTINT_FCLK_B_500NS (0UL) +#define NMI_EXTINT_FCLK_B_1US (1UL << INTC_NOCCR_NOCSEL_POS) +#define NMI_EXTINT_FCLK_B_2US (2UL << INTC_NOCCR_NOCSEL_POS) +#define NMI_EXTINT_FCLK_B_4US INTC_NOCCR_NOCSEL + +/** + * @} + */ + +/** + * @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection + * @{ + */ +#define EXTINT_TRIG_FALLING (0UL) +#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0 +#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1 +#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG + +/** + * @} + */ + +/** + * @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection + * @{ + */ +#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WUPEN_EIRQWUEN_0 +#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WUPEN_EIRQWUEN_1 +#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WUPEN_EIRQWUEN_2 +#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WUPEN_EIRQWUEN_3 +#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WUPEN_EIRQWUEN_4 +#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WUPEN_EIRQWUEN_5 +#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WUPEN_EIRQWUEN_6 +#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WUPEN_EIRQWUEN_7 +#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WUPEN_EIRQWUEN_8 +#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WUPEN_EIRQWUEN_9 +#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WUPEN_EIRQWUEN_10 +#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WUPEN_EIRQWUEN_11 +#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WUPEN_EIRQWUEN_12 +#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WUPEN_EIRQWUEN_13 +#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WUPEN_EIRQWUEN_14 +#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WUPEN_EIRQWUEN_15 +#define INTC_STOP_WKUP_SWDT INTC_WUPEN_SWDTWUEN +#define INTC_STOP_WKUP_LVD1 INTC_WUPEN_PVD1WUEN +#define INTC_STOP_WKUP_LVD2 INTC_WUPEN_PVD2WUEN +#define INTC_STOP_WKUP_CMP INTC_WUPEN_CMPWUEN +#define INTC_STOP_WKUP_WKTM INTC_WUPEN_WKTMWUEN +#define INTC_STOP_WKUP_RTC_ALM INTC_WUPEN_RTCALMWUEN +#define INTC_STOP_WKUP_RTC_PRD INTC_WUPEN_RTCPRDWUEN +#define INTC_STOP_WKUP_TMR0_CMP INTC_WUPEN_TMR0GCMWUEN +#define INTC_STOP_WKUP_TMR2_CMP INTC_WUPEN_TMR2GCMWUEN +#define INTC_STOP_WKUP_TMR2_OVF INTC_WUPEN_TMR2OVFWUEN +#define INTC_STOP_WKUP_USART1_RX INTC_WUPEN_RXWUEN +#define INTC_STOP_WKUP_USBHS INTC_WUPEN_USHWUEN +#define INTC_STOP_WKUP_USBFS INTC_WUPEN_USFWUEN +#define INTC_STOP_WKUP_ETH INTC_WUPEN_ETHWUEN +#define INTC_WUPEN_ALL \ + (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \ + INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \ + INTC_WUPEN_CMPWUEN | INTC_WUPEN_WKTMWUEN | \ + INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \ + INTC_WUPEN_TMR0GCMWUEN | INTC_WUPEN_TMR2GCMWUEN | \ + INTC_WUPEN_TMR2OVFWUEN | INTC_WUPEN_RXWUEN | \ + INTC_WUPEN_USHWUEN | INTC_WUPEN_USFWUEN | \ + INTC_WUPEN_ETHWUEN) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup INTC_Global_Functions + * @{ + */ + +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig); +int32_t INTC_IrqSignOut(IRQn_Type enIRQn); +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState); +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState); +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority); +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState); + +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit); +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit); +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src); +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState); +void NMI_ClearNmiStatus(uint32_t u32Src); + +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit); +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit); +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh); +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh); + +void IRQ000_Handler(void); +void IRQ001_Handler(void); +void IRQ002_Handler(void); +void IRQ003_Handler(void); +void IRQ004_Handler(void); +void IRQ005_Handler(void); +void IRQ006_Handler(void); +void IRQ007_Handler(void); + +void IRQ008_Handler(void); +void IRQ009_Handler(void); +void IRQ010_Handler(void); +void IRQ011_Handler(void); +void IRQ012_Handler(void); +void IRQ013_Handler(void); +void IRQ014_Handler(void); +void IRQ015_Handler(void); + +void IRQ016_Handler(void); +void IRQ017_Handler(void); +void IRQ018_Handler(void); +void IRQ019_Handler(void); +void IRQ020_Handler(void); +void IRQ021_Handler(void); +void IRQ022_Handler(void); +void IRQ023_Handler(void); + +void IRQ024_Handler(void); +void IRQ025_Handler(void); +void IRQ026_Handler(void); +void IRQ027_Handler(void); +void IRQ028_Handler(void); +void IRQ029_Handler(void); +void IRQ030_Handler(void); +void IRQ031_Handler(void); +void IRQ032_Handler(void); +void IRQ033_Handler(void); +void IRQ034_Handler(void); +void IRQ035_Handler(void); +void IRQ036_Handler(void); +void IRQ037_Handler(void); +void IRQ038_Handler(void); +void IRQ039_Handler(void); +void IRQ040_Handler(void); +void IRQ041_Handler(void); +void IRQ042_Handler(void); +void IRQ043_Handler(void); +void IRQ044_Handler(void); +void IRQ045_Handler(void); +void IRQ046_Handler(void); +void IRQ047_Handler(void); +void IRQ048_Handler(void); +void IRQ049_Handler(void); +void IRQ050_Handler(void); +void IRQ051_Handler(void); +void IRQ052_Handler(void); +void IRQ053_Handler(void); +void IRQ054_Handler(void); +void IRQ055_Handler(void); +void IRQ056_Handler(void); +void IRQ057_Handler(void); +void IRQ058_Handler(void); +void IRQ059_Handler(void); +void IRQ060_Handler(void); +void IRQ061_Handler(void); +void IRQ062_Handler(void); +void IRQ063_Handler(void); +void IRQ064_Handler(void); +void IRQ065_Handler(void); +void IRQ066_Handler(void); +void IRQ067_Handler(void); +void IRQ068_Handler(void); +void IRQ069_Handler(void); +void IRQ070_Handler(void); +void IRQ071_Handler(void); +void IRQ072_Handler(void); +void IRQ073_Handler(void); +void IRQ074_Handler(void); +void IRQ075_Handler(void); +void IRQ076_Handler(void); +void IRQ077_Handler(void); +void IRQ078_Handler(void); +void IRQ079_Handler(void); +void IRQ080_Handler(void); +void IRQ081_Handler(void); +void IRQ082_Handler(void); +void IRQ083_Handler(void); +void IRQ084_Handler(void); +void IRQ085_Handler(void); +void IRQ086_Handler(void); +void IRQ087_Handler(void); +void IRQ088_Handler(void); +void IRQ089_Handler(void); +void IRQ090_Handler(void); +void IRQ091_Handler(void); +void IRQ092_Handler(void); +void IRQ093_Handler(void); +void IRQ094_Handler(void); +void IRQ095_Handler(void); +void IRQ096_Handler(void); +void IRQ097_Handler(void); +void IRQ098_Handler(void); +void IRQ099_Handler(void); +void IRQ100_Handler(void); +void IRQ101_Handler(void); +void IRQ102_Handler(void); +void IRQ103_Handler(void); +void IRQ104_Handler(void); +void IRQ105_Handler(void); +void IRQ106_Handler(void); +void IRQ107_Handler(void); +void IRQ108_Handler(void); +void IRQ109_Handler(void); +void IRQ110_Handler(void); +void IRQ111_Handler(void); +void IRQ112_Handler(void); +void IRQ113_Handler(void); +void IRQ114_Handler(void); +void IRQ115_Handler(void); +void IRQ116_Handler(void); +void IRQ117_Handler(void); +void IRQ118_Handler(void); +void IRQ119_Handler(void); +void IRQ120_Handler(void); +void IRQ121_Handler(void); +void IRQ122_Handler(void); +void IRQ123_Handler(void); +void IRQ124_Handler(void); +void IRQ125_Handler(void); +void IRQ126_Handler(void); +void IRQ127_Handler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h new file mode 100644 index 0000000000..2cff107fbe --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h @@ -0,0 +1,239 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.h + * @brief This file contains all the functions prototypes of the KEYSCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_KEYSCAN_H__ +#define __HC32_LL_KEYSCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_KEYSCAN + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types + * @{ + */ + +/** + * @brief KEYSCAN configuration + */ +typedef struct { + uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles. + This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */ + + uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */ + + uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Clock_Sel */ + + uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyout_Sel */ + + uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyin_Sel */ +} stc_keyscan_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection + * @{ + */ +#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection + * @{ + */ +#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */ +#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */ +#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */ +#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */ +#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */ +#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */ +#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */ +#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */ +#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */ +#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */ +#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */ +#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */ +#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */ +#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */ +#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */ +#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */ +#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */ +#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */ +#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */ +#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */ +#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */ +#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */ +#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection + * @{ + */ +#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */ +#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */ +#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection + * @{ + */ +#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */ +#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */ +#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */ +#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */ +#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */ +#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */ +#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection + * @{ + */ +#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */ +#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */ +#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */ +#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */ +#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */ +#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */ +#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */ +#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */ +#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */ +#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */ +#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */ +#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */ +#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */ +#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */ +#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */ +#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */ +#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup KEYSCAN_Global_Functions + * @{ + */ +/** + * @brief Get KEYOUT index. + * @param None + * @retval uint32_t: KEYOUT index 0~7. + */ +__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void) +{ + return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX); +} + +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit); +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit); +void KEYSCAN_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_KEYSCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mau.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mau.h new file mode 100644 index 0000000000..e7228003e5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mau.h @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * @file hc32_ll_mau.h + * @brief This file contains all the functions prototypes of the MAU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MAU_H__ +#define __HC32_LL_MAU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MAU + * @{ + */ + +#if (LL_MAU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup MAU_Global_Macros MAU Global Macros + * @{ + */ + +#define MAU_SQRT_TIMEOUT (HCLK_VALUE / 10000UL)/* About 1mS timeout */ +#define MAU_SQRT_OUTPUT_LSHIFT_MAX (16U) +#define MAU_SIN_Q15_SCALAR (0x8000UL) +#define MAU_SIN_ANGIDX_TOTAL (0x1000UL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addtogroup MAU_Global_Functions + * @{ + */ + +void MAU_SqrtInit(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState); +void MAU_SqrtDeInit(CM_MAU_TypeDef *MAUx); + +void MAU_SqrtResultLShiftConfig(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber); +void MAU_SqrtIntCmd(CM_MAU_TypeDef *MAUx, en_functional_state_t enNewState); +void MAU_SqrtWriteData(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand); +en_flag_status_t MAU_SqrtGetStatus(const CM_MAU_TypeDef *MAUx); +uint32_t MAU_SqrtReadData(const CM_MAU_TypeDef *MAUx); +void MAU_SqrtStart(CM_MAU_TypeDef *MAUx); + +int32_t MAU_Sqrt(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result); + +int16_t MAU_Sin(CM_MAU_TypeDef *MAUx, uint16_t u16AngleIdx); + +/** + * @} + */ + +#endif /* LL_MAU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MAU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h new file mode 100644 index 0000000000..c555bd47a6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h @@ -0,0 +1,394 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.h + * @brief This file contains all the functions prototypes of the MPU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MPU_H__ +#define __HC32_LL_MPU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MPU + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Types MPU Global Types + * @{ + */ + +/** + * @brief MPU Unit configure structure definition + */ +typedef struct { + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space. + This parameter can be a value of @ref MPU_Background_Write_Permission */ + uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space + This parameter can be a value of @ref MPU_Background_Read_Permission */ +} stc_mpu_unit_config_t; + +/** + * @brief MPU Init structure definition + */ +typedef struct { + stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */ + stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */ + stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */ + stc_mpu_unit_config_t stcUsbHSDma; /*!< Configure storage protection unit of USBHS_DMA */ + stc_mpu_unit_config_t stcEthDma; /*!< Configure storage protection unit of ETH_DMA */ +} stc_mpu_init_t; + +/** + * @brief MPU Region Permission structure definition + */ +typedef struct { + uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region. + This parameter can be a value of @ref MPU_Region_Write_Permission */ + uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region. + This parameter can be a value of @ref MPU_Region_Read_Permission */ +} stc_mpu_region_permission_t; + +/** + * @brief MPU region initialization structure definition + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + */ +typedef struct { + uint32_t u32BaseAddr; /*!< Specifies the base address of the region. + This parameter can be a number between 0UL and 0xFFFFFFE0UL */ + uint32_t u32Size; /*!< Specifies the size of the region. + This parameter can be a value of @ref MPU_Region_Size */ + stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */ + stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */ + stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */ + stc_mpu_region_permission_t stcUsbHSDma; /*!< Specifies the USBHS_DMA access permission for the region */ + stc_mpu_region_permission_t stcEthDma; /*!< Specifies the ETH_DMA access permission for the region */ +} stc_mpu_region_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Macros MPU Global Macros + * @{ + */ + +/** + * @defgroup MPU_Unit_Type MPU Unit Type + * @{ + */ +#define MPU_UNIT_DMA1 (0x01UL) /*!< System DMA_1 MPU */ +#define MPU_UNIT_DMA2 (0x02UL) /*!< System DMA_2 MPU */ +#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */ +#define MPU_UNIT_USBHS_DMA (0x08UL) /*!< USBHS_DMA MPU */ +#define MPU_UNIT_ETH_DMA (0x10UL) /*!< ETH_DMA MPU */ +#define MPU_UNIT_ALL (MPU_UNIT_DMA1 | MPU_UNIT_DMA2 | MPU_UNIT_USBFS_DMA | \ + MPU_UNIT_USBHS_DMA | MPU_UNIT_ETH_DMA) +/** + * @} + */ + +/** + * @defgroup MPU_Region_Number MPU Region Number + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @{ + */ +#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */ +#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */ +#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */ +#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */ +#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */ +#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */ +#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */ +#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */ +#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */ +#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */ +#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */ +#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */ +#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */ +#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */ +#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */ +#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Write_Permission MPU Background Write Permission + * @{ + */ +#define MPU_BACKGROUND_WR_DISABLE (MPU_S1CR_SMPU1BWP) /*!< Disable write the background space */ +#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Read_Permission MPU Background Read Permission + * @{ + */ +#define MPU_BACKGROUND_RD_DISABLE (MPU_S1CR_SMPU1BRP) /*!< Disable read the background space */ +#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Exception_Type MPU Exception Type + * @{ + */ +#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */ +#define MPU_EXP_TYPE_BUS_ERR (MPU_S1CR_SMPU1ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */ +#define MPU_EXP_TYPE_NMI (MPU_S1CR_SMPU1ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */ +#define MPU_EXP_TYPE_RST (MPU_S1CR_SMPU1ACT) /*!< The host unit access protection regions will trigger the reset */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Write_Permission MPU Region Write Permission + * @{ + */ +#define MPU_REGION_WR_DISABLE (MPU_S1RGWP_S1RG0WP) /*!< Disable write the region */ +#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Read_Permission MPU Region Read Permission + * @{ + */ +#define MPU_REGION_RD_DISABLE (MPU_S1RGRP_S1RG0RP) /*!< Disable read the region */ +#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Size MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */ +#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */ +#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */ +#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */ +#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */ +#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */ +#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */ +#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */ +#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */ +#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */ +#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */ +#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */ +#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */ +#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */ +#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */ +#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */ +#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */ +#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */ +#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */ +#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */ +#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */ +#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */ +#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */ +#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */ +#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */ +#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */ +#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */ +#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */ +/** + * @} + */ + +/** + * @defgroup MPU_Flag MPU Flag + * @{ + */ +#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */ +#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */ +#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */ + +#define MPU_FLAG_HMPUEAF (MPU_SR_HMPUEAF) /*!< USBHS_DMA error flag */ +#define MPU_FLAG_EMPUEAF (MPU_SR_EMPUEAF) /*!< ETH_DMA error flag */ +#define MPU_FLAG_ALL (MPU_FLAG_SMPU1EAF | MPU_FLAG_SMPU2EAF | MPU_FLAG_FMPUEAF | \ + MPU_FLAG_HMPUEAF | MPU_FLAG_EMPUEAF) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Type MPU IP Type + * @note IP access protection is not available in privileged mode. + * @{ + */ +#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */ +#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */ +#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */ +#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */ +#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */ +#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */ +#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */ +#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */ +#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */ +#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */ +#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */ +#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */ +#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */ +#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */ +#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \ + MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \ + MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \ + MPU_IP_FCG | MPU_IP_RMU_CMU_PWC) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Exception_Type MPU IP Exception Type + * @{ + */ +#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */ +#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */ +/** + * @} + */ + +/** + * @defgroup MPU_Register_Protect_Key INTC Registers Protect Key + * @{ + */ +#define MPU_REG_LOCK_KEY (0x96A4UL) +#define MPU_REG_UNLOCK_KEY (0x96A5UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MPU_Global_Functions + * @{ + */ + +/** + * @brief MPU write protect unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Unlock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY); +} + +/** + * @brief MPU write protect lock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Lock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY); +} + +void MPU_REG_Unlock(void); +void MPU_REG_Lock(void); + +void MPU_DeInit(void); +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit); +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit); +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type); +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState); +en_flag_status_t MPU_GetStatus(uint32_t u32Flag); +void MPU_ClearStatus(uint32_t u32Flag); + +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit); +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit); +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr); +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size); +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); + +void MPU_IP_SetExceptionType(uint32_t u32Type); +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_nfc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_nfc.h new file mode 100644 index 0000000000..552ecf4151 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_nfc.h @@ -0,0 +1,591 @@ +/** + ******************************************************************************* + * @file hc32_ll_nfc.h + * @brief This file contains all the functions prototypes of the EXMC NFC + * (External Memory Controller: NAND Flash Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_NFC_H__ +#define __HC32_LL_NFC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EXMC + * @{ + */ + +/** + * @addtogroup LL_NFC + * @{ + */ + +#if (LL_NFC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Global_Types EXMC_NFC Global Types + * @{ + */ + +/** + * @brief EXMC_NFC Base Configuration Structure definition + */ +typedef struct { + uint32_t u32CapacitySize; /*!< Defines the capacity size. + This parameter can be a value of @ref EXMC_NFC_BANK_Memory_Capacity. */ + uint32_t u32MemoryWidth; /*!< Defines the memory width. + This parameter can be a value of @ref EXMC_NFC_Memory_Width. */ + uint32_t u32BankNum; /*!< Defines the bank number. + This parameter can be a value of @ref EXMC_NFC_Bank_Number */ + uint32_t u32PageSize; /*!< Defines the page size. + This parameter can be a value of @ref EXMC_NFC_Page_Size. */ + uint32_t u32WriteProtect; /*!< Defines the write protect. + This parameter can be a value of @ref EXMC_NFC_Write_Protect. */ + uint32_t u32EccMode; /*!< Defines the ECC mode. + This parameter can be a value of @ref EXMC_NFC_ECC_Mode. */ + uint32_t u32RowAddrCycle; /*!< Defines the row address cycle. + This parameter can be a value of @ref EXMC_NFC_Row_Address_Cycle. */ + uint8_t u8SpareSizeForUserData; /*!< Defines the spare column size for user data. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_base_config_t; + +/** + * @brief EXMC_NFC Timing Register 0 Configuration Structure definition + */ +typedef struct { + uint32_t u32TS; /*!< Defines the CLE/ALE/CE setup time in memory clock cycles(tALS/tCS/tCLS). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TWP; /*!< Defines the WE# pulse width time in memory clock cycles(tWP). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TRP; /*!< Defines the RE# pulse width time in memory clock cycles(tRP). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TH; /*!< Defines the CLE/ALE/CE hold time in memory clock cycles(tALH/tCH/tCLH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_timing_reg0_config_t; + +/** + * @brief EXMC_NFC Timing Register 1 Configuration Structure definition + */ +typedef struct { + uint32_t u32TWH; /*!< Defines the WE# pulse width HIGH time in memory clock cycles(tWH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TRH; /*!< Defines the RE# HIGH hold time in memory clock cycles(tREH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TRR; /*!< Defines the Ready to RE# LOW time in memory clock cycles(tRR). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TWB; /*!< Defines the WE# HIGH to busy time in memory clock cycles(tWB). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_timing_reg1_config_t; + +/** + * @brief EXMC_NFC Timing Register 2 Configuration Structure definition + */ +typedef struct { + uint32_t u32TCCS; /*!< Defines the command(change read/write column) delay time in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TWTR; /*!< Defines the WE# HIGH to RE# LOW time in memory clock cycles(tWHR). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TRTW; /*!< Defines the RE# HIGH to WE# LOW time in memory clock cycles(tRHW). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32TADL; /*!< Defines the Address to Data Loading time in memory clock cycles(tADL). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_timing_reg2_config_t; + +/** + * @brief EXMC_NFC Initialization Structure definition + */ +typedef struct { + uint32_t u32OpenPage; /*!< NFC memory open-page selection. + This structure details refer @ref EXMC_NFC_Open_Page. */ + stc_exmc_nfc_base_config_t stcBaseConfig; /*!< NFC memory base configure. + This structure details refer @ref stc_exmc_nfc_base_config_t. */ + stc_exmc_nfc_timing_reg0_config_t stcTimingReg0; /*!< NFC memory timing configure 0. + This structure details refer @ref stc_exmc_nfc_timing_reg0_config_t. */ + stc_exmc_nfc_timing_reg1_config_t stcTimingReg1; /*!< NFC memory timing configure 1. + This structure details refer @ref stc_exmc_nfc_timing_reg1_config_t. */ + stc_exmc_nfc_timing_reg2_config_t stcTimingReg2; /*!< NFC memory timing configure 2. + This structure details refer @ref stc_exmc_nfc_timing_reg2_config_t. */ +} stc_exmc_nfc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Global_Macros EXMC_NFC Global Macros + * @{ + */ + +/** + * @defgroup EXMC_NFC_Bank EXMC_NFC Bank + * @{ + */ +#define EXMC_NFC_BANK0 (0UL) /*!< Bank 0 */ +#define EXMC_NFC_BANK1 (1UL) /*!< Bank 1 */ +#define EXMC_NFC_BANK2 (2UL) /*!< Bank 2 */ +#define EXMC_NFC_BANK3 (3UL) /*!< Bank 3 */ +#define EXMC_NFC_BANK4 (4UL) /*!< Bank 4 */ +#define EXMC_NFC_BANK5 (5UL) /*!< Bank 5 */ +#define EXMC_NFC_BANK6 (6UL) /*!< Bank 6 */ +#define EXMC_NFC_BANK7 (7UL) /*!< Bank 7 */ +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Page_Size EXMC_NFC Page Size + * @{ + */ +#define EXMC_NFC_PAGE_SIZE_2KBYTE (NFC_BACR_PAGE_0) +#define EXMC_NFC_PAGE_SIZE_4KBYTE (NFC_BACR_PAGE_1) +#define EXMC_NFC_PAGE_SIZE_8KBYTE (NFC_BACR_PAGE) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_BANK_Memory_Capacity EXMC_NFC BANK Memory Capacity + * @{ + */ +#define EXMC_NFC_BANK_CAPACITY_512MBIT (3UL) +#define EXMC_NFC_BANK_CAPACITY_1GBIT (4UL) +#define EXMC_NFC_BANK_CAPACITY_2GBIT (5UL) +#define EXMC_NFC_BANK_CAPACITY_4GBIT (6UL) +#define EXMC_NFC_BANK_CAPACITY_8GBIT (7UL) +#define EXMC_NFC_BANK_CAPACITY_16GBIT (0UL) +#define EXMC_NFC_BANK_CAPACITY_32GBIT (1UL) +#define EXMC_NFC_BANK_CAPACITY_64GBIT (2UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Memory_Width EXMC_NFC Memory Width + * @{ + */ +#define EXMC_NFC_MEMORY_WIDTH_8BIT (0UL) +#define EXMC_NFC_MEMORY_WIDTH_16BIT (NFC_BACR_B16BIT) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Bank_Number EXMC_NFC Bank Number + * @{ + */ +#define EXMC_NFC_1BANK (0UL) +#define EXMC_NFC_2BANKS (NFC_BACR_BANK_0) +#define EXMC_NFC_4BANKS (NFC_BACR_BANK_1) +#define EXMC_NFC_8BANKS (NFC_BACR_BANK) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Open_Page EXMC_NFC Open Page + * @{ + */ +#define EXMC_NFC_OPEN_PAGE_DISABLE (0UL) +#define EXMC_NFC_OPEN_PAGE_ENABLE (PERIC_NFC_STCR_OPENP) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Write_Protect EXMC_NFC Write Protect + * @{ + */ +#define EXMC_NFC_WR_PROTECT_ENABLE (0UL) +#define EXMC_NFC_WR_PROTECT_DISABLE (NFC_BACR_WP) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Mode EXMC_NFC ECC Mode + * @{ + */ +#define EXMC_NFC_1BIT_ECC (0UL) +#define EXMC_NFC_4BIT_ECC (NFC_BACR_ECCM_0) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Row_Address_Cycle EXMC_NFC Row Address Cycle + * @{ + */ +#define EXMC_NFC_2_ROW_ADDR_CYCLE (0UL) +#define EXMC_NFC_3_ROW_ADDR_CYCLE (NFC_BACR_RAC) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Calculate_Bytes EXMC_NFC ECC Calculate Bytes + * @{ + */ +#define EXMC_NFC_ECC_CALCULATE_BLOCK_BYTE (512UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Value_Bytes EXMC_NFC ECC Value Bytes + * @{ + */ +#define EXMC_NFC_1BIT_ECC_VALUE_BYTE (3UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_1Bit_ECC_Result EXMC_NFC 1Bit ECC Result + * @{ + */ +#define EXMC_NFC_1BIT_ECC_NONE_ERR (0UL) +#define EXMC_NFC_1BIT_ECC_SINGLE_BIT_ERR (NFC_ECCR_SE) +#define EXMC_NFC_1BIT_ECC_MULTIPLE_BITS_ERR (NFC_ECCR_ME) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_1Bit_ECC_Error_Bit_Location EXMC_NFC 1Bit ECC Error Bit Location + * @{ + */ +#define EXMC_NFC_1BIT_ECC_ERR_BIT0 (0UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT1 (1UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT2 (2UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT3 (3UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT4 (4UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT5 (5UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT6 (6UL) +#define EXMC_NFC_1BIT_ECC_ERR_BIT7 (7UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Section EXMC_NFC ECC Section + * @{ + */ +#define EXMC_NFC_ECC_SECTION0 (0UL) +#define EXMC_NFC_ECC_SECTION1 (1UL) +#define EXMC_NFC_ECC_SECTION2 (2UL) +#define EXMC_NFC_ECC_SECTION3 (3UL) +#define EXMC_NFC_ECC_SECTION4 (4UL) +#define EXMC_NFC_ECC_SECTION5 (5UL) +#define EXMC_NFC_ECC_SECTION6 (6UL) +#define EXMC_NFC_ECC_SECTION7 (7UL) +#define EXMC_NFC_ECC_SECTION8 (8UL) +#define EXMC_NFC_ECC_SECTION9 (9UL) +#define EXMC_NFC_ECC_SECTION10 (10UL) +#define EXMC_NFC_ECC_SECTION11 (11UL) +#define EXMC_NFC_ECC_SECTION12 (12UL) +#define EXMC_NFC_ECC_SECTION13 (13UL) +#define EXMC_NFC_ECC_SECTION14 (14UL) +#define EXMC_NFC_ECC_SECTION15 (15UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Interrupt EXMC_NFC Interrupt + * @{ + */ +#define EXMC_NFC_INT_RB_BANK0 (NFC_IENR_RBEN_0) +#define EXMC_NFC_INT_RB_BANK1 (NFC_IENR_RBEN_1) +#define EXMC_NFC_INT_RB_BANK2 (NFC_IENR_RBEN_2) +#define EXMC_NFC_INT_RB_BANK3 (NFC_IENR_RBEN_3) +#define EXMC_NFC_INT_RB_BANK4 (NFC_IENR_RBEN_4) +#define EXMC_NFC_INT_RB_BANK5 (NFC_IENR_RBEN_5) +#define EXMC_NFC_INT_RB_BANK6 (NFC_IENR_RBEN_6) +#define EXMC_NFC_INT_RB_BANK7 (NFC_IENR_RBEN_7) +#define EXMC_NFC_INT_ECC_ERROR (NFC_IENR_ECCEEN) +#define EXMC_NFC_INT_ECC_CALC_COMPLETION (NFC_IENR_ECCCEN) +#define EXMC_NFC_INT_ECC_CORRECTABLE_ERR (NFC_IENR_ECCECEN) +#define EXMC_NFC_INT_ECC_UNCORRECTABLE_ERR (NFC_IENR_ECCEUEN) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Flag EXMC_NFC Flag + * @{ + */ +#define EXMC_NFC_FLAG_RB_BANK0 (NFC_ISTR_RBST_0) +#define EXMC_NFC_FLAG_RB_BANK1 (NFC_ISTR_RBST_1) +#define EXMC_NFC_FLAG_RB_BANK2 (NFC_ISTR_RBST_2) +#define EXMC_NFC_FLAG_RB_BANK3 (NFC_ISTR_RBST_3) +#define EXMC_NFC_FLAG_RB_BANK4 (NFC_ISTR_RBST_4) +#define EXMC_NFC_FLAG_RB_BANK5 (NFC_ISTR_RBST_5) +#define EXMC_NFC_FLAG_RB_BANK6 (NFC_ISTR_RBST_6) +#define EXMC_NFC_FLAG_RB_BANK7 (NFC_ISTR_RBST_7) +#define EXMC_NFC_FLAG_ECC_ERR (NFC_ISTR_ECCEST) +#define EXMC_NFC_FLAG_ECC_CALC_COMPLETION (NFC_ISTR_ECCCST) +#define EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR (NFC_ISTR_ECCECST) +#define EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR (NFC_ISTR_ECCEUST) +#define EXMC_NFC_FLAG_ECC_CALCULATING (1UL << 31UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Max_Timeout EXMC_NFC Max Timeout + * @{ + */ +#define EXMC_NFC_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Memory_Command EXMC_NFC Memory Command + * @{ + */ +#define EXMC_NFC_CMD_RD_1ST (0x00UL) +#define EXMC_NFC_CMD_RD_2ND (0xE0UL) + +#define EXMC_NFC_CMD_COPYBACK_READ_1ST (0x00UL) +#define EXMC_NFC_CMD_COPYBACK_READ_2ND (0x35UL) + +#define EXMC_NFC_CMD_CHANGE_RD_COL_1ST (0x05UL) +#define EXMC_NFC_CMD_CHANGE_RD_COL_2ND (0xE0UL) + +#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_1ST (0x06UL) +#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_2ND (0xE0UL) + +#define EXMC_NFC_CMD_RD_CACHE_RANDOM_1ST (0x00UL) +#define EXMC_NFC_CMD_RD_CACHE_RANDOM_2ND (0x31UL) + +#define EXMC_NFC_CMD_CALCULATE_ECC (0x23UL) + +#define EXMC_NFC_CMD_RD_CACHE_SEQ (0x31UL) + +#define EXMC_NFC_CMD_RD_CACHE_END (0x3FUL) + +#define EXMC_NFC_CMD_BLK_ERASE_1ST (0x60UL) +#define EXMC_NFC_CMD_BLK_ERASE_2ND (0xD0UL) + +#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_1ST (0x60UL) +#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_2ND (0xD1UL) + +#define EXMC_NFC_CMD_RD_STATUS (0x70UL) + +#define EXMC_NFC_CMD_RD_STATUS_ENHANCED (0x78UL) + +#define EXMC_NFC_CMD_PAGE_PROGRAM_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_PROGRAM_2ND (0x10UL) + +#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_2ND (0x11UL) + +#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_2ND (0x15UL) + +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_1ST (0x85UL) +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_2ND (0x10UL) + +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_1ST (0x85UL) +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_2ND (0x11UL) + +#define EXMC_NFC_CMD_CHANGE_WR_COL (0x85UL) + +#define EXMC_NFC_CMD_CHANGE_ROW_ADDR (0x85UL) + +#define EXMC_NFC_CMD_RD_ID (0x90UL) + +#define EXMC_NFC_CMD_RD_PARAMETER_PAGE (0xECUL) + +#define EXMC_NFC_CMD_RD_UNIQUE_ID (0xEDUL) + +#define EXMC_NFC_CMD_GET_FEATURES (0xEEUL) + +#define EXMC_NFC_CMD_SET_FEATURES (0xEFUL) + +#define EXMC_NFC_CMD_RST_LUN (0xFAUL) + +#define EXMC_NFC_CMD_ASYNCHRONOUS_RST (0xFCUL) + +#define EXMC_NFC_CMD_DESELECT_CHIP (0xFEUL) + +#define EXMC_NFC_CMD_RESET (0xFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_NFC_Global_Functions + * @{ + */ + +/** + * @brief Set EXMC_NFC command register value. + * @param [in] u32Value The combination value of command @ref EXMC_NFC_Memory_Command and arguments. + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteCmdReg(uint32_t u32Value) +{ + WRITE_REG32(CM_NFC->CMDR, u32Value); +} + +/** + * @brief Set EXMC_NFC Index register value. + * @param [in] u32Value The value of NFC_IDXR0. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteIDXR0(uint32_t u32Value) +{ + WRITE_REG32(CM_NFC->IDXR0, u32Value); +} + +/** + * @brief Set EXMC_NFC Index register value. + * @param [in] u8Value The value of NFC_IDXR1. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteIDXR1(uint8_t u8Value) +{ + WRITE_REG32(CM_NFC->IDXR1, u8Value); +} + +/** + * @brief De-select NFC bank. + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_DeselectChip(void) +{ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP); +} + +/** + * @brief Get the 4BIT ECC error section. + * @param None + * @retval The 4BIT ECC error section + */ +__STATIC_INLINE uint16_t EXMC_NFC_Get4BitEccErrSection(void) +{ + return (uint16_t)READ_REG32(CM_NFC->ECC_STAT); +} + +/* Initialization and configuration EXMC_NFC functions */ +int32_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcNfcInit); +int32_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcNfcInit); +void EXMC_NFC_DeInit(void); + +void EXMC_NFC_Cmd(en_functional_state_t enNewState); +void EXMC_NFC_EccCmd(en_functional_state_t enNewState); +void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState); +void EXMC_NFC_IntCmd(uint16_t u16IntType, en_functional_state_t enNewState); +en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag); +void EXMC_NFC_ClearStatus(uint32_t u32Flag); +en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag); +uint32_t EXMC_NFC_Get1BitEccResult(uint32_t u32Section); +uint32_t EXMC_NFC_Get1BitEccErrBitLocation(uint32_t u32Section); +uint32_t EXMC_NFC_Get1BitEccErrByteLocation(uint32_t u32Section); +void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData); +void EXMC_NFC_SetEccMode(uint32_t u32EccMode); +int32_t EXMC_NFC_GetSyndrome(uint32_t u32Section, uint16_t au16Synd[], uint8_t u8Len); + +/* EXMC_NFC command functions */ +uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank); +uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank, uint32_t u32RowAddr); +int32_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout); +int32_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout); +int32_t EXMC_NFC_ResetLun(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout); +int32_t EXMC_NFC_ReadId(uint32_t u32Bank, uint32_t u32IdAddr, + uint8_t au8DevId[], uint32_t u32NumBytes, uint32_t u32Timeout); +int32_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank, uint32_t au32UniqueId[], uint8_t u8NumWords, uint32_t u32Timeout); +int32_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank, + uint32_t au32Data[], uint16_t u16NumWords, uint32_t u32Timeout); +int32_t EXMC_NFC_SetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr, + const uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout); +int32_t EXMC_NFC_GetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr, + uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout); +int32_t EXMC_NFC_EraseBlock(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout); +int32_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank, uint32_t u32Page, uint8_t *pu8Data, + uint32_t u32NumBytes, uint32_t u32Timeout); +int32_t EXMC_NFC_WritePageMeta(uint32_t u32Bank, uint32_t u32Page, + const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout); +int32_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank, uint32_t u32Page, + uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout); +int32_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank, uint32_t u32Page, + const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout); +/** + * @} + */ + +#endif /* LL_NFC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_NFC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h new file mode 100644 index 0000000000..722679086c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h @@ -0,0 +1,202 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.h + * @brief This file contains all the functions prototypes of the OTS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_OTS_H__ +#define __HC32_LL_OTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_OTS + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Types OTS Global Types + * @{ + */ + +/** + * @brief Conditions of default parameters(slope K and offset M). + * @note Paramter 'u8T1' CANNOT equal to parameter 'u8T2'. + */ +typedef struct { + uint16_t u16ClockFreq; /*!< Frequency(MHz) of clock sources that OTS is going to use. */ + uint8_t u8T1; /*!< Temperature value T1 for the default parameter. + This parameter can be a value of @ref OTS_Param_Temp_Cond */ + uint8_t u8T2; /*!< Temperature value T2 for the default parameter. + This parameter can be a value of @ref OTS_Param_Temp_Cond */ +} stc_para_temp_cond_t; + +/** + * @brief OTS initialization structure. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< Specifies clock source for OTS. + This parameter can be a value of @ref OTS_Clock_Source */ + uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature). + This parameter can be a value of @ref OTS_Auto_Off_En */ + float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ + float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ + stc_para_temp_cond_t stcParaCond; /*!< Specifies the temperature conditions of the default parameters(slope K and offset M) if you + want to use the default parameters. */ +} stc_ots_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Macros OTS Global Macros + * @{ + */ + +/** + * @defgroup OTS_Clock_Source OTS Clock Source + * @{ + */ +#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */ +#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */ +/** + * @} + */ + +/** + * @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control + * @{ + */ +#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */ +#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */ +/** + * @} + */ + +/** + * @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition + * @{ + */ +#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup OTS_Global_Functions + * @{ + */ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U); +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U); +} + +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit); +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit); +void OTS_DeInit(void); + +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); + +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout); + +float32_t OTS_CalculateTemp(void); + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h new file mode 100644 index 0000000000..24b72a60f7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h @@ -0,0 +1,693 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.h + * @brief This file contains all the functions prototypes of the PWC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_PWC_H__ +#define __HC32_LL_PWC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_PWC + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Types PWC Global Types + * @{ + */ +/** + * @brief PWC LVD Init + */ +typedef struct { + uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */ + uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */ + uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */ + uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */ + uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */ + uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */ + uint32_t u32TriggerEdge; /*!< LVD trigger setting, @ref PWC_LVD_TRIG_Sel for details */ +} stc_pwc_lvd_init_t; + +/** + * @brief PWC LVD Init + */ +typedef struct { + uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */ + uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */ + uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */ +} stc_pwc_pd_mode_config_t; + +/** + * @brief PWC Stop mode Init + */ +typedef struct { + uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode, + @ref PWC_STOP_CLK_Sel for details. */ + uint8_t u8StopDrv; /*!< Stop mode drive capacity, + @ref PWC_STOP_DRV_Sel for details. */ + uint16_t u16ExBusHold; /*!< Expos status in stop mode, + @ref PWC_STOP_EXBUS_Sel for details. */ + uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode, + @ref STOP_FLASH_WAIT_Sel for details. */ +} stc_pwc_stop_mode_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Macros PWC Global Macros + * @{ + */ + +/** + * @defgroup PWC_PDMode_Sel Power down mode selection + * @{ + */ +#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */ +#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */ +#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */ +#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode + * @{ + */ +#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */ +#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */ +#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode + * @{ + */ +#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */ +#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode + * @{ + */ +#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */ +#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode + * @{ + */ +#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */ +#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode + * @{ + */ +#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */ +#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */ + +/** + * @} + */ + +/** + * @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode + * @{ + */ +#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */ +#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_RAM_Config Operating mode for RAM Config + * @{ + */ +#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */ +#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_Periph_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_CAN1 (PWC_PRAMLPC_PRAMPDC0) +#define PWC_RAM_PD_CAN2 (PWC_PRAMLPC_PRAMPDC1) +#define PWC_RAM_PD_CACHE (PWC_PRAMLPC_PRAMPDC2) +#define PWC_RAM_PD_USBFS (PWC_PRAMLPC_PRAMPDC3) +#define PWC_RAM_PD_USBHS (PWC_PRAMLPC_PRAMPDC4) +#define PWC_RAM_PD_ETHERTX (PWC_PRAMLPC_PRAMPDC5) +#define PWC_RAM_PD_ETHERRX (PWC_PRAMLPC_PRAMPDC6) +#define PWC_RAM_PD_SDIO1 (PWC_PRAMLPC_PRAMPDC7) +#define PWC_RAM_PD_SDIO2 (PWC_PRAMLPC_PRAMPDC8) +#define PWC_RAM_PD_NFC (PWC_PRAMLPC_PRAMPDC9) +#define PWC_RAM_PD_ALL (0x3FFU) + +/** + * @} + */ + +/** + * @defgroup PWC_PD_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_SRAM1_1 (PWC_RAMPC0_RAMPDC0) /*< 0x20000000 ~ 0x2000FFFF */ +#define PWC_RAM_PD_SRAM1_2 (PWC_RAMPC0_RAMPDC1) /*< 0x20010000 ~ 0x2001FFFF */ +#define PWC_RAM_PD_SRAM2_1 (PWC_RAMPC0_RAMPDC2) /*< 0x20020000 ~ 0x2002FFFF */ +#define PWC_RAM_PD_SRAM2_2 (PWC_RAMPC0_RAMPDC3) /*< 0x20030000 ~ 0x2003FFFF */ +#define PWC_RAM_PD_SRAM3_1 (PWC_RAMPC0_RAMPDC4) /*< 0x20040000 ~ 0x2004FFFF */ +#define PWC_RAM_PD_SRAM3_2 (PWC_RAMPC0_RAMPDC5) /*< 0x20050000 ~ 0x20057FFF */ +#define PWC_RAM_PD_SRAM4 (PWC_RAMPC0_RAMPDC6) /*< 0x20058000 ~ 0x2005FFFF */ +#define PWC_RAM_PD_SRAMH_1 (PWC_RAMPC0_RAMPDC7) /*< 0x1FFE0000 ~ 0x1FFE7FFF */ +#define PWC_RAM_PD_SRAMH_2 (PWC_RAMPC0_RAMPDC8) /*< 0x1FFE8000 ~ 0x1FFEFFFF */ +#define PWC_RAM_PD_SRAMH_3 (PWC_RAMPC0_RAMPDC9) /*< 0x1FFF0000 ~ 0x1FFF7FFF */ +#define PWC_RAM_PD_SRAMH_4 (PWC_RAMPC0_RAMPDC10) /*< 0x1FFF8000 ~ 0x1FFFFFFF */ +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Channel PWC LVD channel + * @{ + */ +#define PWC_LVD_CH1 (0x00U) +#define PWC_LVD_CH2 (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Config PWC LVD Config + * @{ + */ +#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select + * @{ + */ +#define PWC_LVD_EXP_TYPE_NONE (0x00U) +#define PWC_LVD_EXP_TYPE_INT (0x0101U) +#define PWC_LVD_EXP_TYPE_NMI (0x0001U) +#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config + * @{ + */ +#define PWC_LVD_CMP_OFF (0x00U) +#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF + * @{ + */ +#define PWC_LVD_FILTER_ON (0x00U) +#define PWC_LVD_FILTER_OFF (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability + * @note modified this value must when PWC_LVD_FILTER_OFF + * @{ + */ +#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */ +#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */ + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage + * @{ + * @note | HC32F472 || HC32F451,HC32F452 || || || +* | HC32F4A0 || HC32F460 || HC32M423/HC32M424 || HC32F120/HC32M120/HC32F160 || + * | LVD1 | LVD2 || LVD1 | LVD2 || LVD1 | LVD2 || LVD || + * LVL0 | 2.0V | 2.1V || 2.0V | 2.1V || 4.29V ~ 4.39V || 3.92V ~ 4.07V || + * LVL1 | 2.1V | 2.3V || 2.1V | 2.3V || 4.14V ~ 4.23V || 3.67V ~ 3.77V || + * LVL2 | 2.3V | 2.5V || 2.3V | 2.5V || 4.02V ~ 4.14V || 3.06V ~ 3.15V || + * LVL3 | 2.5V | 2.6V || 2.5V | 2.6V || 3.84V ~ 3.96V || 2.96V ~ 3.04V || + * LVL4 | 2.6V | 2.7V || 2.6V | 2.6V || 3.10V ~ 3.20V || 2.86V ~ 2.94V || + * LVL5 | 2.7V | 2.8V || 2.6V | 2.8V || 3.00V ~ 3.09V || 2.75V ~ 2.83V || + * LVL6 | 2.8V | 2.9V || 2.8V | 2.9V || 2.90V ~ 2.99V || 2.65V ~ 2.73V || + * LVL7 | 2.9V | --- || 2.9V | --- || 2.79V ~ 2.87V || 2.55V ~ 2.63V || + * LVL8 | --- | --- || --- | --- || 2.68V ~ 2.75V || 2.45V ~ 2.52V || + * LVL9 | --- | --- || --- | --- || 2.34V ~ 2.41V || 2.04V ~ 2.11V || + * LVL10 | --- | --- || --- | --- || 2.14V ~ 2.21V || 1.94V ~ 2.00V || + * LVL11 | --- | --- || --- | --- || 1.94V ~ 2.01V || 1.84V ~ 1.90V || + * LVL12 | --- | --- || --- | --- || 1.84V ~ 1.90V || ------------- || + * EXVCC | --- | EXVCC || --- | EXVC C || ---- | EXVCC || EXVCC || + */ +#define PWC_LVD_THRESHOLD_LVL0 (0x00U) +#define PWC_LVD_THRESHOLD_LVL1 (0x01U) +#define PWC_LVD_THRESHOLD_LVL2 (0x02U) +#define PWC_LVD_THRESHOLD_LVL3 (0x03U) +#define PWC_LVD_THRESHOLD_LVL4 (0x04U) +#define PWC_LVD_THRESHOLD_LVL5 (0x05U) +#define PWC_LVD_THRESHOLD_LVL6 (0x06U) +#define PWC_LVD_THRESHOLD_LVL7 (0x07U) +#define PWC_LVD_EXTVCC (0x07U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_TRIG_Sel LVD trigger setting + * @{ + */ +#define PWC_LVD_TRIG_FALLING (0x00UL << PWC_PVDICR_PVD1EDGS_POS) +#define PWC_LVD_TRIG_RISING (0x01UL << PWC_PVDICR_PVD1EDGS_POS) +#define PWC_LVD_TRIG_BOTH (0x02UL << PWC_PVDICR_PVD1EDGS_POS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Flag LVD flag + * @{ + */ +#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */ +#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */ +#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */ +#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */ + +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection + * @{ + */ +#define PWC_PD_WKUP0_POS (0U) +#define PWC_PD_WKUP1_POS (8U) +#define PWC_PD_WKUP2_POS (16U) +#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_NMI (PWC_PDWKE2_NMIWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge. + * @{ + */ +#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS) +#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS) +#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS) +#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS) +#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS) +#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS) + +#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \ + PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection + * @{ + */ +#define PWC_PD_WKUP_TRIG_FALLING (0x00U) +#define PWC_PD_WKUP_TRIG_RISING (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection + * @{ + */ +#define PWC_PD_WKUP_FLAG0_POS (0U) +#define PWC_PD_WKUP_FLAG1_POS (8U) +#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS) + +#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \ + PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \ + PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | PWC_PD_WKUP_FLAG_WKTM) +/** + * @} + */ + +/** + * @defgroup PWC_Monitor_Power PWC Power Monitor voltage definition + * @{ + */ +#define PWC_PWR_MON_IREF (0x00U) /*!< Internal reference voltage */ +#define PWC_PWR_MON_VBAT_DIV2 (PWC_PWRC4_ADBUFS) /*!< 1/2 VBAT voltage */ +/** + * @} + */ + +/** + * @defgroup PWC_VBAT_Reference_Voltage PWC VBAT Reference Voltage + * @{ + */ +#define PWC_VBAT_REF_VOL_1P8V (0x00U) /*!< Vbat reference voltage is 1.8V */ +#define PWC_VBAT_REF_VOL_2P1V (0x01U) /*!< Vbat reference voltage is 2.1V */ +/** + * @} + */ + +/** + * @defgroup PWC_BACKUP_RAM_Flag PWC Backup RAM Flag + * @{ + */ +#define PWC_BACKUP_RAM_FLAG_RAMPDF (PWC_VBATCR_RAMPDF) /*!< Backup RAM power down flag */ +#define PWC_BACKUP_RAM_FLAG_RAMVALID (PWC_VBATCR_RAMVALID) /*!< Backup RAM read/write flag */ +/** + * @} + */ + +/** + * @defgroup PWC_WKT_State PWC WKT State + * @{ + */ +#define PWC_WKT_OFF (0x00U) +#define PWC_WKT_ON (PWC_WKTC2_WKTCE) +/** + * @} + */ + +/** + * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source + * @{ + */ +#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTC2_WKCKS_POS)) /*!< 64Hz Clock */ +#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTC2_WKCKS_POS)) /*!< XTAL32 Clock */ +#define PWC_WKT_CLK_SRC_RTCLRC ((0x02U << PWC_WKTC2_WKCKS_POS)) /*!< RTCLRC Clock */ +/** + * @} + */ + +/** + * @defgroup PWC_Ldo_Sel PWC LDO Selection + * @{ + */ +#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD) +#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD) +#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL) +/** + * @} + */ + +/** + * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code. + * @brief Lock/unlock Code for each module + * PWC_UNLOCK_CODE0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * PWC_UNLOCK_CODE1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * PWC_UNLOCK_CODE2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @{ + */ +#define PWC_WRITE_ENABLE (0xA500U) +#define PWC_UNLOCK_CODE0 (0xA501U) +#define PWC_UNLOCK_CODE1 (0xA502U) +#define PWC_UNLOCK_CODE2 (0xA508U) + +/** + * @brief PWC FCG0 Unlock/Lock code + */ +#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL) +#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup PWC_Global_Functions + * @{ + */ +/** + * @brief Lock PWC, CLK, RMU register. + * @param [in] u16Module Lock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module) +{ + CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC))); +} + +/** + * @brief Unlock PWC, CLK, RMU register. + * @param [in] u16Module Unlock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module) +{ + SET_REG16_BIT(CM_PWC->FPRC, u16Module); +} + +/** + * @brief Lock PWC_FCG0 register . + * @param None + * @retval None + */ +__STATIC_INLINE void PWC_FCG0_REG_Lock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY); +} + +/** + * @brief Unlock PWR_FCG0 register. + * @param None + * @retval None + * @note Call this function before FCG_Fcg0PeriphClockCmd() + */ +__STATIC_INLINE void PWC_FCG0_REG_Unlock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY); +} + +/* PWC PD Function */ +void PWC_PD_Enter(void); +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig); +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig); +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState); +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge); +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag); +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag); +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState); +void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState); + +/* PWC WKTM Function */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal); +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal); +uint16_t PWC_WKT_GetCompareValue(void); +void PWC_WKT_Cmd(en_functional_state_t enNewState); +en_flag_status_t PWC_WKT_GetStatus(void); +void PWC_WKT_ClearStatus(void); + +void PWC_RamModeConfig(uint16_t u16Mode); + +/* PWC Sleep Function */ +void PWC_SLEEP_Enter(void); + +/* PWC Stop Function */ +void PWC_STOP_Enter(void); +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig); +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig); +void PWC_STOP_ClockSelect(uint8_t u8Clock); +void PWC_STOP_SetDrv(uint8_t u8StopDrv); +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState); + +void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold); + +/* PWC Speed Switch Function */ +int32_t PWC_HighSpeedToLowSpeed(void); +int32_t PWC_LowSpeedToHighSpeed(void); + +/* PWC LDO Function */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState); + +/* PWC LVD Function, LVD for PVD while HC32F460, HC32F451, HC32F452 and HC32F4A0 */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit); +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState); +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock); +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage); +void PWC_LVD_ClearStatus(uint8_t u8Flag); +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag); + +/* PWC Power Monitor Function */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState); +void PWC_SetPowerMonitorVoltageSrc(uint8_t u8VoltageSrc); + +/* PWC VBAT Function */ +void PWC_VBAT_SetMonitorVoltage(uint8_t u8RefVoltage); +void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState); +en_flag_status_t PWC_VBAT_GetVoltageStatus(void); +void PWC_VBAT_VoltageDivMonitorCmd(en_functional_state_t enNewState); +void PWC_VBAT_Reset(void); +void PWC_VBAT_PowerCmd(en_functional_state_t enNewState); + +/* PWC Backup RAM Function */ +void PWC_BKR_PowerCmd(en_functional_state_t enNewState); +en_flag_status_t PWC_BKR_GetStatus(uint8_t u8Flag); +void PWC_BKR_Write(uint8_t u8RegNum, uint8_t u8RegVal); +uint8_t PWC_BKR_Read(uint8_t u8RegNum); + +/* PWC RAM Function */ + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h new file mode 100644 index 0000000000..9b214659f1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h @@ -0,0 +1,445 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.h + * @brief This file contains all the functions prototypes of the QSPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_QSPI_H__ +#define __HC32_LL_QSPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_QSPI + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Types QSPI Global Types + * @{ + */ + +/** + * @brief QSPI initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref QSPI_Clock_Division */ + uint32_t u32SpiMode; /*!< Specifies the SPI mode. + This parameter can be a value of @ref QSPI_SPI_Mode */ + uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode. + This parameter can be a value of @ref QSPI_Prefetch_Mode */ + uint32_t u32ReadMode; /*!< Specifies the read mode. + This parameter can be a value of @ref QSPI_Read_Mode */ + uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles. + This parameter can be a value of @ref QSPI_Dummy_Cycle */ + uint32_t u32AddrWidth; /*!< Specifies the address width. + This parameter can be a value of @ref QSPI_Addr_Width */ + uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup. + This parameter can be a value of @ref QSPI_QSSN_Setup_Time */ + uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release. + This parameter can be a value of @ref QSPI_QSSN_Release_Time */ + uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN. + This parameter can be a value of @ref QSPI_QSSN_Interval_Time */ +} stc_qspi_init_t; + +/** + * @brief QSPI Custom read mode structure definition + */ +typedef struct { + uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol. + This parameter can be a value of @ref QSPI_Instruction_Protocol */ + uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol. + This parameter can be a value of @ref QSPI_Addr_Protocol */ + uint32_t u32DataProtocol; /*!< Specifies the data stage protocol. + This parameter can be a value of @ref QSPI_Data_Protocol */ + uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ +} stc_qspi_custom_mode_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Macros QSPI Global Macros + * @{ + */ + +/* QSPI memory mapping base and end address */ +#define QSPI_ROM_BASE (0x98000000UL) +#define QSPI_ROM_END (0x9BFFFFFFUL) + +/** + * @defgroup QSPI_Clock_Division QSPI Clock Division + * @{ + */ +#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */ +#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */ +#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */ +#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */ +#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */ +#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */ +#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */ +#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */ +#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */ +#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */ +#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */ +#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */ +#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */ +#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */ +#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */ +#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */ +#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */ +#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */ +#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */ +#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */ +#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */ +#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */ +#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */ +#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */ +#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */ +#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */ +#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */ +#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */ +#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */ +#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */ +#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */ +#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */ +#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */ +#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */ +#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */ +#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */ +#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */ +#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */ +#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */ +#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */ +#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */ +#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */ +#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */ +#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */ +#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */ +#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */ +#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */ +#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */ +#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */ +#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */ +#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */ +#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */ +#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */ +#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */ +#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */ +#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */ +#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */ +#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */ +#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */ +#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */ +#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */ +#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */ +#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */ +/** + * @} + */ + +/** + * @defgroup QSPI_SPI_Mode QSPI SPI Mode + * @{ + */ +#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */ +#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode + * @{ + */ +#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */ +#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */ +#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */ +/** + * @} + */ + +/** + * @defgroup QSPI_Read_Mode QSPI Read Mode + * @{ + */ +#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */ +#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */ +#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */ +#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */ +#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */ +#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */ +#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */ +#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */ +/** + * @} + */ + +/** + * @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle + * @{ + */ +#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */ +#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */ +#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */ +#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */ +#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */ +#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */ +#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */ +#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */ +#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */ +#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */ +#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */ +#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */ +#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Width QSPI Address Width + * @{ + */ +#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */ +#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */ +#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time + * @{ + */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time + * @{ + */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time + * @{ + */ +#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol + * @{ + */ +#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */ +#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */ +#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Protocol QSPI Address Protocol + * @{ + */ +#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */ +#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */ +#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Data_Protocol QSPI Data Protocol + * @{ + */ +#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */ +#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */ +#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level + * @{ + */ +#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */ +#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */ +/** + * @} + */ + +/** + * @defgroup QSPI_Status_Flag QSPI Status Flag + * @{ + */ +#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */ +#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */ +#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */ +#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */ +#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */ + +#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \ + QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \ + QSPI_FLAG_PREFETCH_STOP) +#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup QSPI_Global_Functions + * @{ + */ + +/** + * @brief Write data in direct communication mode. + * @param [in] u8Value Byte data. + * @retval None + */ +__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value) +{ + WRITE_REG32(CM_QSPI->DCOM, u8Value); +} + +/** + * @brief Read data in communication mode. + * @param None + * @retval uint8_t Byte data. + */ +__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void) +{ + return (uint8_t)CM_QSPI->DCOM; +} + +/* Initialization and configuration functions */ +void QSPI_DeInit(void); +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit); +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit); +void QSPI_SetWpPinLevel(uint32_t u32Level); +void QSPI_SetPrefetchMode(uint32_t u32Mode); +void QSPI_SelectMemoryBlock(uint8_t u8Block); +void QSPI_SetReadMode(uint32_t u32Mode); +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode); +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void QSPI_EnterDirectCommMode(void); +void QSPI_ExitDirectCommMode(void); +void QSPI_WriteDirectCommValue(uint8_t u8Value); +uint8_t QSPI_ReadDirectCommValue(void); + +/* Interrupt and flag management functions */ +uint8_t QSPI_GetPrefetchBufSize(void); +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag); +void QSPI_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h new file mode 100644 index 0000000000..1852a91f9c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.h + * @brief This file contains all the functions prototypes of the RMU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RMU_H__ +#define __HC32_LL_RMU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RMU + * @{ + */ +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Macros RMU Global Macros + * @{ + */ + +/** + * @defgroup RMU_ResetCause Rmu reset cause + * @{ + */ +#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */ +#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */ +#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */ +#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */ +#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */ +#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */ +#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */ +#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */ +#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */ +#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */ +#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */ +#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */ +#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */ +#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */ +#define RMU_FLAG_CPU_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */ +#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */ +#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \ + RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \ + RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \ + RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_CPU_LOCKUP | RMU_FLAG_MX) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RMU_Global_Functions + * @{ + */ + +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause); +void RMU_ClearStatus(void); + +void RMU_CPULockUpCmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h new file mode 100644 index 0000000000..5fda0116f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h @@ -0,0 +1,459 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.h + * @brief This file contains all the functions prototypes of the RTC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RTC_H__ +#define __HC32_LL_RTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RTC + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Types RTC Global Types + * @{ + */ + +/** + * @brief RTC Init structure definition + */ +typedef struct { + uint8_t u8ClockSrc; /*!< Specifies the RTC clock source. + This parameter can be a value of @ref RTC_Clock_Source */ + uint8_t u8HourFormat; /*!< Specifies the RTC hour format. + This parameter can be a value of @ref RTC_Hour_Format */ + uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period. + This parameter can be a value of @ref RTC_Interrupt_Period */ + uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation */ + uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation_Mode */ + uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation. + This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */ +} stc_rtc_init_t; + +/** + * @brief RTC Date structure definition + */ +typedef struct { + uint8_t u8Year; /*!< Specifies the RTC Year. + This parameter can be a number between Min_Data = 0 and Max_Data = 99 */ + uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + uint8_t u8Day; /*!< Specifies the RTC Day. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ + uint8_t u8Weekday; /*!< Specifies the RTC Weekday. + This parameter can be a value of @ref RTC_Weekday */ +} stc_rtc_date_t; + +/** + * @brief RTC Time structure definition + */ +typedef struct { + uint8_t u8Hour; /*!< Specifies the RTC Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8Minute; /*!< Specifies the RTC Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8Second; /*!< Specifies the RTC Second. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_time_t; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct { + uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday. + This parameter can be a value of @ref RTC_Alarm_Weekday */ + uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_alarm_t; + +/** + * @brief RTC Intrusion structure definition + */ +typedef struct { + uint8_t u8Timestamp; /*!< Specifies the validity of RTC intrusion timestemp. + This parameter can be a value of @ref RTC_Intrusion_Timestamp */ + uint8_t u8ResetBackupReg; /*!< Specifies the validity of RTC intrusion event that trigger backup registers reset. + This parameter can be a value of @ref RTC_Intrusion_Reset_Backup_Register */ + uint8_t u8Filter; /*!< Specifies the RTC intrusion pin filter. + This parameter can be a value of @ref RTC_Intrusion_Filter */ + uint8_t u8TriggerEdge; /*!< Specifies the RTC intrusion trigger edge. + This parameter can be a value of @ref RTC_Intrusion_Trigger_Edge */ +} stc_rtc_intrusion_t; + +/** + * @brief RTC Timestamp structure definition + */ +typedef struct { + stc_rtc_time_t stcTime; /*!< Specifies the RTC Intrusion Timestamp Time members */ + uint8_t u8Month; /*!< Specifies the Month of RTC timestamp (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + uint8_t u8Day; /*!< Specifies the Day of RTC timestamp. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ +} stc_rtc_timestamp_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Macros RTC Global Macros + * @{ + */ + +/** + * @defgroup RTC_Data_Format RTC Data Format + * @{ + */ +#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */ +#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */ +/** + * @} + */ + +/** + * @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion + * @{ + */ +#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U)) +#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU)) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */ +#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour_Format RTC Hour Format + * @{ + */ +#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */ +#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */ +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt_Period RTC Interrupt Period + * @{ + */ +#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */ +#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */ +#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */ +#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */ +#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */ +#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */ +#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation RTC Clock Compensation + * @{ + */ +#define RTC_CLK_COMPEN_DISABLE (0U) +#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode + * @{ + */ +#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */ +#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM + * @{ + */ +#define RTC_HOUR_24H (0U) /*!< 24-hour format */ +#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */ +#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */ +/** + * @} + */ + +/** + * @defgroup RTC_Month RTC Month + * @{ + */ +#define RTC_MONTH_JANUARY (0x01U) +#define RTC_MONTH_FEBRUARY (0x02U) +#define RTC_MONTH_MARCH (0x03U) +#define RTC_MONTH_APRIL (0x04U) +#define RTC_MONTH_MAY (0x05U) +#define RTC_MONTH_JUNE (0x06U) +#define RTC_MONTH_JULY (0x07U) +#define RTC_MONTH_AUGUST (0x08U) +#define RTC_MONTH_SEPTEMBER (0x09U) +#define RTC_MONTH_OCTOBER (0x0AU) +#define RTC_MONTH_NOVEMBER (0x0BU) +#define RTC_MONTH_DECEMBER (0x0CU) +/** + * @} + */ + +/** + * @defgroup RTC_Weekday RTC Weekday + * @{ + */ +#define RTC_WEEKDAY_SUNDAY (0x00U) +#define RTC_WEEKDAY_MONDAY (0x01U) +#define RTC_WEEKDAY_TUESDAY (0x02U) +#define RTC_WEEKDAY_WEDNESDAY (0x03U) +#define RTC_WEEKDAY_THURSDAY (0x04U) +#define RTC_WEEKDAY_FRIDAY (0x05U) +#define RTC_WEEKDAY_SATURDAY (0x06U) +/** + * @} + */ + +/** + * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday + * @{ + */ +#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U) +#define RTC_ALARM_WEEKDAY_MONDAY (0x02U) +#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U) +#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U) +#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U) +#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U) +#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U) +#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Channel RTC Intrustion Channel + * @{ + */ +#define RTC_INTRU_CH0 (0x00U) +#define RTC_INTRU_CH1 (0x04U) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Timestamp RTC Intrustion Timestamp + * @{ + */ +#define RTC_INTRU_TS_DISABLE (0U) +#define RTC_INTRU_TS_ENABLE (RTC_TPCR0_TSTPE0) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Reset_Backup_Register RTC Intrusion Reset Backup Register + * @{ + */ +#define RTC_INTRU_RST_BACKUP_REG_DISABLE (0U) +#define RTC_INTRU_RST_BACKUP_REG_ENABLE (RTC_TPCR0_TPRSTE0) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Filter RTC Intrusion Filter + * @{ + */ +#define RTC_INTRU_FILTER_INVD (0U) /*!< Invalid filter function */ +#define RTC_INTRU_FILTER_THREE_TIME (RTC_TPCR0_TPNF0_1) /*!< The filter detection is consistent with the timing clock for 3 times */ +#define RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32 (RTC_TPCR0_TPNF0) /*!< The filter detection is consistent with the 32 frequency division of the timing clock for 3 times */ +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Trigger_Edge RTC Intrusion Trigger Edge + * @{ + */ +#define RTC_INTRU_TRIG_EDGE_NONE (0U) /*!< No detect */ +#define RTC_INTRU_TRIG_EDGE_RISING (RTC_TPCR0_TPCT0_0) /*!< Detect rising edge */ +#define RTC_INTRU_TRIG_EDGE_FALLING (RTC_TPCR0_TPCT0_1) /*!< Detect falling edge */ +#define RTC_INTRU_TRIG_EDGE_RISING_FALLING (RTC_TPCR0_TPCT0) /*!< Detect rising and falling edge */ +/** + * @} + */ + +/** + * @defgroup RTC_Flag RTC Flag + * @{ + */ +#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */ +#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */ + +#define RTC_FLAG_PERIOD (RTC_CR2_PRDF) /*!< Period flag */ +#define RTC_FLAG_INTRU_OVF ((uint32_t)RTC_TPSR_TPOVF << 16U) /*!< Intrusion overflow flag */ +#define RTC_FLAG_INTRU_CH0 ((uint32_t)RTC_TPSR_TPF0 << 16U) /*!< RTCIC0 intrusion flag */ +#define RTC_FLAG_INTRU_CH1 ((uint32_t)RTC_TPSR_TPF1 << 16U) /*!< RTCIC1 intrusion flag */ +#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM | RTC_FLAG_PERIOD | \ + RTC_FLAG_INTRU_OVF | RTC_FLAG_INTRU_CH0 | RTC_FLAG_INTRU_CH1) +#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM | RTC_FLAG_PERIOD | \ + RTC_FLAG_INTRU_OVF | RTC_FLAG_INTRU_CH0 | RTC_FLAG_INTRU_CH1) +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt RTC Interrupt + * @{ + */ +#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */ +#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */ + +#define RTC_INT_INTRU_CH0 ((uint32_t)RTC_TPCR0_TPIE0 << 8U) /*!< RTCIC0 intrusion interrupt */ +#define RTC_INT_INTRU_CH1 ((uint32_t)RTC_TPCR1_TPIE1 << 16U) /*!< RTCIC1 intrusion interrupt */ +#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM | RTC_INT_INTRU_CH0 | RTC_INT_INTRU_CH1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RTC_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t RTC_DeInit(void); +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit); +int32_t RTC_EnterRwMode(void); +int32_t RTC_ExitRwMode(void); + +/* Control configuration */ +int32_t RTC_ConfirmLPMCond(void); +void RTC_SetIntPeriod(uint8_t u8Period); +void RTC_SetClockSrc(uint8_t u8Src); +void RTC_SetClockCompenValue(uint16_t u16Value); +en_functional_state_t RTC_GetCounterState(void); +void RTC_Cmd(en_functional_state_t enNewState); +void RTC_LrcCmd(en_functional_state_t enNewState); +void RTC_OneHzOutputCmd(en_functional_state_t enNewState); +void RTC_ClockCompenCmd(en_functional_state_t enNewState); + +/* Date and time functions */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); + +/* Alarm configuration functions */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +void RTC_AlarmCmd(en_functional_state_t enNewState); + +/* Intrusion timestamp functions */ +void RTC_INTRU_DeInit(uint8_t u8Ch); +int32_t RTC_INTRU_Init(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru); +int32_t RTC_INTRU_StructInit(stc_rtc_intrusion_t *pstcIntru); +int32_t RTC_INTRU_GetTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp); +void RTC_INTRU_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t RTC_GetStatus(uint32_t u32Flag); +void RTC_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h new file mode 100644 index 0000000000..4e2efabdb4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h @@ -0,0 +1,763 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.h + * @brief This file contains all the functions prototypes of the SDIOC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SDIOC_H__ +#define __HC32_LL_SDIOC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SDIOC + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Types SDIOC Global Types + * @{ + */ + +/** + * @brief SDIOC Init structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the SDIOC work mode. + This parameter can be a value of @ref SDIOC_Mode */ + uint8_t u8CardDetect; /*!< Specifies the SDIOC card detect way. + This parameter can be a value of @ref SDIOC_Card_Detect_Way */ + uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode. + This parameter can be a value of @ref SDIOC_Speed_Mode */ + uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width. + This parameter can be a value of @ref SDIOC_Bus_Width */ + uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division. + This parameter can be a value of @ref SDIOC_Clock_Division */ +} stc_sdioc_init_t; + +/** + * @brief SDIOC Command Configuration structure definition + */ +typedef struct { + uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */ + uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + uint16_t u16CmdType; /*!< Specifies the SDIOC command type. + This parameter can be a value of @ref SDIOC_Command_Type */ + uint16_t u16DataLine; /*!< Specifies whether SDIOC uses data lines in current command. + This parameter can be a value of @ref SDIOC_Data_Line_Valid */ + uint16_t u16ResponseType; /*!< Specifies the SDIOC response type. + This parameter can be a value of @ref SDIOC_Response_Type */ +} stc_sdioc_cmd_config_t; + +/** + * @brief SDIOC Data Configuration structure definition + */ +typedef struct { + uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size. + This parameter must be a number between Min_Data = 1 and Max_Data = 512 */ + uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */ + uint16_t u16TransDir; /*!< Specifies the SDIOC data transfer direction. + This parameter can be a value of @ref SDIOC_Transfer_Direction */ + uint16_t u16AutoCmd12; /*!< Specifies the validity of the SDIOC Auto Send CMD12. + This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */ + uint16_t u16TransMode; /*!< Specifies the SDIOC data transfer mode. + This parameter can be a value of @ref SDIOC_Transfer_Mode */ + uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time. + This parameter can be a value of @ref SDIOC_Data_Timeout_Time */ +} stc_sdioc_data_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Macros SDIOC Global Macros + * @{ + */ + +/** + * @defgroup SDIOC_Mode SDIOC Mode + * @{ + */ +#define SDIOC_MD_SD (0x00UL) /*!< SDIOCx selects SD mode */ +#define SDIOC_MD_MMC (0x01UL) /*!< SDIOCx selects MMC mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Way SDIOC Card Detect Way + * @{ + */ +#define SDIOC_CARD_DETECT_CD_PIN_LVL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */ +#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level + * @{ + */ +#define SDIOC_CARD_DETECT_TEST_LVL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */ +#define SDIOC_CARD_DETECT_TEST_LVL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Speed_Mode SDIOC Speed Mode + * @{ + */ +#define SDIOC_SPEED_MD_NORMAL (0x00U) /*!< Normal speed mode */ +#define SDIOC_SPEED_MD_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Bus_Width SDIOC Bus Width + * @{ + */ +#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */ +#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */ +#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Clock_Division SDIOC Clock Division + * @{ + */ +#define SDIOC_CLK_DIV1 (0x00U) /*!< CLK1/1 */ +#define SDIOC_CLK_DIV2 (SDIOC_CLKCON_FS_0) /*!< CLK1/2 */ +#define SDIOC_CLK_DIV4 (SDIOC_CLKCON_FS_1) /*!< CLK1/4 */ +#define SDIOC_CLK_DIV8 (SDIOC_CLKCON_FS_2) /*!< CLK1/8 */ +#define SDIOC_CLK_DIV16 (SDIOC_CLKCON_FS_3) /*!< CLK1/16 */ +#define SDIOC_CLK_DIV32 (SDIOC_CLKCON_FS_4) /*!< CLK1/32 */ +#define SDIOC_CLK_DIV64 (SDIOC_CLKCON_FS_5) /*!< CLK1/64 */ +#define SDIOC_CLK_DIV128 (SDIOC_CLKCON_FS_6) /*!< CLK1/128 */ +#define SDIOC_CLK_DIV256 (SDIOC_CLKCON_FS_7) /*!< CLK1/256 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Command_Type SDIOC Command Type + * @{ + */ +#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */ +#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */ +#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */ +#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid + * @{ + */ +#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */ +#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction + * @{ + */ +#define SDIOC_TRANS_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */ +#define SDIOC_TRANS_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12 + * @{ + */ +#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */ +#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode + * @{ + */ +#define SDIOC_TRANS_MD_SINGLE (0x00U) /*!< Single Block transfer */ +#define SDIOC_TRANS_MD_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */ +#define SDIOC_TRANS_MD_MULTI (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */ +#define SDIOC_TRANS_MD_STOP_MULTI (0x8000U | SDIOC_TRANS_MD_MULTI) /*!< Stop Multiple Block transfer */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time + * @{ + */ +#define SDIOC_DATA_TIMEOUT_CLK_2E13 (0x00U) /*!< Timeout time: CLK1*2^13 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E14 (0x01U) /*!< Timeout time: CLK1*2^14 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E15 (0x02U) /*!< Timeout time: CLK1*2^15 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E16 (0x03U) /*!< Timeout time: CLK1*2^16 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E17 (0x04U) /*!< Timeout time: CLK1*2^17 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E18 (0x05U) /*!< Timeout time: CLK1*2^18 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E19 (0x06U) /*!< Timeout time: CLK1*2^19 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E20 (0x07U) /*!< Timeout time: CLK1*2^20 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E21 (0x08U) /*!< Timeout time: CLK1*2^21 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E22 (0x09U) /*!< Timeout time: CLK1*2^22 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E23 (0x0AU) /*!< Timeout time: CLK1*2^23 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E24 (0x0BU) /*!< Timeout time: CLK1*2^24 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E25 (0x0CU) /*!< Timeout time: CLK1*2^25 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E26 (0x0DU) /*!< Timeout time: CLK1*2^26 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E27 (0x0EU) /*!< Timeout time: CLK1*2^27 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Register SDIOC Response Register + * @{ + */ +#define SDIOC_RESP_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */ +#define SDIOC_RESP_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */ +#define SDIOC_RESP_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */ +#define SDIOC_RESP_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Software_Reset_Type SDIOC Software Reset Type + * @{ + */ +#define SDIOC_SW_RST_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */ +#define SDIOC_SW_RST_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */ +#define SDIOC_SW_RST_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency + * @{ + */ +#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */ +#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Host_Flag SDIOC Host Flag + * @{ + */ +#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */ +#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */ +#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */ +#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */ +#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */ +#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */ +#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */ +#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */ +#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */ +#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */ +#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */ +#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */ +#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */ +#define SDIOC_HOST_FLAG_ALL (SDIOC_HOST_FLAG_CMDL | SDIOC_HOST_FLAG_DATL | SDIOC_HOST_FLAG_WPL | \ + SDIOC_HOST_FLAG_CDL | SDIOC_HOST_FLAG_CSS | SDIOC_HOST_FLAG_CIN | \ + SDIOC_HOST_FLAG_BRE | SDIOC_HOST_FLAG_BWE | SDIOC_HOST_FLAG_RTA | \ + SDIOC_HOST_FLAG_WTA | SDIOC_HOST_FLAG_DA | SDIOC_HOST_FLAG_CID | \ + SDIOC_HOST_FLAG_CIC) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt_Flag SDIOC Interrupt Flag + * @{ + */ +#define SDIOC_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */ +#define SDIOC_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */ +#define SDIOC_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */ +#define SDIOC_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */ +#define SDIOC_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */ +#define SDIOC_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */ +#define SDIOC_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */ +#define SDIOC_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */ +#define SDIOC_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */ +#define SDIOC_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */ +#define SDIOC_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */ +#define SDIOC_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */ +#define SDIOC_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */ +#define SDIOC_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */ +#define SDIOC_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */ +#define SDIOC_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */ +#define SDIOC_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */ +#define SDIOC_INT_STATIC_FLAGS (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC) +#define SDIOC_NORMAL_INT_FLAG_ALL (SDIOC_INT_FLAG_EI | SDIOC_INT_FLAG_CINT | SDIOC_INT_FLAG_CRM | \ + SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | SDIOC_INT_FLAG_BWR | \ + SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | SDIOC_INT_FLAG_CC) +#define SDIOC_ERR_INT_FLAG_ALL (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE) +#define SDIOC_INT_FLAG_ALL (SDIOC_NORMAL_INT_FLAG_ALL | SDIOC_ERR_INT_FLAG_ALL) +#define SDIOC_INT_FLAG_CLR_ALL (SDIOC_INT_FLAG_CRM | SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | \ + SDIOC_INT_FLAG_BWR | SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC | SDIOC_ERR_INT_FLAG_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt SDIOC Interrupt + * @{ + */ +#define SDIOC_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */ +#define SDIOC_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */ +#define SDIOC_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */ +#define SDIOC_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */ +#define SDIOC_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */ +#define SDIOC_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */ +#define SDIOC_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */ +#define SDIOC_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */ +#define SDIOC_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */ +#define SDIOC_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */ +#define SDIOC_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */ +#define SDIOC_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */ +#define SDIOC_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */ +#define SDIOC_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */ +#define SDIOC_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */ +#define SDIOC_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */ +#define SDIOC_NORMAL_INT_ALL (SDIOC_INT_CINTSEN | SDIOC_INT_CRMSEN | SDIOC_INT_CISTSEN | \ + SDIOC_INT_BRRSEN | SDIOC_INT_BWRSEN | SDIOC_INT_BGESEN | \ + SDIOC_INT_TCSEN | SDIOC_INT_CCSEN) +#define SDIOC_ERR_INT_ALL (SDIOC_INT_ACESEN | SDIOC_INT_DEBESEN | SDIOC_INT_DCESEN | \ + SDIOC_INT_DTOESEN | SDIOC_INT_CIESEN | SDIOC_INT_CEBESEN | \ + SDIOC_INT_CCESEN | SDIOC_INT_CTOESEN) +#define SDIOC_INT_ALL (SDIOC_NORMAL_INT_ALL | SDIOC_ERR_INT_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_CMD_Error_Flag SDIOC Auto CMD Error Flag + * @{ + */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_ALL (SDIOC_AUTO_CMD_ERR_FLAG_CMDE | SDIOC_AUTO_CMD_ERR_FLAG_IE | \ + SDIOC_AUTO_CMD_ERR_FLAG_EBE | SDIOC_AUTO_CMD_ERR_FLAG_CE | \ + SDIOC_AUTO_CMD_ERR_FLAG_TOE | SDIOC_AUTO_CMD_ERR_FLAG_NE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error + * @{ + */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */ +#define SDIOC_FORCE_AUTO_CMD_ERR_ALL (SDIOC_FORCE_AUTO_CMD_ERR_FCMDE | SDIOC_FORCE_AUTO_CMD_ERR_FIE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FEBE | SDIOC_FORCE_AUTO_CMD_ERR_FCE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FTOE | SDIOC_FORCE_AUTO_CMD_ERR_FNE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt + * @{ + */ +#define SDIOC_FORCE_ERR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */ +#define SDIOC_FORCE_ERR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */ +#define SDIOC_FORCE_ERR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */ +#define SDIOC_FORCE_ERR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */ +#define SDIOC_FORCE_ERR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */ +#define SDIOC_FORCE_ERR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */ +#define SDIOC_FORCE_ERR_INT_ALL (SDIOC_FORCE_ERR_INT_FACE | SDIOC_FORCE_ERR_INT_FDEBE | \ + SDIOC_FORCE_ERR_INT_FDCE | SDIOC_FORCE_ERR_INT_FDTOE | \ + SDIOC_FORCE_ERR_INT_FCIE | SDIOC_FORCE_ERR_INT_FCEBE | \ + SDIOC_FORCE_ERR_INT_FCCE | SDIOC_FORCE_ERR_INT_FCTOE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Type SDIOC Response Type + * @{ + */ +#define SDIOC_RESP_TYPE_NO (0x00U) /*!< No Response */ +#define SDIOC_RESP_TYPE_R2 (SDIOC_CMD_RESTYP_0) /*!< Command Response 2 */ +#define SDIOC_RESP_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */ +#define SDIOC_RESP_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */ +#define SDIOC_RESP_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */ +/** + * @} + */ + +#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */ +#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */ +#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \ + operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \ + and asks the card whether card supports voltage. */ +#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */ +#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */ +#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */ +#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */ +#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */ +#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \ + Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ +#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD18_READ_MULTI_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \ + STOP_TRANSMISSION command. */ +#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */ +#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD25_WRITE_MULTI_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */ +#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDIOC_CMD35_ERASE_GROUP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \ + set by switch function command (CMD6). */ +#define SDIOC_CMD36_ERASE_GROUP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \ + Reserved for each command system set by switch function command (CMD6). */ +#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */ +#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \ + the SET_BLOCK_LEN command. */ +#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \ + than a standard command. */ +#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \ + for general purpose/application specific commands. */ +#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * @note SDIOC_CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \ + widths are given in SCR register. */ +#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */ +#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \ + 32bit+CRC data block. */ +#define SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT (23U) /*!< Set the number of write blocks to be pre-erased before writing (to be used for faster \ + Multiple Block WR com-mand). */ +#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \ + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDIOC_ACMD52_RW_DIRECT (52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDIOC_ACMD53_RW_EXTENDED (53U) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * @note SDIOC_CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD43_GET_MKB (43U) +#define SDIOC_ACMD44_GET_MID (44U) +#define SDIOC_ACMD45_SET_CER_RN1 (45U) +#define SDIOC_ACMD46_GET_CER_RN2 (46U) +#define SDIOC_ACMD47_SET_CER_RES2 (47U) +#define SDIOC_ACMD48_GET_CER_RES1 (48U) +#define SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK (18U) +#define SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK (25U) +#define SDIOC_ACMD38_SECURE_ERASE (38U) +#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U) +#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U) + +/** + * @defgroup SDMMC_Error_Code SDMMC Error Code + * @{ + */ +#define SDMMC_ERR_NONE (0x00000000UL) /*!< No error */ +#define SDMMC_ERR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */ +#define SDMMC_ERR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */ +#define SDMMC_ERR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \ + number of transferred bytes does not match the block length */ +#define SDMMC_ERR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */ +#define SDMMC_ERR_WR_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */ +#define SDMMC_ERR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \ + or if there was an attempt to access a locked card */ +#define SDMMC_ERR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */ +#define SDMMC_ERR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */ +#define SDMMC_ERR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERR_CC_ERR (0x00100000UL) /*!< Internal card controller error */ +#define SDMMC_ERR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */ +#define SDMMC_ERR_STREAM_RD_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERR_STREAM_WR_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */ +#define SDMMC_ERR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */ +#define SDMMC_ERR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERR_ERASE_RST (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \ + erase sequence command was received */ +#define SDMMC_ERR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */ +#define SDMMC_ERR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */ +#define SDMMC_ERR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */ +#define SDMMC_ERR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */ +#define SDMMC_ERR_SWITCH_ERR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \ + the SWITCH command */ +#define SDMMC_ERR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */ +#define SDMMC_ERR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */ +#define SDMMC_ERR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */ +#define SDMMC_ERR_INVD_VOLT (0x00000004UL) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERR_REQ_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */ +#define SDMMC_ERR_UNSUPPORT_FEATURE (0x00000001UL) /*!< Error when feature is not insupported */ + +#define SDMMC_ERR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */ +/** + * @} + */ + +/** + * @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit + * @{ + */ +#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U) +#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */ +#define SDMMC_STATUS_CURR_STATE_POS (9U) +#define SDMMC_STATUS_CURR_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */ +#define SDMMC_STATUS_RDY_FOR_DATA_POS (8U) +#define SDMMC_STATUS_RDY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */ +#define SDMMC_STATUS_APP_CMD_POS (5U) +#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */ +/** + * @} + */ + +/** + * @defgroup SDMMC_SCR_Register SDMMC SCR Register + * @{ + */ +#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL) +#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL) +#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_OCR_Register SDMMC OCR Register + * @{ + */ +#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL) +#define SDMMC_OCR_STD_CAPACITY (0x00000000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_CSD_Register SDMMC CSD Register + * @{ + */ +/* Command Class supported */ +#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_Common_Parameter SDMMC Common Parameter + * @{ + */ +#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL) +#define SDMMC_MAX_VOLT_TRIAL (0x0000FFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SDIOC_Global_Functions + * @{ + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx); +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type); +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx); +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div); +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div); +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv); +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode); +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth); +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src); +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level); + +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value); +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len); +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len); + +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); + +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType); +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag); +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); + +/* SDMMC Commands management functions */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); + +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD41_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); + +int32_t SDMMC_CMD1_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h new file mode 100644 index 0000000000..8d437c5739 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h @@ -0,0 +1,396 @@ +/** + ******************************************************************************* + * @file hc32_ll_smc.h + * @brief This file contains all the functions prototypes of the EXMC_SMC + * (External Memory Controller: Static Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SMC_H__ +#define __HC32_LL_SMC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EXMC + * @{ + */ + +/** + * @addtogroup LL_SMC + * @{ + */ + +#if (LL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Types EXMC_SMC Global Types + * @{ + */ + +/** + * @brief EXMC_SMC Chip Configuration Structure definition + */ +typedef struct { + uint32_t u32ReadMode; /*!< Defines the read sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */ + uint32_t u32WriteMode; /*!< Defines the write sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */ + uint32_t u32ReadBurstLen; /*!< Defines the number of read data access. + This parameter can be a value of @ref EXMC_SMC_Memory_Read_Burst_Length. */ + uint32_t u32WriteBurstLen; /*!< Defines the number of write data access. + This parameter can be a value of @ref EXMC_SMC_Memory_Write_Burst_Length. */ + uint32_t u32MemoryWidth; /*!< Defines the SMC memory width. + This parameter can be a value of @ref EXMC_SMC_Memory_Width. */ + uint32_t u32BAA; /*!< Defines the SMC BAA signal enable. + This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */ + uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable. + This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */ + uint32_t u32BLS; /*!< Defines the SMC BLS signal selection. + This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */ + uint32_t u32AddrMatch; /*!< Defines the address match. + This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */ + uint32_t u32AddrMask; /*!< Defines the address mask. + This parameter can be a value of @ref EXMC_SMC_Mask_Address. */ +} stc_exmc_smc_chip_config_t; + +/** + * @brief EXMC_SMC Timing Configuration Structure definition + */ +typedef struct { + uint8_t u8RC; /*!< Defines the RC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8WC; /*!< Defines the WC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8CEOE; /*!< Defines the CEOE in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8WP; /*!< Defines the WP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8PC; /*!< Defines the PC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8TR; /*!< Defines the TR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ +} stc_exmc_smc_timing_config_t; + +/** + * @brief EXMC_SMC Initialization Structure definition + */ +typedef struct { + stc_exmc_smc_chip_config_t stcChipConfig; /*!< SMC memory chip configure. + This structure details refer @ref stc_exmc_smc_chip_config_t. */ + stc_exmc_smc_timing_config_t stcTimingConfig; /*!< SMC memory timing configure. + This structure details refer @ref stc_exmc_smc_timing_config_t. */ +} stc_exmc_smc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Macros EXMC_SMC Global Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Chip EXMC_SMC Chip + * @{ + */ +#define EXMC_SMC_CHIP0 (0UL) /*!< Chip 0 */ +#define EXMC_SMC_CHIP1 (1UL) /*!< Chip 1 */ +#define EXMC_SMC_CHIP2 (2UL) /*!< Chip 2 */ +#define EXMC_SMC_CHIP3 (3UL) /*!< Chip 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Read_Mode EXMC_SMC Memory Read Mode + * @{ + */ +#define EXMC_SMC_READ_ASYNC (0UL) +#define EXMC_SMC_READ_SYNC (SMC_CPCR_RSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Write_Mode EXMC_SMC Memory Write Mode + * @{ + */ +#define EXMC_SMC_WRITE_ASYNC (0UL) +#define EXMC_SMC_WRITE_SYNC (SMC_CPCR_WSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Read_Burst_Length EXMC_SMC Memory Read Burst Length + * @{ + */ +#define EXMC_SMC_READ_BURST_1BEAT (0UL) +#define EXMC_SMC_READ_BURST_4BEAT (1UL << SMC_CPCR_RBL_POS) +#define EXMC_SMC_READ_BURST_8BEAT (2UL << SMC_CPCR_RBL_POS) +#define EXMC_SMC_READ_BURST_16BEAT (3UL << SMC_CPCR_RBL_POS) +#define EXMC_SMC_READ_BURST_32BEAT (4UL << SMC_CPCR_RBL_POS) +#define EXMC_SMC_READ_BURST_CONTINUOUS (5UL << SMC_CPCR_RBL_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Write_Burst_Length EXMC_SMC Memory Write Burst Length + * @{ + */ +#define EXMC_SMC_WRITE_BURST_1BEAT (0UL) +#define EXMC_SMC_WRITE_BURST_4BEAT (1UL << SMC_CPCR_WBL_POS) +#define EXMC_SMC_WRITE_BURST_8BEAT (2UL << SMC_CPCR_WBL_POS) +#define EXMC_SMC_WRITE_BURST_16BEAT (3UL << SMC_CPCR_WBL_POS) +#define EXMC_SMC_WRITE_BURST_32BEAT (4UL << SMC_CPCR_WBL_POS) +#define EXMC_SMC_WRITE_BURST_CONTINUOUS (5UL << SMC_CPCR_WBL_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Width EXMC_SMC Memory Width + * @{ + */ +#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0) +#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BAA_Port_Selection EXMC_SMC BAA Port Selection + * @{ + */ +#define EXMC_SMC_BAA_PORT_DISABLE (0UL) +#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_ADV_Port_Selection EXMC_SMC ADV Port Selection + * @{ + */ +#define EXMC_SMC_ADV_PORT_DISABLE (0UL) +#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC_SMC BLS Synchronization Selection + * @{ + */ +#define EXMC_SMC_BLS_SYNC_CS (0UL) +#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Command EXMC_SMC Command + * @{ + */ +#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */ +#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */ +#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_CRE_Polarity EXMC_SMC CRE Polarity + * @{ + */ +#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */ +#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Status EXMC_SMC Status + * @{ + */ +#define EXMC_SMC_READY (0UL) /*!< SMC is ready */ +#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Sample_Clock EXMC_SMC Sample Clock + * @{ + */ +#define EXMC_SMC_SAMPLE_CLK_INTERNCLK (0UL) /*!< Internal EXCLK */ +#define EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT (SMC_BACR_CKSEL_0) /*!< Invert internal EXCLK */ +#define EXMC_SMC_SAMPLE_CLK_EXTCLK (SMC_BACR_CKSEL_1) /*!< External clock from EXMC_CLK port */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Mask_Address EXMC_SMC Mask Address + * @{ + */ +#define EXMC_SMC_ADDR_MASK_16MB (0xFFUL) +#define EXMC_SMC_ADDR_MASK_32MB (0xFEUL) +#define EXMC_SMC_ADDR_MASK_64MB (0xFCUL) +#define EXMC_SMC_ADDR_MASK_128MB (0xF8UL) +#define EXMC_SMC_ADDR_MASK_256MB (0xF0UL) +#define EXMC_SMC_ADDR_MASK_512MB (0xE0UL) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Address_Space EXMC_SMC Address Space + * @{ + */ +#define EXMC_SMC_ADDR_MIN (0x60000000UL) +#define EXMC_SMC_ADDR_MAX (0x7FFFFFFFUL) +/** + * @} + */ + +/** + * @brief SMC device memory address shifting. + * @param [in] mem_base_addr SMC base address + * @param [in] mem_width SMC memory width + * @param [in] addr SMC device memory address + * @retval SMC device shifted address value + */ +#define SMC_ADDR_SHIFT(mem_base_addr, mem_width, addr) \ +( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_addr) + ((addr) << 1U))) : \ + (((mem_base_addr) + ((addr) << 2U))))) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_SMC_Global_Functions + * @{ + */ + +/** + * @brief SMC entry low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_EntryLowPower(void) +{ + WRITE_REG32(CM_SMC->STCR0, SMC_STCR0_LPWIR); +} + +/** + * @brief SMC exit low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_ExitLowPower(void) +{ + WRITE_REG32(CM_SMC->STCR1, SMC_STCR1_LPWOR); +} + +/** + * @brief Get SMC status + * @param None + * @retval Returned value can be one of the macros group @ref EXMC_SMC_Status + * - EXMC_SMC_READY: SMC is ready + * - EXMC_SMC_LOWPOWER: SMC is low power + */ +__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void) +{ + return READ_REG32_BIT(CM_SMC->STSR, SMC_STSR_STATUS); +} + +/* Initialization and configuration EXMC_SMC functions */ +int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit); +int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit); +void EXMC_SMC_DeInit(void); + +void EXMC_SMC_Cmd(en_functional_state_t enNewState); +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState); +void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock); +void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal); + +void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr); +uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip); +uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip); +int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig); +int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig); + +/** + * @} + */ + +#endif /* LL_SMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SMC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h new file mode 100644 index 0000000000..e5f482dcef --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h @@ -0,0 +1,432 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SPI_H__ +#define __HC32_LL_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SPI + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + */ +typedef struct { + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Trans_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32SuspendMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct { + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define + * @{ + */ +#define SPI_4_WIRE (0UL) +#define SPI_3_WIRE (SPI_CR1_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR1_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_LOOPBACK_INVD (0UL) +#define SPI_LOOPBACK_MOSI_INVT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_LOOPBACK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Int_Type_Define SPI Interrupt Type Define + * @{ + */ +#define SPI_INT_ERR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUF_EMPTY (SPI_CR1_TXIE) +#define SPI_INT_RX_BUF_FULL (SPI_CR1_RXIE) +#define SPI_INT_IDLE (SPI_CR1_IDIE) +#define SPI_IRQ_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE ) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define + * @{ + */ +#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define + * @{ + */ +#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx Define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF + * after enough data frame write to the SPI_DR + * @{ + */ +#define SPI_1_FRAME (0UL) /*!< Data 1 frame */ +#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_4_FRAME (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */ +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode Define + * @{ + */ +#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ +#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ + +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define + * @{ + */ +#define SPI_BR_CLK_DIV2 (0UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 2. */ +#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 4. */ +#define SPI_BR_CLK_DIV8 (2UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 8. */ +#define SPI_BR_CLK_DIV16 (3UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 16. */ +#define SPI_BR_CLK_DIV32 (4UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 32. */ +#define SPI_BR_CLK_DIV64 (5UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 64. */ +#define SPI_BR_CLK_DIV128 (6UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 128. */ +#define SPI_BR_CLK_DIV256 (7UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 256. */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI Data Size Define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS) + +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI First Bit Define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI State Flag Define + * @{ + */ +#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF) +#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */ +#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERLOAD) +#define SPI_FLAG_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \ + SPI_FLAG_UNDERLOAD | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit); +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit); +void SPI_DeInit(CM_SPI_TypeDef *SPIx); + +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState); + +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig); +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig); + +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout); +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout); +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h new file mode 100644 index 0000000000..3f730564e4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h @@ -0,0 +1,235 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.h + * @brief This file contains all the functions prototypes of the SRAM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SRAM_H__ +#define __HC32_LL_SRAM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SRAM + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Macros SRAM Global Macros + * @{ + */ + +/** + * @defgroup SRAM_Sel SRAM Selection + * @{ + */ +/* SRAM selection */ +#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFE0000~0x1FFFFFFF, 128KB */ +#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB + SRAM2: 0x20020000~0x2003FFFF, 128KB + SRAM3: 0x20040000~0x20057FFF, 96KB */ +#define SRAM_SRAM4 (1UL << 1U) /*!< SRAM4: 0x20058000~0x2005FFFF, 32KB */ +#define SRAM_SRAMB (1UL << 3U) /*!< SRAMB: 0x200F0000~0x200F0FFF, 4KB */ +#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB) +#define SRAM_ECC_SRAM4 (SRAM_SRAM4) +#define SRAM_ECC_SRAMB (SRAM_SRAMB) + +/** + * @} + */ + +/** + * @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle + * @{ + */ +#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */ +#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */ +#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */ +#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */ +#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */ +#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */ +#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */ +#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Mode SRAM Error Mode + * @note Even-parity check error, ECC check error. + * @{ + */ +#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurres while check error occurres. */ +#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurres while check error occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_Mode SRAM ECC Mode + * @{ + */ +#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */ +#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: + ECC error corrects. + No 1-bit-error status flag setting, no interrupt or reset. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: + ECC error corrects. + 1-bit-error status flag sets, no interrupt or reset. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurres: + ECC error corrects. + 1-bit-error status flag sets and interrupt or reset occurres. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag + * @{ + */ +#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */ +#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */ +#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */ +#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */ +#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */ +#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */ +#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */ +#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */ +#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */ +#define SRAM_FLAG_ALL (0x1FFUL) +/** + * @} + */ + +/** + * @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key + * @{ + */ +#define SRAM_REG_LOCK_KEY (0x76U) +#define SRAM_REG_UNLOCK_KEY (0x77U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SRAM_Global_Functions + * @{ + */ + +/** + * @brief Lock SRAM registers, write protect. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Lock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY); +} + +/** + * @brief Unlock SRAM registers, write enable. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Unlock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY); +} + +void SRAM_Init(void); +void SRAM_DeInit(void); + +void SRAM_REG_Lock(void); +void SRAM_REG_Unlock(void); + +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle); +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode); +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode); + +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag); +void SRAM_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SRAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h new file mode 100644 index 0000000000..2752bb1d6c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h @@ -0,0 +1,226 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.h + * @brief This file contains all the functions prototypes of the SWDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SWDT_H__ +#define __HC32_LL_SWDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SWDT + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Types SWDT Global Types + * @{ + */ + +/** + * @brief SWDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of SWDT. + This parameter can be a value of @ref SWDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of SWDT. + This parameter can be a value of @ref SWDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of SWDT. + This parameter can be a value of @ref SWDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep/Stop Mode). + This parameter can be a value of @ref SWDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for SWDT. + This parameter can be a value of @ref SWDT_Exception_Type */ +} stc_swdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Macros SWDT Global Macros + * @{ + */ + +/** + * @defgroup SWDT_Count_Period SWDT Count Period + * @{ + */ +#define SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define SWDT_CNT_PERIOD4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define SWDT_CNT_PERIOD16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define SWDT_CNT_PERIOD65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup SWDT_Clock_Division SWDT Clock Division + * @{ + */ +#define SWDT_CLK_DIV1 (0UL) /*!< SWDTCLK/1 */ +#define SWDT_CLK_DIV16 (0x04UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/16 */ +#define SWDT_CLK_DIV32 (0x05UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/32 */ +#define SWDT_CLK_DIV64 (0x06UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/64 */ +#define SWDT_CLK_DIV128 (0x07UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/128 */ +#define SWDT_CLK_DIV256 (0x08UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/256 */ +#define SWDT_CLK_DIV2048 (0x0BUL << SWDT_CR_CKS_POS) /*!< SWDTCLK/2048 */ +/** + * @} + */ + +/** + * @defgroup SWDT_Refresh_Range SWDT Refresh Range + * @{ + */ +#define SWDT_RANGE_0TO25PCT (0x01UL << SWDT_CR_WDPT_POS) /*!< 0%~25% */ +#define SWDT_RANGE_25TO50PCT (0x02UL << SWDT_CR_WDPT_POS) /*!< 25%~50% */ +#define SWDT_RANGE_0TO50PCT (0x03UL << SWDT_CR_WDPT_POS) /*!< 0%~50% */ +#define SWDT_RANGE_50TO75PCT (0x04UL << SWDT_CR_WDPT_POS) /*!< 50%~75% */ +#define SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define SWDT_RANGE_25TO75PCT (0x06UL << SWDT_CR_WDPT_POS) /*!< 25%~75% */ +#define SWDT_RANGE_0TO75PCT (0x07UL << SWDT_CR_WDPT_POS) /*!< 0%~75% */ +#define SWDT_RANGE_75TO100PCT (0x08UL << SWDT_CR_WDPT_POS) /*!< 75%~100% */ +#define SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << SWDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << SWDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define SWDT_RANGE_50TO100PCT (0x0CUL << SWDT_CR_WDPT_POS) /*!< 50%~100% */ +#define SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define SWDT_RANGE_25TO100PCT (0x0EUL << SWDT_CR_WDPT_POS) /*!< 25%~100% */ +#define SWDT_RANGE_0TO100PCT (0x0FUL << SWDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup SWDT_LPM_Count SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode. + * @{ + */ +#define SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */ +#define SWDT_LPM_CNT_STOP (SWDT_CR_SLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/** + * @defgroup SWDT_Exception_Type SWDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define SWDT_EXP_TYPE_RST (SWDT_CR_ITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup SWDT_Flag SWDT Flag + * @{ + */ +#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */ +#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */ +#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Get SWDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t SWDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit); +void SWDT_FeedDog(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag); +int32_t SWDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h new file mode 100644 index 0000000000..b6ddbcbf16 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.h + * @brief This file contains all the functions prototypes of the TMR0 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR0_H__ +#define __HC32_LL_TMR0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR0 + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Types TMR0 Global Types + * @{ + */ + +/** + * @brief TMR0 initialization structure definition + * @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT". + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Source */ + uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Division */ + uint32_t u32Func; /*!< Specifies the function of TMR0 channel. + This parameter can be a value of @ref TMR0_Function */ + uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel. + This parameter can be a value of half-word */ +} stc_tmr0_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Macros TMR0 Global Macros + * @{ + */ + +/** + * @defgroup TMR0_Channel TMR0 Channel + * @note TMR0 on the HC32F120,HC32F160 and HC32M120 chips is only "TMR0_CH_A". + * @{ + */ +#define TMR0_CH_A (0UL) +#define TMR0_CH_B (1UL) +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Source TMR0 Clock Source + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + * @{ + */ +#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */ +#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */ +#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */ +#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */ +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Division TMR0 Clock Division + * @{ + */ +#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */ +#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */ +#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */ +#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */ +#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */ +#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */ +#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */ +#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */ +#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */ +#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */ +#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR0_Function TMR0 Function + * @{ + */ +#define TMR0_FUNC_CMP (0UL) /*!< Output comare function */ +#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */ +/** + * @} + */ + +/** + * @defgroup TMR0_Interrupt TMR0 Interrupt + * @{ + */ +#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA) + +#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB) +#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B) +/** + * @} + */ + +/** + * @defgroup TMR0_FLAG TMR0 Flag + * @{ + */ +#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA) + +#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB) +#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR0_Global_Functions + * @{ + */ + +/* Initialization functions */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x); +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init); +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init); +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); + +/* Control configuration functions */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src); +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div); +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func); + +/* Hardware trigger Functions */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr2.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr2.h new file mode 100644 index 0000000000..61ad07bd22 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr2.h @@ -0,0 +1,352 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr2.h + * @brief This file contains all the functions prototypes of the TMR2(Timer2) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR2_H__ +#define __HC32_LL_TMR2_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR2 + * @{ + */ +#if (LL_TMR2_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR2_Global_Types TMR2 Global Types + * @{ + */ + +/** + * @brief TMR2 PWM configuration structure. + */ +typedef struct { + uint32_t u32StartPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting start. + This parameter can be a value of @ref TMR2_PWM_Polarity */ + uint32_t u32StopPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting stop. + This parameter can be a value of @ref TMR2_PWM_Polarity */ + uint32_t u32CompareMatchPolarity; /*!< Specifies the polarity of PWM output when TMR2 counter matches the compare value. + This parameter can be a value of @ref TMR2_PWM_Polarity */ +} stc_tmr2_pwm_init_t; + +/** + * @brief TMR2 initialization structure. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source for TMR2 channel. + This parameter can be a value of @ref TMR2_Clock_Source */ + uint32_t u32ClockDiv; /*!< Specifies the division of the clock source. + This parameter can be a value of @ref TMR2_Clock_Divider */ + uint32_t u32Func; /*!< Specifies the function mode for TMR2 channel. + This parameter can be a value of @ref TMR2_Function */ + uint32_t u32CompareValue; /*!< Specifies the compare value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ +} stc_tmr2_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR2_Global_Macros TMR2 Global Macros + * @{ + */ + +/** + * @defgroup TMR2_Channel TMR2 Channel + * @{ + */ +#define TMR2_CH_A (0U) /*!< Channel A of TMR2. */ +#define TMR2_CH_B (1U) /*!< Channel B of TMR2. */ +/** + * @} + */ + +/** + * @defgroup TMR2_Function TMR2 Function + * @{ + */ +#define TMR2_FUNC_CMP (0x0U) /*!< The function of TMR2 channel is ouput compare. */ +#define TMR2_FUNC_CAPT (TMR2_BCONR_CAPMDA) /*!< The function of TMR2 channel is input capture. */ +/** + * @} + */ + +/** + * @defgroup TMR2_Clock_Source TMR2 Clock Source + * @{ + */ +#define TMR2_CLK_PCLK1 (0x0U) /*!< Synchronous clock source, PCLK1. */ +#define TMR2_CLK_TRIG_RISING (TMR2_BCONR_SYNCLKA_0) /*!< Synchronous clock source, rising edge of TIM2__TRIGA/B. + One rising edge causes one count. */ +#define TMR2_CLK_TRIG_FALLING (TMR2_BCONR_SYNCLKA_1) /*!< Synchronous clock source, falling edge of TIM2__TRIGA/B. + One falling edge causes one count. */ +#define TMR2_CLK_EVT (TMR2_BCONR_SYNCLKA) /*!< Synchronous clock source, peripheral event. The event is specified by register TMR2_HTSSR. + One event causes one count. */ +#define TMR2_CLK_TMR6_OVF (TMR2_BCONR_SYNCLKAT_0) /*!< Synchronous clock source, the event of counting overflow of TIMER6. + It is NOT need to set register TMR2_HTSSR. */ +#define TMR2_CLK_TMR6_UDF (TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, the event of counting underflow of TIMER6. + It is NOT need to set register TMR2_HTSSR. */ +#define TMR2_CLK_TMR6_OVF_UDF (TMR2_BCONR_SYNCLKAT_0 | \ + TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, both overflow and underflow of TIMER6. */ +#define TMR2_CLK_LRC (TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, LRC(32.768KHz). */ +#define TMR2_CLK_XTAL32 (TMR2_BCONR_ASYNCLKA_0 | \ + TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, XTAL32(32.768KHz). */ +#define TMR2_CLK_PIN_CLK (TMR2_BCONR_ASYNCLKA_1 | \ + TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, input from pin TIM2__CLKA/B. */ +/** + * @} + */ + +/** + * @defgroup TMR2_Clock_Divider TMR2 Clock Divider + * @{ + */ +#define TMR2_CLK_DIV1 (0x0U) /*!< Clock source. */ +#define TMR2_CLK_DIV2 (0x1UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 2. */ +#define TMR2_CLK_DIV4 (0x2UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 4. */ +#define TMR2_CLK_DIV8 (0x3UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 8. */ +#define TMR2_CLK_DIV16 (0x4UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 16. */ +#define TMR2_CLK_DIV32 (0x5UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 32. */ +#define TMR2_CLK_DIV64 (0x6UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 64. */ +#define TMR2_CLK_DIV128 (0x7UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 128. */ +#define TMR2_CLK_DIV256 (0x8UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 256. */ +#define TMR2_CLK_DIV512 (0x9UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 512. */ +#define TMR2_CLK_DIV1024 (0xAUL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMR2_Interrupt_Type TMR2 Interrupt Type + * @{ + */ +#define TMR2_INT_MATCH_CH_A (TMR2_ICONR_CMENA) /*!< TMR2 count match interrupt. */ +#define TMR2_INT_OVF_CH_A (TMR2_ICONR_OVENA) /*!< TMR2 count overflow interrupt. */ +#define TMR2_INT_MATCH_CH_B (TMR2_ICONR_CMENB) /*!< TMR2 count match interrupt. */ +#define TMR2_INT_OVF_CH_B (TMR2_ICONR_OVENB) /*!< TMR2 count overflow interrupt. */ +#define TMR2_INT_ALL (TMR2_INT_MATCH_CH_A | TMR2_INT_OVF_CH_A | \ + TMR2_INT_MATCH_CH_B | TMR2_INT_OVF_CH_B) +/** + * @} + */ + +/** + * @defgroup TMR2_Status_Flag TMR2 Status Flag + * @{ + */ +#define TMR2_FLAG_MATCH_CH_A (TMR2_STFLR_CMFA) /*!< Counter match flag of channel A. */ +#define TMR2_FLAG_OVF_CH_A (TMR2_STFLR_OVFA) /*!< Counter overflow flag channel A. */ +#define TMR2_FLAG_MATCH_CH_B (TMR2_STFLR_CMFB) /*!< Counter match flag channel B. */ +#define TMR2_FLAG_OVF_CH_B (TMR2_STFLR_OVFB) /*!< Counter overflow flag channel B. */ +#define TMR2_FLAG_ALL (TMR2_FLAG_MATCH_CH_A | TMR2_FLAG_OVF_CH_A | \ + TMR2_FLAG_MATCH_CH_B | TMR2_FLAG_OVF_CH_B) +/** + * @} + */ + +/** + * @defgroup TMR2_Counter_State TMR2 Counter State + * @{ + */ +#define TMR2_CNT_STAT_START (0U) /*!< Counter start counting. */ +#define TMR2_CNT_STAT_STOP (1U) /*!< Counter stop counting. */ +#define TMR2_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matchs the compare value. */ +/** + * @} + */ + +/** + * @defgroup TMR2_PWM_Polarity TMR2 PWM Polarity + * @{ + */ +#define TMR2_PWM_LOW (0x0U) /*!< PWM output low. */ +#define TMR2_PWM_HIGH (0x1U) /*!< PWM output high. */ +#define TMR2_PWM_HOLD (0x2U) /*!< PWM output keeps the current polarity. */ +#define TMR2_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMR2_Start_Condition TMR2 Start Condition + * @{ + */ +#define TMR2_START_COND_INVD (0x0U) /*!< The start condition of TMR2 is INVALID. */ +#define TMR2_START_COND_TRIG_RISING (TMR2_HCONR_HSTAA0) /*!< The start condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */ +#define TMR2_START_COND_TRIG_FALLING (TMR2_HCONR_HSTAA1) /*!< The start condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */ +#define TMR2_START_COND_EVT (TMR2_HCONR_HSTAA2) /*!< The start condition of TMR2 is the specified event occurred. */ +#define TMR2_START_COND_ALL (TMR2_START_COND_TRIG_RISING | TMR2_START_COND_TRIG_FALLING | \ + TMR2_START_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMR2_Stop_Condition TMR2 Stop Condition + * @{ + */ +#define TMR2_STOP_COND_INVD (0x0U) /*!< The stop condition of TMR2 is INVALID. */ +#define TMR2_STOP_COND_TRIG_RISING (TMR2_HCONR_HSTPA0) /*!< The stop condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */ +#define TMR2_STOP_COND_TRIG_FALLING (TMR2_HCONR_HSTPA1) /*!< The stop condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */ +#define TMR2_STOP_COND_EVT (TMR2_HCONR_HSTPA2) /*!< The stop condition of TMR2 is the specified event occurred. */ +#define TMR2_STOP_COND_ALL (TMR2_STOP_COND_TRIG_RISING | TMR2_STOP_COND_TRIG_FALLING | \ + TMR2_STOP_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMR2_Clear_Condition TMR2 Clear Condition + * @{ + */ +#define TMR2_CLR_COND_INVD (0x0U) /*!< The clear condition of TMR2 is INVALID. */ +#define TMR2_CLR_COND_TRIG_RISING (TMR2_HCONR_HCLEA0) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */ +#define TMR2_CLR_COND_TRIG_FALLING (TMR2_HCONR_HCLEA1) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */ +#define TMR2_CLR_COND_EVT (TMR2_HCONR_HCLEA2) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the specified event occurred. */ +#define TMR2_CLR_COND_ALL (TMR2_CLR_COND_TRIG_RISING | TMR2_CLR_COND_TRIG_FALLING | \ + TMR2_CLR_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMR2_Capture_Condition TMR2 Capture Condition + * @{ + */ +#define TMR2_CAPT_COND_INVD (0x0U) /*!< The capture condition of TMR2 is INVALID. */ +#define TMR2_CAPT_COND_TRIG_RISING (TMR2_HCONR_HICPA0) /*!< The capture condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */ +#define TMR2_CAPT_COND_TRIG_FALLING (TMR2_HCONR_HICPA1) /*!< The capture condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */ +#define TMR2_CAPT_COND_EVT (TMR2_HCONR_HICPA2) /*!< The capture condition of TMR2 is the specified event occurred. */ +#define TMR2_CAPT_COND_ALL (TMR2_CAPT_COND_TRIG_RISING | TMR2_CAPT_COND_TRIG_FALLING | \ + TMR2_CAPT_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMR2_Filter_Clock_Divider TMR2 Filter Clock Divider + * @{ + */ +#define TMR2_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timer2 / 1 */ +#define TMR2_FILTER_CLK_DIV4 (TMR2_PCONR_NOFICKA_0) /*!< The filter clock is the clock of timer2 / 4 */ +#define TMR2_FILTER_CLK_DIV16 (TMR2_PCONR_NOFICKA_1) /*!< The filter clock is the clock of timer2 / 16 */ +#define TMR2_FILTER_CLK_DIV64 (TMR2_PCONR_NOFICKA) /*!< The filter clock is the clock of timer2 / 64 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR2_Global_Functions + * @{ + */ +int32_t TMR2_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_init_t *pstcTmr2Init); +int32_t TMR2_StructInit(stc_tmr2_init_t *pstcTmr2Init); +void TMR2_DeInit(CM_TMR2_TypeDef *TMR2x); + +void TMR2_SetFunc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Func); +void TMR2_SetClockSrc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Src); +void TMR2_SetClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div); + +int32_t TMR2_PWM_StructInit(stc_tmr2_pwm_init_t *pstPwmInit); +int32_t TMR2_PWM_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_pwm_init_t *pstPwmInit); +void TMR2_PWM_OutputCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState); + +void TMR2_HWCaptureCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +void TMR2_HWStartCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR2_HWStopCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR2_HWClearCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +void TMR2_SetFilterClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div); +void TMR2_FilterCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState); + +void TMR2_IntCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32IntType, en_functional_state_t enNewState); + +void TMR2_Start(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch); +void TMR2_Stop(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch); + +en_flag_status_t TMR2_GetStatus(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag); +void TMR2_ClearStatus(CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag); + +void TMR2_SetCompareValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMR2_GetCompareValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch); + +void TMR2_SetCountValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMR2_GetCountValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch); + +void TMR2_PWM_SetPolarity(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint8_t u8CountState, uint32_t u32Polarity); + +/** + * @} + */ + +#endif /* LL_TMR2_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR2_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h new file mode 100644 index 0000000000..1af85c1841 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h @@ -0,0 +1,801 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.h + * @brief This file contains all the functions prototypes of the TMR4 + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR4_H__ +#define __HC32_LL_TMR4_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR4 + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Types TMR4 Global Types + * @{ + */ + +/** + * @brief TMR4 Counter function initialization configuration + * @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< TMR4 counter clock source. + This parameter can be a value of @ref TMR4_Count_Clock_Source */ + uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division. + This parameter can be a value of @ref TMR4_Count_Clock_Division. */ + uint16_t u16CountMode; /*!< TMR4 counter mode. + This parameter can be a value of @ref TMR4_Count_Mode */ + uint16_t u16PeriodValue; /*!< TMR4 counter period value. + This parameter can be a value of half-word */ +} stc_tmr4_init_t; + +/** + * @brief The configuration of Output-Compare high channel(OUH/OVH/OWH) + */ +typedef union { + uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */ + + struct { /*!< OCMRxH(x=U/V/W) register struct field bit */ + uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrh_t; + +/** + * @brief The configuration of Output-Compare low channel(OUL/OVL/OWL) + */ +typedef union { + uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */ + + struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/ + uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is coutning down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrl_t; + +/** + * @brief TMR4 Output-Compare(OC) initialization configuration + */ +typedef struct { + uint16_t u16CompareValue; /*!< TMR4 OC compare match value. + This parameter can be a value of half-word. */ + uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled. + This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */ + uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask. + This parameter can be a value of @ref TMR4_OC_Buffer_Object. */ +} stc_tmr4_oc_init_t; + +/** + * @brief TMR4 PWM initialization configuration + * @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock. + */ +typedef struct { + uint16_t u16Mode; /*!< Select PWM mode + This parameter can be a value of @ref TMR4_PWM_Mode */ + uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer. + This parameter can be a value of @ref TMR4_PWM_Clock_Division. */ + uint16_t u16Polarity; /*!< TMR4 PWM polarity + This parameter can be a value of @ref TMR4_PWM_Polarity */ +} stc_tmr4_pwm_init_t; + +/** + * @brief TMR4 Special-Event(EVT) initialization configuration + */ +typedef struct { + uint16_t u16Mode; /*!< TMR4 event mode + This parameter can be a value of @ref TMR4_Event_Mode */ + uint16_t u16CompareValue; /*!< TMR4 event compare match value. + This parameter can be a value of half-word */ + uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition. + This parameter can be a value of @ref TMR4_Event_Output_Event */ + uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event. + This parameter can be a value of @ref TMR4_Event_Match_Condition */ +} stc_tmr4_evt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Macros TMR4 Global Macros + * @{ + */ + +/** + * @defgroup TMR4_Counter_Macros TMR4 Counter Macros + * @{ + */ + +/** + * @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source + * @{ + */ +#define TMR4_CLK_SRC_INTERNCLK (0U) +#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division + * @{ + */ +#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */ +#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */ +#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */ +#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */ +#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */ +#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */ +#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */ +#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */ +#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */ +#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */ +#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Mode TMR4 Count Mode + * @{ + */ +#define TMR4_MD_SAWTOOTH (0U) +#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag TMR4 Flag + * @{ + */ +#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */ +#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */ +#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */ +#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */ +#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */ +#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */ +#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */ +#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */ +#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */ +#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */ +#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */ + +#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \ + TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \ + TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \ + TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Interrupt TMR4 Interrupt + * @{ + */ +#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */ +#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */ +#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */ +#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */ +#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */ +#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */ +#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */ +#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */ +#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */ +#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */ +#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */ + +#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \ + TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \ + TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \ + TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time + * @{ + */ +#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */ +#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) */ +#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) */ +#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) */ +#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) */ +#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) */ +#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) */ +#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) */ +#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) */ +#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) */ +#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) */ +#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) */ +#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) */ +#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) */ +#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) */ +#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros + * @{ + */ + +/** + * @defgroup TMR4_OC_Channel TMR4 OC Channel + * @{ + */ +#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */ +#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */ +#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */ +#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */ +#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */ +#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity + * @{ + */ +#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */ +#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object + * @{ + */ +#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function index */ +#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function index */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition + * @{ + */ +#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */ +#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */ +#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */ +#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State + * @{ + */ +#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */ +#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity + * @{ + */ +#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */ +#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */ +#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */ +#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Macros TMR4 PWM Macros + * @{ + */ + +/** + * @defgroup TMR4_PWM_Channel TMR4 PWM Channel + * @{ + */ +#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */ +#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */ +#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin TMR4 PWM Pin + * @{ + */ +#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */ +#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */ +#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */ +#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */ +#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */ +#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division + * @{ + */ +#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */ +#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */ +#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */ +#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */ +#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */ +#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Mode TMR4 PWM Mode + * @{ + */ +#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */ +#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */ +#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity + * @{ + */ +#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */ +#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */ +#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */ +#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index + * @{ + */ +#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */ +#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status + * @{ + */ +#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal */ +#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) to Hi-z */ +#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output low level */ +#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output high level */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin_Output_Mode TMR4 PWM Pin Mode + * @{ + */ +#define TMR4_PWM_PIN_OUTPUT_OS (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output polarity by specified register TMR4_PSCR.OSxy */ +#define TMR4_PWM_PIN_OUTPUT_NORMAL (TMR4_PSCR_OEUH) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal PWM */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_OE_Bit_Effect_Time TMR4 PWM Register TMR4_PSCR.OE Bit Effect Time + * @{ + */ +#define TMR4_PWM_OE_EFFECT_IMMED (TMR4_PSCR_ODT_0) /*!< TMR4 PWM reister TMR4_PSCR.OE bit immediate effect. */ +#define TMR4_PWM_OE_EFFECT_COUNT_PEAK (TMR4_PSCR_ODT) /*!< TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count peak. */ +#define TMR4_PWM_OE_EFFECT_COUNT_VALLEY (TMR4_PSCR_ODT_1) /*!< TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count valley. */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Macros TMR4 Event Macros + * @{ + */ + +/** + * @defgroup TMR4_Event_Channel TMR4 Event Channel + * @{ + */ +#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */ +#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */ +#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */ +#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */ +#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */ +#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition + * @{ + */ +#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */ +#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */ +#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */ +#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count vallay */ +#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \ + TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask TMR4 Event Mask + * @{ + */ +#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */ +#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */ +#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition + * @{ + */ +#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */ +#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */ +#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */ +#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mode TMR4 Event Mode + * @{ + */ +#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */ +#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object + * @{ + */ +#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */ +#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times + * @{ + */ +#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */ +#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */ +#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */ +#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */ +#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */ +#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */ +#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */ +#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */ +#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */ +#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */ +#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */ +#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */ +#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */ +#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */ +#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */ +#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Event TMR4 Event Output Event + * @{ + */ +#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */ +#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */ +#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */ +#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */ +#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */ +#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal + * @{ + */ +#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR4_Global_Functions + * @{ + */ + +/** + * @addtogroup TMR4_Counter_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 counter functions */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init); +void TMR4_DeInit(CM_TMR4_TypeDef *TMR4x); +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src); +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div); +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode); +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x); +void TMR4_Start(CM_TMR4_TypeDef *TMR4x); +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x); +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState); +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType); +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime); +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType); + +void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Output_Compare_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 Output-Compare functions */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit); +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit); +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState); +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond); +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh); +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl); +/** + * @} + */ + +/** + * @addtogroup TMR4_PWM_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 PWM functions */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div); +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value); +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex); + +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus); + +void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time); +void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Event_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 event functions */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit); +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit); +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object); +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime); +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event); +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond); +void TMR4_EVT_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_EVT_EventIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState); +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal); +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR4_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h new file mode 100644 index 0000000000..fa9ac14999 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h @@ -0,0 +1,917 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.h + * @brief Head file for TMR6 module. + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR6_H__ +#define __HC32_LL_TMR6_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR6 + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Types TMR6 Global Types + * @{ + */ + +/** + * @brief Timer6 count function structure definition + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */ + union { + struct { + uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */ + uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */ + uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */ + } sw_count; + struct { + uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */ + uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */ + uint32_t u32Reserved; /*!< Reserved */ + } hw_count; + }; + uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */ + uint32_t u32CountReload; /*!< Count reload after overflow @ref TMR6_Count_Reload_Define */ +} stc_timer6_init_t; + +/** + * @brief Timer6 pwm output function structure definition + */ +typedef struct { + uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */ + uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountUpMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-up mode \ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountDownMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-down mode \ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountUpMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-up mode \ + @ref TMR6_Pin_Polarity_Define*/ + uint32_t u32CountDownMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-down mode\ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32UdfPolarity; /*!< Pin polarity when underflow @ref TMR6_Pin_Polarity_Define */ + uint32_t u32OvfPolarity; /*!< Pin polarity when overflow @ref TMR6_Pin_Polarity_Define */ +} stc_tmr6_pwm_init_t; + +/** + * @brief Timer6 buffer function configuration structure definition + */ +typedef struct { + uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \ + @ref TMR6_Buf_Num_Define */ + uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \ + @ref TMR6_Buf_Trans_Cond_Define */ +} stc_tmr6_buf_config_t; + +/** + * @brief Timer6 Valid period function configuration structure definition + */ +typedef struct { + uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \ + @ref TMR6_Valid_Period_Count_Cond_Define */ + uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */ +} stc_tmr6_valid_period_config_t; + +/** + * @brief Timer6 EMB configuration structure definition + */ +typedef struct { + uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_Ch_Define */ + uint32_t u32ReleaseMode; /*!< Pin release mode when EMB event invalid @ref TMR6_Emb_Release_Mode_Define */ + uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */ +} stc_tmr6_emb_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \ + @ref TMR6_Deadtime_Reg_Equal_Func_Define */ + uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \ + @ref TMR6_Deadtime_CountUp_Buf_Func_Define*/ + uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \ + @ref TMR6_Deadtime_CountDown_Buf_Func_Define*/ + uint32_t u32UpdateCond; /*!< Buffer transfer condition for triangular wave mode \ + @ref TMR6_Deadtime_Buf_Trans_Cond_Define */ +} stc_tmr6_deadtime_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */ + uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \ + the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */ + uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \ + during the time of Z phase input mask \ + @ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/ +} stc_tmr6_zmask_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Macros TMR6 Global Macros + * @{ + */ + +/** + * @defgroup TMR6_Count_Src_Define TMR6 Count Source Define + * @{ + */ +#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */ +#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */ +/** + * @} + */ + +/** + * @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define + * @{ + */ +#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */ +#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */ +#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */ +#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */ +#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */ +#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */ +#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \ + Triangular wave peak point */ +#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \ + Triangular wave valley point */ +#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */ +#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */ +#define TMR6_FLAG_CLR_ALL (0x00001EFFUL) /*!< Clear all flag */ +#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \ + TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \ + TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \ + TMR6_FLAG_CNT_DIR) +/** + * @} + */ + +/** + * @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define + * @{ + */ +#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */ +#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */ +#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */ +#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */ +#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */ +#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */ +#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */ +#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */ +#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */ +#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\ + TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \ + TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B) +/** + * @} + */ + +/** + * @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define + * @{ + */ +#define TMR6_PERIOD_REG_A (0x00UL) +#define TMR6_PERIOD_REG_B (0x01UL) +#define TMR6_PERIOD_REG_C (0x02UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define + * @{ + */ +#define TMR6_CMP_REG_A (0x00UL) +#define TMR6_CMP_REG_B (0x01UL) +#define TMR6_CMP_REG_C (0x02UL) +#define TMR6_CMP_REG_D (0x03UL) +#define TMR6_CMP_REG_E (0x04UL) +#define TMR6_CMP_REG_F (0x05UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define + * @{ + */ +#define TMR6_CH_A (0x00UL) +#define TMR6_CH_B (0x01UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define + * @{ + */ +#define TMR6_BUF_SINGLE (0x00000000UL) +#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define + * @{ + */ +#define TMR6_BUF_TRANS_INVD (0x00000000UL) +#define TMR6_BUF_TRANS_OVF (0x00000004UL) +#define TMR6_BUF_TRANS_UDF (0x00000008UL) +#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define + * @{ + */ +#define TMR6_VALID_PERIOD_INVD (0x00000000UL) /*!< Valid period function off */ +#define TMR6_VALID_PERIOD_CNT_COND_UDF (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave underflow */ +#define TMR6_VALID_PERIOD_CNT_COND_OVF (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave overflow */ +#define TMR6_VALID_PERIOD_CNT_COND_OVF_UDF (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave overflow and underflow */ +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define + * @{ + */ +#define TMR6_VALID_PERIOD_CNT_INVD (0x00000000UL) +#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define + * @{ + */ +#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */ +#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */ +#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */ +#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define + * @{ + */ +#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6__PWMA */ +#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6__PWMB */ +#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */ +#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */ +#define TMR6_INPUT_TRIGC (0x04U) /*!< Input pin TIM6_TRIGC */ +#define TMR6_INPUT_TRIGD (0x05U) /*!< Input pin TIM6_TRIGD */ +/** + * @} + */ + +/** + * @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define + * @{ + */ +#define TMR6_FILTER_CLK_DIV1 (0x00U) +#define TMR6_FILTER_CLK_DIV4 (0x01U) +#define TMR6_FILTER_CLK_DIV16 (0x02U) +#define TMR6_FILTER_CLK_DIV64 (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection + * @{ + */ +#define TMR6_PIN_CMP_OUTPUT (0x00U) +#define TMR6_PIN_CAPT_INPUT (TMR6_PCNAR_CAPMDA) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_State_Define TMR6 Count State + * @{ + */ +#define TMR6_STAT_START (0U) /*!< Count start */ +#define TMR6_STAT_STOP (1U) /*!< Count stop */ +#define TMR6_STAT_OVF (2U) /*!< Count overflow */ +#define TMR6_STAT_UDF (3U) /*!< Count underflow */ +#define TMR6_STAT_UP_CNT_MATCH_A (4U) /*!< Count up match compare register A */ +#define TMR6_STAT_DOWN_CNT_MATCH_A (5U) /*!< Count down match compare register A */ +#define TMR6_STAT_UP_CNT_MATCH_B (6U) /*!< Count up match compare register B */ +#define TMR6_STAT_DOWN_CNT_MATCH_B (7U) /*!< Count down match compare register B */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity + * @{ + */ + +#define TMR6_PWM_LOW (0x00U) +#define TMR6_PWM_HIGH (0x01U) +#define TMR6_PWM_HOLD (0x02U) +#define TMR6_PWM_INVT (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Force_Output_Polarity_Define TMR6 Force Output Polarity Next Period + * @{ + */ +#define TMR6_PWM_FORCE_INVD (0x00U) +#define TMR6_PWM_FORCE_LOW (0x02U) +#define TMR6_PWM_FORCE_HIGH (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Ch_Define TMR6 EMB Event Channel + * @{ + */ +#define TMR6_EMB_EVT_CH0 (0x00U) +#define TMR6_EMB_EVT_CH1 (TMR6_PCNAR_EMBSA_0) +#define TMR6_EMB_EVT_CH2 (TMR6_PCNAR_EMBSA_1) +#define TMR6_EMB_EVT_CH3 (TMR6_PCNAR_EMBSA) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Release_Mode_Define TMR6 EMB Function Release Mode When EMB Event Invalid + * @{ + */ +#define TMR6_EMB_RELEASE_IMMED (0x00U) +#define TMR6_EMB_RELEASE_OVF (TMR6_PCNAR_EMBRA_0) +#define TMR6_EMB_RELEASE_UDF (TMR6_PCNAR_EMBRA_1) +#define TMR6_EMB_RELEASE_OVF_UDF (TMR6_PCNAR_EMBRA) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid + * @{ + */ +#define TMR6_EMB_PIN_NORMAL (0x00U) +#define TMR6_EMB_PIN_HIZ (TMR6_PCNAR_EMBCA_0) +#define TMR6_EMB_PIN_LOW (TMR6_PCNAR_EMBCA_1) +#define TMR6_EMB_PIN_HIGH (TMR6_PCNAR_EMBCA) + +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Buf_Trans_Cond_Define TMR6 Dead Time Buffer Transfer Condition Define For Triangular Count Mode + * @{ + */ +#define TMR6_DEADTIME_BUF_COND_INVD (0x00U) +#define TMR6_DEADTIME_BUF_COND_OVF (TMR6_DCONR_DTBTRU) +#define TMR6_DEADTIME_BUF_COND_UDF (TMR6_DCONR_DTBTRD) +#define TMR6_DEADTIME_BUF_COND_OVF_UDF (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR + * @{ + */ +#define TMR6_DEADTIME_EQUAL_OFF (0x00U) +#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA) +/** + * @} + */ + +/** + * @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define + * @{ + */ +#define TMR6_SW_SYNC_U1 (TMR6CR_SSTAR_SSTA1) +#define TMR6_SW_SYNC_U2 (TMR6CR_SSTAR_SSTA2) +#define TMR6_SW_SYNC_U3 (TMR6CR_SSTAR_SSTA3) +#define TMR6_SW_SYNC_U4 (TMR6CR_SSTAR_SSTA4) +#define TMR6_SW_SYNC_U5 (TMR6CR_SSTAR_SSTA5) +#define TMR6_SW_SYNC_U6 (TMR6CR_SSTAR_SSTA6) +#define TMR6_SW_SYNC_U7 (TMR6CR_SSTAR_SSTA7) +#define TMR6_SW_SYNC_U8 (TMR6CR_SSTAR_SSTA8) +#define TMR6_SW_SYNC_ALL (0xFFU) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define + * @{ + */ +#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA0) +#define TMR6_START_COND_PWMA_FAILLING (TMR6_HSTAR_HSTA1) +#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA2) +#define TMR6_START_COND_PWMB_FAILLING (TMR6_HSTAR_HSTA3) +#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA8) +#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA9) +#define TMR6_START_COND_EVT2 (TMR6_HSTAR_HSTA10) +#define TMR6_START_COND_EVT3 (TMR6_HSTAR_HSTA11) +#define TMR6_START_COND_TRIGEA_RISING (TMR6_HSTAR_HSTA16) +#define TMR6_START_COND_TRIGEA_FAILLING (TMR6_HSTAR_HSTA17) +#define TMR6_START_COND_TRIGEB_RISING (TMR6_HSTAR_HSTA18) +#define TMR6_START_COND_TRIGEB_FAILLING (TMR6_HSTAR_HSTA19) +#define TMR6_START_COND_TRIGEC_RISING (TMR6_HSTAR_HSTA20) +#define TMR6_START_COND_TRIGEC_FAILLING (TMR6_HSTAR_HSTA21) +#define TMR6_START_COND_TRIGED_RISING (TMR6_HSTAR_HSTA22) +#define TMR6_START_COND_TRIGED_FAILLING (TMR6_HSTAR_HSTA23) +#define TMR6_START_COND_ALL (0x00FF0F0FUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define + * @{ + */ +#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP0) +#define TMR6_STOP_COND_PWMA_FAILLING (TMR6_HSTPR_HSTP1) +#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP2) +#define TMR6_STOP_COND_PWMB_FAILLING (TMR6_HSTPR_HSTP3) +#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP8) +#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP9) +#define TMR6_STOP_COND_EVT2 (TMR6_HSTPR_HSTP10) +#define TMR6_STOP_COND_EVT3 (TMR6_HSTPR_HSTP11) +#define TMR6_STOP_COND_TRIGEA_RISING (TMR6_HSTPR_HSTP16) +#define TMR6_STOP_COND_TRIGEA_FAILLING (TMR6_HSTPR_HSTP17) +#define TMR6_STOP_COND_TRIGEB_RISING (TMR6_HSTPR_HSTP18) +#define TMR6_STOP_COND_TRIGEB_FAILLING (TMR6_HSTPR_HSTP19) +#define TMR6_STOP_COND_TRIGEC_RISING (TMR6_HSTPR_HSTP20) +#define TMR6_STOP_COND_TRIGEC_FAILLING (TMR6_HSTPR_HSTP21) +#define TMR6_STOP_COND_TRIGED_RISING (TMR6_HSTPR_HSTP22) +#define TMR6_STOP_COND_TRIGED_FAILLING (TMR6_HSTPR_HSTP23) +#define TMR6_STOP_COND_ALL (0x00FF0F0FUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define + * @{ + */ +#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE0) +#define TMR6_CLR_COND_PWMA_FAILLING (TMR6_HCLRR_HCLE1) +#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE2) +#define TMR6_CLR_COND_PWMB_FAILLING (TMR6_HCLRR_HCLE3) +#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE8) +#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE9) +#define TMR6_CLR_COND_EVT2 (TMR6_HCLRR_HCLE10) +#define TMR6_CLR_COND_EVT3 (TMR6_HCLRR_HCLE11) +#define TMR6_CLR_COND_TRIGEA_RISING (TMR6_HCLRR_HCLE16) +#define TMR6_CLR_COND_TRIGEA_FAILLING (TMR6_HCLRR_HCLE17) +#define TMR6_CLR_COND_TRIGEB_RISING (TMR6_HCLRR_HCLE18) +#define TMR6_CLR_COND_TRIGEB_FAILLING (TMR6_HCLRR_HCLE19) +#define TMR6_CLR_COND_TRIGEC_RISING (TMR6_HCLRR_HCLE20) +#define TMR6_CLR_COND_TRIGEC_FAILLING (TMR6_HCLRR_HCLE21) +#define TMR6_CLR_COND_TRIGED_RISING (TMR6_HCLRR_HCLE22) +#define TMR6_CLR_COND_TRIGED_FAILLING (TMR6_HCLRR_HCLE23) +#define TMR6_CLR_COND_ALL (0x00FF0F0FUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_update_condition_Define TMR6 Hardware Update Condition Define + * @{ + */ +#define TMR6_UPD_COND_PWMA_RISING (TMR6_HUPDR_HUPD0) +#define TMR6_UPD_COND_PWMA_FAILLING (TMR6_HUPDR_HUPD1) +#define TMR6_UPD_COND_PWMB_RISING (TMR6_HUPDR_HUPD2) +#define TMR6_UPD_COND_PWMB_FAILLING (TMR6_HUPDR_HUPD3) +#define TMR6_UPD_COND_EVT0 (TMR6_HUPDR_HUPD8) +#define TMR6_UPD_COND_EVT1 (TMR6_HUPDR_HUPD9) +#define TMR6_UPD_COND_EVT2 (TMR6_HUPDR_HUPD10) +#define TMR6_UPD_COND_EVT3 (TMR6_HUPDR_HUPD11) +#define TMR6_UPD_COND_TRIGEA_RISING (TMR6_HUPDR_HUPD16) +#define TMR6_UPD_COND_TRIGEA_FAILLING (TMR6_HUPDR_HUPD17) +#define TMR6_UPD_COND_TRIGEB_RISING (TMR6_HUPDR_HUPD18) +#define TMR6_UPD_COND_TRIGEB_FAILLING (TMR6_HUPDR_HUPD19) +#define TMR6_UPD_COND_TRIGEC_RISING (TMR6_HUPDR_HUPD20) +#define TMR6_UPD_COND_TRIGEC_FAILLING (TMR6_HUPDR_HUPD21) +#define TMR6_UPD_COND_TRIGED_RISING (TMR6_HUPDR_HUPD22) +#define TMR6_UPD_COND_TRIGED_FAILLING (TMR6_HUPDR_HUPD23) +#define TMR6_UPD_COND_ALL (0x00FF0F0FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define + * @{ + */ +#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA0) +#define TMR6_CAPT_COND_PWMA_FAILLING (TMR6_HCPAR_HCPA1) +#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA2) +#define TMR6_CAPT_COND_PWMB_FAILLING (TMR6_HCPAR_HCPA3) +#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA8) +#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA9) +#define TMR6_CAPT_COND_EVT2 (TMR6_HCPAR_HCPA10) +#define TMR6_CAPT_COND_EVT3 (TMR6_HCPAR_HCPA11) +#define TMR6_CAPT_COND_TRIGEA_RISING (TMR6_HCPAR_HCPA16) +#define TMR6_CAPT_COND_TRIGEA_FAILLING (TMR6_HCPAR_HCPA17) +#define TMR6_CAPT_COND_TRIGEB_RISING (TMR6_HCPAR_HCPA18) +#define TMR6_CAPT_COND_TRIGEB_FAILLING (TMR6_HCPAR_HCPA19) +#define TMR6_CAPT_COND_TRIGEC_RISING (TMR6_HCPAR_HCPA20) +#define TMR6_CAPT_COND_TRIGEC_FAILLING (TMR6_HCPAR_HCPA21) +#define TMR6_CAPT_COND_TRIGED_RISING (TMR6_HCPAR_HCPA22) +#define TMR6_CAPT_COND_TRIGED_FAILLING (TMR6_HCPAR_HCPA23) +#define TMR6_CAPT_COND_ALL (0x00FF0F0FUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define + * @{ + */ +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCUPR_HCUP1) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCUPR_HCUP3) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCUPR_HCUP5) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCUPR_HCUP7) +#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP8) +#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP9) +#define TMR6_CNT_UP_COND_EVT2 (TMR6_HCUPR_HCUP10) +#define TMR6_CNT_UP_COND_EVT3 (TMR6_HCUPR_HCUP11) +#define TMR6_CNT_UP_COND_TRIGEA_RISING (TMR6_HCUPR_HCUP16) +#define TMR6_CNT_UP_COND_TRIGEA_FAILLING (TMR6_HCUPR_HCUP17) +#define TMR6_CNT_UP_COND_TRIGEB_RISING (TMR6_HCUPR_HCUP18) +#define TMR6_CNT_UP_COND_TRIGEB_FAILLING (TMR6_HCUPR_HCUP19) +#define TMR6_CNT_UP_COND_TRIGEC_RISING (TMR6_HCUPR_HCUP20) +#define TMR6_CNT_UP_COND_TRIGEC_FAILLING (TMR6_HCUPR_HCUP21) +#define TMR6_CNT_UP_COND_TRIGED_RISING (TMR6_HCUPR_HCUP22) +#define TMR6_CNT_UP_COND_TRIGED_FAILLING (TMR6_HCUPR_HCUP23) +#define TMR6_CNT_UP_COND_ALL (0x00FF0FFFUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define + * @{ + */ +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCDOR_HCDO1) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCDOR_HCDO3) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCDOR_HCDO5) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCDOR_HCDO7) +#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO8) +#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO9) +#define TMR6_CNT_DOWN_COND_EVT2 (TMR6_HCDOR_HCDO10) +#define TMR6_CNT_DOWN_COND_EVT3 (TMR6_HCDOR_HCDO11) +#define TMR6_CNT_DOWN_COND_TRIGEA_RISING (TMR6_HCDOR_HCDO16) +#define TMR6_CNT_DOWN_COND_TRIGEA_FAILLING (TMR6_HCDOR_HCDO17) +#define TMR6_CNT_DOWN_COND_TRIGEB_RISING (TMR6_HCDOR_HCDO18) +#define TMR6_CNT_DOWN_COND_TRIGEB_FAILLING (TMR6_HCDOR_HCDO19) +#define TMR6_CNT_DOWN_COND_TRIGEC_RISING (TMR6_HCDOR_HCDO20) +#define TMR6_CNT_DOWN_COND_TRIGEC_FAILLING (TMR6_HCDOR_HCDO21) +#define TMR6_CNT_DOWN_COND_TRIGED_RISING (TMR6_HCDOR_HCDO22) +#define TMR6_CNT_DOWN_COND_TRIGED_FAILLING (TMR6_HCDOR_HCDO23) +#define TMR6_CNT_DOWN_COND_ALL (0x00FF0FFFUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define + * @{ + */ +#define TMR6_CNT_UP (TMR6_GCONR_DIR) +#define TMR6_CNT_DOWN (0x00U) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define + * @{ + */ +#define TMR6_MD_SAWTOOTH (0x00U) +#define TMR6_MD_TRIANGLE (TMR6_GCONR_MODE) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define + * @{ + */ +#define TMR6_CLK_DIV1 (0x00UL) +#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Reload_Define TMR6 Count Stop After Overflow Function Define + * @{ + */ +#define TMR6_CNT_RELOAD_ON (0x00U) +#define TMR6_CNT_RELOAD_OFF (TMR6_GCONR_OVSTP) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define + * @{ + */ +#define TMR6_ZMASK_FUNC_INVD (0x00U) +#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0) +#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1) +#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action + * @{ + */ +#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00U) +#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action + * @{ + */ +#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00U) +#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR6_Global_Functions + * @{ + */ +/** + * @brief Get Software Sync start status + * @param None + * @retval uint32_t Data indicate the read status. + */ +__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void) +{ + return READ_REG32(CM_TMR6CR->SSTAR); +} + +/* Base count */ +int32_t TMR6_StructInit(stc_timer6_init_t *pstcTmr6Init); +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_timer6_init_t *pstcTmr6Init); + +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode); +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir); +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x); +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div); +void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Hardware count */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); + +/* PWM output */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit); +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit); +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity); +void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity); + +/* Input capture */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +/* Pin config */ +int32_t TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div); +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState); +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func); + +/* Universal */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x); +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x); +void TMR6_Start(CM_TMR6_TypeDef *TMR6x); +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x); + +/* Register write */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); + +/* Register read */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); + +/* Buffer function */ +int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig); + +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Extend function */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig); +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig); + +/* Software synchronous control */ +void TMR6_SWSyncStart(uint32_t u32Unit); +void TMR6_SWSyncStop(uint32_t u32Unit); +void TMR6_SWSyncClear(uint32_t u32Unit); +void TMR6_SWSyncUpdate(uint32_t u32Unit); + +/* Hardware control */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h new file mode 100644 index 0000000000..c3bd06d3ad --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h @@ -0,0 +1,556 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.h + * @brief This file contains all the functions prototypes of the TMRA(TimerA) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMRA_H__ +#define __HC32_LL_TMRA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMRA + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Types TMRA Global Types + * @{ + */ +/** + * @brief TMRA initialization structure. + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source of TMRA. + This parameter can be a value of @ref TMRA_Count_Src */ + union { + struct { + uint16_t u16ClockDiv; /*!< Specifies the divider of software clock source. + This parameter can be a value of @ref TMRA_Clock_Divider */ + uint16_t u16CountMode; /*!< Specifies count mode. + This parameter can be a value of @ref TMRA_Count_Mode */ + uint16_t u16CountDir; /*!< Specifies count direction. + This parameter can be a value of @ref TMRA_Count_Dir */ + } sw_count; + struct { + + uint16_t u16CountUpCond; /*!< Hardware count up condition. + This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */ + uint16_t u16CountDownCond; /*!< Hardware count down condition. + This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */ + uint16_t u16Reserved; /*!< Reserved, for future use. */ + } hw_count; + }; + uint32_t u32PeriodValue; /*!< Specifies the period reference value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ + uint16_t u16CountReload; /*!< Continue counting or stop when counter overflow/underflow. + This parameter can be a value of @ref TMRA_Count_Reload_En */ +} stc_tmra_init_t; + +/** + * @brief TMRA PWM configuration structure. + */ +typedef struct { + uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel. + This parameter can be a number between: + 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. */ + uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting. + This parameter can be a value of @ref TMRA_PWM_Polarity + NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when + sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified + as @ref TMRA_CLK_DIV1 */ + uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ +} stc_tmra_pwm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Macros TMRA Global Macros + * @{ + */ + +/** + * @defgroup TMRA_Count_Src TMRA Count Source + * @{ + */ +#define TMRA_CNT_SRC_SW (0U) +#define TMRA_CNT_SRC_HW (1U) +/** + * @} + */ + +/** + * @defgroup TMRA_Channel TMRA Channel + * @note TMRA_1 and TMRA_2 of HC32M423 contain only one channel TMRA_CH1. + * @{ + */ +#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */ +#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */ +#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */ +#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Dir TMRA Count Direction + * @{ + */ +#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */ +#define TMRA_DIR_UP (TMRA_BCSTR_DIR) /*!< TMRA count up. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Mode TMRA Count Mode + * @{ + */ +#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */ +#define TMRA_MD_TRIANGLE (TMRA_BCSTR_MODE) /*!< Count mode is triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Function_Mode TMRA TMRA Function Mode + * @{ + */ +#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */ +#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */ +/** + * @} + */ + +/* Counter reload */ +/** + * @defgroup TMRA_Count_Reload_En TMRA Count Reload + * @{ + */ +#define TMRA_CNT_RELOAD_DISABLE (TMRA_BCSTR_OVSTP) /*!< Stop when counter overflow/underflow. */ +#define TMRA_CNT_RELOAD_ENABLE (0U) /*!< When counter overflow/underflow, counter reload to continue counting. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Clock_Divider TMRA Clock Divider + * @{ + */ +#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */ +#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */ +#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */ +#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */ +#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */ +#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */ +#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */ +#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */ +#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */ +#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */ +#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin TMRA Pin With Filter + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain pin TMRA_PIN_PWM2. + * @{ + */ +#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA__TRIG. */ +#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA__CLKA. */ +#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA__CLKB. */ +#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA__PWM1. */ +#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA__PWM2. */ +#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA__PWM3. */ +#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA__PWM4. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts up. */ +/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */ +#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts down. */ +/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */ +#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain interrupt TMRA_INT_CMP_CH2. + * @{ + */ +#define TMRA_INT_OVF (1UL << 12U) /*!< The interrupt of counting overflow. */ +#define TMRA_INT_UDF (1UL << 13U) /*!< The interrupt of counting underflow. */ +#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */ +#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */ +#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */ +#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */ +#define TMRA_INT_ALL (0xF3000UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Type TMRA Event Type + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain event TMRA_EVT_CMP_CH2. + * @{ + */ +#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */ +#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */ +#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */ +#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */ +#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | \ + TMRA_EVT_CMP_CH3 | TMRA_EVT_CMP_CH4) +/** + * @} + */ + +/** + * @defgroup TMRA_Status_Flag TMRA Status Flag + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain flag TMRA_FLAG_CMP_CH2. + * @{ + */ +#define TMRA_FLAG_OVF (1UL << 14U) /*!< The flag of counting overflow. */ +#define TMRA_FLAG_UDF (1UL << 15U) /*!< The flag of counting underflow. */ +#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */ +#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */ +#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */ +#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */ +#define TMRA_FLAG_ALL (0xFC000UL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Capture_Cond TMRA Capture Condition + * @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4. + * @{ + */ +#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */ +#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */ +#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \ + TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \ + TMRA_CAPT_COND_TRIG_FALLING) + +/** + * @} + */ + +/** + * @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition + * @{ + */ +#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. + When counting overflow or underflow or counting register was cleared, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */ +#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \ + TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider + * @{ + */ +#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timerA / 1 */ +#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of timerA / 4 */ +#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of timerA / 16 */ +#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of timerA / 64 */ +/** + * @} + */ + +/** + * @defgroup TMRA_Counter_State TMRA Counter State + * @{ + */ +#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */ +#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */ +#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matchs the compare value. */ +#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matchs the period value. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Polarity TMRA PWM Polarity + * @{ + */ +#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */ +#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */ +#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity + * @{ + */ +#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */ +#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition + * @{ + */ +#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */ +#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \ + TMRA_START_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition + * @{ + */ +#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */ +#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \ + TMRA_STOP_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12. + * @{ + */ +#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */ +#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \ + TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \ + TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \ + TMRA_CLR_COND_PWM3_FALLING) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMRA_Global_Functions + * @{ + */ +/* Base count(use software clock PCLK/HCLK) */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit); +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit); +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint16_t u16Mode); +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint16_t u16Dir); +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint16_t u16Div); + +/* Hardware count */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +/* Set function mode */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func); + +/* Ouput compare */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit); +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit); +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity); +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity); + +/* Input capture */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Trigger: hardware trigger to start/stop/clear the counter */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Filter */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div); +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState); + +/* Global */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx); +/* Counting direction, period value, counter value, compare value */ +uint16_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx); + +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch); + +/* Sync start. */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + +/* Reload and continue counting when overflow/underflow? */ +void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond); +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); + +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); + +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState); +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState); + +void TMRA_Start(CM_TMRA_TypeDef *TMRAx); +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx); + +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMRA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h new file mode 100644 index 0000000000..9bff88f20e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.h + * @brief This file contains all the functions prototypes of the TRNG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TRNG_H__ +#define __HC32_LL_TRNG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TRNG + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup TRNG_Global_Macros TRNG Global Macros + * @{ + */ + +/** + * @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value + * @{ + */ +#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */ +#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */ +/** + * @} + */ + +/** + * @defgroup TRNG_Shift_Ctrl TRNG Shift Control + * @{ + */ +#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */ +#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */ +#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */ +#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TRNG_Global_Functions + * @{ + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn); + +/* For polling mode. */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint8_t u8RandomLen); + +/* For interrupt mode. */ +void TRNG_Start(void); +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen); + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h new file mode 100644 index 0000000000..c47cf631e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h @@ -0,0 +1,540 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.h + * @brief This file contains all the functions prototypes of the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USART_H__ +#define __HC32_LL_USART_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USART + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup USART_Global_Types USART Global Types + * @{ + */ + +/** + * @brief clock synchronization mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_clocksync_init_t; + +/** + * @brief UART multiple-processor initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_multiprocessor_init_t; + +/** + * @brief UART mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32Parity; /*!< Parity format. + This parameter can be a value of @ref USART_Parity_Control */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_uart_init_t; + +/** + * @brief LIN mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ + +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32BmcClockDiv; /*!< BMC clock division. + This parameter can be a value of @ref USART_LIN_BMC_Clock_Division. + @note The clock division is valid when clock source is the internal clock. */ + uint32_t u32DetectBreakLen; /*!< Detect break length. + This parameter can be a value of @ref USART_LIN_Detect_Break_Length */ + uint32_t u32SendBreakLen; /*!< Send break length. + This parameter can be a value of @ref USART_LIN_Send_Break_Length */ + uint32_t u32SendBreakMode; /*!< Send break mode. + This parameter can be a value of @ref USART_LIN_Send_Break_Mode */ +} stc_usart_lin_init_t; + +/** + * @brief Smartcard mode initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is calculated according with smartcard default ETU and clock. */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ +} stc_usart_smartcard_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Global_Macros USART Global Macros + * @{ + */ + +/** + * @defgroup USART_Flag USART Flag + * @{ + */ +#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */ +#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */ +#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */ +#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */ +#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */ +#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */ +#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */ +#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */ +#define USART_FLAG_LIN_ERR (USART_SR_BE) /*!< LIN bus error flag */ +#define USART_FLAG_LIN_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */ +#define USART_FLAG_LIN_BREAK (USART_SR_LBD) /*!< LIN break signal detection flag */ + +#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \ + USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \ + USART_FLAG_TX_CPLT | USART_FLAG_LIN_BREAK | USART_FLAG_LIN_WKUP | \ + USART_FLAG_LIN_ERR | USART_FLAG_MX_PROCESSOR) + +/** + * @} + */ + +/** + * @defgroup USART_Transmission_Type USART Transmission Type + * @{ + */ +#define USART_TRANS_DATA (0UL) +#define USART_TRANS_ID (USART_DR_MPID) +/** + * @} + */ + +/** + * @defgroup USART_Function USART Function + * @{ + */ +#define USART_TX (USART_CR1_TE) /*!< USART TX function */ +#define USART_RX (USART_CR1_RE) /*!< USART RX function */ +#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */ +#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */ +#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */ + +#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timerout function */ +#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */ + +#define USART_LIN (USART_CR2_LINEN << 16UL) /*!< USART LIN function */ +#define USART_LIN_WKUP (USART_CR2_WKUPE << 16UL) /*!< USART LIN wakeup signal detect function */ +#define USART_LIN_ERR (USART_CR2_BEE << 16UL) /*!< USART LIN bus error detect function */ +#define USART_LIN_BREAK (USART_CR2_LBDL << 16UL) /*!< USART LIN bus break field detect function */ +#define USART_LIN_INT_ERR (USART_CR2_BEIE << 16UL) /*!< USART LIN bus error detect interrupt function */ +#define USART_LIN_INT_BREAK (USART_CR2_LBDIE << 16UL) /*!< USART LIN bus break field detect interrupt function */ +#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE << 16UL) /*!< USART LIN bus wakeup signal detect interrupt function */ + +#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \ + USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY | USART_LIN | USART_LIN_WKUP | \ + USART_LIN_ERR | USART_LIN_BREAK | USART_LIN_INT_ERR | USART_LIN_INT_BREAK | \ + USART_LIN_INT_WKUP) + +/** + * @} + */ + +/** + * @defgroup USART_Parity_Control USART Parity Control + * @{ + */ +#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */ +#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */ +#define USART_PARITY_ODD (USART_CR1_PCE | \ + USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** + * @defgroup USART_Data_Width_Bit USART Data Width Bit + * @{ + */ +#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */ +#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Over_Sample_Bit USART Over Sample Bit + * @{ + */ +#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */ +#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */ +/** + * @} + */ + +/** + * @defgroup USART_First_Bit USART First Bit + * @{ + */ +#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */ +#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */ +/** + * @} + */ + +/** + * @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity + * @{ + */ +#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */ +#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Source USART Clock Source + * @{ + */ +#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */ +#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */ +/** + * @} + */ + +/** + * @defgroup USART_CK_Output_Selection USART_CK Output Selection + * @{ + */ +#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */ +#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Bit USART Stop Bit + * @{ + */ +#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */ +#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */ +/** + * @} + */ + +/** + * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control + * @{ + */ +#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */ +#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */ +#define USART_HW_FLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow controle */ +#define USART_HW_FLOWCTRL_RTS_CTS (USART_HW_FLOWCTRL_CTS | \ + USART_HW_FLOWCTRL_RTS) /*!< USART hardware flow control RTS and CTS mode */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division USART Clock Division + * @{ + */ +#define USART_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */ +#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */ +#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */ +/** + * @} + */ + +/** + * @defgroup USART_Max_Timeout USART Max Timeout + * @{ + */ +#define USART_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock + * @{ + */ +#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */ +#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */ +#define USART_SC_ETU_CLK128 (2UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */ +#define USART_SC_ETU_CLK256 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */ +#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Mode_Noise_Filter_Width_Level USART Stop Mode Noise Filter Width Level + * @{ + */ +#define USART_STOP_MD_FILTER_LVL1 (0UL) /*!< Filter width level 1 */ +#define USART_STOP_MD_FILTER_LVL2 (PERIC_USART1_NFC_USASRT1_NFS_0) /*!< Filter width level 2 */ +#define USART_STOP_MD_FILTER_LVL3 (PERIC_USART1_NFC_USASRT1_NFS_1) /*!< Filter width level 3 */ +#define USART_STOP_MD_FILTER_LVL4 (PERIC_USART1_NFC_USASRT1_NFS) /*!< Filter width level 4 */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_BMC_Clock_Division USART LIN Baudrate Measure Counter Clock Division + * @{ + */ +#define USART_LIN_BMC_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_LIN_BMC_CLK_DIV2 (USART_PR_LBMPSC_0) /*!< CLK/2 */ +#define USART_LIN_BMC_CLK_DIV4 (USART_PR_LBMPSC_1) /*!< CLK/4 */ +#define USART_LIN_BMC_CLK_DIV8 (USART_PR_LBMPSC) /*!< CLK/8 */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode + * @{ + */ +#define USART_LIN_SEND_BREAK_MD_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */ +#define USART_LIN_SEND_BREAK_MD_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length + * @{ + */ +#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */ +#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length + * @{ + */ +#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */ +#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */ +#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */ +#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup USART_Global_Functions + * @{ + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit); +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error); +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit); +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error); +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit); +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit); +int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error); + +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit); +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error); + +void USART_DeInit(CM_USART_TypeDef *USARTx); +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState); +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity); +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit); +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit); +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth); +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit); +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity); +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint32_t u32Type); +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx); +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc); +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx); +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl); +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx); +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data); +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID); + +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error); + +/* Smartcard function */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock); + +void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level); + +void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx); +en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx); +void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode); +uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx); +uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx); +uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx); +void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len); +void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len); + +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h new file mode 100644 index 0000000000..1cc920b0b0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h @@ -0,0 +1,671 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.h + * @brief A detailed description is available at hardware registers + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USB_H__ +#define __HC32_LL_USB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +#include "usb_app_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USB + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_MAX_TX_FIFOS (16U) +#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS) +#define USB_MAX_EP_NUM (16U) + +#define USB_MAX_EP0_SIZE (64U) +/* working mode of the USB core */ +#define DEVICE_MODE (0U) +#define HOST_MODE (1U) + +/* Macro definations for device mode*/ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS) + +/* EP type */ +#define EP_TYPE_CTRL (0U) +#define EP_TYPE_ISOC (1U) +#define EP_TYPE_BULK (2U) +#define EP_TYPE_INTR (3U) +#define EP_TYPE_MSK (3U) + +/* USB port speed */ +#define PRTSPD_FULL_SPEED (1U) +#define PRTSPD_LOW_SPEED (2U) + +/* PHY clock */ +#define HCFG_30_60_MHZ (0U) +#define HCFG_48_MHZ (1U) +#define HCFG_6_MHZ (2U) + +#define USB_EP_TX_DIS (0x0000U) +#define USB_EP_TX_STALL (0x0010U) +#define USB_EP_TX_NAK (0x0020U) +#define USB_EP_TX_VALID (0x0030U) + +#define USB_EP_RX_DIS (0x0000U) +#define USB_EP_RX_STALL (0x1000U) +#define USB_EP_RX_NAK (0x2000U) +#define USB_EP_RX_VALID (0x3000U) + +#define USB_OK (0U) +#define USB_ERROR (1U) + +#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS) + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) +#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU)) +#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U)) + +#ifdef USB_INTERNAL_DMA_ENABLED +#define __USB_ALIGN_END +#if defined (__GNUC__) /* GNU Compiler */ +#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4))) +#elif defined (__CC_ARM) /* ARM Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __USB_ALIGN_BEGIN +#elif defined (__TASKING__) /* TASKING Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#endif +#else +#define __USB_ALIGN_BEGIN +#define __USB_ALIGN_END +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +typedef struct { + __IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */ + uint32_t Reserved04; /* Reserved 004h */ + __IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /* Reset Register 010h */ + __IO uint32_t GINTSTS; /* Interrupt Register 014h */ + __IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ + __IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h */ + /* DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */ + __IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */ + uint32_t Reserved30[3]; /* Reserved 030h-038h */ + __IO uint32_t CID; /* User ID Register 03Ch */ + uint32_t Reserved40[5]; /* Reserved 040h-050h */ + __IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */ + uint32_t Reserved58[42]; /* Reserved 058h-0FCh */ + __IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */ + __IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */ +} USB_CORE_GREGS; + +typedef struct { + __IO uint32_t DCFG; /* Device Configuration Register 800h */ + __IO uint32_t DCTL; /* Device Control Register 804h */ + __IO uint32_t DSTS; /* Device Status Register (RO) 808h */ + uint32_t Reserved0C; /* Reserved 80Ch */ + __IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */ + __IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */ + __IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */ + __IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */ + uint32_t Reserved20[4]; /* Reserved 820h-82Ch */ + __IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */ + __IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */ + __IO uint32_t DEACHINT; /* Deivce Each EP Interrupt Register 838h */ + __IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */ + uint32_t Reserved40; /* Reserved 840h */ + __IO uint32_t DIEPEACHMSK1; /* Deveice IN EP1 Interrupt Mask Register 844h */ + uint32_t Reserved48[15]; /* Reserved 848-880h */ + __IO uint32_t DOEPEACHMSK1; /* Deveice OUT EP1 Interrupt Mask Register 884h */ +} USB_CORE_DREGS; + +typedef struct { + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_CORE_INEPREGS; + +typedef struct { + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_CORE_OUTEPREGS; + +typedef struct { + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_CORE_HREGS; + +typedef struct { + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_CORE_HC_REGS; + +typedef struct { /* 000h */ + USB_CORE_GREGS *GREGS; + USB_CORE_DREGS *DREGS; + USB_CORE_HREGS *HREGS; + USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS]; + __IO uint32_t *HPRT; + __IO uint32_t *DFIFO[USB_MAX_TX_FIFOS]; + __IO uint32_t *GCCTL; +} LL_USB_TypeDef; + +typedef struct { + uint8_t host_chnum; + uint8_t dev_epnum; + uint8_t dmaen; + uint8_t low_power; + uint8_t phy_type; + uint8_t core_type; +} USB_CORE_BASIC_CFGS; + +typedef struct { + uint8_t dev_addr; + uint8_t ep_idx; + uint8_t is_epin; + uint8_t ch_speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t pid_type; + uint8_t in_toggle; + uint8_t out_toggle; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_HOST_CH; + +typedef struct { + uint8_t epidx; + uint8_t ep_dir; + uint8_t trans_type; + uint8_t ep_stall; + uint8_t data_pid_start; + uint8_t datax_pid; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* Transfer level variables */ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctl_data_len; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_DEV_EP; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addtogroup USB_Global_Functions + * @{ + */ + +/** + * @brief get the current mode of the usb core from the corresponding register + * @param [in] USBx usb instance + * @retval current mode 1: host mode 0: device mode + */ +__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx) +{ + if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) { + return 1U; + } else { + return 0U; + } +} + +/** + * @brief Initializes the normal interrupts + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM); +} + +/** + * @brief clear all the pending device interrupt bits and mask the IN and OUT + * endpoint interrupts. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL); +} + +/** + * @brief generate a device connect signal to the USB host + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); +} + +/** + * @brief test of mode processing + * @param [in] USBx usb instance + * @param [in] reg Register write + * @retval None + */ +__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg) +{ + WRITE_REG32(USBx->DREGS->DCTL, reg); +} + +/** + * @brief Enables the controller's Global interrupts in the AHB Configuration + * registers. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx) +{ + SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Disable the controller's Global interrupt in the AHB Configuration + * register. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Get the Core Interrupt bits from the interrupt register not including + * the bits that are masked. + * @param [in] USBx usb instance + * @retval status[32bits] + */ +__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->GREGS->GINTSTS); + v &= READ_REG32(USBx->GREGS->GINTMSK); + return v; +} + +/** + * @brief Get the out endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which OUT EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return ((v & 0xFFFF0000UL) >> 16U); +} + +/** + * @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the + * interrupt bits that are masked. + * @param [in] USBx usb instance + * @param [in] epnum end point index + * @retval all the interrupt bits on DOEPINTn while n = epnum + */ +__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum) +{ + uint32_t v; + v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT); + v &= READ_REG32(USBx->DREGS->DOEPMSK); + return v; +} + +/** + * @brief Get the IN endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which IN EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return (v & 0xFFFFUL); +} + +/** + * @brief Set the device a new address. + * @param [in] USBx usb instance + * @param [in] address device address which will be set to the corresponding register. + * @retval None + */ +__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS); +} + +/** + * @brief Select the USB PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (1U == PhyType) { + CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + //SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4); //todo 手册上没有该bit + } else { + SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + } +} + +/** + * @brief Select the USB device PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (1U == PhyType) { + CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } else { + SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } + +} + +/** + * @brief USB DMA function command. + * @param [in] USBx usb instance + * @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable + * @retval None + */ +__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS); +} + +/** + * @brief USB burst length config. + * @param [in] USBx usb instance + * @param [in] len Burst length + * @retval None + */ +__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS); +} + +/** + * @brief USB frame interval config + * @param [in] USBx usb instance + * @param [in] interval Frame interval + * @retval None + */ +__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval); +} + +#ifdef USE_HOST_MODE +/** + * @brief Read the register HPRT and reset the following bits. + * @param [in] USBx usb instance + * @retval value of HPRT + */ +//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL) +__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx) +{ +//todo don't have prtovrcurrchng bit + return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG)); +} + +/** + * @brief Issues a ping token + * @param [in] USBx usb instance + * @param [in] hc_num the host channel index + * @retval None + */ +//#define USBFS_HCTSIZ_DOPNG (0x80000000UL) +__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + //todo don't have dopng bit + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA); +} + +/** + * @brief This function returns the frame number for sof packet + * @param [in] USBx usb instance + * @retval Frame number + */ +__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx) +{ + return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL); +} + +/** + * @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type + * @param [in] USBx usb instance + * @param [in] freq clock frequency + * @retval None + */ +__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq) +{ + MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS); +} + +/** + * @brief suspend the port + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PSUSP; + u32hprt &= ~USBFS_HPRT_PRES; + WRITE_REG32(*USBx->HPRT, u32hprt); +} + +/** + * @brief control the enumeration speed of the core, this function make sure that + * the maximum speed supperted by the connected device. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS); +} + +/** + * @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx) +{ +#ifdef USB_FS_MODE + /* USBFS Core*/ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */ + /* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#else + /* USBHS Core */ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#endif +} + +/** + * @brief reset the channel whose channel number is ch_idx + * @param [in] USBx usb instance + * @param [in] ch_idx channel number + * @retval None + */ +__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx) +{ + MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR, + USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR, + USBFS_HCCHAR_CHDIS); +} +#endif /* end of USE_HOST_MODE */ + +extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_setregaddr(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn); +extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num); +extern void usb_rxfifoflush(LL_USB_TypeDef *USBx); +extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode); +extern void usb_coresoftrst(LL_USB_TypeDef *USBx); + +#ifdef USE_HOST_MODE +extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num); +extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hprtrst(LL_USB_TypeDef *USBx); +extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State); +#endif + +#ifdef USE_DEVICE_MODE +extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern void usb_ep0activate(LL_USB_TypeDef *USBx); +extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf); +extern void usb_remotewakeupen(LL_USB_TypeDef *USBx); +extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status); +extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum); +extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link); +#endif + +/** + * @} + */ + +#endif /* LL_USB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h new file mode 100644 index 0000000000..236d7365fd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h @@ -0,0 +1,131 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.h + * @brief This file contains all the functions prototypes of the DDL utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_UTILITY_H__ +#define __HC32_LL_UTILITY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_UTILITY + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup UTILITY_Global_Functions + * @{ + */ + +/* Imprecise delay */ +void DDL_DelayMS(uint32_t u32Count); +void DDL_DelayUS(uint32_t u32Count); + +/* Systick functions */ +int32_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +#if (LL_PRINT_ENABLE == DDL_ON) +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)); +#endif + +/* You can add your own assert functions by implement the function DDL_AssertHandler + definition follow the function DDL_AssertHandler declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do { \ + ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \ +} while (0) +/* Exported function */ +void DDL_AssertHandler(const char *file, int line); +#else +#define DDL_ASSERT(x) ((void)0U) +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) +#include +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData); + +#define DDL_PrintfInit (void)LL_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit) +#define DDL_Printf(...) +#endif + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h new file mode 100644 index 0000000000..ac77925e6d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.h + * @brief This file contains all the functions prototypes of the WDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_WDT_H__ +#define __HC32_LL_WDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_WDT + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Types WDT Global Types + * @{ + */ + +/** + * @brief WDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT. + This parameter can be a value of @ref WDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT. + This parameter can be a value of @ref WDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT. + This parameter can be a value of @ref WDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode). + This parameter can be a value of @ref WDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT. + This parameter can be a value of @ref WDT_Exception_Type */ +} stc_wdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Macros WDT Global Macros + * @{ + */ + +/** + * @defgroup WDT_Count_Period WDT Count Period + * @{ + */ +#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup WDT_Clock_Division WDT Clock Division + * @{ + */ +#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */ +#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */ +#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */ +#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */ +#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */ +#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */ +#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */ +#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */ +/** + * @} + */ + +/** + * @defgroup WDT_Refresh_Range WDT Refresh Range + * @{ + */ +#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */ +#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */ +#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */ +#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */ +#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */ +#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */ +#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */ +#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */ +#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */ +#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup WDT_LPM_Count WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode. + * @{ + */ +#define WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup WDT_Exception_Type WDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup WDT_Flag WDT Flag + * @{ + */ +#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */ +#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */ +#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup WDT_Global_Functions + * @{ + */ + +/** + * @brief Get WDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t WDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +void WDT_FeedDog(void); +uint16_t WDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag); +int32_t WDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32f4a0_ll_interrupts_share.h b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32f4a0_ll_interrupts_share.h new file mode 100644 index 0000000000..f885a2db54 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/inc/hc32f4a0_ll_interrupts_share.h @@ -0,0 +1,583 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ll_interrupts_share.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_LL_SHARE_INTERRUPTS_H__ +#define __HC32F4A0_LL_SHARE_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HC32F4A0_SHARE_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup Share_Interrupts_Global_Functions + * @{ + */ + +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState); + +void IRQ128_Handler(void); +void IRQ129_Handler(void); +void IRQ130_Handler(void); +void IRQ131_Handler(void); +void IRQ132_Handler(void); +void IRQ133_Handler(void); +void IRQ134_Handler(void); +void IRQ135_Handler(void); +void IRQ136_Handler(void); +void IRQ137_Handler(void); +void IRQ138_Handler(void); +void IRQ139_Handler(void); +void IRQ140_Handler(void); +void IRQ141_Handler(void); +void IRQ142_Handler(void); +void IRQ143_Handler(void); + +void EXTINT00_IrqHandler(void); +void EXTINT01_IrqHandler(void); +void EXTINT02_IrqHandler(void); +void EXTINT03_IrqHandler(void); +void EXTINT04_IrqHandler(void); +void EXTINT05_IrqHandler(void); +void EXTINT06_IrqHandler(void); +void EXTINT07_IrqHandler(void); +void EXTINT08_IrqHandler(void); +void EXTINT09_IrqHandler(void); +void EXTINT10_IrqHandler(void); +void EXTINT11_IrqHandler(void); +void EXTINT12_IrqHandler(void); +void EXTINT13_IrqHandler(void); +void EXTINT14_IrqHandler(void); +void EXTINT15_IrqHandler(void); +void DMA1_TC0_IrqHandler(void); +void DMA1_TC1_IrqHandler(void); +void DMA1_TC2_IrqHandler(void); +void DMA1_TC3_IrqHandler(void); +void DMA1_TC4_IrqHandler(void); +void DMA1_TC5_IrqHandler(void); +void DMA1_TC6_IrqHandler(void); +void DMA1_TC7_IrqHandler(void); +void DMA1_BTC0_IrqHandler(void); +void DMA1_BTC1_IrqHandler(void); +void DMA1_BTC2_IrqHandler(void); +void DMA1_BTC3_IrqHandler(void); +void DMA1_BTC4_IrqHandler(void); +void DMA1_BTC5_IrqHandler(void); +void DMA1_BTC6_IrqHandler(void); +void DMA1_BTC7_IrqHandler(void); +void DMA1_Error0_IrqHandler(void); +void DMA1_Error1_IrqHandler(void); +void DMA1_Error2_IrqHandler(void); +void DMA1_Error3_IrqHandler(void); +void DMA1_Error4_IrqHandler(void); +void DMA1_Error5_IrqHandler(void); +void DMA1_Error6_IrqHandler(void); +void DMA1_Error7_IrqHandler(void); +void DMA2_TC0_IrqHandler(void); +void DMA2_TC1_IrqHandler(void); +void DMA2_TC2_IrqHandler(void); +void DMA2_TC3_IrqHandler(void); +void DMA2_TC4_IrqHandler(void); +void DMA2_TC5_IrqHandler(void); +void DMA2_TC6_IrqHandler(void); +void DMA2_TC7_IrqHandler(void); +void DMA2_BTC0_IrqHandler(void); +void DMA2_BTC1_IrqHandler(void); +void DMA2_BTC2_IrqHandler(void); +void DMA2_BTC3_IrqHandler(void); +void DMA2_BTC4_IrqHandler(void); +void DMA2_BTC5_IrqHandler(void); +void DMA2_BTC6_IrqHandler(void); +void DMA2_BTC7_IrqHandler(void); +void DMA2_Error0_IrqHandler(void); +void DMA2_Error1_IrqHandler(void); +void DMA2_Error2_IrqHandler(void); +void DMA2_Error3_IrqHandler(void); +void DMA2_Error4_IrqHandler(void); +void DMA2_Error5_IrqHandler(void); +void DMA2_Error6_IrqHandler(void); +void DMA2_Error7_IrqHandler(void); +void EFM_ProgramEraseError_IrqHandler(void); +void EFM_ColError_IrqHandler(void); +void EFM_OpEnd_IrqHandler(void); +void QSPI_Error_IrqHandler(void); +void MAU_Sqrt_IrqHandler(void); +void DVP_FrameStart_IrqHandler(void); +void DVP_FrameEnd_IrqHandler(void); +void DVP_LineStart_IrqHandler(void); +void DVP_LineEnd_IrqHandler(void); +void DVP_SWSyncError_IrqHandler(void); +void DVP_FifoError_IrqHandler(void); +void FMAC1_IrqHandler(void); +void FMAC2_IrqHandler(void); +void FMAC3_IrqHandler(void); +void FMAC4_IrqHandler(void); +void DCU1_IrqHandler(void); +void DCU2_IrqHandler(void); +void DCU3_IrqHandler(void); +void DCU4_IrqHandler(void); +void DCU5_IrqHandler(void); +void DCU6_IrqHandler(void); +void DCU7_IrqHandler(void); +void DCU8_IrqHandler(void); +void TMR0_1_CmpA_IrqHandler(void); +void TMR0_1_CmpB_IrqHandler(void); +void TMR0_2_CmpA_IrqHandler(void); +void TMR0_2_CmpB_IrqHandler(void); +void TMR2_1_CmpA_IrqHandler(void); +void TMR2_1_CmpB_IrqHandler(void); +void TMR2_1_OvfA_IrqHandler(void); +void TMR2_1_OvfB_IrqHandler(void); +void TMR2_2_CmpA_IrqHandler(void); +void TMR2_2_CmpB_IrqHandler(void); +void TMR2_2_OvfA_IrqHandler(void); +void TMR2_2_OvfB_IrqHandler(void); +void TMR2_3_CmpA_IrqHandler(void); +void TMR2_3_CmpB_IrqHandler(void); +void TMR2_3_OvfA_IrqHandler(void); +void TMR2_3_OvfB_IrqHandler(void); +void TMR2_4_CmpA_IrqHandler(void); +void TMR2_4_CmpB_IrqHandler(void); +void TMR2_4_OvfA_IrqHandler(void); +void TMR2_4_OvfB_IrqHandler(void); +void RTC_TimeStamp0_IrqHandler(void); +void RTC_TimeStamp1_IrqHandler(void); +void RTC_Alarm_IrqHandler(void); +void RTC_Period_IrqHandler(void); +void CLK_XtalStop_IrqHandler(void); +void SWDT_IrqHandler(void); +void WDT_IrqHandler(void); +void PWC_WakeupTimer_IrqHandler(void); +void TMR6_1_GCmpA_IrqHandler(void); +void TMR6_1_GCmpB_IrqHandler(void); +void TMR6_1_GCmpC_IrqHandler(void); +void TMR6_1_GCmpD_IrqHandler(void); +void TMR6_1_GCmpE_IrqHandler(void); +void TMR6_1_GCmpF_IrqHandler(void); +void TMR6_1_GOvf_IrqHandler(void); +void TMR6_1_GUdf_IrqHandler(void); +void TMR6_1_GDte_IrqHandler(void); +void TMR6_1_SCmpUpA_IrqHandler(void); +void TMR6_1_SCmpDownA_IrqHandler(void); +void TMR6_1_SCmpUpB_IrqHandler(void); +void TMR6_1_SCmpDownB_IrqHandler(void); +void TMR6_2_GCmpA_IrqHandler(void); +void TMR6_2_GCmpB_IrqHandler(void); +void TMR6_2_GCmpC_IrqHandler(void); +void TMR6_2_GCmpD_IrqHandler(void); +void TMR6_2_GCmpE_IrqHandler(void); +void TMR6_2_GCmpF_IrqHandler(void); +void TMR6_2_GOvf_IrqHandler(void); +void TMR6_2_GUdf_IrqHandler(void); +void TMR6_2_GDte_IrqHandler(void); +void TMR6_2_SCmpUpA_IrqHandler(void); +void TMR6_2_SCmpDownA_IrqHandler(void); +void TMR6_2_SCmpUpB_IrqHandler(void); +void TMR6_2_SCmpDownB_IrqHandler(void); +void TMR6_3_GCmpA_IrqHandler(void); +void TMR6_3_GCmpB_IrqHandler(void); +void TMR6_3_GCmpC_IrqHandler(void); +void TMR6_3_GCmpD_IrqHandler(void); +void TMR6_3_GCmpE_IrqHandler(void); +void TMR6_3_GCmpF_IrqHandler(void); +void TMR6_3_GOvf_IrqHandler(void); +void TMR6_3_GUdf_IrqHandler(void); +void TMR6_3_GDte_IrqHandler(void); +void TMR6_3_SCmpUpA_IrqHandler(void); +void TMR6_3_SCmpDownA_IrqHandler(void); +void TMR6_3_SCmpUpB_IrqHandler(void); +void TMR6_3_SCmpDownB_IrqHandler(void); +void TMR6_4_GCmpA_IrqHandler(void); +void TMR6_4_GCmpB_IrqHandler(void); +void TMR6_4_GCmpC_IrqHandler(void); +void TMR6_4_GCmpD_IrqHandler(void); +void TMR6_4_GCmpE_IrqHandler(void); +void TMR6_4_GCmpF_IrqHandler(void); +void TMR6_4_GOvf_IrqHandler(void); +void TMR6_4_GUdf_IrqHandler(void); +void TMR6_4_Gdte_IrqHandler(void); +void TMR6_4_SCmpUpA_IrqHandler(void); +void TMR6_4_SCmpDownA_IrqHandler(void); +void TMR6_4_SCmpUpB_IrqHandler(void); +void TMR6_4_SCmpDownB_IrqHandler(void); +void TMR6_5_GCmpA_IrqHandler(void); +void TMR6_5_GCmpB_IrqHandler(void); +void TMR6_5_GCmpC_IrqHandler(void); +void TMR6_5_GCmpD_IrqHandler(void); +void TMR6_5_GCmpE_IrqHandler(void); +void TMR6_5_GCmpF_IrqHandler(void); +void TMR6_5_GOvf_IrqHandler(void); +void TMR6_5_GUdf_IrqHandler(void); +void TMR6_5_Gdte_IrqHandler(void); +void TMR6_5_SCmpUpA_IrqHandler(void); +void TMR6_5_SCmpDownA_IrqHandler(void); +void TMR6_5_SCmpUpB_IrqHandler(void); +void TMR6_5_SCmpDownB_IrqHandler(void); +void TMR6_6_GCmpA_IrqHandler(void); +void TMR6_6_GCmpB_IrqHandler(void); +void TMR6_6_GCmpC_IrqHandler(void); +void TMR6_6_GCmpD_IrqHandler(void); +void TMR6_6_GCmpE_IrqHandler(void); +void TMR6_6_GCmpF_IrqHandler(void); +void TMR6_6_GOvf_IrqHandler(void); +void TMR6_6_GUdf_IrqHandler(void); +void TMR6_6_Gdte_IrqHandler(void); +void TMR6_6_SCmpUpA_IrqHandler(void); +void TMR6_6_SCmpDownA_IrqHandler(void); +void TMR6_6_SCmpUpB_IrqHandler(void); +void TMR6_6_SCmpDownB_IrqHandler(void); +void TMR6_7_GCmpA_IrqHandler(void); +void TMR6_7_GCmpB_IrqHandler(void); +void TMR6_7_GCmpC_IrqHandler(void); +void TMR6_7_GCmpD_IrqHandler(void); +void TMR6_7_GCmpE_IrqHandler(void); +void TMR6_7_GCmpF_IrqHandler(void); +void TMR6_7_GOvf_IrqHandler(void); +void TMR6_7_GUdf_IrqHandler(void); +void TMR6_7_Gdte_IrqHandler(void); +void TMR6_7_SCmpUpA_IrqHandler(void); +void TMR6_7_SCmpDownA_IrqHandler(void); +void TMR6_7_SCmpUpB_IrqHandler(void); +void TMR6_7_SCmpDownB_IrqHandler(void); +void TMR6_8_GCmpA_IrqHandler(void); +void TMR6_8_GCmpB_IrqHandler(void); +void TMR6_8_GCmpC_IrqHandler(void); +void TMR6_8_GCmpD_IrqHandler(void); +void TMR6_8_GCmpE_IrqHandler(void); +void TMR6_8_GCmpF_IrqHandler(void); +void TMR6_8_GOvf_IrqHandler(void); +void TMR6_8_GUdf_IrqHandler(void); +void TMR6_8_Gdte_IrqHandler(void); +void TMR6_8_SCmpUpA_IrqHandler(void); +void TMR6_8_SCmpDownA_IrqHandler(void); +void TMR6_8_SCmpUpB_IrqHandler(void); +void TMR6_8_SCmpDownB_IrqHandler(void); +void TMR4_1_GCmpUH_IrqHandler(void); +void TMR4_1_GCmpUL_IrqHandler(void); +void TMR4_1_GCmpVH_IrqHandler(void); +void TMR4_1_GCmpVL_IrqHandler(void); +void TMR4_1_GCmpWH_IrqHandler(void); +void TMR4_1_GCmpWL_IrqHandler(void); +void TMR4_1_Ovf_IrqHandler(void); +void TMR4_1_Udf_IrqHandler(void); +void TMR4_1_ReloadU_IrqHandler(void); +void TMR4_1_ReloadV_IrqHandler(void); +void TMR4_1_ReloadW_IrqHandler(void); +void TMR4_2_GCmpUH_IrqHandler(void); +void TMR4_2_GCmpUL_IrqHandler(void); +void TMR4_2_GCmpVH_IrqHandler(void); +void TMR4_2_GCmpVL_IrqHandler(void); +void TMR4_2_GCmpWH_IrqHandler(void); +void TMR4_2_GCmpWL_IrqHandler(void); +void TMR4_2_Ovf_IrqHandler(void); +void TMR4_2_Udf_IrqHandler(void); +void TMR4_2_ReloadU_IrqHandler(void); +void TMR4_2_ReloadV_IrqHandler(void); +void TMR4_2_ReloadW_IrqHandler(void); +void TMR4_3_GCmpUH_IrqHandler(void); +void TMR4_3_GCmpUL_IrqHandler(void); +void TMR4_3_GCmpVH_IrqHandler(void); +void TMR4_3_GCmpVL_IrqHandler(void); +void TMR4_3_GCmpWH_IrqHandler(void); +void TMR4_3_GCmpWL_IrqHandler(void); +void TMR4_3_Ovf_IrqHandler(void); +void TMR4_3_Udf_IrqHandler(void); +void TMR4_3_ReloadU_IrqHandler(void); +void TMR4_3_ReloadV_IrqHandler(void); +void TMR4_3_ReloadW_IrqHandler(void); +void TMRA_1_Ovf_IrqHandler(void); +void TMRA_1_Udf_IrqHandler(void); +void TMRA_1_Cmp1_IrqHandler(void); +void TMRA_1_Cmp2_IrqHandler(void); +void TMRA_1_Cmp3_IrqHandler(void); +void TMRA_1_Cmp4_IrqHandler(void); +void TMRA_2_Ovf_IrqHandler(void); +void TMRA_2_Udf_IrqHandler(void); +void TMRA_2_Cmp1_IrqHandler(void); +void TMRA_2_Cmp2_IrqHandler(void); +void TMRA_2_Cmp3_IrqHandler(void); +void TMRA_2_Cmp4_IrqHandler(void); +void TMRA_3_Ovf_IrqHandler(void); +void TMRA_3_Udf_IrqHandler(void); +void TMRA_3_Cmp1_IrqHandler(void); +void TMRA_3_Cmp2_IrqHandler(void); +void TMRA_3_Cmp3_IrqHandler(void); +void TMRA_3_Cmp4_IrqHandler(void); +void TMRA_4_Ovf_IrqHandler(void); +void TMRA_4_Udf_IrqHandler(void); +void TMRA_4_Cmp1_IrqHandler(void); +void TMRA_4_Cmp2_IrqHandler(void); +void TMRA_4_Cmp3_IrqHandler(void); +void TMRA_4_Cmp4_IrqHandler(void); +void TMRA_5_Ovf_IrqHandler(void); +void TMRA_5_Udf_IrqHandler(void); +void TMRA_5_Cmp1_IrqHandler(void); +void TMRA_5_Cmp2_IrqHandler(void); +void TMRA_5_Cmp3_IrqHandler(void); +void TMRA_5_Cmp4_IrqHandler(void); +void TMRA_6_Ovf_IrqHandler(void); +void TMRA_6_Udf_IrqHandler(void); +void TMRA_6_Cmp1_IrqHandler(void); +void TMRA_6_Cmp2_IrqHandler(void); +void TMRA_6_Cmp3_IrqHandler(void); +void TMRA_6_Cmp4_IrqHandler(void); +void TMRA_7_Ovf_IrqHandler(void); +void TMRA_7_Udf_IrqHandler(void); +void TMRA_7_Cmp1_IrqHandler(void); +void TMRA_7_Cmp2_IrqHandler(void); +void TMRA_7_Cmp3_IrqHandler(void); +void TMRA_7_Cmp4_IrqHandler(void); +void TMRA_8_Ovf_IrqHandler(void); +void TMRA_8_Udf_IrqHandler(void); +void TMRA_8_Cmp1_IrqHandler(void); +void TMRA_8_Cmp2_IrqHandler(void); +void TMRA_8_Cmp3_IrqHandler(void); +void TMRA_8_Cmp4_IrqHandler(void); +void TMRA_9_Ovf_IrqHandler(void); +void TMRA_9_Udf_IrqHandler(void); +void TMRA_9_Cmp1_IrqHandler(void); +void TMRA_9_Cmp2_IrqHandler(void); +void TMRA_9_Cmp3_IrqHandler(void); +void TMRA_9_Cmp4_IrqHandler(void); +void TMRA_10_Ovf_IrqHandler(void); +void TMRA_10_Udf_IrqHandler(void); +void TMRA_10_Cmp1_IrqHandler(void); +void TMRA_10_Cmp2_IrqHandler(void); +void TMRA_10_Cmp3_IrqHandler(void); +void TMRA_10_Cmp4_IrqHandler(void); +void TMRA_11_Ovf_IrqHandler(void); +void TMRA_11_Udf_IrqHandler(void); +void TMRA_11_Cmp1_IrqHandler(void); +void TMRA_11_Cmp2_IrqHandler(void); +void TMRA_11_Cmp3_IrqHandler(void); +void TMRA_11_Cmp4_IrqHandler(void); +void TMRA_12_Ovf_IrqHandler(void); +void TMRA_12_Udf_IrqHandler(void); +void TMRA_12_Cmp1_IrqHandler(void); +void TMRA_12_Cmp2_IrqHandler(void); +void TMRA_12_Cmp3_IrqHandler(void); +void TMRA_12_Cmp4_IrqHandler(void); +void EMB_GR0_IrqHandler(void); +void EMB_GR1_IrqHandler(void); +void EMB_GR2_IrqHandler(void); +void EMB_GR3_IrqHandler(void); +void EMB_GR4_IrqHandler(void); +void EMB_GR5_IrqHandler(void); +void EMB_GR6_IrqHandler(void); +void USART1_RxError_IrqHandler(void); +void USART1_RxFull_IrqHandler(void); +void USART1_TxEmpty_IrqHandler(void); +void USART1_TxComplete_IrqHandler(void); +void USART1_RxTO_IrqHandler(void); +void USART2_RxError_IrqHandler(void); +void USART2_RxFull_IrqHandler(void); +void USART2_TxEmpty_IrqHandler(void); +void USART2_TxComplete_IrqHandler(void); +void USART2_RxTO_IrqHandler(void); +void USART3_RxError_IrqHandler(void); +void USART3_RxFull_IrqHandler(void); +void USART3_TxEmpty_IrqHandler(void); +void USART3_TxComplete_IrqHandler(void); +void USART4_RxError_IrqHandler(void); +void USART4_RxFull_IrqHandler(void); +void USART4_TxEmpty_IrqHandler(void); +void USART4_TxComplete_IrqHandler(void); +void USART5_LinBreakField_IrqHandler(void); +void USART5_LinWakeup_IrqHandler(void); +void USART5_RxError_IrqHandler(void); +void USART5_RxFull_IrqHandler(void); +void USART5_TxEmpty_IrqHandler(void); +void USART5_TxComplete_IrqHandler(void); +void USART6_RxError_IrqHandler(void); +void USART6_RxFull_IrqHandler(void); +void USART6_TxEmpty_IrqHandler(void); +void USART6_TxComplete_IrqHandler(void); +void USART6_RxTO_IrqHandler(void); +void USART7_RxError_IrqHandler(void); +void USART7_RxFull_IrqHandler(void); +void USART7_TxEmpty_IrqHandler(void); +void USART7_TxComplete_IrqHandler(void); +void USART7_RxTO_IrqHandler(void); +void USART8_RxError_IrqHandler(void); +void USART8_RxFull_IrqHandler(void); +void USART8_TxEmpty_IrqHandler(void); +void USART8_TxComplete_IrqHandler(void); +void USART9_RxError_IrqHandler(void); +void USART9_RxFull_IrqHandler(void); +void USART9_TxEmpty_IrqHandler(void); +void USART9_TxComplete_IrqHandler(void); +void USART10_LinBreakField_IrqHandler(void); +void USART10_LinWakeup_IrqHandler(void); +void USART10_RxError_IrqHandler(void); +void USART10_RxFull_IrqHandler(void); +void USART10_TxEmpty_IrqHandler(void); +void USART10_TxComplete_IrqHandler(void); +void SPI1_RxFull_IrqHandler(void); +void SPI1_TxEmpty_IrqHandler(void); +void SPI1_Error_IrqHandler(void); +void SPI1_Idle_IrqHandler(void); +void SPI2_RxFull_IrqHandler(void); +void SPI2_TxEmpty_IrqHandler(void); +void SPI2_Error_IrqHandler(void); +void SPI2_Idle_IrqHandler(void); +void SPI3_RxFull_IrqHandler(void); +void SPI3_TxEmpty_IrqHandler(void); +void SPI3_Error_IrqHandler(void); +void SPI3_Idle_IrqHandler(void); +void SPI4_RxFull_IrqHandler(void); +void SPI4_TxEmpty_IrqHandler(void); +void SPI4_Error_IrqHandler(void); +void SPI4_Idle_IrqHandler(void); +void SPI5_RxFull_IrqHandler(void); +void SPI5_TxEmpty_IrqHandler(void); +void SPI5_Error_IrqHandler(void); +void SPI5_Idle_IrqHandler(void); +void SPI6_RxFull_IrqHandler(void); +void SPI6_TxEmpty_IrqHandler(void); +void SPI6_Error_IrqHandler(void); +void SPI6_Idle_IrqHandler(void); +void CAN1_IrqHandler(void); +void CAN2_IrqHandler(void); +void I2S1_Tx_IrqHandler(void); +void I2S1_Rx_IrqHandler(void); +void I2S1_Error_IrqHandler(void); +void I2S2_Tx_IrqHandler(void); +void I2S2_Rx_IrqHandler(void); +void I2S2_Error_IrqHandler(void); +void I2S3_Tx_IrqHandler(void); +void I2S3_Rx_IrqHandler(void); +void I2S3_Error_IrqHandler(void); +void I2S4_Tx_IrqHandler(void); +void I2S4_Rx_IrqHandler(void); +void I2S4_Error_IrqHandler(void); +void USBFS_Global_IrqHandler(void); +void SDIOC1_Normal_IrqHandler(void); +void SDIOC1_Error_IrqHandler(void); +void SDIOC2_Normal_IrqHandler(void); +void SDIOC2_Error_IrqHandler(void); +void ETH_Global_IrqHandler(void); +void ETH_Wakeup_IrqHandler(void); +void I2C1_RxFull_IrqHandler(void); +void I2C1_TxComplete_IrqHandler(void); +void I2C1_TxEmpty_IrqHandler(void); +void I2C1_Error_IrqHandler(void); +void I2C2_RxFull_IrqHandler(void); +void I2C2_TxComplete_IrqHandler(void); +void I2C2_TxEmpty_IrqHandler(void); +void I2C2_Error_IrqHandler(void); +void I2C3_RxFull_IrqHandler(void); +void I2C3_TxComplete_IrqHandler(void); +void I2C3_TxEmpty_IrqHandler(void); +void I2C3_Error_IrqHandler(void); +void I2C4_RxFull_IrqHandler(void); +void I2C4_TxComplete_IrqHandler(void); +void I2C4_TxEmpty_IrqHandler(void); +void I2C4_Error_IrqHandler(void); +void I2C5_RxFull_IrqHandler(void); +void I2C5_TxComplete_IrqHandler(void); +void I2C5_TxEmpty_IrqHandler(void); +void I2C5_Error_IrqHandler(void); +void I2C6_RxFull_IrqHandler(void); +void I2C6_TxComplete_IrqHandler(void); +void I2C6_TxEmpty_IrqHandler(void); +void I2C6_Error_IrqHandler(void); +void PWC_LVD1_IrqHandler(void); +void PWC_LVD2_IrqHandler(void); +void FCM_Error_IrqHandler(void); +void FCM_End_IrqHandler(void); +void FCM_Ovf_IrqHandler(void); +void CTC_Udf_IrqHandler(void); +void CTC_Ovf_IrqHandler(void); +void ADC1_SeqA_IrqHandler(void); +void ADC1_SeqB_IrqHandler(void); +void ADC1_Cmp0_IrqHandler(void); +void ADC1_Cmp1_IrqHandler(void); +void ADC1_CmpComb_IrqHandler(void); +void ADC2_SeqA_IrqHandler(void); +void ADC2_SeqB_IrqHandler(void); +void ADC2_Cmp0_IrqHandler(void); +void ADC2_Cmp1_IrqHandler(void); +void ADC2_CmpComb_IrqHandler(void); +void ADC3_SeqA_IrqHandler(void); +void ADC3_SeqB_IrqHandler(void); +void ADC3_Cmp0_IrqHandler(void); +void ADC3_Cmp1_IrqHandler(void); +void ADC3_CmpComb_IrqHandler(void); +void NFC_IrqHandler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_LL_SHARE_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll.c new file mode 100644 index 0000000000..e8492b76c2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll.c @@ -0,0 +1,170 @@ +/** + ******************************************************************************* + * @file hc32_ll.c + * @brief This file provides firmware functions to low-level drivers (LL). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_Global Global + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup LL_Global_Functions LL Global Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Unlock all EFM registers */ + EFM_REG_Unlock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Unlock FCG register */ + PWC_FCG0_REG_Unlock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Unlock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Unlock all MPU registers */ + MPU_REG_Unlock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Unlock SRAM register: WTCR, CKCR */ + SRAM_REG_Unlock(); + } +#endif +} + +void LL_PERIPH_WP(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Lock all EFM registers */ + EFM_REG_Lock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Lock FCG register */ + PWC_FCG0_REG_Lock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Lock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Lock all MPU registers */ + MPU_REG_Lock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Lock SRAM register: WTCR, CKCR */ + SRAM_REG_Lock(); + } +#endif +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c new file mode 100644 index 0000000000..c03a0e57de --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c @@ -0,0 +1,1174 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.c + * @brief This file provides firmware functions to manage the Analog-to-Digital + * Converter(ADC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_adc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ADC ADC + * @brief Analog-to-Digital Converter Driver Library + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Local_Macros ADC Local Macros + * @{ + */ +/** + * @defgroup ADC_PGA_En ADC PGA Function Control + * @{ + */ +#define ADC_PGA_DISABLE (0x0U) +#define ADC_PGA_ENABLE (0xEU) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_DR_CHSR ADC AWD DR CHSR + * @{ + */ +#define ADC_AWDx_DR(awd, reg_base) (*(__IO uint16_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U))) +#define ADC_AWDx_CHSR(awd, reg_base) (*(__IO uint8_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U))) +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Max ADC Channel Max + * @{ + */ +#define ADC1_CH_MAX (ADC_CH15) +#define ADC2_CH_MAX (ADC_CH15) +#define ADC3_CH_MAX (ADC_CH19) +#define ADC_REMAP_CH_MAX (ADC_CH15) +#define ADC_REMAP_PIN_MAX (ADC12_PIN_PC5) +#define ADC_SSTR_NUM (16U) + +/** + * @} + */ + +/** + * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity + * @{ + */ +#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) + +#define IS_ADC_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* ADC unit check */ +#define IS_ADC_UNIT(x) \ +( ((x) == CM_ADC1) || \ + ((x) == CM_ADC2) || \ + ((x) == CM_ADC3)) + +#define IS_ADC_SEQ(x) (((x) == ADC_SEQ_A) || ((x) == ADC_SEQ_B)) + +/* ADC channel check */ +#define IS_ADC_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_CH_MAX)) || \ + (((adc) == CM_ADC3) && ((ch) <= ADC3_CH_MAX))) + +#define IS_ADC_SCAN_MD(x) \ +( ((x) == ADC_MD_SEQA_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT) || \ + ((x) == ADC_MD_SEQA_SEQB_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT_SEQB_SINGLESHOT)) + +#define IS_ADC_RESOLUTION(x) \ +( ((x) == ADC_RESOLUTION_8BIT) || \ + ((x) == ADC_RESOLUTION_10BIT) || \ + ((x) == ADC_RESOLUTION_12BIT)) + +#define IS_ADC_HARDTRIG(x) \ +( ((x) == ADC_HARDTRIG_ADTRG_PIN) || \ + ((x) == ADC_HARDTRIG_EVT0) || \ + ((x) == ADC_HARDTRIG_EVT1) || \ + ((x) == ADC_HARDTRIG_EVT0_EVT1)) + +#define IS_ADC_DATAALIGN(x) \ +( ((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) + +#define IS_ADC_SEQA_RESUME_MD(x) \ +( ((x) == ADC_SEQA_RESUME_SCAN_CONT) || \ + ((x) == ADC_SEQA_RESUME_SCAN_RESTART)) + +#define IS_ADC_SAMPLE_TIME(x) ((x) >= 5U) + +#define IS_ADC_INT(x) IS_ADC_BIT_MASK(x, ADC_INT_ALL) + +#define IS_ADC_FLAG(x) IS_ADC_BIT_MASK(x, ADC_FLAG_ALL) + +/* Scan-average. */ +#define IS_ADC_AVG_CNT(x) (((x) | ADC_AVG_CNT256) == ADC_AVG_CNT256) + +/* Extended channel. */ +#define IS_ADC_EXTCH_SRC(x) \ +( ((x) == ADC_EXTCH_EXTERN_ANALOG_PIN) || \ + ((x) == ADC_EXTCH_INTERN_ANALOG_SRC)) + +/* Channel remap. */ +#define IS_ADC_REMAP_PIN(adc, pin) (IS_ADC_UNIT(adc) && ((pin) <= ADC_REMAP_PIN_MAX)) +#define IS_ADC_REMAP_CH(adc, ch) (IS_ADC_UNIT(adc) && ((ch) <= ADC_REMAP_CH_MAX)) + +/* Sync mode. */ +#define IS_ADC_SYNC_MD(x) \ +( ((x) == ADC_SYNC_SINGLE_DELAY_TRIG) || \ + ((x) == ADC_SYNC_SINGLE_PARALLEL_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_DELAY_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_PARALLEL_TRIG)) + +#define IS_ADC_SYNC(x) (((x) == ADC_SYNC_ADC1_ADC2) || ((x) == ADC_SYNC_ADC1_ADC2_ADC3)) + +/* Analog watchdog. */ +#define IS_ADC_AWD_MD(x) \ +( ((x) == ADC_AWD_MD_CMP_OUT) || \ + ((x) == ADC_AWD_MD_CMP_IN)) + +#define IS_ADC_AWD(x) ((x) <= ADC_AWD1) + +/* AWD flag check */ +#define IS_ADC_AWD_FLAG(x) IS_ADC_BIT_MASK(x, ADC_AWD_FLAG_ALL) + +/* Two AWD units */ +#define IS_ADC_AWD_COMB_MD(x) \ +( ((x) == ADC_AWD_COMB_INVD) || \ + ((x) == ADC_AWD_COMB_OR) || \ + ((x) == ADC_AWD_COMB_AND) || \ + ((x) == ADC_AWD_COMB_XOR)) + +#define IS_ADC_AWD_INT(x) IS_ADC_BIT_MASK(x, ADC_AWD_INT_ALL) + +/* Sample hold. */ +#define IS_ADC_SPLHOLD_SPLTIME(x) ((x) >= 4U) + +#define IS_ADC_SPLHOLD_UNIT(x) ((x) == CM_ADC1) + +#define IS_ADC_SH_CH(x) ((x) <= ADC_CH2) + +/* PGA */ +#define IS_ADC_PGA_GAIN(x) ((x) <= ADC_PGA_GAIN_32) + +#define IS_ADC_PGA_VSS(x) (((x) == ADC_PGA_VSS_PGAVSS) || ((x) == ADC_PGA_VSS_AVSS)) + +/* PGA unit */ +#define IS_ADC_PGA(adc, pga) \ +( (((adc) == CM_ADC1) && ((pga) <= ADC_PGA3)) || \ + (((adc) == CM_ADC2) && ((pga) == ADC_PGA4))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Functions ADC Global Functions + * @{ + */ + +/** + * @brief Initializes the specified ADC peripheral according to the specified parameters + * in the structure pstcAdcInit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure that contains the + * configuration information for the specified ADC. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (pstcAdcInit != NULL) { + DDL_ASSERT(IS_ADC_SCAN_MD(pstcAdcInit->u16ScanMode)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcAdcInit->u16Resolution)); + DDL_ASSERT(IS_ADC_DATAALIGN(pstcAdcInit->u16DataAlign)); + + /* Configures scan mode, resolution, data align. */ + WRITE_REG16(ADCx->CR0, pstcAdcInit->u16ScanMode | \ + pstcAdcInit->u16Resolution | \ + pstcAdcInit->u16DataAlign); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitializes the specified ADC peripheral registers to their default reset values. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_DeInit(CM_ADC_TypeDef *ADCx) +{ + /* SSTRx */ + uint8_t i; + __IO uint8_t *reg8SSTR; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + /* Stop the ADC. */ + WRITE_REG8(ADCx->STR, 0U); + + /* Set the registers to reset value. */ + WRITE_REG16(ADCx->CR0, 0x0U); + WRITE_REG16(ADCx->CR1, 0x0U); + WRITE_REG16(ADCx->TRGSR, 0x0U); + WRITE_REG32(ADCx->CHSELRA, 0x0U); + WRITE_REG32(ADCx->CHSELRB, 0x0U); + WRITE_REG8(ADCx->ICR, 0x03U); + /* AVCHSELR */ + WRITE_REG32(ADCx->AVCHSELR, 0x0U); + + /* SSTRx */ + reg8SSTR = (__IO uint8_t *)((uint32_t)&ADCx->SSTR0); + for (i = 0U; i < ADC_SSTR_NUM; i++) { + reg8SSTR[i] = 0x0BU; + } + + /* SSTRL */ + if (ADCx == CM_ADC3) { + WRITE_REG8(ADCx->SSTRL, 0x0BU); + } + + /* CHMUXRx */ + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + + /* ISR clearing */ + WRITE_REG8(ADCx->ISCLRR, 0x13U); + + /* Sync mode */ + WRITE_REG16(ADCx->SYNCCR, 0x0U); + + /* Analog watchdog */ + WRITE_REG16(ADCx->AWDCR, 0x0U); + WRITE_REG8(ADCx->AWDSCLRR, 0x13U); + WRITE_REG16(ADCx->AWD0DR0, 0x0U); + WRITE_REG16(ADCx->AWD0DR1, 0xFFFFU); + WRITE_REG16(ADCx->AWD1DR0, 0x0U); + WRITE_REG16(ADCx->AWD1DR1, 0xFFFFU); + WRITE_REG8(ADCx->AWD0CHSR, 0x0U); + WRITE_REG8(ADCx->AWD1CHSR, 0x0U); + + /* Sample hold */ + WRITE_REG16(ADCx->SHCR, 0x0U); + + /* PGA and OPA */ + if (ADCx == CM_ADC1) { + WRITE_REG8(ADCx->PGACR1, 0x0U); + WRITE_REG8(ADCx->PGACR2, 0x0U); + WRITE_REG8(ADCx->PGACR3, 0x0U); + WRITE_REG8(ADCx->PGAVSSENR, 0x0U); + } else if (ADCx == CM_ADC2) { + WRITE_REG8(ADCx->PGACR1, 0x0U); + WRITE_REG8(ADCx->PGAVSSENR, 0x0U); + } else { + /* rsvd */ + } +} + +/** + * @brief Set each @ref stc_adc_init_t field to default value. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcAdcInit != NULL) { + pstcAdcInit->u16ScanMode = ADC_MD_SEQA_SINGLESHOT; + pstcAdcInit->u16Resolution = ADC_RESOLUTION_12BIT; + pstcAdcInit->u16DataAlign = ADC_DATAALIGN_RIGHT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Seq The sequence whose channel specified by 'u8Ch' will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: ADC sequence A. + * @arg ADC_SEQ_B: ADC sequence B. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note Sequence A can always started by software(by calling @ref ADC_Start()), + * regardless of whether the hardware trigger source is valid or not. + * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig() + * and @ref ADC_TriggerCmd(). + */ +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint32_t u32CHSELAddr; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL); + if (enNewState == ENABLE) { + /* Enable the specified channel. */ + SET_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } else { + /* Disable the specified channel. */ + CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } +} + +/** + * @brief Set sampling time for the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The channel to be set sampling time. + * This parameter can be values of @ref ADC_Channel + * @param [in] u8SampleTime Sampling time for the channel that specified by 'u8Ch'. + * @retval None + */ +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_SAMPLE_TIME(u8SampleTime)); + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + if (u8Ch < ADC_SSTR_NUM) { + u32Addr = (uint32_t)&ADCx->SSTR0 + u8Ch; + WRITE_REG8(RW_MEM8(u32Addr), u8SampleTime); + } else { + WRITE_REG8(ADCx->SSTRL, u8SampleTime); + } + +} + +/** + * @brief Set scan-average count. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16AverageCount Scan-average count. + * This parameter can be a value of @ref ADC_Average_Count + * @arg ADC_AVG_CNT2: 2 consecutive average conversions. + * @arg ADC_AVG_CNT4: 4 consecutive average conversions. + * @arg ADC_AVG_CNT8: 8 consecutive average conversions. + * @arg ADC_AVG_CNT16: 16 consecutive average conversions. + * @arg ADC_AVG_CNT32: 32 consecutive average conversions. + * @arg ADC_AVG_CNT64: 64 consecutive average conversions. + * @arg ADC_AVG_CNT128: 128 consecutive average conversions. + * @arg ADC_AVG_CNT256: 256 consecutive average conversions. + * @retval None + */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AVG_CNT(u16AverageCount)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AverageCount); +} + +/** + * @brief Enable or disable conversion data average calculation channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } else { + CLR_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } +} + +/** + * @brief Specifies the analog input source of extended channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8ExtChSrc The analog input source of extended channel. + * This paramter can be a value of @ref ADC_Ext_Ch_Analog_Src + * @retval None + */ +void ADC_SetExtChSrc(CM_ADC_TypeDef *ADCx, uint8_t u8ExtChSrc) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_EXTCH_SRC(u8ExtChSrc)); + WRITE_REG8(ADCx->EXCHSELR, u8ExtChSrc); +} + +/** + * @brief Specifies the hard trigger for the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] u16TriggerSel Hard trigger selection. This parameter can be a value of @ref ADC_Hard_Trigger_Sel + * @arg ADC_HARDTRIG_ADTRG_PIN: Selects the following edge of pin ADTRG as the trigger of ADC sequence. + * @arg ADC_HARDTRIG_EVT0: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR0(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT1: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR1(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT0_EVT1: Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_ITRGSELR0 and register ADCx_ITRGSELR1. + * @retval None + * @note ADC must be stopped while calling this function. + * @note The trigger source CANNOT be an event that generated by the sequence itself. + */ +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_ADC_HARDTRIG(u16TriggerSel)); + + u8Seq *= ADC_TRGSR_TRGSELB_POS; + MODIFY_REG16(ADCx->TRGSR, \ + (uint32_t)ADC_TRGSR_TRGSELA << u8Seq, \ + (uint32_t)u16TriggerSel << u8Seq); +} + +/** + * @brief Enable or disable the hard trigger of the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note ADC must be stopped while calling this function. + */ +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->TRGSR; + /* Enable bit position: u8Seq * sequence_offset + enable_bit_base. */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (uint32_t)u8Seq * ADC_TRGSR_TRGSELB_POS + ADC_TRGSR_TRGENA_POS), enNewState); +} + +/** + * @brief Enable or disable ADC interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8IntType ADC interrupt. + * This parameter can be values of @ref ADC_Int_Type + * @arg ADC_INT_EOCA: Interrupt of the end of conversion of sequence A. + * @arg ADC_INT_EOCB: Interrupt of the end of conversion of sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(ADCx->ICR, u8IntType); + } else { + CLR_REG8_BIT(ADCx->ICR, u8IntType); + } +} + +/** + * @brief Start sequence A conversion. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Start(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, ADC_STR_STRT); +} + +/** + * @brief Stop ADC conversion, both sequence A and sequence B. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Stop(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, 0U); +} + +/** + * @brief Get the ADC value of the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @retval An uint16_t type value of ADC value. + */ +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + + return RW_MEM16((uint32_t)&ADCx->DR0 + u8Ch * 2UL); +} + +/** + * @brief Get the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be a value of @ref ADC_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + if (READ_REG8_BIT(ADCx->ISR, u8Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be valueS of @ref ADC_Status_Flag + * @retval None + */ +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + WRITE_REG8(ADCx->ISCLRR, u8Flag); +} + +/** + * @brief Remap the correspondence between ADC channel and analog input pins. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch This parameter can be values of @ref ADC_Channel + * @param [in] u8AdcPin This parameter can be a value of @ref ADC_Remap_Pin + * @retval None + */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin) +{ + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_REMAP_PIN(ADCx, u8AdcPin)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + MODIFY_REG16(regCHMUXR[u8RegIdx], \ + ((uint32_t)ADC_CHMUXR0_CH00MUX << u8FieldOfs), \ + ((uint32_t)u8AdcPin << u8FieldOfs)); +} + +/** + * @brief Get the ADC pin corresponding to the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch ADC channel. + * This parameter can be one of the following values of @ref ADC_Channel + * @retval An uint8_t type value of ADC pin. @ref ADC_Remap_Pin + */ +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + uint8_t u8RetPin; + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + u8RetPin = ((uint8_t)(regCHMUXR[u8RegIdx] >> u8FieldOfs)) & 0xFU; + + return u8RetPin; +} + +/** + * @brief Reset channel-pin mapping. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); +} + +/** + * @brief Configures synchronous mode. + * @param [in] u16SyncUnit Specify the ADC units which work synchronously. + * This parameter can be a value of @ref ADC_Sync_Unit + * @param [in] u16SyncMode Synchronous mode. + * This parameter can be a value of @ref ADC_Sync_Mode + * @arg ADC_SYNC_SINGLE_DELAY_TRIG: Single shot delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan once. + * @arg ADC_SYNC_SINGLE_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan once. + * @arg ADC_SYNC_CYCLIC_DELAY_TRIG: Cyclic delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan cyclicly(keep scaning till you stop them). + * @arg ADC_SYNC_CYCLIC_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan cyclicly(keep scaning till you stop them). + * @param [in] u8TriggerDelay Trigger delay time(ADCLK cycle), range is [1, 255]. + * @retval None + */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay) +{ + DDL_ASSERT(IS_ADC_SYNC(u16SyncUnit)); + DDL_ASSERT(IS_ADC_SYNC_MD(u16SyncMode)); + + u16SyncMode |= ((uint16_t)((uint32_t)u8TriggerDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit; + MODIFY_REG16(CM_ADC1->SYNCCR, ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY, u16SyncMode); +} + +/** + * @brief Enable or disable synchronous mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_SyncModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_ADC1->SYNCCR_b.SYNCEN, enNewState); +} + +/** + * @brief Configures analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @param [in] pstcAwd Pointer to a @ref stc_adc_awd_config_t structure value that + * contains the configuration information of the AWD. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAwd == NULL. + */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd) +{ + uint32_t u32AwdDr0; + uint32_t u32AwdDr1; + uint32_t u32AwdChsr; + uint32_t u32Addr; + uint8_t u8Pos; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + if (pstcAwd != NULL) { + DDL_ASSERT(IS_ADC_AWD_MD(pstcAwd->u16WatchdogMode)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0; + u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1; + u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR; + + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), pstcAwd->u16WatchdogMode); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), pstcAwd->u16LowThreshold); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), pstcAwd->u16HighThreshold); + WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies combination mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16CombMode Combination mode of analog watchdog. + * This parameter can be a value of @ref ADC_AWD_Comb_Mode + * @arg ADC_AWD_COMB_INVD Combination mode is invalid. + * @arg ADC_AWD_COMB_OR: The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_AND: The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_XOR: Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. + * @retval None + */ +void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_COMB_MD(u16CombMode)); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDCM, u16CombMode); +} + +/** + * @brief Specifies the comapre mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16WatchdogMode Analog watchdog comapre mode. + * This parameter can be a value of @ref ADC_AWD_Mode + * @arg ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * @arg ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + * @retval None + */ +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode) +{ + uint8_t u8Pos; + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_ADC_AWD_MD(u16WatchdogMode)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), u16WatchdogMode); +} + +/** + * @brief Get the comapre mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @retval Analog watchdog compare mode. A value of @ref ADC_AWD_Mode + * - ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * - ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + */ +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit) +{ + uint16_t u16RetMode; + + uint8_t u8Pos; + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + u16RetMode = (uint16_t)PERIPH_BIT_BAND(u32Addr, u8Pos); + + return u16RetMode; +} + +/** + * @brief Specifies the low threshold and high threshold of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16LowThreshold Low threshold of analog watchdog. + * @param [in] u16HighThreshold High threshold of analog watchdog. + * @retval None + */ +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold) +{ + uint32_t u32AwdDr0; + uint32_t u32AwdDr1; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0; + u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1; + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), u16LowThreshold); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), u16HighThreshold); +} + +/** + * @brief Select the specified ADC channel as an analog watchdog channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + uint32_t u32AwdChsr; + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR; + WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch); +} + +/** + * @brief Enable or disable the specified analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->AWDCR; + /* Enable bit position: u8AwdUnit * 4 */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (u8AwdUnit * 4UL)), enNewState); +} + +/** + * @brief Enable or disable the specified analog watchdog interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16IntType Interrupt of AWD. + * This parameter can be a value of @ref ADC_AWD_Int_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_INT(u16IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->AWDCR, u16IntType); + } else { + CLR_REG16_BIT(ADCx->AWDCR, u16IntType); + } +} + +/** + * @brief Get the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag)); + if (READ_REG8_BIT(ADCx->AWDSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval None + */ +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag)); + WRITE_REG8(ADCx->AWDSCLRR, u32Flag); +} + +/** + * @brief Specifies sampling time of sample-hold. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8SampleTime Sampling time of sample hold. + * @retval None + */ +void ADC_SH_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8SampleTime) +{ + DDL_ASSERT(IS_ADC_SPLHOLD_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SPLHOLD_SPLTIME(u8SampleTime)); + MODIFY_REG16(ADCx->SHCR, ADC_SHCR_SHSST, u8SampleTime); +} + +/** + * @brief Enable or disable sample-hold channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch Sample hold channel. + * This parameter can be ADC_CH0, ADC_CH1 and ADC_CH2 of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_SH_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_SPLHOLD_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SH_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->SHCR, (1UL << u8Ch) << ADC_SHCR_SHSEL_POS); + } else { + CLR_REG16_BIT(ADCx->SHCR, (1UL << u8Ch) << ADC_SHCR_SHSEL_POS); + } +} + +/** + * @brief Configures the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] u8Gain Gain of the specified PGA. + * This parameter can be a value of @ref ADC_PGA_Gain + * @arg ADC_PGA_GAIN_2: PGA gain factor is 2. + * @arg ADC_PGA_GAIN_2P133: PGA gain factor is 2.133. + * @arg ADC_PGA_GAIN_2P286: PGA gain factor is 2.286. + * @arg ADC_PGA_GAIN_2P667: PGA gain factor is 2.667. + * @arg ADC_PGA_GAIN_2P909: PGA gain factor is 2.909. + * @arg ADC_PGA_GAIN_3P2: PGA gain factor is 3.2. + * @arg ADC_PGA_GAIN_3P556: PGA gain factor is 2.556. + * @arg ADC_PGA_GAIN_4: PGA gain factor is 4. + * @arg ADC_PGA_GAIN_4P571: PGA gain factor is 4.571. + * @arg ADC_PGA_GAIN_5P333: PGA gain factor is 5.333. + * @arg ADC_PGA_GAIN_6P4: PGA gain factor is 6.4. + * @arg ADC_PGA_GAIN_8: PGA gain factor is 8. + * @arg ADC_PGA_GAIN_10P667: PGA gain factor is 10.667. + * @arg ADC_PGA_GAIN_16: PGA gain factor is 16. + * @arg ADC_PGA_GAIN_32: PGA gain factor is 32. + * @param [in] u8PgaVss VSS for the specified PGA. + * This parameter can be a value of @ref ADC_PGA_VSS + * @arg ADC_PGA_VSS_PGAVSS: Use pin PGAx_VSS as the reference GND of PGAx + * @arg ADC_PGA_VSS_AVSS: Use AVSS as the reference GND of PGAx. + * @retval None + */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss) +{ + uint32_t u32Addr; + uint32_t u32PGACRAddr; + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_ADC_PGA_GAIN(u8Gain)); + DDL_ASSERT(IS_ADC_PGA_VSS(u8PgaVss)); + + if (ADCx == CM_ADC2) { + u8PgaUnit = 0U; + } + u32PGACRAddr = (uint32_t)&ADCx->PGACR1 + u8PgaUnit; + MODIFY_REG8(RW_MEM8(u32PGACRAddr), ADC_PGACR_PGAGAIN, u8Gain << ADC_PGACR_PGAGAIN_POS); + u32Addr = (uint32_t)&ADCx->PGAVSSENR; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8PgaUnit), u8PgaVss); +} + +/** + * @brief Enable the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState) +{ + const uint8_t au8Cmd[] = {ADC_PGA_DISABLE, ADC_PGA_ENABLE}; + uint32_t u32PGACRAddr; + + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ADCx == CM_ADC2) { + u8PgaUnit = 0U; + } + u32PGACRAddr = (uint32_t)&ADCx->PGACR1 + u8PgaUnit; + MODIFY_REG8(RW_MEM8(u32PGACRAddr), ADC_PGACR_PGACTL, au8Cmd[(uint8_t)enNewState]); +} + +/** + * @brief Enable or disable automatically clear data register. + * The automatic clearing function is mainly used to detect whether the data register is updated. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } else { + CLR_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } +} + +/** + * @brief Sequence A restart channel selection. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16SeqAResumeMode Sequence A resume mode. + * This parameter can be a value of @ref ADC_SeqA_Resume_Mode + * @arg ADC_SEQA_RESUME_SCAN_CONT: Scanning will continue from the interrupted channel. + * @arg ADC_SEQA_RESUME_SCAN_RESTART: Scanning will start from the first channel. + * @retval None + */ +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQA_RESUME_MD(u16SeqAResumeMode)); + WRITE_REG16(ADCx->CR1, u16SeqAResumeMode); +} + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c new file mode 100644 index 0000000000..674cbe9e83 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c @@ -0,0 +1,287 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.c + * @brief This file provides firmware functions to manage the Advanced Encryption + * Standard(AES). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aes.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AES AES + * @brief AES Driver Library + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Local_Macros AES Local Macros + * @{ + */ +/* Delay count for timeout */ +#define AES_TIMEOUT (30000UL) + +/* AES block size */ +#define AES_BLOCK_SIZE (16U) + +/** + * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity + * @{ + */ +#define IS_AES_KEY_SIZE(x) \ +( ((x) == AES_KEY_SIZE_16BYTE) || \ + ((x) == AES_KEY_SIZE_24BYTE) || \ + ((x) == AES_KEY_SIZE_32BYTE)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AES_Local_Functions AES Local Functions + * @{ + */ +/** + * @brief Write the input buffer in data register. + * @param [in] pu8SrcData Point to the source data buffer. + * @retval None + */ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData); + + for (i = 0U; i < 4U; i++) { + regDR[i] = pu32Data[i]; + } +} + +/** + * @brief Read the from data register. + * @param [out] pu8Result Point to the result buffer. + * @retval None + */ +static void AES_ReadData(uint8_t *pu8Result) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result); + + for (i = 0U; i < 4U; i++) { + pu32Result[i] = regDR[i]; + } +} + +/** + * @brief Write the input buffer in key register. + * @param [in] pu8Key Pointer to the key buffer. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @retval None + */ +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize) +{ + uint8_t i; + uint8_t u8KeyWordSize = u8KeySize / 4U; + __IO uint32_t *regKR = &CM_AES->KR0; + const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key); + + for (i = 0U; i < u8KeyWordSize; i++) { + regKR[i] = pu32Key[i]; + } + switch (u8KeySize) { + case 16U: + u8KeySize = 0U; + break; + case 24U: + u8KeySize = 1U; + break; + case 32U: + u8KeySize = 2U; + break; + default: + break; + } + MODIFY_REG32(CM_AES->CR, AES_CR_KEYSIZE, ((uint32_t)u8KeySize << AES_CR_KEYSIZE_POS)); +} + +/** + * @brief Wait AES operation done. + * @param None + * @retval None + */ +static int32_t AES_WaitDone(void) +{ + __IO uint32_t u32TimeCount = 0UL; + int32_t i32Ret = LL_OK; + + while (bCM_AES->CR_b.START != 0UL) { + if (u32TimeCount++ >= AES_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup AES_Global_Functions AES Global Functions + * @{ + */ + +/** + * @brief AES encryption. + * @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted). + * @param [in] u32PlaintextSize Length of plaintext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Ciphertext Buffer of the ciphertext. + * @retval int32_t: + * - LL_OK: Encrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Encrypt timeout. + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES encrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 0UL); + while (u32Index < u32PlaintextSize) { + AES_WriteData(&pu8Plaintext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Ciphertext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief AES decryption. + * @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted). + * @param [in] u32CiphertextSize Length of ciphertext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Plaintext Buffer of the plaintext. + * @retval int32_t: + * - LL_OK: Decrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Decrypt timeout. + */ +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES decrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 1UL); + while (u32Index < u32CiphertextSize) { + AES_WriteData(&pu8Ciphertext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Plaintext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c new file mode 100644 index 0000000000..fe47df5317 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.c + * @brief This file provides firmware functions to manage the AOS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aos.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AOS AOS + * @brief AOS Driver Library + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Local_Macros AOS Local Macros + * @{ + */ + +/** + * @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity + * @{ + */ +#define IS_AOS_COMM_TRIG(x) \ +( ((x) != 0UL) && \ + ((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Validity AOS Trigger Select Validity + * @{ + */ +#define IS_AOS_TRIG_SEL(x) \ +( ((x) == AOS_DCU1) || \ + ((x) == AOS_DCU2) || \ + ((x) == AOS_DCU3) || \ + ((x) == AOS_DCU4) || \ + ((x) == AOS_DMA1_0) || \ + ((x) == AOS_DMA1_1) || \ + ((x) == AOS_DMA1_2) || \ + ((x) == AOS_DMA1_3) || \ + ((x) == AOS_DMA1_4) || \ + ((x) == AOS_DMA1_5) || \ + ((x) == AOS_DMA1_6) || \ + ((x) == AOS_DMA1_7) || \ + ((x) == AOS_DMA2_0) || \ + ((x) == AOS_DMA2_1) || \ + ((x) == AOS_DMA2_2) || \ + ((x) == AOS_DMA2_3) || \ + ((x) == AOS_DMA2_4) || \ + ((x) == AOS_DMA2_5) || \ + ((x) == AOS_DMA2_6) || \ + ((x) == AOS_DMA2_7) || \ + ((x) == AOS_DMA_RC) || \ + ((x) == AOS_TMR6_0) || \ + ((x) == AOS_TMR6_1) || \ + ((x) == AOS_TMR6_2) || \ + ((x) == AOS_TMR6_3) || \ + ((x) == AOS_EVTPORT12) || \ + ((x) == AOS_EVTPORT34) || \ + ((x) == AOS_TMR0) || \ + ((x) == AOS_TMR2) || \ + ((x) == AOS_HASH_A) || \ + ((x) == AOS_HASH_B) || \ + ((x) == AOS_TMRA_0) || \ + ((x) == AOS_TMRA_1) || \ + ((x) == AOS_TMRA_2) || \ + ((x) == AOS_TMRA_3) || \ + ((x) == AOS_OTS) || \ + ((x) == AOS_ADC1_0) || \ + ((x) == AOS_ADC1_1) || \ + ((x) == AOS_ADC2_0) || \ + ((x) == AOS_ADC2_1) || \ + ((x) == AOS_ADC3_0) || \ + ((x) == AOS_ADC3_1) || \ + ((x) == AOS_COMM_1) || \ + ((x) == AOS_COMM_2)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Functions AOS Global Functions + * @{ + */ + +/** + * @brief Event Port Hardware trigger common event function command + * @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details + * @param [in] u32CommonTrigger Common trigger ID + * This parameter can be one of the following values: + * @arg AOS_COMM_TRIG1: Common trigger 1. + * @arg AOS_COMM_TRIG2: Common trigger 2. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel)); + DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger); + } else { + CLR_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger); + } +} + +/** + * @brief Event Port Hardware trigger common event function command + * @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details + * @param [in] enEvent Event source configuration, @ref en_event_src_t in details + * @retval None + */ +void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent) +{ + DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel)); + + MODIFY_REG32(*(__IO uint32_t *)u32TriggerSel, AOS_TRIG_SEL_MASK, enEvent); +} + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c new file mode 100644 index 0000000000..6957be459f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c @@ -0,0 +1,1497 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.c + * @brief This file provides firmware functions to manage the CAN. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_can.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CAN CAN + * @brief CAN Driver Library + * @{ + */ + +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Macros CAN Local Macros + * @{ + */ + +/** + * @defgroup CAN_Check_Parameters_Validity CAN Check Parameters Validity + * @{ + */ +#define IS_CAN_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_CAN_FUNC_EN(x, en) (((x) == 0U) || ((x) == (en))) + +/* CAN unit */ +#define IS_CAN_UNIT(x) (((x) == CM_CAN1) || ((x) == CM_CAN2)) +#define IS_CAN_FD_UNIT(x) ((x) == CM_CAN2) + +#define IS_CAN_BIT_TIME_PRESC(x) (((x) >= 1U) && ((x) <= 256U)) + +#define IS_CAN_WORK_MD(x) ((x) <= CAN_WORK_MD_ELB_SILENT) + +#define IS_CAN_TX_BUF_TYPE(x) (((x) == CAN_TX_BUF_PTB) || ((x) == CAN_TX_BUF_STB)) + +#define IS_CAN_PTB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_PTB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_STB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_PRIO_MD(x) IS_CAN_FUNC_EN(x, CAN_STB_PRIO_MD_ENABLE) + +#define IS_CAN_TX_REQ(x) IS_CAN_BIT_MASK(x, CAN_TX_REQ_STB_ONE|CAN_TX_REQ_STB_ALL|CAN_TX_REQ_PTB) + +#define IS_CAN_RX_ALL_FRAME(x) IS_CAN_FUNC_EN(x, CAN_RX_ALL_FRAME_ENABLE) + +#define IS_CAN_RX_OVF_MD(x) (((x) == CAN_RX_OVF_SAVE_NEW) || ((x) == CAN_RX_OVF_DISCARD_NEW)) + +#define IS_CAN_SELF_ACK(x) IS_CAN_FUNC_EN(x, CAN_SELF_ACK_ENABLE) + +#define IS_CAN_INT(x) IS_CAN_BIT_MASK(x, CAN_INT_ALL) + +#define IS_CAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_FLAG_ALL) + +#define IS_CAN_ID(ide, x) \ +( (((ide) == 1U) && (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL)) || \ + (((ide) == 0U) && (((x) | 0x7FFUL) == 0x7FFUL))) + +#define IS_CAN_ID_MASK(x) (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL) + +#define IS_CAN_IDE(x) (((x) == 0U) || ((x) == 1U)) + +#define IS_CAN_FILTER(x) IS_CAN_BIT_MASK(x, CAN_FILTER_ALL) + +#define IS_CAN_RX_WARN(x) (((x) >= CAN_RX_WARN_MIN) && ((x) <= CAN_RX_WARN_MAX)) + +#define IS_CAN_ERR_WARN(x) ((x) < 16U) + +#define IS_CAN_FD_MD(x) (((x) == CAN_FD_MD_BOSCH) || ((x) == CAN_FD_MD_ISO)) + +#define IS_CAN_FD_TDC(x) IS_CAN_FUNC_EN(x, CAN_FD_TDC_ENABLE) + +#define IS_CAN_FD_SSP(x) ((x) < 128U) + +#define IS_TTCAN_TX_BUF_MD(x) (((x) == CAN_TTC_TX_BUF_MD_CAN) || ((x) == CAN_TTC_TX_BUF_MD_TTCAN)) + +#define IS_TTCAN_TX_BUF_SEL(x) ((x) <= CAN_TTC_TX_BUF_STB3) + +#define IS_TTCAN_INT(x) IS_CAN_BIT_MASK(x, CAN_TTC_INT_ALL) + +#define IS_TTCAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_TTC_FLAG_ALL) + +#define IS_TTCAN_TX_EN_WINDOW(x) (((x) > 0U) && ((x) <= 16U)) + +#define IS_TTCAN_NTU_PRESCALER(x) \ +( ((x) == CAN_TTC_NTU_PRESCALER1) || \ + ((x) == CAN_TTC_NTU_PRESCALER2) || \ + ((x) == CAN_TTC_NTU_PRESCALER4) || \ + ((x) == CAN_TTC_NTU_PRESCALER8)) + +#define IS_TTCAN_TRIG_TYPE(x) \ +( ((x) == CAN_TTC_TRIG_IMMED_TRIG) || \ + ((x) == CAN_TTC_TRIG_TIME_TRIG) || \ + ((x) == CAN_TTC_TRIG_SINGLESHOT_TX_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_START_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_STOP_TRIG)) + +#define IS_CAN_ID_TYPE(x) \ +( ((x) == CAN_ID_STD_EXT) || \ + ((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) + +#define IS_CAN_SBT(seg1, seg2, sjw) \ +( (((seg1) >= 2U) && ((seg1) <= 65U)) && \ + (((seg2) >= 1U) && ((seg2) <= 8U)) && \ + (((sjw) >= 1U) && ((sjw) <= 16U)) && \ + ((seg1) >= ((seg2) + 1U)) && \ + ((seg2) >= (sjw))) + +#define IS_CAN_FD_SBT(seg1, seg2, sjw) \ +( (((seg1) >= 2U) && ((seg1) <= 65U)) && \ + (((seg2) >= 1U) && ((seg2) <= 32U)) && \ + (((sjw) >= 1U) && ((sjw) <= 16U)) && \ + ((seg1) >= ((seg2) + 1U)) && \ + ((seg2) >= (sjw))) + +#define IS_CAN_FD_FBT(seg1, seg2, sjw) \ +( (((seg1) >= 2U) && ((seg1) <= 17U)) && \ + (((seg2) >= 1U) && ((seg2) <= 8U)) && \ + (((sjw) >= 1U) && ((sjw) <= 8U)) && \ + ((seg1) >= ((seg2) + 1U)) && \ + ((seg2) >= (sjw))) + +/* CAN Data Length Code(DLC) */ +#define IS_CAN20_DLC(fdf, dlc) (((fdf) == 0U) && ((dlc) <= CAN_DLC8)) + +/** + * @} + */ + +/** + * @defgroup CAN_Miscellaneous_Macros CAN Miscellaneous Macros + * @{ + */ +/* CAN buffer number */ +#define CAN_RX_BUF_NUM (8U) + +#define CAN_RX_WARN_MIN (1U) +#define CAN_RX_WARN_MAX (CAN_RX_BUF_NUM) + +#define CAN_ERRINT_FLAG_MASK (CAN_ERRINT_BEIF | CAN_ERRINT_ALIF | CAN_ERRINT_EPIF) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Variables CAN Local Variables + * @{ + */ +const static uint8_t m_au8DLC2Size[16U] = { + 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Functions CAN Local Functions + * @{ + */ + +#if defined __DEBUG +/** + * @brief Initialization parameter check. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval None + */ +static void CAN_InitParameterCheck(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + stc_canfd_config_t *pstcCanFd = pstcCanInit->pstcCanFd; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_WORK_MD(pstcCanInit->u8WorkMode)); + DDL_ASSERT(IS_CAN_PTB_SINGLESHOT_TX(pstcCanInit->u8PTBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_SINGLESHOT_TX(pstcCanInit->u8STBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_PRIO_MD(pstcCanInit->u8STBPrioMode)); + DDL_ASSERT(IS_CAN_RX_WARN(pstcCanInit->u8RxWarnLimit)); + DDL_ASSERT(IS_CAN_ERR_WARN(pstcCanInit->u8ErrorWarnLimit)); + DDL_ASSERT(IS_CAN_FILTER(pstcCanInit->u16FilterSelect)); + DDL_ASSERT(IS_CAN_RX_ALL_FRAME(pstcCanInit->u8RxAllFrame)); + DDL_ASSERT(IS_CAN_RX_OVF_MD(pstcCanInit->u8RxOvfMode)); + DDL_ASSERT(IS_CAN_SELF_ACK(pstcCanInit->u8SelfAck)); + + if (pstcCanFd != NULL) { + DDL_ASSERT(IS_CAN_FD_UNIT(CANx)); + DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler)); + DDL_ASSERT(IS_CAN_FD_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1, + pstcCanInit->stcBitCfg.u32TimeSeg2, + pstcCanInit->stcBitCfg.u32SJW)); + + DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanFd->stcBitCfg.u32Prescaler)); + DDL_ASSERT(IS_CAN_FD_FBT(pstcCanFd->stcBitCfg.u32TimeSeg1, + pstcCanFd->stcBitCfg.u32TimeSeg2, + pstcCanFd->stcBitCfg.u32SJW)); + + DDL_ASSERT(IS_CAN_FD_MD(pstcCanFd->u8Mode)); + DDL_ASSERT(IS_CAN_FD_TDC(pstcCanFd->u8TDC)); + DDL_ASSERT(IS_CAN_FD_SSP(pstcCanFd->u8SSPOffset)); + } else { + DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler)); + DDL_ASSERT(IS_CAN_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1, + pstcCanInit->stcBitCfg.u32TimeSeg2, + pstcCanInit->stcBitCfg.u32SJW)); + } +} +#endif + +/** + * @brief Specifies work mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8WorkMode Work mode of CAN. + * This parameter can be a value of @ref CAN_Work_Mode + * @arg CAN_WORK_MD_NORMAL: Normal work mode. + * @arg CAN_WORK_MD_SILENT: Silent work mode. Prohibit data transmission. + * @arg CAN_WORK_MD_ILB: Internal loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB: External loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB_SILENT: External lopp back silent mode, just for self-test while developing. + * It is forbidden to respond to received frames and error frames, + * but data can be transmitted. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +static void CAN_SetWorkMode(CM_CAN_TypeDef *CANx, uint8_t u8WorkMode) +{ + uint8_t u8CFGSTAT = 0U; + uint8_t u8TCMD = 0U; + + switch (u8WorkMode) { + case CAN_WORK_MD_SILENT: + u8TCMD = CAN_TCMD_LOM; + break; + case CAN_WORK_MD_ILB: + u8CFGSTAT = CAN_CFG_STAT_LBMI; + break; + case CAN_WORK_MD_ELB: + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_ELB_SILENT: + u8TCMD = CAN_TCMD_LOM; + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_NORMAL: + default: + break; + } + + MODIFY_REG8(CANx->CFG_STAT, CAN_CFG_STAT_LBMI | CAN_CFG_STAT_LBME, u8CFGSTAT); + MODIFY_REG8(CANx->TCMD, CAN_TCMD_LOM, u8TCMD); +} + +/** + * @brief Configures acceptance filter. Set ID and ID mask for the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] pstcFilter Pointer to a stc_can_filter_config_t structure type array which contains ID and ID mask + * values for the acceptance filters specified by parameter u16FilterSelect. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - u16FilterSelect == 0U. + * - pstcFilter == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +static int32_t CAN_FilterConfig(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, + const stc_can_filter_config_t *pstcFilter) +{ + uint8_t u8FilterAddr = 0U; + uint8_t i = 0U; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if ((u16FilterSelect != 0U) && (pstcFilter != NULL)) { + while (u16FilterSelect != 0U) { + if ((u16FilterSelect & 0x1U) != 0U) { + DDL_ASSERT(IS_CAN_ID_TYPE(pstcFilter[i].u32IDType)); + DDL_ASSERT(IS_CAN_ID_MASK(pstcFilter[i].u32IDMask)); + WRITE_REG8(CANx->ACFCTRL, u8FilterAddr); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32ID); + SET_REG8_BIT(CANx->ACFCTRL, CAN_ACFCTRL_SELMASK); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32IDMask | pstcFilter[i].u32IDType); + i++; + } + u16FilterSelect >>= 1U; + u8FilterAddr++; + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configures the specified CAN FD according to the specified parameters + * in a @ref stc_canfd_config_t structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanFd Pointer to a @ref stc_canfd_config_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanFd == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +static int32_t CAN_FD_Config(CM_CAN_TypeDef *CANx, const stc_canfd_config_t *pstcCanFd) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanFd != NULL) { + /* Specifies CAN FD ISO mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_FD_ISO, pstcCanFd->u8Mode); + /* + * Configures fast bit time. + * Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + * TQ = u32Prescaler / CANClock. + * Fast bit time = (u32TimeSeg1 + u32TimeSeg2) * TQ. + */ + WRITE_REG32(CANx->FBT, ((pstcCanFd->stcBitCfg.u32TimeSeg1 - 2U) | \ + ((pstcCanFd->stcBitCfg.u32TimeSeg2 - 1U) << CAN_FBT_F_SEG_2_POS) | \ + ((pstcCanFd->stcBitCfg.u32SJW - 1U) << CAN_FBT_F_SJW_POS) | \ + ((pstcCanFd->stcBitCfg.u32Prescaler - 1U) << CAN_FBT_F_PRESC_POS))); + + /* Specifies the secondary sample point. Number of TQ. + Enable or disable TDC. */ + WRITE_REG8(CANx->TDC, pstcCanFd->u8TDC | pstcCanFd->u8SSPOffset); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Write TX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval None + */ +static void CAN_WriteTxBuf(CM_CAN_TypeDef *CANx, const stc_can_tx_frame_t *pstcTx) +{ + uint8_t i; + uint8_t u8WordLen; + __IO uint32_t *reg32TBUF; + uint32_t *pu32TxData = (uint32_t *)((uint32_t)(&pstcTx->au8Data[0U])); + + reg32TBUF = (__IO uint32_t *)((uint32_t)&CANx->TBUF); + reg32TBUF[0U] = pstcTx->u32ID; + reg32TBUF[1U] = pstcTx->u32Ctrl; + + if (pstcTx->DLC != CAN_DLC0) { + u8WordLen = (m_au8DLC2Size[pstcTx->DLC] + 3U) / 4U; + for (i = 0U; i < u8WordLen; i++) { + reg32TBUF[2U + i] = pu32TxData[i]; + } + } +} + +/** + * @brief Read RX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval None + */ +static void CAN_ReadRxBuf(const CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + __I uint32_t *reg32RBUF; + uint8_t i; + uint8_t u8WordLen; + uint32_t *pu32RxData = (uint32_t *)((uint32_t)(&pstcRx->au8Data[0U])); + + reg32RBUF = (__I uint32_t *)((uint32_t)&CANx->RBUF); + pstcRx->u32ID = reg32RBUF[0U]; + pstcRx->u32Ctrl = reg32RBUF[1U]; + + u8WordLen = (m_au8DLC2Size[pstcRx->DLC] + 3U) / 4U; + for (i = 0U; i < u8WordLen; i++) { + pu32RxData[i] = reg32RBUF[2U + i]; + } +} + +/** + * @} + */ + +/** + * @defgroup CAN_Global_Functions CAN Global Functions + * @{ + */ + +/** + * @brief Initializes the specified CAN peripheral according to the specified parameters + * in the structure pstcCanInit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL + */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { +#if defined __DEBUG + CAN_InitParameterCheck(CANx, pstcCanInit); +#endif /* __DEBUG */ + + /* Software reset. */ + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Configures nominal bit time. */ + WRITE_REG32(CANx->SBT, ((pstcCanInit->stcBitCfg.u32TimeSeg1 - 2U) | \ + ((pstcCanInit->stcBitCfg.u32TimeSeg2 - 1U) << CAN_SBT_S_SEG_2_POS) | \ + ((pstcCanInit->stcBitCfg.u32SJW - 1U) << CAN_SBT_S_SJW_POS) | \ + ((pstcCanInit->stcBitCfg.u32Prescaler - 1U) << CAN_SBT_S_PRESC_POS))); + /* Enable or disable STB priority mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TSMODE, pstcCanInit->u8STBPrioMode); + /* Configures acceptance filters. */ + (void)CAN_FilterConfig(CANx, pstcCanInit->u16FilterSelect, pstcCanInit->pstcFilter); + + /* Configures CAN-FD */ + /* Configures CAN-FD if needed. */ + if (pstcCanInit->pstcCanFd != NULL) { + (void)CAN_FD_Config(CANx, pstcCanInit->pstcCanFd); + } + + /* CAN enters normal communication mode. */ + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Specifies CAN work mode. */ + CAN_SetWorkMode(CANx, pstcCanInit->u8WorkMode); + /* Enable or disable single shot transmission mode of PTB and STB. */ + MODIFY_REG8(CANx->CFG_STAT, \ + (CAN_CFG_STAT_TPSS | CAN_CFG_STAT_TSSS), \ + (pstcCanInit->u8PTBSingleShotTx | pstcCanInit->u8STBSingleShotTx)); + /* Specifies receive buffer almost full warning limit. Specifies error warning limit. */ + WRITE_REG8(CANx->LIMIT, ((pstcCanInit->u8RxWarnLimit << CAN_LIMIT_AFWL_POS) | pstcCanInit->u8ErrorWarnLimit)); + + /* Enable or disable RX all frames(include frames with error). + Specifies receive overflow mode. In case of a full rx buffer when a new message is received. + Enable or disable self-acknowledge. */ + WRITE_REG8(CANx->RCTRL, pstcCanInit->u8RxAllFrame | \ + pstcCanInit->u8RxOvfMode | \ + pstcCanInit->u8SelfAck); + /* Enable acceptance filters that configured before. */ + WRITE_REG16(CANx->ACFEN, pstcCanInit->u16FilterSelect); + /* Configures TTCAN if needed. */ + if (pstcCanInit->pstcCanTtc != NULL) { + (void)CAN_TTC_Config(CANx, pstcCanInit->pstcCanTtc); + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set each @ref stc_can_init_t field to a default value. + * Classical CAN bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 4. + * Bit rate 500Kbps, 1 bit time is 20TQs, sample point is 80%. + * CAN-FD bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, + * secondary sample point is 80%. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL. + */ +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { + /* + * Synchronization Segment(SS): Fixed as 1TQ + * Propagation Time Segment(PTS) and Phase Buffer Segment 1(PBS1): 15TQs + * Phase Buffer Segment 2(PBS2): 4TQs + * + * Field 'S_SEG_1' in register CAN_SBT contains SS, PTS and PBS1. + * Field 'S_SEG_2' in register CAN_SBT only contains PBS2. + * Sample point = (SS + PTS + PBS1) / (SS + PTS + PBS1 + PBS2) + * = (1 + 15) / (1 + 15 + 4) + * = 80%. + */ + pstcCanInit->stcBitCfg.u32Prescaler = 4U; + pstcCanInit->stcBitCfg.u32TimeSeg1 = 16U; + pstcCanInit->stcBitCfg.u32TimeSeg2 = 4U; + pstcCanInit->stcBitCfg.u32SJW = 2U; + pstcCanInit->pstcFilter = NULL; + pstcCanInit->u16FilterSelect = 0U; + pstcCanInit->u8WorkMode = CAN_WORK_MD_NORMAL; + pstcCanInit->u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBSingleShotTx = CAN_STB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBPrioMode = CAN_STB_PRIO_MD_DISABLE; + pstcCanInit->u8RxWarnLimit = CAN_RX_WARN_MAX; + pstcCanInit->u8ErrorWarnLimit = 7U; + pstcCanInit->u8RxAllFrame = CAN_RX_ALL_FRAME_DISABLE; + pstcCanInit->u8RxOvfMode = CAN_RX_OVF_DISCARD_NEW; + pstcCanInit->u8SelfAck = CAN_SELF_ACK_DISABLE; + pstcCanInit->pstcCanTtc = NULL; + pstcCanInit->pstcCanFd = NULL; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitializes the specified CAN peripheral registers to their default reset values. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval None + */ +void CAN_DeInit(CM_CAN_TypeDef *CANx) +{ + uint8_t i; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + for (i = 0U; i < 2U; i++) { + WRITE_REG8(CANx->CFG_STAT, 0x80U); + WRITE_REG8(CANx->TCMD, 0x00U); + WRITE_REG8(CANx->TCTRL, 0x90U); + WRITE_REG8(CANx->RCTRL, 0x10U); + WRITE_REG8(CANx->RTIE, 0xFEU); + WRITE_REG8(CANx->RTIF, 0xFFU); + WRITE_REG8(CANx->ERRINT, 0xD5U); + WRITE_REG8(CANx->LIMIT, 0x1BU); + WRITE_REG32(CANx->SBT, 0x01020203UL); + WRITE_REG8(CANx->RECNT, 0x00U); + WRITE_REG8(CANx->TECNT, 0x00U); + WRITE_REG8(CANx->ACFCTRL, 0x00U); + WRITE_REG8(CANx->TBSLOT, 0x00U); + WRITE_REG8(CANx->TTCFG, 0xD8U); + WRITE_REG16(CANx->TRG_CFG, 0x00U); + WRITE_REG16(CANx->TT_TRIG, 0x00U); + WRITE_REG16(CANx->TT_WTRIG, 0x00U); + WRITE_REG16(CANx->ACFEN, 0x01U); + WRITE_REG32(CANx->FBT, 0x01020203UL); + WRITE_REG8(CANx->TDC, 0x00U); + + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + } +} + +/** + * @brief Enable or disable specified interrupts. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32IntType Interrupt of CAN. + * This parameter can be values of @ref CAN_Interrupt_Type + * @arg CAN_INT_ERR_INT: Register bit RTIE.EIE. Error interrupt. + * @arg CAN_INT_STB_TX: Register bit RTIE.TSIE. STB was transmitted successfully. + * @arg CAN_INT_PTB_TX: Register bit RTIE.TPIE. PTB was transmitted successfully. + * @arg CAN_INT_RX_BUF_WARN: Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_INT_RX_BUF_FULL: Register bit RTIE.RFIE. The FIFO of receive buffer is full. + * @arg CAN_INT_RX_OVERRUN: Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. + * @arg CAN_INT_RX: Register bit RTIE.RIE. Received a valid data frame or remote frame. + * @arg CAN_INT_BUS_ERR: Register bit ERRINT.BEIE. Arbitration lost caused bus error + * @arg CAN_INT_ARBITR_LOST: Register bit ERRINT.ALIE. Arbitration lost. + * @arg CAN_INT_ERR_PASSIVE: Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint8_t u8RTIE; + uint8_t u8ERRINT; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8RTIE = (uint8_t)u32IntType; + u8ERRINT = (uint8_t)(u32IntType >> 8U); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->RTIE, u8RTIE); + SET_REG8_BIT(CANx->ERRINT, u8ERRINT); + } else { + CLR_REG8_BIT(CANx->RTIE, u8RTIE); + CLR_REG8_BIT(CANx->ERRINT, u8ERRINT); + } +} + +/** + * @brief Fills transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType CAN transmit buffer type. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @arg CAN_TX_BUF_PTB: Primary transmit buffer. + * @arg CAN_TX_BUF_STB: Secondary transmit buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The specified transmit buffer is full. + * - LL_ERR_BUSY: The specified transmit buffer is being transmitted. + */ +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx) +{ + uint32_t u32RegAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + + if (pstcTx != NULL) { +#if defined __DEBUG + if (CANx == CM_CAN1) { + DDL_ASSERT(IS_CAN20_DLC(pstcTx->FDF, pstcTx->DLC)); + } else { + if (pstcTx->FDF == 1U) { + DDL_ASSERT((pstcTx->u32ID & 0x8UL) != 0x8UL); + } + } +#endif +#if defined __DEBUG + if (pstcTx->RTR == 1U) { + DDL_ASSERT(pstcTx->DLC != CAN_DLC0); + } +#endif + i32Ret = LL_OK; + + if (((pstcTx->FDF == 1U) && ((pstcTx->u32ID & 0x8UL) == 0x8UL)) || \ + ((pstcTx->RTR == 1U) && (pstcTx->DLC == CAN_DLC0))) { + i32Ret = LL_ERR_INVD_PARAM; + } + + if (i32Ret == LL_OK) { + if (u8TxBufType == CAN_TX_BUF_PTB) { + if (READ_REG8_BIT(CANx->TCMD, CAN_TCMD_TPE) != 0U) { + /* PTB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } + } else { + if (READ_REG8_BIT(CANx->TCMD, (CAN_TCMD_TSONE | CAN_TCMD_TSALL)) != 0U) { + /* STB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } else { + if (READ_REG8_BIT(CANx->RTIE, CAN_RTIE_TSFF) != 0U) { + /* All STBs are filled. */ + i32Ret = LL_ERR_BUF_FULL; + } + } + } + } + + if (i32Ret == LL_OK) { + /* Assert ID */ + DDL_ASSERT(IS_CAN_ID(pstcTx->IDE, pstcTx->u32ID)); + + /* Specifies the transmit buffer, PTB or STB. */ + u32RegAddr = (uint32_t)&CANx->TCMD; + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, CAN_TCMD_TBSEL_POS), u8TxBufType); + + CAN_WriteTxBuf(CANx, pstcTx); + + if (u8TxBufType == CAN_TX_BUF_STB) { + /* After writes the data in transmit buffer(TB), sets the TSNEXT bit to indicate that the current + STB slot has been filled, so that the hardware will point TB to the next STB slot. */ + SET_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSNEXT); + } + } + } + + return i32Ret; +} + +/** + * @brief Starts transmission. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxRequest The transmit buffer to be transmitted. + * This parameter can be values of @ref CAN_Tx_Request + * @arg CAN_TX_REQ_STB_ONE: Transmit one STB frame. + * @arg CAN_TX_REQ_STB_ALL: Transmit all STB frames. + * @arg CAN_TX_REQ_PTB: Transmit PTB frame. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_REQ(u8TxRequest)); + SET_REG8_BIT(CANx->TCMD, u8TxRequest); +} + +/** + * @brief Abort the transmission of the specified transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType The transmit buffer to be aborted. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @arg CAN_TX_BUF_PTB: Abort PTB transmission. + * @arg CAN_TX_BUF_STB: Abort STB transmission. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType) +{ + uint8_t au8Abort[] = {CAN_TCMD_TPA, CAN_TCMD_TSA}; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + SET_REG8_BIT(CANx->TCMD, au8Abort[u8TxBufType]); +} + +/** + * @brief Get one received frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval int32_t: + * - LL_OK: Get one received frame successfully. + * - LL_ERR_BUF_EMPTY: Receive buffer is empty, and no frame has been read. + * - LL_ERR_INVD_PARAM: pstcRx == NULL. + */ +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + int32_t i32Ret = LL_ERR_BUF_EMPTY; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcRx == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT) != CAN_RX_BUF_EMPTY) { + CAN_ReadRxBuf(CANx, pstcRx); + /* Set RB to point to the next RB slot. */ + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get the status of specified flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be a value of @ref CAN_Status_Flag + * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * @arg CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * @arg CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8CFGSTAT; + uint8_t u8RCTRL; + uint8_t u8RTIE; + uint8_t u8RTIF; + uint8_t u8ERRINT; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u8CFGSTAT = (uint8_t)(u32Flag); + u8RCTRL = (uint8_t)(u32Flag & CAN_FLAG_RX_BUF_OVF); + u8RTIE = (uint8_t)(u32Flag >> 8U); + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + u8CFGSTAT = READ_REG8_BIT(CANx->CFG_STAT, u8CFGSTAT); + u8RCTRL = READ_REG8_BIT(CANx->RCTRL, u8RCTRL); + u8RTIE = READ_REG8_BIT(CANx->RTIE, u8RTIE); + u8RTIF = READ_REG8_BIT(CANx->RTIF, u8RTIF); + u8ERRINT = READ_REG8_BIT(CANx->ERRINT, u8ERRINT); + + if ((u8CFGSTAT != 0U) || (u8RCTRL != 0U) || \ + (u8RTIE != 0U) || (u8RTIF != 0U) || (u8ERRINT != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of specified flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be values of @ref CAN_Status_Flag + * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter + * and the set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval None + */ +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8RTIF; + uint8_t u8ERRINT; + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u32Flag &= CAN_FLAG_CLR_ALL; + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + if ((u32Flag & CAN_FLAG_RX_BUF_OVF) != 0U) { + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + } + + WRITE_REG8(CANx->RTIF, u8RTIF); + + u8Reg = READ_REG8(CANx->ERRINT); + u8Reg &= (uint8_t)(~CAN_ERRINT_FLAG_MASK); + u8Reg |= u8ERRINT; + WRITE_REG8(CANx->ERRINT, u8Reg); +} + +/** + * @brief Get the value of CAN status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint32_t type value that includes the flowing status flags. + * - CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * - CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * - CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * - CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * - CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * - CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * - CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * - CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * - CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * - CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * - CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * - CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * - CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * - CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * - CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * - CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * - CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * - CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + */ +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + uint32_t u32RCTRL; + uint32_t u32RTIE; + uint32_t u32RTIF; + uint32_t u32ERRINT; + uint32_t u32RetVal; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32RetVal = CANx->CFG_STAT; + u32RCTRL = CANx->RCTRL; + u32RCTRL &= CAN_FLAG_RX_BUF_OVF; + u32RTIE = CANx->RTIE; + u32RTIF = CANx->RTIF; + u32ERRINT = CANx->ERRINT; + + u32RetVal |= (u32RCTRL | (u32RTIE << 8U) | (u32RTIF << 16U) | (u32ERRINT << 24U)); + u32RetVal &= CAN_FLAG_ALL; + + return u32RetVal; +} + +/** + * @brief Get the information of CAN errors. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcErr Pointer to a @ref stc_can_error_info_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcErr == NULL. + */ +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcErr != NULL) { + pstcErr->u8ArbitrLostPos = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_ALC); + pstcErr->u8ErrorType = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_KOER) >> CAN_EALCAP_KOER_POS; + pstcErr->u8RxErrorCount = READ_REG8(CANx->RECNT); + pstcErr->u8TxErrorCount = READ_REG8(CANx->TECNT); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get status(full or empty) of transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of transmit buffer. It can be a value of @ref CAN_Tx_Buf_Status + * - CAN_TX_BUF_EMPTY: TTCAN is disabled(TTEN == 0): STB is empty. + * TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + * PTB and STB are both empty. + * - CAN_TX_BUF_NOT_MORE_THAN_HALF: TTEN == 0: STB is not less than half full; + * TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. + * - CAN_TX_BUF_MORE_THAN_HALF: TTEN == 0: STB is more than half full; + * TTEN == 1 && TTTBM == 1: reserved value. + * - CAN_TX_BUF_FULL: TTEN == 0: STB is full; + * TTEN == 1 && TTTBM == 1: PTB and STB are both full. + */ +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSSTAT)); +} + +/** + * @brief Get status(full or empty) of receive buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of receive buffer. It can be a value of @ref CAN_Rx_Buf_Status + * - CAN_RX_BUF_EMPTY: Receive buffer is empty. + * - CAN_RX_BUF_NOT_WARN: Receive buffer is not empty, but is less than almost full warning limit. + * - CAN_RX_BUF_WARN: Receive buffer is not full, but is more than or equal to almost full warning limit. + * - CAN_RX_BUF_FULL: Receive buffer is full. + */ +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT)); +} + +/** + * @brief Enable or disable the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FILTER(u16FilterSelect)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(CANx->ACFEN, u16FilterSelect); + } else { + CLR_REG16_BIT(CANx->ACFEN, u16FilterSelect); + } +} + +/** + * @brief Set receive buffer full warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8RxWarnLimit: Receive buffer full warning limit. + * When the number of received frames reaches the value specified by + * parameter 'u8RxWarnLimit', register bit RTIF.RAFIF set and the + * interrupt occurred if it was enabled. + * @retval None + */ +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RX_WARN(u8RxWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_AFWL, u8RxWarnLimit << CAN_LIMIT_AFWL_POS); +} + +/** + * @brief Set error warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8ErrorWarnLimit Programmable error warning limit. Range is [0, 15]. + * Error warning limit = (u8ErrorWarnLimit + 1) * 8. + * @retval None + */ +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_ERR_WARN(u8ErrorWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_EWL, u8ErrorWarnLimit); +} + +/** + * @brief Set each @ref stc_canfd_config_t field to a default value. + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, + * secondary sample point is 80%. + * @param [in] pstcCanFd Pointer to a @ref stc_canfd_config_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanFd == NULL. + * @note 1. CAN-FD is only available on these part numbers: HC32F4A0TIHB, HC32F4A0SITB, HC32F4A0SGTB. + * @note 2. CAN2 supports CAN-FD. + */ +int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd) +{ + /* + * u8TDC: Enable(CAN_FD_TDC_ENABLE) or disable(CAN_FD_TDC_DISABLE) transmitter delay compensation. + * u8SSPOffset: The position(TQs) of secondary sample point. + * + * Primary sample point: u32TimeSeg1 / (u32TimeSeg1 + u32TimeSeg2) = 80% + * Secondary sample point: u8SSPOffset / (u32TimeSeg1 + u32TimeSeg2) = 80% + * + * u32TimeSeg1: TQs of segment 1. Contains synchronization segment, + * propagation time segment and phase buffer segment 1. + * u32TimeSeg2: TQs of segment 2(Phase buffer segment 2). + * u32SJW: TQs of synchronization jump width. + * u32Prescaler: Range [1, 256]. + */ + + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanFd != NULL) { + pstcCanFd->stcBitCfg.u32Prescaler = 1U; + pstcCanFd->stcBitCfg.u32TimeSeg1 = 16U; + pstcCanFd->stcBitCfg.u32TimeSeg2 = 4U; + pstcCanFd->stcBitCfg.u32SJW = 4U; + pstcCanFd->u8Mode = CAN_FD_MD_ISO; + pstcCanFd->u8TDC = CAN_FD_TDC_ENABLE; + pstcCanFd->u8SSPOffset = 16U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set each @ref stc_can_ttc_config_t field to a default value. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + pstcCanTtc->u8NTUPrescaler = CAN_TTC_NTU_PRESCALER1; + pstcCanTtc->u32RefMsgID = 0x0UL; + pstcCanTtc->u32RefMsgIDE = 0U; + pstcCanTtc->u8TxBufMode = CAN_TTC_TX_BUF_MD_TTCAN; + pstcCanTtc->u16TriggerType = CAN_TTC_TRIG_SINGLESHOT_TX_TRIG; + pstcCanTtc->u16TxEnableWindow = 16U; + pstcCanTtc->u16TxTriggerTime = 0xFFFFU; + pstcCanTtc->u16WatchTriggerTime = 0xFFFFU; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configures the specified TTCAN according to the specified parameters + * in @ref stc_can_ttc_config_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32RefMsgID; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcCanTtc != NULL) { + DDL_ASSERT(IS_TTCAN_TX_BUF_MD(pstcCanTtc->u8TxBufMode)); + DDL_ASSERT(IS_TTCAN_NTU_PRESCALER(pstcCanTtc->u8NTUPrescaler)); + DDL_ASSERT(IS_CAN_ID(pstcCanTtc->u32RefMsgIDE, pstcCanTtc->u32RefMsgID)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(pstcCanTtc->u16TriggerType)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(pstcCanTtc->u16TxEnableWindow)); + + u32RefMsgID = pstcCanTtc->u32RefMsgID & ((uint32_t)(~CAN_REF_MSG_REF_IDE)); + /* Specifies transmission buffer mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TTTBM, pstcCanTtc->u8TxBufMode); + /* Specifies Tx_Enable window and trigger type. */ + WRITE_REG16(CANx->TRG_CFG, pstcCanTtc->u16TriggerType | + ((pstcCanTtc->u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS)); + /* Specifies ID of reference message and its extension bit. */ + WRITE_REG32(CANx->REF_MSG, (((pstcCanTtc->u32RefMsgIDE << CAN_REF_MSG_REF_IDE_POS) | u32RefMsgID))); + /* Specifies transmission trigger time. */ + WRITE_REG16(CANx->TT_TRIG, pstcCanTtc->u16TxTriggerTime); + /* Specifies watch trigger time. */ + WRITE_REG16(CANx->TT_WTRIG, pstcCanTtc->u16WatchTriggerTime); + /* Specifies NTU prescaler. */ + MODIFY_REG8(CANx->TTCFG, CAN_TTCFG_T_PRESC, pstcCanTtc->u8NTUPrescaler); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified interrupts of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8IntType Interrupt of TTCAN. + * This parameter can be values of @ref TTCAN_Interrupt_Type + * @arg CAN_TTC_INT_TIME_TRIG: Time trigger interrupt. + * @arg CAN_TTC_INT_WATCH_TRIG: Watch trigger interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->TTCFG, u8IntType); + } else { + CLR_REG8_BIT(CANx->TTCFG, u8IntType); + } +} + +/** + * @brief Enable or disable TTCAN of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&CANx->TTCFG; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, CAN_TTCFG_TTEN_POS), enNewState); +} + +/** + * @brief Get status of the sepcified TTCAN flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be values of @ref TTCAN_Status_Flag + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + if (READ_REG8_BIT(CANx->TTCFG, (u8Flag & CAN_TTC_FLAG_ALL)) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of TTCAN flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be a value of @ref TTCAN_Status_Flag except CAN_TTC_FLAG_TRIG_ERR. + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval None + */ +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + u8Reg = READ_REG8(CANx->TTCFG); + u8Reg &= (uint8_t)(~CAN_TTC_FLAG_ALL); + u8Reg |= u8Flag; + WRITE_REG8(CANx->TTCFG, u8Reg); +} + +/** + * @brief Get the status value of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value that includes the flowing status flags. + * - CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * - CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * - CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + */ +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return READ_REG8_BIT(CANx->TTCFG, CAN_TTC_FLAG_ALL); +} + +/** + * @brief Specifies trigger type of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TriggerType TTCAN trigger type. + * This parameter can be a value of @ref TTCAN_Trigger_Type + * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission. + * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers. + * @arg CAN_TTC_TRIG_SINGLESHOT_TX_TRIG: Single shot transmit trigger for exclusive time windows. + * @arg CAN_TTC_TRIG_TX_START_TRIG: Transmit start trigger for merged arbitrating time windows. + * @arg CAN_TTC_TRIG_TX_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows. + * @retval None + */ +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(u16TriggerType)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE, u16TriggerType); +} + +/** + * @brief Specifies transmit enable window time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxEnableWindow Number of NTU. Time period within which the transmit of a message may be started. + * @retval None + */ +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(u16TxEnableWindow)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TEW, (u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS); +} + +/** + * @brief Specifies transmit trigger time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxTriggerTime Transmit trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_TRIG, u16TxTriggerTime); +} + +/** + * @brief TTCAN specifies watch-trigger time. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16WatchTriggerTime Watch trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_WTRIG, u16WatchTriggerTime); +} + +/** + * @brief TTCAN fill transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8CANTTCTxBuf TTCAN transmit buffer selection. + * This parameter can be a value of @ref TTCAN_Tx_Buf_Sel + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The target transmit buffer is full. + */ +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_BUF_SEL(u8CANTTCTxBuf)); + + if (pstcTx != NULL) { + DDL_ASSERT(IS_CAN20_DLC(pstcTx->FDF, pstcTx->DLC)); + + if (READ_REG8_BIT(CANx->TCTRL, CAN_TX_BUF_FULL) == CAN_TX_BUF_FULL) { + i32Ret = LL_ERR_BUF_FULL; + } else { + WRITE_REG8(CANx->TBSLOT, u8CANTTCTxBuf); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8CANTTCTxBuf); + CAN_WriteTxBuf(CANx, pstcTx); + + /* Set buffer as filled. */ + SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF); + + /* Write MSB of TT_TRIG to transmit. */ + WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get the configuration of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + u32Tmp = READ_REG32(CANx->REF_MSG); + pstcCanTtc->u8TxBufMode = READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TTTBM); + pstcCanTtc->u8NTUPrescaler = READ_REG8_BIT(CANx->TTCFG, CAN_TTCFG_T_PRESC); + pstcCanTtc->u32RefMsgIDE = (u32Tmp >> CAN_REF_MSG_REF_IDE_POS) & 0x1UL; + pstcCanTtc->u32RefMsgID = u32Tmp & 0x7FFFFFFFUL; + pstcCanTtc->u16TriggerType = READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE); + pstcCanTtc->u16TxEnableWindow = (READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TEW) >> CAN_TRG_CFG_TEW_POS) + 1U; + pstcCanTtc->u16TxTriggerTime = READ_REG16(CANx->TT_TRIG); + pstcCanTtc->u16WatchTriggerTime = READ_REG16(CANx->TT_WTRIG); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c new file mode 100644 index 0000000000..be9e0770a1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c @@ -0,0 +1,1776 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.c + * @brief This file provides firmware functions to manage the Clock(CLK). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_clk.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CLK CLK + * @brief Clock Driver Library + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Macros CLK Local Macros + * @{ + */ + +/** + * @brief CLK_FREQ Clock frequency definition + */ +#define CLK_FREQ_48M (48UL*1000UL*1000UL) +#define CLK_FREQ_64M (64UL*1000UL*1000UL) +#define CLK_FREQ_32M (32UL*1000UL*1000UL) + +/** + * @brief Be able to modify TIMEOUT according to board condition. + */ +#define CLK_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_LRC_TIMEOUT ((uint32_t)0x200U) + +#define CLK_MRC_TIMEOUT ((uint32_t)0x200U) +#define CLK_XTAL32_TIMEOUT ((uint32_t)0x200U) + +/** + * @brief LRC State ON or OFF + */ +#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP) +#define CLK_LRC_ON (0x00U) + +/** + * @brief MRC State ON or OFF + */ +#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP) +#define CLK_MRC_ON (0x80U) + +/** + * @brief Clk PLL Relevant Parameter Range Definition + */ +#define CLK_PLLP_DEFAULT (0x01UL) +#define CLK_PLLQ_DEFAULT (0x01UL) +#define CLK_PLLR_DEFAULT (0x01UL) +#define CLK_PLLN_DEFAULT (0x13UL) +#define CLK_PLLM_DEFAULT (0x00UL) + +#define CLK_PLLR_DIV_MIN (2UL) +#define CLK_PLLR_DIV_MAX (16UL) +#define CLK_PLLQ_DIV_MIN (2UL) +#define CLK_PLLQ_DIV_MAX (16UL) +#define CLK_PLLP_DIV_MIN (2UL) +#define CLK_PLLP_DIV_MAX (16UL) + +#define CLK_PLLX_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MAX (480UL*1000UL*1000UL) +#define CLK_PLLXM_DIV_MIN (2UL) +#define CLK_PLLXM_DIV_MAX (24UL) +#define CLK_PLLXN_MULTI_MIN (20UL) +#define CLK_PLLXN_MULTI_MAX (480UL) +#define CLK_PLLXR_DIV_MIN (2UL) +#define CLK_PLLXR_DIV_MAX (16UL) +#define CLK_PLLXQ_DIV_MIN (2UL) +#define CLK_PLLXQ_DIV_MAX (16UL) +#define CLK_PLLXP_DIV_MIN (2UL) +#define CLK_PLLXP_DIV_MAX (16UL) +#define CLK_PLLXP_DEFAULT (0x01UL) +#define CLK_PLLXQ_DEFAULT (0x01UL) +#define CLK_PLLXR_DEFAULT (0x01UL) +#define CLK_PLLXN_DEFAULT (0x13UL) +#define CLK_PLLXM_DEFAULT (0x00UL) + +#define CLK_PLLX_FREQ_MAX (240UL*1000UL*1000UL) +#define CLK_PLL_FREQ_MIN (375UL*100UL*1000UL) +#define CLK_PLL_FREQ_MAX (240UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MIN (8UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MIN (600UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MAX (1200UL*1000UL*1000UL) +#define CLK_PLLM_DIV_MIN (1UL) +#define CLK_PLLM_DIV_MAX (4UL) +#define CLK_PLLN_MULTI_MIN (25UL) +#define CLK_PLLN_MULTI_MAX (150UL) + +/** + * @brief Clk PLL Register Redefinition + */ +#define PLL_SRC_REG (CM_CMU->PLLHCFGR) +#define PLL_SRC_BIT (CMU_PLLHCFGR_PLLSRC) +#define PLL_SRC_POS (CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_EN_REG (CM_CMU->PLLHCR) +#define PLLX_EN_REG (CM_CMU->PLLACR) + +/** + * @brief Switch clock stable time + * @note Approx. 30us + */ +#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL) + +/** + * @brief Clk FCG Default Value + */ +#define CLK_FCG0_DEFAULT (0xFFFFFA0EUL) +#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL) + +/** + * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) + +/* Parameter valid check for XTAL state */ +#define IS_CLK_XTAL_STATE(x) \ +( ((x) == CLK_XTAL_OFF) || \ + ((x) == CLK_XTAL_ON)) + +/* Parameter valid check for XTAL mode */ +#define IS_CLK_XTAL_MD(x) \ +( ((x) == CLK_XTAL_MD_OSC) || \ + ((x) == CLK_XTAL_MD_EXCLK)) + +/* Parameter valid check for XTAL driver ability mode */ +#define IS_CLK_XTAL_DRV_MD(x) \ +( ((x) == CLK_XTAL_DRV_HIGH) || \ + ((x) == CLK_XTAL_DRV_MID) || \ + ((x) == CLK_XTAL_DRV_LOW) || \ + ((x) == CLK_XTAL_DRV_ULOW)) + +/* Parameter valid check for XTAL stable time selection */ +#define IS_CLK_XTAL_STB_SEL(x) \ +( ((x) == CLK_XTAL_STB_133US) || \ + ((x) == CLK_XTAL_STB_255US) || \ + ((x) == CLK_XTAL_STB_499US) || \ + ((x) == CLK_XTAL_STB_988US) || \ + ((x) == CLK_XTAL_STB_2MS) || \ + ((x) == CLK_XTAL_STB_4MS) || \ + ((x) == CLK_XTAL_STB_8MS) || \ + ((x) == CLK_XTAL_STB_16MS) || \ + ((x) == CLK_XTAL_STB_31MS)) + +/* Parameter valid check for XTALSTD state */ +#define IS_CLK_XTALSTD_STATE(x) \ +( ((x) == CLK_XTALSTD_OFF) || \ + ((x) == CLK_XTALSTD_ON)) + +/* Parameter valid check for XTALSTD mode */ +#define IS_CLK_XTALSTD_MD(x) \ +( ((x) == CLK_XTALSTD_MD_RST) || \ + ((x) == CLK_XTALSTD_MD_INT)) + +/* Parameter valid check for XTALSTD interrupt state */ +#define IS_CLK_XTALSTD_INT_STATE(x) \ +( ((x) == CLK_XTALSTD_INT_OFF) || \ + ((x) == CLK_XTALSTD_INT_ON)) + +/* Parameter valid check for XTALSTD reset state */ +#define IS_CLK_XTALSTD_RST_STATE(x) \ +( ((x) == CLK_XTALSTD_RST_OFF) || \ + ((x) == CLK_XTALSTD_RST_ON)) + +/* Parameter valid check for PLL state */ +#define IS_CLK_PLL_STATE(x) \ +( ((x) == CLK_PLL_OFF) || \ + ((x) == CLK_PLL_ON)) + +/* Parameter validity check for PLL input source */ +#define IS_CLK_PLL_SRC(x) \ +( ((x) == CLK_PLL_SRC_XTAL) || \ + ((x) == CLK_PLL_SRC_HRC)) + +/* Parameter validity check for PLL frequency range */ +#define IS_CLK_PLL_FREQ(x) \ +( ((x) <= CLK_PLL_FREQ_MAX) && \ + ((x) >= CLK_PLL_FREQ_MIN)) + +/* Parameter validity check for PLL M divide */ +#define IS_CLK_PLLM_DIV(x) \ +( ((x) <= CLK_PLLM_DIV_MAX) && \ + ((x) >= CLK_PLLM_DIV_MIN)) + +/* Parameter validity check for PLL N multi- */ +#define IS_CLK_PLLN_MULTI(x) \ +( ((x) <= CLK_PLLN_MULTI_MAX) && \ + ((x) >= CLK_PLLN_MULTI_MIN)) + +/* Parameter validity check for PLL P divide */ +#define IS_CLK_PLLP_DIV(x) \ +( ((x) <= CLK_PLLP_DIV_MAX) && \ + ((x) >= CLK_PLLP_DIV_MIN)) + +/* Parameter validity check for PLL_input freq./PLLM(vco_in) */ +#define IS_CLK_PLL_VCO_IN(x) \ +( ((x) <= CLK_PLL_VCO_IN_MAX) && \ + ((x) >= CLK_PLL_VCO_IN_MIN)) + +/* Parameter validity check for PLL vco_in*PLLN(vco_out) */ +#define IS_CLK_PLL_VCO_OUT(x) \ +( ((x) <= CLK_PLL_VCO_OUT_MAX) && \ + ((x) >= CLK_PLL_VCO_OUT_MIN)) + +/* Parameter validity check for PLL R divide */ +#define IS_CLK_PLLR_DIV(x) \ +( ((x) <= CLK_PLLR_DIV_MAX) && \ + ((x) >= CLK_PLLR_DIV_MIN)) + +/* Parameter validity check for PLL Q divede */ +#define IS_CLK_PLLQ_DIV(x) \ +( ((x) <= CLK_PLLQ_DIV_MAX) && \ + ((x) >= CLK_PLLQ_DIV_MIN)) + +/* Parameter valid check for PLLX state */ +#define IS_CLK_PLLX_STATE(x) \ +( ((x) == CLK_PLLX_OFF) || \ + ((x) == CLK_PLLX_ON)) + +/* Parameter validity check for PLLX frequency range */ +#define IS_CLK_PLLX_FREQ(x) \ +( (CLK_PLLX_FREQ_MIN <= (x)) && \ + (CLK_PLLX_FREQ_MAX >= (x))) + +/* Parameter validity check for PLLX M divide */ +#define IS_CLK_PLLXM_DIV(x) \ +( (CLK_PLLXM_DIV_MIN <= (x)) && \ + (CLK_PLLXM_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX N multi- */ +#define IS_CLK_PLLXN_MULTI(x) \ +( (CLK_PLLXN_MULTI_MIN <= (x)) && \ + (CLK_PLLXN_MULTI_MAX >= (x))) + +/* Parameter validity check for PLLX R divide */ +#define IS_CLK_PLLXR_DIV(x) \ +( (CLK_PLLXR_DIV_MIN <= (x)) && \ + (CLK_PLLXR_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX Q divede */ +#define IS_CLK_PLLXQ_DIV(x) \ +( (CLK_PLLXQ_DIV_MIN <= (x)) && \ + (CLK_PLLXQ_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX P divide */ +#define IS_CLK_PLLXP_DIV(x) \ +( (CLK_PLLXP_DIV_MIN <= (x)) && \ + (CLK_PLLXP_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX_input freq./PLLM(vco_in) */ +#define IS_CLK_PLLX_VCO_IN(x) \ +( (CLK_PLLX_VCO_IN_MIN <= (x)) && \ + (CLK_PLLX_VCO_IN_MAX >= (x))) + +/* Parameter validity check for PLLX vco_in*PLLN(vco_out) */ +#define IS_CLK_PLLX_VCO_OUT(x) \ +( (CLK_PLLX_VCO_OUT_MIN <= (x)) && \ + (CLK_PLLX_VCO_OUT_MAX >= (x))) + +/* Parameter valid check for XTAL32 state */ +#define IS_CLK_XTAL32_STATE(x) \ +( ((x) == CLK_XTAL32_OFF) || \ + ((x) == CLK_XTAL32_ON)) + +/* Parameter valid check for XTAL32 driver ability mode */ +#define IS_CLK_XTAL32_DRV_MD(x) \ +( ((x) == CLK_XTAL32_DRV_MID) || \ + ((x) == CLK_XTAL32_DRV_HIGH)) + +/* Parameter valid check for XTAL32 filtering selection */ +#define IS_CLK_XTAL32_FILT_SEL(x) \ +( ((x) == CLK_XTAL32_FILTER_ALL_MD) || \ + ((x) == CLK_XTAL32_FILTER_RUN_MD) || \ + ((x) == CLK_XTAL32_FILTER_OFF)) + +/* Parameter valid check for system clock source */ +#define IS_CLK_SYSCLK_SRC(x) \ +( ((x) == CLK_SYSCLK_SRC_HRC) || \ + ((x) == CLK_SYSCLK_SRC_MRC) || \ + ((x) == CLK_SYSCLK_SRC_LRC) || \ + ((x) == CLK_SYSCLK_SRC_XTAL) || \ + ((x) == CLK_SYSCLK_SRC_XTAL32) || \ + ((x) == CLK_SYSCLK_SRC_PLL)) + +/* Parameter valid check for CLK stable flag. */ +#define IS_CLK_STB_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK)) + +/* Parameter valid check for bus clock category */ +#define IS_CLK_BUS_CLK_CATE(x) (((x) & CLK_BUS_CLK_ALL) != (0x00U)) + +/* Parameter valid check for HCLK divider */ +#define IS_CLK_HCLK_DIV(x) \ +( ((x) == CLK_HCLK_DIV1) || \ + ((x) == CLK_HCLK_DIV2) || \ + ((x) == CLK_HCLK_DIV4) || \ + ((x) == CLK_HCLK_DIV8) || \ + ((x) == CLK_HCLK_DIV16) || \ + ((x) == CLK_HCLK_DIV32) || \ + ((x) == CLK_HCLK_DIV64)) + +/* Parameter valid check for PCLK1 divider */ +#define IS_CLK_PCLK1_DIV(x) \ +( ((x) == CLK_PCLK1_DIV1) || \ + ((x) == CLK_PCLK1_DIV2) || \ + ((x) == CLK_PCLK1_DIV4) || \ + ((x) == CLK_PCLK1_DIV8) || \ + ((x) == CLK_PCLK1_DIV16) || \ + ((x) == CLK_PCLK1_DIV32) || \ + ((x) == CLK_PCLK1_DIV64)) + +/* Parameter valid check for PCLK4 divider */ +#define IS_CLK_PCLK4_DIV(x) \ +( ((x) == CLK_PCLK4_DIV1) || \ + ((x) == CLK_PCLK4_DIV2) || \ + ((x) == CLK_PCLK4_DIV4) || \ + ((x) == CLK_PCLK4_DIV8) || \ + ((x) == CLK_PCLK4_DIV16) || \ + ((x) == CLK_PCLK4_DIV32) || \ + ((x) == CLK_PCLK4_DIV64)) + +/* Parameter valid check for PCLK3 divider */ +#define IS_CLK_PCLK3_DIV(x) \ +( ((x) == CLK_PCLK3_DIV1) || \ + ((x) == CLK_PCLK3_DIV2) || \ + ((x) == CLK_PCLK3_DIV4) || \ + ((x) == CLK_PCLK3_DIV8) || \ + ((x) == CLK_PCLK3_DIV16) || \ + ((x) == CLK_PCLK3_DIV32) || \ + ((x) == CLK_PCLK3_DIV64)) + +/* Parameter valid check for EXCLK divider */ +#define IS_CLK_EXCLK_DIV(x) \ +( ((x) == CLK_EXCLK_DIV1) || \ + ((x) == CLK_EXCLK_DIV2) || \ + ((x) == CLK_EXCLK_DIV4) || \ + ((x) == CLK_EXCLK_DIV8) || \ + ((x) == CLK_EXCLK_DIV16) || \ + ((x) == CLK_EXCLK_DIV32) || \ + ((x) == CLK_EXCLK_DIV64)) + +/* Parameter valid check for PCLK0 divider */ +#define IS_CLK_PCLK0_DIV(x) \ +( ((x) == CLK_PCLK0_DIV1) || \ + ((x) == CLK_PCLK0_DIV2) || \ + ((x) == CLK_PCLK0_DIV4) || \ + ((x) == CLK_PCLK0_DIV8) || \ + ((x) == CLK_PCLK0_DIV16) || \ + ((x) == CLK_PCLK0_DIV32) || \ + ((x) == CLK_PCLK0_DIV64)) + +/* Parameter valid check for PCLK2 divider */ +#define IS_CLK_PCLK2_DIV(x) \ +( ((x) == CLK_PCLK2_DIV1) || \ + ((x) == CLK_PCLK2_DIV2) || \ + ((x) == CLK_PCLK2_DIV4) || \ + ((x) == CLK_PCLK2_DIV8) || \ + ((x) == CLK_PCLK2_DIV16) || \ + ((x) == CLK_PCLK2_DIV32) || \ + ((x) == CLK_PCLK2_DIV64)) + +/* Parameter valid check for bus clock */ +#define IS_CLK_BUS_CLK(x) \ +( ((x) == CLK_BUS_HCLK) || \ + ((x) == CLK_BUS_EXCLK) || \ + ((x) == CLK_BUS_PCLK0) || \ + ((x) == CLK_BUS_PCLK1) || \ + ((x) == CLK_BUS_PCLK2) || \ + ((x) == CLK_BUS_PCLK3) || \ + ((x) == CLK_BUS_PCLK4)) + +/* Parameter valid check for USB clock source */ +#define IS_CLK_USBCLK_SRC(x) \ +( ((x) == CLK_USBCLK_SYSCLK_DIV2) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV3) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV4) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV5) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV6) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV7) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV8) || \ + ((x) == CLK_USBCLK_PLLQ) || \ + ((x) == CLK_USBCLK_PLLR) || \ + ((x) == CLK_USBCLK_PLLXP) || \ + ((x) == CLK_USBCLK_PLLXQ) || \ + ((x) == CLK_USBCLK_PLLXR)) + +/* Parameter valid check for CAN clock source */ +#define IS_CLK_CANCLK(x) \ +( ((x) == CLK_CANCLK_SYSCLK_DIV2) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV3) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV4) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV5) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV6) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV7) || \ + ((x) == CLK_CANCLK_SYSCLK_DIV8) || \ + ((x) == CLK_CANCLK_PLLQ) || \ + ((x) == CLK_CANCLK_PLLR) || \ + ((x) == CLK_CANCLK_PLLXP) || \ + ((x) == CLK_CANCLK_PLLXQ) || \ + ((x) == CLK_CANCLK_PLLXR) || \ + ((x) == CLK_CANCLK_XTAL )) + +/* Parameter valid check for CAN channel for clock source config */ +#define IS_CLK_CAN_UNIT(x) \ +( ((x) == CLK_CAN1) || \ + ((x) == CLK_CAN2)) + +/* Parameter valid check for I2S channel for clock source config */ +#define IS_CLK_I2S_UNIT(x) \ +( ((x) == CLK_I2S1) || \ + ((x) == CLK_I2S2) || \ + ((x) == CLK_I2S3) || \ + ((x) == CLK_I2S4)) + +/* Parameter valid check for peripheral source */ +#define IS_CLK_PERIPHCLK_SRC(x) \ +( ((x) == CLK_PERIPHCLK_PCLK) || \ + ((x) == CLK_PERIPHCLK_PLLQ) || \ + ((x) == CLK_PERIPHCLK_PLLR) || \ + ((x) == CLK_PERIPHCLK_PLLXP) || \ + ((x) == CLK_PERIPHCLK_PLLXQ) || \ + ((x) == CLK_PERIPHCLK_PLLXR)) + +/* Parameter valid check for TPIU clock divider */ +#define IS_CLK_TPIUCLK_DIV(x) \ +( ((x) == CLK_TPIUCLK_DIV1) || \ + ((x) == CLK_TPIUCLK_DIV2) || \ + ((x) == CLK_TPIUCLK_DIV4)) + +/* Parameter valid check for CLK MCO clock source . */ +#define IS_CLK_MCO_SRC(x) \ +( ((x) == CLK_MCO_SRC_HRC) || \ + ((x) == CLK_MCO_SRC_MRC) || \ + ((x) == CLK_MCO_SRC_LRC) || \ + ((x) == CLK_MCO_SRC_XTAL) || \ + ((x) == CLK_MCO_SRC_XTAL32) || \ + ((x) == CLK_MCO_SRC_PLLP) || \ + ((x) == CLK_MCO_SRC_PLLQ) || \ + ((x) == CLK_MCO_SRC_PLLXP) || \ + ((x) == CLK_MCO_SRC_PLLXQ) || \ + ((x) == CLK_MCO_SRC_PLLXR) || \ + ((x) == CLK_MCO_SRC_HCLK)) + +/* Parameter valid check for CLK MCO clock divide. */ +#define IS_CLK_MCO_DIV(x) \ +( ((x) == CLK_MCO_DIV1) || \ + ((x) == CLK_MCO_DIV2) || \ + ((x) == CLK_MCO_DIV4) || \ + ((x) == CLK_MCO_DIV8) || \ + ((x) == CLK_MCO_DIV16) || \ + ((x) == CLK_MCO_DIV32) || \ + ((x) == CLK_MCO_DIV64) || \ + ((x) == CLK_MCO_DIV128)) + +/* Parameter valid check for CLK MCO channel. */ +#define IS_CLK_MCO_CH(x) \ +( ((x) == CLK_MCO1) || \ + ((x) == CLK_MCO2)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +/** + * @brief Clk delay function + * @param [in] u32Delay count + * @retval when switch clock srouce,shoud be delay some time to wait stable. + */ +static void CLK_Delay(uint32_t u32Delay) +{ + __IO uint32_t u32Timeout = 0UL; + + while (u32Timeout < u32Delay) { + u32Timeout++; + } +} + +/** + * @brief Wait clock stable flag. + * @param [in] u8Flag Specifies the stable flag to be wait. @ref CLK_STB_Flag + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t + */ +static int32_t CLK_WaitStable(uint8_t u8Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_ERR_TIMEOUT; + + while (u32Timeout <= u32Time) { + if (SET == CLK_GetStableStatus(u8Flag)) { + i32Ret = LL_OK; + break; + } + u32Timeout++; + } + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +#ifdef __DEBUG +/* + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The PLLx frequency (VCOOUT/PLLxP_Q_R) is between 15 ~ 240MHz. +*/ +static void PLLxParamCheck(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + uint32_t vcoIn; + uint32_t vcoOut; + + DDL_ASSERT(IS_CLK_PLLXM_DIV(pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLXN_MULTI(pstcPLLxInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLXR_DIV(pstcPLLxInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLLXQ_DIV(pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLXP_DIV(pstcPLLxInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLL_SRC_XTAL == PLL_SRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLxInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLLX_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLLX_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_STATE(pstcPLLxInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); +} +#endif /* __DEBUG */ + +static void SetSysClockSrc(uint8_t u8Src) +{ + uint8_t u8TmpFlag = 0U; + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW) || (CLK_SYSCLK_SRC_PLL == u8Src)) { + u8TmpFlag = 1U; + /* FCG0 protect judgment */ + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + + /* Wait stable after close FCGx. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } + + /* Set system clock source */ + WRITE_REG8(CM_CMU->CKSWR, u8Src); + + /* Wait stable after setting system clock source */ + CLK_Delay(CLK_SYSCLK_SW_STB); + + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } +} + +static void GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + stc_clock_scale_t *pstcClockScale; + uint32_t u32HrcValue; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + + switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + case CLK_SYSCLK_SRC_HRC: + /* HRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_MRC: + /* MRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = MRC_VALUE; + break; + case CLK_SYSCLK_SRC_LRC: + /* LRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = LRC_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL: + /* XTAL is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL32: + /* XTAL32 is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_PLL: + /* PLLHP is used as system clock. */ + pllp = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS); + plln = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS); + pllm = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS); + + /* fpll = ((pllin / pllm) * plln) / pllp */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pstcClockFreq->u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } else { + u32HrcValue = HRC_VALUE; + pstcClockFreq->u32SysclkFreq = ((u32HrcValue / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } + break; + default: + break; + } + + pstcClockScale = (stc_clock_scale_t *)((uint32_t)&CM_CMU->SCFGR); + pstcClockScale->SCFGR = READ_REG32(CM_CMU->SCFGR); + /* Get hclk. */ + pstcClockFreq->u32HclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.HCLKS; + /* Get pclk1. */ + pstcClockFreq->u32Pclk1Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK1S; + /* Get pclk4. */ + pstcClockFreq->u32Pclk4Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK4S; + /* Get pclk3. */ + pstcClockFreq->u32Pclk3Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK3S; + /* Get exck. */ + pstcClockFreq->u32ExclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.EXCKS; + /* Get pclk0. */ + pstcClockFreq->u32Pclk0Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK0S; + /* Get pclk2. */ + pstcClockFreq->u32Pclk2Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK2S; +} + +static void SetSysClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + uint8_t u8TmpFlag = 0U; + + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS)); + DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S)); + DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S)); + + DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS)); + DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S)); + DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S)); + DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S)); + + DDL_ASSERT(IS_CLK_BUS_CLK_CATE(u32Clock)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + u8TmpFlag = 1U; + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } + + MODIFY_REG32(CM_CMU->SCFGR, u32Clock, u32Div); + CLK_Delay(CLK_SYSCLK_SW_STB); + + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } +} + +/** +* @} +*/ + +/** + * @defgroup CLK_Global_Functions CLK Global Functions + * @{ + */ +/** + * @brief LRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: LRC operate successfully + * - LL_ERR_BUSY: LRC is the system clock, CANNOT stop it. + * @note DO NOT STOP LRC while using it as system clock. + */ +int32_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_LRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_ON); + + CLK_Delay(CLK_LRC_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief MRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: MRC operate successfully + * - LL_ERR_BUSY: MRC is the system clock, CANNOT stop it. + * @note DO NOT STOP MRC while using it as system clock. + */ +int32_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_MRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_ON); + + CLK_Delay(CLK_MRC_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief HRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: HRC operate successfully + * - LL_ERR_BUSY: HRC is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: HRC operate Timeout + * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock. + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_HRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_HRC == PLL_SRC) { + /* HRC as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Set HRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for HRC. + * @retval None + */ +void CLK_HrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->HRCTRM, i8TrimVal); +} + +/** + * @brief Set MRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for MRC. + * @retval None + */ +void CLK_MrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->MRCTRM, i8TrimVal); +} + +/** + * @brief Set LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for LRC. + * @retval None + */ +void CLK_LrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->LRCTRM, i8TrimVal); +} + +/** + * @brief Set RTC LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for RTC LRC. + * @retval None + */ +void CLK_RtcLrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->RTCLRCTRM, i8TrimVal); +} + +/** + * @brief Init Xtal initial structure with default value. + * @param [in] pstcXtalInit specifies the Parameter of XTAL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalInit->u8State = CLK_XTAL_OFF; + pstcXtalInit->u8Mode = CLK_XTAL_MD_OSC; + pstcXtalInit->u8Drv = CLK_XTAL_DRV_HIGH; + pstcXtalInit->u8StableTime = CLK_XTAL_STB_2MS; + } + return i32Ret; +} + +/** + * @brief XTAL initialize. + * @param [in] pstcXtalInit specifies the XTAL initial config. + * @arg u8State : The new state of the XTAL. + * @arg u8Drv : The XTAL drive ability. + * @arg u8Mode : The XTAL mode selection osc or exclk. + * @arg u8StableTime : The XTAL stable time selection. + * @retval int32_t: + * - LL_OK: XTAL initial successfully. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * - LL_ERR_BUSY: XTAL is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL while using it as system clock. + */ +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret; + + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8State)); + DDL_ASSERT(IS_CLK_XTAL_DRV_MD(pstcXtalInit->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL_MD(pstcXtalInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTAL_STB_SEL(pstcXtalInit->u8StableTime)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTALSTBCR, pstcXtalInit->u8StableTime); + + WRITE_REG8(CM_CMU->XTALCFGR, (0x80U | pstcXtalInit->u8Drv | pstcXtalInit->u8Mode)); + + if (CLK_XTAL_ON == pstcXtalInit->u8State) { + i32Ret = CLK_XtalCmd(ENABLE); + } else { + i32Ret = CLK_XtalCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL operate successfully + * - LL_ERR_BUSY: XTAL is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock. + */ +int32_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } + /* XTAL as PLL clock source and PLL is working */ + else if (CLK_PLL_SRC_XTAL == PLL_SRC) { + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Init XtalStd initial structure with default value. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalStdInit->u8State = CLK_XTALSTD_OFF; + pstcXtalStdInit->u8Mode = CLK_XTALSTD_MD_INT; + pstcXtalStdInit->u8Int = CLK_XTALSTD_INT_OFF; + pstcXtalStdInit->u8Reset = CLK_XTALSTD_RST_OFF; + } + + return i32Ret; +} + +/** + * @brief Initialise the XTAL status detection. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @arg u8State: The new state of the XTALSTD. + * @arg u8Mode: The XTAL status detection occur interrupt or reset. + * @arg u8Int: The XTAL status detection interrupt on or off. + * @arg u8Reset: The XTAL status detection reset on or off. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_STATE(pstcXtalStdInit->u8State)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_MD(pstcXtalStdInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTALSTD_INT_STATE(pstcXtalStdInit->u8Int)); + DDL_ASSERT(IS_CLK_XTALSTD_RST_STATE(pstcXtalStdInit->u8Reset)); + + /* Configure and enable XTALSTD */ + WRITE_REG8(CM_CMU->XTALSTDCR, (pstcXtalStdInit->u8State | \ + pstcXtalStdInit->u8Mode | \ + pstcXtalStdInit->u8Int | \ + pstcXtalStdInit->u8Reset)); + } + + return i32Ret; +} + +/** + * @brief Clear the XTAL error flag. + * @param None + * @retval None + * @note The system clock should not be XTAL before call this function. + */ +void CLK_ClearXtalStdStatus(void) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0x01U == READ_REG8(CM_CMU->XTALSTDSR)) { + /* Clear the XTAL STD flag */ + WRITE_REG8(CM_CMU->XTALSTDSR, 0x00U); + } +} + +/** + * @brief Get the XTAL error flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetXtalStdStatus(void) +{ + return ((0x00U != READ_REG32(CM_CMU->XTALSTDSR)) ? SET : RESET); +} + +/** + * @brief Init Xtal32 initial structure with default value. + * @param [in] pstcXtal32Init specifies the Parameter of XTAL32. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtal32Init->u8State = CLK_XTAL32_ON; + pstcXtal32Init->u8Drv = CLK_XTAL32_DRV_MID; + pstcXtal32Init->u8Filter = CLK_XTAL32_FILTER_ALL_MD; + } + + return i32Ret; +} + +/** + * @brief XTAL32 initialize. + * @param [in] pstcXtal32Init specifies the XTAL32 initial config. + * @arg u8State : The new state of the XTAL32. + * @arg u8Drv : The XTAL32 drive capacity. + * @arg u8Filter : The XTAL32 noise filter on or off. + * @retval int32_t: + * - LL_OK: XTAL32 initial successfully. + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret; + + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameters check */ + DDL_ASSERT(IS_CLK_XTAL32_STATE(pstcXtal32Init->u8State)); + DDL_ASSERT(IS_CLK_XTAL32_DRV_MD(pstcXtal32Init->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Filter)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTAL32CFGR, pstcXtal32Init->u8Drv); + WRITE_REG8(CM_CMU->XTAL32NFR, pstcXtal32Init->u8Filter); + + if (CLK_XTAL32_ON == pstcXtal32Init->u8State) { + i32Ret = CLK_Xtal32Cmd(ENABLE); + } else { + i32Ret = CLK_Xtal32Cmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL32 function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL32 operate successfully + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL32 == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_ON); + /* wait stable*/ + CLK_Delay(CLK_XTAL32_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief XTAL32 clock input function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note None + */ +void CLK_Xtal32InputCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG32(bCM_CMU->XTAL32CFGR_b.XTAL32IE, enNewState); +} + +/** + * @brief Set PLL source clock. + * @param [in] u32PllSrc PLL source clock. + * @arg CLK_PLL_SRC_XTAL + * @arg CLK_PLL_SRC_HRC + * @retval None + */ +void CLK_SetPLLSrc(uint32_t u32PllSrc) +{ + DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, u32PllSrc << PLL_SRC_POS); +} + +/** + * @brief Init PLL initial structure with default value. + * @param [in] pstcPLLInit specifies the Parameter of PLL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLInit->PLLCFGR = 0UL; + pstcPLLInit->PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + pstcPLLInit->PLLCFGR_f.PLLM = CLK_PLLM_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLN = CLK_PLLN_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLP = CLK_PLLP_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLQ = CLK_PLLQ_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLR = CLK_PLLR_DEFAULT; + pstcPLLInit->u8PLLState = CLK_PLL_OFF; + } + return i32Ret; +} + +/** + * @brief PLLH initialize. + * @param [in] pstcPLLInit specifies the structure of PLLH initial config. + * @arg u8PLLState : The new state of the PLLH. + * @arg PLLCFGR : PLLH config. + * @retval int32_t: + * - LL_OK: PLLH initial successfully + * - LL_ERR_TIMEOUT: PLLH initial timeout + * - LL_ERR_BUSY: PLLH is the source clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz. + * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz. + */ +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret; + +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { +#ifdef __DEBUG + DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLInit->PLLCFGR_f.PLLSRC)); + DDL_ASSERT(IS_CLK_PLLM_DIV(pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLN_MULTI(pstcPLLInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLP_DIV(pstcPLLInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLL_SRC_XTAL == pstcPLLInit->PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLL_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLL_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLQ_DIV(pstcPLLInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLR_DIV(pstcPLLInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLL_STATE(pstcPLLInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); +#endif /* __DEBUG */ + + /* set PLL source in advance */ + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, pstcPLLInit->PLLCFGR_f.PLLSRC << PLL_SRC_POS); + WRITE_REG32(CM_CMU->PLLHCFGR, pstcPLLInit->PLLCFGR); + + if (CLK_PLL_ON == pstcPLLInit->u8PLLState) { + i32Ret = CLK_PLLCmd(ENABLE); + } else { + i32Ret = CLK_PLLCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief PLL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: PLL operate successfully + * - LL_ERR_BUSY: PLL is the system clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: PLL operate timeout + * @note DO NOT STOP PLL while using it as system clock. + */ +int32_t CLK_PLLCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(PLL_EN_REG, CLK_PLL_OFF); + } + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLL_EN_REG, CLK_PLL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLL, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Init PLLx initial structure with default value. + * @param [in] pstcPLLxInit specifies the Parameter of PLLx. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Pllx for UPLL while HC32F460, HC32F451, HC32F452 + * Pllx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLxInit->PLLCFGR = 0UL; + pstcPLLxInit->u8PLLState = CLK_PLLX_OFF; + pstcPLLxInit->PLLCFGR_f.PLLP = CLK_PLLXP_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLQ = CLK_PLLXQ_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLR = CLK_PLLXR_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLN = CLK_PLLXN_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLM = CLK_PLLXM_DEFAULT; + } + return i32Ret; +} + +/** + * @brief PLLx Initialize. + * @param [in] pstcPLLxInit specifies the structure of UPLL initial config. + * @arg u8PLLState : The new state of the UPLL. + * @arg PLLCFGR : UPLL config. + * @retval int32_t: + * - LL_OK: UPLL initial successfully + * - LL_ERR_TIMEOUT: UPLL initial timeout + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The UPLL frequency (VCOOUT/UPLLP_Q_R) is between 15 ~ 240MHz. + */ +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret; + + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { +#ifdef __DEBUG + PLLxParamCheck(pstcPLLxInit); +#endif + + WRITE_REG32(CM_CMU->PLLACFGR, pstcPLLxInit->PLLCFGR); + + if (CLK_PLLX_ON == pstcPLLxInit->u8PLLState) { + i32Ret = CLK_PLLxCmd(ENABLE); + } else { + i32Ret = CLK_PLLxCmd(DISABLE); + } + } + return i32Ret; +} + +/** + * @brief PLLx function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: UPLL operate successfully + * - LL_ERR_TIMEOUT: UPLL operate timeout + * @note PLLx for UPLL while HC32F460, HC32F451, HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_OFF); + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLLX, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] u8Src Specifies the clock source to output. @ref CLK_MCO_Clock_Source + * @param [in] u8Div Specifies the MCOx prescaler. @ref CLK_MCO_Clock_Prescaler + * @retval None + * @note MCO pin should be configured in alternate function 1 mode. + */ +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div) +{ + __IO uint8_t *MCOCFGRx; + + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCO_SRC(u8Src)); + DDL_ASSERT(IS_CLK_MCO_DIV(u8Div)); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + /* enable register write. */ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCOCFGR1 + u8Ch)); + + /* Config the MCO */ + MODIFY_REG8(*MCOCFGRx, (CMU_MCOCFGR_MCOSEL | CMU_MCOCFGR_MCODIV), (u8Src | u8Div)); +} + +/** + * @brief Enable or disable the MCO1 output. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + __IO uint8_t *MCOCFGRx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCOCFGR1 + u8Ch)); + + /* Enable or disable clock output. */ + MODIFY_REG8(*MCOCFGRx, CMU_MCOCFGR_MCOEN, (uint8_t)enNewState << CMU_MCOCFGR_MCOEN_POS); +} + +/** + * @brief PLL/XTAL/HRC stable flag read. + * @param [in] u8Flag specifies the stable flag to be read. @ref CLK_STB_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_CLK_STB_FLAG(u8Flag)); + + return ((0x00U != READ_REG8_BIT(CM_CMU->OSCSTBSR, u8Flag)) ? SET : RESET); +} + +/** + * @brief Set the system clock source. + * @param [in] u8Src specifies the source of system clock. @ref CLK_System_Clock_Source + * @retval None + */ +void CLK_SetSysClockSrc(uint8_t u8Src) +{ + /* Set system clock source */ + SetSysClockSrc(u8Src); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Get bus clock frequency. + * @param [out] pstcClockFreq specifies the pointer to get bus frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcClockFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + GetClockFreq(pstcClockFreq); + } + return i32Ret; +} + +/** + * @brief Get bus clock frequency. + * @param [in] u32Clock specifies the bus clock to get frequency. @ref CLK_Bus_Clock_Sel + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock) +{ + uint32_t u32ClockFreq; + DDL_ASSERT(IS_CLK_BUS_CLK(u32Clock)); + + switch (u32Clock) { + case CLK_BUS_HCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS); + break; + case CLK_BUS_PCLK1: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + break; + case CLK_BUS_PCLK4: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS); + break; + case CLK_BUS_PCLK3: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + break; + case CLK_BUS_EXCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS); + break; + case CLK_BUS_PCLK0: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + break; + case CLK_BUS_PCLK2: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS); + break; + default: + u32ClockFreq = SystemCoreClock; + break; + } + return u32ClockFreq; +} + +/** + * @brief Get PLL clock frequency. + * @param [out] pstcPllClkFreq specifies the pointer to get PLL frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note PLL for MPLL, PLLx for UPLL while HC32F460, HC32F451, HC32F452 + * PLL for PLLH, PLLx for PLLA while HC32F4A0 + */ +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq) +{ + int32_t i32Ret = LL_OK; + uint32_t pllin; + uint32_t plln; + uint32_t pllm; + uint32_t pllp; + uint32_t pllq; + uint32_t pllr; + uint32_t pllxn; + uint32_t pllxm; + uint32_t pllxp; + uint32_t pllxq; + uint32_t pllxr; + + if (NULL == pstcPllClkFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pllp = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS); + pllq = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHQ) >> CMU_PLLHCFGR_PLLHQ_POS); + pllr = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHR) >> CMU_PLLHCFGR_PLLHR_POS); + plln = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS); + pllm = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS); + + pllxp = (uint32_t)((CM_CMU->PLLACFGR & CMU_PLLACFGR_PLLAP) >> CMU_PLLACFGR_PLLAP_POS); + pllxq = (uint32_t)((CM_CMU->PLLACFGR & CMU_PLLACFGR_PLLAQ) >> CMU_PLLACFGR_PLLAQ_POS); + pllxr = (uint32_t)((CM_CMU->PLLACFGR & CMU_PLLACFGR_PLLAR) >> CMU_PLLACFGR_PLLAR_POS); + pllxn = (uint32_t)((CM_CMU->PLLACFGR & CMU_PLLACFGR_PLLAN) >> CMU_PLLACFGR_PLLAN_POS); + pllxm = (uint32_t)((CM_CMU->PLLACFGR & CMU_PLLACFGR_PLLAM) >> CMU_PLLACFGR_PLLAM_POS); + + /* PLLHP is used as system clock. */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pllin = XTAL_VALUE; + } else { + pllin = HRC_VALUE; + } + + pstcPllClkFreq->u32PllVcin = (pllin / (pllm + 1UL)); + pstcPllClkFreq->u32PllVco = ((pllin / (pllm + 1UL)) * (plln + 1UL)); + pstcPllClkFreq->u32PllP = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + + pstcPllClkFreq->u32PllQ = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllq + 1UL); + pstcPllClkFreq->u32PllR = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllr + 1UL); + pstcPllClkFreq->u32PllxVcin = (pllin / (pllxm + 1UL)); + pstcPllClkFreq->u32PllxVco = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)); + pstcPllClkFreq->u32PllxP = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxp + 1UL); + pstcPllClkFreq->u32PllxQ = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxq + 1UL); + pstcPllClkFreq->u32PllxR = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxr + 1UL); + } + return i32Ret; +} + +/** + * @brief HCLK/PCLK divide setting. + * @param [in] u32Clock specifies the clock to be divided. @ref CLK_Bus_Clock_Sel + * @param [in] u32Div specifies the clock divide factor. @ref CLK_Clock_Divider + * @retval None + * @note u32Div could choose CLK_HCLK_Divider, CLK_PCLK0_Divider, CLK_PCLK1_Divider, + * CLK_PCLK2_Divider, CLK_PCLK3_Divider, CLK_PCLK4_Divider, CLK_EXCLK_Divider, according to the MCU + */ +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + /* Set clock divider */ + SetSysClockDiv(u32Clock, u32Div); + + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Set peripheral clock source. + * @param [in] u16Src specifies the peripheral clock source. @ref CLK_PERIPH_Sel + * @retval None + * @note peripheral for ADC/DAC/TRNG while HC32F460,HC32F4A0, HC32F451, HC32F452 + * peripheral only for ADC while HC32M423,HC32F120,HC32F160,HC32M120 + */ +void CLK_SetPeriClockSrc(uint16_t u16Src) +{ + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u16Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->PERICKSEL, u16Src); +} + +/** + * @brief USB clock source config. + * @param [in] u8Src specifies the USB clock source. @ref CLK_USBCLK_Sel + * @retval None + */ +void CLK_SetUSBClockSrc(uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_USBCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->USBCKCFGR, u8Src); +} + +/** + * @brief I2S clock source config. + * @param [in] u8Unit specifies the I2S channel for clock source. @ref CLK_I2S_Sel + * @arg CLK_I2S1: I2S Channel 1 + * @arg CLK_I2S2: I2S Channel 2 + * @arg CLK_I2S3: I2S Channel 3 + * @arg CLK_I2S4: I2S Channel 4 + * @param [in] u8Src specifies the I2S clock source. @ref CLK_PERIPH_Sel + * @retval None + */ +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_I2S_UNIT(u8Unit)); + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG16(CM_CMU->I2SCKSEL, (uint16_t)CMU_I2SCKSEL_I2S1CKSEL << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS), \ + (uint16_t)u8Src << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS)); +} + +/** + * @brief CAN clock source config. + * @param [in] u8Unit specifies the CAN channel for clock source. @ref CLK_CAN_Sel + * @arg CLK_CAN1: CAN Channel 1 + * @arg CLK_CAN2: CAN Channel 2 + * @arg CLK_CAN2: CAN Channel 3 (for HC32F472 only) + * @param [in] u8Src specifies the CAN clock source. @ref CLK_CANCLK_Sel + * @retval None + */ +void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_CAN_UNIT(u8Unit)); + DDL_ASSERT(IS_CLK_CANCLK(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0U != (CLK_CAN1 & u8Unit)) { + MODIFY_REG8(CM_CMU->CANCKCFGR, CMU_CANCKCFGR_CAN1CKS, u8Src); + } + if (0U != (CLK_CAN2 & u8Unit)) { + MODIFY_REG8(CM_CMU->CANCKCFGR, CMU_CANCKCFGR_CAN2CKS, u8Src << CMU_CANCKCFGR_CAN2CKS_POS); + } +} + +/** + * @brief Enable or disable the TPIU clock. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_TpiuClockCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKOE, (uint8_t)enNewState << CMU_TPIUCKCFGR_TPIUCKOE_POS); +} + +/** + * @brief TPIU clock divider config. + * @param [in] u8Div specifies the TPIU clock divide factor. @ref CLK_TPIU_Divider + * @arg CLK_TPIUCLK_DIV1: TPIU clock no divide + * @arg CLK_TPIUCLK_DIV2: TPIU clock divide by 2 + * @arg CLK_TPIUCLK_DIV4: TPIU clock divide by 4 + * @retval None + */ +void CLK_SetTpiuClockDiv(uint8_t u8Div) +{ + DDL_ASSERT(IS_CLK_TPIUCLK_DIV(u8Div)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8Div); +} +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c new file mode 100644 index 0000000000..c7b66419a0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c @@ -0,0 +1,716 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.c + * @brief This file provides firmware functions to manage the Comparator(CMP). + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_cmp.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CMP CMP + * @brief CMP Driver Library + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Macros CMP Local Macros + * @{ + */ + +/** + * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity + * @{ + */ +#define IS_CMP_UNIT(x) \ +( ((x) == CM_CMP1) || \ + ((x) == CM_CMP2) || \ + ((x) == CM_CMP3) || \ + ((x) == CM_CMP4)) + +#define IS_CMP_WIN_MD_UNIT(x) \ +( ((x) == CMP_WIN_CMP12) || \ + ((x) == CMP_WIN_CMP34)) + +#define IS_CMP1_3_POSITIVE_IN(x) \ +( ((x) == CMP_POSITIVE_NONE) || \ + ((x) == CMP1_POSITIVE_PGA1_BP) || \ + ((x) == CMP1_POSITIVE_PGA1) || \ + ((x) == CMP1_POSITIVE_PGA2) || \ + ((x) == CMP1_POSITIVE_CMP1_INP2) || \ + ((x) == CMP1_POSITIVE_CMP1_INP3) || \ + ((x) == CMP1_POSITIVE_CMP2_INP3) || \ + ((x) == CMP1_POSITIVE_CMP1_INP4)) + +#define IS_CMP2_4_POSITIVE_IN(x) \ +( ((x) == CMP_POSITIVE_NONE) || \ + ((x) == CMP2_POSITIVE_PGA2_BP) || \ + ((x) == CMP2_POSITIVE_PGA2) || \ + ((x) == CMP2_POSITIVE_CMP2_INP3) || \ + ((x) == CMP2_POSITIVE_CMP2_INP4)) + +#define IS_CMP_NEGATIVE_IN(x) \ +( ((x) == CMP_NEGATIVE_NONE) || \ + ((x) == CMP1_NEGATIVE_DAC1_OUT1) || \ + ((x) == CMP1_NEGATIVE_DAC1_OUT2) || \ + ((x) == CMP1_NEGATIVE_CMP123_INM3) || \ + ((x) == CMP1_NEGATIVE_CMP1_INM4)) + +#define IS_CMP_WIN_LOW_IN(x) \ +( ((x) == CMP_WIN_LOW_NONE) || \ + ((x) == CMP12_WIN_LOW_DAC1_OUT1) || \ + ((x) == CMP12_WIN_LOW_DAC1_OUT2) || \ + ((x) == CMP12_WIN_LOW_CMP123_INM3) || \ + ((x) == CMP12_WIN_LOW_CMP1_INM4)) + +#define IS_CMP_WIN_HIGH_IN(x) \ +( ((x) == CMP_WIN_HIGH_NONE) || \ + ((x) == CMP12_WIN_HIGH_DAC1_OUT1) || \ + ((x) == CMP12_WIN_HIGH_DAC1_OUT2) || \ + ((x) == CMP12_WIN_HIGH_CMP123_INM3) || \ + ((x) == CMP12_WIN_HIGH_CMP2_INM4)) + +#define IS_CMP_OUT_POLARITY(x) \ +( ((x) == CMP_OUT_INVT_OFF) || \ + ((x) == CMP_OUT_INVT_ON)) + +#define IS_CMP_OUT_FILTER(x) \ +( ((x) == CMP_OUT_FILTER_NONE) || \ + ((x) == CMP_OUT_FILTER_CLK) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV8) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV32)) + +#define IS_CMP_OUT_DETECT_EDGE(x) \ +( ((x) == CMP_DETECT_EDGS_NONE) || \ + ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +#define IS_CMP_BLANKWIN_VALID_LVL(x) \ +( ((x) == CMP_BLANKWIN_VALID_LVL_LOW) || \ + ((x) == CMP_BLANKWIN_VALID_LVL_HIGH)) + +#define IS_CMP_BLANKWIN_OUT_LVL(x) \ +( ((x) == CMP_BLANKWIN_OUTPUT_LVL_LOW) || \ + ((x) == CMP_BLANKWIN_OUTPUT_LVL_HIGH)) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Functions CMP Local Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +static void CMP_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + ; + } + } +} + +/** + * @brief Get CMP function status and disable CMP + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval uint16_t The register value + */ +static uint16_t GetCmpFuncStatusAndDisFunc(CM_CMP_TypeDef *CMPx) +{ + uint16_t u16temp; + /* Read CMP status */ + u16temp = (uint16_t)(uint8_t)READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + return u16temp; +} + +/** + * @brief Revcover CMP function status + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpFuncStatus CMP function status backup value + * @retval None + */ +static void RecoverCmpFuncStatus(CM_CMP_TypeDef *CMPx, uint16_t u16CmpFuncStatus) +{ + if (u16CmpFuncStatus != 0U) { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u16CmpFuncStatus); + /* Delay 1us */ + CMP_DelayUS(1U); + } +} + +/** + * @} + */ + +/** + * @defgroup CMP_Global_Functions CMP Global Functions + * @{ + */ + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCmpInit Pointer to a structure variable which will be initialized. @ref stc_cmp_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpInit != NULL) { + pstcCmpInit->u16PositiveInput = CMP_POSITIVE_NONE; + pstcCmpInit->u16NegativeInput = CMP_NEGATIVE_NONE; + pstcCmpInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCmpWindowInit Pointer to a structure variable. @ref stc_cmp_window_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpWindowInit != NULL) { + pstcCmpWindowInit->u8WinVolLow = CMP_NEGATIVE_NONE; + pstcCmpWindowInit->u8WinVolHigh = CMP_NEGATIVE_NONE; + pstcCmpWindowInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpWindowInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpWindowInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize CMP unit + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval None + */ +void CMP_DeInit(CM_CMP_TypeDef *CMPx) +{ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + CLR_REG8(CMPx->MDR); + CLR_REG8(CMPx->FIR); + CLR_REG8(CMPx->OCR); + CLR_REG8(CMPx->PMSR); + CLR_REG16(CMPx->VISR); + CLR_REG16(CMPx->TWSR); + CLR_REG16(CMPx->TWPR); +} + +/** + * @brief CMP normal mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcCmpInit CMP function base parameter structure + * @arg pstcCmpInit->u16PositiveInput: @ref CMP_Positive_Input_Select + * @arg pstcCmpInit->u16NegativeInput: @ref CMP_Negative_Input_Select + * @arg pstcCmpInit->u16OutPolarity: @ref CMP_Out_Polarity_Select + * @arg pstcCmpInit->u16OutDetectEdge: @ref CMP_Out_Detect_Edge_Select + * @arg pstcCmpInit->u16OutFilter: @ref CMP_Out_Filter + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCmpInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u16OutFilter)); + if ((CM_CMP1 == CMPx) || (CM_CMP3 == CMPx)) { + DDL_ASSERT(IS_CMP1_3_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP2_4_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } + DDL_ASSERT(IS_CMP_NEGATIVE_IN(pstcCmpInit->u16NegativeInput)); + + /* Stop CMP compare */ + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + + /* Set voltage in */ + WRITE_REG8(CMPx->PMSR, (pstcCmpInit->u16PositiveInput & CMP_PMSR_CVSL) | pstcCmpInit->u16NegativeInput); + if ((CM_CMP1 == CMPx) || (CM_CMP3 == CMPx)) { + if ((CMP_PMSR_CVSL_1 == (pstcCmpInit->u16PositiveInput & CMP_PMSR_CVSL)) \ + || (CMP_PMSR_CVSL_2 == (pstcCmpInit->u16PositiveInput & CMP_PMSR_CVSL))) { + WRITE_REG16(CMPx->VISR, (pstcCmpInit->u16PositiveInput >> VISR_OFFSET) & (CMP_VISR_P3SL | CMP_VISR_P2SL)); + } + } + + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Start CMP compare */ + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(CMPx->FIR, (pstcCmpInit->u16OutFilter | pstcCmpInit->u16OutDetectEdge)); + WRITE_REG8(CMPx->OCR, pstcCmpInit->u16OutPolarity); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Voltage compare function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + } else { + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + } + +} + +/** + * @brief Voltage compare interrupt function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } else { + CLR_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } +} + +/** + * @brief Voltage compare output command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } + +} + +/** + * @brief Voltage compare output port VCOUT function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } + +} + +/** + * @brief Voltage compare result flag read + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An @ref en_flag_status_t enumeration type value. + * In normal mode + * - RESET: compare voltage < reference voltage + * - SET: compare voltage > reference voltage + * In Window mode + * - RESET: compare voltage < reference low voltage or compare voltage > reference high voltage + * - SET: reference low voltage < compare voltage < reference high voltage + */ +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx) +{ + en_flag_status_t i32Ret; + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + i32Ret = (READ_REG8_BIT(CMPx->MDR, CMP_MDR_CMON) != 0U) ? SET : RESET; + return i32Ret; +} + +/** + * @brief Set output detect edge + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. @ref CMP_Out_Detect_Edge_Select + * @retval None + */ +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output detect edge selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_EDGS, u8CmpEdges); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output filter + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpFilter CMP output filter selection. @ref CMP_Out_Filter + * @retval None + */ +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + /* CMP output filter selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_FCKS, u8CmpFilter); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output polarity + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpPolarity CMP output polarity selection. @ref CMP_Out_Polarity_Select + * @retval None + */ +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(u16CmpPolarity)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output polarity selection */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_COPS, u16CmpPolarity); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set positive in(compare voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16PositiveInput @ref CMP_Positive_Input_Select + * @retval None + */ +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + if ((CM_CMP1 == CMPx) || (CM_CMP3 == CMPx)) { + DDL_ASSERT(IS_CMP1_3_POSITIVE_IN(u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP2_4_POSITIVE_IN(u16PositiveInput)); + } + + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG8(CMPx->PMSR, CMP_PMSR_CVSL, (u16PositiveInput & CMP_PMSR_CVSL)); + if ((CM_CMP1 == CMPx) || (CM_CMP3 == CMPx)) { + if ((CMP_PMSR_CVSL_1 == (u16PositiveInput & CMP_PMSR_CVSL)) || (CMP_PMSR_CVSL_2 == (u16PositiveInput & CMP_PMSR_CVSL))) { + MODIFY_REG16(CMPx->VISR, (CMP_VISR_P3SL | CMP_VISR_P2SL), (u16PositiveInput >> VISR_OFFSET)); + } + } + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set negative in(reference voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16NegativeInput @ref CMP_Negative_Input_Select + * @retval None + */ +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_NEGATIVE_IN(u16NegativeInput)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG8(CMPx->PMSR, CMP_PMSR_RVSL, u16NegativeInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief CMP window mode initialize + * @param [in] u8WinCMPx @ref CMP_Window_Mode_Unit + * @param [in] pstcCmpWindowInit CMP function base parameter structure @ref stc_cmp_window_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + * @note Window mode compare input: + * HC32F4A0: + * CMP2_INP3 valid for u16PositiveInput of CMP_WIN_CMP12 + * CMP4_INP3 valid for u16PositiveInput of CMP_WIN_CMP34 + * HC32M423 + * IVCMP2_2 valid for u16PositiveInput of CMP_WIN_CMP23 + * HC32M424 + * IVCMP1_0 or IVCMP1_1 valid for u16PositiveInput CMP_WIN_CMP13 + * IVCMP2_0 or IVCMP2_1 valid for u16PositiveInput CMP_WIN_CMP24 + * HC32M120 + * IVCMP2_0 valid for u16PositiveInput of CMP_WIN_CMP12 + */ +int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check configuration structure */ + if (NULL != pstcCmpWindowInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_WIN_MD_UNIT(u8WinCMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpWindowInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpWindowInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpWindowInit->u16OutFilter)); + DDL_ASSERT(IS_CMP_WIN_LOW_IN(pstcCmpWindowInit->u8WinVolLow)); + DDL_ASSERT(IS_CMP_WIN_HIGH_IN(pstcCmpWindowInit->u8WinVolHigh)); + + CM_CMP_TypeDef *pCMP_MAIN; + CM_CMP_TypeDef *pCMP_MINOR; + + if (u8WinCMPx == CMP_WIN_CMP12) { + pCMP_MAIN = CM_CMP2; + pCMP_MINOR = CM_CMP1; + } else { + pCMP_MAIN = CM_CMP4; + pCMP_MINOR = CM_CMP3; + } + /* Stop CMP compare */ + CLR_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB); + CLR_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB); + + /* Set positive in(compare voltage), window voltage */ + WRITE_REG8(pCMP_MINOR->PMSR, (CMP1_POSITIVE_CMP2_INP3 & CMP_PMSR_CVSL) | pstcCmpWindowInit->u8WinVolLow); + WRITE_REG8(pCMP_MAIN->PMSR, (CMP2_POSITIVE_CMP2_INP3 & CMP_PMSR_CVSL) | pstcCmpWindowInit->u8WinVolHigh); + WRITE_REG16(pCMP_MINOR->VISR, (CMP1_POSITIVE_CMP2_INP3 >> VISR_OFFSET) & (CMP_VISR_P3SL | CMP_VISR_P2SL)); + WRITE_REG16(pCMP_MAIN->VISR, (CMP2_POSITIVE_CMP2_INP3 >> VISR_OFFSET) & (CMP_VISR_P3SL | CMP_VISR_P2SL)); + /* Select window compare mode */ + SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CWDE); + /* Start CMP compare function */ + SET_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB); + SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(pCMP_MAIN->FIR, pstcCmpWindowInit->u16OutFilter | pstcCmpWindowInit->u16OutDetectEdge); + WRITE_REG8(pCMP_MAIN->OCR, pstcCmpWindowInit->u16OutPolarity); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Blank window function disable specified window source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16BlankWindowSrc Blank window source. + * @retval None + */ +void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + /* Set blank window valid level high */ + CLR_REG16_BIT(CMPx->TWPR, u16BlankWindowSrc); + /* Disable blank window source */ + CLR_REG16_BIT(CMPx->TWSR, u16BlankWindowSrc); +} + +/** + * @brief Voltage compare blank window function configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcBlankWindowInit Configuration structure for blank window mode. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcBlankWindowInit) { + i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_BLANKWIN_VALID_LVL(pstcBlankWindowInit->u8ValidLevel)); + DDL_ASSERT(IS_CMP_BLANKWIN_OUT_LVL(pstcBlankWindowInit->u8OutLevel)); + + /* Select output level when blank window valid */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_TWOL, pstcBlankWindowInit->u8OutLevel); + /* Select blank window valid level */ + if (CMP_BLANKWIN_VALID_LVL_LOW == pstcBlankWindowInit->u8ValidLevel) { + SET_REG16_BIT(CMPx->TWPR, pstcBlankWindowInit->u16Src); + } else { + CLR_REG16_BIT(CMPx->TWPR, pstcBlankWindowInit->u16Src); + } + /* Select blank window source */ + SET_REG16_BIT(CMPx->TWSR, pstcBlankWindowInit->u16Src); + } + return i32Ret; +} + +/** + * @brief CMP out blank window function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE); + } +} + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c new file mode 100644 index 0000000000..a321beb427 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c @@ -0,0 +1,584 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.c + * @brief This file provides firmware functions to manage the Cyclic Redundancy + * Check(CRC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_crc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CRC CRC + * @brief Cyclic Redundancy Check Driver Library + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Macros CRC Local Macros + * @{ + */ + +/** + * @defgroup CRC_Check_Parameters_Validity CRC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for CRC protocol. */ +#define IS_CRC_PROTOCOL(x) \ +( ((x) == CRC_CRC16) || \ + ((x) == CRC_CRC32)) + +/*! Parameter validity check for CRC data width. */ +#define IS_CRC_DATA_WIDTH(x) \ +( ((x) == CRC_DATA_WIDTH_8BIT) || \ + ((x) == CRC_DATA_WIDTH_16BIT) || \ + ((x) == CRC_DATA_WIDTH_32BIT)) + +/** + * @} + */ + +/** + * @defgroup CRC_Registers_Reset_Value_definition CRC Registers Reset Value + * @{ + */ +#define CRC_CR_RST_VALUE (0x0001UL) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Bit_Width CRC Data Bit Width + * @{ + */ +#define CRC_DATA_WIDTH_8BIT (1U) +#define CRC_DATA_WIDTH_16BIT (2U) +#define CRC_DATA_WIDTH_32BIT (4U) +/** + * @} + */ + +/** + * @defgroup CRC_Register_Address CRC Register Address + * @{ + */ +#define CRC_DATA_ADDR ((uint32_t)(&CM_CRC->DAT0)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Functions CRC Local Functions + * @{ + */ + +/** + * @brief Calculate the CRC value of a 8-bit data buffer. + * @param [in] au8Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au8Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM8(u32DataAddr) = au8Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 16-bit data buffer. + * @param [in] au16Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au16Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM16(u32DataAddr) = au16Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 32-bit data buffer. + * @param [in] au32Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au32Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM32(u32DataAddr) = au32Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +static uint32_t CRC_Accumulate(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + u32CrcValue = READ_REG32(CM_CRC->RESLT); + } else { + u32CrcValue = (READ_REG16(CM_CRC->RESLT) & CRC16_INIT_VALUE); + } + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +static uint32_t CRC_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + WRITE_REG32(CM_CRC->RESLT, u32InitValue); + } else { + WRITE_REG16(CM_CRC->RESLT, (u32InitValue & CRC16_INIT_VALUE)); + } + + u32CrcValue = CRC_Accumulate(u8DataWidth, pvData, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +static en_flag_status_t CRC_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, + const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_Calculate(u32InitValue, u8DataWidth, pvData, u32Len); + + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + (void)CRC_WriteData32(&u32ExpectValue, 1UL); + } else { + (void)CRC_WriteData16((uint16_t *)((void *)&u32ExpectValue), 1UL); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} +/** + * @} + */ + +/** + * @defgroup CRC_Global_Functions CRC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_crc_init_t to default values. + * @param [out] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + pstcCrcInit->u32Protocol = CRC_CRC16; + pstcCrcInit->u32InitValue = CRC16_INIT_VALUE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the CRC. + * @param [in] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + DDL_ASSERT(IS_CRC_PROTOCOL(pstcCrcInit->u32Protocol)); + CRC_DeInit(); + + MODIFY_REG32(CM_CRC->CR, CRC_CRC32, pstcCrcInit->u32Protocol); + + /* Set initial value */ + if (CRC_CRC32 == pstcCrcInit->u32Protocol) { + WRITE_REG32(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } else { + WRITE_REG16(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize the CRC. + * @param None + * @retval None + */ +void CRC_DeInit(void) +{ + WRITE_REG32(CM_CRC->CR, CRC_CR_RST_VALUE); +} + +/** + * @brief Get status of the CRC operation result. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_GetResultStatus(void) +{ + uint32_t u32Status; + + u32Status = READ_REG32_BIT(CM_CRC->CR, CRC_CR_FLAG); + + return (u32Status > 0UL) ? SET : RESET; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_8BIT, au8Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_16BIT, au16Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_32BIT, au32Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData8(uint32_t u32InitValue, const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_8BIT, au8Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData16(uint32_t u32InitValue, const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_16BIT, au16Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData32(uint32_t u32InitValue, const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_32BIT, au32Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData8(uint32_t u32InitValue, const uint8_t au8Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_8BIT, au8Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData16(uint32_t u32InitValue, const uint16_t au16Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_16BIT, au16Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData32(uint32_t u32InitValue, const uint32_t au32Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_32BIT, au32Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c new file mode 100644 index 0000000000..da133922dd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c @@ -0,0 +1,384 @@ +/** + ******************************************************************************* + * @file hc32_ll_ctc.c + * @brief This file provides firmware functions to manage the Clock Trimming + * Controller(CTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_ctc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CTC CTC + * @brief CTC Driver Library + * @{ + */ + +#if (LL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Local_Macros CTC Local Macros + * @{ + */ + +/** + * @defgroup CTC_Check_Parameters_Validity CTC Check Parameters Validity + * @{ + */ +#define IS_CTC_REF_CLK_SRC(x) \ +( ((x) == CTC_REF_CLK_SRC_XTAL) || \ + ((x) == CTC_REF_CLK_SRC_XTAL32) || \ + ((x) == CTC_REF_CLK_SRC_CTCREF)) + +#define IS_CTC_REF_CLK_DIV(x) \ +( ((x) == CTC_REF_CLK_DIV8) || \ + ((x) == CTC_REF_CLK_DIV32) || \ + ((x) == CTC_REF_CLK_DIV128) || \ + ((x) == CTC_REF_CLK_DIV256) || \ + ((x) == CTC_REF_CLK_DIV512) || \ + ((x) == CTC_REF_CLK_DIV1024) || \ + ((x) == CTC_REF_CLK_DIV2048) || \ + ((x) == CTC_REF_CLK_DIV4096)) + +#define IS_CTC_OFFSET_VALUE(x) ((x) <= 0xFFUL) + +#define IS_CTC_RELOAD_VALUE(x) ((x) <= 0xFFFFUL) + +#define IS_CTC_TRIM_VALUE(x) ((x) <= 0x3FUL) + +#define IS_CTC_TOLERANT_ERR(x) \ +( ((x) >= 0.0F) && \ + ((x) <= CTC_TOLERANT_ERR_MAX)) + +#define IS_CTC_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | CTC_FLAG_ALL) == CTC_FLAG_ALL)) + +/** + * @} + */ + +/** + * @defgroup CTC_Tolerant_Error_Max CTC Tolerant Error Max + * @{ + */ +#define CTC_TOLERANT_ERR_MAX (1.0F) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup CTC_Local_Functions CTC Local Functions + * @{ + */ + +/** + * @brief Get HRC clock frequency. + * @param None + * @retval HRC clock frequency. + */ +static uint32_t CTC_GetHrcClockFreq(void) +{ + return HRC_VALUE; +} + +/** + * @brief Get reference clock division. + * @param [in] u32Cr1RefPsc CTC CR1 REFPSC bits value. + * This parameter can be between Min_Data=0 and Max_Data=7 + * @retval Reference clock division. + */ +static uint32_t CTC_GetRefClockDiv(uint32_t u32Cr1RefPsc) +{ + uint32_t u32RefclkDiv; + + if (u32Cr1RefPsc < CTC_REF_CLK_DIV128) { + u32RefclkDiv = (8UL << (2UL * u32Cr1RefPsc)); + } else { + u32RefclkDiv = (32UL << u32Cr1RefPsc); + } + + return u32RefclkDiv; +} + +/** + * @} + */ + +/** + * @defgroup CTC_Global_Functions CTC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_ctc_ct_init_t to default values. + * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCtcInit value is NULL. + */ +int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCtcInit) { + pstcCtcInit->u32RefClockFreq = 0UL; + pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_SRC_CTCREF; + pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8; + pstcCtcInit->f32TolerantErrRate = 0.0F; + pstcCtcInit->u8TrimValue = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize CTC function. + * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_BUSY: CTC state is busy. + * - LL_ERR_INVD_PARAM: If one of following cases matches: + * - The pointer pstcCtcInit value is NULL. + * - Reference frequency is out of range. + * - Calculate reload & offset value out of range. + */ +int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit) +{ + float32_t f32OffsetValue; + uint32_t u32RegValue; + uint32_t u32ReloadValue; + uint32_t u32OffsetValue; + uint32_t u32RefClockDiv; + uint32_t u32CtcHrcFreq; + uint32_t u32Multiplier; + uint64_t u64InterClock; + int32_t i32Ret = LL_ERR_BUSY; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) { + if ((NULL == pstcCtcInit) || (0UL == pstcCtcInit->u32RefClockFreq)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CTC_REF_CLK_SRC(pstcCtcInit->u32RefClockSrc)); + DDL_ASSERT(IS_CTC_REF_CLK_DIV(pstcCtcInit->u32RefClockDiv)); + DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u8TrimValue)); + DDL_ASSERT(IS_CTC_TOLERANT_ERR(pstcCtcInit->f32TolerantErrRate)); + u32CtcHrcFreq = CTC_GetHrcClockFreq(); + + u32RefClockDiv = CTC_GetRefClockDiv(pstcCtcInit->u32RefClockDiv); + u64InterClock = ((uint64_t)u32CtcHrcFreq) * ((uint64_t)(u32RefClockDiv)); + u32Multiplier = (uint32_t)(u64InterClock / pstcCtcInit->u32RefClockFreq); + + /* Calculate offset value formula: OFSVAL = (Fhrc / (Fref * Fref_divsion)) * TA */ + f32OffsetValue = ((float32_t)u32Multiplier) * (pstcCtcInit->f32TolerantErrRate); + u32OffsetValue = (uint32_t)(f32OffsetValue); + + /* Calculate reload value formula: RLDVAL = (Fhrc / (Fref * Fref_divsion)) + OFSVAL */ + u32ReloadValue = u32Multiplier + u32OffsetValue; + + /* Check reload and offset value */ + if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) { + /* Set CR1 */ + u32RegValue = (pstcCtcInit->u32RefClockDiv | pstcCtcInit->u32RefClockSrc | \ + ((uint32_t)pstcCtcInit->u8TrimValue << CTC_CR1_TRMVAL_POS)); + WRITE_REG32(CM_CTC->CR1, u32RegValue); + + /* Set CR2 */ + u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue); + WRITE_REG32(CM_CTC->CR2, u32RegValue); + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief De-Initialize CTC function. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_BUSY: CTC state is busy + */ +int32_t CTC_DeInit(void) +{ + int32_t i32Ret = LL_ERR_BUSY; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) { + /* Configures the registers to reset value. */ + WRITE_REG32(CM_CTC->CR1, 0UL); + WRITE_REG32(CM_CTC->CR2, 0UL); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable CTC error interrupt function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CTC_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE); + } else { + CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE); + } +} + +/** + * @brief Get CTC flag status. + * @param [in] u32Flag CTC flag + * This parameter can be any composed value of the macros group @ref CTC_Flag + * @arg CTC_FLAG_TRIM_OK: Trimming OK flag + * @arg CTC_FLAG_TRIM_OVF: Trimming overflow flag + * @arg CTC_FLAG_TRIM_UDF: Trimming underflow flag + * @arg CTC_FLAG_BUSY: CTC busy flag + * @retval Returned value can be one of the following values: + */ +en_flag_status_t CTC_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_CTC_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_CTC->STR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Set CTC trimming value. + * @param [in] u8TrimValue CTC trimming value + * This parameter can be Min_Data=0 && Max_Data=0x3F + * @retval None + */ +void CTC_SetTrimValue(uint8_t u8TrimValue) +{ + DDL_ASSERT(IS_CTC_TRIM_VALUE(u8TrimValue)); + + MODIFY_REG32(CM_CTC->CR1, CTC_CR1_TRMVAL, ((uint32_t)u8TrimValue << CTC_CR1_TRMVAL_POS)); +} + +/** + * @brief Get CTC trimming value. + * @param None + * @retval CTC trimming value(between Min_Data=0 and Max_Data=0x3F) + */ +uint8_t CTC_GetTrimValue(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_CTC->CR1, CTC_CR1_TRMVAL) >> CTC_CR1_TRMVAL_POS); +} + +/** + * @brief Set CTC reload value. + * @param [in] u16ReloadValue CTC reload value + * This parameter can be between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +void CTC_SetReloadValue(uint16_t u16ReloadValue) +{ + MODIFY_REG32(CM_CTC->CR2, CTC_CR2_RLDVAL, ((uint32_t)u16ReloadValue << CTC_CR2_RLDVAL_POS)); +} + +/** + * @brief Get CTC reload value. + * @param None + * @retval CTC reload value (between Min_Data=0 and Max_Data=0xFFFF) + */ +uint16_t CTC_GetReloadValue(void) +{ + return (uint16_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_RLDVAL) >> CTC_CR2_RLDVAL_POS); +} + +/** + * @brief Set CTC offset value. + * @param [in] u8OffsetValue CTC offset value + * This parameter can be between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +void CTC_SetOffsetValue(uint8_t u8OffsetValue) +{ + MODIFY_REG32(CM_CTC->CR2, CTC_CR2_OFSVAL, ((uint32_t)u8OffsetValue << CTC_CR2_OFSVAL_POS)); +} + +/** + * @brief Get CTC offset value. + * @param None + * @retval CTC offset value (between Min_Data=0 and Max_Data=0xFF) + */ +uint8_t CTC_GetOffsetValue(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_OFSVAL) >> CTC_CR2_OFSVAL_POS); +} + +/** + * @} + */ + +#endif /* LL_CTC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c new file mode 100644 index 0000000000..5cf01421e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c @@ -0,0 +1,529 @@ +/** + ******************************************************************************* + * @file hc32_ll_dac.c + * @brief This file provides firmware functions to manage the Digital-to-Analog + * Converter(DAC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dac.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DAC DAC + * @brief DAC Driver Library + * @{ + */ + +#if (LL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DAC_Local_Macros DAC Local Macros + * @{ + */ + +/** + * @defgroup DAC_Check_Parameters_Validity DAC Check Parameters Validity + * @{ + */ + +#define IS_VALID_UNIT(x) (((x) == CM_DAC1) || ((x) == CM_DAC2)) + +#define IS_VALID_CH(x) (((x) == DAC_CH1) || ((x) == DAC_CH2)) + +#define IS_VALID_DATA_ALIGN(x) (((x) == DAC_DATA_ALIGN_L) || ((x) == DAC_DATA_ALIGN_R)) + +#define IS_VALID_DATA_SRC(x) (((x) == DAC_DATA_SRC_DATAREG) || ((x) == DAC_DATA_SRC_DCU)) + +#define IS_VALID_ADCPRIO_CONFIG(x) ((0U != (x)) && (DAC_ADP_SELECT_ALL == ((x) | DAC_ADP_SELECT_ALL))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Functions DAC Global Functions + * @{ + */ + +/** + * @brief Set DAC data source for specified channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify the DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] u16Src Specify the data source. + * This parameter can be a value of @ref DAC_DATA_SRC + * - DAC_DATA_SRC_DATAREG: convert source is from data register + * - DAC_DATA_SRC_DCU: convert source is from DCU + * @retval None + */ +void DAC_SetDataSrc(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_VALID_DATA_SRC(u16Src)); + + MODIFY_REG16(DACx->DACR, DAC_DACR_EXTDSL1 << u16Ch, u16Src << u16Ch); +} + +/** + * @brief DAC data register's data alignment pattern configuration + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Align Specify the data alignment. + * This parameter can be a value of @ref DAC_DATAREG_ALIGN_PATTERN + * - DAC_DATA_ALIGN_L: left alignment + * - DAC_DATA_ALIGN_R: right alignment + * @retval None + */ +void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_DATA_ALIGN(u16Align)); + + MODIFY_REG16(DACx->DACR, DAC_DACR_ALIGN, u16Align); +} + +/** + * @brief DAC output function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16Cmd = (uint16_t)(1UL << (DAC_DAOCR_DAODIS1_POS + u16Ch)); + + if (ENABLE == enNewState) { + CLR_REG16_BIT(DACx->DAOCR, u16Cmd); + } else { + SET_REG16_BIT(DACx->DAOCR, u16Cmd); + } +} + +/** + * @brief DAC AMP function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_MD: cannot ENABLE AMP when data source is from DCU + */ +int32_t DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16Cmd = (uint16_t)(1UL << (DAC_DACR_EXTDSL1_POS + u16Ch)); + + if ((0U != (READ_REG16_BIT(DACx->DACR, u16Cmd))) && (ENABLE == enNewState)) { + i32Ret = LL_ERR_INVD_MD; + } else { + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DAAMP1_POS + u16Ch)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DACR, u16Cmd); + } else { + CLR_REG16_BIT(DACx->DACR, u16Cmd); + } + } + + return i32Ret; +} + +/** + * @brief DAC ADC priority function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioCmd + */ +void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } else { + CLR_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } +} + +/** + * @brief Enable or Disable the ADC priority for the selected ADCx + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16ADCxPrio ADCx priority to be enabled or disabled. + * This parameter can be one or any combination of the following values: + * @arg DAC_ADP_SELECT_ADC1 + * @arg DAC_ADP_SELECT_ADC2 + * @arg DAC_ADP_SELECT_ADC3 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioConfig + */ +void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_ADCPRIO_CONFIG(u16ADCxPrio)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } else { + CLR_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } +} + +/** + * @brief Start the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_MD: cannot start single channel when \n + * this channel have already been started by \n + * @ref DAC_StartDualCh + */ +int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_OK; + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if ((DACx->DACR & DAC_DACR_DAEN) != 0U) { + i32Ret = LL_ERR_INVD_MD; + } else { + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1EN_POS + u16Ch)); + SET_REG16_BIT(DACx->DACR, u16Cmd); + } + + return i32Ret; +} + +/** + * @brief Stop the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_MD: cannot stop single channel when \n + * this channel is started by \n + * @ref DAC_StartDualCh + */ +int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_OK; + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if ((DACx->DACR & DAC_DACR_DAEN) != 0U) { + i32Ret = LL_ERR_INVD_MD; + } else { + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1EN_POS + u16Ch)); + CLR_REG16_BIT(DACx->DACR, u16Cmd); + } + + return i32Ret; +} + +/** + * @brief Start DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval None + */ +void DAC_StartDualCh(CM_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + SET_REG16_BIT(DACx->DACR, DAC_DACR_DAEN); +} + +/** + * @brief Stop DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval None + */ +void DAC_StopDualCh(CM_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + CLR_REG16_BIT(DACx->DACR, DAC_DACR_DAEN); +} + +/** + * @brief Set the specified data to the data holding register of specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] u16Data Data to be loaded into data holding register of specified channel + * @retval None + */ +void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data) +{ + __IO uint16_t *DADRx; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if (READ_REG16_BIT(DACx->DACR, DAC_DACR_ALIGN) == DAC_DATA_ALIGN_L) { + DDL_ASSERT(0U == (u16Data & 0xFU)); + } else { + DDL_ASSERT(0U == (u16Data & 0xF000U)); + } + + DADRx = (uint16_t *)((uint32_t) & (DACx->DADR1) + u16Ch * 2UL); + WRITE_REG16(*DADRx, u16Data); +} + +/** + * @brief Set the specified data to the data holding register of DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param u16Data1: Data to be loaded into data holding register of channel 1 + * @param u16Data2: Data to be loaded into data holding register of channel 2 + * @retval None + */ +void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2) +{ + uint32_t u32Data; + __IO uint32_t *u32DADRx; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if (READ_REG16_BIT(DACx->DACR, DAC_DACR_ALIGN) == DAC_DATA_ALIGN_L) { + DDL_ASSERT(0U == (u16Data1 & 0xFU)); + DDL_ASSERT(0U == (u16Data2 & 0xFU)); + } else { + DDL_ASSERT(0U == (u16Data1 & 0xF000U)); + DDL_ASSERT(0U == (u16Data2 & 0xF000U)); + } + + u32Data = ((uint32_t)u16Data2 << 16U) | u16Data1; + u32DADRx = (__IO uint32_t *)(uint32_t)(&DACx->DADR1); + WRITE_REG32(*u32DADRx, u32Data); +} + +/** + * @brief Get convert status of specified channel in ADC priority mode + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_ERR_INVD_MD: Could not get convert status when adc priority is not enabled + * - LL_OK: Data convert completed + * - LL_ERR_BUSY: Data convert is ongoing + */ +int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_ERR_INVD_MD; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if (0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN)) { + i32Ret = LL_ERR_BUSY; + + if (READ_REG16_BIT(DACx->DAADPCR, (DAC_DAADPCR_DA1SF << u16Ch)) == 0U) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Fills each pstcDacInit member with its default value + * @param [in] pstcDacInit pointer to a stc_dac_init_t structure which will + * be initialized. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDacInit is NULL + */ +int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcDacInit != NULL) { + pstcDacInit->u16Src = DAC_DATA_SRC_DATAREG; + pstcDacInit->enOutput = ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the DAC peripheral according to the specified parameters + * in the stc_dac_init_t + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify the DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH or DAC_CH_x + * @param [in] pstcDacInit pointer to a stc_dac_init_t structure that contains + * the configuration information for the specified DAC channel. + * @retval int32_t: + * - LL_OK: Initialize successfully + * - LL_ERR_INVD_PARAM: pstcDacInit is NULL + */ +int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcDacInit != NULL) { + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_VALID_DATA_SRC(pstcDacInit->u16Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDacInit->enOutput)); + + DAC_SetDataSrc(DACx, u16Ch, pstcDacInit->u16Src); + DAC_OutputCmd(DACx, u16Ch, pstcDacInit->enOutput); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval None + */ +void DAC_DeInit(CM_DAC_TypeDef *DACx) +{ + __IO uint32_t *u32DADRx; + + WRITE_REG16(DACx->DACR, 0x0000UL); + WRITE_REG16(DACx->DAOCR, 0x0000UL); + WRITE_REG16(DACx->DAADPCR, 0x0000UL); + u32DADRx = (__IO uint32_t *)(uint32_t)(&DACx->DADR1); + WRITE_REG32(*u32DADRx, 0x0000UL); +} + +/** + * @} + */ + +#endif /* LL_DAC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c new file mode 100644 index 0000000000..5edea225ed --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c @@ -0,0 +1,605 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.c + * @brief This file provides firmware functions to manage the DCU(Data Computing + * Unit). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dcu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DCU DCU + * @brief DCU Driver Library + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Local_Macros DCU Local Macros + * @{ + */ + +/** + * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity + * @{ + */ + +#define IS_DCU_WAVE_FUNC_UNIT(x) \ +( ((x) == CM_DCU1) || \ + ((x) == CM_DCU2) || \ + ((x) == CM_DCU3) || \ + ((x) == CM_DCU4)) + +#define IS_DCU_BASE_FUNC_UNIT(x) \ +( ((x) == CM_DCU5) || \ + ((x) == CM_DCU6) || \ + ((x) == CM_DCU7) || \ + ((x) == CM_DCU8)) + +#define IS_DCU_UNIT(x) \ +( (IS_DCU_BASE_FUNC_UNIT(x)) || \ + (IS_DCU_WAVE_FUNC_UNIT(x))) + +#define IS_DCU_BASE_FUNC_UNIT_MD(x) \ +( ((x) == DCU_MD_CMP) || \ + ((x) == DCU_MD_ADD) || \ + ((x) == DCU_MD_SUB) || \ + ((x) == DCU_MD_HW_ADD) || \ + ((x) == DCU_MD_HW_SUB) || \ + ((x) == DCU_MD_INVD)) + +#define IS_DCU_WAVE_FUNC_UNIT_MD(x) \ +( IS_DCU_BASE_FUNC_UNIT_MD(x) || \ + ((x) == DCU_MD_TRIANGLE_WAVE) || \ + ((x) == DCU_MD_SAWTOOTH_WAVE_DEC) || \ + ((x) == DCU_MD_SAWTOOTH_WAVE_INC)) + +#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_WAVE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_WAVE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_CMP_COND(x) \ +( ((x) == DCU_CMP_TRIG_DATA0) || \ + ((x) == DCU_CMP_TRIG_DATA0_DATA1_DATA2)) + +#define IS_DCU_DATA_WIDTH(x) \ +( ((x) == DCU_DATA_WIDTH_8BIT) || \ + ((x) == DCU_DATA_WIDTH_16BIT) || \ + ((x) == DCU_DATA_WIDTH_32BIT)) + +#define IS_DCU_INT_CATEGORY(x) \ +( ((x) == DCU_CATEGORY_OP) || \ + ((x) == DCU_CATEGORY_CMP_WIN) || \ + ((x) == DCU_CATEGORY_CMP_NON_WIN) || \ + ((x) == DCU_CATEGORY_WAVE)) + +#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_CARRY) + +#define IS_DCU_INT_CMP_WIN(x) \ +( ((x) == DCU_INT_CMP_WIN_INSIDE) || \ + ((x) == DCU_INT_CMP_WIN_OUTSIDE)) + +#define IS_DCU_INT_CMP_NON_WIN(x) \ +( ((x) != 0UL) || \ + (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL)) + +#define IS_DCU_INT_WAVE_MD(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL)) + +#define IS_DCU_DATA_REG(x) \ +( ((x) == DCU_DATA0_IDX) || \ + ((x) == DCU_DATA1_IDX) || \ + ((x) == DCU_DATA2_IDX)) + +#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL) +/** + * @} + */ + +/** + * @defgroup DCU_Flag_Mask DCU Flag Mask + * @{ + */ +#define DCU_BASE_FUNC_UNIT_FLAG_MASK (0x0E7FUL) +#define DCU_WAVE_FUNC_UNIT_FLAG_MASK (DCU_BASE_FUNC_UNIT_FLAG_MASK | 0x0E00UL) +/** + * @} + */ + +/** + * @defgroup DCU_DATA1_Limit_Position DCU_DATA1 Limit Position + * @{ + */ +#define DCU_DATA1_LOWER_LIMIT_POS (0UL) +#define DCU_DATA1_UPPER_LIMIT_POS (16UL) +/** + * @} + */ + +/** + * @defgroup DCU_Register_Address DCU Register Address + * @{ + */ +#define DCU_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define DCU_DATA_REG_ADDR(_UNITx_, _IDX_) (DCU_REG_ADDR((_UNITx_)->DATA0) + ((_IDX_) << 2UL)) + +#define DCU_DATA_REG8(_UNITx_, _IDX_) (*(__IO uint8_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG16(_UNITx_, _IDX_) (*(__IO uint16_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG32(_UNITx_, _IDX_) (*(__IO uint32_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Functions DCU Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_dcu_init_t to default values. + * @param [out] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + pstcDcuInit->u32Mode = DCU_MD_INVD; + pstcDcuInit->u32DataWidth = DCU_DATA_WIDTH_8BIT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MD(pstcDcuInit->u32Mode)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(pstcDcuInit->u32Mode))); + DDL_ASSERT(IS_DCU_DATA_WIDTH(pstcDcuInit->u32DataWidth)); + + /* Set register: CTL */ + WRITE_REG32(DCUx->CTL, (pstcDcuInit->u32Mode | pstcDcuInit->u32DataWidth)); + + /* Disable interrupt */ + WRITE_REG32(DCUx->INTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @retval None + */ +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(DCUx->CTL, 0x00000000UL); + WRITE_REG32(DCUx->INTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + return LL_OK; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcWaveconfig Pointer to a @ref stc_dcu_wave_config_t structure (DCU wave function configuration data structure). + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcWaveconfig value is NULL. + */ +int32_t DCU_WaveConfig(CM_DCU_TypeDef *DCUx, const stc_dcu_wave_config_t *pstcWaveconfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcWaveconfig) { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_WAVE_LOWER_LIMIT(pstcWaveconfig->u32LowerLimit)); + DDL_ASSERT(IS_DCU_WAVE_UPPER_LIMIT(pstcWaveconfig->u32UpperLimit)); + DDL_ASSERT(IS_DCU_WAVE_STEP(pstcWaveconfig->u32Step)); + + WRITE_REG32(DCUx->DATA0, 0x00000000UL); + WRITE_REG32(DCUx->DATA1, ((pstcWaveconfig->u32LowerLimit << DCU_DATA1_LOWER_LIMIT_POS) | \ + (pstcWaveconfig->u32UpperLimit << DCU_DATA1_UPPER_LIMIT_POS))); + WRITE_REG32(DCUx->DATA2, pstcWaveconfig->u32Step); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Mode DCU mode + * This parameter can be one of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode) +{ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MD(u32Mode)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(u32Mode))); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode); +} + +/** + * @brief Set DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataWidth DCU data width + * This parameter can be one of the macros group @ref DCU_Data_Width + * @arg DCU_DATA_WIDTH_8BIT: DCU data size 8 bit + * @arg DCU_DATA_WIDTH_16BIT: DCU data size 16 bit + * @arg DCU_DATA_WIDTH_32BIT: DCU data size 32 bit + * @retval None + */ +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataWidth); +} + +/** + * @brief Set DCU compare trigger condition. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Cond DCU compare trigger condition + * This parameter can be one of the macros group @ref DCU_Compare_Trigger_Condition + * @arg DCU_CMP_TRIG_DATA0: DCU compare triggered by DATA0. + * @arg DCU_CMP_TRIG_DATA0_DATA1_DATA2: DCU compare triggered by DATA0 or DATA1 or DATA2. + * @retval None + */ +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_CMP_COND(u32Cond)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_COMP_TRG, u32Cond); +} + +/** + * @brief Get DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag))); + + return (0UL == READ_REG32_BIT(DCUx->FLAG, u32Flag)) ? RESET : SET; +} + +/** + * @brief Clear DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag))); + + WRITE_REG32(DCUx->FLAGCLR, u32Flag); +} + +/** + * @brief Enable or disable DCU interupt function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } else { + CLR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } +} + +/** + * @brief Enable/disable DCU the specified interrupt source. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32IntCategory DCU interrupt categorye + * This parameter can be one of the macros group @ref DCU_Category. + * @param [in] u32IntType DCU interrupt type + * This parameter can be one of the following case: + * a. this parameter can be one of the macros group @ref DCU_Operation_Interrupt when u32Category = DCU_CATEGORY_OP. + * b. this parameter can be one of the macros group @ref DCU_Window_Compare_Interrupt when u32Category = DCU_CATEGORY_CMP_WIN. + * c. this parameter can be one of the macros group @ref DCU_Compare_Interrupt when u32Category = DCU_CATEGORY_CMP_NON_WIN. + * d. this parameter can be one of the macros group @ref DCU_Wave_Mode_Interrupt when u32Category = DCU_CATEGORY_WAVE. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DCU_CATEGORY_OP == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_OP(u32IntType)); + u32Type = (u32IntType & DCU_INT_OP_CARRY); + } else if (DCU_CATEGORY_CMP_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL); + } else if (DCU_CATEGORY_CMP_NON_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL); + } else { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_WAVE_MD(u32IntType)); + u32Type = (u32IntType & DCU_INT_WAVE_MD_ALL); + } + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->INTSEL, u32Type); + } else { + CLR_REG32_BIT(DCUx->INTSEL, u32Type); + } +} + +/** + * @brief Read DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for byte + */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG8(DCU_DATA_REG8(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u8Data The data to write. + * @retval None + */ +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data) +{ + __IO uint8_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG8(DCUx, u32DataIndex); + WRITE_REG8(*DATA, u8Data); +} + +/** + * @brief Read DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for half-word + */ +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG16(DCU_DATA_REG16(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u16Data The data to write. + * @retval None + */ +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data) +{ + __IO uint16_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG16(DCUx, u32DataIndex); + WRITE_REG16(*DATA, u16Data); +} + +/** + * @brief Read DCU register DATA for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for word + */ +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG32(DCU_DATA_REG32(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA0 for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u32Data The data to write. + * @retval None + */ +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data) +{ + __IO uint32_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG32(DCUx, u32DataIndex); + WRITE_REG32(*DATA, u32Data); +} + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c new file mode 100644 index 0000000000..472c4fd914 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c @@ -0,0 +1,1196 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.c + * @brief This file provides firmware functions to manage the Direct Memory + * Access (DMA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dma.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DMA DMA + * @brief Direct Memory Access Driver Library + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Local_Macros DMA Local Macros + * @{ + */ +#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +/** + * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity + * @{ + */ +/* Parameter valid check for DMA unit. */ +#define IS_DMA_UNIT(x) \ +( ((x) == CM_DMA1) || \ + ((x) == CM_DMA2)) + +/* Parameter valid check for DMA channel. */ +#define IS_DMA_CH(x) ((x) <= DMA_CH7) + +/* Parameter valid check for DMA multiplex channel. */ +#define IS_DMA_MX_CH(x) \ +( ((x) != 0x00UL) && \ + (((x) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL)) + +/* Parameter valid check for DMA block size. */ +#define IS_DMA_BLOCK_SIZE(x) ((x) < 1024U) + +/* Parameter valid check for DMA non-sequence transfer count. */ +#define IS_DMA_NON_SEQ_TRANS_CNT(x) ((x) < 4096U) + +/* Parameter valid check for DMA non-sequence offset. */ +#define IS_DMA_NON_SEQ_OFFSET(x) ((x) <= ((1UL << 20U) - 1UL)) + +/* Parameter valid check for DMA LLP function. */ +#define IS_DMA_LLP_EN(x) \ +( ((x) == DMA_LLP_ENABLE) || \ + ((x) == DMA_LLP_DISABLE)) + +/* Parameter valid check for DMA linked-list-pointer mode. */ +#define IS_DMA_LLP_MD(x) \ +( ((x) == DMA_LLP_RUN) || \ + ((x) == DMA_LLP_WAIT)) + +/* Parameter valid check for DMA error flag. */ +#define IS_DMA_ERR_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_ERR_MASK) == DMA_FLAG_ERR_MASK)) + +/* Parameter valid check for DMA transfer flag. */ +#define IS_DMA_TRANS_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_TRANS_MASK) == DMA_FLAG_TRANS_MASK)) + +/* Parameter valid check for DMA error interrupt. */ +#define IS_DMA_ERR_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_ERR_MASK) == DMA_INT_ERR_MASK)) + +/* Parameter valid check for DMA transfer interrupt. */ +#define IS_DMA_TRANS_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_TRANS_MASK) == DMA_INT_TRANS_MASK)) + +/* Parameter valid check for DMA request status. */ +#define IS_DMA_REQ_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_REQ_MASK) == DMA_STAT_REQ_MASK)) + +/* Parameter valid check for DMA channel status. */ +#define IS_DMA_TRANS_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_TRANS_MASK) == DMA_STAT_TRANS_MASK)) + +/* Parameter valid check for DMA transfer data width. */ +#define IS_DMA_DATA_WIDTH(x) \ +( ((x) == DMA_DATAWIDTH_8BIT) || \ + ((x) == DMA_DATAWIDTH_16BIT) || \ + ((x) == DMA_DATAWIDTH_32BIT)) + +/* Parameter valid check for DMA source address mode. */ +#define IS_DMA_SADDR_MD(x) \ +( ((x) == DMA_SRC_ADDR_FIX) || \ + ((x) == DMA_SRC_ADDR_INC) || \ + ((x) == DMA_SRC_ADDR_DEC)) + +/* Parameter valid check for DMA destination address mode. */ +#define IS_DMA_DADDR_MD(x) \ +( ((x) == DMA_DEST_ADDR_FIX) || \ + ((x) == DMA_DEST_ADDR_INC) || \ + ((x) == DMA_DEST_ADDR_DEC)) + +/* Parameter valid check for DMA repeat mode. */ +#define IS_DMA_RPT_MD(x) \ +( ((x) == DMA_RPT_NONE) || \ + ((x) == DMA_RPT_SRC) || \ + ((x) == DMA_RPT_DEST) || \ + ((x) == DMA_RPT_BOTH)) + +/* Parameter valid check for DMA non_sequence mode. */ +#define IS_DMA_NON_SEQ_MD(x) \ +( ((x) == DMA_NON_SEQ_NONE) || \ + ((x) == DMA_NON_SEQ_SRC) || \ + ((x) == DMA_NON_SEQ_DEST) || \ + ((x) == DMA_NON_SEQ_BOTH)) + +/* Parameter valid check for DMA global interrupt function. */ +#define IS_DMA_INT_FUNC(x) \ +( ((x) == DMA_INT_ENABLE) || \ + ((x) == DMA_INT_DISABLE)) + +/* Parameter valid check for DMA reconfig count mode. */ +#define IS_DMA_RC_CNT_MD(x) \ +( ((x) == DMA_RC_CNT_KEEP) || \ + ((x) == DMA_RC_CNT_SRC) || \ + ((x) == DMA_RC_CNT_DEST)) + +/* Parameter valid check for DMA reconfig destination address mode. */ +#define IS_DMA_RC_DA_MD(x) \ +( ((x) == DMA_RC_DEST_ADDR_KEEP) || \ + ((x) == DMA_RC_DEST_ADDR_NS) || \ + ((x) == DMA_RC_DEST_ADDR_RPT)) + +/* Parameter valid check for DMA reconfig source address mode. */ +#define IS_DMA_RC_SA_MD(x) \ +( ((x) == DMA_RC_SRC_ADDR_KEEP) || \ + ((x) == DMA_RC_SRC_ADDR_NS) || \ + ((x) == DMA_RC_SRC_ADDR_RPT)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Functions DMA Global Functions + * @{ + */ + +/** + * @brief DMA global function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Global setting, ENABLE or DISABLE DMA */ + WRITE_REG32(DMAx->EN, enNewState); +} + +/** + * @brief DMA error IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32ErrInt DMA error IRQ flag. @ref DMA_Int_Request_Err_Sel, @ref DMA_Int_Trans_Err_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } +} + +/** + * @brief Get DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer error flag & request error flag + */ +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + return (0U != READ_REG32_BIT(DMAx->INTSTAT0, u32Flag) ? SET : RESET); +} + +/** + * @brief Clear DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval None + * @note Include transfer error flag & request error flag + */ +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR0, u32Flag); +} + +/** + * @brief DMA transfer IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32TransCompleteInt DMA transfer complete IRQ flag. @ref DMA_Int_Btc_Sel, @ref DMA_Int_Tc_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransCompleteInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } +} + +/** + * @brief Get DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer IRQ flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer complete flag & block transfer complete flag + */ +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + return ((0U != READ_REG32_BIT(DMAx->INTSTAT1, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer complete flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval None + * @note Include transfer complete flag & block transfer complete flag + */ +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR1, u32Flag); +} + +/** + * @brief DMA multiplex channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8MxCh DMA multiplex channel. @ref DMA_Mx_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_MX_CH(u8MxCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(DMAx->CHEN, u8MxCh); + } else { + WRITE_REG32(DMAx->CHENCLR, u8MxCh); + } +} + +/** + * @brief DMA channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t + */ +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(DMAx->CHEN, ((1UL << u8Ch) & DMA_CHEN_CHEN)); + } else { + WRITE_REG32(DMAx->CHENCLR, ((1UL << u8Ch) & DMA_CHENCLR_CHENCLR)); + } + + return LL_OK; +} + +/** + * @brief Get DMA transfer status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA transfer status. @ref DMA_Trans_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->CHSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Get DMA request status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA request status. @ref DMA_Req_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_REQ_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->REQSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Config DMA source address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA source address. + * @retval int32_t + */ +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + + return LL_OK; +} + +/** + * @brief Config DMA destination address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA destination address. + * @retval int32_t + */ +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + + return LL_OK; +} + +/** + * @brief Config DMA transfer count. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Count DMA transfer count (0: infinite, 1 ~ 65535). + * @retval int32_t + */ +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + return LL_OK; +} + +/** + * @brief Config DMA block size per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA block size (range: 1~1024, 0 is for 1024). + * @retval int32_t + */ +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + + return LL_OK; +} + +/** + * @brief Config DMA source repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA destination repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA source transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA source transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA destination transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA destination transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA source offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA source offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + + return LL_OK; +} + +/** + * @brief Config DMA destination offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA destination offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + + return LL_OK; +} + +/** + * @brief De-Initialize DMA function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval None + */ +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + /* Disable */ + SET_REG32_BIT(DMAx->CHENCLR, DMA_CHENCLR_CHENCLR << u8Ch); + + /* Set default value. */ + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), 0UL); + WRITE_REG32(DMAx->INTMASK0, 0UL); + WRITE_REG32(DMAx->INTMASK1, 0UL); + WRITE_REG32(DMAx->INTCLR0, DMA_INTCLR0_CLRTRNERR | DMA_INTCLR0_CLRREQERR); + WRITE_REG32(DMAx->INTCLR1, DMA_INTCLR1_CLRTC | DMA_INTCLR1_CLRBTC); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), 1UL); + WRITE_REG32(DMA_CH_REG(DMAx->CHCTL0, u8Ch), 0x00001000UL); + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), 0UL); + +} + +/** + * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value + * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaInit->u32IntEn = DMA_INT_DISABLE; + pstcDmaInit->u32SrcAddr = 0x00UL; + pstcDmaInit->u32DestAddr = 0x00UL; + pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT; + pstcDmaInit->u32BlockSize = 0x00UL; + pstcDmaInit->u32TransCount = 0x01UL; + pstcDmaInit->u32SrcAddrInc = DMA_SRC_ADDR_FIX; + pstcDmaInit->u32DestAddrInc = DMA_DEST_ADDR_FIX; + } + return i32Ret; +} + +/** + * @brief DMA basic function initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaInit DMA config structure. + * @arg u32IntEn DMA interrupt ENABLE or DISABLE. + * @arg u32SrcAddr DMA source address. + * @arg u32DestAddr DMA destination address. + * @arg u32DataWidth DMA data width. + * @arg u32BlockSize DMA block size. + * @arg u32TransCount DMA transfer count. + * @arg u32SrcAddrInc DMA source address direction. + * @arg u32DestAddrInc DMA destination address direction. + * @retval int32_t: + * - LL_OK: DMA basic function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth)); + DDL_ASSERT(IS_DMA_SADDR_MD(pstcDmaInit->u32SrcAddrInc)); + DDL_ASSERT(IS_DMA_DADDR_MD(pstcDmaInit->u32DestAddrInc)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaInit->u32BlockSize)); + DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), \ + (pstcDmaInit->u32BlockSize | (pstcDmaInit->u32TransCount << DMA_DTCTL_CNT_POS))); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \ + (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | pstcDmaInit->u32SrcAddrInc | \ + pstcDmaInit->u32DestAddrInc)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA repeat mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRepeatInit Pointer to a stc_dma_repeat_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA repeat mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRepeatInit->u32Mode = DMA_RPT_NONE; + pstcDmaRepeatInit->u32SrcCount = 0x00UL; + pstcDmaRepeatInit->u32DestCount = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA repeat mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRepeatInit DMA repeat mode config structure. + * @note Call this function after DMA_Init(); + */ +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RPT_MD(pstcDmaRepeatInit->u32Mode)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32DestCount)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32SrcCount)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN), pstcDmaRepeatInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \ + ((pstcDmaRepeatInit->u32DestCount << DMA_RPT_DRPT_POS) | pstcDmaRepeatInit->u32SrcCount)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaNonSeqInit->u32Mode = DMA_NON_SEQ_NONE; + pstcDmaNonSeqInit->u32SrcCount = 0x00UL; + pstcDmaNonSeqInit->u32SrcOffset = 0x00UL; + pstcDmaNonSeqInit->u32DestCount = 0x00UL; + pstcDmaNonSeqInit->u32DestOffset = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure. + * @retval int32_t: + * - LL_OK: DMA non-sequence function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaNonSeqInit->u32Mode)); + + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32SrcCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32DestCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32SrcOffset)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32DestOffset)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaNonSeqInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32SrcCount << DMA_SNSEQCTL_SNSCNT_POS) | \ + pstcDmaNonSeqInit->u32SrcOffset)); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32DestCount << DMA_DNSEQCTL_DNSCNT_POS) | \ + pstcDmaNonSeqInit->u32DestOffset)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA LLP mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaLlpInit->u32State = DMA_LLP_DISABLE; + pstcDmaLlpInit->u32Mode = DMA_LLP_WAIT; + pstcDmaLlpInit->u32Addr = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA LLP mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaLlpInit DMA LLP config structure. + * @arg u32State DMA LLP ENABLE or DISABLE. + * @arg u32Mode DMA LLP auto-run or wait request. + * @arg u32Addr DMA LLP next list pointer address. + * @arg u32AddrSelect DMA LLP address mode. + * @retval int32_t: + * - LL_OK: DMA LLP function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32State)); + DDL_ASSERT(IS_DMA_LLP_MD(pstcDmaLlpInit->u32Mode)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \ + (pstcDmaLlpInit->u32State | pstcDmaLlpInit->u32Mode)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32Addr & DMA_LLP_LLP); + + } + + return i32Ret; +} + +/** + * @brief Config DMA LLP value. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr Next link pointer address for DMA LLP mode. + * @retval None + */ +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32Addr & DMA_LLP_LLP)); +} + +/** + * @brief DMA LLP ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } else { + CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } +} + +/** + * @brief DMA reconfig function ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMAx->RCFGCTL, 1UL); + } else { + CLR_REG32_BIT(DMAx->RCFGCTL, 1UL); + } +} + +/** + * @brief DMA LLP ENABLE or DISABLE for reconfig function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_RCFGLLP, \ + ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS) | ((uint32_t)enNewState << DMA_RCFGCTL_RCFGLLP_POS)); +} + +/** + * @brief Initialize DMA re-config mode config structure. + * Fill each pstcDmaRCInit with default value + * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA reconfig mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRCInit->u32CountMode = DMA_RC_CNT_KEEP; + pstcDmaRCInit->u32DestAddrMode = DMA_RC_DEST_ADDR_KEEP; + pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SRC_ADDR_KEEP; + } + return i32Ret; +} + +/** + * @brief DMA reconfig mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRCInit DMA reconfig mode config structure + * @arg u32CountMode DMA reconfig count mode. + * @arg u32DestAddrMode DMA reconfig destination address mode. + * @arg u32SrcAddrMode DMA reconfig source address mode. + * @retval int32_t: + * - LL_OK: DMA reconfig function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer +*/ +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RC_CNT_MD(pstcDmaRCInit->u32CountMode)); + DDL_ASSERT(IS_DMA_RC_DA_MD(pstcDmaRCInit->u32DestAddrMode)); + DDL_ASSERT(IS_DMA_RC_SA_MD(pstcDmaRCInit->u32SrcAddrMode)); + + MODIFY_REG32(DMAx->RCFGCTL, \ + (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | DMA_RCFGCTL_CNTMD), \ + (pstcDmaRCInit->u32CountMode | pstcDmaRCInit->u32SrcAddrMode | \ + pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS))); + } + return i32Ret; +} + +/** + * @brief DMA get current source address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source address. + */ +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch)); +} + +/** + * @brief DMA get current destination address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination address. + */ +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch)); +} + +/** + * @brief DMA get current transfer count + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current transfer count. + */ +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL); +} + +/** + * @brief DMA get current block size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current block size. + */ +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE)); +} + +/** + * @brief DMA get current source repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source repeat size. + */ +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT)); +} + +/** + * @brief DMA get current destination repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination repeat size. + */ +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL); +} + +/** + * @brief DMA get current source count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current destination count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA,, x can be 0-1 + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current source offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET)); +} + +/** + * @brief DMA get current destination offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET)); +} + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dmc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dmc.c new file mode 100644 index 0000000000..a75932d82e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dmc.c @@ -0,0 +1,565 @@ +/** + ******************************************************************************* + * @file hc32_ll_dmc.c + * @brief This file provides firmware functions to manage the EXMC_DMC + * (External Memory Controller: Dynamic Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dmc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EXMC EXMC + * @brief External Memory Controller Driver Library + * @{ + */ + +/** + * @defgroup LL_DMC DMC + * @brief Dynamic Memory Controller Driver Library + * @{ + */ + +#if (LL_DMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Local_Macros EXMC_DMC Local Macros + * @{ + */ + +/** + * @defgroup EXMC_DMC_Check_Parameters_Validity EXMC_DMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_DMC_MEM_WIDTH(x) \ +( ((x) == EXMC_DMC_MEMORY_WIDTH_16BIT) || \ + ((x) == EXMC_DMC_MEMORY_WIDTH_32BIT)) + +#define IS_EXMC_DMC_CHIP(x) \ +( ((x) == EXMC_DMC_CHIP0) || \ + ((x) == EXMC_DMC_CHIP1) || \ + ((x) == EXMC_DMC_CHIP2) || \ + ((x) == EXMC_DMC_CHIP3)) + +#define IS_EXMC_DMC_BANK(x) \ +( ((x) == EXMC_DMC_BANK0) || \ + ((x) == EXMC_DMC_BANK1) || \ + ((x) == EXMC_DMC_BANK2) || \ + ((x) == EXMC_DMC_BANK3)) + +#define IS_EXMC_DMC_CMD(x) \ +( ((x) == EXMC_DMC_CMD_PRECHARGE_ALL) || \ + ((x) == EXMC_DMC_CMD_AUTO_REFRESH) || \ + ((x) == EXMC_DMC_CMD_MDREG_CONFIG) || \ + ((x) == EXMC_DMC_CMD_NOP)) + +#define IS_EXMC_DMC_CS_DECODE_MD(x) \ +( ((x) == EXMC_DMC_CS_DECODE_ROWBANKCOL) || \ + ((x) == EXMC_DMC_CS_DECODE_BANKROWCOL)) + +#define IS_EXMC_DMC_COLUMN_BITS_NUM(x) \ +( ((x) == EXMC_DMC_COLUMN_BITS_NUM8) || \ + ((x) == EXMC_DMC_COLUMN_BITS_NUM9) || \ + ((x) == EXMC_DMC_COLUMN_BITS_NUM10) || \ + ((x) == EXMC_DMC_COLUMN_BITS_NUM11) || \ + ((x) == EXMC_DMC_COLUMN_BITS_NUM12)) + +#define IS_EXMC_DMC_ROW_BITS_NUM(x) \ +( ((x) == EXMC_DMC_ROW_BITS_NUM11) || \ + ((x) == EXMC_DMC_ROW_BITS_NUM12) || \ + ((x) == EXMC_DMC_ROW_BITS_NUM13) || \ + ((x) == EXMC_DMC_ROW_BITS_NUM14) || \ + ((x) == EXMC_DMC_ROW_BITS_NUM15) || \ + ((x) == EXMC_DMC_ROW_BITS_NUM16)) + +#define IS_EXMC_DMC_AUTO_PRECHARGE_PIN(x) \ +( ((x) == EXMC_DMC_AUTO_PRECHARGE_A8) || \ + ((x) == EXMC_DMC_AUTO_PRECHARGE_A10)) + +#define IS_EXMC_DMC_CKE_OUTPUT_SEL(x) \ +( ((x) == EXMC_DMC_CKE_OUTPUT_ENABLE) || \ + ((x) == EXMC_DMC_CKE_OUTPUT_DISABLE)) + +#define EXMC_DMC_CLK_SEL(x) \ +( ((x) == EXMC_DMC_CLK_NORMAL_OUTPUT) || \ + ((x) == EXMC_DMC_CLK_NOP_STOP_OUTPUT)) + +#define IS_EXMC_DMC_BURST(x) \ +( ((x) == EXMC_DMC_BURST_1BEAT) || \ + ((x) == EXMC_DMC_BURST_2BEAT) || \ + ((x) == EXMC_DMC_BURST_4BEAT) || \ + ((x) == EXMC_DMC_BURST_8BEAT) || \ + ((x) == EXMC_DMC_BURST_16BEAT)) + +#define IS_EXMC_DMC_AUTO_REFRESH_CHIPS(x) \ +( ((x) == EXMC_DMC_AUTO_REFRESH_1CHIP) || \ + ((x) == EXMC_DMC_AUTO_REFRESH_2CHIPS) || \ + ((x) == EXMC_DMC_AUTO_REFRESH_3CHIPS) || \ + ((x) == EXMC_DMC_AUTO_REFRESH_4CHIPS)) + +#define IS_EXMC_DMC_MAP_ADDR(match, msk) \ +( (EXMC_DMC_MAP_ADDR((match), (msk)) >= EXMC_DMC_ADDR_MIN) && \ + (EXMC_DMC_MAP_ADDR((match), (msk)) <= EXMC_DMC_ADDR_MAX)) + +#define IS_EXMC_DMC_STATE(x) \ +( ((x) == EXMC_DMC_CTRL_STATE_GO) || \ + ((x) == EXMC_DMC_CTRL_STATE_SLEEP) || \ + ((x) == EXMC_DMC_CTRL_STATE_WAKEUP) || \ + ((x) == EXMC_DMC_CTRL_STATE_PAUSE) || \ + ((x) == EXMC_DMC_CTRL_STATE_CONFIG)) + +#define IS_EXMC_DMC_SAMPLE_CLK(x) \ +( ((x) == EXMC_DMC_SAMPLE_CLK_EXTCLK) || \ + ((x) == EXMC_DMC_SAMPLE_CLK_INTERNCLK) || \ + ((x) == EXMC_DMC_SAMPLE_CLK_INTERNCLK_INVT)) + +#define IS_EXMC_DMC_TIMING_CASL_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_DQSS_CYCLE(x) ((x) <= 3UL) + +#define IS_EXMC_DMC_TIMING_MRD_CYCLE(x) ((x) <= 0x7FUL) + +#define IS_EXMC_DMC_TIMING_RAS_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_RCD_B_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RCD_P_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RFC_B_CYCLE(x) ((x) <= 0x1FUL) + +#define IS_EXMC_DMC_TIMING_RFC_P_CYCLE(x) ((x) <= 0x1FUL) + +#define IS_EXMC_DMC_TIMING_RP_B_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RP_P_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RRD_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_WR_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_WTR_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_CKE_DISABLE_PERIOD(x) ((x) <= 0x3FUL) + +#define IS_EXMC_DMC_CMD_ADDR(x) ((x) <= 0x7FFFUL) + +#define IS_EXMC_DMC_REFRESH_PERIOD(x) ((x) <= 0x7FFFUL) + +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Register EXMC_DMC Register + * @{ + */ +#define EXMC_DMC_CSCRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_DMC->CSCR0)) + (4UL * (__CHIPx__)))) +/** + * @} + */ + +/* EXMC_DMC map address */ +#define EXMC_DMC_MAP_ADDR(MATCH, MSK) ((~((MATCH) ^ (MSK))) << 24U) + +/** + * @defgroup EXMC_DMC_Timing EXMC_DMC Timing + * @{ + */ +#define DMC_TMCR_RP_MASK (DMC_TMCR_T_RP_T_RP_B | DMC_TMCR_T_RP_T_RP_P) +#define DMC_TMCR_RCD_MASK (DMC_TMCR_T_RCD_T_RCD_B | DMC_TMCR_T_RCD_T_RCD_P) +#define DMC_TMCR_RFC_MASK (DMC_TMCR_T_RFC_T_RFC_B | DMC_TMCR_T_RFC_T_RFC_P) + +#define DMC_TMCR_RP(x) \ +((uint32_t)(x)->stcTimingConfig.u8RP_B | ((uint32_t)(x)->stcTimingConfig.u8RP_P << DMC_TMCR_T_RP_T_RP_P_POS)) + +#define DMC_TMCR_RCD(x) \ +((uint32_t)(x)->stcTimingConfig.u8RCD_B | ((uint32_t)(x)->stcTimingConfig.u8RCD_P << DMC_TMCR_T_RCD_T_RCD_P_POS)) + +#define DMC_TMCR_RFC(x) \ +((uint32_t)(x)->stcTimingConfig.u8RFC_B | ((uint32_t)(x)->stcTimingConfig.u8RFC_P << DMC_TMCR_T_RFC_T_RFC_P_POS)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Functions EXMC_DMC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_exmc_dmc_init_t to default values + * @param [out] pstcDmcInit Pointer to a @ref stc_exmc_dmc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDmcInit value is NULL. + */ +int32_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcDmcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDmcInit) { + pstcDmcInit->u32SampleClock = EXMC_DMC_SAMPLE_CLK_INTERNCLK; + pstcDmcInit->u32MemoryWidth = EXMC_DMC_MEMORY_WIDTH_16BIT; + pstcDmcInit->u32RefreshPeriod = 0xA60UL; + pstcDmcInit->u32ColumnBitsNumber = EXMC_DMC_COLUMN_BITS_NUM8; + pstcDmcInit->u32RowBitsNumber = EXMC_DMC_ROW_BITS_NUM15; + pstcDmcInit->u32AutoPrechargePin = EXMC_DMC_AUTO_PRECHARGE_A10; + pstcDmcInit->u32CkeOutputSel = EXMC_DMC_CKE_OUTPUT_ENABLE; + pstcDmcInit->u32MemClockSel = EXMC_DMC_CLK_NORMAL_OUTPUT; + pstcDmcInit->u32CkeDisablePeriod = 0UL; + pstcDmcInit->u32MemBurst = EXMC_DMC_BURST_4BEAT; + pstcDmcInit->u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_1CHIP; + + pstcDmcInit->stcTimingConfig.u8CASL = 0x3U; + pstcDmcInit->stcTimingConfig.u8DQSS = 0x1U; + pstcDmcInit->stcTimingConfig.u8MRD = 0x02U; + pstcDmcInit->stcTimingConfig.u8RAS = 0x07U; + pstcDmcInit->stcTimingConfig.u8RC = 0x0BU; + pstcDmcInit->stcTimingConfig.u8RCD_B = 0x05U; + pstcDmcInit->stcTimingConfig.u8RCD_P = 0x00U; + pstcDmcInit->stcTimingConfig.u8RFC_B = 0x12U; + pstcDmcInit->stcTimingConfig.u8RFC_P = 0x0U; + pstcDmcInit->stcTimingConfig.u8RP_B = 0x05U; + pstcDmcInit->stcTimingConfig.u8RP_P = 0x00U; + pstcDmcInit->stcTimingConfig.u8RRD = 0x02U; + pstcDmcInit->stcTimingConfig.u8WR = 0x03U; + pstcDmcInit->stcTimingConfig.u8WTR = 0x02U; + pstcDmcInit->stcTimingConfig.u8XP = 0x01U; + pstcDmcInit->stcTimingConfig.u8XSR = 0x0AU; + pstcDmcInit->stcTimingConfig.u8ESR = 0x14U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EXMC_DMC function. + * @param [in] pstcDmcInit Pointer to a @ref stc_exmc_dmc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDmcInit value is NULL. + */ +int32_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcDmcInit) +{ + uint32_t u32RegVal; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDmcInit) { + DDL_ASSERT(IS_EXMC_DMC_SAMPLE_CLK(pstcDmcInit->u32SampleClock)); + DDL_ASSERT(IS_EXMC_DMC_MEM_WIDTH(pstcDmcInit->u32MemoryWidth)); + DDL_ASSERT(IS_EXMC_DMC_REFRESH_PERIOD(pstcDmcInit->u32RefreshPeriod)); + DDL_ASSERT(IS_EXMC_DMC_COLUMN_BITS_NUM(pstcDmcInit->u32ColumnBitsNumber)); + DDL_ASSERT(IS_EXMC_DMC_ROW_BITS_NUM(pstcDmcInit->u32RowBitsNumber)); + DDL_ASSERT(IS_EXMC_DMC_AUTO_PRECHARGE_PIN(pstcDmcInit->u32AutoPrechargePin)); + DDL_ASSERT(IS_EXMC_DMC_CKE_OUTPUT_SEL(pstcDmcInit->u32CkeOutputSel)); + DDL_ASSERT(EXMC_DMC_CLK_SEL(pstcDmcInit->u32MemClockSel)); + DDL_ASSERT(IS_EXMC_DMC_CKE_DISABLE_PERIOD(pstcDmcInit->u32CkeDisablePeriod)); + DDL_ASSERT(IS_EXMC_DMC_BURST(pstcDmcInit->u32MemBurst)); + DDL_ASSERT(IS_EXMC_DMC_AUTO_REFRESH_CHIPS(pstcDmcInit->u32AutoRefreshChips)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_CASL_CYCLE(pstcDmcInit->stcTimingConfig.u8CASL)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_DQSS_CYCLE(pstcDmcInit->stcTimingConfig.u8DQSS)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_MRD_CYCLE(pstcDmcInit->stcTimingConfig.u8MRD)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RAS_CYCLE(pstcDmcInit->stcTimingConfig.u8RAS)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RC_CYCLE(pstcDmcInit->stcTimingConfig.u8RC)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RCD_B_CYCLE(pstcDmcInit->stcTimingConfig.u8RCD_B)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RCD_P_CYCLE(pstcDmcInit->stcTimingConfig.u8RCD_P)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RFC_B_CYCLE(pstcDmcInit->stcTimingConfig.u8RFC_B)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RFC_P_CYCLE(pstcDmcInit->stcTimingConfig.u8RFC_P)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RP_B_CYCLE(pstcDmcInit->stcTimingConfig.u8RP_B)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RP_P_CYCLE(pstcDmcInit->stcTimingConfig.u8RP_P)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RRD_CYCLE(pstcDmcInit->stcTimingConfig.u8RRD)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_WR_CYCLE(pstcDmcInit->stcTimingConfig.u8WR)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_WTR_CYCLE(pstcDmcInit->stcTimingConfig.u8WTR)); + + /* Set sample clock for DMC.*/ + MODIFY_REG32(CM_DMC->BACR, DMC_BACR_CKSEL, pstcDmcInit->u32SampleClock); + + /* Set memrory width(16bit or 32bit) for DMC.*/ + MODIFY_REG32(CM_DMC->BACR, DMC_BACR_DMCMW, pstcDmcInit->u32MemoryWidth); + + /* set auto refresh period*/ + WRITE_REG32(CM_DMC->RFTR, pstcDmcInit->u32RefreshPeriod); + + /* Set timing parameters for DMC.*/ + WRITE_REG32(CM_DMC->TMCR_T_CASL, pstcDmcInit->stcTimingConfig.u8CASL); + WRITE_REG32(CM_DMC->TMCR_T_DQSS, pstcDmcInit->stcTimingConfig.u8DQSS); + WRITE_REG32(CM_DMC->TMCR_T_MRD, pstcDmcInit->stcTimingConfig.u8MRD); + WRITE_REG32(CM_DMC->TMCR_T_RAS, pstcDmcInit->stcTimingConfig.u8RAS); + WRITE_REG32(CM_DMC->TMCR_T_RC, pstcDmcInit->stcTimingConfig.u8RC); + WRITE_REG32(CM_DMC->TMCR_T_RRD, pstcDmcInit->stcTimingConfig.u8RRD); + WRITE_REG32(CM_DMC->TMCR_T_WR, pstcDmcInit->stcTimingConfig.u8WR); + WRITE_REG32(CM_DMC->TMCR_T_WTR, pstcDmcInit->stcTimingConfig.u8WTR); + WRITE_REG32(CM_DMC->TMCR_T_XP, pstcDmcInit->stcTimingConfig.u8XP); + WRITE_REG32(CM_DMC->TMCR_T_XSR, pstcDmcInit->stcTimingConfig.u8XSR); + WRITE_REG32(CM_DMC->TMCR_T_ESR, pstcDmcInit->stcTimingConfig.u8ESR); + MODIFY_REG32(CM_DMC->TMCR_T_RP, DMC_TMCR_RP_MASK, DMC_TMCR_RP(pstcDmcInit)); + MODIFY_REG32(CM_DMC->TMCR_T_RCD, DMC_TMCR_RCD_MASK, DMC_TMCR_RCD(pstcDmcInit)); + MODIFY_REG32(CM_DMC->TMCR_T_RFC, DMC_TMCR_RFC_MASK, DMC_TMCR_RFC(pstcDmcInit)); + + /* Set base parameters for DMC: burst length, Rowbitwidth,ColbitWidth etc.*/ + u32RegVal = (pstcDmcInit->u32ColumnBitsNumber | pstcDmcInit->u32RowBitsNumber | \ + pstcDmcInit->u32AutoPrechargePin | pstcDmcInit->u32CkeOutputSel | \ + pstcDmcInit->u32AutoRefreshChips | pstcDmcInit->u32MemClockSel | \ + (pstcDmcInit->u32CkeDisablePeriod << DMC_CPCR_CKEDISPRD_POS) | \ + pstcDmcInit->u32MemBurst); + WRITE_REG32(CM_DMC->CPCR, u32RegVal); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EXMC_DMC function. + * @param None + * @retval None + */ +void EXMC_DMC_DeInit(void) +{ + /* Disable */ + CLR_REG32_BIT(CM_PERIC->DMC_ENAR, PERIC_DMC_ENAR_DMCEN); + + /* Configures the registers to reset value. */ + WRITE_REG32(CM_DMC->CPCR, 0x00020040UL); + + WRITE_REG32(CM_DMC->TMCR_T_CASL, 0x00000003UL); + WRITE_REG32(CM_DMC->TMCR_T_DQSS, 0x00000001UL); + WRITE_REG32(CM_DMC->TMCR_T_MRD, 0x00000002UL); + WRITE_REG32(CM_DMC->TMCR_T_RAS, 0x00000007UL); + WRITE_REG32(CM_DMC->TMCR_T_RC, 0x0000000BUL); + WRITE_REG32(CM_DMC->TMCR_T_RCD, 0x00000035UL); + WRITE_REG32(CM_DMC->TMCR_T_RFC, 0x00001012UL); + WRITE_REG32(CM_DMC->TMCR_T_RP, 0x00000035UL); + WRITE_REG32(CM_DMC->TMCR_T_RRD, 0x00000002UL); + WRITE_REG32(CM_DMC->TMCR_T_WR, 0x00000003UL); + WRITE_REG32(CM_DMC->TMCR_T_WTR, 0x00000002UL); + WRITE_REG32(CM_DMC->TMCR_T_XP, 0x00000001UL); + WRITE_REG32(CM_DMC->TMCR_T_XSR, 0x0000000AUL); + WRITE_REG32(CM_DMC->TMCR_T_ESR, 0x00000014UL); +} + +/** + * @brief Enable/disable DMC. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_DMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->DMC_ENAR, PERIC_DMC_ENAR_DMCEN); + } else { + CLR_REG32_BIT(CM_PERIC->DMC_ENAR, PERIC_DMC_ENAR_DMCEN); + } +} + +/** + * @brief Set EXMC_DMC state. + * @param [in] u32State The command chip number. + * This parameter can be one of the macros group @ref EXMC_DMC_Control_State + * @arg EXMC_DMC_CTRL_STATE_GO: Go + * @arg EXMC_DMC_CTRL_STATE_SLEEP: Sleep for low power + * @arg EXMC_DMC_CTRL_STATE_WAKEUP: Wake up + * @arg EXMC_DMC_CTRL_STATE_PAUSE: Pause + * @arg EXMC_DMC_CTRL_STATE_CONFIG: Configure + * @retval None + */ +void EXMC_DMC_SetState(uint32_t u32State) +{ + DDL_ASSERT(IS_EXMC_DMC_STATE(u32State)); + + WRITE_REG32(CM_DMC->STCR, u32State); +} + +/** + * @brief Configure EXMC_DMC CS function. + * @param [in] u32Chip The command chip number. + * This parameter can be one of the macros group @ref EXMC_DMC_Chip + * @arg EXMC_DMC_CHIP0: Chip 0 + * @arg EXMC_DMC_CHIP1: Chip 1 + * @arg EXMC_DMC_CHIP2: Chip 2 + * @arg EXMC_DMC_CHIP3: Chip 3 + * @param [in] pstcChipConfig Pointer to a @ref stc_exmc_dmc_chip_config_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcConfig value is NULL. + */ +int32_t EXMC_DMC_ChipConfig(uint32_t u32Chip, const stc_exmc_dmc_chip_config_t *pstcChipConfig) +{ + uint32_t u32RegVal; + __IO uint32_t *DMC_CSCRx; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcChipConfig) { + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_DMC_CS_DECODE_MD(pstcChipConfig->u32AddrDecodeMode)); + DDL_ASSERT(IS_EXMC_DMC_MAP_ADDR(pstcChipConfig->u32AddrMatch, pstcChipConfig->u32AddrMask)); + + /* Set chip selection for DMC.*/ + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + u32RegVal = ((pstcChipConfig->u32AddrMask << DMC_CSCR_ADDMSK_POS) | \ + (pstcChipConfig->u32AddrMatch << DMC_CSCR_ADDMAT_POS) | \ + pstcChipConfig->u32AddrDecodeMode); + WRITE_REG32(*DMC_CSCRx, u32RegVal); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get the start address of the specified DMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_DMC_Chip + * @arg EXMC_DMC_CHIP0: Chip 0 + * @arg EXMC_DMC_CHIP1: Chip 1 + * @arg EXMC_DMC_CHIP2: Chip 2 + * @arg EXMC_DMC_CHIP3: Chip 3 + * @retval The start address of the specified DMC chip. + */ +uint32_t EXMC_DMC_GetChipStartAddr(uint32_t u32Chip) +{ + __IO uint32_t *DMC_CSCRx; + + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + return (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) << 16U); +} + +/** + * @brief Get the end address of the specified DMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_DMC_Chip + * @arg EXMC_DMC_CHIP0: Chip 0 + * @arg EXMC_DMC_CHIP1: Chip 1 + * @arg EXMC_DMC_CHIP2: Chip 2 + * @arg EXMC_DMC_CHIP3: Chip 3 + * @retval The end address of the specified DMC chip + */ +uint32_t EXMC_DMC_GetChipEndAddr(uint32_t u32Chip) +{ + uint32_t u32Mask; + uint32_t u32Match; + __IO uint32_t *DMC_CSCRx; + + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + u32Mask = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMSK) >> DMC_CSCR_ADDMSK_POS); + u32Match = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) >> DMC_CSCR_ADDMAT_POS); + return EXMC_DMC_MAP_ADDR(u32Match, u32Mask); +} + +/** + * @brief Set EXMC_SMC command. + * @param [in] u32Chip The command chip number. + * This parameter can be one of the macros group @ref EXMC_DMC_Chip + * @arg EXMC_DMC_CHIP0: Chip 0 + * @arg EXMC_DMC_CHIP1: Chip 1 + * @arg EXMC_DMC_CHIP2: Chip 2 + * @arg EXMC_DMC_CHIP3: Chip 3 + * @param [in] u32Bank The command bank. + * This parameter can be one of the macros group @ref EXMC_DMC_Bank + * @arg EXMC_DMC_BANK0: Bank 0 + * @arg EXMC_DMC_BANK1: Bank 1 + * @arg EXMC_DMC_BANK2: Bank 2 + * @arg EXMC_DMC_BANK3: Bank 3 + * @param [in] u32Cmd The command. + * This parameter can be one of the macros group @ref EXMC_DMC_Command + * @arg EXMC_DMC_CMD_PRECHARGE_ALL:Precharge all + * @arg EXMC_DMC_CMD_AUTO_REFRESH: Auto refresh + * @arg EXMC_DMC_CMD_MDREG_CONFIG: Set memory device mode register + * @arg EXMC_DMC_CMD_NOP: NOP + * @param [in] u32Addr The address parameter for CMD MdRegConfig only. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFFUL + * @retval None + */ +void EXMC_DMC_SetCommand(uint32_t u32Chip, uint32_t u32Bank, uint32_t u32Cmd, uint32_t u32Addr) +{ + uint32_t u32RegVal; + + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_DMC_BANK(u32Bank)); + DDL_ASSERT(IS_EXMC_DMC_CMD(u32Cmd)); + DDL_ASSERT(IS_EXMC_DMC_CMD_ADDR(u32Addr)); + + u32RegVal = (u32Addr | (u32Bank << DMC_CMDR_CMDBA_POS) | u32Cmd | (u32Chip << DMC_CMDR_CMDCHIP_POS)); + WRITE_REG32(CM_DMC->CMDR, u32RegVal); +} + +/** + * @} + */ + +#endif /* LL_DMC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dvp.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dvp.c new file mode 100644 index 0000000000..ea3c9933a6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_dvp.c @@ -0,0 +1,426 @@ +/** + ******************************************************************************* + * @file hc32_ll_dvp.c + * @brief This file provides firmware functions to manage the DVP(Digital Video + * Processor) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dvp.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DVP DVP + * @brief Digital Video Processor Driver Library + * @{ + */ + +#if (LL_DVP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DVP_Local_Macros DVP Local Macros + * @{ + */ + +/** + * @defgroup DVP_Check_Parameters_Validity DVP Check Parameters Validity + * @{ + */ + +#define IS_DVP_CAPT_MD(x) \ +( ((x) == DVP_CAPT_MD_CONTINUOS_FRAME) || \ + ((x) == DVP_CAPT_MD_SINGLE_FRAME)) + +#define IS_DVP_SYNC_MD(x) \ +( ((x) == DVP_SYNC_MD_HW) || \ + ((x) == DVP_SYNC_MD_SW)) + +#define IS_DVP_PIXCLK_POLARITY(x) \ +( ((x) == DVP_PIXCLK_RISING) || \ + ((x) == DVP_PIXCLK_FALLING)) + +#define IS_DVP_HSYNC_POLARITY(x) \ +( ((x) == DVP_HSYNC_LOW) || \ + ((x) == DVP_HSYNC_HIGH)) + +#define IS_DVP_VSYNC_POLARITY(x) \ +( ((x) == DVP_VSYNC_LOW) || \ + ((x) == DVP_VSYNC_HIGH)) + +#define IS_DVP_CAPT_FREQ(x) \ +( ((x) == DVP_CAPT_FREQ_ALL_FRAME) || \ + ((x) == DVP_CAPT_FREQ_ONT_TIME_2FRAME) || \ + ((x) == DVP_CAPT_FREQ_ONT_TIME_4FRAME)) + +#define IS_DVP_DATA_WIDTH(x) \ +( ((x) == DVP_DATA_WIDTH_8BIT) || \ + ((x) == DVP_DATA_WIDTH_10BIT) || \ + ((x) == DVP_DATA_WIDTH_12BIT) || \ + ((x) == DVP_DATA_WIDTH_14BIT)) + +#define IS_DVP_FLAG(x) \ +( ((x) != 0UL) || \ + (((x) | DVP_FLAG_ALL) == DVP_FLAG_ALL)) + +#define IS_DVP_INT(x) \ +( ((x) != 0UL) || \ + (((x) | DVP_INT_ALL) == DVP_INT_ALL)) + +#define IS_DVP_CROP_WIN_ROW_START_LINE(x) ((x) <= 0x3FFFU) + +#define IS_DVP_CROP_WIN_COLOUM_START_LINE(x) ((x) <= 0x3FFFU) + +#define IS_DVP_CROP_WIN_ROW_LINE_SIZE(x) (((x) >= 0x04U) && ((x) <= 0x3FFFU)) + +#define IS_DVP_CROP_WIN_COLOUM_LINE_SIZE(x) ((x) <= 0x3FFFU) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Functions DVP Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_dvp_init_t to default values + * @param [out] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDvpInit value is NULL. + */ +int32_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDvpInit) { + pstcDvpInit->u32SyncMode = DVP_SYNC_MD_HW; + pstcDvpInit->u32DataWidth = DVP_DATA_WIDTH_8BIT; + pstcDvpInit->u32CaptureMode = DVP_CAPT_MD_CONTINUOS_FRAME; + pstcDvpInit->u32CaptureFreq = DVP_CAPT_FREQ_ALL_FRAME; + pstcDvpInit->u32PIXCLKPolarity = DVP_PIXCLK_FALLING; + pstcDvpInit->u32HSYNCPolarity = DVP_HSYNC_LOW; + pstcDvpInit->u32VSYNCPolarity = DVP_VSYNC_LOW; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize DVP function. + * @param [in] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDvpInit value is NULL. + */ +int32_t DVP_Init(const stc_dvp_init_t *pstcDvpInit) +{ + uint32_t u32Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDvpInit) { + DDL_ASSERT(IS_DVP_SYNC_MD(pstcDvpInit->u32SyncMode)); + DDL_ASSERT(IS_DVP_DATA_WIDTH(pstcDvpInit->u32DataWidth)); + DDL_ASSERT(IS_DVP_CAPT_MD(pstcDvpInit->u32CaptureMode)); + DDL_ASSERT(IS_DVP_CAPT_FREQ(pstcDvpInit->u32CaptureFreq)); + DDL_ASSERT(IS_DVP_PIXCLK_POLARITY(pstcDvpInit->u32PIXCLKPolarity)); + DDL_ASSERT(IS_DVP_HSYNC_POLARITY(pstcDvpInit->u32HSYNCPolarity)); + DDL_ASSERT(IS_DVP_VSYNC_POLARITY(pstcDvpInit->u32VSYNCPolarity)); + + /* Configure DVP */ + u32Value = (pstcDvpInit->u32SyncMode | pstcDvpInit->u32DataWidth | pstcDvpInit->u32CaptureMode | \ + pstcDvpInit->u32CaptureFreq | pstcDvpInit->u32PIXCLKPolarity | pstcDvpInit->u32HSYNCPolarity | \ + pstcDvpInit->u32VSYNCPolarity); + WRITE_REG32(CM_DVP->CTR, u32Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize DVP function. + * @param None + * @retval None + */ +void DVP_DeInit(void) +{ + WRITE_REG32(CM_DVP->CTR, 0UL); + WRITE_REG32(CM_DVP->STR, 0UL); + WRITE_REG32(CM_DVP->IER, 0UL); + WRITE_REG32(CM_DVP->SSYNDR, 0UL); + WRITE_REG32(CM_DVP->SSYNMR, 0xFFFFFFFFUL); + WRITE_REG32(CM_DVP->CPSFTR, 0UL); + WRITE_REG32(CM_DVP->CPSZER, 0UL); +} + +/** + * @brief Enable/disable DVP. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DVP_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DVP->CTR, DVP_CTR_DVPEN); + } else { + CLR_REG32_BIT(CM_DVP->CTR, DVP_CTR_DVPEN); + } +} + +/** + * @brief Enable/disable the specified DVP interrupt. + * @param [in] u32IntType DVP interrupt type + * This parameter can be any composed value of the macros group @ref DVP_Interrupt + * @arg DVP_INT_FRAME_START: Frame start interrupt + * @arg DVP_INT_LINE_START: Line start interrupt + * @arg DVP_INT_LINE_END: Line end interrupt + * @arg DVP_INT_FRAME_END: Frame end interrupt + * @arg DVP_INT_FIFO_OVF: FIFO overflow error interrupt + * @arg DVP_INT_SYNC_ERR: Sync error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DVP_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DVP->IER, u32IntType); + } else { + CLR_REG32_BIT(CM_DVP->IER, u32IntType); + } +} + +/** + * @brief Enable/disable DVP crop. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DVP_CropCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_DVP->CTR_b.CROPEN, enNewState); +} + +/** + * @brief Enable/disable DVP JPEG format. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DVP_JPEGCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DVP->CTR, DVP_CTR_JPEGEN); + } else { + CLR_REG32_BIT(CM_DVP->CTR, DVP_CTR_JPEGEN); + } +} + +/** + * @brief Enable/disable DVP capture. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DVP_CaptrueCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DVP->CTR, DVP_CTR_CAPEN); + } else { + CLR_REG32_BIT(CM_DVP->CTR, DVP_CTR_CAPEN); + } +} + +/** + * @brief Get the specified DVP flag status. + * @param [in] u32Flag DVP flag + * This parameter can be any composed value of the macros group @ref DVP_Flag + * @arg DVP_FLAG_FRAME_START: Frame start flag + * @arg DVP_FLAG_LINE_START: Line start flag + * @arg DVP_FLAG_LINE_END: Line end flag + * @arg DVP_FLAG_FRAME_END: Frame end flag + * @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag + * @arg DVP_FLAG_SYNC_ERR: Sync error interrupt + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DVP_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_DVP_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_DVP->STR, u32Flag) == 0UL) ? RESET : SET); +} + +/** + * @brief Clear the specified DVP flag status. + * @param [in] u32Flag DVP flag + * This parameter can be any composed value of the macros group @ref DVP_Flag + * @arg DVP_FLAG_FRAME_START: Frame start flag + * @arg DVP_FLAG_LINE_START: Line start flag + * @arg DVP_FLAG_LINE_END: Line end flag + * @arg DVP_FLAG_FRAME_END: Frame end flag + * @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag + * @arg DVP_FLAG_SYNC_ERR: Sync error interrupt + * @retval None + */ +void DVP_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_DVP_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_DVP->STR, u32Flag); +} + +/** + * @brief Set DVP software sync code. + * @param [in] pstcSyncCode Pointer to a @ref stc_dvp_sw_sync_code_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The parameter pstcSyncCode value is NULL. + */ +int32_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode) +{ + uint32_t u32Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSyncCode) { + /* Set sync code. */ + u32Value = (((uint32_t)pstcSyncCode->u8FrameStartSyncCode << DVP_SSYNDR_FSDAT_POS) | \ + ((uint32_t)pstcSyncCode->u8LineStartSyncCode << DVP_SSYNDR_LSDAT_POS) | \ + ((uint32_t)pstcSyncCode->u8LineEndSyncCode << DVP_SSYNDR_LEDAT_POS) | \ + ((uint32_t)pstcSyncCode->u8FrameEndSyncCode << DVP_SSYNDR_FEDAT_POS)); + WRITE_REG32(CM_DVP->SSYNDR, u32Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set DVP software sync mask code. + * @param [in] pstcMaskCode Pointer to a @ref stc_dvp_sw_mask_code_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The parameter pstcMaskCode value is NULL. + */ +int32_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode) +{ + uint32_t u32Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMaskCode) { + /* Set sync code. */ + u32Value = (((uint32_t)pstcMaskCode->u8FrameStartMaskCode << DVP_SSYNMR_FSMSK_POS) | \ + ((uint32_t)pstcMaskCode->u8LineStartMaskCode << DVP_SSYNMR_LSMSK_POS) | \ + ((uint32_t)pstcMaskCode->u8LineEndMaskCode << DVP_SSYNMR_LEMSK_POS) | \ + ((uint32_t)pstcMaskCode->u8FrameEndMaskCode << DVP_SSYNMR_FEMSK_POS)); + WRITE_REG32(CM_DVP->SSYNMR, u32Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set DVP software sync mask code. + * @param [in] pstcConfig Pointer to a @ref stc_dvp_crop_window_config_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The parameter pstcConfig value is NULL. + */ +int32_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig) +{ + uint32_t u32Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcConfig) { + DDL_ASSERT(IS_DVP_CROP_WIN_ROW_START_LINE(pstcConfig->u16RowStartLine)); + DDL_ASSERT(IS_DVP_CROP_WIN_COLOUM_START_LINE(pstcConfig->u16ColoumStartLine)); + DDL_ASSERT(IS_DVP_CROP_WIN_ROW_LINE_SIZE(pstcConfig->u16RowLineSize)); + DDL_ASSERT(IS_DVP_CROP_WIN_COLOUM_LINE_SIZE(pstcConfig->u16ColoumLineSize)); + + /* Configure crop window */ + u32Value = ((uint32_t)pstcConfig->u16RowStartLine | \ + ((uint32_t)pstcConfig->u16ColoumStartLine << DVP_CPSFTR_CSHIFT_POS)); + WRITE_REG32(CM_DVP->CPSFTR, u32Value); + + u32Value = ((uint32_t)pstcConfig->u16RowLineSize | \ + ((uint32_t)pstcConfig->u16ColoumLineSize << DVP_CPSZER_CSIZE_POS)); + WRITE_REG32(CM_DVP->CPSZER, u32Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_DVP_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c new file mode 100644 index 0000000000..ef40753756 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c @@ -0,0 +1,1450 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.c + * @brief This file provides firmware functions to manage the Embedded Flash + * Memory unit (EFM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_efm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EFM EFM + * @brief Embedded Flash Management Driver Library + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Local_Macros EFM Local Macros + * @{ + */ +#define REG_LEN (32U) +#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */ +#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */ +#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */ +#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */ + +#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x)))) + +#define EFM_FLAG0_POS (0U) +#define EFM_FLAG1_POS (16U) +#define EFM_OTP_END_SECTOR_NUM (15U) +#define EFM_FLASH1_START_SECTOR_NUM (128U) +#define EFM_SWAP_FLASH1_END_SECTOR_NUM (EFM_FLASH1_START_SECTOR_NUM + EFM_OTP_END_SECTOR_NUM) +#define EFM_SWAP_FLASH1_END_ADDR (EFM_FLASH_1_START_ADDR + EFM_OTP_END_ADDR1) +#define EFM_OTP_UNLOCK_KEY1 (0x10325476UL) +#define EFM_OTP_UNLOCK_KEY2 (0xEFCDAB89UL) + +/** + * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask + * @{ + */ +#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_PREFETE | EFM_FRMC_DCACHE | EFM_FRMC_ICACHE) + +/** + * @} + */ + +/** + * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity + * @{ + */ +/* Parameter validity check for efm chip . */ +#define IS_EFM_CHIP(x) \ +( ((x) == EFM_CHIP0) || \ + ((x) == EFM_CHIP1) || \ + ((x) == EFM_CHIP_ALL)) + +/* Parameter validity check for flash latency. */ +#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15) + +/* Parameter validity check for operate mode. */ +#define IS_EFM_OPERATE_MD(x) \ +( ((x) == EFM_MD_PGM_SINGLE) || \ + ((x) == EFM_MD_PGM_READBACK) || \ + ((x) == EFM_MD_PGM_SEQ) || \ + ((x) == EFM_MD_ERASE_SECTOR) || \ + ((x) == EFM_MD_ERASE_ONE_CHIP) || \ + ((x) == EFM_MD_ERASE_ALL_CHIP) || \ + ((x) == EFM_MD_READONLY)) + +/* Parameter validity check for efm status. */ +#define IS_EFM_STATUS(x) \ +( ((x) == EFM_FLASH0_ACT_FLASH1_ACT) || \ + ((x) == EFM_FLASH0_STP_FLASH1_ACT) || \ + ((x) == EFM_FLASH0_ACT_FLASH1_STP) || \ + ((x) == EFM_FLASH0_STP_FLASH1_STP)) + +/* Parameter validity check for flash interrupt select. */ +#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL) + +/* Parameter validity check for flash flag. */ +#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for flash clear flag. */ +#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for bus status while flash program or erase. */ +#define IS_EFM_BUS_STATUS(x) \ +( ((x) == EFM_BUS_HOLD) || \ + ((x) == EFM_BUS_RELEASE)) + +/* Parameter validity check for efm address. */ +#define IS_EFM_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR))) + +/* Parameter validity check for efm eraseaddress. */ +#define IS_EFM_ERASE_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR))) + +/* Parameter validity check for efm erase mode . */ +#define IS_EFM_ERASE_MD(x) \ +( ((x) == EFM_MD_ERASE_ONE_CHIP) || \ + ((x) == EFM_MD_ERASE_FULL)) + +/* Parameter validity check for EFM lock status. */ +#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for EFM_FWMC register lock status. */ +#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.KEY1LOCK == 0U) + +/* Parameter validity check for OTP lock status. */ +#define IS_EFM_OTP_UNLOCK() (bCM_EFM->FWMC_b.KEY2LOCK == 0U) + +/* Parameter validity check for sector protected register locking. */ +#define IS_EFM_SECTOR_PROTECT_REG_LOCK(x) ((x) <= 0xFFU) + +/* Parameter validity check for EFM sector number */ +#define IS_EFM_SECTOR_NUM(x) ((x) <= 256U) + +/* Parameter validity check for EFM remap lock status. */ +#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL) + +/* Parameter validity check for EFM remap index */ +#define IS_EFM_REMAP_IDX(x) \ +( ((x) == EFM_REMAP_IDX0) || \ + ((x) == EFM_REMAP_IDX1)) + +/* Parameter validity check for EFM remap size */ +#define IS_EFM_REMAP_SIZE(x) \ +( ((x) >= EFM_REMAP_4K) && \ + ((x) <= EFM_REMAP_512K)) + +/* Parameter validity check for EFM remap address */ +#define IS_EFM_REMAP_ADDR(x) \ +( ((x) <= EFM_REMAP_ROM_END_ADDR) || \ + (((x) >= EFM_REMAP_RAM_START_ADDR) && \ + ((x) <= EFM_REMAP_RAM_END_ADDR))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EFM_Local_Functions EFM Local Functions + * @{ + */ +/** + * @brief Wait EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + * @note None + */ +static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (SET != EFM_GetStatus(u32Flag)) { + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Clear EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + * @note None + */ +static int32_t EFM_ClearFlag(uint32_t u32Flag) +{ + uint32_t u32Time = EFM_TIMEOUT; + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (RESET != EFM_GetStatus(u32Flag)) { + EFM_ClearStatus(u32Flag); + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Wait EFM flag. + * @param [in] u32Addr Specifies the address to calculate. + * @retval uint8_t: The count that flag should shift. + * @note None + */ +static uint8_t EFM_FlagShift(uint32_t u32Addr) +{ + uint8_t u8Shift; + + if (SET == EFM_GetSwapStatus()) { + if (0xFFFFFFFFUL != RW_MEM32(EFM_OTP_ENABLE_ADDR)) { + if ((u32Addr <= EFM_OTP_END_ADDR1) || ((u32Addr > EFM_SWAP_FLASH1_END_ADDR) && (u32Addr < EFM_END_ADDR))) { + u8Shift = EFM_FLAG0_POS; + } else { + u8Shift = EFM_FLAG1_POS; + } + } else { + if ((u32Addr >= EFM_FLASH_1_START_ADDR) && (u32Addr <= EFM_END_ADDR)) { + u8Shift = EFM_FLAG0_POS; + } else { + u8Shift = EFM_FLAG1_POS; + } + } + } else { + if ((u32Addr >= EFM_FLASH_1_START_ADDR) && (u32Addr <= EFM_END_ADDR)) { + u8Shift = EFM_FLAG1_POS; + } else { + u8Shift = EFM_FLAG0_POS; + } + } + + return u8Shift; +} + +/** + * @} + */ + +/** + * @defgroup EFM_Global_Functions EFM Global Functions + * @{ + */ + +/** + * @brief Enable or disable EFM. + * @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note + */ +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u32Flash)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_EFM->FSTP, u32Flash); + } else { + SET_REG32_BIT(CM_EFM->FSTP, u32Flash); + } +} + +/** + * @brief Set the efm read wait cycles. + * @param [in] u32WaitCycle Specifies the efm read wait cycles. + * @arg This parameter can be of a value of @ref EFM_Wait_Cycle + * @retval int32_t: + * - LL_OK: Program successful... + * - LL_ERR_TIMEOUT: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle) +{ + uint32_t u32Timeout = 0UL; + + /* Param valid check */ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle)); + + MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle); + while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) { + u32Timeout++; + if (u32Timeout > EFM_TIMEOUT) { + return LL_ERR_TIMEOUT; + } + } + return LL_OK; +} + +/** + * @brief Enable or disable the flash data cache reset. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note None + */ +void EFM_DataCacheResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.CRST, enNewState); +} + +/** + * @brief Enable or disable the flash prefetch. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_PrefetchCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.PREFETE, enNewState); +} + +/** + * @brief Enable or disable the flash data cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_DCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.DCACHE, enNewState); +} + +/** + * @brief Enable or disable the flash instruction cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ICacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.ICACHE, enNewState); +} + +/** + * @brief Enable or disable the Read of low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState); +} + +/** + * @brief Enable or disable the EFM swap function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Program successful... + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SwapCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (enNewState == ENABLE) { + /* Set Program single mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Enable flash swap function */ + RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } else { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Checks whether the swap function enable or disable. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetSwapStatus(void) +{ + return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? RESET : SET); +} + +/** + * @brief Set the FLASH erase program mode . + * @param [in] u32Mode Specifies the FLASH erase program mode. + * @arg This parameter can be of a value of @ref EFM_OperateMode_Sel + * @retval int32_t: + * - LL_OK: Set mode successfull. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note None + */ +int32_t EFM_SetOperateMode(uint32_t u32Mode) +{ + int32_t i32Ret = LL_OK; + DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + if (i32Ret == LL_OK) { + /* Set the program or erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode); + } + return i32Ret; +} + +/** + * @brief Enable or Disable EFM interrupt. + * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel + * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source + * @arg EFM_INT_PEERR: Program/erase error Interrupt source + * @arg EFM_INT_COLERR: Read collide error Interrupt source + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } else { + CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } +} + +/** + * @brief Check any of the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Check all the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear the flash flag. + * @param [in] u32Flag Specifies the FLASH flag to clear. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag)); + + SET_REG32_BIT(CM_EFM->FSCLR, u32Flag); +} + +/** + * @brief Set bus status while flash program or erase. + * @param [in] u32Status Specifies the new bus status while flash program or erase. + * This parameter can be one of the following values: + * @arg EFM_BUS_HOLD: Bus busy while flash program or erase. + * @arg EFM_BUS_RELEASE: Bus release while flash program or erase. + * @retval None + * @note None + */ +void EFM_SetBusStatus(uint32_t u32Status) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status); +} + +/** + * @brief EFM read byte. + * @param [in] u32Addr The specified address to read. + * @param [in] pu8ReadBuf The specified read buffer. + * @param [in] u32ByteLen The specified length to read. + * @retval int32_t: + * - LL_OK: Read successful.. + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note None. + */ +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint8_t *pu8Buf = (uint8_t *)u32Addr; + uint32_t u32Len = u32ByteLen; + uint32_t u32ReadyFlag = EFM_FLAG_RDY; + + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen * 4U)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + if (NULL != pu8ReadBuf) { + uint32_t u32EndAddr = u32Addr + u32ByteLen * 4U; + if (u32Addr < EFM_FLASH_1_START_ADDR) { + if (u32EndAddr >= EFM_FLASH_1_START_ADDR) { + u32ReadyFlag |= EFM_FLAG_RDY1; + } + } else { + u32ReadyFlag = EFM_FLAG_RDY1; + } + + if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) { + while (0UL != u32Len) { + *(pu8ReadBuf++) = *(pu8Buf++); + u32Len--; + } + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_NOT_RDY; + } + } + + return i32Ret; +} + +/** + * @brief EFM program (single program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful. + * - LL_ERR_NOT_RDY: EFM if not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + u8Shift = EFM_FlagShift((uint32_t)u32pDest); + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + u8Shift = EFM_FlagShift((uint32_t)u32pDest); + *u32pDest++ = u32LastWord; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + } + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM single program mode(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE function */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = EFM_FlagShift(u32Addr); + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Program data. */ + RW_MEM32(u32Addr) = u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM single program with read back(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR: program error + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = EFM_FlagShift(u32Addr); + /* Set Program and read back mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Get the flag MISMTCH */ + if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) { + /* Clear flag PGMISMTCH */ + EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift); + i32Ret = LL_ERR; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM program (sequence program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR_TIMEOUT: program error timeout + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint8_t u8Shift = 0U; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set sequence program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ); + + while (u32LoopWords-- > 0UL) { + u8Shift = EFM_FlagShift((uint32_t)u32pDest); + /* program data. */ + *u32pDest++ = *u32pSource++; + /* wait for operation end flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_OPTEND << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + } + /* Clear operation end flag */ + if (LL_ERR_TIMEOUT == EFM_ClearFlag(EFM_FLAG_OPTEND << u8Shift)) { + i32Ret = LL_ERR_TIMEOUT; + } + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + u8Shift = EFM_FlagShift((uint32_t)u32pDest); + *u32pDest++ = u32LastWord; + + /* wait for operation end flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_OPTEND << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + } + /* Clear operation end flag */ + if (LL_ERR_TIMEOUT == EFM_ClearFlag(EFM_FLAG_OPTEND << u8Shift)) { + i32Ret = LL_ERR_TIMEOUT; + } + + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM sector erase. + * @param [in] u32Addr The address in the specified sector. + * @retval int32_t: + * - LL_OK: Erase successful. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SectorErase(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = EFM_FlagShift(u32Addr); + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* Clear the operation end flag */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM chip erase. + * @param [in] u8Chip Specifies the chip to be erased. + * @arg EFM_CHIP0 Chip0 + * @arg EFM_CHIP1 Chip1 + * @arg EFM_CHIP_ALL All Chip + * @retval int32_t: + * - LL_OK: Erase successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ChipErase(uint8_t u8Chip) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32Addr = 0UL; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u8Chip)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (EFM_CHIP1 == u8Chip) { + u32Addr = EFM_FLASH_1_START_ADDR; + } + u8Shift = EFM_FlagShift(u32Addr); + if ((EFM_CHIP_ALL == u8Chip) && (SET == EFM_GetSwapStatus())) { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* wait for operation end flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_OPTEND, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + } + /* CLear the operation end flag */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* Set chip erase mode. */ + if (EFM_CHIP_ALL == u8Chip) { + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP); + } else { + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ONE_CHIP); + } + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief FWMC register write enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note None + */ +void EFM_FWMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(CM_EFM->KEY1, 0x01234567UL); + WRITE_REG32(CM_EFM->KEY1, 0xFEDCBA98UL); + } else { + SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY1LOCK); + } +} + +/** + * @brief Get chip ID. + * @param None + * @retval Returns the value of the Chip ID + */ +uint32_t EFM_GetCID(void) +{ + return READ_REG32(CM_EFM->CHIPID); +} + +/** + * @brief EFM OTP operate unlock. + * @param None + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_OTP_WP_Unlock(void) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY2); +} + +/** + * @brief EFM OTP write protect lock. + * @param None + * @retval None + * @note None + */ +void EFM_OTP_WP_Lock(void) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY2LOCK); +} + +/** + * @brief EFM OTP Enable. + * @param None + * @retval None + * @note None + */ +int32_t EFM_OTP_Enable(void) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EFM_OTP_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + if (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) { + /* Enable OTP */ + RW_MEM32(EFM_OTP_ENABLE_ADDR) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Sector protected register lock. + * @param [in] u32RegLock Specifies sector protected register locking. + * @arg EFM_WRLOCK0 ~ EFM_WRLOCK7: For HC32F4A0 + * @arg EFM_WRLOCK0, EFM_WRLOCK4: For HC32F472 + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_SectorProtectRegLock(uint32_t u32RegLock) +{ + DDL_ASSERT(IS_EFM_SECTOR_PROTECT_REG_LOCK(u32RegLock)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + SET_REG32_BIT(CM_EFM->WLOCK, u32RegLock); +} + +/** + * @brief Set sector lock or unlock (Single). + * @param [in] u8SectorNum Specifies sector for unlock. + * This parameter can be set 0~255 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + * If you want to unlock sequence sectors,Please call EFM_SequenceSectorOperateCmd function + */ +void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState) +{ + __IO uint32_t *EFM_FxNWPRTy; + const uint8_t u8RegIndex = u8SectorNum / REG_LEN; + const uint8_t u8BitPos = u8SectorNum % REG_LEN; + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u8RegIndex << 2UL)); + MODIFY_REG32(*EFM_FxNWPRTy, 1UL << u8BitPos, (uint32_t)enNewState << u8BitPos); +} + +/** + * @brief Set sector lock or unlock (Sequence). + * @param [in] u32StartSectorNum Specifies start sector to unlock. + * This parameter can be set 0~255. + * @param [in] u16Count Specifies count of sectors to unlock. + * This parameter can be set 0~256. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + * If you want to unlock only one sector,Please call EFM_SingleSectorOperateCmd function + */ +void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState) +{ + __IO uint32_t *EFM_FxNWPRTy; + uint32_t u32EndSectorNum; + uint16_t u16StartRegIndex; + uint16_t u16StartBitPos; + uint16_t u16EndRegIndex; + uint16_t u16EndBitPos; + uint32_t u32RegValue; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_SECTOR_NUM(u32StartSectorNum + u16Count)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (SET == EFM_GetSwapStatus()) { + if (0xFFFFFFFFUL != RW_MEM32(EFM_OTP_ENABLE_ADDR)) { + if (u32StartSectorNum > EFM_SWAP_FLASH1_END_SECTOR_NUM) { + u32StartSectorNum -= EFM_FLASH1_START_SECTOR_NUM; + } else if ((u32StartSectorNum > EFM_OTP_END_SECTOR_NUM) && (u32StartSectorNum < EFM_FLASH1_START_SECTOR_NUM)) { + u32StartSectorNum += EFM_FLASH1_START_SECTOR_NUM; + } else { + /* reserved */ + } + } else { + if (u32StartSectorNum >= EFM_FLASH1_START_SECTOR_NUM) { + u32StartSectorNum -= EFM_FLASH1_START_SECTOR_NUM; + } else { + u32StartSectorNum += EFM_FLASH1_START_SECTOR_NUM; + } + } + } + + u16StartRegIndex = (uint16_t)(u32StartSectorNum / REG_LEN); /* Register offset for the start sector */ + u16StartBitPos = (uint16_t)(u32StartSectorNum % REG_LEN); /* Bit offset for the start sector */ + u32EndSectorNum = (uint16_t)(u32StartSectorNum + u16Count - 1U); /* Calculate the end sector */ + u16EndRegIndex = (uint16_t)(u32EndSectorNum / REG_LEN); /* Register offset for the end sector */ + u16EndBitPos = (uint16_t)(u32EndSectorNum % REG_LEN); /* Bit offset for the end sector */ + + if ((u16StartBitPos == 0U) && (u16EndBitPos == 31U)) { + while (u16StartRegIndex <= u16EndRegIndex) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16StartRegIndex << 2UL)); + if (EFM_FxNWPRTy > (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT3)) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + (((uint32_t)u16StartRegIndex - 8UL) << 2UL)); + } + if (enNewState == ENABLE) { + WRITE_REG32(*EFM_FxNWPRTy, 0xFFFFFFFFUL); + } else { + WRITE_REG32(*EFM_FxNWPRTy, 0x0UL); + } + u16StartRegIndex += 1U; + } + } else { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16StartRegIndex << 2UL)); + if (u16StartRegIndex == u16EndRegIndex) { + u32RegValue = ((1UL << u16EndBitPos) - (1UL << u16StartBitPos)) | (1UL << u16EndBitPos); + if (enNewState == ENABLE) { + SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + } else { + CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + } + } else { + u32RegValue = ((1UL << 31U) - (1UL << u16StartBitPos)) | (1UL << 31U); + if (enNewState == ENABLE) { + SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + while (u16StartRegIndex < (u16EndRegIndex - 1U)) { + u16StartRegIndex += 1U; + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16StartRegIndex << 2UL)); + if (EFM_FxNWPRTy > (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT3)) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + (((uint32_t)u16StartRegIndex - 8UL) << 2UL)); + } + WRITE_REG32(*EFM_FxNWPRTy, 0xFFFFFFFFUL); + } + u32RegValue = ((1UL << u16EndBitPos) - 1UL) | (1UL << u16EndBitPos); + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16EndRegIndex << 2UL)); + if (EFM_FxNWPRTy > (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT3)) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + (((uint32_t)u16EndRegIndex - 8UL) << 2UL)); + } + SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + } else { + CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + while (u16StartRegIndex < (u16EndRegIndex - 1U)) { + u16StartRegIndex += 1U; + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16StartRegIndex << 2UL)); + if (EFM_FxNWPRTy > (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT3)) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + (((uint32_t)u16StartRegIndex - 8UL) << 2UL)); + } + WRITE_REG32(*EFM_FxNWPRTy, 0x0UL); + } + u32RegValue = ((1UL << u16EndBitPos) - 1UL) | (1UL << u16EndBitPos); + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + ((uint32_t)u16EndRegIndex << 2UL)); + if (EFM_FxNWPRTy > (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT3)) { + EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&CM_EFM->F0NWPRT0) + (((uint32_t)u16EndRegIndex - 8UL) << 2UL)); + } + CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue); + } + } + } +} + +/** + * @brief EFM OTP lock. + * @param [in] u32Addr Specifies the OTP block + * @retval int32_t: + * - LL_OK: Lock successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note The address should be word align. + * Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first. + */ +int32_t EFM_OTP_Lock(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_OTP_UNLOCK()); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + if (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) { + /* Enable OTP */ + RW_MEM32(EFM_OTP_ENABLE_ADDR) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* OTP latch */ + RW_MEM32(u32Addr) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + } + + return i32Ret; +} + +/** + * @brief Get unique ID. + * @param [out] pstcUID Unique ID struct + * @retval Returns the value of the unique ID + */ +void EFM_GetUID(stc_efm_unique_id_t *pstcUID) +{ + if (NULL != pstcUID) { + pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0); + pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1); + pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2); + } +} + +/** + * @brief Init REMAP initial structure with default value. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcEfmRemapInit->u32State = EFM_REMAP_OFF; + pstcEfmRemapInit->u32Addr = 0UL; + pstcEfmRemapInit->u32Size = EFM_REMAP_4K; + } + return i32Ret; +} + +/** + * @brief REMAP initialize. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *REMCRx; + + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr)); + if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \ + pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size); + } + } + return i32Ret; +} + +/** + * @brief EFM REMAP de-initialize. + * @param None + * @retval None + */ +void EFM_REMAP_DeInit(void) +{ + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + + WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL); + WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL); +} + +/** + * @brief Enable or disable REMAP function. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + REMCRx = &REMCR_REG(u8RemapIdx); + if (ENABLE == enNewState) { + SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } else { + CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } +} + +/** + * @brief Set specified REMAP target address. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Addr Specifies the target address. + * @retval None + */ +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr); +} + +/** + * @brief Set specified REMAP size. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Size Specifies the remap size. + * @retval None + */ +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size); +} + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c new file mode 100644 index 0000000000..0bda6cf025 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c @@ -0,0 +1,718 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.c + * @brief This file provides firmware functions to manage the EMB + * (Emergency Brake). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_emb.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EMB EMB + * @brief Emergency Brake Driver Library + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Local_Macros EMB Local Macros + * @{ + */ + +/** + * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity + * @{ + */ +#define IS_EMB_GROUP(x) \ +( ((x) == CM_EMB0) || \ + ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3) || \ + ((x) == CM_EMB4) || \ + ((x) == CM_EMB5) || \ + ((x) == CM_EMB6)) +#define IS_EMB_TMR4_GROUP(x) \ +( ((x) == CM_EMB4) || \ + ((x) == CM_EMB5) || \ + ((x) == CM_EMB6)) +#define IS_EMB_TMR6_GROUP(x) \ +( ((x) == CM_EMB0) || \ + ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) + +#define IS_EMB_OSC_STAT(x) \ +( ((x) == EMB_OSC_ENABLE) || \ + ((x) == EMB_OSC_DISABLE)) + +#define IS_EMB_TMR4_PWM_W_STAT(x) \ +( ((x) == EMB_TMR4_PWM_W_ENABLE) || \ + ((x) == EMB_TMR4_PWM_W_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_W_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_V_STAT(x) \ +( ((x) == EMB_TMR4_PWM_V_ENABLE) || \ + ((x) == EMB_TMR4_PWM_V_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_V_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_U_STAT(x) \ +( ((x) == EMB_TMR4_PWM_U_ENABLE) || \ + ((x) == EMB_TMR4_PWM_U_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_U_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH)) + +#define IS_EMB_CMP1_STAT(x) \ +( ((x) == EMB_CMP1_ENABLE) || \ + ((x) == EMB_CMP1_DISABLE)) + +#define IS_EMB_CMP2_STAT(x) \ +( ((x) == EMB_CMP2_ENABLE) || \ + ((x) == EMB_CMP2_DISABLE)) + +#define IS_EMB_CMP3_STAT(x) \ +( ((x) == EMB_CMP3_ENABLE) || \ + ((x) == EMB_CMP3_DISABLE)) + +#define IS_EMB_CMP4_STAT(x) \ +( ((x) == EMB_CMP4_ENABLE) || \ + ((x) == EMB_CMP4_DISABLE)) + +#define IS_EMB_PORT1_STAT(x) \ +( ((x) == EMB_PORT1_ENABLE) || \ + ((x) == EMB_PORT1_DISABLE)) + +#define IS_EMB_PORT1_DETECT_LVL(x) \ +( ((x) == EMB_PORT1_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT1_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT1_FILTER_STAT(x) \ +( ((x) == EMB_PORT1_FILTER_ENABLE) || \ + ((x) == EMB_PORT1_FILTER_DISABLE)) + +#define IS_EMB_PORT1_FILTER_DIV(x) (((x) & (~EMB_PORT1_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_PORT2_STAT(x) \ +( ((x) == EMB_PORT2_ENABLE) || \ + ((x) == EMB_PORT2_DISABLE)) + +#define IS_EMB_PORT2_DETECT_LVL(x) \ +( ((x) == EMB_PORT2_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT2_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT2_FILTER_STAT(x) \ +( ((x) == EMB_PORT2_FILTER_ENABLE) || \ + ((x) == EMB_PORT2_FILTER_DISABLE)) + +#define IS_EMB_PORT2_FILTER_DIV(x) (((x) & (~EMB_PORT2_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_PORT3_STAT(x) \ +( ((x) == EMB_PORT3_ENABLE) || \ + ((x) == EMB_PORT3_DISABLE)) + +#define IS_EMB_PORT3_DETECT_LVL(x) \ +( ((x) == EMB_PORT3_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT3_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT3_FILTER_STAT(x) \ +( ((x) == EMB_PORT3_FILTER_ENABLE) || \ + ((x) == EMB_PORT3_FILTER_DISABLE)) + +#define IS_EMB_PORT3_FILTER_DIV(x) (((x) & (~EMB_PORT3_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_PORT4_STAT(x) \ +( ((x) == EMB_PORT4_ENABLE) || \ + ((x) == EMB_PORT4_DISABLE)) + +#define IS_EMB_PORT4_DETECT_LVL(x) \ +( ((x) == EMB_PORT4_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT4_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT4_FILTER_STAT(x) \ +( ((x) == EMB_PORT4_FILTER_ENABLE) || \ + ((x) == EMB_PORT4_FILTER_DISABLE)) + +#define IS_EMB_PORT4_FILTER_DIV(x) (((x) & (~EMB_PORT4_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_TMR6_1_PWM_STAT(x) \ +( ((x) == EMB_TMR6_1_PWM_ENABLE) || \ + ((x) == EMB_TMR6_1_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_1_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_2_PWM_STAT(x) \ +( ((x) == EMB_TMR6_2_PWM_ENABLE) || \ + ((x) == EMB_TMR6_2_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_2_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_3_PWM_STAT(x) \ +( ((x) == EMB_TMR6_3_PWM_ENABLE) || \ + ((x) == EMB_TMR6_3_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_3_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_4_PWM_STAT(x) \ +( ((x) == EMB_TMR6_4_PWM_ENABLE) || \ + ((x) == EMB_TMR6_4_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_4_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_5_PWM_STAT(x) \ +( ((x) == EMB_TMR6_5_PWM_ENABLE) || \ + ((x) == EMB_TMR6_5_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_5_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_6_PWM_STAT(x) \ +( ((x) == EMB_TMR6_6_PWM_ENABLE) || \ + ((x) == EMB_TMR6_6_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_6_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_7_PWM_STAT(x) \ +( ((x) == EMB_TMR6_7_PWM_ENABLE) || \ + ((x) == EMB_TMR6_7_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_7_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_8_PWM_STAT(x) \ +( ((x) == EMB_TMR6_8_PWM_ENABLE) || \ + ((x) == EMB_TMR6_8_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_8_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_INT(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_INT_ALL) == EMB_INT_ALL)) + +#define IS_EMB_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_FLAG_ALL) == EMB_FLAG_ALL)) + +#define IS_EMB_RELEASE_PWM_COND(x) \ +( ((x) == EMB_RELEASE_PWM_COND_FLAG_ZERO) || \ + ((x) == EMB_RELEASE_PWM_COND_STAT_ZERO)) + +#define IS_EMB_MONITOR_EVT(x) \ +( ((x) == EMB_EVT_PWMS) || \ + ((x) == EMB_EVT_CMP) || \ + ((x) == EMB_EVT_OSC) || \ + ((x) == EMB_EVT_PORT1) || \ + ((x) == EMB_EVT_PORT2) || \ + ((x) == EMB_EVT_PORT3) || \ + ((x) == EMB_EVT_PORT4)) + +/** + * @} + */ + +#define EMB_PORT1_FILTER_CLK_DIV_MASK EMB_PORT1_FILTER_CLK_DIV128 +#define EMB_PORT2_FILTER_CLK_DIV_MASK EMB_PORT2_FILTER_CLK_DIV128 +#define EMB_PORT3_FILTER_CLK_DIV_MASK EMB_PORT3_FILTER_CLK_DIV128 +#define EMB_PORT4_FILTER_CLK_DIV_MASK EMB_PORT4_FILTER_CLK_DIV128 +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EMB_Global_Functions EMB Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_emb_tmr4_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE; + + /* PWM */ + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState = EMB_TMR4_PWM_U_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState = EMB_TMR4_PWM_V_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState = EMB_TMR4_PWM_W_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR4. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR4_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState)); + DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState)); + DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState)); + DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR4_PWM_U_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_U_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_V_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_V_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_W_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_W_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel)); + + /* OSC */ + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State); + u32Reg1Value |= pstcEmbInit->stcCmp.u32Cmp3State; + u32Reg1Value |= pstcEmbInit->stcCmp.u32Cmp4State; + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel); + u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState); + + EMB_DeInit(EMBx); + + WRITE_REG32(EMBx->CTL2, u32Reg2Value); + WRITE_REG32(EMBx->CTL1, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_emb_tmr6_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE; + /* PWM */ + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState = EMB_TMR6_1_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState = EMB_TMR6_2_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState = EMB_TMR6_3_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel = EMB_DETECT_TMR6_4_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState = EMB_TMR6_4_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState = EMB_TMR6_5_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState = EMB_TMR6_6_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel = EMB_DETECT_TMR6_7_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState = EMB_TMR6_7_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel = EMB_DETECT_TMR6_8_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState = EMB_TMR6_8_PWM_DISABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR6. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR6_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState)); + DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState)); + DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState)); + DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR6_1_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_1_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_2_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_2_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_3_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_3_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_4_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_4_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_5_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_5_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_6_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_6_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_7_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_7_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_8_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_8_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel)); + + /* OSC */ + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel); + u32Reg1Value |= (pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState | \ + pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState | \ + pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel | \ + pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel | \ + pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State); + u32Reg1Value |= pstcEmbInit->stcCmp.u32Cmp4State; + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel); + u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState); + + EMB_DeInit(EMBx); + + WRITE_REG32(EMBx->CTL2, u32Reg2Value); + WRITE_REG32(EMBx->CTL1, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EMB function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @retval None + */ +void EMB_DeInit(CM_EMB_TypeDef *EMBx) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); +} + +/** + * @brief Set the EMB interrupt function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32IntType EMB interrupt source + * This parameter can be any composed value of the macros group @ref EMB_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_VALID_EMB_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(EMBx->INTEN, u32IntType); + } else { + CLR_REG32_BIT(EMBx->INTEN, u32IntType); + } +} + +/** + * @brief Get EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value(prefix with EMB_FLAG) of the macros group @ref EMB_Flag_State. + * @retval None + * @note This parameter u32Flag prefix with EMB_FLAG(eg EMB_FLAG_CMP) of the macros group @ref EMB_Flag_State. + */ +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + SET_REG32_BIT(EMBx->STATCLR, u32Flag); +} + +/** + * @brief Clear EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value of the macros group @ref EMB_Flag_State. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + return (READ_REG32_BIT(EMBx->STAT, u32Flag) == 0UL) ? RESET : SET; +} + +/** + * @brief Start/stop EMB brake by software control + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(EMBx->SOE, enNewState); +} + +/** + * @brief Set EMB release PWM condition for the specified event. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Event Monitor event + * This parameter can be any composed value of the macros group @ref EMB_Monitor_Event. + * @param [in] u32Cond Release PWM condition + * This parameter can be one of the macros group @ref EMB_Release_TMR_PWM_Condition + * @arg EMB_RELEASE_PWM_COND_FLAG_ZERO: Release PWM when flag bit of the specified event is zero + * @arg EMB_RELEASE_PWM_COND_STAT_ZERO: Release PWM when state bit of the specified event is zero + * @retval None + */ +void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_MONITOR_EVT(u32Event)); + DDL_ASSERT(IS_EMB_RELEASE_PWM_COND(u32Cond)); + + if (EMB_RELEASE_PWM_COND_FLAG_ZERO == u32Cond) { + CLR_REG32_BIT(EMBx->RLSSEL, u32Event); + } else { + SET_REG32_BIT(EMBx->RLSSEL, u32Event); + } +} + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_eth.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_eth.c new file mode 100644 index 0000000000..1181ee22e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_eth.c @@ -0,0 +1,4200 @@ +/** + ******************************************************************************* + * @file hc32_ll_eth.c + * @brief This file provides firmware functions to manage the Ethernet MAC + * Controller(ETH). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_eth.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ETH ETH + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (LL_ETH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ETH_Local_Macros ETH Local Macros + * @{ + */ + +/* Ethernet register Mask */ +#define ETH_MAC_IFCONFR_CLR_MASK (ETH_MAC_IFCONFR_RCKINV | ETH_MAC_IFCONFR_TCKINV) +#define ETH_MAC_CONFIGR_CLR_MASK (0x72CF7EF0UL) +#define ETH_MAC_FLOCTLR_CLR_MASK (0xFFFF00BEUL) +#define ETH_MAC_FLTCTLR_CLR_MASK (0x802107FFUL) +#define ETH_MAC_SMIADDR_CLR_MASK (0x0000FFC3UL) +#define ETH_DMA_BUSMODR_CLR_MASK (0x0FFFFFFEUL) +#define ETH_DMA_OPRMODR_CLR_MASK (0x0721C0FCUL) +#define ETH_PTP_TSPCTLR_CLR_MASK (0x0007FE02UL) + +/* Ethernet MAC Address byte length */ +#define ETH_MAC_ADDR_BYTE_LEN (6U) +/* Ethernet DMA Tx descriptors Collision Count Shift */ +#define ETH_DMA_TXDESC_COLLISION_CNT_SHIFT (3UL) +/* Ethernet DMA Rx descriptors Frame Length Shift */ +#define ETH_DMA_RXDESC_FRAME_LEN_SHIFT (16UL) +/* Ethernet DMA Tx/Rx descriptors Buffer2 Size Shift */ +#define ETH_DMA_DESC_BUF2_SIZE_SHIFT (16UL) +/* Ethernet Remote Wake-up frame register length */ +#define ETH_WAKEUP_REG_LEN (8U) +/* Ethernet PTP PPS channel 1 time register address Shift */ +#define ETH_PTP_PPS1_TIME_REG_ADDR_SHIFT (0x64U) + +/* Wait timeout(ms) */ +#define ETH_WR_REG_TIMEOUT (50UL) +#define ETH_SW_RST_TIMEOUT (200UL) +#define ETH_LINK_STATUS_TIMEOUT (3000UL) +#define ETH_AUTO_NEGO_CPLT_TIMEOUT (1000UL) + +/** Get the specified register address */ +#define ETH_MAC_MACADHR_ADDR(__SHIFT__) (__IO uint32_t *)((uint32_t)(&(CM_ETH->MAC_MACADHR0)) + \ + (uint32_t)(__SHIFT__)) +#define ETH_MAC_MACADLR_ADDR(__SHIFT__) (__IO uint32_t *)((uint32_t)(&(CM_ETH->MAC_MACADLR0)) + \ + (uint32_t)(__SHIFT__)) +#define ETH_PTP_TMTSECR_ADDR(__SHIFT__) (__IO uint32_t *)((uint32_t)(&(CM_ETH->PTP_TMTSECR0)) + \ + (uint32_t)(__SHIFT__)) +#define ETH_PTP_TMTNSER_ADDR(__SHIFT__) (__IO uint32_t *)((uint32_t)(&(CM_ETH->PTP_TMTNSER0)) + \ + (uint32_t)(__SHIFT__)) + +/** + * @defgroup ETH_Check_Parameters_Validity ETH Check Parameters Validity + * @{ + */ +#define IS_ETH_PHY_ADDR(x) ((x) < 0x20U) +#define IS_ETH_PHY_REG(x) ((x) < 0x20U) + +#define IS_ETH_AUTO_NEGO(x) \ +( ((x) == ETH_AUTO_NEGO_DISABLE) || \ + ((x) == ETH_AUTO_NEGO_ENABLE)) + +#define IS_ETH_MAC_IF(x) \ +( ((x) == ETH_MAC_IF_MII) || \ + ((x) == ETH_MAC_IF_RMII)) + +#define IS_ETH_MAC_SPEED(x) \ +( ((x) == ETH_MAC_SPEED_10M) || \ + ((x) == ETH_MAC_SPEED_100M)) + +#define IS_ETH_MAC_DUPLEX_MD(x) \ +( ((x) == ETH_MAC_DUPLEX_MD_HALF) || \ + ((x) == ETH_MAC_DUPLEX_MD_FULL)) + +#define IS_ETH_MAC_CHECKSUM_MD(x) \ +( ((x) == ETH_MAC_CHECKSUM_MD_SW) || \ + ((x) == ETH_MAC_CHECKSUM_MD_HW)) + +#define IS_ETH_RX_MD(x) \ +( ((x) == ETH_RX_MD_POLLING) || \ + ((x) == ETH_RX_MD_INT)) + +#define IS_ETH_MAC_TX_CLK_POLARITY(x) \ +( ((x) == ETH_MAC_TX_CLK_POLARITY_KEEP) || \ + ((x) == ETH_MAC_TX_CLK_POLARITY_INVERSE)) + +#define IS_ETH_MAC_RX_CLK_POLARITY(x) \ +( ((x) == ETH_MAC_RX_CLK_POLARITY_KEEP) || \ + ((x) == ETH_MAC_RX_CLK_POLARITY_INVERSE)) + +#define IS_ETH_MAC_SRC_ADDR_MD(x) \ +( ((x) == ETH_MAC_SRC_ADDR_MD_BY_DMA_TXDESC) || \ + ((x) == ETH_MAC_SRC_ADDR_MD_INSTER_MACADDR0) || \ + ((x) == ETH_MAC_SRC_ADDR_MD_REPLACE_MACADDR0) || \ + ((x) == ETH_MAC_SRC_ADDR_MD_INSTER_MACADDR1) || \ + ((x) == ETH_MAC_SRC_ADDR_MD_REPLACE_MACADDR1)) + +#define IS_ETH_MAC_TYPE_FRAME_STRIP_FCS(x) \ +( ((x) == ETH_MAC_TYPE_FRAME_STRIP_FCS_DISABLE) || \ + ((x) == ETH_MAC_TYPE_FRAME_STRIP_FCS_ENABLE)) + +#define IS_ETH_MAC_WATCHDOG(x) \ +( ((x) == ETH_MAC_WATCHDOG_DISABLE) || \ + ((x) == ETH_MAC_WATCHDOG_ENABLE)) + +#define IS_ETH_MAC_JABBER(x) \ +( ((x) == ETH_MAC_JABBER_DISABLE) || \ + ((x) == ETH_MAC_JABBER_ENABLE)) + +#define IS_ETH_MAC_INTERFRAME_GAP(x) \ +( ((x) == ETH_MAC_INTERFRAME_GAP_96BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_88BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_80BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_72BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_64BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_56BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_48BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_40BIT)) + +#define IS_ETH_MAC_CARRIER_SENSE(x) \ +( ((x) == ETH_MAC_CARRIER_SENSE_DISABLE) || \ + ((x) == ETH_MAC_CARRIER_SENSE_ENABLE)) + +#define IS_ETH_MAC_RX_OWN(x) \ +( ((x) == ETH_MAC_RX_OWN_DISABLE) || \ + ((x) == ETH_MAC_RX_OWN_ENABLE)) + +#define IS_ETH_MAC_CHECKSUM_OFFLOAD(x) \ +( ((x) == ETH_MAC_CHECKSUM_OFFLOAD_DISABLE) || \ + ((x) == ETH_MAC_CHECKSUM_OFFLOAD_ENABLE)) + +#define IS_ETH_MAC_RETRY_TRANS(x) \ +( ((x) == ETH_MAC_RETRY_TRANS_DISABLE) || \ + ((x) == ETH_MAC_RETRY_TRANS_ENABLE)) + +#define IS_ETH_MAC_AUTO_STRIP_PAD_FCS(x) \ +( ((x) == ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE) || \ + ((x) == ETH_MAC_AUTO_STRIP_PAD_FCS_ENABLE)) + +#define IS_ETH_MAC_BACKOFF_LIMIT(x) \ +( ((x) == ETH_MAC_BACKOFF_LIMIT10) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT8) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT4) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT1)) + +#define IS_ETH_MAC_DEFERRAL_CHECK(x) \ +( ((x) == ETH_MAC_DEFERRAL_CHECK_DISABLE) || \ + ((x) == ETH_MAC_DEFERRAL_CHECK_ENABLE)) + +#define IS_ETH_MAC_ZERO_QUANTA_PAUSE(x) \ +( ((x) == ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE) || \ + ((x) == ETH_MAC_ZERO_QUANTA_PAUSE_ENABLE)) + +#define IS_ETH_MAC_PAUSE_LOW_THRESHOLD(x) \ +( ((x) == ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS4) || \ + ((x) == ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS28) || \ + ((x) == ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS144) || \ + ((x) == ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS256)) + +#define IS_ETH_MAC_UNICAST_PAUSE_FRAME_DETECT(x) \ +( ((x) == ETH_MAC_UNICAST_PAUSE_FRAME_DETECT_DISABLE) || \ + ((x) == ETH_MAC_UNICAST_PAUSE_FRAME_DETECT_ENABLE)) + +#define IS_ETH_MAC_RX_FLOW_CTRL(x) \ +( ((x) == ETH_MAC_RX_FLOW_CTRL_DISABLE) || \ + ((x) == ETH_MAC_RX_FLOW_CTRL_ENABLE)) + +#define IS_ETH_MAC_TRANS_FLOW_CTRL(x) \ +( ((x) == ETH_MAC_TRANS_FLOW_CTRL_DISABLE) || \ + ((x) == ETH_MAC_TRANS_FLOW_CTRL_ENABLE)) + +#define IS_ETH_MAC_RX_ALL(x) \ +( ((x) == ETH_MAC_RX_ALL_DISABLE) || \ + ((x) == ETH_MAC_RX_ALL_ENABLE)) + +#define IS_ETH_MAC_DROP_NOT_TCPUDP(x) \ +( ((x) == ETH_MAC_DROP_NOT_TCPUDP_DISABLE) || \ + ((x) == ETH_MAC_DROP_NOT_TCPUDP_ENABLE)) + +#define IS_ETH_MAC_VLAN_TAG_FILTER(x) \ +( ((x) == ETH_MAC_VLAN_TAG_FILTER_DISABLE) || \ + ((x) == ETH_MAC_VLAN_TAG_FILTER_ENABLE)) + +#define IS_ETH_MAC_SRC_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_SRC_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_MAC_SRC_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_SRC_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_PASS_CTRL_FRAME(x) \ +( ((x) == ETH_MAC_PASS_CTRL_FRAME_BLOCK_ALL) || \ + ((x) == ETH_MAC_PASS_CTRL_FRAME_FORWARD_NOT_PAUSE) || \ + ((x) == ETH_MAC_PASS_CTRL_FRAME_FORWARD_ALL) || \ + ((x) == ETH_MAC_PASS_CTRL_FRAME_FORWARD_PASS_FILTER)) + +#define IS_ETH_MAC_BROADCAST_FRAME(x) \ +( ((x) == ETH_MAC_RX_BROADCAST_FRAME_DISABLE) || \ + ((x) == ETH_MAC_RX_BROADCAST_FRAME_ENABLE)) + +#define IS_ETH_MAC_DEST_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_DEST_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_DEST_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_MULTICAST_FRAME_FILTER(x) \ +( ((x) == ETH_MAC_MULTICAST_FRAME_FILTER_NONE) || \ + ((x) == ETH_MAC_MULTICAST_FRAME_FILTER_PERFECT) || \ + ((x) == ETH_MAC_MULTICAST_FRAME_FILTER_HASHTABLE) || \ + ((x) == ETH_MAC_MULTICAST_FRAME_FILTER_PERFECT_HASHTABLE)) + +#define IS_ETH_MAC_UNICAST_FRAME_FILTER(x) \ +( ((x) == ETH_MAC_UNICAST_FRAME_FILTER_PERFECT) || \ + ((x) == ETH_MAC_UNICAST_FRAME_FILTER_HASHTABLE) || \ + ((x) == ETH_MAC_UNICAST_FRAME_FILTER_PERFECT_HASHTABLE)) + +#define IS_ETH_MAC_PROMISCUOUS_MD(x) \ +( ((x) == ETH_MAC_PROMISCUOUS_MD_DISABLE) || \ + ((x) == ETH_MAC_PROMISCUOUS_MD_ENABLE)) + +#define IS_ETH_MAC_TXVLAN_MD(x) \ +( ((x) == ETH_MAC_TXVLAN_MD_BY_DMA_TXDESC) || \ + ((x) == ETH_MAC_TXVLAN_MD_BYPASS) || \ + ((x) == ETH_MAC_TXVLAN_MD_REMOVE_TAG) || \ + ((x) == ETH_MAC_TXVLAN_MD_INSERT_TAG) || \ + ((x) == ETH_MAC_TXVLAN_MD_REPLACE_TAG)) + +#define IS_ETH_MAC_RXVLAN_FILTER(x) \ +( ((x) == ETH_MAC_RXVLAN_FILTER_NORMAL) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_INVERSE) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_NORMAL_HASHTABLE) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_INVERSE_HASHTABLE)) + +#define IS_ETH_MAC_RXVLAN_CMP(x) \ +( ((x) == ETH_MAC_RXVLAN_CMP_16BIT) || \ + ((x) == ETH_MAC_RXVLAN_CMP_12BIT)) + +#define IS_ETH_MAC_L4_DEST_PORT_FILTER(x) \ +( ((x) == ETH_MAC_L4_DEST_PORT_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L4_DEST_PORT_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L4_DEST_PORT_FILTER_INVERSE)) + +#define IS_ETH_MAC_L4_SRC_PORT_FILTER(x) \ +( ((x) == ETH_MAC_L4_SRC_PORT_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L4_SRC_PORT_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L4_SRC_PORT_FILTER_INVERSE)) + +#define IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(x) \ +( ((x) == ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP) || \ + ((x) == ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP)) + +#define IS_ETH_MAC_L3_DEST_ADDR_FILTER_MASK(x) \ +( ((x) | ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT30_0) == \ + ETH_MAC_L3_DEST_ADDR_FILTER_MASK_BIT30_0) + +#define IS_ETH_MAC_L3_SRC_ADDR_FILTER_MASK(x) \ +( ((x) | ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT30_0) == \ + ETH_MAC_L3_SRC_ADDR_FILTER_MASK_BIT30_0) + +#define IS_ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK(x) \ +( ((x) | ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT126_0) == \ + ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_BIT126_0) + +#define IS_ETH_MAC_L3_DEST_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_L3_DEST_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L3_DEST_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L3_DEST_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_L3_SRC_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_L3_SRC_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L3_SRC_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L3_SRC_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(x) \ +( ((x) == ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4) || \ + ((x) == ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6)) + +#define IS_ETH_MAC_ADDR_NORMAL_INDEX(x) \ +( ((x) == ETH_MAC_ADDR_IDX0) || \ + ((x) == ETH_MAC_ADDR_IDX1) || \ + ((x) == ETH_MAC_ADDR_IDX2) || \ + ((x) == ETH_MAC_ADDR_IDX3) || \ + ((x) == ETH_MAC_ADDR_IDX4)) + +#define IS_ETH_MAC_ADDR_SPEC_INDEX(x) \ +( ((x) == ETH_MAC_ADDR_IDX1) || \ + ((x) == ETH_MAC_ADDR_IDX2) || \ + ((x) == ETH_MAC_ADDR_IDX3) || \ + ((x) == ETH_MAC_ADDR_IDX4)) + +#define IS_ETH_MAC_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_MAC_ADDR_FILTER_PERFECT_DEST_ADDR) || \ + ((x) == ETH_MAC_ADDR_FILTER_PERFECT_SRC_ADDR)) + +#define IS_ETH_MAC_ADDR_MASK(x) \ +( ((x) | ETH_MAC_ADDR_MASK_ALL) == ETH_MAC_ADDR_MASK_ALL) + +#define IS_ETH_MAC_INT_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MAC_INT_FLAG_ALL) == ETH_MAC_INT_FLAG_ALL)) + +#define IS_ETH_MAC_INT(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MAC_INT_ALL) == ETH_MAC_INT_ALL)) + +#define IS_ETH_DMA_BURST_MD(x) \ +( ((x) == ETH_DMA_BURST_MD_NORMAL) || \ + ((x) == ETH_DMA_BURST_MD_FIXED) || \ + ((x) == ETH_DMA_BURST_MD_MIXED)) + +#define IS_ETH_DMA_ADDR_ALIGN(x) \ +( ((x) == ETH_DMA_ADDR_ALIGN_DISABLE) || \ + ((x) == ETH_DMA_ADDR_ALIGN_ENABLE)) + +#define IS_ETH_DMA_RX_BURST_LEN(x) \ +( ((x) == ETH_DMA_RX_BURST_LEN_1BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_2BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_4BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_16BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_32BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_8BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_16BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_32BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_64BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_128BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LEN_8XPBL_256BEAT)) + +#define IS_ETH_DMA_TX_BURST_LEN(x) \ +( ((x) == ETH_DMA_TX_BURST_LEN_1BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_2BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_4BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_16BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_32BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_8BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_16BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_32BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_64BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_128BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LEN_8XPBL_256BEAT)) + +#define IS_ETH_DMA_ENHANCE_DESC(x) \ +( ((x) == ETH_DMA_ENHANCE_DESC_DISABLE) || \ + ((x) == ETH_DMA_ENHANCE_DESC_ENABLE)) + +#define IS_ETH_DMA_DESC_SKIP_LEN(x) ((x) < 0x20U) + +#define IS_ETH_DMA_PRIO_ARBITRATION(x) \ +( ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_1_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_2_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_3_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_4_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_1_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_2_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_3_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_4_1) || \ + ((x) == ETH_DMA_ARBITRATION_FIXED_RX_PRIOR_TX) || \ + ((x) == ETH_DMA_ARBITRATION_FIXED_TX_PRIOR_RX)) + +#define IS_ETH_DMA_DROP_CHECKSUM_ERR_FRAME(x) \ +( ((x) == ETH_DMA_DROP_CHECKSUM_ERR_FRAME_DISABLE) || \ + ((x) == ETH_DMA_DROP_CHECKSUM_ERR_FRAME_ENABLE)) + +#define IS_ETH_DMA_RX_STORE_FORWARD(x) \ +( ((x) == ETH_DMA_RX_STORE_FORWARD_DISABLE) || \ + ((x) == ETH_DMA_RX_STORE_FORWARD_ENABLE)) + +#define IS_ETH_DMA_FLUSH_RX_FRAME(x) \ +( ((x) == ETH_DMA_FLUSH_RX_FRAME_DISABLE) || \ + ((x) == ETH_DMA_FLUSH_RX_FRAME_ENABLE)) + +#define IS_ETH_DMA_TRANS_STORE_FORWARD(x) \ +( ((x) == ETH_DMA_TRANS_STORE_FORWARD_DISABLE) || \ + ((x) == ETH_DMA_TRANS_STORE_FORWARD_ENABLE)) + +#define IS_ETH_DMA_TRANS_THRESHOLD(x) \ +( ((x) == ETH_DMA_TRANS_THRESHOLD_64BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_128BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_192BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_256BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_40BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_32BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_24BYTE) || \ + ((x) == ETH_DMA_TRANS_THRESHOLD_16BYTE)) + +#define IS_ETH_DMA_FORWARD_ERR_FRAME(x) \ +( ((x) == ETH_DMA_FORWARD_ERR_FRAME_DISABLE) || \ + ((x) == ETH_DMA_FORWARD_ERR_FRAME_ENABLE)) + +#define IS_ETH_DMA_FORWARD_UNDERSIZE_FRAME(x) \ +( ((x) == ETH_DMA_FORWARD_UNDERSIZE_FRAME_DISABLE) || \ + ((x) == ETH_DMA_FORWARD_UNDERSIZE_FRAME_ENABLE)) + +#define IS_ETH_DMA_DROP_JUMBO_FRAME(x) \ +( ((x) == ETH_DMA_DROP_JUMBO_FRAME_DISABLE) || \ + ((x) == ETH_DMA_DROP_JUMBO_FRAME_ENABLE)) + +#define IS_ETH_DMA_RX_THRESHOLD(x) \ +( ((x) == ETH_DMA_RX_THRESHOLD_64BYTE) || \ + ((x) == ETH_DMA_RX_THRESHOLD_32BYTE) || \ + ((x) == ETH_DMA_RX_THRESHOLD_96BYTE) || \ + ((x) == ETH_DMA_RX_THRESHOLD_128BYTE)) + +#define IS_ETH_DMA_SEC_FRAME_OPERA(x) \ +( ((x) == ETH_DMA_SEC_FRAME_OPERA_DISABLE) || \ + ((x) == ETH_DMA_SEC_FRAME_OPERA_ENABLE)) + +#define IS_ETH_DMA_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_FLAG_ALL) == ETH_DMA_FLAG_ALL)) + +#define IS_ETH_DMA_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_FLAG_CLR_ALL) == ETH_DMA_FLAG_CLR_ALL)) + +#define IS_ETH_DMA_INT(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_INT_ALL) == ETH_DMA_INT_ALL)) + +#define IS_ETH_DMA_MISS_FRAME_TYPE(x) \ +( ((x) == ETH_DMA_OVF_RXFIFO_CNT) || \ + ((x) == ETH_DMA_OVF_MISS_FRAME_CNT)) + +#define IS_ETH_DMA_DESC_OWN(x) \ +( ((x) == ETH_DMA_DESC_OWN_CPU) || \ + ((x) == ETH_DMA_DESC_OWN_DMA)) + +#define IS_ETH_DMA_DESC_BUF(x) \ +( ((x) == ETH_DMA_DESC_BUF1) || \ + ((x) == ETH_DMA_DESC_BUF2)) + +#define IS_ETH_DMA_TXDESC_BUF_SIZE(x) ((x) <= 0x1FFFFFFFUL) + +#define IS_ETH_DMA_TXDESC_CHECKSUM_CTRL(x) \ +( ((x) == ETH_DMA_TXDESC_CHECKSUM_BYPASS) || \ + ((x) == ETH_DMA_TXDESC_CHECKSUM_IPV4_HEADER) || \ + ((x) == ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_SEGMENT) || \ + ((x) == ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_FULL)) + +#define IS_ETH_DMA_TXDESC_VLAN_CTRL(x) \ +( ((x) == ETH_DMA_TXDESC_VLAN_BYPASS) || \ + ((x) == ETH_DMA_TXDESC_VLAN_REMOVE_TAG) || \ + ((x) == ETH_DMA_TXDESC_VLAN_INSERT_TAG) || \ + ((x) == ETH_DMA_TXDESC_VLAN_REPLACE_TAG)) + +#define IS_ETH_DMA_TXDESC_SRC_ADDR_CTRL(x) \ +( ((x) == ETH_DMA_TXDESC_SRC_ADDR_BYPASS) || \ + ((x) == ETH_DMA_TXDESC_SRC_ADDR_INSTER_MACADDR0) || \ + ((x) == ETH_DMA_TXDESC_SRC_ADDR_REPLACE_MACADDR0) || \ + ((x) == ETH_DMA_TXDESC_SRC_ADDR_INSTER_MACADDR1) || \ + ((x) == ETH_DMA_TXDESC_SRC_ADDR_REPLACE_MACADDR1)) + +#define IS_ETH_PMT_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_PMT_FLAG_ALL) == ETH_PMT_FLAG_ALL)) + +#define IS_ETH_PMT_WAKEUP_SRC(x) \ +( ((x) != 0U) && \ + (((x) | ETH_PMT_WAKEUP_SRC_ALL) == ETH_PMT_WAKEUP_SRC_ALL)) + +#define IS_ETH_MMC_CNT_PRESET_MD(x) \ +( ((x) == ETH_MMC_CNT_PRESET_MD_DISABLE) || \ + ((x) == ETH_MMC_CNT_PRESET_MD_HALF_VALUE) || \ + ((x) == ETH_MMC_CNT_PRESET_MD_FULL_VALUE)) + +#define IS_ETH_MMC_RD_RST(x) \ +( ((x) == ETH_MMC_RD_RST_DISABLE) || \ + ((x) == ETH_MMC_RD_RST_ENABLE)) + +#define IS_ETH_MMC_CNT_RELOAD(x) \ +( ((x) == ETH_MMC_CNT_RELOAD_DISABLE) || \ + ((x) == ETH_MMC_CNT_RELOAD_ENABLE)) + +#define IS_ETH_MMC_TX_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MMC_FLAG_TX_ALL) == ETH_MMC_FLAG_TX_ALL)) + +#define IS_ETH_MMC_RX_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MMC_FLAG_RX_ALL) == ETH_MMC_FLAG_RX_ALL)) + +#define IS_ETH_MMC_TX_INT(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MMC_INT_TX_ALL) == ETH_MMC_INT_TX_ALL)) + +#define IS_ETH_MMC_RX_INT(x) \ +( ((x) != 0U) && \ + (((x) | ETH_MMC_INT_RX_ALL) == ETH_MMC_INT_RX_ALL)) + +#define IS_ETH_MMC_REG(x) \ +( ((x) == ETH_MMC_REG_TXBRGFR) || \ + ((x) == ETH_MMC_REG_TXMUGFR) || \ + ((x) == ETH_MMC_REG_TXDEEFR) || \ + ((x) == ETH_MMC_REG_TXLCEFR) || \ + ((x) == ETH_MMC_REG_TXECEFR) || \ + ((x) == ETH_MMC_REG_TXCAEFR) || \ + ((x) == ETH_MMC_REG_TXUNGFR) || \ + ((x) == ETH_MMC_REG_TXEDEFR) || \ + ((x) == ETH_MMC_REG_RXBRGFR) || \ + ((x) == ETH_MMC_REG_RXMUGFR) || \ + ((x) == ETH_MMC_REG_RXCREFR) || \ + ((x) == ETH_MMC_REG_RXALEFR) || \ + ((x) == ETH_MMC_REG_RXRUEFR) || \ + ((x) == ETH_MMC_REG_RXUNGFR) || \ + ((x) == ETH_MMC_REG_RXLEEFR) || \ + ((x) == ETH_MMC_REG_RXOREFR)) + +#define IS_ETH_PTP_DEST_ADDR_FILTER(x) \ +( ((x) == ETH_PTP_DEST_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_PTP_DEST_ADDR_FILTER_ENABLE)) + +#define IS_ETH_PTP_DATAGRAM_TYPE(x) \ +( ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_PDELAY)) + +#define IS_ETH_PTP_FRAME_TYPE(x) \ +( ((x) != 0U) && \ + (((x) | ETH_PTP_FRAME_TYPE_ALL) == ETH_PTP_FRAME_TYPE_ALL)) + +#define IS_ETH_PTP_DATAGRAM_VER(x) \ +( ((x) == ETH_PTP_DATAGRAM_VER_IEEE1588V1) || \ + ((x) == ETH_PTP_DATAGRAM_VER_IEEE1588V2)) + +#define IS_ETH_PTP_SUBSEC_SCALE(x) \ +( ((x) == ETH_PTP_SUBSEC_SCALE_HEX) || \ + ((x) == ETH_PTP_SUBSEC_SCALE_DEC)) + +#define IS_ETH_PTP_CALIB_MD(x) \ +( ((x) == ETH_PTP_CALIB_MD_COARSE) || \ + ((x) == ETH_PTP_CALIB_MD_FINE)) + +#define IS_ETH_PTP_TIME_UPDATE_SIGN(x) \ +( ((x) == ETH_PTP_TIME_UPDATE_SIGN_MINUS) || \ + ((x) == ETH_PTP_TIME_UPDATE_SIGN_PLUS)) + +#define IS_ETH_PTP_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | ETH_PTP_FLAG_ALL) == ETH_PTP_FLAG_ALL)) + +#define IS_ETH_PPS_CH(x) \ +( ((x) == ETH_PPS_CH0) || \ + ((x) == ETH_PPS_CH1)) + +#define IS_ETH_PPS_TRIG_FUNC(x) \ +( ((x) == ETH_PPS_TRIG_FUNC_INT_EVT) || \ + ((x) == ETH_PPS_TRIG_FUNC_INT_PPS_EVT) || \ + ((x) == ETH_PPS_TRIG_FUNC_PPS_EVT)) + +#define IS_ETH_PPS_OUTPUT_MD(x) \ +( ((x) == ETH_PPS_OUTPUT_MD_CONTINUE) || \ + ((x) == ETH_PPS_OUTPUT_MD_ONCE)) + +#define IS_ETH_PPS_OUTPUT_FREQ(x) \ +( ((x) == ETH_PPS_OUTPUT_FREQ_1HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_2HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_4HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_8HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_16HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_32HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_64HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_128HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_256HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_512HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_1024HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_2048HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_4096HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_8192HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_16384HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_32768HZ) || \ + ((x) == ETH_PPS_OUTPUT_ONE_PULSE)) + +#define IS_ETH_PPS1_COMPLEX_FUNC(ch, mode, freq) \ +( ((ch) == ETH_PPS_CH0) || \ + (((mode) == ETH_PPS_OUTPUT_MD_CONTINUE) && \ + ((freq) == ETH_PPS_OUTPUT_ONE_PULSE))) + +#define IS_ETH_PTP_SUB_SEC(x) ((x) <= 0x7FFFFFFFUL) + +#define IS_ETH_DMA_TXDESC_STATUS(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_TXDESC_STATUS_ALL) == ETH_DMA_TXDESC_STATUS_ALL)) + +#define IS_ETH_DMA_RXDESC_STATUS(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_RXDESC_STATUS_ALL) == ETH_DMA_RXDESC_STATUS_ALL)) + +#define IS_ETH_DMA_RXDESC_EXTEND_STATUS(x) \ +( ((x) != 0U) && \ + (((x) | ETH_DMA_RXDESC_EXTEND_STATUS_ALL) == \ + ETH_DMA_RXDESC_EXTEND_STATUS_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Functions ETH Global Functions + * @{ + */ + +/** + * @brief De-Initialize ETH. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t ETH_DeInit(void) +{ + int32_t i32Ret; + + ETH_MAC_DeInit(); + ETH_DMA_DeInit(); + ETH_MACADDR_DeInit(ETH_MAC_ADDR_IDX0); + ETH_MACADDR_DeInit(ETH_MAC_ADDR_IDX1); + ETH_MACADDR_DeInit(ETH_MAC_ADDR_IDX2); + ETH_MACADDR_DeInit(ETH_MAC_ADDR_IDX3); + ETH_MACADDR_DeInit(ETH_MAC_ADDR_IDX4); + ETH_MAC_L3L4FilterDeInit(); + ETH_PTP_DeInit(); + ETH_PPS_DeInit(ETH_PPS_CH0); + ETH_PPS_DeInit(ETH_PPS_CH1); + i32Ret = ETH_MMC_DeInit(); + if (LL_OK == i32Ret) { + i32Ret = ETH_DMA_SoftwareReset(); + } + + return i32Ret; +} + +/** + * @brief Initialize ETH. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] pstcEthInit Pointer to a @ref stc_eth_init_t structure + * @retval int32_t: + * - LL_OK: ETH Initialize success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL or pstcEthInit == NULL or PHY Address error + * - LL_ERR_TIMEOUT: Initialize timeout + */ +int32_t ETH_Init(stc_eth_handle_t *pstcEthHandle, stc_eth_init_t *pstcEthInit) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + uint32_t u32TempReg; + uint32_t u32BusClk; + uint32_t u32PhyTimeout; + uint16_t u16PhyReg = 0U; + + if ((NULL == pstcEthHandle) || (NULL == pstcEthInit)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_AUTO_NEGO(pstcEthHandle->stcCommInit.u16AutoNego)); + DDL_ASSERT(IS_ETH_MAC_CHECKSUM_MD(pstcEthHandle->stcCommInit.u32ChecksumMode)); + DDL_ASSERT(IS_ETH_RX_MD(pstcEthHandle->stcCommInit.u32ReceiveMode)); + DDL_ASSERT(IS_ETH_MAC_IF(pstcEthHandle->stcCommInit.u32Interface)); + + /* Select MII or RMII Mode*/ + MODIFY_REG32(CM_ETH->MAC_IFCONFR, ETH_MAC_IFCONFR_IFSEL, pstcEthHandle->stcCommInit.u32Interface); + /* ETH software reset */ + if (LL_OK != ETH_DMA_SoftwareReset()) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Get ETH frequency value */ + u32BusClk = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, + CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + /* Set SMIC bits depending on PCLK1 clock value */ + /* PCLK1 Clock Range between 20-35 MHz */ + if ((u32BusClk >= 20000000UL) && (u32BusClk < 35000000UL)) { + u32TempReg = ETH_MAC_SMIADDR_SMIC_1; + } else if ((u32BusClk >= 35000000UL) && (u32BusClk < 60000000UL)) { /* PCLK1 Clock Range between 35-60 MHz */ + u32TempReg = ETH_MAC_SMIADDR_SMIC_1 | ETH_MAC_SMIADDR_SMIC_0; + } else if ((u32BusClk >= 60000000UL) && (u32BusClk < 100000000UL)) { /* PCLK1 Clock Range between 60-100 MHz */ + u32TempReg = 0UL; + } else { /* PCLK1 Clock Range between 100-120 MHz */ + u32TempReg = ETH_MAC_SMIADDR_SMIC_0; + } + /* Configure the ETH MDC Clock Range */ + MODIFY_REG32(CM_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIC, u32TempReg); + + /* PHY initialization and configuration */ + /* Reset the PHY */ + if (LL_OK != (ETH_PHY_WriteReg(pstcEthHandle, PHY_BCR, PHY_SOFT_RESET))) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Delay to assure PHY reset */ + DDL_DelayMS(ETH_PHY_RST_DELAY); + if (ETH_AUTO_NEGO_DISABLE != pstcEthHandle->stcCommInit.u16AutoNego) { + u32PhyTimeout = ETH_PHY_RD_TIMEOUT * (HCLK_VALUE / 20000UL); + /* Wait for linke status */ + u32Count = ETH_LINK_STATUS_TIMEOUT * (HCLK_VALUE / 20000UL); + while (PHY_LINK_STATUS != (u16PhyReg & PHY_LINK_STATUS)) { + if (0UL == u32Count) { + break; + } + if (LL_ERR_TIMEOUT == ETH_PHY_ReadReg(pstcEthHandle, PHY_BSR, &u16PhyReg)) { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - u32PhyTimeout) : 0UL; + } else { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - (u32PhyTimeout / 150U)) : 0UL; + } + } + + if ((0x0000U == u16PhyReg) || (0xFFFFU == u16PhyReg)) { + i32Ret = LL_ERR_INVD_PARAM; + } else if (PHY_LINK_STATUS != (u16PhyReg & PHY_LINK_STATUS)) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Enable Auto-Negotiation */ + if (LL_OK != (ETH_PHY_WriteReg(pstcEthHandle, PHY_BCR, PHY_AUTONEGOTIATION))) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Wait until the auto-negotiation will be completed */ + u32Count = ETH_AUTO_NEGO_CPLT_TIMEOUT * (HCLK_VALUE / 20000UL); + while (PHY_AUTONEGO_COMPLETE != (u16PhyReg & PHY_AUTONEGO_COMPLETE)) { + if (0UL == u32Count) { + break; + } + if (LL_ERR_TIMEOUT == ETH_PHY_ReadReg(pstcEthHandle, PHY_BSR, &u16PhyReg)) { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - u32PhyTimeout) : 0UL; + } else { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - (u32PhyTimeout / 150U)) : 0UL; + } + } + + if (PHY_AUTONEGO_COMPLETE != (u16PhyReg & PHY_AUTONEGO_COMPLETE)) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Read the result of the auto-negotiation */ + /* Configure ETH duplex mode according to the result of automatic negotiation */ + if (0U != (u16PhyReg & (uint16_t)(PHY_100BASE_TX_FD | PHY_10BASE_T_FD))) { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_DUPLEX_MD_FULL; + } else { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_DUPLEX_MD_HALF; + } + /* Configure ETH speed according to the result of automatic negotiation */ + if (0U != (u16PhyReg & (uint16_t)(PHY_100BASE_TX_FD | PHY_100BASE_TX_HD))) { + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_100M; + } else { + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_10M; + } + } + } + } + } else { /* AutoNegotiation Disable */ + DDL_ASSERT(IS_ETH_MAC_SPEED(pstcEthHandle->stcCommInit.u32Speed)); + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MD(pstcEthHandle->stcCommInit.u32DuplexMode)); + + if (LL_OK != ETH_PHY_WriteReg(pstcEthHandle, PHY_BCR, + ((uint16_t)(pstcEthHandle->stcCommInit.u32DuplexMode >> 3U) | + (uint16_t)(pstcEthHandle->stcCommInit.u32Speed >> 1U)))) { + i32Ret = LL_ERR_TIMEOUT; + } else { + /* Delay to assure PHY configuration */ + DDL_DelayMS(ETH_PHY_CONFIG_DELAY); + } + } + } + + /* Auto-negotiation failed */ + if (LL_OK != i32Ret) { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_DUPLEX_MD_FULL; + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_100M; + } + /* Config checksum offload */ + if (ETH_MAC_CHECKSUM_MD_HW == pstcEthHandle->stcCommInit.u32ChecksumMode) { + pstcEthInit->stcMacInit.u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLOAD_ENABLE; + } else { + pstcEthInit->stcMacInit.u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLOAD_DISABLE; + } + + /* Config MAC,DMA,MMC and PTP */ + (void)ETH_MAC_Init(pstcEthHandle, &pstcEthInit->stcMacInit); + (void)ETH_DMA_Init(&pstcEthInit->stcDmaInit); + /* Mask all MMC interrupts */ + ETH_MMC_TxIntCmd(ETH_MMC_INT_TX_ALL, DISABLE); + ETH_MMC_RxIntCmd(ETH_MMC_INT_RX_ALL, DISABLE); + /* Enable the ETH Rx Interrupt */ + if (ETH_RX_MD_INT == pstcEthHandle->stcCommInit.u32ReceiveMode) { + ETH_DMA_IntCmd(ETH_DMA_INT_NIE | ETH_DMA_INT_RIE, ENABLE); + } + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_comm_init_t to default values. + * @param [out] pstcCommInit Pointer to a @ref stc_eth_comm_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcCommInit == NULL + */ +int32_t ETH_CommStructInit(stc_eth_comm_init_t *pstcCommInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCommInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcCommInit->u16AutoNego = ETH_AUTO_NEGO_ENABLE; + pstcCommInit->u16PhyAddr = ETH_PHY_ADDR; + pstcCommInit->au8MacAddr[0] = ETH_MAC_ADDR0; + pstcCommInit->au8MacAddr[1] = ETH_MAC_ADDR1; + pstcCommInit->au8MacAddr[2] = ETH_MAC_ADDR2; + pstcCommInit->au8MacAddr[3] = ETH_MAC_ADDR3; + pstcCommInit->au8MacAddr[4] = ETH_MAC_ADDR4; + pstcCommInit->au8MacAddr[5] = ETH_MAC_ADDR5; + pstcCommInit->u32Interface = ETH_MAC_IF_MII; + pstcCommInit->u32Speed = ETH_MAC_SPEED_100M; + pstcCommInit->u32DuplexMode = ETH_MAC_DUPLEX_MD_FULL; + pstcCommInit->u32ChecksumMode = ETH_MAC_CHECKSUM_MD_HW; + pstcCommInit->u32ReceiveMode = ETH_RX_MD_POLLING; + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_init_t to default values. + * @param [out] pstcEthInit Pointer to a @ref stc_eth_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcEthInit == NULL + */ +int32_t ETH_StructInit(stc_eth_init_t *pstcEthInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcEthInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + (void)ETH_MAC_StructInit(&pstcEthInit->stcMacInit); + (void)ETH_DMA_StructInit(&pstcEthInit->stcDmaInit); + } + + return i32Ret; +} + +/** + * @brief Enable MAC and DMA Transmission/Reception + * @param None + * @retval int32_t: + * - LL_OK: Enable success + * - LL_ERR_TIMEOUT: Enable timeout + */ +int32_t ETH_Start(void) +{ + int32_t i32Ret; + + /* Flush Transmit FIFO */ + i32Ret = ETH_DMA_FlushTransFIFO(); + if (LL_OK == i32Ret) { + /* Enable MAC Transmit */ + ETH_MAC_TransCmd(ENABLE); + /* Enable MAC Receive */ + ETH_MAC_ReceiveCmd(ENABLE); + /* Enable DMA Transmit */ + ETH_DMA_TransCmd(ENABLE); + /* Enable DMA Receive */ + ETH_DMA_ReceiveCmd(ENABLE); + } + + return i32Ret; +} + +/** + * @brief Disable MAC and DMA Transmission/Reception + * @param None + * @retval int32_t: + * - LL_OK: Disable success + * - LL_ERR_TIMEOUT: Disable timeout + */ +int32_t ETH_Stop(void) +{ + int32_t i32Ret; + + /* Disable DMA Transmit */ + ETH_DMA_TransCmd(DISABLE); + /* Disable DMA Receive */ + ETH_DMA_ReceiveCmd(DISABLE); + /* Disable MAC Receive */ + ETH_MAC_ReceiveCmd(DISABLE); + /* Disable MAC Transmit */ + ETH_MAC_TransCmd(DISABLE); + /* Flush Transmit FIFO */ + i32Ret = ETH_DMA_FlushTransFIFO(); + + return i32Ret; +} + +/******************************************************************************/ +/* PHY Functions */ +/******************************************************************************/ +/** + * @brief Write PHY register + * @note More PHY register could be written depending on the used PHY. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u16Reg PHY register address + * This parameter can be one of the following values: + * @arg PHY_BCR: PHY Basic Control Register + * @arg other value: The value range from 1 to 31 + * @param [in] u16Value PHY register value + * @retval int32_t: + * - LL_OK: Write register success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL + * - LL_ERR_TIMEOUT: Write timeout + */ +int32_t ETH_PHY_WriteReg(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t u16Value) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + if (NULL == pstcEthHandle) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDR(pstcEthHandle->stcCommInit.u16PhyAddr)); + DDL_ASSERT(IS_ETH_PHY_REG(u16Reg)); + + /* Set the MAC_SMIDATR register */ + WRITE_REG32(CM_ETH->MAC_SMIDATR, u16Value); + /* Set the MAC_SMIADDR register */ + /* Keep only the MDC Clock Range SMIC[3:0] bits value */ + MODIFY_REG32(CM_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_CLR_MASK, + (((uint32_t)(pstcEthHandle->stcCommInit.u16PhyAddr) << ETH_MAC_SMIADDR_SMIA_POS) | + ((uint32_t)u16Reg << ETH_MAC_SMIADDR_SMIR_POS) | ETH_MAC_SMIADDR_SMIW | ETH_MAC_SMIADDR_SMIB)); + /* Check for the Busy flag */ + u32Count = ETH_PHY_WR_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIB)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + + return i32Ret; +} + +/** + * @brief Read PHY register. + * @note More PHY register could be read depending on the used PHY. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u16Reg PHY register address + * This parameter can be one of the following values: + * @arg PHY_BCR: PHY Basic Control Register + * @arg PHY_BSR: PHY Basic Status Register + * @arg other value: The value range from 2 to 31 + * @param [out] pu16Value Pointer to PHY register value + * @retval int32_t: + * - LL_OK: Read register success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL or pu16Value == NULL + * - LL_ERR_TIMEOUT: Read timeout + */ +int32_t ETH_PHY_ReadReg(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t *pu16Value) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + if ((NULL == pstcEthHandle) || (NULL == pu16Value)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDR(pstcEthHandle->stcCommInit.u16PhyAddr)); + DDL_ASSERT(IS_ETH_PHY_REG(u16Reg)); + + *pu16Value = 0U; + /* Set the MAC_SMIADDR register */ + /* Keep only the MDC Clock Range SMIC[3:0] bits value */ + MODIFY_REG32(CM_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_CLR_MASK, + (((uint32_t)(pstcEthHandle->stcCommInit.u16PhyAddr) << ETH_MAC_SMIADDR_SMIA_POS) | + ((uint32_t)u16Reg << ETH_MAC_SMIADDR_SMIR_POS) | ETH_MAC_SMIADDR_SMIB)); + /* Check for the Busy flag */ + u32Count = ETH_PHY_RD_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIB)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + if (LL_ERR_TIMEOUT != i32Ret) { + /* Get the MAC_SMIDATR value */ + *pu16Value = (uint16_t)(READ_REG32(CM_ETH->MAC_SMIDATR)); + } + } + + return i32Ret; +} + +/** + * @brief Enabele or disable PHY loopback. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Set loopback success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL + * - LL_ERR: Communication error + */ +int32_t ETH_PHY_LoopBackCmd(stc_eth_handle_t *pstcEthHandle, en_functional_state_t enNewState) +{ + int32_t i32Ret; + uint16_t u16Value; + + if (NULL == pstcEthHandle) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDR(pstcEthHandle->stcCommInit.u16PhyAddr)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + i32Ret = ETH_PHY_ReadReg(pstcEthHandle, PHY_BCR, &u16Value); + if (i32Ret == LL_OK) { + if (DISABLE != enNewState) { + SET_REG16_BIT(u16Value, PHY_LOOPBACK); + } else { + CLR_REG16_BIT(u16Value, PHY_LOOPBACK); + } + if (LL_OK != ETH_PHY_WriteReg(pstcEthHandle, PHY_BCR, u16Value)) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/******************************************************************************/ +/* MAC Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC. + * @param None + * @retval None + */ +void ETH_MAC_DeInit(void) +{ + WRITE_REG32(CM_ETH->MAC_IFCONFR, 0UL); + WRITE_REG32(CM_ETH->MAC_CONFIGR, 0x00008000UL); + MODIFY_REG32(CM_ETH->MAC_FLTCTLR, ETH_MAC_FLTCTLR_CLR_MASK, 0UL); + WRITE_REG32(CM_ETH->MAC_FLOCTLR, 0UL); + WRITE_REG32(CM_ETH->MAC_INTMSKR, 0UL); + WRITE_REG32(CM_ETH->MAC_SMIADDR, 0UL); + WRITE_REG32(CM_ETH->MAC_SMIDATR, 0UL); + WRITE_REG32(CM_ETH->MAC_RTWKFFR, 0UL); + WRITE_REG32(CM_ETH->MAC_PMTCTLR, 0UL); + WRITE_REG32(CM_ETH->MAC_HASHTLR, 0UL); + WRITE_REG32(CM_ETH->MAC_HASHTHR, 0UL); + WRITE_REG32(CM_ETH->MAC_VTACTLR, 0UL); + WRITE_REG32(CM_ETH->MAC_VTAFLTR, 0UL); + WRITE_REG32(CM_ETH->MAC_VLAHTBR, 0UL); +} + +/** + * @brief Initialize MAC. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] pstcMacInit Pointer to a @ref stc_eth_mac_init_t structure + * @retval int32_t: + * - LL_OK: MAC Initialize success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL or pstcMacInit == NULL + */ +int32_t ETH_MAC_Init(stc_eth_handle_t *pstcEthHandle, const stc_eth_mac_init_t *pstcMacInit) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcEthHandle) || (NULL == pstcMacInit)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_TX_CLK_POLARITY(pstcMacInit->u32TxClockPolarity)); + DDL_ASSERT(IS_ETH_MAC_RX_CLK_POLARITY(pstcMacInit->u32RxClockPolarity)); + DDL_ASSERT(IS_ETH_MAC_SRC_ADDR_MD(pstcMacInit->u32SrcAddrMode)); + DDL_ASSERT(IS_ETH_MAC_TYPE_FRAME_STRIP_FCS(pstcMacInit->u32TypeFrameStripFCS)); + DDL_ASSERT(IS_ETH_MAC_WATCHDOG(pstcMacInit->u32Watchdog)); + DDL_ASSERT(IS_ETH_MAC_JABBER(pstcMacInit->u32Jabber)); + DDL_ASSERT(IS_ETH_MAC_INTERFRAME_GAP(pstcMacInit->u32InterframeGap)); + DDL_ASSERT(IS_ETH_MAC_CARRIER_SENSE(pstcMacInit->u32CarrierSense)); + DDL_ASSERT(IS_ETH_MAC_SPEED(pstcEthHandle->stcCommInit.u32Speed)); + DDL_ASSERT(IS_ETH_MAC_RX_OWN(pstcMacInit->u32ReceiveOwn)); + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MD(pstcEthHandle->stcCommInit.u32DuplexMode)); + DDL_ASSERT(IS_ETH_MAC_CHECKSUM_OFFLOAD(pstcMacInit->u32ChecksumOffload)); + DDL_ASSERT(IS_ETH_MAC_RETRY_TRANS(pstcMacInit->u32RetryTrans)); + DDL_ASSERT(IS_ETH_MAC_AUTO_STRIP_PAD_FCS(pstcMacInit->u32AutoStripPadFCS)); + DDL_ASSERT(IS_ETH_MAC_BACKOFF_LIMIT(pstcMacInit->u32BackOffLimit)); + DDL_ASSERT(IS_ETH_MAC_DEFERRAL_CHECK(pstcMacInit->u32DeferralCheck)); + DDL_ASSERT(IS_ETH_MAC_ZERO_QUANTA_PAUSE(pstcMacInit->u32ZeroQuantaPause)); + DDL_ASSERT(IS_ETH_MAC_PAUSE_LOW_THRESHOLD(pstcMacInit->u32PauseLowThreshold)); + DDL_ASSERT(IS_ETH_MAC_UNICAST_PAUSE_FRAME_DETECT(pstcMacInit->u32UnicastPauseFrame)); + DDL_ASSERT(IS_ETH_MAC_RX_FLOW_CTRL(pstcMacInit->u32ReceiveFlowControl)); + DDL_ASSERT(IS_ETH_MAC_TRANS_FLOW_CTRL(pstcMacInit->u32TransFlowControl)); + DDL_ASSERT(IS_ETH_MAC_RX_ALL(pstcMacInit->u32ReceiveAll)); + DDL_ASSERT(IS_ETH_MAC_DROP_NOT_TCPUDP(pstcMacInit->u32DropNotTcpUdp)); + DDL_ASSERT(IS_ETH_MAC_VLAN_TAG_FILTER(pstcMacInit->u32VlanTagFilter)); + DDL_ASSERT(IS_ETH_MAC_SRC_ADDR_FILTER(pstcMacInit->u32SrcAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_PASS_CTRL_FRAME(pstcMacInit->u32PassControlFrame)); + DDL_ASSERT(IS_ETH_MAC_BROADCAST_FRAME(pstcMacInit->u32BroadcastFrame)); + DDL_ASSERT(IS_ETH_MAC_DEST_ADDR_FILTER(pstcMacInit->u32DestAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_MULTICAST_FRAME_FILTER(pstcMacInit->u32MulticastFrameFilter)); + DDL_ASSERT(IS_ETH_MAC_UNICAST_FRAME_FILTER(pstcMacInit->u32UnicastFrameFilter)); + DDL_ASSERT(IS_ETH_MAC_PROMISCUOUS_MD(pstcMacInit->u32PromiscuousMode)); + DDL_ASSERT(IS_ETH_MAC_TXVLAN_MD(pstcMacInit->u32TxVlanMode)); + DDL_ASSERT(IS_ETH_MAC_RXVLAN_FILTER(pstcMacInit->u32RxVlanFilter)); + DDL_ASSERT(IS_ETH_MAC_RXVLAN_CMP(pstcMacInit->u32RxVlanCompare)); + + /* Set MAC_IFCONFR register */ + MODIFY_REG32(CM_ETH->MAC_IFCONFR, ETH_MAC_IFCONFR_CLR_MASK, + (pstcMacInit->u32TxClockPolarity | pstcMacInit->u32RxClockPolarity)); + /* Set MAC_CONFIGR register */ + MODIFY_REG32(CM_ETH->MAC_CONFIGR, ETH_MAC_CONFIGR_CLR_MASK, + (pstcMacInit->u32SrcAddrMode | pstcMacInit->u32TypeFrameStripFCS | + pstcMacInit->u32Watchdog | pstcMacInit->u32Jabber | + pstcMacInit->u32InterframeGap | pstcMacInit->u32CarrierSense | + pstcEthHandle->stcCommInit.u32Speed | pstcMacInit->u32ReceiveOwn | + pstcMacInit->u32DeferralCheck | pstcEthHandle->stcCommInit.u32DuplexMode | + pstcMacInit->u32ChecksumOffload | pstcMacInit->u32RetryTrans | + pstcMacInit->u32AutoStripPadFCS | pstcMacInit->u32BackOffLimit)); + /* Set MAC_FLOCTLR register */ + MODIFY_REG32(CM_ETH->MAC_FLOCTLR, ETH_MAC_FLOCTLR_CLR_MASK, + ((((uint32_t)pstcMacInit->u16PauseTime) << 16U) | pstcMacInit->u32ZeroQuantaPause | + pstcMacInit->u32PauseLowThreshold | pstcMacInit->u32UnicastPauseFrame | + pstcMacInit->u32ReceiveFlowControl | pstcMacInit->u32TransFlowControl)); + /* Set MAC_FLTCTLR register */ + MODIFY_REG32(CM_ETH->MAC_FLTCTLR, ETH_MAC_FLTCTLR_CLR_MASK, + (pstcMacInit->u32ReceiveAll | pstcMacInit->u32DropNotTcpUdp | + pstcMacInit->u32PromiscuousMode | pstcMacInit->u32VlanTagFilter | + pstcMacInit->u32SrcAddrFilter | pstcMacInit->u32PassControlFrame | + pstcMacInit->u32BroadcastFrame | pstcMacInit->u32DestAddrFilter | + pstcMacInit->u32MulticastFrameFilter | pstcMacInit->u32UnicastFrameFilter)); + /* Set Hash table register */ + WRITE_REG32(CM_ETH->MAC_HASHTLR, pstcMacInit->u32HashTableLow); + WRITE_REG32(CM_ETH->MAC_HASHTHR, pstcMacInit->u32HashTableHigh); + /* Set Tx VLAN register */ + WRITE_REG32(CM_ETH->MAC_VTACTLR, (pstcMacInit->u32TxVlanMode | pstcMacInit->u16TxVlanTag)); + /* Set Rx VLAN register */ + WRITE_REG32(CM_ETH->MAC_VTAFLTR, (pstcMacInit->u32RxVlanFilter | pstcMacInit->u32RxVlanCompare | + pstcMacInit->u16RxVlanTag)); + WRITE_REG32(CM_ETH->MAC_VLAHTBR, pstcMacInit->u16RxVlanHashTable); + /* Config MAC address in ETH MAC0 */ + (void)ETH_MACADDR_SetAddr(ETH_MAC_ADDR_IDX0, pstcEthHandle->stcCommInit.au8MacAddr); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_mac_init_t to default values. + * @param [out] pstcMacInit Pointer to a @ref stc_eth_mac_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcMacInit == NULL + */ +int32_t ETH_MAC_StructInit(stc_eth_mac_init_t *pstcMacInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMacInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMacInit->u32TxClockPolarity = ETH_MAC_TX_CLK_POLARITY_KEEP; + pstcMacInit->u32RxClockPolarity = ETH_MAC_RX_CLK_POLARITY_KEEP; + pstcMacInit->u32SrcAddrMode = ETH_MAC_TXVLAN_MD_BY_DMA_TXDESC; + pstcMacInit->u32TypeFrameStripFCS = ETH_MAC_TYPE_FRAME_STRIP_FCS_DISABLE; + pstcMacInit->u32Watchdog = ETH_MAC_WATCHDOG_ENABLE; + pstcMacInit->u32Jabber = ETH_MAC_JABBER_ENABLE; + pstcMacInit->u32InterframeGap = ETH_MAC_INTERFRAME_GAP_96BIT; + pstcMacInit->u32CarrierSense = ETH_MAC_CARRIER_SENSE_ENABLE; + pstcMacInit->u32ReceiveOwn = ETH_MAC_RX_OWN_ENABLE; + pstcMacInit->u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLOAD_DISABLE; + pstcMacInit->u32RetryTrans = ETH_MAC_RETRY_TRANS_DISABLE; + pstcMacInit->u32AutoStripPadFCS = ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE; + pstcMacInit->u32BackOffLimit = ETH_MAC_BACKOFF_LIMIT10; + pstcMacInit->u32DeferralCheck = ETH_MAC_DEFERRAL_CHECK_DISABLE; + pstcMacInit->u16PauseTime = 0U; + pstcMacInit->u32ZeroQuantaPause = ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE; + pstcMacInit->u32PauseLowThreshold = ETH_MAC_PAUSE_LOW_THRESHOLD_MINUS4; + pstcMacInit->u32UnicastPauseFrame = ETH_MAC_UNICAST_PAUSE_FRAME_DETECT_DISABLE; + pstcMacInit->u32ReceiveFlowControl = ETH_MAC_RX_FLOW_CTRL_DISABLE; + pstcMacInit->u32TransFlowControl = ETH_MAC_TRANS_FLOW_CTRL_DISABLE; + pstcMacInit->u32ReceiveAll = ETH_MAC_RX_ALL_DISABLE; + pstcMacInit->u32DropNotTcpUdp = ETH_MAC_DROP_NOT_TCPUDP_DISABLE; + + pstcMacInit->u32VlanTagFilter = ETH_MAC_VLAN_TAG_FILTER_DISABLE; + pstcMacInit->u32SrcAddrFilter = ETH_MAC_SRC_ADDR_FILTER_DISABLE; + pstcMacInit->u32PassControlFrame = ETH_MAC_PASS_CTRL_FRAME_FORWARD_NOT_PAUSE; + pstcMacInit->u32BroadcastFrame = ETH_MAC_RX_BROADCAST_FRAME_ENABLE; + pstcMacInit->u32DestAddrFilter = ETH_MAC_DEST_ADDR_FILTER_NORMAL; + pstcMacInit->u32MulticastFrameFilter = ETH_MAC_MULTICAST_FRAME_FILTER_PERFECT; + pstcMacInit->u32UnicastFrameFilter = ETH_MAC_UNICAST_FRAME_FILTER_PERFECT; + pstcMacInit->u32PromiscuousMode = ETH_MAC_PROMISCUOUS_MD_DISABLE; + pstcMacInit->u32HashTableHigh = 0UL; + pstcMacInit->u32HashTableLow = 0UL; + pstcMacInit->u32TxVlanMode = ETH_MAC_TXVLAN_MD_BYPASS; + pstcMacInit->u16TxVlanTag = 0U; + pstcMacInit->u32RxVlanFilter = ETH_MAC_RXVLAN_FILTER_NORMAL; + pstcMacInit->u32RxVlanCompare = ETH_MAC_RXVLAN_CMP_16BIT; + pstcMacInit->u16RxVlanTag = 0U; + pstcMacInit->u16RxVlanHashTable = 0U; + } + + return i32Ret; +} + +/** + * @brief Set MAC duplex mode and speed. + * @param [in] u32Mode MAC duplex mode + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_DUPLEX_MD_HALF: Half duplex mode + * @arg ETH_MAC_DUPLEX_MD_FULL: Full duplex mode + * @param [in] u32Speed MAC speed + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_SPEED_10M: 10Mbps + * @arg ETH_MAC_SPEED_100M: 100Mbps + * @retval None + */ +void ETH_MAC_SetDuplexSpeed(uint32_t u32Mode, uint32_t u32Speed) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MD(u32Mode)); + DDL_ASSERT(IS_ETH_MAC_SPEED(u32Speed)); + + MODIFY_REG32(CM_ETH->MAC_CONFIGR, (ETH_MAC_CONFIGR_FES | ETH_MAC_CONFIGR_DM), (u32Mode | u32Speed)); +} + +/** + * @brief Set MAC hash table. + * @param [in] u32HashHigh Hash table high value. + * @param [in] u32HashLow Hash table low value. + * @retval None + */ +void ETH_MAC_SetHashTable(uint32_t u32HashHigh, uint32_t u32HashLow) +{ + WRITE_REG32(CM_ETH->MAC_HASHTLR, u32HashLow); + WRITE_REG32(CM_ETH->MAC_HASHTHR, u32HashHigh); +} + +/** + * @brief Set MAC Tx VLAN tag value. + * @param [in] u16TxTag The tag value of Tx VLAN. + * @retval None + */ +void ETH_MAC_SetTxVlanTagValue(uint16_t u16TxTag) +{ + MODIFY_REG32(CM_ETH->MAC_VTACTLR, ETH_MAC_VTACTLR_VLANV, u16TxTag); +} + +/** + * @brief Set MAC Rx VLAN tag value. + * @param [in] u16RxTag The tag value of Rx VLAN. + * @retval None + */ +void ETH_MAC_SetRxVlanTagValue(uint16_t u16RxTag) +{ + MODIFY_REG32(CM_ETH->MAC_VTAFLTR, ETH_MAC_VTAFLTR_VLFLT, u16RxTag); +} + +/** + * @brief Set MAC Rx VLAN hash table. + * @param [in] u16HashValue The value of Rx VLAN hash table. + * @retval None + */ +void ETH_MAC_SetRxVlanHashTable(uint16_t u16HashValue) +{ + WRITE_REG32(CM_ETH->MAC_VLAHTBR, u16HashValue); +} + +/** + * @brief Enable or disable MAC loopback. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_LoopBackCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_CONFIGR_b.LM, enNewState); +} + +/** + * @brief Enable or disable MAC Back Pressure. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_BackPressureCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_FLOCTLR_b.FCA_BPA, enNewState); +} + +/** + * @brief Enable or disable MAC Transmit. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_TransCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_CONFIGR_b.TE, enNewState); +} + +/** + * @brief Enable or disable MAC Receive. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_ReceiveCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_CONFIGR_b.RE, enNewState); +} + +/** + * @brief Enable or disable MAC interrupt. + * @param [in] u32IntType MAC interrupt source type + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_INT_TSPIM: Time stamp trigger interrupt (on MAC) + * @arg ETH_MAC_INT_PMTIM: PMT interrupt (on MAC) + * @arg ETH_MAC_INT_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_ETH->MAC_INTMSKR, u32IntType); + } else { + SET_REG32_BIT(CM_ETH->MAC_INTMSKR, u32IntType); + } +} + +/** + * @brief Get MAC interrupt status. + * @param [in] u32Flag MAC interrupt flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_INT_FLAG_TSPIS: Time stamp trigger flag (on MAC) + * @arg ETH_MAC_INT_FLAG_MMCTXIS: MMC transmit flag + * @arg ETH_MAC_INT_FLAG_MMCRXIS: MMC receive flag + * @arg ETH_MAC_INT_FLAG_MMCIS: MMC flag (on MAC) + * @arg ETH_MAC_INT_FLAG_PMTIS: PMT flag (on MAC) + * @arg ETH_MAC_INT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_MAC_GetIntStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_INT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->MAC_INTSTSR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* MAC Address Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX0: MAC address 0 + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @retval None + */ +void ETH_MACADDR_DeInit(uint32_t u32Index) +{ + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32MacHigh = 0x0000FFFFUL; + + DDL_ASSERT(IS_ETH_MAC_ADDR_NORMAL_INDEX(u32Index)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MACADLR = ETH_MAC_MACADLR_ADDR(u32Index); + if (ETH_MAC_ADDR_IDX0 == u32Index) { + u32MacHigh |= 0x80000000UL; + } + WRITE_REG32(*MACADHR, u32MacHigh); + WRITE_REG32(*MACADLR, 0xFFFFFFFFUL); +} + +/** + * @brief Initialize MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX0: MAC address 0 + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @param [in] pstcMacAddrInit Pointer to a @ref stc_eth_mac_addr_config_t structure + * @retval int32_t: + * - LL_OK: MAC Address Initialize success + * - LL_ERR_INVD_PARAM: pstcMacAddrInit == NULL + */ +int32_t ETH_MACADDR_Init(uint32_t u32Index, const stc_eth_mac_addr_config_t *pstcMacAddrInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == pstcMacAddrInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDR_NORMAL_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDR_FILTER(pstcMacAddrInit->u32MacAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_ADDR_MASK(pstcMacAddrInit->u32MacAddrMask)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MACADLR = ETH_MAC_MACADLR_ADDR(u32Index); + /* Set MAC address high register */ + u32TempReg = ((uint32_t)pstcMacAddrInit->au8MacAddr[5] << 8U) | (uint32_t)pstcMacAddrInit->au8MacAddr[4]; + if (ETH_MAC_ADDR_IDX0 != u32Index) { + u32TempReg |= pstcMacAddrInit->u32MacAddrFilter | pstcMacAddrInit->u32MacAddrMask; + } + WRITE_REG32(*MACADHR, u32TempReg); + /* Set MAC address low register */ + pu32AddrLow = (uint32_t *)((uint32_t) & (pstcMacAddrInit->au8MacAddr[0])); + WRITE_REG32(*MACADLR, *pu32AddrLow); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_mac_addr_config_t to default values. + * @param [out] pstcMacAddrInit Pointer to a @ref stc_eth_mac_addr_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcMacAddrInit == NULL + */ +int32_t ETH_MACADDR_StructInit(stc_eth_mac_addr_config_t *pstcMacAddrInit) +{ + int32_t i32Ret = LL_OK; + uint8_t i; + + if (NULL == pstcMacAddrInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMacAddrInit->u32MacAddrFilter = ETH_MAC_ADDR_FILTER_DISABLE; + pstcMacAddrInit->u32MacAddrMask = ETH_MAC_ADDR_MASK_DISABLE; + for (i = 0U; i < ETH_MAC_ADDR_BYTE_LEN; i++) { + pstcMacAddrInit->au8MacAddr[i] = 0x00U; + } + } + + return i32Ret; +} + +/** + * @brief Set MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX0: MAC address 0 + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @param [in] au8Addr Pointer to MAC address buffer(6 bytes). + * @retval int32_t: + * - LL_OK: Set address success + * - LL_ERR_INVD_PARAM: au8Addr == NULL + */ +int32_t ETH_MACADDR_SetAddr(uint32_t u32Index, uint8_t au8Addr[]) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == au8Addr) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDR_NORMAL_INDEX(u32Index)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MACADLR = ETH_MAC_MACADLR_ADDR(u32Index); + /* Set MAC address high register */ + u32TempReg = ((uint32_t)au8Addr[5] << 8U) | (uint32_t)au8Addr[4]; + WRITE_REG32(*MACADHR, u32TempReg); + /* Set MAC address low register */ + pu32AddrLow = (uint32_t *)((uint32_t) & (au8Addr[0])); + WRITE_REG32(*MACADLR, *pu32AddrLow); + } + + return i32Ret; +} + +/** + * @brief Get MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX0: MAC address 0 + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @param [out] au8Addr Pointer to MAC address buffer(6 bytes). + * @retval int32_t: + * - LL_OK: Set address success + * - LL_ERR_INVD_PARAM: au8Addr == NULL + */ +int32_t ETH_MACADDR_GetAddr(uint32_t u32Index, uint8_t au8Addr[]) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == au8Addr) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDR_NORMAL_INDEX(u32Index)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MACADLR = ETH_MAC_MACADLR_ADDR(u32Index); + /* Get MAC address high */ + u32TempReg = READ_REG32(*MACADHR); + au8Addr[5] = (uint8_t)((u32TempReg >> 8U) & 0x000000FFUL); + au8Addr[4] = (uint8_t)(u32TempReg & 0x000000FFUL); + /* Get MAC address low */ + pu32AddrLow = (uint32_t *)((uint32_t) & (au8Addr[0])); + *pu32AddrLow = READ_REG32(*MACADLR); + } + + return i32Ret; +} + +/** + * @brief Set MAC Address filter mode. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @param [in] u32Mode MAC address filter mode. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_FILTER_DISABLE: Disable perfect filter with MAC address. + * @arg ETH_MAC_ADDR_FILTER_PERFECT_DEST_ADDR: Filter the DA address of the received frame with MAC address. + * @arg ETH_MAC_ADDR_FILTER_PERFECT_SRC_ADDR: Filter the SA address of the received frame with MAC address. + * @retval None + */ +void ETH_MACADDR_SetFilterMode(uint32_t u32Index, uint32_t u32Mode) +{ + __IO uint32_t *MACADHR; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDR_SPEC_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDR_FILTER(u32Mode)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MODIFY_REG32(*MACADHR, (ETH_MAC_MACADHR1_SA1 | ETH_MAC_MACADHR1_AE1), u32Mode); +} + +/** + * @brief Set MAC Address Transmit priority ratio. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_IDX1: MAC address 1 + * @arg ETH_MAC_ADDR_IDX2: MAC address 2 + * @arg ETH_MAC_ADDR_IDX3: MAC address 3 + * @arg ETH_MAC_ADDR_IDX4: MAC address 4 + * @param [in] u32Mask MAC address filter mask. + * This parameter can be one of the following values or any combination of BYTE1 through BYTE6: + * @arg ETH_MAC_ADDR_MASK_DISABLE: Disable MAC Address Mask + * @arg ETH_MAC_ADDR_MASK_BYTE6: Mask MAC Address high reg bits [15:8] + * @arg ETH_MAC_ADDR_MASK_BYTE5: Mask MAC Address high reg bits [7:0] + * @arg ETH_MAC_ADDR_MASK_BYTE4: Mask MAC Address low reg bits [31:24] + * @arg ETH_MAC_ADDR_MASK_BYTE3: Mask MAC Address low reg bits [23:16] + * @arg ETH_MAC_ADDR_MASK_BYTE2: Mask MAC Address low reg bits [15:8] + * @arg ETH_MAC_ADDR_MASK_BYTE1: Mask MAC Address low reg bits [7:0] + * @arg ETH_MAC_ADDR_MASK_ALL: Mask MAC Address low reg bits [31:0] and low high bits [15:0] + * @retval None + */ +void ETH_MACADDR_SetFilterMask(uint32_t u32Index, uint32_t u32Mask) +{ + __IO uint32_t *MACADHR; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDR_SPEC_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDR_MASK(u32Mask)); + + MACADHR = ETH_MAC_MACADHR_ADDR(u32Index); + MODIFY_REG32(*MACADHR, ETH_MAC_MACADHR1_MBC1, u32Mask); +} + +/******************************************************************************/ +/* MAC L3L4 Filter Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC L3L4 Filter. + * @param None + * @retval None + */ +void ETH_MAC_L3L4FilterDeInit(void) +{ + WRITE_REG32(bCM_ETH->MAC_FLTCTLR_b.IPFE, DISABLE); + WRITE_REG32(CM_ETH->MAC_L34CTLR, 0UL); + WRITE_REG32(CM_ETH->MAC_L4PORTR, 0UL); + WRITE_REG32(CM_ETH->MAC_L3ADDRR0, 0UL); + WRITE_REG32(CM_ETH->MAC_L3ADDRR1, 0UL); + WRITE_REG32(CM_ETH->MAC_L3ADDRR2, 0UL); + WRITE_REG32(CM_ETH->MAC_L3ADDRR3, 0UL); +} + +/** + * @brief Initialize MAC L3L4 Filter. + * @param [in] pstcL3L4FilterInit Pointer to a @ref stc_eth_l3l4_filter_config_t structure + * @retval int32_t: + * - LL_OK: MAC L3L4 Filter Initialize success + * - LL_ERR_INVD_PARAM: pstcL3L4FilterInit == NULL + */ +int32_t ETH_MAC_L3L4FilterInit(const stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcL3L4FilterInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L4_DEST_PORT_FILTER(pstcL3L4FilterInit->u32DestPortFilter)); + DDL_ASSERT(IS_ETH_MAC_L4_SRC_PORT_FILTER(pstcL3L4FilterInit->u32SrcPortFilter)); + DDL_ASSERT(IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(pstcL3L4FilterInit->u32PortFilterProtocol)); + DDL_ASSERT(IS_ETH_MAC_L3_DEST_ADDR_FILTER_MASK(pstcL3L4FilterInit->u32Ip4DestAddrFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_SRC_ADDR_FILTER_MASK(pstcL3L4FilterInit->u32Ip4SrcAddrFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK(pstcL3L4FilterInit->u32Ip6AddrFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_DEST_ADDR_FILTER(pstcL3L4FilterInit->u32DestAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_L3_SRC_ADDR_FILTER(pstcL3L4FilterInit->u32SrcAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(pstcL3L4FilterInit->u32AddrFilterProtocol)); + + /* Set L3/L4 control register */ + if (ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4 != pstcL3L4FilterInit->u32AddrFilterProtocol) { + WRITE_REG32(CM_ETH->MAC_L34CTLR, + (pstcL3L4FilterInit->u32DestPortFilter | pstcL3L4FilterInit->u32SrcPortFilter | + pstcL3L4FilterInit->u32PortFilterProtocol | pstcL3L4FilterInit->u32Ip6AddrFilterMask | + pstcL3L4FilterInit->u32DestAddrFilter | pstcL3L4FilterInit->u32SrcAddrFilter | + pstcL3L4FilterInit->u32AddrFilterProtocol)); + WRITE_REG32(CM_ETH->MAC_L3ADDRR0, pstcL3L4FilterInit->au32Ip6AddrFilterValue[0]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR1, pstcL3L4FilterInit->au32Ip6AddrFilterValue[1]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR2, pstcL3L4FilterInit->au32Ip6AddrFilterValue[2]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR3, pstcL3L4FilterInit->au32Ip6AddrFilterValue[3]); + } else { /* IPv4 protocol*/ + WRITE_REG32(CM_ETH->MAC_L34CTLR, + (pstcL3L4FilterInit->u32DestPortFilter | pstcL3L4FilterInit->u32SrcPortFilter | + pstcL3L4FilterInit->u32PortFilterProtocol | pstcL3L4FilterInit->u32Ip4DestAddrFilterMask | + pstcL3L4FilterInit->u32Ip4SrcAddrFilterMask | pstcL3L4FilterInit->u32DestAddrFilter | + pstcL3L4FilterInit->u32SrcAddrFilter | pstcL3L4FilterInit->u32AddrFilterProtocol)); + WRITE_REG32(CM_ETH->MAC_L3ADDRR0, pstcL3L4FilterInit->u32Ip4SrcAddrFilterValue); + WRITE_REG32(CM_ETH->MAC_L3ADDRR1, pstcL3L4FilterInit->u32Ip4DestAddrFilterValue); + } + WRITE_REG32(CM_ETH->MAC_L4PORTR, ((((uint32_t)pstcL3L4FilterInit->u16DestProtFilterValue) << + ETH_MAC_L4PORTR_L4DPVAL_POS) | pstcL3L4FilterInit->u16SrcProtFilterValue)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_l3l4_filter_config_t to default values. + * @param [out] pstcL3L4FilterInit Pointer to a @ref stc_eth_l3l4_filter_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcL3L4FilterInit == NULL + */ +int32_t ETH_MAC_L3L4FilterStructInit(stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit) +{ + int32_t i32Ret = LL_OK; + uint8_t i; + + if (NULL == pstcL3L4FilterInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcL3L4FilterInit->u32DestPortFilter = ETH_MAC_L4_DEST_PORT_FILTER_DISABLE; + pstcL3L4FilterInit->u32SrcPortFilter = ETH_MAC_L4_SRC_PORT_FILTER_DISABLE; + pstcL3L4FilterInit->u32PortFilterProtocol = ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP; + pstcL3L4FilterInit->u32Ip4DestAddrFilterMask = ETH_MAC_L3_DEST_ADDR_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32Ip4SrcAddrFilterMask = ETH_MAC_L3_SRC_ADDR_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32Ip6AddrFilterMask = ETH_MAC_L3_DEST_SRC_ADDR_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32DestAddrFilter = ETH_MAC_L3_DEST_ADDR_FILTER_DISABLE; + pstcL3L4FilterInit->u32SrcAddrFilter = ETH_MAC_SRC_ADDR_FILTER_DISABLE; + pstcL3L4FilterInit->u32AddrFilterProtocol = ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4; + pstcL3L4FilterInit->u16DestProtFilterValue = 0U; + pstcL3L4FilterInit->u16SrcProtFilterValue = 0U; + pstcL3L4FilterInit->u32Ip4DestAddrFilterValue = 0UL; + pstcL3L4FilterInit->u32Ip4SrcAddrFilterValue = 0UL; + for (i = 0U; i < 4U; i++) { + pstcL3L4FilterInit->au32Ip6AddrFilterValue[i] = 0UL; + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable MAC L3L4 Filter function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MAC_L3L4FilterCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_FLTCTLR_b.IPFE, enNewState); +} + +/** + * @brief Set L4 port filter protocol. + * @param [in] u32Protocol MAC L4 port filter protocol. + * This parameter can be one of the following values: + * @arg ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP: Port filter for TCP frame + * @arg ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP: Port filter for UDP frame + * @retval None + */ +void ETH_MAC_SetPortFilterProtocol(uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(u32Protocol)); + + WRITE_REG32(bCM_ETH->MAC_L34CTLR_b.L4PEN, (u32Protocol >> ETH_MAC_L34CTLR_L4PEN_POS)); +} + +/** + * @brief Set L4 Destination port filter value. + * @param [in] u16Port The value of Destination port. + * @retval None + */ +void ETH_MAC_SetDestPortFilterValue(uint16_t u16Port) +{ + MODIFY_REG32(CM_ETH->MAC_L4PORTR, ETH_MAC_L4PORTR_L4DPVAL, ((uint32_t)u16Port << 16U)); +} + +/** + * @brief Set L4 Source port filter value. + * @param [in] u16Port The value of Source port. + * @retval None + */ +void ETH_MAC_SetSrcPortFilterValue(uint16_t u16Port) +{ + MODIFY_REG32(CM_ETH->MAC_L4PORTR, ETH_MAC_L4PORTR_L4SPVAL, u16Port); +} + +/** + * @brief Set L3 address filter protocol. + * @param [in] u32Protocol MAC L3 address filter protocol. + * This parameter can be one of the following values: + * @arg ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4: Ip Address filter for IPv4 + * @arg ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6: Ip Address filter for IPv6 + * @retval None + */ +void ETH_MAC_SetAddrFilterProtocol(uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(u32Protocol)); + + WRITE_REG32(bCM_ETH->MAC_L34CTLR_b.L3PEN, u32Protocol); +} + +/** + * @brief Set L3 Destination address filter value of IPv4. + * @param [in] u32Addr The value of Destination address. + * @retval None + */ +void ETH_MAC_SetIpv4DestAddrFilterValue(uint32_t u32Addr) +{ + WRITE_REG32(CM_ETH->MAC_L3ADDRR1, u32Addr); +} + +/** + * @brief Set L3 Source address filter value of IPv4. + * @param [in] u32Addr The value of Source address. + * @retval None + */ +void ETH_MAC_SetIpv4SrcAddrFilterValue(uint32_t u32Addr) +{ + WRITE_REG32(CM_ETH->MAC_L3ADDRR0, u32Addr); +} + +/** + * @brief Set L3 Destination/Source Address filter value of IPv6. + * @param [in] au32Addr Pointer to Destination/Source Address buffer(4 words). + * @retval int32_t: + * - LL_OK: Set Address filter value success + * - LL_ERR_INVD_PARAM: au32Addr == NULL + */ +int32_t ETH_MAC_SetIpv6AddrFilterValue(const uint32_t au32Addr[]) +{ + int32_t i32Ret = LL_OK; + + if (NULL == au32Addr) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + WRITE_REG32(CM_ETH->MAC_L3ADDRR0, au32Addr[0]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR1, au32Addr[1]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR2, au32Addr[2]); + WRITE_REG32(CM_ETH->MAC_L3ADDRR3, au32Addr[3]); + } + + return i32Ret; +} + +/******************************************************************************/ +/* DMA Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize DMA. + * @param None + * @retval None + */ +void ETH_DMA_DeInit(void) +{ + WRITE_REG32(CM_ETH->DMA_BUSMODR, 0x00020101UL); + WRITE_REG32(CM_ETH->DMA_OPRMODR, 0U); + WRITE_REG32(CM_ETH->DMA_INTENAR, 0U); + WRITE_REG32(CM_ETH->DMA_REVWDTR, 0U); + WRITE_REG32(CM_ETH->DMA_TXDLADR, 0U); + WRITE_REG32(CM_ETH->DMA_RXDLADR, 0U); +} + +/** + * @brief Initialize DMA. + * @param [in] pstcDmaInit Pointer to a @ref stc_eth_dma_init_t structure + * @retval int32_t: + * - LL_OK: DMA Initialize success + * - LL_ERR_INVD_PARAM: pstcDmaInit == NULL + */ +int32_t ETH_DMA_Init(const stc_eth_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_BURST_MD(pstcDmaInit->u32BurstMode)); + DDL_ASSERT(IS_ETH_DMA_ADDR_ALIGN(pstcDmaInit->u32AddrAlign)); + DDL_ASSERT(IS_ETH_DMA_RX_BURST_LEN(pstcDmaInit->u32RxBurstLen)); + DDL_ASSERT(IS_ETH_DMA_TX_BURST_LEN(pstcDmaInit->u32TxBurstLen)); + DDL_ASSERT(IS_ETH_DMA_ENHANCE_DESC(pstcDmaInit->u32EnhanceDesc)); + DDL_ASSERT(IS_ETH_DMA_DESC_SKIP_LEN(pstcDmaInit->u32DescSkipLen)); + DDL_ASSERT(IS_ETH_DMA_PRIO_ARBITRATION(pstcDmaInit->u32Arbitration)); + DDL_ASSERT(IS_ETH_DMA_DROP_CHECKSUM_ERR_FRAME(pstcDmaInit->u32DropChecksumErrorFrame)); + DDL_ASSERT(IS_ETH_DMA_RX_STORE_FORWARD(pstcDmaInit->u32ReceiveStoreForward)); + DDL_ASSERT(IS_ETH_DMA_FLUSH_RX_FRAME(pstcDmaInit->u32FlushReceiveFrame)); + DDL_ASSERT(IS_ETH_DMA_TRANS_STORE_FORWARD(pstcDmaInit->u32TransStoreForward)); + DDL_ASSERT(IS_ETH_DMA_TRANS_THRESHOLD(pstcDmaInit->u32TransThreshold)); + DDL_ASSERT(IS_ETH_DMA_FORWARD_ERR_FRAME(pstcDmaInit->u32ForwardErrorFrame)); + DDL_ASSERT(IS_ETH_DMA_FORWARD_UNDERSIZE_FRAME(pstcDmaInit->u32ForwardUndersizeFrame)); + DDL_ASSERT(IS_ETH_DMA_DROP_JUMBO_FRAME(pstcDmaInit->u32DropJumboFrame)); + DDL_ASSERT(IS_ETH_DMA_RX_THRESHOLD(pstcDmaInit->u32ReceiveThreshold)); + DDL_ASSERT(IS_ETH_DMA_SEC_FRAME_OPERA(pstcDmaInit->u32SecFrameOperate)); + + /* Set Bus mode register */ + MODIFY_REG32(CM_ETH->DMA_BUSMODR, ETH_DMA_BUSMODR_CLR_MASK, + (pstcDmaInit->u32BurstMode | pstcDmaInit->u32AddrAlign | pstcDmaInit->u32RxBurstLen | + pstcDmaInit->u32TxBurstLen | pstcDmaInit->u32EnhanceDesc | pstcDmaInit->u32DescSkipLen | + pstcDmaInit->u32Arbitration | ETH_DMA_BUSMODR_SPBL)); + /* Set Operation mode register */ + MODIFY_REG32(CM_ETH->DMA_OPRMODR, ETH_DMA_OPRMODR_CLR_MASK, + (pstcDmaInit->u32DropChecksumErrorFrame | pstcDmaInit->u32ReceiveStoreForward | + pstcDmaInit->u32FlushReceiveFrame | pstcDmaInit->u32TransStoreForward | + pstcDmaInit->u32TransThreshold | pstcDmaInit->u32ForwardErrorFrame | + pstcDmaInit->u32ForwardUndersizeFrame | pstcDmaInit->u32DropJumboFrame | + pstcDmaInit->u32ReceiveThreshold | pstcDmaInit->u32SecFrameOperate)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_dma_init_t to default values. + * @param [out] pstcDmaInit Pointer to a @ref stc_eth_dma_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDmaInit == NULL + */ +int32_t ETH_DMA_StructInit(stc_eth_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaInit->u32BurstMode = ETH_DMA_BURST_MD_FIXED; + pstcDmaInit->u32AddrAlign = ETH_DMA_ADDR_ALIGN_ENABLE; + pstcDmaInit->u32RxBurstLen = ETH_DMA_RX_BURST_LEN_32BEAT; + pstcDmaInit->u32TxBurstLen = ETH_DMA_TX_BURST_LEN_32BEAT; + pstcDmaInit->u32EnhanceDesc = ETH_DMA_ENHANCE_DESC_ENABLE; + pstcDmaInit->u32DescSkipLen = 0U; + pstcDmaInit->u32Arbitration = ETH_DMA_ARBITRATION_LOOP_RXTX_1_1; + pstcDmaInit->u32DropChecksumErrorFrame = ETH_DMA_DROP_CHECKSUM_ERR_FRAME_ENABLE; + pstcDmaInit->u32ReceiveStoreForward = ETH_DMA_RX_STORE_FORWARD_ENABLE; + pstcDmaInit->u32FlushReceiveFrame = ETH_DMA_FLUSH_RX_FRAME_ENABLE; + pstcDmaInit->u32TransStoreForward = ETH_DMA_TRANS_STORE_FORWARD_ENABLE; + pstcDmaInit->u32TransThreshold = ETH_DMA_TRANS_THRESHOLD_64BYTE; + pstcDmaInit->u32ForwardErrorFrame = ETH_DMA_FORWARD_ERR_FRAME_DISABLE; + pstcDmaInit->u32ForwardUndersizeFrame = ETH_DMA_FORWARD_UNDERSIZE_FRAME_DISABLE; + pstcDmaInit->u32DropJumboFrame = ETH_DMA_DROP_JUMBO_FRAME_DISABLE; + pstcDmaInit->u32ReceiveThreshold = ETH_DMA_RX_THRESHOLD_64BYTE; + pstcDmaInit->u32SecFrameOperate = ETH_DMA_SEC_FRAME_OPERA_ENABLE; + } + + return i32Ret; +} + +/** + * @brief Set DMA software reset. + * @param None + * @retval int32_t: + * - LL_OK: Software reset success + * - LL_ERR_TIMEOUT: Reset timeout + */ +int32_t ETH_DMA_SoftwareReset(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_ETH->DMA_BUSMODR_b.SWR, 1U); + u32Count = ETH_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->DMA_BUSMODR_b.SWR)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Set DMA Transmit priority ratio. + * @param [in] u32Ratio Priority ratio + * This parameter can be one of the following values: + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_1_1: Rx:Tx = 1:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_2_1: Rx:Tx = 2:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_3_1: Rx:Tx = 3:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_4_1: Rx:Tx = 4:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_1_1: Tx:Rx = 1:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_2_1: Tx:Rx = 2:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_3_1: Tx:Rx = 3:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_4_1: Tx:Rx = 4:1 + * @arg ETH_DMA_ARBITRATION_FIXED_RX_PRIOR_TX: Fixed priority: Rx is higher than Tx + * @arg ETH_DMA_ARBITRATION_FIXED_TX_PRIOR_RX: Fixed priority: Tx is higher than Rx + * @retval None + */ +void ETH_DMA_SetTransPriorityRatio(uint32_t u32Ratio) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_PRIO_ARBITRATION(u32Ratio)); + + MODIFY_REG32(CM_ETH->DMA_BUSMODR, (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT | ETH_DMA_BUSMODR_DMAA), u32Ratio); +} + +/** + * @brief Set DMA Rx watchdog counter. + * @param [in] u8Value The value of Watchdog timer + * @retval None + */ +void ETH_DMA_SetRxWatchdogCounter(uint8_t u8Value) +{ + WRITE_REG32(CM_ETH->DMA_REVWDTR, u8Value); +} + +/** + * @brief Flush transmit FIFO. + * @param None + * @retval int32_t: + * - LL_OK: Flush transmit FIFO success + * - LL_ERR_TIMEOUT: Flush timeout + */ +int32_t ETH_DMA_FlushTransFIFO(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_ETH->DMA_OPRMODR_b.FTF, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->DMA_OPRMODR_b.FTF)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA transmit. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_DMA_TransCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->DMA_OPRMODR_b.STT, enNewState); +} + +/** + * @brief Enable or disable DMA receive. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_DMA_ReceiveCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->DMA_OPRMODR_b.STR, enNewState); +} + +/** + * @brief Enable or disable DMA interrupt. + * @param [in] u32IntType DMA interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_INT_NIE: Normal interrupt summary + * @arg ETH_DMA_INT_AIE: Abnormal interrupt summary + * @arg ETH_DMA_INT_ERE: Early receive interrupt + * @arg ETH_DMA_INT_FBE: Fatal bus error interrupt + * @arg ETH_DMA_INT_ETE: Early transmit interrupt + * @arg ETH_DMA_INT_RWE: Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RSE: Receive process stopped interrupt + * @arg ETH_DMA_INT_RUE: Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RIE: Receive interrupt + * @arg ETH_DMA_INT_UNE: Transmit Underflow interrupt + * @arg ETH_DMA_INT_OVE: Receive Overflow interrupt + * @arg ETH_DMA_INT_TJE: Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TUE: Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TSE: Transmit process stopped interrupt + * @arg ETH_DMA_INT_TIE: Transmit interrupt + * @arg ETH_DMA_INT_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_DMA_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(CM_ETH->DMA_INTENAR, u32IntType); + } else { + CLR_REG32_BIT(CM_ETH->DMA_INTENAR, u32IntType); + } +} + +/** + * @brief Get DMA flag status. + * @param [in] u32Flag DMA flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_FLAG_PTPS: Time-stamp trigger status + * @arg ETH_DMA_FLAG_PMTS: PMT trigger status + * @arg ETH_DMA_FLAG_MMCS: MMC trigger status + * @arg ETH_DMA_FLAG_NIS: Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS: Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ERS: Early receive flag + * @arg ETH_DMA_FLAG_FBS: Fatal bus error flag + * @arg ETH_DMA_FLAG_ETS: Early transmit flag + * @arg ETH_DMA_FLAG_RWS: Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RSS: Receive stopped flag + * @arg ETH_DMA_FLAG_RUS: Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RIS: Receive flag + * @arg ETH_DMA_FLAG_UNS: Transmit Underflow flag + * @arg ETH_DMA_FLAG_OVS: Receive Overflow flag + * @arg ETH_DMA_FLAG_TJS: Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TUS: Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TSS: Transmit stopped flag + * @arg ETH_DMA_FLAG_TIS: Transmit interrupt flag + * @arg ETH_DMA_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_DMA_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->DMA_DMASTSR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear DMA flag. + * @param [in] u32Flag DMA flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_FLAG_NIS: Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS: Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ERS: Early receive flag + * @arg ETH_DMA_FLAG_FBS: Fatal bus error flag + * @arg ETH_DMA_FLAG_ETS: Early transmit flag + * @arg ETH_DMA_FLAG_RWS: Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RSS: Receive stopped flag + * @arg ETH_DMA_FLAG_RUS: Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RIS: Receive flag + * @arg ETH_DMA_FLAG_UNS: Transmit Underflow flag + * @arg ETH_DMA_FLAG_OVS: Receive Overflow flag + * @arg ETH_DMA_FLAG_TJS: Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TUS: Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TSS: Transmit stopped flag + * @arg ETH_DMA_FLAG_TIS: Transmit interrupt flag + * @arg ETH_DMA_FLAG_CLR_ALL: All of the above + * @retval None + */ +void ETH_DMA_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_CLR_FLAG(u32Flag)); + + WRITE_REG32(CM_ETH->DMA_DMASTSR, u32Flag); +} + +/** + * @brief Get DMA overflow flag status. + * @param [in] u32Flag DMA overflow flag type + * This parameter can be one of the following values: + * @arg ETH_DMA_OVF_RXFIFO_CNT: Overflow bit for FIFO overflow counter + * @arg ETH_DMA_OVF_MISS_FRAME_CNT: Overflow bit for miss frame counter + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_DMA_GetOvfStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_MISS_FRAME_TYPE(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->DMA_RFRCNTR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* DMA descriptor Functions */ +/******************************************************************************/ +/** + * @brief Initializes DMA Tx descriptor in chain mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] astcTxDescTab Pointer to the first Tx desc list + * @param [in] au8TxBuf Pointer to the first TxBuffer list + * @param [in] u32TxBufCnt Number of the Tx desc in the list + * @retval int32_t: + * - LL_OK: Initializes Tx chain mode success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL or astcTxDescTab == NULL or au8TxBuf == NULL or u32TxBufCnt == 0 + */ +int32_t ETH_DMA_TxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcTxDescTab[], + const uint8_t au8TxBuf[], uint32_t u32TxBufCnt) +{ + uint32_t i; + stc_eth_dma_desc_t *pstcTxDesc; + int32_t i32Ret = LL_OK; + + if ((NULL == pstcEthHandle) || (NULL == astcTxDescTab) || (NULL == au8TxBuf) || (0UL == u32TxBufCnt)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Set the DMATxDesc pointer with the first in the astcTxDescTab list */ + pstcEthHandle->stcTxDesc = astcTxDescTab; + /* Fill each DMATxDesc descriptor */ + for (i = 0U; i < u32TxBufCnt; i++) { + pstcTxDesc = &astcTxDescTab[i]; + /* Set Second Address Chained */ + pstcTxDesc->u32ControlStatus = ETH_DMA_TXDESC_TSAC; + /* Set Buffer1 address pointer */ + pstcTxDesc->u32Buf1Addr = (uint32_t)(&au8TxBuf[i * ETH_TX_BUF_SIZE]); + /* Set the DMA Tx descriptors checksum insertion */ + if (ETH_MAC_CHECKSUM_MD_HW == pstcEthHandle->stcCommInit.u32ChecksumMode) { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_CIC_TCPUDPICMP_FULL); + } + /* Initialize the next descriptor with the Next Descriptor Polling */ + if (i < (u32TxBufCnt - 1U)) { + pstcTxDesc->u32Buf2NextDescAddr = (uint32_t)(&astcTxDescTab[i + 1U]); + } else { + pstcTxDesc->u32Buf2NextDescAddr = (uint32_t)astcTxDescTab; + } + } + /* Set Transmit Descriptor List Address Register */ + WRITE_REG32(CM_ETH->DMA_TXDLADR, (uint32_t)astcTxDescTab); + } + + return i32Ret; +} + +/** + * @brief Initializes DMA Rx descriptor in chain mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] astcRxDescTab Pointer to the first Rx desc list + * @param [in] au8RxBuf Pointer to the first RxBuffer list + * @param [in] u32RxBufCnt Number of the Rx desc in the list + * @retval int32_t: + * - LL_OK: Initializes Rx chain mode success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL or astcRxDescTab == NULL or au8RxBuf == NULL or u32RxBufCnt == 0 + */ +int32_t ETH_DMA_RxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcRxDescTab[], + const uint8_t au8RxBuf[], uint32_t u32RxBufCnt) +{ + uint32_t i; + stc_eth_dma_desc_t *pstcRxDesc; + int32_t i32Ret = LL_OK; + + if ((NULL == pstcEthHandle) || (NULL == astcRxDescTab) || (NULL == au8RxBuf) || (0UL == u32RxBufCnt)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Set the DMARxDesc pointer with the first in the astcRxDescTab list */ + pstcEthHandle->stcRxDesc = astcRxDescTab; + /* Fill each DMARxDesc descriptor */ + for (i = 0UL; i < u32RxBufCnt; i++) { + pstcRxDesc = &astcRxDescTab[i]; + /* Set Own bit of the Rx descriptor */ + pstcRxDesc->u32ControlStatus = ETH_DMA_RXDESC_OWN; + /* Set Buffer1 size and Second Address Chained */ + pstcRxDesc->u32ControlBufSize = ETH_RX_BUF_SIZE | ETH_DMA_RXDESC_RSAC; + /* Set Buffer1 address pointer */ + pstcRxDesc->u32Buf1Addr = (uint32_t)(&au8RxBuf[i * ETH_RX_BUF_SIZE]); + /* Set the DMA Rx Descriptor interrupt */ + if (ETH_RX_MD_INT == pstcEthHandle->stcCommInit.u32ReceiveMode) { + CLR_REG32_BIT(pstcRxDesc->u32ControlBufSize, ETH_DMA_RXDESC_DIC); + } + /* Initialize the next descriptor with the Next Descriptor Polling */ + if (i < (u32RxBufCnt - 1U)) { + pstcRxDesc->u32Buf2NextDescAddr = (uint32_t)(&astcRxDescTab[i + 1U]); + } else { + pstcRxDesc->u32Buf2NextDescAddr = (uint32_t)astcRxDescTab; + } + } + /* Set Receive Descriptor List Address Register */ + WRITE_REG32(CM_ETH->DMA_RXDLADR, (uint32_t)astcRxDescTab); + } + + return i32Ret; +} + +/** + * @brief Set DMA transmit frame. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u32FrameLen Total of data to be transmit + * @retval int32_t: + * - LL_OK: Set transmit frame success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL + * - LL_ERR_INVD_MD: Descriptor is owned by the DMA + */ +int32_t ETH_DMA_SetTransFrame(stc_eth_handle_t *pstcEthHandle, uint32_t u32FrameLen) +{ + uint32_t i; + uint32_t u32BufCnt; + uint32_t u32Size; + int32_t i32Ret = LL_OK; + + if ((NULL == pstcEthHandle) || (0U == u32FrameLen)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check if the descriptor is owned by the CPU */ + if (0UL != (pstcEthHandle->stcTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN)) { + i32Ret = LL_ERR_INVD_MD; + } else { + /* Get the number of needed Tx buffers for the current frame */ + if (u32FrameLen > ETH_TX_BUF_SIZE) { + u32BufCnt = u32FrameLen / ETH_TX_BUF_SIZE; + if (0UL != (u32FrameLen % ETH_TX_BUF_SIZE)) { + u32BufCnt++; + } + } else { + u32BufCnt = 1U; + } + + if (1U == u32BufCnt) { + /* Set FIRST and LAST segment */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, (ETH_DMA_TXDESC_TFS | ETH_DMA_TXDESC_TLS)); + /* Set frame size */ + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufSize, ETH_DMA_TXDESC_TBS1, + (u32FrameLen & ETH_DMA_TXDESC_TBS1)); + /* Set Own bit of the Tx descriptor */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_OWN); + /* Point to next descriptor */ + pstcEthHandle->stcTxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcTxDesc->u32Buf2NextDescAddr); + } else { + for (i = 0U; i < u32BufCnt; i++) { + /* Clear FIRST and LAST segment bits */ + CLR_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, + (ETH_DMA_TXDESC_TFS | ETH_DMA_TXDESC_TLS)); + if (0U == i) { + /* Set the FIRST segment bit */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_TFS); + } + if ((u32BufCnt - 1U) == i) { + /* Set the last segment bit */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_TLS); + u32Size = u32FrameLen - ((u32BufCnt - 1U) * ETH_TX_BUF_SIZE); + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufSize, ETH_DMA_TXDESC_TBS1, + (u32Size & ETH_DMA_TXDESC_TBS1)); + } else { + /* Set frame size */ + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufSize, ETH_DMA_TXDESC_TBS1, + (ETH_TX_BUF_SIZE & ETH_DMA_TXDESC_TBS1)); + } + + /* Set Own bit of the Tx descriptor */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_OWN); + /* Pointer to next descriptor */ + pstcEthHandle->stcTxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcTxDesc->u32Buf2NextDescAddr); + } + } + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if (0UL != (READ_REG32_BIT(CM_ETH->DMA_DMASTSR, ETH_DMA_FLAG_TUS))) { + /* Clear DMA TUS flag */ + WRITE_REG32(CM_ETH->DMA_DMASTSR, ETH_DMA_FLAG_TUS); + /* Resume DMA transmission */ + WRITE_REG32(CM_ETH->DMA_TXPOLLR, 0UL); + } + } + } + + return i32Ret; +} + +/** + * @brief Get DMA receive frame. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @retval int32_t: + * - LL_OK: Get receive frame success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL + * - LL_ERR: Not completed frame received + */ +int32_t ETH_DMA_GetReceiveFrame(stc_eth_handle_t *pstcEthHandle) +{ + int32_t i32Ret = LL_ERR; + + if (NULL == pstcEthHandle) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check if segment is not owned by DMA */ + if (0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMA_RXDESC_OWN)) { + /* Check if last segment */ + if (0UL != (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMA_RXDESC_RLS)) { + pstcEthHandle->stcRxFrame.u32SegCount++; + pstcEthHandle->stcRxFrame.pstcLSDesc = pstcEthHandle->stcRxDesc; + /* Check if last segment is first segment */ + if (1U == pstcEthHandle->stcRxFrame.u32SegCount) { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + } + + /* Get the Frame Length of the received packet: Strip FCS */ + pstcEthHandle->stcRxFrame.u32Len = ((pstcEthHandle->stcRxDesc->u32ControlStatus & + ETH_DMA_RXDESC_FRAL) >> ETH_DMA_RXDESC_FRAME_LEN_SHIFT) - 4U; + /* Get the address of the buffer start address */ + pstcEthHandle->stcRxFrame.u32Buf = (pstcEthHandle->stcRxFrame.pstcFSDesc)->u32Buf1Addr; + /* Pointer to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + /* Get success */ + i32Ret = LL_OK; + } else if (0UL != (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMA_RXDESC_RFS)) { /* Check if first segment */ + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + pstcEthHandle->stcRxFrame.pstcLSDesc = NULL; + pstcEthHandle->stcRxFrame.u32SegCount = 1U; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + } else { /* Check if intermediate segment */ + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + } + } + } + + return i32Ret; +} + +/** + * @brief Get DMA receive frame in interrupt mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @retval int32_t: + * - LL_OK: Get receive frame success + * - LL_ERR_INVD_PARAM: pstcEthHandle == NULL + * - LL_ERR: Not completed frame received + */ +int32_t ETH_DMA_GetReceiveFrame_Int(stc_eth_handle_t *pstcEthHandle) +{ + uint32_t u32DescCnt = 0U; + int32_t i32Ret = LL_ERR; + + if (NULL == pstcEthHandle) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Scan descriptor owned by CPU */ + while ((0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMA_RXDESC_OWN)) && + (u32DescCnt < ETH_RX_BUF_SIZE)) { + u32DescCnt++; + /* Check if first segment in frame */ + if (ETH_DMA_RXDESC_RFS == (pstcEthHandle->stcRxDesc->u32ControlStatus & + (ETH_DMA_RXDESC_RFS | ETH_DMA_RXDESC_RLS))) { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + pstcEthHandle->stcRxFrame.pstcLSDesc = NULL; + pstcEthHandle->stcRxFrame.u32SegCount = 1U; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + } else if (0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & (ETH_DMA_RXDESC_RFS | ETH_DMA_RXDESC_RLS))) { + /* Check if intermediate segment */ + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + } else { /* Last segment */ + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Last segment */ + pstcEthHandle->stcRxFrame.pstcLSDesc = pstcEthHandle->stcRxDesc; + /* Check if last segment is first segment */ + if (1U == pstcEthHandle->stcRxFrame.u32SegCount) { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + } + + /* Get the Frame Length of the received packet: Strip FCS */ + pstcEthHandle->stcRxFrame.u32Len = ((pstcEthHandle->stcRxDesc->u32ControlStatus & + ETH_DMA_RXDESC_FRAL) >> ETH_DMA_RXDESC_FRAME_LEN_SHIFT) - 4U; + /* Get the address of the buffer start address */ + pstcEthHandle->stcRxFrame.u32Buf = (pstcEthHandle->stcRxFrame.pstcFSDesc)->u32Buf1Addr; + /* Pointer to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcRxDesc->u32Buf2NextDescAddr); + /* Get success */ + i32Ret = LL_OK; + break; + } + } + } + + return i32Ret; +} + +/** + * @brief Set DMA Tx descriptor own bit. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Owner DMA Tx descriptor owner + * This parameter can be one of the following values: + * @arg ETH_DMA_DESC_OWN_CPU: Descriptor is owned by CPU + * @arg ETH_DMA_DESC_OWN_DMA: Descriptor is owned by DMA + * @retval int32_t: + * - LL_OK: Set Tx descriptor own bit success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_SetTxDescOwn(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Owner) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_DESC_OWN(u32Owner)); + + if (ETH_DMA_DESC_OWN_CPU != u32Owner) { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_OWN); + } else { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_OWN); + } + } + + return i32Ret; +} + +/** + * @brief Set DMA Tx descriptor buffer size. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u8BufNum Buffer sequence number + * This parameter can be one of the following values: + * @arg ETH_DMA_DESC_BUF1: DMA Tx Desc Buffer1 + * @arg ETH_DMA_DESC_BUF2: DMA Tx Desc Buffer2 + * @param [in] u32BufSize DMA Tx buffer size + * @retval int32_t: + * - LL_OK: Set Tx descriptor buffer size success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_SetTxDescBufSize(stc_eth_dma_desc_t *pstcTxDesc, uint8_t u8BufNum, uint32_t u32BufSize) +{ + int32_t i32Ret = LL_OK; + uint32_t u32ShiftBit = 0UL; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_DESC_BUF(u8BufNum)); + DDL_ASSERT(IS_ETH_DMA_TXDESC_BUF_SIZE(u32BufSize)); + + /* DMA Tx Desc buffer2 */ + if (ETH_DMA_DESC_BUF1 != u8BufNum) { + u32ShiftBit = ETH_DMA_DESC_BUF2_SIZE_SHIFT; + } + MODIFY_REG32(pstcTxDesc->u32ControlBufSize, (ETH_DMA_TXDESC_TBS1 << u32ShiftBit), + (u32BufSize << u32ShiftBit)); + } + + return i32Ret; +} + +/** + * @brief Configure DMA Tx descriptor checksum insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32ChecksumMode Checksum insert mode + * This parameter can be one of the following values: + * @arg ETH_DMA_TXDESC_CHECKSUM_BYPASS: Checksum Engine is bypassed + * @arg ETH_DMA_TXDESC_CHECKSUM_IPV4_HEADER: IPv4 header checksum insertion + * @arg ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP Checksum Insertion calculated over segment only + * @arg ETH_DMA_TXDESC_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP Checksum Insertion fully calculated + * @retval int32_t: + * - LL_OK: Configure Tx descriptor checksum insert success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescChecksumInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32ChecksumMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_TXDESC_CHECKSUM_CTRL(u32ChecksumMode)); + + MODIFY_REG32(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_CIC, u32ChecksumMode); + } + + return i32Ret; +} + +/** + * @brief Configure DMA Tx descriptor VLAN insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32VlanMode VLAN insert mode + * This parameter can be one of the following values: + * @arg ETH_DMA_TXDESC_VLAN_BYPASS: VLAN Insertion is bypassed + * @arg ETH_DMA_TXDESC_VLAN_REMOVE_TAG: Remove Tag and Type fields in VLAN frame + * @arg ETH_DMA_TXDESC_VLAN_INSERT_TAG: Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame + * @arg ETH_DMA_TXDESC_VLAN_REPLACE_TAG: Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register + * @retval int32_t: + * - LL_OK: Configure Tx descriptor VLAN insert success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescVlanInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32VlanMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_TXDESC_VLAN_CTRL(u32VlanMode)); + + MODIFY_REG32(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_VLANC, u32VlanMode); + } + + return i32Ret; +} + +/** + * @brief Configure DMA Tx descriptor SA insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Mode SA insert mode + * This parameter can be one of the following values: + * @arg ETH_DMA_TXDESC_SAIRC_BYPASS: Source Address Insertion or Replace Control is bypassed + * @arg ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR0: Insert address value in MAC address register 0 into transmit frame as SA address + * @arg ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR0: Replace SA address in transmit frame with address value in MAC address register 0 + * @arg ETH_DMA_TXDESC_SAIRC_INSTER_MACADDR1: Insert address value in MAC address register 1 into transmit frame as SA address + * @arg ETH_DMA_TXDESC_SAIRC_REPLACE_MACADDR1: Replace SA address in transmit frame with address value in MAC address register 1 + * @retval int32_t: + * - LL_OK: Configure Tx descriptor SA insert success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescSrcAddrInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Mode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_TXDESC_SRC_ADDR_CTRL(u32Mode)); + + MODIFY_REG32(pstcTxDesc->u32ControlBufSize, ETH_DMA_TXDESC_SAIRC, u32Mode); + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Tx descriptor add CRC. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Configure Tx add CRC success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescCrcCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_DCRC); + } else { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_DCRC); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Tx descriptor padding. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Configure Tx padding success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescPadCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_DPAD); + } else { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_DPAD); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Tx descriptor timestamp. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Configure Tx padding success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescTimestamp(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_TTSE); + } else { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_TTSE); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Tx descriptor replace CRC. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Configure Tx replace CRC success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescReplaceCrcCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_CRCR); + } else { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_CRCR); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Tx finished interrupt. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Configure Tx interrupt configure success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL + */ +int32_t ETH_DMA_TxDescIntCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_IOC); + } else { + CLR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMA_TXDESC_IOC); + } + } + + return i32Ret; +} + +/** + * @brief Get DMA Tx descriptor flag status. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Tx descriptor flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_TXDESC_OWN: OWN bit + * @arg ETH_DMA_TXDESC_IOC: Interrupt on Completion + * @arg ETH_DMA_TXDESC_TLS: Transmit Last Segment + * @arg ETH_DMA_TXDESC_TFS: Transmit First Segment + * @arg ETH_DMA_TXDESC_DCRC: Disable CRC + * @arg ETH_DMA_TXDESC_DPAD: Disable Padding + * @arg ETH_DMA_TXDESC_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMA_TXDESC_CRCR: CRC Replace Control + * @arg ETH_DMA_TXDESC_TER: Transmit End of Ring + * @arg ETH_DMA_TXDESC_TSAC: Second Address Chained + * @arg ETH_DMA_TXDESC_TTSS: Tx Time Stamp Status + * @arg ETH_DMA_TXDESC_IHE: IP Header Error + * @arg ETH_DMA_TXDESC_ETSUM: Tx Error summary + * @arg ETH_DMA_TXDESC_JTE: Jabber Timeout Error + * @arg ETH_DMA_TXDESC_FFF: Frame Flushed + * @arg ETH_DMA_TXDESC_TPCE: Payload Checksum Error + * @arg ETH_DMA_TXDESC_LOCE: Loss Carrier Error + * @arg ETH_DMA_TXDESC_NCE: No Carrier Error + * @arg ETH_DMA_TXDESC_TLCE: Late Collision Error + * @arg ETH_DMA_TXDESC_ECE: Excessive Collision Error + * @arg ETH_DMA_TXDESC_VLF: VLAN Frame + * @arg ETH_DMA_TXDESC_EDE: Excessive Deferral Error + * @arg ETH_DMA_TXDESC_UDE: Underflow Error + * @arg ETH_DMA_TXDESC_DEE: Deferred Error + * @arg ETH_DMA_TXDESC_STATUS_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_DMA_GetTxDescStatus(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_TXDESC_STATUS(u32Flag)); + + if (NULL != pstcTxDesc) { + if (0UL != (pstcTxDesc->u32ControlStatus & u32Flag)) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Tx descriptor collision count + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32Count Pointer to DMA Tx collision count + * @retval int32_t: + * - LL_OK: Get collision count success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL or pu32Count == NULL + */ +int32_t ETH_DMA_GetTxDescCollisionCount(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32Count) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcTxDesc) || (NULL == pu32Count)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32Count = (pstcTxDesc->u32ControlStatus >> ETH_DMA_TXDESC_COLLISION_CNT_SHIFT) & ((uint32_t)0x0000000FUL); + } + + return i32Ret; +} + +/** + * @brief Get DMA Tx descriptor timestamp. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32High Timestamp high bit time + * @param [out] pu32Low Timestamp low bit time + * @retval int32_t: + * - LL_OK: Get timestamp success + * - LL_ERR_INVD_PARAM: pstcTxDesc == NULL or pu32High == NULL or pu32Low == NULL + */ +int32_t ETH_DMA_GetTxDescTimeStamp(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32High, uint32_t *pu32Low) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcTxDesc) || (NULL == pu32High) || (NULL == pu32Low)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32Low = pstcTxDesc->u32TimestampLow; + *pu32High = pstcTxDesc->u32TimestampHigh; + } + + return i32Ret; +} + +/** + * @brief Set DMA Rx descriptor own bit. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Owner DMA Rx descriptor owner + * This parameter can be one of the following values: + * @arg ETH_DMA_DESC_OWN_CPU: Descriptor is owned by CPU + * @arg ETH_DMA_DESC_OWN_DMA: Descriptor is owned by DMA + * @retval int32_t: + * - LL_OK: Set Rx descriptor own bit success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL + */ +int32_t ETH_DMA_SetRxDescOwn(stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Owner) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_DESC_OWN(u32Owner)); + + if (ETH_DMA_DESC_OWN_CPU != u32Owner) { + SET_REG32_BIT(pstcRxDesc->u32ControlStatus, ETH_DMA_RXDESC_OWN); + } else { + CLR_REG32_BIT(pstcRxDesc->u32ControlStatus, ETH_DMA_RXDESC_OWN); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable DMA Rx finished interrupt. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Rx interrupt configure success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL + */ +int32_t ETH_DMA_RxDescIntCmd(stc_eth_dma_desc_t *pstcRxDesc, en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRxDesc) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(pstcRxDesc->u32ControlBufSize, ETH_DMA_RXDESC_DIC); + } else { + SET_REG32_BIT(pstcRxDesc->u32ControlBufSize, ETH_DMA_RXDESC_DIC); + } + } + + return i32Ret; +} + +/** + * @brief Get DMA Rx descriptor flag status. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Rx descriptor flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_RXDESC_OWN: OWN bit + * @arg ETH_DMA_RXDESC_DAF: DA Filter Fail for the received frame + * @arg ETH_DMA_RXDESC_ERSUM: Rx Error summary + * @arg ETH_DMA_RXDESC_DPE: Descriptor Error + * @arg ETH_DMA_RXDESC_SAF: SA Filter Fail for the received frame + * @arg ETH_DMA_RXDESC_LEE: Length Error + * @arg ETH_DMA_RXDESC_OVE: Overflow Error + * @arg ETH_DMA_RXDESC_VLAT VLAN Tag + * @arg ETH_DMA_RXDESC_RFS: First descriptor + * @arg ETH_DMA_RXDESC_RLS: Last descriptor + * @arg ETH_DMA_RXDESC_IPE_TSPA_GF: COE Error or Time stamp valid or jumbo frame + * @arg ETH_DMA_RXDESC_RLCE: Late collision Error + * @arg ETH_DMA_RXDESC_FRAT: Frame type + * @arg ETH_DMA_RXDESC_WTE: Receive Watchdog Timeout + * @arg ETH_DMA_RXDESC_REE: Receive error + * @arg ETH_DMA_RXDESC_DBE: Dribble bit error + * @arg ETH_DMA_RXDESC_CRE: CRC error + * @arg ETH_DMA_RXDESC_DAS_ESA: MAC Address Filter/Status bit extension + * @arg ETH_DMA_RXDESC_STATUS_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_DMA_GetRxDescStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_RXDESC_STATUS(u32Flag)); + + if (NULL != pstcRxDesc) { + if (0UL != (pstcRxDesc->u32ControlStatus & u32Flag)) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Rx descriptor extend flag status. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Rx descriptor extend flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_RXDESC_L4FMS: L4 Port Filter Status + * @arg ETH_DMA_RXDESC_L3FMS: L3 Address Filter Status + * @arg ETH_DMA_RXDESC_TSPD: Discard Time Stamp + * @arg ETH_DMA_RXDESC_PTPV: PTP Version + * @arg ETH_DMA_RXDESC_PTPFT: PTP Frame Type + * @arg ETH_DMA_RXDESC_IPV6DR: IPv6 Packet Received + * @arg ETH_DMA_RXDESC_IPV4DR: IPv4 Packet Received + * @arg ETH_DMA_RXDESC_IPCB: COE engine Bypassed + * @arg ETH_DMA_RXDESC_IPPE: IP Payload Error + * @arg ETH_DMA_RXDESC_IPHE: IP Header Error + * @arg ETH_DMA_RXDESC_EXTEND_STATUS_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_DMA_GetRxDescExtendStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_RXDESC_EXTEND_STATUS(u32Flag)); + + if (NULL != pstcRxDesc) { + if (0UL != (pstcRxDesc->u32ExtendStatus & u32Flag)) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Rx descriptor payload type. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32PayloadType Pointer to DMA Rx payload type + * The payload type may be one of the following values: + * - ETH_DMA_RXDESC_IPPT_UNKNOWN: Unknown + * - ETH_DMA_RXDESC_IPPT_UDP: UDP + * - ETH_DMA_RXDESC_IPPT_TCP: TCP + * - ETH_DMA_RXDESC_IPPT_ICMP: ICMP + * @retval int32_t: + * - LL_OK: Get payload type success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL or pu32PayloadType == NULL + */ +int32_t ETH_DMA_GetRxDescPayloadType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32PayloadType) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcRxDesc) || (NULL == pu32PayloadType)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32PayloadType = pstcRxDesc->u32ExtendStatus & ETH_DMA_RXDESC_IPPT; + } + + return i32Ret; +} + +/** + * @brief Get DMA Rx descriptor datagram type. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32DatagramType Pointer to DMA Rx datagram type + * The payload type may be one of the following values: + * - ETH_DMA_RXDESC_MTP_NONE: No PTP messages + * - ETH_DMA_RXDESC_MTP_SYNC: SYNC message (all clock types) + * - ETH_DMA_RXDESC_MTP_FOLLOW_UP: Follow_Up message (all clock types) + * - ETH_DMA_RXDESC_MTP_DELAY_REQ: Delay_Req message (all clock types) + * - ETH_DMA_RXDESC_MTP_DELAY_RESP: Delay_Resp message (all clock types) + * - ETH_DMA_RXDESC_MTP_PDELAY_REQ: Pdelay_Req message (peer-to-peer transparent clock) + * - ETH_DMA_RXDESC_MTP_PDELAY_RESP: Pdelay_Resp message (peer-to-peer transparent clock) + * - ETH_DMA_RXDESC_MTP_PDELAY_RESP_FOLLOW_UP: Pdelay_Resp_Follow_Up message (peer-to-peer transparent clock) + * - ETH_DMA_RXDESC_MTP_ANNOUNCE: Announce message (Ordinary or Boundary clock) + * - ETH_DMA_RXDESC_MTP_MANAGEMENT: Management message (Ordinary or Boundary clock) + * - ETH_DMA_RXDESC_MTP_SIGNALING: Signaling message (Ordinary or Boundary clock) + * - ETH_DMA_RXDESC_MTP_DEFAULT: Default Datagram Type + * @retval int32_t: + * - LL_OK: Get datagram type success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL or pu32DatagramType == NULL + */ +int32_t ETH_DMA_GetRxDescDatagramType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32DatagramType) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcRxDesc) || (NULL == pu32DatagramType)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32DatagramType = pstcRxDesc->u32ExtendStatus & ETH_DMA_RXDESC_MTP; + } + + return i32Ret; +} + +/** + * @brief Get DMA Rx descriptor frame length. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32FrameLen Pointer to DMA Rx frame length + * @retval int32_t: + * - LL_OK: Get frame length success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL or pu32FrameLen == NULL + */ +int32_t ETH_DMA_GetRxDescFrameLen(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32FrameLen) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcRxDesc) || (NULL == pu32FrameLen)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32FrameLen = (pstcRxDesc->u32ControlStatus >> ETH_DMA_RXDESC_FRAME_LEN_SHIFT) & ((uint32_t)0x00003FFFUL); + } + + return i32Ret; +} + +/** + * @brief Get DMA Rx descriptor buffer size. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u8BufNum Buffer sequence number + * This parameter can be one of the following values: + * @arg ETH_DMA_DESC_BUF1: DMA Rx Desc Buffer1 + * @arg ETH_DMA_DESC_BUF2: DMA Rx Desc Buffer2 + * @param [out] pu32BufSize Pointer to DMA Rx buffer size + * @retval int32_t: + * - LL_OK: Get buffer size success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL or pu32BufSize == NULL + */ +int32_t ETH_DMA_GetRxDescBufSize(const stc_eth_dma_desc_t *pstcRxDesc, uint8_t u8BufNum, uint32_t *pu32BufSize) +{ + int32_t i32Ret = LL_OK; + uint32_t u32ShiftBit = 0UL; + + if ((NULL == pstcRxDesc) || (NULL == pu32BufSize)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_DESC_BUF(u8BufNum)); + + /* DMA Rx Desc buffer2 */ + if (ETH_DMA_DESC_BUF1 != u8BufNum) { + u32ShiftBit = ETH_DMA_DESC_BUF2_SIZE_SHIFT; + } + *pu32BufSize = (pstcRxDesc->u32ControlBufSize >> u32ShiftBit) & ((uint32_t)0x00001FFFUL); + } + + return i32Ret; +} + +/** + * @brief Get DMA Rx descriptor timestamp. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32High Timestamp high bit time + * @param [out] pu32Low Timestamp low bit time + * @retval int32_t: + * - LL_OK: Get timestamp success + * - LL_ERR_INVD_PARAM: pstcRxDesc == NULL or pu32High == NULL or pu32Low == NULL + */ +int32_t ETH_DMA_GetRxDescTimeStamp(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32High, uint32_t *pu32Low) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pstcRxDesc) || (NULL == pu32High) || (NULL == pu32Low)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32Low = pstcRxDesc->u32TimestampLow; + *pu32High = pstcRxDesc->u32TimestampHigh; + } + + return i32Ret; +} + +/******************************************************************************/ +/* PMT Functions */ +/******************************************************************************/ +/** + * @brief Reset PMT wakeup frame pointer. + * @param None + * @retval int32_t: + * - LL_OK: Reset pointer success + * - LL_ERR_TIMEOUT: Reset timeout + */ +int32_t ETH_PMT_ResetWakeupFramePointer(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_ETH->MAC_PMTCTLR_b.RTWKFR, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->MAC_PMTCTLR_b.RTWKFR)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} +/** + * @brief Write PMT wakeup frame register. + * @param [in] au32RegBuf Pointer to wakeup frame filter register buffer(8 words). + * @retval int32_t: + * - LL_OK: Write register success + * - LL_ERR_INVD_PARAM: au32RegBuf == NULL + */ +int32_t ETH_PMT_WriteWakeupFrameReg(const uint32_t au32RegBuf[]) +{ + uint32_t i; + int32_t i32Ret = LL_OK; + + if (NULL == au32RegBuf) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + for (i = 0U; i < ETH_WAKEUP_REG_LEN; i++) { + WRITE_REG32(CM_ETH->MAC_RTWKFFR, au32RegBuf[i]); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable PMT forward wakeup frame. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_PMT_ForwardWakeupFrameCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MAC_PMTCTLR_b.RTWKTR, enNewState); +} + +/** + * @brief Enable or disable PMT wakeup source. + * @param [in] u32WakeupSrc Wakeup source + * This parameter can be one or any combination of the following values: + * @arg ETH_PMT_WAKEUP_SRC_GLOBAL_UNICAST: Global unicast + * @arg ETH_PMT_WAKEUP_SRC_WAKEUP_FRAME: Wake-Up Frame + * @arg ETH_PMT_WAKEUP_SRC_MAGIC_PACKET: Magic Packet + * @arg ETH_PMT_WAKEUP_SRC_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_PMT_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PMT_WAKEUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(CM_ETH->MAC_PMTCTLR, u32WakeupSrc); + } else { + CLR_REG32_BIT(CM_ETH->MAC_PMTCTLR, u32WakeupSrc); + } +} + +/** + * @brief Enable or disable PMT powerdown mode. + * @param None + * @retval int32_t: + * - LL_OK: Set powerdown mode success + * - LL_ERR: Set powerdown mode failed + */ +int32_t ETH_PMT_EnterPowerDown(void) +{ + int32_t i32Ret = LL_ERR; + + if (0UL != READ_REG32(bCM_ETH->MAC_PMTCTLR_b.MPEN)) { + if (0UL != READ_REG32(bCM_ETH->MAC_PMTCTLR_b.WKEN)) { + WRITE_REG32(bCM_ETH->MAC_PMTCTLR_b.PWDN, ENABLE); + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get PMT flag status. + * @param [in] u32Flag PMT flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_PMT_FLAG_RTWKFR: Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WKFR: Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPFR: Magic Packet Received + * @arg ETH_PMT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_PMT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PMT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->MAC_PMTCTLR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* MMC Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MMC. + * @param None + * @retval int32_t: + * - LL_OK: MMC De-Initialize success +* - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t ETH_MMC_DeInit(void) +{ + WRITE_REG32(CM_ETH->MMC_MMCCTLR, 0UL); + WRITE_REG32(CM_ETH->MMC_RITCTLR, 0UL); + WRITE_REG32(CM_ETH->MMC_TITCTLR, 0UL); + + return ETH_MMC_CounterReset(); +} + +/** + * @brief Initialize MMC. + * @param [in] pstcMmcInit Pointer to a @ref stc_eth_mmc_init_t structure + * @retval int32_t: + * - LL_OK: MMC Initialize success + * - LL_ERR_INVD_PARAM: pstcMmcInit == NULL + */ +int32_t ETH_MMC_Init(const stc_eth_mmc_init_t *pstcMmcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMmcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_CNT_PRESET_MD(pstcMmcInit->u32PresetMode)); + DDL_ASSERT(IS_ETH_MMC_RD_RST(pstcMmcInit->u32ReadReset)); + DDL_ASSERT(IS_ETH_MMC_CNT_RELOAD(pstcMmcInit->u32Reload)); + + MODIFY_REG32(CM_ETH->MMC_MMCCTLR, + (ETH_MMC_MMCCTLR_MCPSEL | ETH_MMC_MMCCTLR_MCPSET | + ETH_MMC_MMCCTLR_ROR | ETH_MMC_MMCCTLR_COS), + (pstcMmcInit->u32PresetMode | pstcMmcInit->u32ReadReset | + pstcMmcInit->u32Reload)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_mmc_init_t to default values. + * @param [out] pstcMmcInit Pointer to a @ref stc_eth_mmc_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcMmcInit == NULL + */ +int32_t ETH_MMC_StructInit(stc_eth_mmc_init_t *pstcMmcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMmcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMmcInit->u32PresetMode = ETH_MMC_CNT_PRESET_MD_DISABLE; + pstcMmcInit->u32ReadReset = ETH_MMC_RD_RST_ENABLE; + pstcMmcInit->u32Reload = ETH_MMC_CNT_RELOAD_ENABLE; + } + + return i32Ret; +} + +/** + * @brief MMC all counter software reset. + * @param None + * @retval int32_t: + * - LL_OK: Reset success + * - LL_ERR_TIMEOUT: Reset timeout + */ +int32_t ETH_MMC_CounterReset(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_ETH->MMC_MMCCTLR_b.CRST, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->MMC_MMCCTLR_b.CRST)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the reset of all MMC counter after reading. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MMC_ResetAfterReadCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->MMC_MMCCTLR_b.ROR, enNewState); +} + +/** + * @brief Enable or disable MMC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MMC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + WRITE_REG32(bCM_ETH->MMC_MMCCTLR_b.MCF, DISABLE); + } else { + WRITE_REG32(bCM_ETH->MMC_MMCCTLR_b.MCF, ENABLE); + } +} + +/** + * @brief Enable or disable MMC transmit interrupt. + * @param [in] u32IntType MMC interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_INT_TXEDEIM: Tx excessive deferral error frame interrupt + * @arg ETH_MMC_INT_TXUGIM: Tx unicast good frame interrupt + * @arg ETH_MMC_INT_TXCAEIM: Tx carrier error frame interrupt + * @arg ETH_MMC_INT_TXECEIM: Tx excessive collision error frame interrupt + * @arg ETH_MMC_INT_TXLCEIM: Tx deferral collision error frame interrupt + * @arg ETH_MMC_INT_TXDEEIM: Tx deferral error frame interrupt + * @arg ETH_MMC_INT_TXMGIM: Tx multicast good frame interrupt + * @arg ETH_MMC_INT_TXBGIM: Tx broadcast good frame interrupt + * @arg ETH_MMC_INT_TX_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MMC_TxIntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_TX_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_ETH->MMC_TITCTLR, u32IntType); + } else { + SET_REG32_BIT(CM_ETH->MMC_TITCTLR, u32IntType); + } +} + +/** + * @brief Enable or disable MMC receive interrupt. + * @param [in] u32IntType MMC interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_INT_RXOEIM: Rx out of scope error frame interrupt + * @arg ETH_MMC_INT_RXLEIM: Rx length error frame interrupt + * @arg ETH_MMC_INT_RXUGIM: Rx unicast good frame interrupt + * @arg ETH_MMC_INT_RXREIM: Rx short error frame interrupt + * @arg ETH_MMC_INT_RXAEIM: Rx alignment error frame interrupt + * @arg ETH_MMC_INT_RXCEIM: Rx crc error frame interrupt + * @arg ETH_MMC_INT_RXMGIM: Rx multicast good frame interrupt + * @arg ETH_MMC_INT_RXBGIM: Rx broadcast good frame interrupt + * @arg ETH_MMC_INT_RX_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_MMC_RxIntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_RX_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_ETH->MMC_RITCTLR, u32IntType); + } else { + SET_REG32_BIT(CM_ETH->MMC_RITCTLR, u32IntType); + } +} + +/** + * @brief Get MMC flag transmit status. + * @param [in] u32Flag MMC flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_FLAG_TXEDEIS: Tx excessive deferral error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXUGIS: Tx unicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXCAEIS: Tx carrier error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXECEIS: Tx excessive collision error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXLCEIS: Tx deferral collision error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXDEEIS: Tx deferral error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXMGIS: Tx multicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXBGIS: Tx broadcast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TX_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_MMC_GetTxStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_TX_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->MMC_TRSSTSR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Get MMC receive flag status. + * @param [in] u32Flag MMC flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_FLAG_RXOEIS: Rx out of scope error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXLEIS: Rx length error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXUGIS: Rx unicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXREIS: Rx short error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXAEIS: Rx alignment error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXCEIS: Rx crc error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXMGIS: Rx multicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXBGIS: Rx broadcast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RX_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_MMC_GetRxStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_RX_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->MMC_REVSTSR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Get MMC register. + * @param [in] u32Reg MMC statistics register + * This parameter can be one of the following values: + * @arg ETH_MMC_REG_TXBRGFR: Tx broadcast good frame Statistical Register + * @arg ETH_MMC_REG_TXMUGFR: Tx multicast good frame Statistical Register + * @arg ETH_MMC_REG_TXDEEFR: Tx deferral error frame Statistical Register + * @arg ETH_MMC_REG_TXLCEFR: Tx deferral collision error frame Statistical Register + * @arg ETH_MMC_REG_TXECEFR: Tx excessive collision error frame Statistical Register + * @arg ETH_MMC_REG_TXCAEFR: Tx carrier error frame Statistical Register + * @arg ETH_MMC_REG_TXUNGFR: Tx unicast good frame Statistical Register + * @arg ETH_MMC_REG_TXEDEFR: Tx excessive deferral error frame Statistical Register + * @arg ETH_MMC_REG_RXBRGFR: Rx broadcast good frame Statistical Register + * @arg ETH_MMC_REG_RXMUGFR: Rx multicast good frame Statistical Register + * @arg ETH_MMC_REG_RXCREFR: Rx crc error frame Statistical Register + * @arg ETH_MMC_REG_RXALEFR: Rx alignment error frame Statistical Register + * @arg ETH_MMC_REG_RXRUEFR: Rx short error frame Statistical Register + * @arg ETH_MMC_REG_RXUNGFR: Rx unicast good frame Statistical Register + * @arg ETH_MMC_REG_RXLEEFR: Rx length error frame Statistical Register + * @arg ETH_MMC_REG_RXOREFR: Rx out of scope error frame Statistical Register + * @retval uint32_t MMC statistics Register value + */ +uint32_t ETH_MMC_GetReg(uint32_t u32Reg) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_REG(u32Reg)); + + return (*(__IO uint32_t *)((uint32_t)(&CM_ETH->MAC_CONFIGR) + u32Reg)); +} + +/******************************************************************************/ +/* PTP Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize PTP. + * @param None + * @retval None + */ +void ETH_PTP_DeInit(void) +{ + WRITE_REG32(CM_ETH->PTP_TSPCTLR, 0x00002000UL); + WRITE_REG32(CM_ETH->PTP_TSPADDR, 0UL); + WRITE_REG32(CM_ETH->PTP_TSPNSAR, 0UL); + WRITE_REG32(CM_ETH->PTP_TMUSECR, 0UL); + WRITE_REG32(CM_ETH->PTP_TMUNSER, 0UL); +} + +/** + * @brief Initialize PTP. + * @param [in] pstcPtpInit Pointer to a @ref stc_eth_ptp_init_t structure + * @retval int32_t: + * - LL_OK: PTP Initialize success + * - LL_ERR: PTP Initialize failed + * - LL_ERR_INVD_PARAM: pstcPtpInit == NULL + */ +int32_t ETH_PTP_Init(const stc_eth_ptp_init_t *pstcPtpInit) +{ + int32_t i32Ret; + + if (NULL == pstcPtpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_DEST_ADDR_FILTER(pstcPtpInit->u32DestAddrFilter)); + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_VER(pstcPtpInit->u32DatagramVersion)); + DDL_ASSERT(IS_ETH_PTP_SUBSEC_SCALE(pstcPtpInit->u32SubsecScale)); + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_TYPE(pstcPtpInit->u32SnapDatagramType)); + DDL_ASSERT(IS_ETH_PTP_FRAME_TYPE(pstcPtpInit->u32SnapFrameType)); + DDL_ASSERT(IS_ETH_PTP_CALIB_MD(pstcPtpInit->u32CalibMode)); + DDL_ASSERT(IS_ETH_PTP_SUB_SEC(pstcPtpInit->u32SubsecInitValue)); + + /* Enable timestamp function */ + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPEN, (uint32_t)ENABLE); + /* Set addend value registers */ + WRITE_REG32(CM_ETH->PTP_TSPNSAR, pstcPtpInit->u8SubsecAddend); + WRITE_REG32(CM_ETH->PTP_TSPADDR, pstcPtpInit->u32BasicAddend); + i32Ret = ETH_PTP_UpdateBasicAddend(); + if (LL_OK == i32Ret) { + /* Set timestamp control register */ + MODIFY_REG32(CM_ETH->PTP_TSPCTLR, ETH_PTP_TSPCTLR_CLR_MASK, + (pstcPtpInit->u32DestAddrFilter | pstcPtpInit->u32SnapDatagramType | + pstcPtpInit->u32SnapFrameType | pstcPtpInit->u32DatagramVersion | + pstcPtpInit->u32SubsecScale | pstcPtpInit->u32CalibMode)); + /* Set initialize value */ + WRITE_REG32(CM_ETH->PTP_TMUSECR, pstcPtpInit->u32SecInitValue); + WRITE_REG32(CM_ETH->PTP_TMUNSER, pstcPtpInit->u32SubsecInitValue); + i32Ret = ETH_PTP_SysTimeInit(); + if (LL_OK != i32Ret) { + i32Ret = LL_ERR; + } + } else { + i32Ret = LL_ERR; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_ptp_init_t to default values. + * @param [out] pstcPtpInit Pointer to a @ref stc_eth_ptp_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcPtpInit == NULL + */ +int32_t ETH_PTP_StructInit(stc_eth_ptp_init_t *pstcPtpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcPtpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPtpInit->u32DestAddrFilter = ETH_PTP_DEST_ADDR_FILTER_DISABLE; + pstcPtpInit->u32SnapDatagramType = ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY; + pstcPtpInit->u32SnapFrameType = ETH_PTP_FRAME_TYPE_IPV4_FRAME; + pstcPtpInit->u32DatagramVersion = ETH_PTP_DATAGRAM_VER_IEEE1588V1; + pstcPtpInit->u32SubsecScale = ETH_PTP_SUBSEC_SCALE_HEX; + pstcPtpInit->u32CalibMode = ETH_PTP_CALIB_MD_COARSE; + pstcPtpInit->u32BasicAddend = 0UL; + pstcPtpInit->u8SubsecAddend = 0U; + pstcPtpInit->u32SecInitValue = 0UL; + pstcPtpInit->u32SubsecInitValue = 0UL; + } + + return i32Ret; +} + +/** + * @brief Set PTP snapshot datagram type. + * @param [in] u32DatagramType Snapshot datagram type + * This parameter can be one of the following values: + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY: SYNC Follow_Up Delay_Req Delay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC: SYNC + * @arg ETH_PTP_DATAGRAM_TYPE_DELAY: Delay_Req + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY: SYNC Follow_Up Delay_Req Delay_Resp Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY: SYNC Pdelay_Req Pdelay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY: Delay_Req Pdelay_Req Pdelay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY: SYNC Delay_Req + * @arg ETH_PTP_DATAGRAM_TYPE_PDELAY: Pdelay_Req Pdelay_Resp + * @retval None + */ +void ETH_PTP_SetSnapDatagramType(uint32_t u32DatagramType) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_TYPE(u32DatagramType)); + + MODIFY_REG32(CM_ETH->PTP_TSPCTLR, ETH_PTP_TSPCTLR_TSPMTSEL, u32DatagramType); +} + +/** + * @brief Set PTP snapshot frame type. + * @param [in] u32FrameType Snapshot frame type + * This parameter can be one or any combination of the following values: + * @arg ETH_PTP_FRAME_TYPE_IPV4_FRAME: snapshot of IPv4 frame + * @arg ETH_PTP_FRAME_TYPE_IPV6_FRAME: snapshot of IPv6 frame + * @arg ETH_PTP_FRAME_TYPE_ETH_FRAME: snapshot of PTP over ethernet frame + * @arg ETH_PTP_FRAME_TYPE_RX_FRAME: snapshot of all received frame + * @arg ETH_PTP_FRAME_TYPE_ALL: All of the above + * @retval None + */ +void ETH_PTP_SetSnapFrameType(uint32_t u32FrameType) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_FRAME_TYPE(u32FrameType)); + + MODIFY_REG32(CM_ETH->PTP_TSPCTLR, + (ETH_PTP_TSPCTLR_TSPOVIPV4 | ETH_PTP_TSPCTLR_TSPOVIPV6 | ETH_PTP_TSPCTLR_TSPOVETH | + ETH_PTP_TSPCTLR_TSPEALL), u32FrameType); +} + +/** + * @brief Set PTP timestamp calibration mode. + * @param [in] u32CalibMode Timestamp calibration mode + * This parameter can be one of the following values: + * @arg ETH_PTP_CALIB_MD_COARSE: Coarse calibration + * @arg ETH_PTP_CALIB_MD_FINE: Fine calibration + * @retval None + */ +void ETH_PTP_SetCalibMode(uint32_t u32CalibMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_CALIB_MD(u32CalibMode)); + + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPUPSEL, u32CalibMode >> ETH_PTP_TSPCTLR_TSPUPSEL_POS); +} + +/** + * @brief Update PTP timestamp basic addend value. + * @note Update Timestamp addend value by basic addend register. + * @param None + * @retval int32_t: + * - LL_OK: Update timestamp addend value success + * - LL_ERR: Current state cannot be updated + * - LL_ERR_TIMEOUT: Update timeout + */ +int32_t ETH_PTP_UpdateBasicAddend(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_ERR; + + if (0UL == READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPADUP)) { + WRITE_REG32(bCM_ETH->MMC_MMCCTLR_b.CRST, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->MMC_MMCCTLR_b.CRST)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_ERR_TIMEOUT != i32Ret) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Update PTP timestamp system time. + * @note Update Timestamp system time by update second and update subsecond registers. + * @param None + * @retval int32_t: + * - LL_OK: Update timestamp system time success + * - LL_ERR: Current state cannot be updated + * - LL_ERR_TIMEOUT: Update timeout + */ +int32_t ETH_PTP_UpdateSysTime(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_ERR; + + if (0UL == READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPINI)) { + if (0UL == READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPUP)) { + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPUP, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPUP)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_ERR_TIMEOUT != i32Ret) { + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Initialize PTP timestamp system time. + * @note Initialize Timestamp system time by update second and update subsecond registers. + * @param None + * @retval int32_t: + * - LL_OK: Initialize timestamp system time success + * - LL_ERR: Current state cannot be initialized + * - LL_ERR_TIMEOUT: Initialize timeout + */ +int32_t ETH_PTP_SysTimeInit(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_ERR; + + if (0UL == READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPINI)) { + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPINI, 1U); + u32Count = ETH_WR_REG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPINI)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_ERR_TIMEOUT != i32Ret) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get PTP timestamp system time. + * @param [out] pu32Sec Pointer to Timestamp system time of Second + * @param [out] pu32Subsec Pointer to Timestamp system time of Subsecond + * @retval int32_t: + * - LL_OK: Get timestamp system time success + * - LL_ERR_INVD_PARAM: pu32Sec == NULL or pu32Subsec == NULL + */ +int32_t ETH_PTP_GetSysTime(uint32_t *pu32Sec, uint32_t *pu32Subsec) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pu32Sec) || (NULL == pu32Subsec)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32Sec = READ_REG32(CM_ETH->PTP_TMSSECR); + *pu32Subsec = READ_REG32(CM_ETH->PTP_TMSNSER); + } + + return i32Ret; +} + +/** + * @brief Set PTP timestamp addend value. + * @param [in] u32BasicAddend Timestamp basic addend value (Between 0x0 and 0xFFFFFFFF) + * @param [in] u8SubsecAddend Timestamp subsecond addend value (Between 0x0 and 0xFF) + * @retval None + */ +void ETH_PTP_SetBasicAddend(uint32_t u32BasicAddend, uint8_t u8SubsecAddend) +{ + WRITE_REG32(CM_ETH->PTP_TSPADDR, u32BasicAddend); + WRITE_REG32(CM_ETH->PTP_TSPNSAR, u8SubsecAddend); +} + +/** + * @brief Get PTP timestamp addend value. + * @param [out] pu32BasicAddend Pointer to basic addend value + * @param [out] pu8SubsecAddend Pointer to subsecond addend value + * @retval int32_t: + * - LL_OK: Get timestamp addend value success + * - LL_ERR_INVD_PARAM: pu32BasicAddend == NULL or pu8SubsecAddend == NULL + */ +int32_t ETH_PTP_GetBasicAddend(uint32_t *pu32BasicAddend, uint8_t *pu8SubsecAddend) +{ + int32_t i32Ret = LL_OK; + + if ((NULL == pu32BasicAddend) || (NULL == pu8SubsecAddend)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32BasicAddend = READ_REG32(CM_ETH->PTP_TSPADDR); + *pu8SubsecAddend = (uint8_t)(READ_REG32(CM_ETH->PTP_TSPNSAR) & ETH_PTP_TSPNSAR_TSPNSEADD); + } + + return i32Ret; +} + +/** + * @brief Set PTP timestamp update time. + * @param [in] u32Sign Timestamp Update Sign + * @arg ETH_PTP_TIME_UPDATE_SIGN_MINUS: Minus + * @arg ETH_PTP_TIME_UPDATE_SIGN_PLUS: Plus + * @param [in] u32Sec Update time of Second (Between 0x0 and 0xFFFFFFFF) + * @param [in] u32Subsec Update time of Subsecond (Between 0x0 and 0x7FFFFFFF) + * @retval None + */ +void ETH_PTP_SetUpdateTime(uint32_t u32Sign, uint32_t u32Sec, uint32_t u32Subsec) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_TIME_UPDATE_SIGN(u32Sign)); + DDL_ASSERT(IS_ETH_PTP_SUB_SEC(u32Subsec)); + + WRITE_REG32(CM_ETH->PTP_TMUSECR, u32Sec); + WRITE_REG32(CM_ETH->PTP_TMUNSER, (u32Sign | u32Subsec)); +} + +/** + * @brief Enable or disable PTP function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_PTP_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPEN, enNewState); +} + +/** + * @brief Enable or disable PTP interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ETH_PTP_IntCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_ETH->PTP_TSPCTLR_b.TSPINT, enNewState); +} + +/** + * @brief Get PTP flag status. + * @param [in] u32Flag PTP flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_PTP_FLAG_TSERR1: Target time 1 error + * @arg ETH_PTP_FLAG_TSTAR1: Target time 1 reached + * @arg ETH_PTP_FLAG_TSERR0: Target time 0 error + * @arg ETH_PTP_FLAG_TSTAR0: Target time 0 reached + * @arg ETH_PTP_FLAG_TSOVF: System time overflow + * @arg ETH_PTP_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ETH_PTP_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_ETH->PTP_TSPSTSR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* PTP PPS Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize PTP PPS. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_CH0: PPS Channel 0 + * @arg ETH_PPS_CH1: PPS Channel 1 + * @retval None + */ +void ETH_PPS_DeInit(uint8_t u8Ch) +{ + uint32_t u32ShiftStep = 0UL; + uint32_t u32ShiftBit = 0UL; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_CH(u8Ch)); + + if (ETH_PPS_CH1 == u8Ch) { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDR_SHIFT; + } + CLR_REG32_BIT(CM_ETH->PTP_PPSCTLR, + ((ETH_PTP_PPSCTLR_PPSFRE0 | ETH_PTP_PPSCTLR_PPSOMD | ETH_PTP_PPSCTLR_TT0SEL) << u32ShiftBit)); + /* Clear target time registers */ + PTP_TMTSECR = ETH_PTP_TMTSECR_ADDR(u32ShiftStep); + PTP_TMTNSER = ETH_PTP_TMTNSER_ADDR(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, 0UL); + WRITE_REG32(*PTP_TMTNSER, 0UL); +} + +/** + * @brief Initialize PTP PPS. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_CH0: PPS Channel 0 + * @arg ETH_PPS_CH1: PPS Channel 1 + * @param [in] pstcPpsInit Pointer to a @ref stc_eth_pps_config_t structure + * @retval int32_t: + * - LL_OK: PPS Initialize success + * - LL_ERR_INVD_PARAM: pstcPpsInit == NULL + */ +int32_t ETH_PPS_Init(uint8_t u8Ch, const stc_eth_pps_config_t *pstcPpsInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32ShiftStep = 0UL; + uint32_t u32ShiftBit = 0UL; + uint32_t u32RegVal; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + if (NULL == pstcPpsInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PTP_SUB_SEC(pstcPpsInit->u32SubsecValue)); + DDL_ASSERT(IS_ETH_PPS_TRIG_FUNC(pstcPpsInit->u32TriggerFunc)); + DDL_ASSERT(IS_ETH_PPS_OUTPUT_MD(pstcPpsInit->u32OutputMode)); + DDL_ASSERT(IS_ETH_PPS_OUTPUT_FREQ(pstcPpsInit->u32OutputFreq)); + DDL_ASSERT(IS_ETH_PPS1_COMPLEX_FUNC(u8Ch, pstcPpsInit->u32OutputMode, pstcPpsInit->u32OutputFreq)); + + u32RegVal = pstcPpsInit->u32OutputFreq | pstcPpsInit->u32TriggerFunc; + if (ETH_PPS_CH1 == u8Ch) { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDR_SHIFT; + } else { + u32RegVal |= pstcPpsInit->u32OutputMode; + } + MODIFY_REG32(CM_ETH->PTP_PPSCTLR, + ((ETH_PTP_PPSCTLR_PPSFRE0 | ETH_PTP_PPSCTLR_PPSOMD | ETH_PTP_PPSCTLR_TT0SEL) << u32ShiftBit), + (u32RegVal << u32ShiftBit)); + /* Set target time registers */ + PTP_TMTSECR = ETH_PTP_TMTSECR_ADDR(u32ShiftStep); + PTP_TMTNSER = ETH_PTP_TMTNSER_ADDR(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, pstcPpsInit->u32SecValue); + WRITE_REG32(*PTP_TMTNSER, pstcPpsInit->u32SubsecValue); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_eth_pps_config_t to default values. + * @param [out] pstcPpsInit Pointer to a @ref stc_eth_pps_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcPpsInit == NULL + */ +int32_t ETH_PPS_StructInit(stc_eth_pps_config_t *pstcPpsInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcPpsInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPpsInit->u32TriggerFunc = ETH_PPS_TRIG_FUNC_INT_EVT; + pstcPpsInit->u32OutputMode = ETH_PPS_OUTPUT_MD_ONCE; + pstcPpsInit->u32OutputFreq = ETH_PPS_OUTPUT_ONE_PULSE; + pstcPpsInit->u32SecValue = 0UL; + pstcPpsInit->u32SubsecValue = 0UL; + } + + return i32Ret; +} + +/** + * @brief Set PTP Target time function. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_CH0: PPS Channel 0 + * @arg ETH_PPS_CH1: PPS Channel 1 + * @param [in] u32Sec Target time of Second (Between 0x0 and 0xFFFFFFFF) + * @param [in] u32Subsec Target time of Subsecond (Between 0x0 and 0x7FFFFFFF) + * @retval None + */ +void ETH_PPS_SetTargetTime(uint8_t u8Ch, uint32_t u32Sec, uint32_t u32Subsec) +{ + uint32_t u32ShiftStep = 0UL; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PTP_SUB_SEC(u32Subsec)); + + if (ETH_PPS_CH1 == u8Ch) { + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDR_SHIFT; + } + PTP_TMTSECR = ETH_PTP_TMTSECR_ADDR(u32ShiftStep); + PTP_TMTNSER = ETH_PTP_TMTNSER_ADDR(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, u32Sec); + WRITE_REG32(*PTP_TMTNSER, u32Subsec); +} + +/** + * @brief Set PTP Target time function. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_CH0: PPS Channel 0 + * @arg ETH_PPS_CH1: PPS Channel 1 + * @param [in] u32Func Arrival time trigger the function + * This parameter can be one of the following values: + * @arg ETH_PPS_TRIG_FUNC_INT_EVT: Interrupt output event + * @arg ETH_PPS_TRIG_FUNC_INT_PPS_EVT: Interrupt out event and PPS single output event + * @arg ETH_PPS_TRIG_FUNC_PPS_EVT: PPS Single output event + * @retval None + */ +void ETH_PPS_SetTriggerFunc(uint8_t u8Ch, uint32_t u32Func) +{ + uint32_t u32ShiftBit = 0UL; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PPS_TRIG_FUNC(u32Func)); + + if (ETH_PPS_CH1 == u8Ch) { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + } + MODIFY_REG32(CM_ETH->PTP_PPSCTLR, (ETH_PTP_PPSCTLR_TT0SEL << u32ShiftBit), (u32Func << u32ShiftBit)); +} + +/** + * @brief Set PTP PPS0 output mode. + * @param [in] u32Mode PPS output mode + * This parameter can be one of the following values: + * @arg ETH_PPS_OUTPUT_MD_CONTINUE: Continuous output mode + * @arg ETH_PPS_OUTPUT_MD_ONCE: Single output mode + * @retval None + */ +void ETH_PPS_SetPps0OutputMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_OUTPUT_MD(u32Mode)); + + WRITE_REG32(bCM_ETH->PTP_PPSCTLR_b.PPSOMD, u32Mode >> ETH_PTP_PPSCTLR_PPSOMD_POS); +} + +/** + * @brief Set PTP PPS0 output frequency. + * @param [in] u32Freq PPS output frequency + * This parameter can be one of the following values: + * @arg ETH_PPS_OUTPUT_FREQ_1HZ: Ouput pulse is 1HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_2HZ: Ouput pulse is 2HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_4HZ: Ouput pulse is 4HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_8HZ: Ouput pulse is 8HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_16HZ: Ouput pulse is 16HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_32HZ: Ouput pulse is 32HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_64HZ: Ouput pulse is 64HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_128HZ: Ouput pulse is 128HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_256HZ: Ouput pulse is 256HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_512HZ: Ouput pulse is 512HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_1024HZ: Ouput pulse is 1024HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_2048HZ: Ouput pulse is 2048HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_4096HZ: Ouput pulse is 4096HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_8192HZ: Ouput pulse is 8192HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_16384HZ: Ouput pulse is 16384HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_32768HZ: Ouput pulse is 32768HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_ONE_PULSE: One pulse is generated in single ouput mode + * @retval None + */ +void ETH_PPS_SetPps0OutputFreq(uint32_t u32Freq) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_OUTPUT_FREQ(u32Freq)); + + MODIFY_REG32(CM_ETH->PTP_PPSCTLR, ETH_PTP_PPSCTLR_PPSFRE0, u32Freq); +} + +/** + * @} + */ + +#endif /* LL_ETH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c new file mode 100644 index 0000000000..25fef9ada4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c @@ -0,0 +1,442 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.c + * @brief This file provides firmware functions to manage the Event Port (EP). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_event_port.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EVENT_PORT EVENT_PORT + * @brief Event Port Driver Library + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Local_Macros Event Port Local Macros + * @{ + */ +#define EP_OFFSET (0x1CUL) +#define PEVNTDIR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTDIRR1) + (EP_OFFSET * (x)))) +#define PEVNTIDR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTIDR1) + (EP_OFFSET * (x)))) +#define PEVNTODR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTODR1) + (EP_OFFSET * (x)))) +#define PEVNTORR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTORR1) + (EP_OFFSET * (x)))) +#define PEVNTOSR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTOSR1) + (EP_OFFSET * (x)))) +#define PEVNTRIS_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTRISR1) + (EP_OFFSET * (x)))) +#define PEVNTFAL_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTFAL1) + (EP_OFFSET * (x)))) +#define PEVNTTRGSR_RST_VALUE (0x1FFUL) +#define EP_PIN_MAX (16U) + +/** + * @defgroup EP_Check_Parameters_Validity Event Port Check Parameters Validity + * @{ + */ +/*! Parameter validity check for port group. */ +#define IS_EVENT_PORT(port) \ +( ((port) == EVT_PORT_1) || \ + ((port) == EVT_PORT_2) || \ + ((port) == EVT_PORT_3) || \ + ((port) == EVT_PORT_4)) + +/*! Parameter valid check for event port trigger edge. */ +#define IS_EP_TRIG_EDGE(edge) \ +( ((edge) == EP_TRIG_NONE) || \ + ((edge) == EP_TRIG_FALLING) || \ + ((edge) == EP_TRIG_RISING) || \ + ((edge) == EP_TRIG_BOTH)) + +/*! Parameter valid check for event port initial output state. */ +#define IS_EP_STATE(state) \ +( ((state) == EVT_PIN_RESET) || \ + ((state) == EVT_PIN_SET)) + +/*! Parameter valid check for event port filter function. */ +#define IS_EP_FILTER(filter) \ +( ((filter) == EP_FILTER_OFF) || \ + ((filter) == EP_FILTER_ON)) + +/*! Parameter validity check for pin. */ +#define IS_EVENT_PIN(pin) (((pin) & EVT_PIN_MASK ) != 0x0000U) + +/*! Parameter valid check for event port operation after triggered. */ +#define IS_EP_OPS(ops) \ +( ((ops) == EP_OPS_NONE) || \ + ((ops) == EP_OPS_LOW) || \ + ((ops) == EP_OPS_HIGH) || \ + ((ops) == EP_OPS_TOGGLE)) + +/*! Parameter valid check for event port direction. */ +#define IS_EP_DIR(dir) \ +( ((dir) == EP_DIR_IN) || \ + ((dir) == EP_DIR_OUT)) + +/*! Parameter valid check for event port filter clock div. */ +#define IS_EP_FILTER_CLK(clk) \ +( ((clk) == EP_FCLK_DIV1) || \ + ((clk) == EP_FCLK_DIV8) || \ + ((clk) == EP_FCLK_DIV32) || \ + ((clk) == EP_FCLK_DIV64)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EP_Global_Functions Event Port Global Functions + * @{ + */ + +/** + * @brief Initialize Event Port. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] pstcEventPortInit Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit) +{ + uint16_t u16PinPos; + int32_t i32Ret = LL_OK; + + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(pstcEventPortInit->u32PinTriggerOps)); + DDL_ASSERT(IS_EP_DIR(pstcEventPortInit->u32PinDir)); + DDL_ASSERT(IS_EP_STATE(pstcEventPortInit->enPinState)); + DDL_ASSERT(IS_EP_TRIG_EDGE(pstcEventPortInit->u32Edge)); + DDL_ASSERT(IS_EP_FILTER(pstcEventPortInit->u32Filter)); + DDL_ASSERT(IS_EP_FILTER_CLK(pstcEventPortInit->u32FilterClock)); + + for (u16PinPos = 0U; u16PinPos < EP_PIN_MAX; u16PinPos++) { + if ((u16EventPin & (1UL << u16PinPos)) != 0U) { + /* Direction config */ + if (EP_DIR_OUT == pstcEventPortInit->u32PinDir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } + /* Set pin initial output value */ + if (EVT_PIN_SET == pstcEventPortInit->enPinState) { + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } + /* Set Pin operation after triggered */ + (void)EP_SetTriggerOps(u8EventPort, u16EventPin, pstcEventPortInit->u32PinTriggerOps); + /* Set trigger edge */ + (void)EP_SetTriggerEdge(u8EventPort, u16EventPin, pstcEventPortInit->u32Edge); + } + MODIFY_REG32(CM_AOS->PEVNTNFCR, \ + ((AOS_PEVNTNFCR_NFEN1 | AOS_PEVNTNFCR_DIVS1) << (u8EventPort * 8UL)), \ + ((pstcEventPortInit->u32Filter | pstcEventPortInit->u32FilterClock) << (u8EventPort * 8UL))); + } + } + return i32Ret; +} + +/** + * @brief De-init Event Port register to default value + * @param None + * @retval None + */ +void EP_DeInit(void) +{ + uint8_t u8EventPort; + + /* Restore all registers to default value */ + WRITE_REG32(CM_AOS->PEVNTTRGSR12, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTTRGSR34, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTNFCR, 0UL); + for (u8EventPort = EVT_PORT_1; u8EventPort < EVT_PORT_4; u8EventPort++) { + WRITE_REG32(PEVNTDIR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTODR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTORR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTOSR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTRIS_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTFAL_REG(u8EventPort), 0UL); + } +} + +/** + * @brief Initialize Event Port config structure. Fill each pstcEventPortInit with default value + * @param [in] pstcEventPortInit: Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset Event Port init structure parameters values */ + pstcEventPortInit->u32PinDir = EP_DIR_IN; + pstcEventPortInit->enPinState = EVT_PIN_RESET; + pstcEventPortInit->u32PinTriggerOps = EP_OPS_NONE; + pstcEventPortInit->u32Edge = EP_TRIG_NONE; + pstcEventPortInit->u32Filter = EP_FILTER_OFF; + pstcEventPortInit->u32FilterClock = EP_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Set event port trigger edge. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Edge: Trigger edge, @ref EP_Trigger_Sel for details + * @retval int32_t: + * - LL_OK: Trigger edge set successful + * - LL_ERR_INVD_PARAM: Undefined edge + */ +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_TRIG_EDGE(u32Edge)); + + /* Set trigger edge */ + switch (u32Edge) { + case EP_TRIG_NONE: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_FALLING: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_RISING: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_BOTH: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Set event port opeartion after triggered + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Ops: The operation after triggered, @ref EP_TriggerOps_Sel for details + * @retval Specified Event port pin input value + */ +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(u32Ops)); + + switch (u32Ops) { + case EP_OPS_NONE: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_LOW: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_HIGH: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_TOGGLE: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Read specified Event port input data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin input value + */ +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTIDR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port input data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port input value + */ +uint16_t EP_ReadInputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTIDR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Read specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin output value + */ +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTODR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port output data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port output value + */ +uint16_t EP_ReadOutputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTODR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Set specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Reset specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Set specified Event port pins direction + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Dir: Pin direction + * @arg EP_DIR_IN + * @arg EP_DIR_OUT + * @retval None + */ +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_DIR(u32Dir)); + + if (EP_DIR_OUT == u32Dir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } +} + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c new file mode 100644 index 0000000000..5082bc462f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.c + * @brief This file provides firmware functions to manage the Function Clock + * Gate (FCG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcg.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCG FCG + * @brief FCG Driver Library + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Local_Macros FCG Local Macros + * @{ + */ +#define IS_FCG0_UNLOCKED() ((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0) + +/** + * @defgroup FCG_Check_Parameters_Validity FCG Check Parameters Validity + * @{ + */ +/* Parameter validity check for peripheral in fcg0. */ +#define IS_FCG0_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG0_PERIPH_MASK) == FCG_FCG0_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg1. */ +#define IS_FCG1_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG1_PERIPH_MASK) == FCG_FCG1_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg2. */ +#define IS_FCG2_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG2_PERIPH_MASK) == FCG_FCG2_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg3. */ +#define IS_FCG3_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG3_PERIPH_MASK) == FCG_FCG3_PERIPH_MASK)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Functions FCG Global Functions + * @{ + */ + +/** + * @brief Enable or disable the FCG0 peripheral clock. + * @param [in] u32Fcg0Periph The peripheral in FCG0 @ref FCG_FCG0_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_FCG0_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } +} + +/** + * @brief Enable or disable the FCG1 peripheral clock. + * @param [in] u32Fcg1Periph The peripheral in FCG1 @ref FCG_FCG1_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } +} + +/** + * @brief Enable or disable the FCG2 peripheral clock. + * @param [in] u32Fcg2Periph The peripheral in FCG2 @ref FCG_FCG2_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } +} + +/** + * @brief Enable or disable the FCG3 peripheral clock. + * @param [in] u32Fcg3Periph The peripheral in FCG3 @ref FCG_FCG3_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } +} + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c new file mode 100644 index 0000000000..594a562bce --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c @@ -0,0 +1,385 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.c + * @brief This file provides firmware functions to manage the Frequency Clock + * Measurement (FCM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCM FCM + * @brief FCM Driver Library + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Local_Macros FCM Local Macros + * @{ + */ + +/* FCM Registers RESET Value */ +#define FCM_REG_RST_VALUE (0x00000000UL) + +/* FCM interrupt mask */ +#define FCM_INT_MASK (FCM_INT_OVF | FCM_INT_END | FCM_INT_ERR) +/* FCM status flag mask */ +#define FCM_FLAG_MASK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF) + +/** + * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity + * @{ + */ + +/* Parameter validity check for FCM target and reference clock source. */ +#define IS_FCM_TARGET_SRC(x) \ +( ((x) == FCM_TARGET_CLK_XTAL) || \ + ((x) == FCM_TARGET_CLK_XTAL32) || \ + ((x) == FCM_TARGET_CLK_HRC) || \ + ((x) == FCM_TARGET_CLK_LRC) || \ + ((x) == FCM_TARGET_CLK_SWDTLRC) || \ + ((x) == FCM_TARGET_CLK_PCLK1) || \ + ((x) == FCM_TARGET_CLK_PLLAP) || \ + ((x) == FCM_TARGET_CLK_MRC) || \ + ((x) == FCM_TARGET_CLK_PLLHP) || \ + ((x) == FCM_TARGET_CLK_RTCLRC)) + +#define IS_FCM_REF_SRC(x) \ +( ((x) == FCM_REF_CLK_XTAL) || \ + ((x) == FCM_REF_CLK_XTAL32) || \ + ((x) == FCM_REF_CLK_HRC) || \ + ((x) == FCM_REF_CLK_LRC) || \ + ((x) == FCM_REF_CLK_SWDTLRC) || \ + ((x) == FCM_REF_CLK_PCLK1) || \ + ((x) == FCM_REF_CLK_PLLAP) || \ + ((x) == FCM_REF_CLK_MRC) || \ + ((x) == FCM_REF_CLK_PLLHP) || \ + ((x) == FCM_REF_CLK_RTCLRC)) + +/* Parameter validity check for FCM target clock division. */ +#define IS_FCM_TARGET_DIV(x) \ +( ((x) == FCM_TARGET_CLK_DIV1) || \ + ((x) == FCM_TARGET_CLK_DIV4) || \ + ((x) == FCM_TARGET_CLK_DIV8) || \ + ((x) == FCM_TARGET_CLK_DIV32)) + +/* Parameter validity check for FCM external reference input function. */ +#define IS_FCM_EXT_REF_FUNC(x) \ +( ((x) == FCM_EXT_REF_OFF) || \ + ((x) == FCM_EXT_REF_ON)) + +/* Parameter validity check for FCM reference clock edge. */ +#define IS_FCM_REF_EDGE(x) \ +( ((x) == FCM_REF_CLK_RISING) || \ + ((x) == FCM_REF_CLK_FALLING) || \ + ((x) == FCM_REF_CLK_BOTH)) + +/* Parameter validity check for FCM digital filter function. */ +#define IS_FCM_DIG_FILTER(x) \ +( ((x) == FCM_DIG_FILTER_OFF) || \ + ((x) == FCM_DIG_FILTER_DIV1) || \ + ((x) == FCM_DIG_FILTER_DIV4) || \ + ((x) == FCM_DIG_FILTER_DIV16)) + +/* Parameter validity check for FCM reference clock division. */ +#define IS_FCM_REF_DIV(x) \ +( ((x) == FCM_REF_CLK_DIV32) || \ + ((x) == FCM_REF_CLK_DIV128) || \ + ((x) == FCM_REF_CLK_DIV1024) || \ + ((x) == FCM_REF_CLK_DIV8192)) + +/* Parameter validity check for FCM exception type function. */ +#define IS_FCM_EXP_TYPE(x) \ +( ((x) == FCM_EXP_TYPE_INT) || \ + ((x) == FCM_EXP_TYPE_RST)) + +/* Parameter validity check for FCM interrupt. */ +#define IS_FCM_INT(x) (((x) | FCM_INT_MASK) == FCM_INT_MASK) + +/* Parameter validity check for FCM flag state. */ +#define IS_FCM_FLAG(x) \ +( ((x) != 0x00UL) && \ + (((x) | FCM_FLAG_MASK) == FCM_FLAG_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Functions FCM Global Functions + * @{ + */ + +/** + * @brief Initialize FCM. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_FCM_TARGET_SRC(pstcFcmInit->u32TargetClock)); + DDL_ASSERT(IS_FCM_TARGET_DIV(pstcFcmInit->u32TargetClockDiv)); + DDL_ASSERT(IS_FCM_EXT_REF_FUNC(pstcFcmInit->u32ExtRefClockEnable)); + DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClockEdge)); + DDL_ASSERT(IS_FCM_DIG_FILTER(pstcFcmInit->u32DigitalFilter)); + DDL_ASSERT(IS_FCM_REF_SRC(pstcFcmInit->u32RefClock)); + DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClockDiv)); + DDL_ASSERT(IS_FCM_EXP_TYPE(pstcFcmInit->u32ExceptionType)); + + WRITE_REG32(CM_FCM->LVR, pstcFcmInit->u16LowerLimit); + WRITE_REG32(CM_FCM->UVR, pstcFcmInit->u16UpperLimit); + WRITE_REG32(CM_FCM->MCCR, (pstcFcmInit->u32TargetClock | pstcFcmInit->u32TargetClockDiv)); + WRITE_REG32(CM_FCM->RCCR, (pstcFcmInit->u32ExtRefClockEnable | pstcFcmInit->u32RefClockEdge | + pstcFcmInit->u32DigitalFilter | pstcFcmInit->u32RefClock | + pstcFcmInit->u32RefClockDiv)); + MODIFY_REG32(CM_FCM->RIER, FCM_RIER_ERRINTRS, pstcFcmInit->u32ExceptionType); + } + return i32Ret; +} + +/** + * @brief Initialize FCM structure. Fill each pstcFcmInit with default value. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM structure initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET FCM init structure parameters values */ + pstcFcmInit->u16LowerLimit = 0U; + pstcFcmInit->u16UpperLimit = 0U; + pstcFcmInit->u32TargetClock = FCM_TARGET_CLK_XTAL; + pstcFcmInit->u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + pstcFcmInit->u32ExtRefClockEnable = FCM_EXT_REF_OFF; + pstcFcmInit->u32RefClockEdge = FCM_REF_CLK_RISING; + pstcFcmInit->u32DigitalFilter = FCM_DIG_FILTER_OFF; + pstcFcmInit->u32RefClock = FCM_REF_CLK_XTAL; + pstcFcmInit->u32RefClockDiv = FCM_REF_CLK_DIV32; + pstcFcmInit->u32ExceptionType = FCM_EXP_TYPE_INT; + } + return i32Ret; +} + +/** + * @brief De-Initialize FCM. + * @param None + * @retval None + */ +void FCM_DeInit(void) +{ + WRITE_REG32(CM_FCM->STR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->CLR, FCM_FLAG_MASK); + WRITE_REG32(CM_FCM->LVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->UVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->MCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RIER, FCM_REG_RST_VALUE); +} + +/** + * @brief Get FCM state, get FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t FCM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_FCM->SR, u32Flag) != 0UL) ? SET : RESET); +} + +/** + * @brief Clear FCM state, Clear FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval None. + */ +void FCM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + SET_REG32_BIT(CM_FCM->CLR, u32Flag); +} + +/** + * @brief Get FCM counter value. + * @param None + * @retval FCM counter value. + */ +uint16_t FCM_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_FCM->CNTR) & 0xFFFFU); +} + +/** + * @brief FCM target clock type and division config. + * @param [in] u32ClockSrc Target clock type. @ref FCM_Target_Clock_Src + * @param [in] u32Div Target clock division. @ref FCM_Target_Clock_Div + * @arg FCM_TARGET_CLK_DIV1 + * @arg FCM_TARGET_CLK_DIV4 + * @arg FCM_TARGET_CLK_DIV8 + * @arg FCM_TARGET_CLK_DIV32 + * @retval None. + */ +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_TARGET_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_TARGET_DIV(u32Div)); + WRITE_REG32(CM_FCM->MCCR, (u32ClockSrc | u32Div)); +} + +/** + * @brief FCM reference clock type and division config. + * @param [in] u32ClockSrc Reference clock type. @ref FCM_Ref_Clock_Src + * @param [in] u32Div Reference clock division. @ref FCM_Ref_Clock_Div + * @arg FCM_REF_CLK_DIV32 + * @arg FCM_REF_CLK_DIV128 + * @arg FCM_REF_CLK_DIV1024 + * @arg FCM_REF_CLK_DIV8192 + * @retval None. + */ +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_REF_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_REF_DIV(u32Div)); + MODIFY_REG32(CM_FCM->RCCR, (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), (u32ClockSrc | u32Div)); +} + +/** + * @brief Enable or disable the FCM reset + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_ResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_FCM->RIER_b.ERRE, enNewState); +} + +/** + * @brief Enable or disable the FCM interrupt + * @param [in] u32IntType The FCM interrupt type. This parameter can be + * one or any combination @ref FCM_Int_Type + * @arg FCM_INT_OVF: FCM overflow interrupt + * @arg FCM_INT_END: FCM calculate end interrupt + * @arg FCM_INT_ERR: FCM frequency abnormal interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCM_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_FCM->RIER, u32IntType); + } else { + CLR_REG32_BIT(CM_FCM->RIER, u32IntType); + } +} + +/** + * @brief FCM function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None. + */ +void FCM_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_FCM->STR_b.START, enNewState); +} + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fmac.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fmac.c new file mode 100644 index 0000000000..9de18446b9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_fmac.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file hc32_ll_fmac.c + * @brief This file provides firmware functions to manage the Filter Math + * Accelerate (FMAC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fmac.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FMAC FMAC + * @brief FMAC Driver Library + * @{ + */ + +#if (LL_FMAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FMAC_Local_Macros FMAC Local Macros + * @{ + */ + +/** + * @defgroup FMAC_Check_Parameters_Validity FMAC Check Parameters Validity + * @{ + */ +#define IS_FMAC_FIR_SHIFT(x) ((x) <= FMAC_FIR_SHIFT_21BIT) + +#define IS_FMAC_FIR_STAGE(x) ((x) <= FMAC_FIR_STAGE_16) + +#define IS_FMAC_INT_FUNC(x) \ +( ((x) == FMAC_INT_ENABLE) || \ + ((x) == FMAC_INT_DISABLE)) + +#define IS_VALID_UNIT(x) \ +( ((x) == CM_FMAC1) || \ + ((x) == CM_FMAC2) || \ + ((x) == CM_FMAC3) || \ + ((x) == CM_FMAC4)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FMAC_Global_Functions FMAC Global Functions + * @{ + */ + +/** + * @brief FMAC peripheral initialization stucture clear + * @param [in] pstcFmacInit FMAC function structure + * @arg See the structure definition for @ref stc_fmac_init_t + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t FMAC_StructInit(stc_fmac_init_t *pstcFmacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcFmacInit != NULL) { + pstcFmacInit->u32Stage = FMAC_FIR_STAGE_0; + pstcFmacInit->u32Shift = FMAC_FIR_SHIFT_0BIT; + pstcFmacInit->pi16Factor = NULL; + pstcFmacInit->u32IntCmd = FMAC_INT_DISABLE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-Initialize FMAC function + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @retval None + */ +void FMAC_DeInit(CM_FMAC_TypeDef *FMACx) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + + WRITE_REG32(FMACx->CTR, 0UL); + WRITE_REG32(FMACx->IER, 0UL); + WRITE_REG32(FMACx->DTR, 0UL); + WRITE_REG32(FMACx->RTR0, 0UL); + WRITE_REG32(FMACx->RTR1, 0UL); + WRITE_REG32(FMACx->STR, 0UL); +} + +/** + * @brief FMAC peripheral function initialize + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] pstcFmacInit FMAC function base parameter structure + * @arg See the structure definition for @ref stc_fmac_init_t + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t FMAC_Init(CM_FMAC_TypeDef *FMACx, const stc_fmac_init_t *pstcFmacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + int16_t *pi16Factor; + __IO uint32_t *FMAC_CORx; + uint32_t i; + if ((pstcFmacInit != NULL) && (pstcFmacInit->pi16Factor != NULL)) { + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FIR_SHIFT(pstcFmacInit->u32Shift)); + DDL_ASSERT(IS_FMAC_FIR_STAGE(pstcFmacInit->u32Stage)); + DDL_ASSERT(IS_FMAC_INT_FUNC(pstcFmacInit->u32IntCmd)); + + pi16Factor = (pstcFmacInit->pi16Factor); + /* Configure filter stage and results right shift bits */ + WRITE_REG32(FMACx->CTR, (pstcFmacInit->u32Stage | (pstcFmacInit->u32Shift << FMAC_CTR_SHIFT_POS))); + /* Configure interrupt command */ + WRITE_REG32(FMACx->IER, pstcFmacInit->u32IntCmd); + for (i = 0U; i < pstcFmacInit->u32Stage + 1U; i++) { + FMAC_CORx = (__IO uint32_t *)((uint32_t)(&FMACx->COR0) + (i << 2UL)); + WRITE_REG32(*FMAC_CORx, *pi16Factor++); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Enable or Disable FMAC + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FMAC_Cmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(FMACx->ENR, enNewState); +} + +/** + * @brief Set Filter result shift bits. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] u32ShiftNum Result shift times. + * This parameter can be one of @ref FMAC_Filter_Shift + * @retval None + */ +void FMAC_SetResultShift(CM_FMAC_TypeDef *FMACx, uint32_t u32ShiftNum) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FIR_SHIFT(u32ShiftNum)); + /* Set Filter result shift bits */ + MODIFY_REG32(FMACx->CTR, FMAC_CTR_SHIFT, u32ShiftNum << FMAC_CTR_SHIFT_POS); +} + +/** + * @brief Set filter stage and filter factor. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] u32FilterStage FMAC filter stage. + * This parameter can be one of @ref FMAC_Filter_Stage + * @param [in] pi16Factor FMAC filter factor. + * This parameter can be set -32768 ~ 32767 + * @retval None + */ +void FMAC_SetStageFactor(CM_FMAC_TypeDef *FMACx, uint32_t u32FilterStage, int16_t *pi16Factor) +{ + __IO uint32_t *FMAC_CORx; + uint8_t i; + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FIR_STAGE(u32FilterStage)); + /* FMAC Software reset */ + CLR_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN); + SET_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN); + /* Set the filter stage */ + MODIFY_REG32(FMACx->CTR, FMAC_CTR_STAGE_NUM, u32FilterStage); + for (i = 0U; i < (u32FilterStage + 1UL); i++) { + FMAC_CORx = (__IO uint32_t *)((uint32_t)(&FMACx->COR0) + ((uint32_t)i << 2UL)); + WRITE_REG32(*FMAC_CORx, *pi16Factor++); + } +} + +/** + * @brief Configure interrupt command. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FMAC_IntCmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(FMACx->IER, enNewState); +} + +/** + * @brief Data input. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [in] i16Factor Data that needs to be processed. + * @retval None + */ +void FMAC_FIRInput(CM_FMAC_TypeDef *FMACx, int16_t i16Factor) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + WRITE_REG32(FMACx->DTR, i16Factor); +} + +/** + * @brief Get FMAC status. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @retval An @ref en_flag_status_t enumeration type value. + * - SET Calculate complete + * - RESET Calculation in progress + */ +en_flag_status_t FMAC_GetStatus(const CM_FMAC_TypeDef *FMACx) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + return ((READ_REG32_BIT(FMACx->STR, FMAC_STR_READY) != 0UL) ? SET : RESET); +} + +/** + * @brief Get calculation results. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg CM_FMAC1: FMAC unit 1 instance register base + * @arg CM_FMAC2: FMAC unit 2 instance register base + * @arg CM_FMAC3: FMAC unit 3 instance register base + * @arg CM_FMAC4: FMAC unit 4 instance register base + * @param [out] pstcResult Get result. + * u32ResultHigh: The high value of the result + * u32ResultLow: The low value of the result + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: pstcResult == NULL + */ +int32_t FMAC_GetResult(const CM_FMAC_TypeDef *FMACx, stc_fmac_result_t *pstcResult) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + + if (pstcResult != NULL) { + pstcResult->u32ResultHigh = READ_REG32(FMACx->RTR0); + pstcResult->u32ResultLow = READ_REG32(FMACx->RTR1); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_FMAC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c new file mode 100644 index 0000000000..b2486e2eed --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c @@ -0,0 +1,650 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.c + * @brief This file provides firmware functions to manage the General Purpose + * Input/Output(GPIO). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_gpio.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_GPIO GPIO + * @brief GPIO Driver Library + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Types GPIO Local Typedefs + * @{ + */ +/** + * @brief GPIO port pin table definition + */ +typedef struct { + uint8_t u8Port; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinMask; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ +} stc_gpio_port_pin_tbl_t; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Macros GPIO Local Macros + * @{ + */ +/** + * @defgroup GPIO_Registers_Setting_definition GPIO Registers setting definition + * @{ + */ +#define GPIO_PSPCR_RST_VALUE (0x001FU) + +#define GPIO_PCCR_RST_VALUE (0x1000U) + +#define GPIO_PINAER_RST_VALUE (0x0000U) + +#define GPIO_PIN_NUM_MAX (16U) +#define GPIO_PORT_OFFSET (0x40UL) +#define GPIO_PIN_OFFSET (0x04UL) +#define GPIO_REG_OFFSET (0x10UL) +#define GPIO_REG_TYPE uint16_t +#define GPIO_PIDR_BASE ((uint32_t)(&CM_GPIO->PIDRA)) +#define GPIO_PODR_BASE ((uint32_t)(&CM_GPIO->PODRA)) +#define GPIO_POSR_BASE ((uint32_t)(&CM_GPIO->POSRA)) +#define GPIO_PORR_BASE ((uint32_t)(&CM_GPIO->PORRA)) +#define GPIO_POTR_BASE ((uint32_t)(&CM_GPIO->POTRA)) +#define GPIO_POER_BASE ((uint32_t)(&CM_GPIO->POERA)) +#define GPIO_PCR_BASE ((uint32_t)(&CM_GPIO->PCRA0)) +#define GPIO_PFSR_BASE ((uint32_t)(&CM_GPIO->PFSRA0)) + +#define PIDR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PIDR_BASE + GPIO_REG_OFFSET * (x))) +#define PODR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PODR_BASE + GPIO_REG_OFFSET * (x))) +#define POSR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POSR_BASE + GPIO_REG_OFFSET * (x))) +#define PORR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PORR_BASE + GPIO_REG_OFFSET * (x))) +#define POTR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POTR_BASE + GPIO_REG_OFFSET * (x))) +#define POER_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POER_BASE + GPIO_REG_OFFSET * (x))) +#define PCR_REG(x, y) (*(__IO uint16_t *)(GPIO_PCR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +#define PFSR_REG(x, y) (*(__IO uint16_t *)(GPIO_PFSR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +/** + * @} + */ + +/** + * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity + * @{ + */ +/*! Parameter validity check for pin state. */ +#define IS_GPIO_PIN_STATE(state) \ +( ((state) == PIN_STAT_RST) || \ + ((state) == PIN_STAT_SET)) + +/*! Parameter validity check for pin direction. */ +#define IS_GPIO_DIR(dir) \ +( ((dir) == PIN_DIR_IN) || \ + ((dir) == PIN_DIR_OUT)) + +/*! Parameter validity check for pin output type. */ +#define IS_GPIO_OUT_TYPE(type) \ +( ((type) == PIN_OUT_TYPE_CMOS) || \ + ((type) == PIN_OUT_TYPE_NMOS)) + +/*! Parameter validity check for pin driver capacity. */ +#define IS_GPIO_PIN_DRV(drv) \ +( ((drv) == PIN_LOW_DRV) || \ + ((drv) == PIN_MID_DRV) || \ + ((drv) == PIN_HIGH_DRV)) + +/*! Parameter validity check for pin attribute. */ +#define IS_GPIO_ATTR(attr) \ +( ((attr) == PIN_ATTR_DIGITAL) || \ + ((attr) == PIN_ATTR_ANALOG)) + +/*! Parameter validity check for pin latch function. */ +#define IS_GPIO_LATCH(latch) \ +( ((latch) == PIN_LATCH_OFF) || \ + ((latch) == PIN_LATCH_ON)) + +/*! Parameter validity check for internal pull-up resistor. */ +#define IS_GPIO_PIN_PU(pu) \ +( ((pu) == PIN_PU_OFF) || \ + ((pu) == PIN_PU_ON)) + +/*! Parameter validity check for pin state invert. */ +#define IS_GPIO_PIN_INVERT(invert) \ +( ((invert) == PIN_INVT_OFF) || \ + ((invert) == PIN_INVT_ON)) + +/*! Parameter validity check for pin input type. */ +#define IS_GPIO_IN_TYPE(type) \ +( ((type) == PIN_IN_TYPE_SMT) || \ + ((type) == PIN_IN_TYPE_CMOS)) + +/*! Parameter validity check for external interrupt function. */ +#define IS_GPIO_EXTINT(extint) \ +( ((extint) == PIN_EXTINT_OFF) || \ + ((extint) == PIN_EXTINT_ON)) + +/*! Parameter validity check for pin number. */ +#define IS_GPIO_PIN(pin) \ +( ((pin) != 0U) && \ + (((pin) & GPIO_PIN_ALL) != 0U)) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT(port) \ +( ((port) == GPIO_PORT_A) || \ + ((port) == GPIO_PORT_B) || \ + ((port) == GPIO_PORT_C) || \ + ((port) == GPIO_PORT_D) || \ + ((port) == GPIO_PORT_E) || \ + ((port) == GPIO_PORT_F) || \ + ((port) == GPIO_PORT_G) || \ + ((port) == GPIO_PORT_H) || \ + ((port) == GPIO_PORT_I)) + +/*! Parameter validity check for pin function. */ +#define IS_GPIO_FUNC(func) \ +( ((func) <= GPIO_FUNC_20) || \ + (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_63))) + +/*! Parameter validity check for debug pin definition. */ +#define IS_GPIO_DEBUG_PORT(port) \ +( ((port) != 0U) && \ + (((port) | GPIO_PIN_DEBUG) == GPIO_PIN_DEBUG)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_GPIO_READ_WAIT(wait) \ +( ((wait) == GPIO_RD_WAIT0) || \ + ((wait) == GPIO_RD_WAIT1) || \ + ((wait) == GPIO_RD_WAIT2) || \ + ((wait) == GPIO_RD_WAIT3) || \ + ((wait) == GPIO_RD_WAIT4) || \ + ((wait) == GPIO_RD_WAIT5) || \ + ((wait) == GPIO_RD_WAIT6) || \ + ((wait) == GPIO_RD_WAIT7)) + +/*! Parameter validity check for Hrpwmp pin definition. */ + +/* Check GPIO register lock status. */ +#define IS_GPIO_UNLOCK() (GPIO_PWPR_WE == (CM_GPIO->PWPR & GPIO_PWPR_WE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Variables GPIO Local Variables + * @{ + */ +static const stc_gpio_port_pin_tbl_t m_astcGpioPortPinTbl[] = { + {GPIO_PORT_A, GPIO_PIN_A_ALL}, + {GPIO_PORT_B, GPIO_PIN_B_ALL}, + {GPIO_PORT_C, GPIO_PIN_C_ALL}, + {GPIO_PORT_D, GPIO_PIN_D_ALL}, + {GPIO_PORT_E, GPIO_PIN_E_ALL}, + {GPIO_PORT_F, GPIO_PIN_F_ALL}, + {GPIO_PORT_G, GPIO_PIN_G_ALL}, + {GPIO_PORT_H, GPIO_PIN_H_ALL}, + {GPIO_PORT_I, GPIO_PIN_I_ALL}, + +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Functions GPIO Global Functions + * @{ + */ + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit) +{ + uint8_t u8PinPos; + uint16_t u16PCRVal; + uint16_t u16PCRMask; + int32_t i32Ret = LL_OK; + __IO uint16_t *PCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState)); + DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir)); + DDL_ASSERT(IS_GPIO_OUT_TYPE(pstcGpioInit->u16PinOutputType)); + DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv)); + DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch)); + DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp)); + DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert)); + DDL_ASSERT(IS_GPIO_EXTINT(pstcGpioInit->u16ExtInt)); + DDL_ASSERT(IS_GPIO_IN_TYPE(pstcGpioInit->u16PinInputType)); + DDL_ASSERT(IS_GPIO_ATTR(pstcGpioInit->u16PinAttr)); + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (1UL << u8PinPos)) != 0U) { + u16PCRVal = pstcGpioInit->u16PinState | pstcGpioInit->u16PinDir | pstcGpioInit->u16PinOutputType | \ + pstcGpioInit->u16PinDrv | pstcGpioInit->u16PullUp | pstcGpioInit->u16Invert | \ + pstcGpioInit->u16ExtInt | pstcGpioInit->u16Latch; + + u16PCRMask = GPIO_PCR_POUT | GPIO_PCR_POUTE | GPIO_PCR_NOD | \ + GPIO_PCR_DRV | GPIO_PCR_PUU | GPIO_PCR_INVE | \ + GPIO_PCR_INTE | GPIO_PCR_LTE ; + u16PCRVal |= pstcGpioInit->u16PinAttr; + u16PCRMask |= GPIO_PCR_DDIS; + + u16PCRVal |= pstcGpioInit->u16PinInputType; + u16PCRMask |= GPIO_PCR_CINSEL; + PCRx = &PCR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PCRx, u16PCRMask, u16PCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief De-init GPIO register to default value + * @param None + * @retval None + */ +void GPIO_DeInit(void) +{ + stc_gpio_init_t stcGpioInit; + uint8_t i; + DDL_ASSERT(IS_GPIO_UNLOCK()); + + (void)GPIO_StructInit(&stcGpioInit); + + for (i = 0U; i < ARRAY_SZ(m_astcGpioPortPinTbl); i++) { + (void)GPIO_Init(m_astcGpioPortPinTbl[i].u8Port, m_astcGpioPortPinTbl[i].u16PinMask, &stcGpioInit); + } + /* GPIO global register reset */ + WRITE_REG16(CM_GPIO->PSPCR, GPIO_PSPCR_RST_VALUE); + WRITE_REG16(CM_GPIO->PCCR, GPIO_PCCR_RST_VALUE); + + WRITE_REG16(CM_GPIO->PINAER, GPIO_PINAER_RST_VALUE); +} + +/** + * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset GPIO init structure parameters values */ + pstcGpioInit->u16PinState = PIN_STAT_RST; + pstcGpioInit->u16PinDir = PIN_DIR_IN; + pstcGpioInit->u16PinDrv = PIN_LOW_DRV; + pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL; + + pstcGpioInit->u16Latch = PIN_LATCH_OFF; + pstcGpioInit->u16PullUp = PIN_PU_OFF; + pstcGpioInit->u16Invert = PIN_INVT_OFF; + pstcGpioInit->u16ExtInt = PIN_EXTINT_OFF; + pstcGpioInit->u16PinOutputType = PIN_OUT_TYPE_CMOS; + pstcGpioInit->u16PinInputType = PIN_IN_TYPE_SMT; + } + return i32Ret; +} + +/** + * @brief GPIO debug port configure. Set debug pins to GPIO + * @param [in] u8DebugPort: @ref GPIO_DebugPin_Sel for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set to debug port (SWD/JTAG) + * @arg DISABLE: set to GPIO + * @retval None + */ +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } else { + CLR_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } +} + +/** + * @brief Set specified Port Pin function + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] u16Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_FUNC(u16Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + WRITE_REG16(*PFSRx, u16Func); + } + } +} + +/** + * @brief GPIO pin sub-function ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } else { + CLR_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } + } + } +} + +/** + * @brief Set the sub-function, it's a global configuration + * @param [in] u8Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetSubFunc(uint8_t u8Func) +{ + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func); +} + +/** + * @brief GPIO output ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO GPIO_REG_TYPE *POERx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + POERx = &POER_REG(u8Port); + if (ENABLE == enNewState) { + SET_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } else { + CLR_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } +} + +/** + * @brief GPIO read wait cycle configure. + * @param [in] u16ReadWait: @ref GPIO_ReadCycle_Sel for each product + * @retval None + */ +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait) +{ + DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait); +} + +/** + * @brief GPIO input MOS always ON configure. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set input MOS always ON + * @arg DISABLE: set input MOS turns on while read operation + * @retval None + */ +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } else { + CLR_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } +} + +/** + * @brief Read specified GPIO input data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin input value + */ +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PIDR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO input data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port input value + */ +uint16_t GPIO_ReadInputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PIDR_REG(u8Port)); +} + +/** + * @brief Read specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin output value + */ +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PODR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO output data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port output value + */ +uint16_t GPIO_ReadOutputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PODR_REG(u8Port)); +} + +/** + * @brief Set specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POSRx = &POSR_REG(u8Port); + SET_REG_BIT(*POSRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Reset specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *PORRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PORRx = &PORR_REG(u8Port); + SET_REG_BIT(*PORRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Write specified GPIO data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16PortVal: Pin output value + * @retval None + */ +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal) +{ + __IO GPIO_REG_TYPE *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + PODRx = &PODR_REG(u8Port); + WRITE_REG(*PODRx, (GPIO_REG_TYPE)u16PortVal); +} +// +/** + * @brief Toggle specified GPIO output data port pin + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POTRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POTRx = &POTR_REG(u8Port); + SET_REG_BIT(*POTRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c new file mode 100644 index 0000000000..17819d4086 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c @@ -0,0 +1,593 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.c + * @brief This file provides firmware functions to manage the HASH + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_hash.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HASH HASH + * @brief HASH Driver Library + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Macros HASH Local Macros + * @{ + */ + +/** + * @defgroup HASH_Miscellaneous_Macros HASH Miscellaneous Macros + * @{ + */ +#define HASH_GROUP_SIZE (64U) +#define HASH_GROUP_SIZE_WORD (HASH_GROUP_SIZE / 4U) +#define HASH_LAST_GROUP_SIZE_MAX (56U) +#define HASH_TIMEOUT (6000U) +#define HASH_MSG_DIGEST_SIZE_WORD (8U) + +#define HASH_KEY_LONG_SIZE (64U) +/** + * @} + */ + +/** + * @defgroup HASH_Action HASH Action + * @{ + */ +#define HASH_ACTION_START (HASH_CR_START) +#define HASH_ACTION_HMAC_END (HASH_CR_HMAC_END) +/** + * @} + */ + +/** + * @defgroup HASH_Check_Parameters_Validity HASH Check Parameters Validity + * @{ + */ +#define IS_HASH_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_HASH_MD(x) (((x) == HASH_MD_SHA256) || ((x) == HASH_MD_HMAC)) + +#define IS_HASH_KEY_SIZE_MD(x) (((x) == HASH_KEY_MD_LONG_SIZE) || ((x) == HASH_KEY_MD_SHORT_SIZE)) + +#define IS_HASH_INT(x) IS_HASH_BIT_MASK(x, HASH_INT_ALL) + +#define IS_HASH_FLAG(x) IS_HASH_BIT_MASK(x, HASH_FLAG_ALL) + +#define IS_HASH_FLAG_CLR(x) IS_HASH_BIT_MASK(x, HASH_FLAG_CLR_ALL) + +#define IS_HASH_MSG_GRP(x) \ +( ((x) == HASH_MSG_GRP_FIRST) || \ + ((x) == HASH_MSG_GRP_END) || \ + ((x) == HASH_MSG_GRP_ONLY_ONE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Functions HASH Local Functions + * @{ + */ + +/** + * @brief Writes the input buffer in data register. + * @param [in] pu8Data The buffer for source data + * @retval None + */ +static void HASH_WriteData(const uint8_t *pu8Data) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_HASH->DR15; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8Data); + + for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) { + regDR[i] = __REV(pu32Data[i]); + } +} + +/** + * @brief Memory copy. + * @param [in] pu8Dest Pointer to a destination address. + * @param [in] pu8Src Pointer to a source address. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemCopy(uint8_t *pu8Dest, const uint8_t *pu8Src, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Dest[i] = pu8Src[i]; + i++; + } +} + +/** + * @brief Memory set. + * @param [in] pu8Mem Pointer to an address. + * @param [in] u8Value Data value. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemSet(uint8_t *pu8Mem, uint8_t u8Value, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Mem[i] = u8Value; + i++; + } +} + +/** + * @brief Wait for the HASH to stop + * @param [in] u32Action HASH action. This parameter can be a value of @ref HASH_Action. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_Wait(uint32_t u32Action) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeCount = 0UL; + + /* Wait for the HASH to stop */ + while (READ_REG32_BIT(CM_HASH->CR, u32Action) != 0UL) { + if (u32TimeCount++ > HASH_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief HASH Filling data + * @param [in] pu8Data The source data buffer + * @param [in] u32DataSize Length of the input buffer in bytes + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_DoCalc(const uint8_t *pu8Data, uint32_t u32DataSize) +{ + uint8_t u8FillBuffer[HASH_GROUP_SIZE]; + uint32_t u32BitLenHigh; + uint32_t u32BitLenLow; + uint32_t u32Index = 0U; + uint8_t u8FirstGroup = 1U; + uint8_t u8HashEnd = 0U; + uint8_t u8DataEndMark = 0U; + uint8_t u8LastGroup = 0U; + int32_t i32Ret; + + u32BitLenHigh = (u32DataSize >> 29U) & 0x7U; + u32BitLenLow = (u32DataSize << 3U); + + /* Stop hash calculating. */ + i32Ret = HASH_Wait(HASH_ACTION_START); + + while ((i32Ret == LL_OK) && (u8HashEnd == 0U)) { + if (u32DataSize >= HASH_GROUP_SIZE) { + HASH_WriteData(&pu8Data[u32Index]); + u32DataSize -= HASH_GROUP_SIZE; + u32Index += HASH_GROUP_SIZE; + } else if (u32DataSize >= HASH_LAST_GROUP_SIZE_MAX) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + u8FillBuffer[u32DataSize] = 0x80U; + u8DataEndMark = 1U; + HASH_WriteData(u8FillBuffer); + u32DataSize = 0U; + } else { + u8HashEnd = 1U; + } + + if (u8HashEnd != 0U) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + if (u32DataSize > 0U) { + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + } + if (u8DataEndMark == 0U) { + u8FillBuffer[u32DataSize] = 0x80U; + } + u8FillBuffer[63U] = (uint8_t)(u32BitLenLow); + u8FillBuffer[62U] = (uint8_t)(u32BitLenLow >> 8U); + u8FillBuffer[61U] = (uint8_t)(u32BitLenLow >> 16U); + u8FillBuffer[60U] = (uint8_t)(u32BitLenLow >> 24U); + u8FillBuffer[59U] = (uint8_t)(u32BitLenHigh); + u8FillBuffer[58U] = (uint8_t)(u32BitLenHigh >> 8U); + u8FillBuffer[57U] = (uint8_t)(u32BitLenHigh >> 16U); + u8FillBuffer[56U] = (uint8_t)(u32BitLenHigh >> 24U); + HASH_WriteData(u8FillBuffer); + u8LastGroup = 1U; + } + + /* First group and last group check */ + /* check if first group */ + if (u8FirstGroup != 0U) { + u8FirstGroup = 0U; + /* Set first group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 1U); + } + /* check if last group */ + if (u8LastGroup != 0U) { + u8LastGroup = 0U; + /* Set last group. */ + WRITE_REG32(bCM_HASH->CR_b.KMSG_END, 1U); + } + + /* Start hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 1U); + i32Ret = HASH_Wait(HASH_ACTION_START); + } + /* Stop hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 0U); + + return i32Ret; +} + +/** + * @brief Read message digest. + * @param [out] pu8MsgDigest Buffer for message digest. + * @retval None + */ +static void HASH_ReadMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + __IO uint32_t *regHR = &CM_HASH->HR7; + uint32_t *pu32MsgDigest = (uint32_t *)((uint32_t)pu8MsgDigest); + + for (i = 0U; i < HASH_MSG_DIGEST_SIZE_WORD; i++) { + pu32MsgDigest[i] = __REV(regHR[i]); + } +} + +/** + * @} + */ + +/** + * @defgroup HASH_Global_Functions HASH Global Functions + * @{ + */ + +/** + * @brief HASH calculate. + * @param [in] pu8SrcData Pointer to the source data buffer. + * @param [in] u32SrcDataSize Length of the source data buffer in bytes. + * @param [out] pu8MsgDigest Buffer of the digest. The size must be 32 bytes. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: Parameter error. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && (pu8MsgDigest != NULL)) { + /* Set HASH mode */ + (void)HASH_SetMode(HASH_MD_SHA256); + i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize); + if (i32Ret == LL_OK) { + /* Get the message digest result */ + HASH_ReadMsgDigest(pu8MsgDigest); + } + } + + return i32Ret; +} + +/** + * @brief HMAC calculate. + * @param [in] pu8SrcData Pointer to the source data buffer. + * @param [in] u32SrcDataSize Length of the source data buffer in bytes. + * @param [in] pu8Key Buffer of the secret key. + * @param [in] u32KeySize Size of the input secret key in bytes. + * @param [out] pu8MsgDigest Buffer of the digest data buffer. The size must be 32 bytes. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: Parameter error. + * - LL_ERR_BUF_FULL: Data filling error. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_HMAC_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, + const uint8_t *pu8Key, uint32_t u32KeySize, + uint8_t *pu8MsgDigest) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint8_t u8FillBuffer[HASH_GROUP_SIZE] = {0U}; + + if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && \ + (pu8Key != NULL) && (u32KeySize != 0UL) && (pu8MsgDigest != NULL)) { + /* Set HMAC Mode */ + (void)HASH_SetMode(HASH_MD_HMAC); + if (u32KeySize > HASH_KEY_LONG_SIZE) { + /* Key size longer than 64 bytes. */ + WRITE_REG32(bCM_HASH->CR_b.LKEY, 1U); + /* Write the key to the data register */ + i32Ret = HASH_DoCalc(pu8Key, u32KeySize); + } else { + HASH_MemCopy(u8FillBuffer, pu8Key, u32KeySize); + /* Key size equal to or shorter than 64 bytes. */ + WRITE_REG32(bCM_HASH->CR_b.LKEY, 0U); + /* Write the key to the data register */ + HASH_WriteData(u8FillBuffer); + /* Only one group. */ + SET_REG32_BIT(CM_HASH->CR, HASH_MSG_GRP_ONLY_ONE); + /* Start hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 1U); + /* Wait for operation completion */ + i32Ret = HASH_Wait(HASH_ACTION_START); + } + /* Clear operation completion flag */ + WRITE_REG32(bCM_HASH->CR_b.CYC_END, 0U); + if (i32Ret == LL_OK) { + i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize); + /* Write the message to the data register */ + if (i32Ret == LL_OK) { + i32Ret = HASH_Wait(HASH_ACTION_HMAC_END); + if (i32Ret == LL_OK) { + /* Clear operation completion flag */ + CLR_REG32_BIT(CM_HASH->CR, HASH_CR_CYC_END | HASH_CR_HMAC_END); + /* Get the message digest result */ + HASH_ReadMsgDigest(pu8MsgDigest); + } + } + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable HASH interrupt. + * @param [in] u32HashInt Specifies the HASH interrupt to check. + * This parameter can be values of @ref HASH_Interrupt + * @arg HASH_INT_GRP: A set of data operations complete interrupt. + * @arg HASH_INT_ALL_CPLT: All data operations complete interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_HASH_INT(u32HashInt)); + + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + if (enNewState == ENABLE) { + SET_REG32_BIT(CM_HASH->CR, u32HashInt); + } else { + CLR_REG32_BIT(CM_HASH->CR, u32HashInt); + } + } + + return i32Ret; +} + +/** + * @brief Get the status of the specified HASH flag. + * @param [in] u32Flag HASH status flag. + * This parameter can be a value of @ref HASH_Status_Flag + * @arg HASH_FLAG_START: Operation in progress. + * @arg HASH_FLAG_BUSY: Operation in progress. + * @arg HASH_FLAG_CYC_END: key or message operation completed. + * @arg HASH_FLAG_HMAC_END: HMAC operation completed. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t HASH_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_HASH_FLAG(u32Flag)); + if (READ_REG32_BIT(CM_HASH->CR, u32Flag) != 0UL) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified HASH flag. + * @param [in] u32Flag HASH status flag. + * This parameter can be a value of @ref HASH_Status_Flag + * @arg HASH_FLAG_CYC_END: Clear the key or message operation completed flag + * @arg HASH_FLAG_HMAC_END: Clear the HMAC operation completed flag + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +int32_t HASH_ClearStatus(uint32_t u32Flag) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_HASH_FLAG_CLR(u32Flag)); + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + CLR_REG32_BIT(CM_HASH->CR, u32Flag); + } + + return i32Ret; +} + +/** + * @brief Specifies HASH mode: SHA256 mode or HMAC mode. + * @param [in] u32HashMode HASH mode selection. + * This parameter can be a value of @ref HASH_Mode + * @arg HASH_MD_SHA256: SHA256 mode + * @arg HASH_MD_HMAC: HMAC mode + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +int32_t HASH_SetMode(uint32_t u32HashMode) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_HASH_MD(u32HashMode)); + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + MODIFY_REG32(CM_HASH->CR, HASH_CR_MODE, u32HashMode); + } + + return i32Ret; +} + +/** + * @brief Set HASH key size mode. + * @param [in] u32SizeMode Key size mode. This parameter can be a value of @ref HASH_Key_Size_Mode + * @arg HASH_KEY_MD_LONG_SIZE: Key size > 64 Bytes + * @arg HASH_KEY_MD_SHORT_SIZE: Key size <= 64 Bytes + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +int32_t HASH_SetKeySizeMode(uint32_t u32SizeMode) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_HASH_KEY_SIZE_MD(u32SizeMode)); + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + MODIFY_REG32(CM_HASH->CR, HASH_CR_LKEY, u32SizeMode); + } + + return i32Ret; +} + +/** + * @brief Set message group. + * @param [in] u32MsgGroup First group or Last group of messages. + * This parameter can be a value of @ref HASH_Msg_Group + + * @arg HASH_MSG_GRP_FIRST: The first group of messages or keys + * @arg HASH_MSG_GRP_END: The last group of messages or keys + * @arg HASH_MSG_GRP_ONLY_ONE: Only one set of message or key + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +int32_t HASH_SetMsgGroup(uint32_t u32MsgGroup) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_HASH_MSG_GRP(u32MsgGroup)); + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + SET_REG32_BIT(CM_HASH->CR, u32MsgGroup); + } + + return i32Ret; +} + +/** + * @brief Start HASH. + * @param None + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +int32_t HASH_Start(void) +{ + int32_t i32Ret; + + /* Wait for the HASH to stop */ + i32Ret = HASH_Wait(HASH_ACTION_START); + if (i32Ret == LL_OK) { + /* Start hash calculating. */ + SET_REG32_BIT(CM_HASH->CR, HASH_CR_START); + } + + return i32Ret; +} + +/** + * @brief Provides the message digest result. + * @param [out] pu8MsgDigest Buffer for message digest. + * @retval None + */ +void HASH_GetMsgDigest(uint8_t *pu8MsgDigest) +{ + HASH_ReadMsgDigest(pu8MsgDigest); +} + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hrpwm.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hrpwm.c new file mode 100644 index 0000000000..9559bc49ec --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_hrpwm.c @@ -0,0 +1,381 @@ +/** + ******************************************************************************* + * @file hc32_ll_hrpwm.c + * @brief This file provides firmware functions to manage the High Resolution + * Pulse-Width Modulation(HRPWM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_hrpwm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HRPWM HRPWM + * @brief HRPWM Driver Library + * @{ + */ + +#if (LL_HRPWM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HRPWM_Local_Macros HRPWM Local Macros + * @{ + */ +/* About 1mS timeout */ +#define HRPWM_CAL_TIMEOUT (HCLK_VALUE/1000UL) +#define HRPWM_PCLK0_MIN (120000000UL) + +#define HRPWM_SYSCLKSRC_HRC (0x00U) +#define HRPWM_SYSCLKSRC_MRC (0x01U) +#define HRPWM_SYSCLKSRC_LRC (0x02U) +#define HRPWM_SYSCLKSRC_XTAL (0x03U) +#define HRPWM_SYSCLKSRC_XTAL32 (0x04U) +#define HRPWM_SYSCLKSRC_PLL (0x05U) + +#define HRPWM_PLLSRC_XTAL (0x00UL) +#define HRPWM_PLLSRC_HRC (0x01UL) + +/** + * @defgroup HRPWM_Check_Param_Validity HRPWM Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for HRPWM output channel */ +#define IS_VALID_HRPWM_CH(x) \ +( ((x) >= HRPWM_CH_MIN) && \ + ((x) <= HRPWM_CH_MAX)) + +/*! Parameter valid check for HRPWM caliration unit */ +#define IS_VALID_HRPWM_CAL_UNIT(x) \ +( (HRPWM_CAL_UNIT0 == (x)) || \ + (HRPWM_CAL_UNIT1 == (x))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup HRPWM_Global_Functions HRPWM Global Functions + * @{ + */ + +/** + * @brief Process for getting HRPWM Calibrate function code + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @param [out] pu8Code The pointer to get calibrate code. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Time out + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t *pu8Code) +{ + __IO uint32_t u32Timeout = HRPWM_CAL_TIMEOUT; + int32_t i32Ret = LL_OK; + + if (NULL != pu8Code) { + /* Enable calibrate */ + HRPWM_CalibrateCmd(u32Unit, ENABLE); + /* Wait calibrate finish flag */ + while (DISABLE == HRPWM_GetCalibrateState(u32Unit)) { + if (0UL == u32Timeout--) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + if (LL_OK == i32Ret) { + /* Get calibrate code */ + *pu8Code = HRPWM_GetCalibrateCode(u32Unit); + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + return i32Ret; +} + +/** + * @brief HRPWM Calibrate function enable or disable for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CALCRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CALCR0) + 4UL * u32Unit); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN); + } else { + CLR_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN); + } +} + +/** + * @brief HRPWM Calibrate function status get for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @retval An @ref en_functional_state_t enumeration value. + */ +en_functional_state_t HRPWM_GetCalibrateState(uint32_t u32Unit) +{ + en_functional_state_t enRet; + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + + CALCRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CALCR0) + 4UL * u32Unit); + + if (0UL != READ_REG32_BIT(*CALCRx, HRPWM_CALCR_ENDF)) { + enRet = ENABLE; + } else { + enRet = DISABLE; + } + return enRet; +} + +/** + * @brief HRPWM Calibrate code get for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @retval uint8_t: The calibration code. + */ +uint8_t HRPWM_GetCalibrateCode(uint32_t u32Unit) +{ + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + + CALCRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CALCR0) + 4UL * u32Unit); + + return ((uint8_t)(READ_REG32(*CALCRx))); +} + +/** + * @brief HRPWM function enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void HRPWM_ChCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CR1) + 4UL * (u32Ch - 1UL)); + if (ENABLE == enNewState) { + SET_REG32_BIT(*CRx, HRPWM_CR_EN); + } else { + CLR_REG32_BIT(*CRx, HRPWM_CR_EN); + } +} + +/** + * @brief HRPWM positive edge adjust enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void HRPWM_ChPositiveAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CR1) + 4UL * (u32Ch - 1UL)); + if (ENABLE == enNewState) { + SET_REG32_BIT(*CRx, HRPWM_CR_PE); + } else { + CLR_REG32_BIT(*CRx, HRPWM_CR_PE); + } +} + +/** + * @brief HRPWM negative edge adjust enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void HRPWM_ChNegativeAdjustCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CR1) + 4UL * (u32Ch - 1UL)); + if (ENABLE == enNewState) { + SET_REG32_BIT(*CRx, HRPWM_CR_NE); + } else { + CLR_REG32_BIT(*CRx, HRPWM_CR_NE); + } +} + +/** + * @brief HRPWM positive edge adjust delay counts configration for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] u8DelayNum Delay counts of minimum delay time. + * @retval None + */ +void HRPWM_ChPositiveAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + + CRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CR1) + 4UL * (u32Ch - 1UL)); + MODIFY_REG32(*CRx, HRPWM_CR_PSEL, ((uint32_t)u8DelayNum - 1UL) << HRPWM_CR_PSEL_POS); +} + +/** + * @brief HRPWM negative edge adjust delay counts configration for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] u8DelayNum Delay counts of minimum delay time. + * @retval None + */ +void HRPWM_ChNegativeAdjustConfig(uint32_t u32Ch, uint8_t u8DelayNum) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + + CRx = (__IO uint32_t *)(((uint32_t)&CM_HRPWM->CR1) + 4UL * (u32Ch - 1UL)); + MODIFY_REG32(*CRx, HRPWM_CR_NSEL, ((uint32_t)u8DelayNum - 1UL) << HRPWM_CR_NSEL_POS); +} + +/** + * @brief HRPWM Judge the condition of calibration function. + * @param None + * @retval An @ref en_functional_state_t enumeration value. + */ +en_functional_state_t HRPWM_CondConfirm(void) +{ + en_functional_state_t enRet = ENABLE; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32SysclkFreq; + uint32_t u32Pclk0Freq; + + switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + case HRPWM_SYSCLKSRC_HRC: + /* HRC is used to system clock */ + u32SysclkFreq = HRC_VALUE; + break; + case HRPWM_SYSCLKSRC_MRC: + /* MRC is used to system clock */ + u32SysclkFreq = MRC_VALUE; + break; + case HRPWM_SYSCLKSRC_LRC: + /* LRC is used to system clock */ + u32SysclkFreq = LRC_VALUE; + break; + case HRPWM_SYSCLKSRC_XTAL: + /* XTAL is used to system clock */ + u32SysclkFreq = XTAL_VALUE; + break; + case HRPWM_SYSCLKSRC_XTAL32: + /* XTAL32 is used to system clock */ + u32SysclkFreq = XTAL32_VALUE; + break; + case HRPWM_SYSCLKSRC_PLL: + /* PLLHP is used as system clock. */ + pllp = (uint32_t)((CM_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + plln = (uint32_t)((CM_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL); + pllm = (uint32_t)((CM_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL); + + /* fpll = ((pllin / pllm) * plln) / pllp */ + if (HRPWM_PLLSRC_XTAL == READ_REG32_BIT(CM_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC)) { + u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } else { + u32SysclkFreq = ((HRC_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } + break; + default: + u32SysclkFreq = HRC_VALUE; + enRet = DISABLE; + break; + } + + if (ENABLE == enRet) { + /* Get pclk0. */ + u32Pclk0Freq = u32SysclkFreq >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + + if (u32Pclk0Freq < HRPWM_PCLK0_MIN) { + enRet = DISABLE; + } + } + return enRet; +} + +/** + * @} + */ + +#endif /* LL_HRPWM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c new file mode 100644 index 0000000000..6accec7d40 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c @@ -0,0 +1,1200 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.c + * @brief This file provides firmware functions to manage the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2c.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2C I2C + * @brief I2C Driver Library + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2C_Local_Macros I2C Local Macros + * @{ + */ + +#define I2C_BAUDRATE_MAX (400000UL) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x3E) +#define I2C_7BIT_MAX (0x7FUL) +#define I2C_10BIT_MAX (0x3FFUL) + +/** + * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity + * @{ + */ + +#define IS_I2C_UNIT(x) (((x) == CM_I2C1) || ((x) == CM_I2C2) || ((x) == CM_I2C3) || ((x) == CM_I2C4) ||\ + ((x) == CM_I2C5) || ((x) == CM_I2C6)) + +#define IS_I2C_DIG_FILTER_CLK(x) ((x) <= I2C_DIG_FILTER_CLK_DIV4) + +#define IS_I2C_7BIT_ADDR(x) ((x) <= I2C_7BIT_MAX) +#define IS_I2C_10BIT_ADDR(x) ((x) <= I2C_10BIT_MAX) + +#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS)) + +#define IS_I2C_SPEED(x) \ +( ((x) != 0U) && \ + ((x) <= I2C_BAUDRATE_MAX)) + +#define IS_I2C_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_ALL) == I2C_FLAG_ALL)) + +#define IS_I2C_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_CLR_ALL) == I2C_FLAG_CLR_ALL)) + +#define IS_I2C_INT_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_INT_ALL) == I2C_INT_ALL)) + +#define IS_I2C_SMBUS_CONFIG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_SMBUS_MATCH_ALL) == I2C_SMBUS_MATCH_ALL)) + +#define IS_I2C_ADDR(mode, addr) \ +( ((I2C_ADDR_7BIT == (mode)) && ((addr) <= 0x7FU)) || \ + ((I2C_ADDR_10BIT == (mode)) && ((addr) <= 0x3FFU)) || \ + (I2C_ADDR_DISABLE == (mode))) + +#define IS_I2C_ADDR_NUM(x) \ +( ((x) == I2C_ADDR0) || \ + ((x) == I2C_ADDR1)) + +#define IS_I2C_CLK_DIV(x) \ +( (x) <= I2C_CLK_DIV128) + +#define IS_I2C_TRANS_DIR(x) \ +( ((x) == I2C_DIR_TX) || \ + ((x) == I2C_DIR_RX)) + +#define IS_I2C_ACK_CONFIG(x) \ +( ((x) == I2C_ACK) || \ + ((x) == I2C_NACK)) + +#define IS_I2C_FLAG_STD(x) \ +( ((x) == RESET) || \ + ((x) == SET)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Functions I2C Global Functions + * @{ + */ + +/** + * @brief Try to wait a status of specified flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag values: + * @param [in] enStatus Expected status @ref en_flag_status_t + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_TIMEOUT; + uint32_t u32RegStatusBit; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + DDL_ASSERT(IS_I2C_FLAG_STD(enStatus)); + + for (;;) { + u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flag)); + if (((enStatus == SET) && (u32Flag == u32RegStatusBit)) || ((enStatus == RESET) && (0UL == u32RegStatusBit))) { + i32Ret = LL_OK; + } + + if ((LL_OK == i32Ret) || (0UL == u32Timeout)) { + break; + } else { + u32Timeout--; + } + } + return i32Ret; +} + +/** + * @brief I2C generate start condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief I2C generate restart condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART); +} + +/** + * @brief I2C generate stop condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Set the baudrate for I2C peripheral. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret = LL_OK; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1UL << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if (0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) { + dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U; + } + + /* Judge if clock divider on*/ + if (I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) { + divsum = 3UL; + } + + if (I2cDivClk != 0UL) { + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F * (float32_t)divsum) + (2.0F * (float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } else { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if (WidthTotal <= SumTotal) { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + WRITE_REG32(I2Cx->CCR, \ + (pstcI2cInit->u32ClockDiv << I2C_CCR_FREQ_POS) | \ + (((uint32_t)WidthHL / 2U) << I2C_CCR_SLOWW_POS) | \ + (((uint32_t)WidthHL - (((uint32_t)WidthHL) / 2U)) << I2C_CCR_SHIGHW_POS)); + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + if ((NULL != pf32Error) && (LL_OK == i32Ret)) { + *pf32Error = fErr; + } + + return i32Ret; +} + +/** + * @brief De-initialize I2C unit + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_DeInit(CM_I2C_TypeDef *I2Cx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* RESET peripheral register and internal status*/ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Initialize I2C peripheral according to the structure + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + if (NULL == pstcI2cInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + + /* I2C baudrate config */ + i32Ret = I2C_BaudrateConfig(I2Cx, pstcI2cInit, pf32Error); + + /* Disable global broadcast address function */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_GCEN); + + /* Release software reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + /* Disable I2C peripheral */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + } + return i32Ret; +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config + * @param [in] u32Addr The slave address + * @retval None + */ +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32Addr)); + + if (I2C_ADDR_DISABLE == u32AddrMode) { + CLR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } else { + if (I2C_ADDR_10BIT == u32AddrMode) { + WRITE_REG32(*pu32SLRx, u32AddrMode + u32Addr); + } else { + WRITE_REG32(*pu32SLRx, u32AddrMode + (u32Addr << 1U)); + } + } +} + +/** + * @brief I2C function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS); +} + +/** + * @brief I2C fast ACK config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (ENABLE == enNewState) { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } else { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } +} + +/** + * @brief I2C bus wait function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } else { + CLR_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } +} + +/** + * @brief I2C SMBUS function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. @ref I2C_Smbus_Match_Config + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SMBUS_CONFIG(u32SmbusConfig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } else { + CLR_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } +} + +/** + * @brief I2C SMBUS function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, (uint32_t)enNewState << I2C_CR1_SMBUS_POS); +} + +/** + * @brief I2C digital filter function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32FilterClock Chose the digital filter clock, @ref I2C_Digital_Filter_Clock + * @retval None + */ +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_DIG_FILTER_CLK(u32FilterClock)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32FilterClock); +} + +/** + * @brief I2C digital filter command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS); +} + +/** + * @brief I2C analog filter function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS); +} + +/** + * @brief I2C general call command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_GCEN, (uint32_t)enNewState << I2C_CR1_GCEN_POS); +} + +/** + * @brief I2C flags status get + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + + return ((0UL != READ_REG32_BIT(I2Cx->SR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear I2C flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specifies the flag to clear, This parameter + * can be any combination of the following values + * @arg I2C_FLAG_START : Start flag clear + * @arg I2C_FLAG_MATCH_ADDR0 : Address 0 detected flag clear + * @arg I2C_FLAG_MATCH_ADDR1 : Address 1 detected flag clear + * @arg I2C_FLAG_TX_CPLT : Transfer end flag clear + * @arg I2C_FLAG_STOP : Stop flag clear + * @arg I2C_FLAG_RX_FULL : Receive buffer full flag clear + * @arg I2C_FLAG_TX_EMPTY : Transfer buffer empty flag clear + * @arg I2C_FLAG_ARBITRATE_FAIL : Arbitration fails flag clear + * @arg I2C_FLAG_NACKF : Nack detected flag clear + * @arg I2C_FLAG_GENERAL_CALL : General call address detected flag clear + * @arg I2C_FLAG_SMBUS_DEFAULT_MATCH: Smbus default address detected flag clear + * @arg I2C_FLAG_SMBUS_HOST_MATCH : Smbus host address detected flag clear + * @arg I2C_FLAG_SMBUS_ALARM_MATCH : Smbus alarm address detected flag clear + * @retval None + */ +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_CLR_FLAG(u32Flag)); + + WRITE_REG32(I2Cx->CLR, u32Flag); +} + +/** + * @brief I2C software reset function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS); +} + +/** + * @brief I2C interrupt command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32IntType Specifies the I2C interrupts @ref I2C_Int_Flag + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_INT_FLAG(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR2, u32IntType); + } else { + CLR_REG32_BIT(I2Cx->CR2, u32IntType); + } +} + +/** + * @brief I2C send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u8Data The data to be send + * @retval None + */ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + WRITE_REG8(I2Cx->DTR, u8Data); +} + +/** + * @brief I2C read data from register + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint8_t The value of the received data + */ +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + return READ_REG8(I2Cx->DRR); +} + +/** + * @brief I2C ACK status configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AckConfig I2C ACK configurate. @ref I2C_Ack_Config + * @retval None + */ +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ACK_CONFIG(u32AckConfig)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig); +} + +/** + * @brief I2C SCL high level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutH Clock timeout period for high level + * @retval None + */ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTHIGH, (uint32_t)u16TimeoutH << I2C_SLTR_TOUTHIGH_POS); +} + +/** + * @brief I2C SCL low level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutL Clock timeout period for low level + * @retval None + */ +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTLOW, u16TimeoutL); +} + +/** + * @brief Enable or disable I2C SCL high level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL low level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } +} + +/** + * @brief I2Cx start + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* generate start signal */ + I2C_GenerateStart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief I2Cx restart + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + /* Send restart condition */ + I2C_GenerateRestart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief I2Cx send address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction, @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_7BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Send I2C address */ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr << 1U) | u8Dir); + + if (I2C_DIR_TX == u8Dir) { + /* If in master transfer process, Need wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + } else { + /* If in master recevie process, wait I2C_FLAG_TRA changed to recevie */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + } + + if (i32Ret == LL_OK) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send 10 bit address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_10BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_TX); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive ACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == RESET) { + /* Write SLA(bit7:0)*/ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr & 0xFFU)); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } else { + i32Ret = LL_ERR; + } + } + } + + if ((u8Dir == I2C_DIR_RX) && (LL_OK == i32Ret)) { + /* Restart */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + I2C_GenerateRestart(I2Cx); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_START, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_RX); + /* If in master receive process, Need wait TRA flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] au8TxData The data array to be sent + * @param [in] u32Size Number of data in array pau8TxData + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count = 0UL; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8TxData != NULL) { + while ((u32Count != u32Size) && (i32Ret == LL_OK)) { + /* Wait tx buffer empty */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (i32Ret == LL_OK) { + /* Send one byte data */ + I2C_WriteData(I2Cx, au8TxData[u32Count]); + + /* Wait transfer end*/ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + /* If receive NACK*/ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + break; + } + u32Count++; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data and stop(for master) + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* Stop before read last data */ + if (i == (u32Size - 1UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + I2C_GenerateStop(I2Cx); + } + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + + if (i == (u32Size - 1UL)) { + /* Wait stop flag after DRR read */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + } + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx stop + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear stop flag */ + while ((SET == I2C_GetStatus(I2Cx, I2C_FLAG_STOP)) && (u32Timeout > 0UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + u32Timeout--; + } + I2C_GenerateStop(I2Cx); + /* Wait stop flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief Initialize structure stc_i2c_init_t variable with default value. + * @param [out] pstcI2cInit Pointer to a stc_i2c_init_t structure variable which will be initialized. + * @ref stc_i2c_init_t. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit) +{ + int32_t i32Ret = LL_OK; + if (pstcI2cInit == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2cInit->u32Baudrate = 50000UL; + pstcI2cInit->u32SclTime = 0UL; + pstcI2cInit->u32ClockDiv = I2C_CLK_DIV1; + } + + return i32Ret; +} + +/** +* @} +*/ + +#endif /* LL_I2C_ENABLE */ + +/** +* @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c new file mode 100644 index 0000000000..3e95136c8d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c @@ -0,0 +1,1027 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.c + * @brief This file provides firmware functions to manage the Inter IC Sound Bus + * (I2S). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2s.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2S I2S + * @brief Inter IC Sound Bus Driver Library + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Local_Macros I2S Local Macros + * @{ + */ +/* CMU registers define */ +#define I2S_CLK_SRC_PCLK (0x00U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLQ (0x08U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLR (0x09U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXP (0x0AU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXQ (0x0BU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXR (0x0CU << CMU_I2SCKSEL_I2S1CKSEL_POS) + +#define I2S_CMU_PLLCFGR PLLHCFGR +#define I2S_CMU_PLLCFGR_PLLSRC CMU_PLLHCFGR_PLLSRC + +#define I2S_CMU_PLLXCFGR PLLACFGR + +#define I2S_CMU_SCFGR SCFGR +#define I2S_CMU_SCFGR_PCLK CMU_SCFGR_PCLK1S +#define I2S_CMU_SCFGR_PCLK_POS CMU_SCFGR_PCLK1S_POS + +#define I2S_CMU_PLLCFGR_PLLM CMU_PLLHCFGR_PLLHM +#define I2S_CMU_PLLCFGR_PLLM_POS CMU_PLLHCFGR_PLLHM_POS +#define I2S_CMU_PLLCFGR_PLLN CMU_PLLHCFGR_PLLHN +#define I2S_CMU_PLLCFGR_PLLN_POS CMU_PLLHCFGR_PLLHN_POS +#define I2S_CMU_PLLCFGR_PLLP CMU_PLLHCFGR_PLLHP +#define I2S_CMU_PLLCFGR_PLLP_POS CMU_PLLHCFGR_PLLHP_POS +#define I2S_CMU_PLLCFGR_PLLQ CMU_PLLHCFGR_PLLHQ +#define I2S_CMU_PLLCFGR_PLLQ_POS CMU_PLLHCFGR_PLLHQ_POS +#define I2S_CMU_PLLCFGR_PLLR CMU_PLLHCFGR_PLLHR +#define I2S_CMU_PLLCFGR_PLLR_POS CMU_PLLHCFGR_PLLHR_POS + +#define I2S_CMU_PLLCFGR_PLLXM CMU_PLLACFGR_PLLAM +#define I2S_CMU_PLLCFGR_PLLXM_POS CMU_PLLACFGR_PLLAM_POS +#define I2S_CMU_PLLCFGR_PLLXN CMU_PLLACFGR_PLLAN +#define I2S_CMU_PLLCFGR_PLLXN_POS CMU_PLLACFGR_PLLAN_POS +#define I2S_CMU_PLLCFGR_PLLXP CMU_PLLACFGR_PLLAP +#define I2S_CMU_PLLCFGR_PLLXP_POS CMU_PLLACFGR_PLLAP_POS +#define I2S_CMU_PLLCFGR_PLLXQ CMU_PLLACFGR_PLLAQ +#define I2S_CMU_PLLCFGR_PLLXQ_POS CMU_PLLACFGR_PLLAQ_POS +#define I2S_CMU_PLLCFGR_PLLXR CMU_PLLACFGR_PLLAR +#define I2S_CMU_PLLCFGR_PLLXR_POS CMU_PLLACFGR_PLLAR_POS + +/* I2S CTRL register Mask */ +#define I2S_CTRL_CLR_MASK (I2S_CTRL_WMS | I2S_CTRL_ODD | I2S_CTRL_MCKOE | \ + I2S_CTRL_TXBIRQWL | I2S_CTRL_RXBIRQWL | I2S_CTRL_I2SPLLSEL | \ + I2S_CTRL_SDOE | I2S_CTRL_LRCKOE | I2S_CTRL_CKOE | \ + I2S_CTRL_DUPLEX | I2S_CTRL_CLKSEL) + +/** + * @defgroup I2S_Check_Parameters_Validity I2S Check Parameters Validity + * @{ + */ +#define IS_I2S_UNIT(x) \ +( ((x) == CM_I2S1) || \ + ((x) == CM_I2S2) || \ + ((x) == CM_I2S3) || \ + ((x) == CM_I2S4)) + +#define IS_I2S_CLK_SRC(x) \ +( ((x) == I2S_CLK_SRC_PLL) || \ + ((x) == I2S_CLK_SRC_EXT)) + +#define IS_I2S_MD(x) \ +( ((x) == I2S_MD_MASTER) || \ + ((x) == I2S_MD_SLAVE)) + +#define IS_I2S_PROTOCOL(x) \ +( ((x) == I2S_PROTOCOL_PHILLIPS) || \ + ((x) == I2S_PROTOCOL_MSB) || \ + ((x) == I2S_PROTOCOL_LSB) || \ + ((x) == I2S_PROTOCOL_PCM_SHORT) || \ + ((x) == I2S_PROTOCOL_PCM_LONG)) + +#define IS_I2S_TRANS_MD(x) \ +( ((x) == I2S_TRANS_MD_HALF_DUPLEX_RX) || \ + ((x) == I2S_TRANS_MD_HALF_DUPLEX_TX) || \ + ((x) == I2S_TRANS_MD_FULL_DUPLEX)) + +#define IS_I2S_AUDIO_FREQ(x) \ +( ((x) == I2S_AUDIO_FREQ_DEFAULT) || \ + (((x) >= I2S_AUDIO_FREQ_8K) && ((x) <= I2S_AUDIO_FREQ_192K))) + +#define IS_I2S_CH_LEN(x) \ +( ((x) == I2S_CH_LEN_16BIT) || \ + ((x) == I2S_CH_LEN_32BIT)) + +#define IS_I2S_DATA_LEN(x) \ +( ((x) == I2S_DATA_LEN_16BIT) || \ + ((x) == I2S_DATA_LEN_24BIT) || \ + ((x) == I2S_DATA_LEN_32BIT)) + +#define IS_I2S_MCK_OUTPUT(x) \ +( ((x) == I2S_MCK_OUTPUT_DISABLE) || \ + ((x) == I2S_MCK_OUTPUT_ENABLE)) + +#define IS_I2S_TRANS_LVL(x) \ +( ((x) == I2S_TRANS_LVL0) || \ + ((x) == I2S_TRANS_LVL1) || \ + ((x) == I2S_TRANS_LVL2) || \ + ((x) == I2S_TRANS_LVL3) || \ + ((x) == I2S_TRANS_LVL4)) + +#define IS_I2S_RECEIVE_LVL(x) \ +( ((x) == I2S_RECEIVE_LVL0) || \ + ((x) == I2S_RECEIVE_LVL1) || \ + ((x) == I2S_RECEIVE_LVL2) || \ + ((x) == I2S_RECEIVE_LVL3) || \ + ((x) == I2S_RECEIVE_LVL4)) + +#define IS_I2S_FUNC(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FUNC_ALL) == I2S_FUNC_ALL)) + +#define IS_I2S_RST_TYPE(x) \ +( ((x) != 0U) && \ + (((x) | I2S_RST_TYPE_ALL) == I2S_RST_TYPE_ALL)) + +#define IS_I2S_INT(x) \ +( ((x) != 0U) && \ + (((x) | I2S_INT_ALL) == I2S_INT_ALL)) + +#define IS_I2S_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_ALL) == I2S_FLAG_ALL)) + +#define IS_I2S_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_CLR_ALL) == I2S_FLAG_CLR_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Functions I2S Global Functions + * @{ + */ + +/** + * @brief Get I2S clock frequency. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t The I2S clock frequency + */ +static uint32_t I2S_GetClockFreq(const CM_I2S_TypeDef *I2Sx) +{ + uint32_t u32ClockShift; + uint16_t u16ClockSrc; + uint32_t u32ClockFreq; + uint32_t u32PllP; + uint32_t u32PllQ; + uint32_t u32PllR; + uint32_t u32PllN; + uint32_t u32PllM; + uint32_t u32PllIn; + uint32_t u32Temp; + + /* Get the offset of the I2S clock source in CMU_I2SCKSEL */ + if (CM_I2S1 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S1CKSEL_POS; + } else if (CM_I2S2 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S2CKSEL_POS; + } else if (CM_I2S3 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S3CKSEL_POS; + } else if (CM_I2S4 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S4CKSEL_POS; + } else { + u32ClockShift = 0UL; + } + + u16ClockSrc = (READ_REG16(CM_CMU->I2SCKSEL) >> u32ClockShift) & CMU_I2SCKSEL_I2S1CKSEL; + if (0UL != READ_REG32_BIT(CM_CMU->I2S_CMU_PLLCFGR, I2S_CMU_PLLCFGR_PLLSRC)) { + u32PllIn = HRC_VALUE; + } else { + u32PllIn = XTAL_VALUE; + } + /* Calculate the clock frequency */ + switch (u16ClockSrc) { + case I2S_CLK_SRC_PCLK: + u32ClockFreq = SystemCoreClock >> ((READ_REG32_BIT(CM_CMU->I2S_CMU_SCFGR, + I2S_CMU_SCFGR_PCLK) >> I2S_CMU_SCFGR_PCLK_POS)); + break; + case I2S_CLK_SRC_PLLQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLQ) >> I2S_CMU_PLLCFGR_PLLQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLR) >> I2S_CMU_PLLCFGR_PLLR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + case I2S_CLK_SRC_PLLXP: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllP = (u32Temp & I2S_CMU_PLLCFGR_PLLXP) >> I2S_CMU_PLLCFGR_PLLXP_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case I2S_CLK_SRC_PLLXQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLXQ) >> I2S_CMU_PLLCFGR_PLLXQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLXR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLXR) >> I2S_CMU_PLLCFGR_PLLXR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + default: + u32ClockFreq = 0UL; + break; + } + + return u32ClockFreq; +} + +/** + * @brief Wait for the flag status of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @param [in] enStatus The flag status + * This parameter can be one of the following values: + * @arg SET: Wait for the flag to set + * @arg RESET: Wait for the flag to reset + * @param [in] u32Timeout Wait the flag timeout(ms) + * @retval int32_t: + * - LL_OK: Wait status success + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t I2S_WaitStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag, + en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Waiting for the flag status to change to the enStatus */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (enStatus != I2S_GetStatus(I2Sx, u32Flag)) { + if (u32Count == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief De-Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval None + */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + /* Reset all registers of I2S */ + WRITE_REG32(I2Sx->CTRL, 0x00004400UL); + WRITE_REG32(I2Sx->ER, 0x00000003UL); + WRITE_REG32(I2Sx->CFGR, 0x00000000UL); + WRITE_REG32(I2Sx->PR, 0x00000002UL); + SET_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); + CLR_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); +} + +/** + * @brief Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR: Set frequency failed + */ +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLK_SRC(pstcI2sInit->u32ClockSrc)); + DDL_ASSERT(IS_I2S_MD(pstcI2sInit->u32Mode)); + DDL_ASSERT(IS_I2S_PROTOCOL(pstcI2sInit->u32Protocol)); + DDL_ASSERT(IS_I2S_TRANS_MD(pstcI2sInit->u32TransMode)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sInit->u32AudioFreq)); + DDL_ASSERT(IS_I2S_CH_LEN(pstcI2sInit->u32ChWidth)); + DDL_ASSERT(IS_I2S_DATA_LEN(pstcI2sInit->u32DataWidth)); + DDL_ASSERT(IS_I2S_MCK_OUTPUT(pstcI2sInit->u32MCKOutput)); + DDL_ASSERT(IS_I2S_TRANS_LVL(pstcI2sInit->u32TransFIFOLevel)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(pstcI2sInit->u32ReceiveFIFOLevel)); + + if (I2S_AUDIO_FREQ_DEFAULT != pstcI2sInit->u32AudioFreq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == pstcI2sInit->u32ClockSrc) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == pstcI2sInit->u32MCKOutput) { + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + /* Set the default values */ + u32I2sOdd = 0U; + u32I2sDiv = 2U; + i32Ret = LL_ERR; + } + u32Temp = pstcI2sInit->u32ClockSrc | pstcI2sInit->u32Mode | + pstcI2sInit->u32Protocol | pstcI2sInit->u32TransMode | + pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth | + pstcI2sInit->u32MCKOutput | pstcI2sInit->u32TransFIFOLevel | + pstcI2sInit->u32ReceiveFIFOLevel | (u32I2sOdd << I2S_CTRL_ODD_POS); + if (I2S_MD_MASTER == pstcI2sInit->u32Mode) { + u32Temp |= (I2S_CTRL_CKOE | I2S_CTRL_LRCKOE); + } + /* Set I2S_CFGR register */ + WRITE_REG32(I2Sx->CFGR, (pstcI2sInit->u32Protocol | pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth)); + /* set I2S_PR register */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + /* Set I2S_CTRL register */ + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_CLR_MASK, u32Temp); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_i2s_init_t member with default value. + * @param [out] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: stc_i2s_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2sInit->u32ClockSrc = I2S_CLK_SRC_PLL; + pstcI2sInit->u32Mode = I2S_MD_MASTER; + pstcI2sInit->u32Protocol = I2S_PROTOCOL_PHILLIPS; + pstcI2sInit->u32TransMode = I2S_TRANS_MD_HALF_DUPLEX_RX; + pstcI2sInit->u32AudioFreq = I2S_AUDIO_FREQ_DEFAULT; + pstcI2sInit->u32ChWidth = I2S_CH_LEN_16BIT; + pstcI2sInit->u32DataWidth = I2S_DATA_LEN_16BIT; + pstcI2sInit->u32MCKOutput = I2S_MCK_OUTPUT_DISABLE; + pstcI2sInit->u32TransFIFOLevel = I2S_TRANS_LVL2; + pstcI2sInit->u32ReceiveFIFOLevel = I2S_RECEIVE_LVL2; + } + + return i32Ret; +} + +/** + * @brief Software reset of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Type Software reset type + * This parameter can be one or any combination of the following values: + * @arg @ref I2S_Reset_Type + * @retval None + */ +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RST_TYPE(u32Type)); + + SET_REG32_BIT(I2Sx->CTRL, u32Type); + CLR_REG32_BIT(I2Sx->CTRL, u32Type); +} + +/** + * @brief Set the transfer mode for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Mode Transfer mode + * This parameter can be one of the following values: + * @arg I2S_TRANS_MD_HALF_DUPLEX_RX: Receive only and half duplex mode + * @arg I2S_TRANS_MD_HALF_DUPLEX_TX: Send only and half duplex mode + * @arg I2S_TRANS_MD_FULL_DUPLEX: Full duplex mode + * @retval None + */ +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_MD(u32Mode)); + + MODIFY_REG32(I2Sx->CTRL, (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE), u32Mode); +} + +/** + * @brief Set the transfer FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Transfer FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Trans_Level + * @retval None + */ +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_TXBIRQWL, u32Level); +} + +/** + * @brief Set the receive FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Receive FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Receive_Level + * @retval None + */ +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_RXBIRQWL, u32Level); +} + +/** + * @brief Set the communication protocol of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Protocol Communication protocol + * This parameter can be one of the following values: + * @arg I2S_PROTOCOL_PHILLIPS: Phillips protocol + * @arg I2S_PROTOCOL_MSB: MSB justified protocol + * @arg I2S_PROTOCOL_LSB: LSB justified protocol + * @arg I2S_PROTOCOL_PCM_SHORT: PCM short-frame protocol + * @arg I2S_PROTOCOL_PCM_LONG: PCM long-frame protocol + * @retval None + */ +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_PROTOCOL(u32Protocol)); + + MODIFY_REG32(I2Sx->CFGR, (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC), u32Protocol); +} + +/** + * @brief Set the audio frequency for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Freq Audio frequency + * This parameter can be 'I2S_AUDIO_FREQ_DEFAULT' or between + * 'I2S_AUDIO_FREQ_8K' and 'I2S_AUDIO_FREQ_192K': + * @arg I2S_AUDIO_FREQ_192K: FS = 192000Hz + * @arg I2S_AUDIO_FREQ_8K: FS = 8000Hz + * @arg I2S_AUDIO_FREQ_DEFAULT + * @retval int32_t: + * - LL_OK: Set success + * - LL_ERR: Set frequency failed + */ +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(u32Freq)); + + if (I2S_AUDIO_FREQ_DEFAULT != u32Freq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_CLKSEL)) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE)) { + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / u32Freq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / u32Freq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / u32Freq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + i32Ret = LL_ERR; + } else { + /* Set clock division */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_ODD, (u32I2sOdd << I2S_CTRL_ODD_POS)); + } + + return i32Ret; +} + +/** + * @brief Enable or disable MCK clock output. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } else { + CLR_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } +} + +/** + * @brief Enable or disable the function of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Func I2S function + * This parameter can be one or any combination of the following values: + * @arg I2S_FUNC_TX: Transfer function + * @arg I2S_FUNC_RX: Receive function + * @arg I2S_FUNC_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FUNC(u32Func)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32Func); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32Func); + } +} + +/** + * @brief I2S send data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Data Send data + * @retval None + */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + WRITE_REG32(I2Sx->TXBUF, u32Data); +} + +/** + * @brief I2S receive data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t Receive data + */ +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + return READ_REG32(I2Sx->RXBUF); +} + +/** + * @brief I2S transmit data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Transmit data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + + if ((NULL == pvTxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + DDL_ASSERT(IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0])); + } else { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0])); + } + + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[i]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[i]); + } + } + } + + return i32Ret; +} + +/** + * @brief I2S receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + uint32_t u32Temp; + + if ((NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[i] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[i] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[i] = u32Temp; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief I2S transmit and receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret; + uint32_t u32TxCnt = 0U; + uint32_t u32RxCnt = 0U; + uint32_t u32DataWidth; + uint32_t u32Temp; + uint8_t u8BreakFlag = 0U; + + if ((NULL == pvTxBuf) || (NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK == i32Ret) { + /* Preload data */ + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + + for (;;) { + /* Transmit data */ + if (u32TxCnt < u32Len) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + } + } + /* Receive data */ + if ((1U != u8BreakFlag) && (u32RxCnt < u32Len)) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp; + } + u32RxCnt++; + } + } + + /* Complete the transmission */ + if ((1U == u8BreakFlag) || ((u32Len == u32TxCnt) && (u32Len == u32RxCnt))) { + break; + } + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable specified I2S interrupt. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32IntType Interrupt type + * This parameter can be one or any combination of the following values: + * @arg I2S_INT_TX: Transfer interrupt + * @arg I2S_INT_RX: Receive interrupt + * @arg I2S_INT_ERR: Communication error interrupt + * @arg I2S_INT_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32IntType); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32IntType); + } +} + +/** + * @brief Get I2S flag status. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint32_t u32NormalFlag; + uint32_t u32ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FLAG(u32Flag)); + + u32NormalFlag = u32Flag & 0xFFFFUL; + u32ErrorFlag = u32Flag >> 16U; + if (0UL != u32NormalFlag) { + if (0UL != (READ_REG32_BIT(I2Sx->SR, u32NormalFlag))) { + enFlagSta = SET; + } + } + if ((RESET == enFlagSta) && (0UL != u32ErrorFlag)) { + if (0UL != (READ_REG32_BIT(I2Sx->ER, u32ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear I2S flag. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_CLR_ALL: All of the above + * @retval None + */ +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(I2Sx->ER, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c new file mode 100644 index 0000000000..32b40a2ab5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.c + * @brief This file provides firmware functions to manage the Initial + * Configuration(ICG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_icg.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ICG ICG + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Local_Macros ICG Local Macros + * @{ + */ + +/** + * @brief ICG Start Address + */ +#define ICG_START_ADDR 0x400 +#define ICG_START_ADDR_AC6 ".ARM.__at_0x400" + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief ICG parameters configuration + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +const uint32_t u32ICGValue[] __attribute__((section(ICG_START_ADDR_AC6))) = +#elif defined (__GNUC__) && !defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((at(ICG_START_ADDR))) = +#elif defined (__ICCARM__) +#pragma location = ICG_START_ADDR +__root static const uint32_t u32ICGValue[] = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~1 */ + ICG_REG_CFG0_CONST, + ICG_REG_CFG1_CONST, + /* ICG 2~3 */ + ICG_REG_CFG2_CONST, + ICG_REG_CFG3_CONST, + /* Reserved 0~3 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 4~7 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 8~11 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 12~15 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 16~19 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c new file mode 100644 index 0000000000..f9a27f47d5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c @@ -0,0 +1,1821 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.c + * @brief This file provides firmware functions to manage the Interrupt Controller + * (INTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_interrupts.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_INTERRUPTS INTERRUPTS + * @brief INTC Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Macros INTC Local Macros + * @{ + */ +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (128U) +#define IRQn_MIN (INT000_IRQn) +#define IRQn_MAX (INT127_IRQn) +#define IRQn_OFFSET (0U) +#define EXTINT_CH_NUM_MAX (16U) +#define EIRQCFR_REG (CM_INTC->EIRQCFR) +#define NMICFR_REG (CM_INTC->NMICFR) +#define INTSEL_REG (uint32_t)(&CM_INTC->SEL0) +#define INTSEL_RST_VALUE (0x1FFUL) +#define IRQ_GRP_MOD (32UL) +#define IRQ_GRP_NUM (6UL) +#define IRQ_GRP_LOW (32UL) +#define IRQ_GRP_HIGH (37UL) +#define IRQ_GRP_BASE (32UL) + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_ALL) == INTC_WUPEN_ALL)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVT(event) \ +( ((event) != 0x00UL) && \ + (((event) | INTC_EVT_ALL) == INTC_EVT_ALL)) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) \ +( ((it) != 0x00UL) && \ + (((it) | INTC_INT_ALL) == INTC_INT_ALL)) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) \ +( ((swi) != 0x00UL) && \ + (((swi) | SWINT_ALL) == SWINT_ALL)) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_ALL) == NMI_SRC_ALL)) + +/*! Parameter validity check for EXTINT filter A function. */ +#define IS_EXTINT_FAE(fae) \ +( ((fae) == EXTINT_FILTER_OFF) || \ + ((fae) == EXTINT_FILTER_ON)) + +/*! Parameter validity check for EXTINT filter A clock division. */ +#define IS_EXTINT_FACLK(faclk) \ +( ((faclk) == EXTINT_FCLK_DIV1) || \ + ((faclk) == EXTINT_FCLK_DIV8) || \ + ((faclk) == EXTINT_FCLK_DIV32) || \ + ((faclk) == EXTINT_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT filter B function. */ +#define IS_NMI_EXTINT_FBE(fbe) \ +( ((fbe) == NMI_EXTINT_FILTER_B_OFF) || \ + ((fbe) == NMI_EXTINT_FILTER_B_ON)) + +/*! Parameter validity check for EXTINT filter B time. */ +#define IS_NMI_EXTINT_FBTIME(fbtime) \ +( ((fbtime) == NMI_EXTINT_FCLK_B_500NS) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_1US) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_2US) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_4US)) + +/*! Parameter validity check for EXTINT trigger edge. */ +#define IS_EXTINT_TRIG(trigger) \ +( ((trigger) == EXTINT_TRIG_LOW) || \ + ((trigger) == EXTINT_TRIG_RISING) || \ + ((trigger) == EXTINT_TRIG_FALLING) || \ + ((trigger) == EXTINT_TRIG_BOTH)) + +/*! Parameter validity check for EXTINT channel. */ +#define IS_EXTINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXTINT_CH_ALL) == EXTINT_CH_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @arg pfnCallback: Callback function + * @retval int32_t: + * - LL_OK: IRQ register successfully + * - LL_ERR_INVD_PARAM: IRQ No. and Peripheral Int source are not match; NULL pointer. + * - LL_ERR_UNINIT: Specified IRQ entry was signed before. + */ +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcIrqSignConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(pstcIrqSignConfig->enIntSrc <= INT_SRC_MAX); + /* IRQ032~127 whether out of range */ + if ((((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_LOW) > \ + (uint32_t)pstcIrqSignConfig->enIRQn) || \ + ((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_HIGH) < \ + (uint32_t)pstcIrqSignConfig->enIRQn)) && \ + ((uint32_t)pstcIrqSignConfig->enIRQn >= IRQ_GRP_BASE)) { + i32Ret = LL_ERR_INVD_PARAM; + } + + else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4U * (uint32_t)(pstcIrqSignConfig->enIRQn))); + /* for MISRAC2004-12.4 */ + if (INTSEL_RST_VALUE == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + //WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else { + i32Ret = LL_ERR_UNINIT; + } + } + } + return i32Ret; +} + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @retval int32_t: + * - LL_OK: IRQ sign out successfully + * - LL_ERR_INVD_PARAM: IRQ No. is out of range + */ +int32_t INTC_IrqSignOut(IRQn_Type enIRQn) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + if ((enIRQn < IRQn_MIN) || (enIRQn > IRQn_MAX)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4UL * (uint32_t)enIRQn)); + WRITE_REG32(*INTC_SELx, INTSEL_RST_VALUE); + m_apfnIrqHandler[(uint8_t)enIRQn - IRQn_OFFSET] = NULL; + } + return i32Ret; +} + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source, @ref INTC_Stop_Wakeup_Source_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->WUPEN, u32WakeupSrc); + } else { + CLR_REG32_BIT(CM_INTC->WUPEN, u32WakeupSrc); + } +} + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index, @ref INTC_Event_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_EVT(u32Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->EVTER, u32Event); + } else { + CLR_REG32_BIT(CM_INTC->EVTER, u32Event); + } +} + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index, @ref INT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_INT(u32Int)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->IER, u32Int); + } else { + CLR_REG32_BIT(CM_INTC->IER, u32Int); + } +} + +/** + * @brief Software Interrupt initialize function + * @param [in] u32Ch: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] pfnCallback: Callback function + * @param [in] u32Priority: Software interrupt priority + * @retval None + */ +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority) +{ + stc_irq_signin_config_t stcIrqSignConfig; + + stcIrqSignConfig.enIRQn = (IRQn_Type)(__CLZ(__RBIT(u32Ch))); + stcIrqSignConfig.enIntSrc = (en_int_src_t)(__CLZ(__RBIT(u32Ch))); + /* Callback function */ + stcIrqSignConfig.pfnCallback = pfnCallback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, u32Priority); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); +} + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWInt: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_SWI(u32SWInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } else { + CLR_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } +} + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcNmiInit->u32Src = 0UL; + } + return i32Ret; +} + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32Src)); + /* Clear all NMI trigger source before set */ + WRITE_REG32(NMICFR_REG, NMI_SRC_ALL); + + /* NMI trigger source configure */ + WRITE_REG32(CM_INTC->NMIENR, pstcNmiInit->u32Src); + + } + return i32Ret; +} + +/** + * @brief Get NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + return (((READ_REG32(CM_INTC->NMIFR) & u32Src)) != 0UL) ? SET : RESET; +} + +/** + * @brief Set NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->NMIENR, u32Src); + } else { + CLR_REG32_BIT(CM_INTC->NMIENR, u32Src); + } +} + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for diff. MCU in details + * @retval None + */ +void NMI_ClearNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + SET_REG32_BIT(NMICFR_REG, u32Src); +} + +/** + * @brief Initialize External interrupt. + * @param [in] u32Ch: ExtInt channel. + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit) +{ + uint8_t u8ExtIntPos; + int32_t i32Ret = LL_OK; + uint32_t EIRQCRVal; + __IO uint32_t *EIRQCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32Ch)); + DDL_ASSERT(IS_EXTINT_FAE(pstcExtIntInit->u32Filter)); + DDL_ASSERT(IS_EXTINT_FACLK(pstcExtIntInit->u32FilterClock)); + DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32Edge)); + DDL_ASSERT(IS_NMI_EXTINT_FBE(pstcExtIntInit->u32FilterB)); + DDL_ASSERT(IS_NMI_EXTINT_FBTIME(pstcExtIntInit->u32FilterBClock)); + for (u8ExtIntPos = 0U; u8ExtIntPos < EXTINT_CH_NUM_MAX; u8ExtIntPos++) { + if (0UL != (u32Ch & (1UL << u8ExtIntPos))) { + EIRQCRVal = pstcExtIntInit->u32Filter | pstcExtIntInit->u32FilterClock | \ + pstcExtIntInit->u32Edge; + EIRQCRVal |= pstcExtIntInit->u32FilterB; + WRITE_REG32(CM_INTC->NOCCR, pstcExtIntInit->u32FilterBClock); + EIRQCRx = (__IO uint32_t *)((uint32_t)&CM_INTC->EIRQCR0 + 4UL * u8ExtIntPos); + WRITE_REG32(*EIRQCRx, EIRQCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief Initialize ExtInt. Fill each pstcExtIntInit with default value + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcExtIntInit->u32Filter = EXTINT_FILTER_OFF; + pstcExtIntInit->u32FilterClock = EXTINT_FCLK_DIV1; + pstcExtIntInit->u32Edge = EXTINT_TRIG_FALLING; + pstcExtIntInit->u32FilterB = NMI_EXTINT_FILTER_B_OFF; + pstcExtIntInit->u32FilterBClock = NMI_EXTINT_FCLK_B_500NS; + } + return i32Ret; +} + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval None + */ +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + SET_REG32_BIT(EIRQCFR_REG, u32ExtIntCh); +} + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + return ((READ_REG16(CM_INTC->EIRQFR) & u32ExtIntCh) != 0U) ? SET : RESET; +} + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) +{ + m_apfnIrqHandler[INT000_IRQn](); +} + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) +{ + m_apfnIrqHandler[INT001_IRQn](); +} + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) +{ + m_apfnIrqHandler[INT002_IRQn](); +} + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) +{ + m_apfnIrqHandler[INT003_IRQn](); +} + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) +{ + m_apfnIrqHandler[INT004_IRQn](); +} + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) +{ + m_apfnIrqHandler[INT005_IRQn](); +} + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) +{ + m_apfnIrqHandler[INT006_IRQn](); +} + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) +{ + m_apfnIrqHandler[INT007_IRQn](); +} + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT008_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT009_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT010_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT011_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT012_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT013_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT014_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT015_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.016 IRQ handler + * @param None + * @retval None + */ +void IRQ016_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT016_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.017 IRQ handler + * @param None + * @retval None + */ +void IRQ017_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT017_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.018 IRQ handler + * @param None + * @retval None + */ +void IRQ018_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT018_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.019 IRQ handler + * @param None + * @retval None + */ +void IRQ019_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT019_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.020 IRQ handler + * @param None + * @retval None + */ +void IRQ020_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT020_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.021 IRQ handler + * @param None + * @retval None + */ +void IRQ021_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT021_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.022 IRQ handler + * @param None + * @retval None + */ +void IRQ022_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT022_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.023 IRQ handler + * @param None + * @retval None + */ +void IRQ023_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT023_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.024 IRQ handler + * @param None + * @retval None + */ +void IRQ024_Handler(void) +{ + m_apfnIrqHandler[INT024_IRQn](); +} + +/** + * @brief Interrupt No.025 IRQ handler + * @param None + * @retval None + */ +void IRQ025_Handler(void) +{ + m_apfnIrqHandler[INT025_IRQn](); +} + +/** + * @brief Interrupt No.026 IRQ handler + * @param None + * @retval None + */ +void IRQ026_Handler(void) +{ + m_apfnIrqHandler[INT026_IRQn](); +} + +/** + * @brief Interrupt No.027 IRQ handler + * @param None + * @retval None + */ +void IRQ027_Handler(void) +{ + m_apfnIrqHandler[INT027_IRQn](); +} + +/** + * @brief Interrupt No.028 IRQ handler + * @param None + * @retval None + */ +void IRQ028_Handler(void) +{ + m_apfnIrqHandler[INT028_IRQn](); +} + +/** + * @brief Interrupt No.029 IRQ handler + * @param None + * @retval None + */ +void IRQ029_Handler(void) +{ + m_apfnIrqHandler[INT029_IRQn](); +} + +/** + * @brief Interrupt No.030 IRQ handler + * @param None + * @retval None + */ +void IRQ030_Handler(void) +{ + m_apfnIrqHandler[INT030_IRQn](); +} + +/** + * @brief Interrupt No.031 IRQ handler + * @param None + * @retval None + */ +void IRQ031_Handler(void) +{ + m_apfnIrqHandler[INT031_IRQn](); +} + +/** + * @brief Interrupt No.032 IRQ handler + * @param None + * @retval None + */ +void IRQ032_Handler(void) +{ + m_apfnIrqHandler[INT032_IRQn](); +} + +/** + * @brief Interrupt No.033 IRQ handler + * @param None + * @retval None + */ +void IRQ033_Handler(void) +{ + m_apfnIrqHandler[INT033_IRQn](); +} + +/** + * @brief Interrupt No.034 IRQ handler + * @param None + * @retval None + */ +void IRQ034_Handler(void) +{ + m_apfnIrqHandler[INT034_IRQn](); +} + +/** + * @brief Interrupt No.035 IRQ handler + * @param None + * @retval None + */ +void IRQ035_Handler(void) +{ + m_apfnIrqHandler[INT035_IRQn](); +} + +/** + * @brief Interrupt No.036 IRQ handler + * @param None + * @retval None + */ +void IRQ036_Handler(void) +{ + m_apfnIrqHandler[INT036_IRQn](); +} + +/** + * @brief Interrupt No.037 IRQ handler + * @param None + * @retval None + */ +void IRQ037_Handler(void) +{ + m_apfnIrqHandler[INT037_IRQn](); +} + +/** + * @brief Interrupt No.038 IRQ handler + * @param None + * @retval None + */ +void IRQ038_Handler(void) +{ + m_apfnIrqHandler[INT038_IRQn](); +} + +/** + * @brief Interrupt No.039 IRQ handler + * @param None + * @retval None + */ +void IRQ039_Handler(void) +{ + m_apfnIrqHandler[INT039_IRQn](); +} + +/** + * @brief Interrupt No.040 IRQ handler + * @param None + * @retval None + */ +void IRQ040_Handler(void) +{ + m_apfnIrqHandler[INT040_IRQn](); +} + +/** + * @brief Interrupt No.041 IRQ handler + * @param None + * @retval None + */ +void IRQ041_Handler(void) +{ + m_apfnIrqHandler[INT041_IRQn](); +} + +/** + * @brief Interrupt No.042 IRQ handler + * @param None + * @retval None + */ +void IRQ042_Handler(void) +{ + m_apfnIrqHandler[INT042_IRQn](); +} + +/** + * @brief Interrupt No.043 IRQ handler + * @param None + * @retval None + */ +void IRQ043_Handler(void) +{ + m_apfnIrqHandler[INT043_IRQn](); +} + +/** + * @brief Interrupt No.044 IRQ handler + * @param None + * @retval None + */ +void IRQ044_Handler(void) +{ + m_apfnIrqHandler[INT044_IRQn](); +} + +/** + * @brief Interrupt No.045 IRQ handler + * @param None + * @retval None + */ +void IRQ045_Handler(void) +{ + m_apfnIrqHandler[INT045_IRQn](); +} + +/** + * @brief Interrupt No.046 IRQ handler + * @param None + * @retval None + */ +void IRQ046_Handler(void) +{ + m_apfnIrqHandler[INT046_IRQn](); +} + +/** + * @brief Interrupt No.047 IRQ handler + * @param None + * @retval None + */ +void IRQ047_Handler(void) +{ + m_apfnIrqHandler[INT047_IRQn](); +} + +/** + * @brief Interrupt No.048 IRQ handler + * @param None + * @retval None + */ +void IRQ048_Handler(void) +{ + m_apfnIrqHandler[INT048_IRQn](); +} + +/** + * @brief Interrupt No.049 IRQ handler + * @param None + * @retval None + */ +void IRQ049_Handler(void) +{ + m_apfnIrqHandler[INT049_IRQn](); +} + +/** + * @brief Interrupt No.050 IRQ handler + * @param None + * @retval None + */ +void IRQ050_Handler(void) +{ + m_apfnIrqHandler[INT050_IRQn](); +} + +/** + * @brief Interrupt No.051 IRQ handler + * @param None + * @retval None + */ +void IRQ051_Handler(void) +{ + m_apfnIrqHandler[INT051_IRQn](); +} + +/** + * @brief Interrupt No.052 IRQ handler + * @param None + * @retval None + */ +void IRQ052_Handler(void) +{ + m_apfnIrqHandler[INT052_IRQn](); +} + +/** + * @brief Interrupt No.053 IRQ handler + * @param None + * @retval None + */ +void IRQ053_Handler(void) +{ + m_apfnIrqHandler[INT053_IRQn](); +} + +/** + * @brief Interrupt No.054 IRQ handler + * @param None + * @retval None + */ +void IRQ054_Handler(void) +{ + m_apfnIrqHandler[INT054_IRQn](); +} + +/** + * @brief Interrupt No.055 IRQ handler + * @param None + * @retval None + */ +void IRQ055_Handler(void) +{ + m_apfnIrqHandler[INT055_IRQn](); +} + +/** + * @brief Interrupt No.056 IRQ handler + * @param None + * @retval None + */ +void IRQ056_Handler(void) +{ + m_apfnIrqHandler[INT056_IRQn](); +} + +/** + * @brief Interrupt No.057 IRQ handler + * @param None + * @retval None + */ +void IRQ057_Handler(void) +{ + m_apfnIrqHandler[INT057_IRQn](); +} + +/** + * @brief Interrupt No.058 IRQ handler + * @param None + * @retval None + */ +void IRQ058_Handler(void) +{ + m_apfnIrqHandler[INT058_IRQn](); +} + +/** + * @brief Interrupt No.059 IRQ handler + * @param None + * @retval None + */ +void IRQ059_Handler(void) +{ + m_apfnIrqHandler[INT059_IRQn](); +} + +/** + * @brief Interrupt No.060 IRQ handler + * @param None + * @retval None + */ +void IRQ060_Handler(void) +{ + m_apfnIrqHandler[INT060_IRQn](); +} + +/** + * @brief Interrupt No.061 IRQ handler + * @param None + * @retval None + */ +void IRQ061_Handler(void) +{ + m_apfnIrqHandler[INT061_IRQn](); +} + +/** + * @brief Interrupt No.062 IRQ handler + * @param None + * @retval None + */ +void IRQ062_Handler(void) +{ + m_apfnIrqHandler[INT062_IRQn](); +} + +/** + * @brief Interrupt No.063 IRQ handler + * @param None + * @retval None + */ +void IRQ063_Handler(void) +{ + m_apfnIrqHandler[INT063_IRQn](); +} + +/** + * @brief Interrupt No.064 IRQ handler + * @param None + * @retval None + */ +void IRQ064_Handler(void) +{ + m_apfnIrqHandler[INT064_IRQn](); +} + +/** + * @brief Interrupt No.065 IRQ handler + * @param None + * @retval None + */ +void IRQ065_Handler(void) +{ + m_apfnIrqHandler[INT065_IRQn](); +} + +/** + * @brief Interrupt No.066 IRQ handler + * @param None + * @retval None + */ +void IRQ066_Handler(void) +{ + m_apfnIrqHandler[INT066_IRQn](); +} + +/** + * @brief Interrupt No.067 IRQ handler + * @param None + * @retval None + */ +void IRQ067_Handler(void) +{ + m_apfnIrqHandler[INT067_IRQn](); +} + +/** + * @brief Interrupt No.068 IRQ handler + * @param None + * @retval None + */ +void IRQ068_Handler(void) +{ + m_apfnIrqHandler[INT068_IRQn](); +} + +/** + * @brief Interrupt No.069 IRQ handler + * @param None + * @retval None + */ +void IRQ069_Handler(void) +{ + m_apfnIrqHandler[INT069_IRQn](); +} + +/** + * @brief Interrupt No.070 IRQ handler + * @param None + * @retval None + */ +void IRQ070_Handler(void) +{ + m_apfnIrqHandler[INT070_IRQn](); +} + +/** + * @brief Interrupt No.071 IRQ handler + * @param None + * @retval None + */ +void IRQ071_Handler(void) +{ + m_apfnIrqHandler[INT071_IRQn](); +} + +/** + * @brief Interrupt No.072 IRQ handler + * @param None + * @retval None + */ +void IRQ072_Handler(void) +{ + m_apfnIrqHandler[INT072_IRQn](); +} + +/** + * @brief Interrupt No.073 IRQ handler + * @param None + * @retval None + */ +void IRQ073_Handler(void) +{ + m_apfnIrqHandler[INT073_IRQn](); +} + +/** + * @brief Interrupt No.074 IRQ handler + * @param None + * @retval None + */ +void IRQ074_Handler(void) +{ + m_apfnIrqHandler[INT074_IRQn](); +} + +/** + * @brief Interrupt No.075 IRQ handler + * @param None + * @retval None + */ +void IRQ075_Handler(void) +{ + m_apfnIrqHandler[INT075_IRQn](); +} + +/** + * @brief Interrupt No.076 IRQ handler + * @param None + * @retval None + */ +void IRQ076_Handler(void) +{ + m_apfnIrqHandler[INT076_IRQn](); +} + +/** + * @brief Interrupt No.077 IRQ handler + * @param None + * @retval None + */ +void IRQ077_Handler(void) +{ + m_apfnIrqHandler[INT077_IRQn](); +} + +/** + * @brief Interrupt No.078 IRQ handler + * @param None + * @retval None + */ +void IRQ078_Handler(void) +{ + m_apfnIrqHandler[INT078_IRQn](); +} + +/** + * @brief Interrupt No.079 IRQ handler + * @param None + * @retval None + */ +void IRQ079_Handler(void) +{ + m_apfnIrqHandler[INT079_IRQn](); +} + +/** + * @brief Interrupt No.080 IRQ handler + * @param None + * @retval None + */ +void IRQ080_Handler(void) +{ + m_apfnIrqHandler[INT080_IRQn](); +} + +/** + * @brief Interrupt No.081 IRQ handler + * @param None + * @retval None + */ +void IRQ081_Handler(void) +{ + m_apfnIrqHandler[INT081_IRQn](); +} + +/** + * @brief Interrupt No.082 IRQ handler + * @param None + * @retval None + */ +void IRQ082_Handler(void) +{ + m_apfnIrqHandler[INT082_IRQn](); +} + +/** + * @brief Interrupt No.083 IRQ handler + * @param None + * @retval None + */ +void IRQ083_Handler(void) +{ + m_apfnIrqHandler[INT083_IRQn](); +} + +/** + * @brief Interrupt No.084 IRQ handler + * @param None + * @retval None + */ +void IRQ084_Handler(void) +{ + m_apfnIrqHandler[INT084_IRQn](); +} + +/** + * @brief Interrupt No.085 IRQ handler + * @param None + * @retval None + */ +void IRQ085_Handler(void) +{ + m_apfnIrqHandler[INT085_IRQn](); +} + +/** + * @brief Interrupt No.086 IRQ handler + * @param None + * @retval None + */ +void IRQ086_Handler(void) +{ + m_apfnIrqHandler[INT086_IRQn](); +} + +/** + * @brief Interrupt No.087 IRQ handler + * @param None + * @retval None + */ +void IRQ087_Handler(void) +{ + m_apfnIrqHandler[INT087_IRQn](); +} + +/** + * @brief Interrupt No.088 IRQ handler + * @param None + * @retval None + */ +void IRQ088_Handler(void) +{ + m_apfnIrqHandler[INT088_IRQn](); +} + +/** + * @brief Interrupt No.089 IRQ handler + * @param None + * @retval None + */ +void IRQ089_Handler(void) +{ + m_apfnIrqHandler[INT089_IRQn](); +} + +/** + * @brief Interrupt No.090 IRQ handler + * @param None + * @retval None + */ +void IRQ090_Handler(void) +{ + m_apfnIrqHandler[INT090_IRQn](); +} + +/** + * @brief Interrupt No.091 IRQ handler + * @param None + * @retval None + */ +void IRQ091_Handler(void) +{ + m_apfnIrqHandler[INT091_IRQn](); +} + +/** + * @brief Interrupt No.092 IRQ handler + * @param None + * @retval None + */ +void IRQ092_Handler(void) +{ + m_apfnIrqHandler[INT092_IRQn](); +} + +/** + * @brief Interrupt No.093 IRQ handler + * @param None + * @retval None + */ +void IRQ093_Handler(void) +{ + m_apfnIrqHandler[INT093_IRQn](); +} + +/** + * @brief Interrupt No.094 IRQ handler + * @param None + * @retval None + */ +void IRQ094_Handler(void) +{ + m_apfnIrqHandler[INT094_IRQn](); +} + +/** + * @brief Interrupt No.095 IRQ handler + * @param None + * @retval None + */ +void IRQ095_Handler(void) +{ + m_apfnIrqHandler[INT095_IRQn](); +} + +/** + * @brief Interrupt No.096 IRQ handler + * @param None + * @retval None + */ +void IRQ096_Handler(void) +{ + m_apfnIrqHandler[INT096_IRQn](); +} + +/** + * @brief Interrupt No.097 IRQ handler + * @param None + * @retval None + */ +void IRQ097_Handler(void) +{ + m_apfnIrqHandler[INT097_IRQn](); +} + +/** + * @brief Interrupt No.098 IRQ handler + * @param None + * @retval None + */ +void IRQ098_Handler(void) +{ + m_apfnIrqHandler[INT098_IRQn](); +} + +/** + * @brief Interrupt No.099 IRQ handler + * @param None + * @retval None + */ +void IRQ099_Handler(void) +{ + m_apfnIrqHandler[INT099_IRQn](); +} + +/** + * @brief Interrupt No.100 IRQ handler + * @param None + * @retval None + */ +void IRQ100_Handler(void) +{ + m_apfnIrqHandler[INT100_IRQn](); +} + +/** + * @brief Interrupt No.101 IRQ handler + * @param None + * @retval None + */ +void IRQ101_Handler(void) +{ + m_apfnIrqHandler[INT101_IRQn](); +} + +/** + * @brief Interrupt No.102 IRQ handler + * @param None + * @retval None + */ +void IRQ102_Handler(void) +{ + m_apfnIrqHandler[INT102_IRQn](); +} + +/** + * @brief Interrupt No.103 IRQ handler + * @param None + * @retval None + */ +void IRQ103_Handler(void) +{ + m_apfnIrqHandler[INT103_IRQn](); +} + +/** + * @brief Interrupt No.104 IRQ handler + * @param None + * @retval None + */ +void IRQ104_Handler(void) +{ + m_apfnIrqHandler[INT104_IRQn](); +} + +/** + * @brief Interrupt No.105 IRQ handler + * @param None + * @retval None + */ +void IRQ105_Handler(void) +{ + m_apfnIrqHandler[INT105_IRQn](); +} + +/** + * @brief Interrupt No.106 IRQ handler + * @param None + * @retval None + */ +void IRQ106_Handler(void) +{ + m_apfnIrqHandler[INT106_IRQn](); +} + +/** + * @brief Interrupt No.107 IRQ handler + * @param None + * @retval None + */ +void IRQ107_Handler(void) +{ + m_apfnIrqHandler[INT107_IRQn](); +} + +/** + * @brief Interrupt No.108 IRQ handler + * @param None + * @retval None + */ +void IRQ108_Handler(void) +{ + m_apfnIrqHandler[INT108_IRQn](); +} + +/** + * @brief Interrupt No.109 IRQ handler + * @param None + * @retval None + */ +void IRQ109_Handler(void) +{ + m_apfnIrqHandler[INT109_IRQn](); +} + +/** + * @brief Interrupt No.110 IRQ handler + * @param None + * @retval None + */ +void IRQ110_Handler(void) +{ + m_apfnIrqHandler[INT110_IRQn](); +} + +/** + * @brief Interrupt No.111 IRQ handler + * @param None + * @retval None + */ +void IRQ111_Handler(void) +{ + m_apfnIrqHandler[INT111_IRQn](); +} + +/** + * @brief Interrupt No.112 IRQ handler + * @param None + * @retval None + */ +void IRQ112_Handler(void) +{ + m_apfnIrqHandler[INT112_IRQn](); +} + +/** + * @brief Interrupt No.113 IRQ handler + * @param None + * @retval None + */ +void IRQ113_Handler(void) +{ + m_apfnIrqHandler[INT113_IRQn](); +} + +/** + * @brief Interrupt No.114 IRQ handler + * @param None + * @retval None + */ +void IRQ114_Handler(void) +{ + m_apfnIrqHandler[INT114_IRQn](); +} + +/** + * @brief Interrupt No.115 IRQ handler + * @param None + * @retval None + */ +void IRQ115_Handler(void) +{ + m_apfnIrqHandler[INT115_IRQn](); +} + +/** + * @brief Interrupt No.116 IRQ handler + * @param None + * @retval None + */ +void IRQ116_Handler(void) +{ + m_apfnIrqHandler[INT116_IRQn](); +} + +/** + * @brief Interrupt No.117 IRQ handler + * @param None + * @retval None + */ +void IRQ117_Handler(void) +{ + m_apfnIrqHandler[INT117_IRQn](); +} + +/** + * @brief Interrupt No.118 IRQ handler + * @param None + * @retval None + */ +void IRQ118_Handler(void) +{ + m_apfnIrqHandler[INT118_IRQn](); +} + +/** + * @brief Interrupt No.119 IRQ handler + * @param None + * @retval None + */ +void IRQ119_Handler(void) +{ + m_apfnIrqHandler[INT119_IRQn](); +} + +/** + * @brief Interrupt No.120 IRQ handler + * @param None + * @retval None + */ +void IRQ120_Handler(void) +{ + m_apfnIrqHandler[INT120_IRQn](); +} + +/** + * @brief Interrupt No.121 IRQ handler + * @param None + * @retval None + */ +void IRQ121_Handler(void) +{ + m_apfnIrqHandler[INT121_IRQn](); +} + +/** + * @brief Interrupt No.122 IRQ handler + * @param None + * @retval None + */ +void IRQ122_Handler(void) +{ + m_apfnIrqHandler[INT122_IRQn](); +} + +/** + * @brief Interrupt No.123 IRQ handler + * @param None + * @retval None + */ +void IRQ123_Handler(void) +{ + m_apfnIrqHandler[INT123_IRQn](); +} + +/** + * @brief Interrupt No.124 IRQ handler + * @param None + * @retval None + */ +void IRQ124_Handler(void) +{ + m_apfnIrqHandler[INT124_IRQn](); +} + +/** + * @brief Interrupt No.125 IRQ handler + * @param None + * @retval None + */ +void IRQ125_Handler(void) +{ + m_apfnIrqHandler[INT125_IRQn](); +} + +/** + * @brief Interrupt No.126 IRQ handler + * @param None + * @retval None + */ +void IRQ126_Handler(void) +{ + m_apfnIrqHandler[INT126_IRQn](); +} + +/** + * @brief Interrupt No.127 IRQ handler + * @param None + * @retval None + */ +void IRQ127_Handler(void) +{ + m_apfnIrqHandler[INT127_IRQn](); +} + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c new file mode 100644 index 0000000000..bb3f1938ba --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.c + * @brief This file provides firmware functions to manage the matrix keyscan + * function (KEYSCAN). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_keyscan.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_KEYSCAN KEYSCAN + * @brief Matrix keyscan Driver Library + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity + * @{ + */ +/*! Parameter valid check for KEYSCAN HiZ state cycles. */ +#define IS_KEYSCAN_HIZ_CYCLE(clc) \ +( ((clc) == KEYSCAN_HIZ_CYCLE_4) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_8) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_16) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_32) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_64) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_256) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_512) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_1024)) + +/*! Parameter valid check for KEYSCAN low level output cycles. */ +#define IS_KEYSCAN_LOW_CYCLE(clc) \ +( ((clc) == KEYSCAN_LOW_CYCLE_4) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16M)) + +/*! Parameter valid check for KEYSCAN scan clock. */ +#define IS_KEYSCAN_CLK(clk) \ +( ((clk) == KEYSCAN_CLK_HCLK) || \ + ((clk) == KEYSCAN_CLK_LRC) || \ + ((clk) == KEYSCAN_CLK_XTAL32)) + +/*! Parameter valid check for KEYSCAN keyout pins. */ +#define IS_KEYSCAN_OUT(out) \ +( ((out) == KEYSCAN_OUT_0T1) || \ + ((out) == KEYSCAN_OUT_0T2) || \ + ((out) == KEYSCAN_OUT_0T3) || \ + ((out) == KEYSCAN_OUT_0T4) || \ + ((out) == KEYSCAN_OUT_0T5) || \ + ((out) == KEYSCAN_OUT_0T6) || \ + ((out) == KEYSCAN_OUT_0T7)) + +/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */ +#define IS_KEYSCAN_IN(in) \ +( ((in) != 0x00U) && \ + (((in) | KEYSCAN_IN_ALL) == KEYSCAN_IN_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions + * @{ + */ + +/** + * @brief KEYSCAN function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void KEYSCAN_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(CM_KEYSCAN->SER, enNewState); +} + +/** + * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value + * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: KEYSCAN structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcKeyscanInit->u32HizCycle = KEYSCAN_HIZ_CYCLE_4; + pstcKeyscanInit->u32LowCycle = KEYSCAN_LOW_CYCLE_4; + pstcKeyscanInit->u32KeyClock = KEYSCAN_CLK_HCLK; + pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1; + pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0; + } + return i32Ret; +} + +/** + * @brief KEYSCAN initialize. + * @param [in] pstcKeyscanInit KEYSCAN config structure. + * @arg u32HizCycle Hiz state keep cycles during low level output. + * @arg u32LowCycle Low level output cycles. + * @arg u32KeyClock Scan clock. + * @arg u32KeyOut KEYOUT selection. + * @arg u32KeyIn KEYIN(EIRQ) selection. + * @retval int32_t: + * - LL_OK: KEYSCAN function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_KEYSCAN_HIZ_CYCLE(pstcKeyscanInit->u32HizCycle)); + DDL_ASSERT(IS_KEYSCAN_LOW_CYCLE(pstcKeyscanInit->u32LowCycle)); + DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClock)); + DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut)); + DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn)); + + WRITE_REG32(CM_KEYSCAN->SCR, \ + (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \ + pstcKeyscanInit->u32KeyClock | pstcKeyscanInit->u32KeyOut | \ + pstcKeyscanInit->u32KeyIn)); + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mau.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mau.c new file mode 100644 index 0000000000..9dae25132b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mau.c @@ -0,0 +1,278 @@ +/** + ******************************************************************************* + * @file hc32_ll_mau.c + * @brief This file provides firmware functions to manage the MAU. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mau.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MAU MAU + * @brief MAU Driver Library + * @{ + */ + +#if (LL_MAU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MAU_Local_Macros MAU Local Macros + * @{ + */ + +/** + * @defgroup MAU_Check_Parameters_Validity MAU Check Parameters Validity + * @{ + */ +#define IS_VALID_UNIT(x) ((x) == CM_MAU) +#define IS_LSHBIT_NUM(x) ((x) <= MAU_SQRT_OUTPUT_LSHIFT_MAX) +#define IS_ANGLE_IDX(x) ((x) < MAU_SIN_ANGIDX_TOTAL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup MAU_Global_Functions MAU Global Functions + * @{ + */ + +/** + * @brief Sqrt result left shift config + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param [in] u8LShBitsNumber Number of left shift bits + * Max value is MAU_SQRT_OUTPUT_LSHIFT_MAX + * @retval None + */ +void MAU_SqrtResultLShiftConfig(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(IS_LSHBIT_NUM(u8LShBitsNumber)); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT, ((uint32_t)u8LShBitsNumber << MAU_CSR_SHIFT_POS)); +} + +/** + * @brief Sqrt interrupt function command + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MAU_SqrtIntCmd(CM_MAU_TypeDef *MAUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_INTEN, (uint32_t)enNewState << MAU_CSR_INTEN_POS); +} + +/** + * @brief Input radicand for sqrt + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param [in] u32Radicand Data to be square rooted + * @retval None + */ +void MAU_SqrtWriteData(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + + WRITE_REG32(MAUx->DTR0, u32Radicand); +} + +/** + * @brief Start sqrt calculation + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @retval None + */ +void MAU_SqrtStart(CM_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + + SET_REG32_BIT(MAUx->CSR, MAU_CSR_START); +} + +/** + * @brief Check whether the sqrt calculation is in progress + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MAU_SqrtGetStatus(const CM_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + + return (0UL != READ_REG32_BIT(MAUx->CSR, MAU_CSR_BUSY)) ? SET : RESET; +} + +/** + * @brief Read result of sqrt + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @retval Result of sqrt,range is [0,0x10000] + */ +uint32_t MAU_SqrtReadData(const CM_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + + return READ_REG32(MAUx->RTR0); +} + +/** + * @brief Initialize the specified DAC peripheral according to the specified parameters. + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param [in] u8LShBitsNumber Sqrt result left shift bits number + * max value is @ref MAU_SQRT_OUTPUT_LSHIFT_MAX + * @param [in] enIntNewState Enable or Disable sqrt interrupt + * @ref en_functional_state_t + * @retval None + */ +void MAU_SqrtInit(CM_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(IS_LSHBIT_NUM(u8LShBitsNumber)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enIntNewState)); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN, + ((((uint32_t)u8LShBitsNumber << MAU_CSR_SHIFT_POS)) | ((uint32_t)enIntNewState << MAU_CSR_INTEN_POS))); +} + +/** + * @brief De-initialize the DAC peripheral. RESET the registers of the specified DAC unit. + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @retval None + */ +void MAU_SqrtDeInit(CM_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + + CLR_REG32_BIT(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN); +} + +/** + * @brief Square root + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param [in] u32Radicand Data to be square rooted + * @param [out] pu32Result Result of sqrt,range is [0,0x10000] + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR: Errors occurred + */ +int32_t MAU_Sqrt(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result) +{ + __IO uint32_t u32TimeCount = MAU_SQRT_TIMEOUT; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(pu32Result != (void *)0UL); + + WRITE_REG32(MAUx->DTR0, u32Radicand); + SET_REG32_BIT(MAUx->CSR, MAU_CSR_START); + __ASM("NOP"); + __ASM("NOP"); + __ASM("NOP"); + + while ((MAUx->CSR & MAU_CSR_BUSY) != 0UL) { + if (u32TimeCount-- == 0UL) { + i32Ret = LL_ERR; + break; + } + } + + if (LL_OK == i32Ret) { + *pu32Result = READ_REG32(MAUx->RTR0); + } + + return i32Ret; +} + +/** + * @brief Sine + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg CM_MAU + * @param u16AngleIdx: Angle index,range is [0,0xFFF], calculation method for reference: + AngleIdx = (uint16_t)(Angle * 4096.0F / 360.0F + 0.5F) % 4096U + * @retval Result of Sine in Q15 format + */ +int16_t MAU_Sin(CM_MAU_TypeDef *MAUx, uint16_t u16AngleIdx) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(IS_ANGLE_IDX(u16AngleIdx)); + + WRITE_REG16(MAUx->DTR1, u16AngleIdx); + __ASM("NOP"); + + return (int16_t)READ_REG16(MAUx->RTR1); +} + +/** + * @} + */ + +#endif /* LL_MAU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c new file mode 100644 index 0000000000..a659ece50a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c @@ -0,0 +1,950 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.c + * @brief This file provides firmware functions to manage the Memory Protection + * Unit(MPU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mpu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MPU MPU + * @brief Memory Protection Unit Driver Library + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Local_Macros MPU Local Macros + * @{ + */ + +/* Number of MPU region */ +#define MPU_REGION_MAX_NUM (16UL) + +/* Number of MPU unit */ +#define MPU_UNIT_MAX_NUM (5UL) + +/* Number of SP unit */ + +/* MPU Register Combination Mask */ +#define MPU_UNIT_CONFIG_MASK (MPU_S1CR_SMPU1BRP | MPU_S1CR_SMPU1BWP | MPU_S1CR_SMPU1ACT) +/* DMA units have 16 regions */ +#define MPU_16REGION_UNIT (MPU_UNIT_DMA1 | MPU_UNIT_DMA2) + +/* Get the specified register address of the MPU Intrusion Control */ +#define MPU_RGD_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U)) +#define MPU_RGE_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGE)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_RGWP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGWP)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_RGRP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGRP)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_CR_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1CR)) + ((uint32_t)(__UNIT__) << 4U)) + +/* Get the SP register address */ + +/** + * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity + * @{ + */ +#define IS_MPU_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL)) + +#define IS_MPU_REGION(x) ((x) <= MPU_REGION_NUM15) + +#define IS_MPU_UNIT_REGION(unit, region) \ +( (((unit) | MPU_16REGION_UNIT) == MPU_16REGION_UNIT) || \ + ((region) <= MPU_REGION_NUM7)) + +#define IS_MPU_BACKGROUND_WR(x) \ +( ((x) == MPU_BACKGROUND_WR_DISABLE) || \ + ((x) == MPU_BACKGROUND_WR_ENABLE)) + +#define IS_MPU_BACKGROUND_RD(x) \ +( ((x) == MPU_BACKGROUND_RD_DISABLE) || \ + ((x) == MPU_BACKGROUND_RD_ENABLE)) + +#define IS_MPU_EXP_TYPE(x) \ +( ((x) == MPU_EXP_TYPE_NONE) || \ + ((x) == MPU_EXP_TYPE_BUS_ERR) || \ + ((x) == MPU_EXP_TYPE_NMI) || \ + ((x) == MPU_EXP_TYPE_RST)) + +#define IS_MPU_REGION_WR(x) \ +( ((x) == MPU_REGION_WR_DISABLE) || \ + ((x) == MPU_REGION_WR_ENABLE)) + +#define IS_MPU_REGION_RD(x) \ +( ((x) == MPU_REGION_RD_DISABLE) || \ + ((x) == MPU_REGION_RD_ENABLE)) + +#define IS_MPU_REGION_SIZE(x) \ +( ((x) >= MPU_REGION_SIZE_32BYTE) && \ + ((x) <= MPU_REGION_SIZE_4GBYTE)) + +#define IS_MPU_REGION_BASE_ADDER(addr, size) \ +( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL) + +#define IS_MPU_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL)) + +#define IS_MPU_IP_TYPE(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_IP_ALL) == MPU_IP_ALL)) + +#define IS_MPU_IP_EXP_TYPE(x) \ +( ((x) == MPU_IP_EXP_TYPE_NONE) || \ + ((x) == MPU_IP_EXP_TYPE_BUS_ERR)) + +#define IS_MPU_UNLOCK() ((CM_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Functions MPU Global Functions + * @{ + */ + +/** + * @brief De-Initialize MPU. + * @param None + * @retval None + */ +void MPU_DeInit(void) +{ + uint32_t i; + __IO uint32_t *RGD; + __IO uint32_t *RGE; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + __IO uint32_t *CR; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + + for (i = 0UL; i < MPU_REGION_MAX_NUM; i++) { + RGD = MPU_RGD_ADDR(i); + WRITE_REG32(*RGD, 0UL); + } + WRITE_REG32(CM_MPU->ECLR, MPU_FLAG_ALL); + WRITE_REG32(CM_MPU->IPPR, 0UL); + for (i = 0UL; i < MPU_UNIT_MAX_NUM; i++) { + RGE = MPU_RGE_ADDR(i); + WRITE_REG32(*RGE, 0UL); + RGWP = MPU_RGWP_ADDR(i); + WRITE_REG32(*RGWP, 0UL); + RGRP = MPU_RGRP_ADDR(i); + WRITE_REG32(*RGRP, 0UL); + CR = MPU_CR_ADDR(i); + WRITE_REG32(*CR, 0UL); + } +} + +/** + * @brief Initialize MPU. + * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma1.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma1.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma2.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma2.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbFSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcUsbFSDma.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcUsbFSDma.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbHSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcUsbHSDma.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcUsbHSDma.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcEthDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcEthDma.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcEthDma.u32BackgroundRead)); + + MODIFY_REG32(CM_MPU->S1CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma1.u32ExceptionType | pstcMpuInit->stcDma1.u32BackgroundWrite | + pstcMpuInit->stcDma1.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->S2CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma2.u32ExceptionType | pstcMpuInit->stcDma2.u32BackgroundWrite | + pstcMpuInit->stcDma2.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->FCR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcUsbFSDma.u32ExceptionType | pstcMpuInit->stcUsbFSDma.u32BackgroundWrite | + pstcMpuInit->stcUsbFSDma.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->HCR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcUsbHSDma.u32ExceptionType | pstcMpuInit->stcUsbHSDma.u32BackgroundWrite | + pstcMpuInit->stcUsbHSDma.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->ECR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcEthDma.u32ExceptionType | pstcMpuInit->stcEthDma.u32BackgroundWrite | + pstcMpuInit->stcEthDma.u32BackgroundRead)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_init_t member with default value. + * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma1.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma1.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma2.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcUsbFSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbFSDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcUsbFSDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcUsbHSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbHSDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcUsbHSDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcEthDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcEthDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcEthDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the exception type of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] u32Type Exception type of MPU unit. + * This parameter can be one of the following values: + * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored + * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered + * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered + * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset + * @retval None + */ +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_EXP_TYPE(u32Type)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + MODIFY_REG32(*CR, MPU_S1CR_SMPU1ACT, u32Type); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the write of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*CR, MPU_S1CR_SMPU1BWP); + } else { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1BWP); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*CR, MPU_S1CR_SMPU1BRP); + } else { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1BRP); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1E); + } else { + CLR_REG32_BIT(*CR, MPU_S1CR_SMPU1E); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Gets the status of MPU flag. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MPU_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_MPU->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear the flag of MPU. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval None + */ +void MPU_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + SET_REG32_BIT(CM_MPU->ECLR, u32Flag); +} + +/** + * @brief Initialize the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *RGD; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + uint32_t i; + uint32_t u32UnitNum = MPU_UNIT_MAX_NUM; + stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_MAX_NUM]; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma1.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma1.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma2.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma2.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcUsbFSDma.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcUsbFSDma.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcUsbHSDma.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcUsbHSDma.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcEthDma.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcEthDma.u32RegionRead)); + + RGD = MPU_RGD_ADDR(u32Num); + WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr)); + /* Configure the read/write permission for the region */ + RegionBuffer[0] = pstcRegionInit->stcDma1; + RegionBuffer[1] = pstcRegionInit->stcDma2; + RegionBuffer[2] = pstcRegionInit->stcUsbFSDma; + RegionBuffer[3] = pstcRegionInit->stcUsbHSDma; + RegionBuffer[4] = pstcRegionInit->stcEthDma; + if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) { + u32UnitNum = 2UL; + } + for (i = 0UL; i < u32UnitNum; i++) { + /* Configure the write permission for the region */ + RGWP = MPU_RGWP_ADDR(i); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionWrite) { + CLR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + /* Configure the read permission for the region */ + RGRP = MPU_RGRP_ADDR(i); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionRead) { + CLR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_region_init_t member with default value. + * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_region_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRegionInit->u32BaseAddr = 0UL; + pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE; + pstcRegionInit->stcDma1.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma1.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcDma2.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma2.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcUsbHSDma.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcUsbHSDma.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcEthDma.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcEthDma.u32RegionRead = MPU_REGION_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the base address of the region. + * @note The effective bits of the 'u32Addr' are related to the 'size' of the region, + * and the low 'size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Addr The base address of the region. + * @retval None + */ +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + + RGD = MPU_RGD_ADDR(u32Num); + /* Check parameters */ + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE))); + + MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr); +} + +/** + * @brief Set the size of the region. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Size The size of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_SIZE_32BYTE: 32 Byte + * @arg MPU_REGION_SIZE_64BYTE: 64 Byte + * @arg MPU_REGION_SIZE_128BYTE: 126 Byte + * @arg MPU_REGION_SIZE_256BYTE: 256 Byte + * @arg MPU_REGION_SIZE_512BYTE: 512 Byte + * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte + * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte + * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte + * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte + * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte + * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte + * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte + * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte + * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte + * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte + * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte + * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte + * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte + * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte + * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte + * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte + * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte + * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte + * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte + * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte + * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte + * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte + * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte + * @retval None + */ +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size)); + + RGD = MPU_RGD_ADDR(u32Num); + MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size); +} + +/** + * @brief Enable or disable the write of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGWP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + /* Configure the write permission for the region */ + RGWP = MPU_RGWP_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGRP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + /* Configure the read permission for the region */ + RGRP = MPU_RGRP_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGE; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGE = MPU_RGE_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + SET_REG32_BIT(*RGE, (0x1UL << u32Num)); + } else { + CLR_REG32_BIT(*RGE, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the type of exception to access the protected IP. + * @param [in] u32Type Exception type of MPU IP. + * This parameter can be one of the following values: + * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored + * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error + * @retval None + */ +void MPU_IP_SetExceptionType(uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32Type)); + + WRITE_REG32(bCM_MPU->IPPR_b.BUSERRE, (u32Type >> MPU_IPPR_BUSERRE_POS)); +} + +/** + * @brief Enable or disable write for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } else { + SET_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } +} + +/** + * @brief Enable or disable read for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, u32Periph); + } else { + SET_REG32_BIT(CM_MPU->IPPR, u32Periph); + } +} + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_nfc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_nfc.c new file mode 100644 index 0000000000..9d4ba872e9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_nfc.c @@ -0,0 +1,1821 @@ +/** + ******************************************************************************* + * @file hc32_ll_nfc.c + * @brief This file provides firmware functions to manage the EXMC NFC + * (External Memory Controller: NAND Flash Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ll_nfc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EXMC EXMC + * @brief External Memory Controller Driver Library + * @{ + */ + +/** + * @defgroup LL_NFC NFC + * @brief NAND Flash Controller Driver Library + * @{ + */ + +#if (LL_NFC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Local_Macros EXMC_NFC Local Macros + * @{ + */ + +/** + * @defgroup EXMC_NFC_Check_Parameters_Validity EXMC_NFC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_NFC_BANK(x) ((x) <= EXMC_NFC_BANK7) + +#define IS_EXMC_NFC_MEMORY_WIDTH(x) \ +( ((x) == EXMC_NFC_MEMORY_WIDTH_8BIT) || \ + ((x) == EXMC_NFC_MEMORY_WIDTH_16BIT)) + +#define IS_EXMC_NFC_BANK_CAPACITY(x) \ +( ((x) == EXMC_NFC_BANK_CAPACITY_1GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_2GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_4GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_8GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_16GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_32GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_64GBIT) || \ + ((x) == EXMC_NFC_BANK_CAPACITY_512MBIT)) + +#define IS_EXMC_NFC_PAGE_SIZE(x) \ +( ((x) == EXMC_NFC_PAGE_SIZE_2KBYTE) || \ + ((x) == EXMC_NFC_PAGE_SIZE_4KBYTE) || \ + ((x) == EXMC_NFC_PAGE_SIZE_8KBYTE)) + +#define IS_EXMC_NFC_BANK_NUM(x) \ +( ((x) == EXMC_NFC_1BANK) || \ + ((x) == EXMC_NFC_2BANKS) || \ + ((x) == EXMC_NFC_4BANKS) || \ + ((x) == EXMC_NFC_8BANKS)) + +#define IS_EXMC_NFC_WR_PROTECT(x) \ +( ((x) == EXMC_NFC_WR_PROTECT_ENABLE) || \ + ((x) == EXMC_NFC_WR_PROTECT_DISABLE)) + +#define IS_EXMC_NFC_ECC_MD(x) \ +( ((x) == EXMC_NFC_1BIT_ECC) || \ + ((x) == EXMC_NFC_4BIT_ECC)) + +#define IS_EXMC_NFC_ROW_ADDR_CYCLES(x) \ +( ((x) == EXMC_NFC_2_ROW_ADDR_CYCLE) || \ + ((x) == EXMC_NFC_3_ROW_ADDR_CYCLE)) + +#define IS_EXMC_NFC_SECTION(x) ((x) <= EXMC_NFC_ECC_SECTION15) + +#define IS_EXMC_NFC_INT(x) \ +( ((x) != 0UL) && \ + (((x) | EXMC_NFC_INT_MASK) == EXMC_NFC_INT_MASK)) + +#define IS_EXMC_NFC_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EXMC_NFC_FLAG_MASK) == EXMC_NFC_FLAG_MASK)) + +#define IS_EXMC_NFC_TIMING_TS(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWP(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRP(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRR(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWB(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TCCS(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWTR(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRTW(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TADL(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_COLUMN(x) ((x) <= NFC_COLUMN_MAX) + +#define IS_EXMC_NFC_PAGE(page, capacity_index) ((page) <= NFC_PAGE_MAX((capacity_index))) + +#define IS_PARAM_ALIGN_WORD(x) (IS_ADDR_ALIGN_WORD((x))) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Interrupt_Mask EXMC_NFC Interrupt Mask + * @{ + */ +#define EXMC_NFC_INT_MASK \ +( EXMC_NFC_INT_RB_BANK0 | \ + EXMC_NFC_INT_RB_BANK1 | \ + EXMC_NFC_INT_RB_BANK2 | \ + EXMC_NFC_INT_RB_BANK3 | \ + EXMC_NFC_INT_RB_BANK4 | \ + EXMC_NFC_INT_RB_BANK5 | \ + EXMC_NFC_INT_RB_BANK6 | \ + EXMC_NFC_INT_RB_BANK7 | \ + EXMC_NFC_INT_ECC_ERROR | \ + EXMC_NFC_INT_ECC_CALC_COMPLETION | \ + EXMC_NFC_INT_ECC_CORRECTABLE_ERR | \ + EXMC_NFC_INT_ECC_UNCORRECTABLE_ERR) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Flag_Mask EXMC_NFC Flag Mask + * @{ + */ +#define EXMC_NFC_FLAG_MASK \ +( EXMC_NFC_FLAG_RB_BANK0 | \ + EXMC_NFC_FLAG_RB_BANK1 | \ + EXMC_NFC_FLAG_RB_BANK2 | \ + EXMC_NFC_FLAG_RB_BANK3 | \ + EXMC_NFC_FLAG_RB_BANK4 | \ + EXMC_NFC_FLAG_RB_BANK5 | \ + EXMC_NFC_FLAG_RB_BANK6 | \ + EXMC_NFC_FLAG_RB_BANK7 | \ + EXMC_NFC_FLAG_ECC_ERR | \ + EXMC_NFC_FLAG_ECC_CALCULATING | \ + EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR | \ + EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Memory_Capacity_Index EXMC_NFC Memory Capacity Index + * @{ + */ +#define NFC_CAPACITY_INDEX_512MBIT (0UL) +#define NFC_CAPACITY_INDEX_1GBIT (1UL) +#define NFC_CAPACITY_INDEX_2GBIT (2UL) +#define NFC_CAPACITY_INDEX_4GBIT (3UL) +#define NFC_CAPACITY_INDEX_8GBIT (4UL) +#define NFC_CAPACITY_INDEX_16GBIT (5UL) +#define NFC_CAPACITY_INDEX_32GBIT (6UL) +#define NFC_CAPACITY_INDEX_64GBIT (7UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Command_Regster_Value EXMC_NFC Command Regster Value + * @{ + */ +/*!< Command value */ +#define NFC_CMD_VALUE(arg, bank, cmd) ((arg) | ((bank) << 8U) | (cmd)) + +/*!< Command: Read status */ +#define NFC_ADDR_VALUE(bank, addr) (0x40000000UL | ((bank) << 8U) | (addr)) + +/*!< Command: Read status */ +#define CMD_RESET(bank) (NFC_CMD_VALUE(0UL, (bank), EXMC_NFC_CMD_RESET)) + +/*!< Command: Read status */ +#define CMD_ASYNC_RESET(bank) (NFC_CMD_VALUE(0x82000000UL, (bank), EXMC_NFC_CMD_ASYNCHRONOUS_RST)) + +/*!< Command: Read status */ +#define CMD_RESET_LUN(bank) (NFC_CMD_VALUE(0x82000000UL, (bank), EXMC_NFC_CMD_RST_LUN)) + +/*!< Command: Read status */ +#define CMD_READ_STATUS(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_RD_STATUS)) + +/*!< Command: Read status */ +#define CMD_READ_STATUS_ENHANCED(bank) (NFC_CMD_VALUE(0x80000000UL, (bank), EXMC_NFC_CMD_RD_STATUS_ENHANCED)) + +/*!< Command: Read ID */ +#define CMD_READ_ID(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_RD_ID)) +#define CMD_READ_ID_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Read unique ID */ +#define CMD_READ_UNIQUEID(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_RD_UNIQUE_ID)) +#define CMD_READ_UNIQUEID_ADDR(bank) (NFC_ADDR_VALUE((bank), 0UL)) + +/*!< Command: Erase block */ +#define CMD_ERASE_BLOCK_1ST_CYCLE(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_BLK_ERASE_1ST)) +#define CMD_ERASE_BLOCK_2ND_CYCLE(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_BLK_ERASE_2ND)) + +/*!< Command: Read parameter page */ +#define CMD_READ_PARAMETER_PAGE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_RD_PARAMETER_PAGE)) +#define CMD_READ_PARAMETER_PAGE_ADDR(bank) (NFC_ADDR_VALUE((bank), 0UL)) + +/*!< Command: Set feature */ +#define CMD_SET_FEATURE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_SET_FEATURES)) +#define CMD_SET_FEATURE_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Get feature */ +#define CMD_GET_FEATURE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_GET_FEATURES)) +#define CMD_GET_FEATURE_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Address cycle */ +#define CMD_ADDR_1ST_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), ((ras) & 0xFFUL))) +#define CMD_ADDR_2ND_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), (((ras) & 0xFF00UL) >> 8UL))) +#define CMD_ADDR_3RD_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), (((ras) & 0xFF0000UL) >> 16UL))) + +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_IDXR_Bit_Position EXMC_NFC IDXR Bit Position + * @{ + */ +#define EXMC_NFC_IDXR_COL_POS (0U) +#define EXMC_NFC_IDXR_2KPAGE_POS (12U) +#define EXMC_NFC_IDXR_512MBIT_BANK_POS (27U) +/** + * @} + */ + +/*!< NFC BACR regsiter: page field value */ +#define NFC_BACR_PAGE_VAL ((uint8_t)((READ_REG32_BIT(CM_NFC->BACR, NFC_BACR_PAGE) >> NFC_BACR_PAGE_POS) & 0x3UL)) + +/*!< NFC Page Size */ +#define NFC_PAGE_SIZE (1024UL << NFC_BACR_PAGE_VAL) + +/*!< NFC page max for the specified capacity */ +#define NFC_PAGE_MAX(capacity_index) ((1UL << (19U + (uint8_t)(capacity_index) - NFC_BACR_PAGE_VAL)) - 1UL) + +/*!< NFC column max */ +#define NFC_COLUMN_MAX ((1UL << (EXMC_NFC_IDXR_2KPAGE_POS + NFC_BACR_PAGE_VAL - 1U)) - 1UL) + +/*!< NFC Spare Size for user data */ +#define NFC_SPARE_SIZE_FOR_USER_DATA ((READ_REG32_BIT(CM_NFC->BACR, NFC_BACR_SCS) >> NFC_BACR_SCS_POS) << 2UL) + +/*!< NFC_ISTR register RBST bit mask */ +#define NFC_FLAG_RB_BANKx_MASK(bank) (EXMC_NFC_FLAG_RB_BANK0 << (EXMC_NFC_BANK7 & (bank))) + +/*!< IDX register mask for 64bit */ +#define NFC_NFC_ISTR_MASK (0xFF53UL) + +/*!< NFC_DATR for 32bit */ +#define NFC_DATR_REG32(x) (CM_NFC->DATR_BASE) + +/** + * @defgroup EXMC_NFC_ECC_Reference EXMC_NFC ECC Reference + * @{ + */ +/*!< NFC_SYND_REG for 32bit */ +#define NFC_SYND_REG32(sect, reg) (*((__IO uint32_t *)((uint32_t)(&(CM_NFC->ECC_SYND0_0)) + (((uint32_t)(sect)) << 4UL) + (((uint32_t)(reg)) << 2UL)))) + +/*!< NFC_ECCR_REG for 32bit */ +#define NFC_ECCR_REG32(sect) (*((__IO uint32_t *)((uint32_t)(&(CM_NFC->ECCR0)) + (((uint32_t)(sect)) << 2UL)))) + +/*!< NFC_SYND_MAX_Length (Unit: half-word ) */ +#define NFC_SYND_MAX_LEN (8U) + +/*!< NFC 1Bit ECC Error Bit Mask */ +#define NFC_1BIT_ECC_ERR_BIT_MASK (0x7U) + +/*!< NFC 1Bit ECC Error Byte Position */ +#define NFC_1BIT_ECC_ERR_BYTE_POS (3U) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_IDXR_Register_Reference EXMC_NFC IDXR Register Reference + * @note capacity_index @ref EXMC_NFC_Memory_Capacity_Index + * @{ + */ +/*!< IDX register value for 64bit */ +#define NFC_IDXR_VAL(bank, page, col, capacity_index) \ +( (((uint64_t)(col)) << EXMC_NFC_IDXR_COL_POS) | \ + (((uint64_t)(page)) << (EXMC_NFC_IDXR_2KPAGE_POS + NFC_BACR_PAGE_VAL - 1U)) | \ + (((uint64_t)(bank)) << (EXMC_NFC_IDXR_512MBIT_BANK_POS + (uint8_t)(capacity_index)))) + +/*!< IDX register mask for 64bit */ +#define NFC_IDXR_MASK (0x1FFFFFFFFFULL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EXMC_NFC_Local_Functions EXMC_NFC Local Functions + * @{ + */ + +/** + * @brief Get capacity size. + * @param None + * @retval Capacity index @ref EXMC_NFC_Memory_Capacity_Index + * - NFC_CAPACITY_INDEX_512MBIT: NFC device capacity 512MBit + * - NFC_CAPACITY_INDEX_1GBIT: NFC device capacity 1GBit + * - NFC_CAPACITY_INDEX_2GBIT: NFC device capacity 2GBit + * - NFC_CAPACITY_INDEX_4GBIT: NFC device capacity 4GBit + * - NFC_CAPACITY_INDEX_8GBIT: NFC device capacity 8GBit + * - NFC_CAPACITY_INDEX_16GBIT: NFC device capacity 16GBit + * - NFC_CAPACITY_INDEX_32GBIT: NFC device capacity 32GBit + * - NFC_CAPACITY_INDEX_64GBIT: NFC device capacity 64GBit + */ +static uint32_t EXMC_NFC_GetCapacityIndex(void) +{ + uint32_t u32Index; + const uint32_t u32BacrSize = READ_REG32_BIT(CM_NFC->BACR, NFC_BACR_SIZE); + + switch (u32BacrSize) { + case EXMC_NFC_BANK_CAPACITY_512MBIT: + u32Index = NFC_CAPACITY_INDEX_512MBIT; + break; + case EXMC_NFC_BANK_CAPACITY_1GBIT: + u32Index = NFC_CAPACITY_INDEX_1GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_2GBIT: + u32Index = NFC_CAPACITY_INDEX_2GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_4GBIT: + u32Index = NFC_CAPACITY_INDEX_4GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_8GBIT: + u32Index = NFC_CAPACITY_INDEX_8GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_16GBIT: + u32Index = NFC_CAPACITY_INDEX_16GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_32GBIT: + u32Index = NFC_CAPACITY_INDEX_32GBIT; + break; + default: + u32Index = NFC_CAPACITY_INDEX_64GBIT; + break; + } + + return u32Index; +} + +/** + * @brief Wait the specified flag with timeout. + * @param [in] u32Flag The specified flag + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC device bank 0 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC device bank 1 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC device bank 2 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC device bank 3 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC device bank 4 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC device bank 5 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC device bank 6 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC device bank 7 busy flag + * @arg EXMC_NFC_FLAG_ECC_ERR: ECC error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR: ECC uncorrectable error + * @param enStatus The waiting flag status (SET or RESET). + * @param u32Timeout Timeout duration(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: Complete wait the expected status of the specified flags. + * - LL_ERR_TIMEOUT: Wait timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +static int32_t EXMC_NFC_WaitFlagUntilTo(uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32To = 0UL; + + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + while (EXMC_NFC_GetStatus(u32Flag) != enStatus) { + /* Block checking flag if timeout value is EXMC_NFC_MAX_TIMEOUT */ + if ((u32To > u32Timeout) && (u32Timeout < EXMC_NFC_MAX_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + + u32To++; + } + + return i32Ret; +} + +/** + * @brief NFC read operation + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] u32Col The column address + * @param [out] au32Data The buffer for reading + * @param [in] u32NumWords The buffer size for words + * @param [in] enEccState Disable/enable ECC function + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer au32Data value is NULL or u32NumWords is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +static int32_t EXMC_NFC_Read(uint32_t u32Bank, uint32_t u32Page, uint32_t u32Col, + uint32_t au32Data[], uint32_t u32NumWords, + en_functional_state_t enEccState, uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + + if ((NULL != au32Data) && (u32NumWords > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_EXMC_NFC_PAGE(u32Page, u32CapacityIndex)); + DDL_ASSERT(IS_EXMC_NFC_COLUMN(u32Col)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enEccState)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR | EXMC_NFC_FLAG_ECC_CALC_COMPLETION | EXMC_NFC_FLAG_ECC_ERR); + + EXMC_NFC_EccCmd(enEccState); + + /* Read page step: + 1. Write 0x00000000 to NFC_CMDR + 2. Write NAND Flash address to NFC_IDXR0/1 + 3. Write 0x000000E0 to NFC_CMDR + 4. Wait RB signal until high level + 5. Read NFC_DATR + 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + + /* 1. Write 0x00000000 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_RD_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + u64Value = (NFC_IDXR_VAL(u32Bank, u32Page, u32Col, u32CapacityIndex) & NFC_IDXR_MASK); + WRITE_REG32(CM_NFC->IDXR0, (uint32_t)(u64Value & 0xFFFFFFFFUL)); + WRITE_REG32(CM_NFC->IDXR1, (uint32_t)(u64Value >> 32UL)); + + /* 3. Write 0x000000E0 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_RD_2ND); + + /* 4. Wait RB signal until high level */ + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + if (LL_OK == i32Ret) { + /* 5. Read NFC_DATR */ + for (i = 0UL; i < u32NumWords; i++) { + au32Data[i] = NFC_DATR_REG32(i); + } + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + if (ENABLE == enEccState) { + /* Write 0x00000023 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_CALCULATE_ECC); + + /* 4. Wait RB signal until high level */ + i32Ret = EXMC_NFC_WaitFlagUntilTo(EXMC_NFC_FLAG_ECC_CALCULATING, RESET, u32Timeout); + EXMC_NFC_EccCmd(DISABLE); + } + } + + /* 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief NFC write operation + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] u32Col The column address + * @param [in] au32Data The buffer for writing + * @param [in] u32NumWords The buffer size for words + * @param [in] enEccState Disable/enable ECC function + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer au32Data value is NULL or u32NumWords is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +static int32_t EXMC_NFC_Write(uint32_t u32Bank, uint32_t u32Page, uint32_t u32Col, + const uint32_t au32Data[], uint32_t u32NumWords, + en_functional_state_t enEccState, uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + + if ((NULL != au32Data) && (u32NumWords > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_EXMC_NFC_PAGE(u32Page, u32CapacityIndex)); + DDL_ASSERT(IS_EXMC_NFC_COLUMN(u32Col)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enEccState)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR | EXMC_NFC_FLAG_ECC_CALC_COMPLETION | EXMC_NFC_FLAG_ECC_ERR); + + EXMC_NFC_EccCmd(enEccState); + + /* Write page step: + 1. Write 0x00000080 to NFC_CMDR + 2. Write NAND Flash address to NFC_IDXR0/1 + 3. Write NFC_DATR + 4. Write 0x00000010 to NFC_CMDR + 5. Wait RB signal until high level + 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + + /* 1. Write 0x00000080 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_PAGE_PROGRAM_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + u64Value = (NFC_IDXR_VAL(u32Bank, u32Page, u32Col, u32CapacityIndex) & NFC_IDXR_MASK); + WRITE_REG32(CM_NFC->IDXR0, (uint32_t)(u64Value & 0xFFFFFFFFUL)); + WRITE_REG32(CM_NFC->IDXR1, (uint32_t)(u64Value >> 32UL)); + + /* 3. Write NFC_DATR */ + for (i = 0UL; i < u32NumWords; i++) { + NFC_DATR_REG32(i) = au32Data[i]; + } + + /* 4. Write 0x00000010 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_PAGE_PROGRAM_2ND); + + /* 5. Wait RB signal until high level */ + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + + /* Write 0x000000FE to NFC_CMDR, and invalidate CE */ + EXMC_NFC_DeselectChip(); + + if (ENABLE == enEccState) { + EXMC_NFC_EccCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Global_Functions EXMC_NFC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_exmc_nfc_init_t to default values + * @param [out] pstcNfcInit Pointer to a @ref stc_exmc_nfc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcNfcInit value is NULL. + */ +int32_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcNfcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcNfcInit) { + pstcNfcInit->stcBaseConfig.u32CapacitySize = EXMC_NFC_BANK_CAPACITY_8GBIT; + pstcNfcInit->stcBaseConfig.u32MemoryWidth = EXMC_NFC_MEMORY_WIDTH_8BIT; + pstcNfcInit->stcBaseConfig.u32BankNum = EXMC_NFC_4BANKS; + pstcNfcInit->stcBaseConfig.u32PageSize = EXMC_NFC_PAGE_SIZE_2KBYTE; + pstcNfcInit->stcBaseConfig.u32WriteProtect = EXMC_NFC_WR_PROTECT_ENABLE; + pstcNfcInit->stcBaseConfig.u32EccMode = EXMC_NFC_1BIT_ECC; + pstcNfcInit->stcBaseConfig.u32RowAddrCycle = EXMC_NFC_3_ROW_ADDR_CYCLE; + pstcNfcInit->stcBaseConfig.u8SpareSizeForUserData = 0U; + + pstcNfcInit->stcTimingReg0.u32TS = 0x02UL; + pstcNfcInit->stcTimingReg0.u32TWP = 0x02UL; + pstcNfcInit->stcTimingReg0.u32TRP = 0x03UL; + pstcNfcInit->stcTimingReg0.u32TH = 0x03UL; + + pstcNfcInit->stcTimingReg1.u32TWH = 0x03UL; + pstcNfcInit->stcTimingReg1.u32TRH = 0x03UL; + pstcNfcInit->stcTimingReg1.u32TRR = 0x02UL; + pstcNfcInit->stcTimingReg1.u32TWB = 0x28UL; + + pstcNfcInit->stcTimingReg2.u32TCCS = 0x03UL; + pstcNfcInit->stcTimingReg2.u32TWTR = 0x0DUL; + pstcNfcInit->stcTimingReg2.u32TRTW = 0x05UL; + pstcNfcInit->stcTimingReg2.u32TADL = 0x03UL; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EXMC_NFC function. + * @param [in] pstcNfcInit Pointer to a @ref stc_exmc_nfc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcNfcInit value is NULL. + */ +int32_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcNfcInit) +{ + uint32_t u32RegVal; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcNfcInit) { + DDL_ASSERT(IS_EXMC_NFC_BANK_CAPACITY(pstcNfcInit->stcBaseConfig.u32CapacitySize)); + DDL_ASSERT(IS_EXMC_NFC_MEMORY_WIDTH(pstcNfcInit->stcBaseConfig.u32MemoryWidth)); + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(pstcNfcInit->stcBaseConfig.u32BankNum)); + DDL_ASSERT(IS_EXMC_NFC_PAGE_SIZE(pstcNfcInit->stcBaseConfig.u32PageSize)); + DDL_ASSERT(IS_EXMC_NFC_WR_PROTECT(pstcNfcInit->stcBaseConfig.u32WriteProtect)); + DDL_ASSERT(IS_EXMC_NFC_ECC_MD(pstcNfcInit->stcBaseConfig.u32EccMode)); + DDL_ASSERT(IS_EXMC_NFC_ROW_ADDR_CYCLES(pstcNfcInit->stcBaseConfig.u32RowAddrCycle)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TS(pstcNfcInit->stcTimingReg0.u32TS)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWP(pstcNfcInit->stcTimingReg0.u32TWP)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRP(pstcNfcInit->stcTimingReg0.u32TRP)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TH(pstcNfcInit->stcTimingReg0.u32TH)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWH(pstcNfcInit->stcTimingReg1.u32TWH)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRH(pstcNfcInit->stcTimingReg1.u32TRH)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRR(pstcNfcInit->stcTimingReg1.u32TRR)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWB(pstcNfcInit->stcTimingReg1.u32TWB)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TCCS(pstcNfcInit->stcTimingReg2.u32TCCS)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWTR(pstcNfcInit->stcTimingReg2.u32TWTR)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRTW(pstcNfcInit->stcTimingReg2.u32TRTW)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TADL(pstcNfcInit->stcTimingReg2.u32TADL)); + + /* Set NFC open-page.*/ + WRITE_REG32(CM_PERIC->NFC_STCR, pstcNfcInit->u32OpenPage); + + /* Disable hardware ECC.*/ + WRITE_REG32(CM_NFC->IENR, 0x00000080UL); + + /* Clear flag.*/ + WRITE_REG32(CM_NFC->ISTR, 0x00000000UL); + + /* Set NFC base configure.*/ + u32RegVal = (pstcNfcInit->stcBaseConfig.u32CapacitySize | pstcNfcInit->stcBaseConfig.u32MemoryWidth | \ + pstcNfcInit->stcBaseConfig.u32BankNum | pstcNfcInit->stcBaseConfig.u32PageSize | \ + pstcNfcInit->stcBaseConfig.u32WriteProtect | pstcNfcInit->stcBaseConfig.u32EccMode | \ + pstcNfcInit->stcBaseConfig.u32RowAddrCycle | \ + (((uint32_t)pstcNfcInit->stcBaseConfig.u8SpareSizeForUserData) << NFC_BACR_SCS_POS)); + WRITE_REG32(CM_NFC->BACR, u32RegVal); + + /* Set NFC timing register 0.*/ + u32RegVal = ((pstcNfcInit->stcTimingReg0.u32TS << NFC_TMCR0_TS_POS) | \ + (pstcNfcInit->stcTimingReg0.u32TWP << NFC_TMCR0_TWP_POS) | \ + (pstcNfcInit->stcTimingReg0.u32TRP << NFC_TMCR0_TRP_POS) | \ + (pstcNfcInit->stcTimingReg0.u32TH << NFC_TMCR0_TH_POS)); + WRITE_REG32(CM_NFC->TMCR0, u32RegVal); + + /* Set NFC timing register 1.*/ + u32RegVal = ((pstcNfcInit->stcTimingReg1.u32TWH << NFC_TMCR1_TWH_POS) | \ + (pstcNfcInit->stcTimingReg1.u32TRH << NFC_TMCR1_TRH_POS) | \ + (pstcNfcInit->stcTimingReg1.u32TRR << NFC_TMCR1_TRR_POS) | \ + (pstcNfcInit->stcTimingReg1.u32TWB << NFC_TMCR1_TWB_POS)); + WRITE_REG32(CM_NFC->TMCR1, u32RegVal); + + /* Set NFC timing register 2.*/ + u32RegVal = ((pstcNfcInit->stcTimingReg2.u32TCCS << NFC_TMCR2_TCCS_POS) | \ + (pstcNfcInit->stcTimingReg2.u32TWTR << NFC_TMCR2_TWTR_POS) | \ + (pstcNfcInit->stcTimingReg2.u32TRTW << NFC_TMCR2_TRTW_POS) | \ + (pstcNfcInit->stcTimingReg2.u32TADL << NFC_TMCR2_TADL_POS)); + WRITE_REG32(CM_NFC->TMCR2, u32RegVal); + + /* De-select NFC bank */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EXMC_NFC function. + * @param None + * @retval None + */ +void EXMC_NFC_DeInit(void) +{ + WRITE_REG32(CM_NFC->BACR, 0x00002187UL); + WRITE_REG32(CM_NFC->IENR, 0x00000080UL); + WRITE_REG32(CM_NFC->ISTR, 0x00000000UL); + WRITE_REG32(CM_NFC->TMCR0, 0x03030202UL); + WRITE_REG32(CM_NFC->TMCR1, 0x28080303UL); + WRITE_REG32(CM_NFC->TMCR2, 0x03050D03UL); +} + +/** + * @brief Enable/disable NFC. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_NFC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->NFC_ENAR, PERIC_NFC_ENAR_NFCEN); + } else { + CLR_REG32_BIT(CM_PERIC->NFC_ENAR, PERIC_NFC_ENAR_NFCEN); + } +} + +/** + * @brief Enable/disable NFC ECC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_NFC_EccCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_NFC->IENR, NFC_IENR_ECCDIS); + } else { + SET_REG32_BIT(CM_NFC->IENR, NFC_IENR_ECCDIS); + } +} + +/** + * @brief Enable/disable NFC write protection function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_NFC->BACR, NFC_BACR_WP); + } else { + SET_REG32_BIT(CM_NFC->BACR, NFC_BACR_WP); + } +} + +/** + * @brief Enable or disable the specified NFC interrupt + * @param [in] u16IntType The specified interrupt + * This parameter can be any composed value of the macros group @ref EXMC_NFC_Interrupt + * @arg EXMC_NFC_INT_RB_BANK0: NFC bank 0 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK1: NFC bank 1 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK2: NFC bank 2 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK3: NFC bank 3 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_INT_RB_BANK5: NFC bank 5 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK6: NFC bank 6 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK7: NFC bank 7 device ready interrupt + * @arg EXMC_NFC_INT_ECC_ERROR: ECC error interrupt + * @arg EXMC_NFC_INT_ECC_CALC_COMPLETION: Calculating ECC completely interrupt + * @arg EXMC_NFC_INT_ECC_CORRECTABLE_ERR: ECC correctable error interrupt + * @arg EXMC_NFC_INT_ECC_UNCORRECTABLE_ERR: ECC uncorrectable error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_NFC_IntCmd(uint16_t u16IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EXMC_NFC_INT(u16IntType)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_NFC->IENR, u16IntType); + } else { + CLR_REG16_BIT(CM_NFC->IENR, u16IntType); + } +} + +/** + * @brief Get the specified flag status. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the macros group @ref EXMC_NFC_Flag + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @arg EXMC_NFC_FLAG_ECC_ERR: ECC error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculate ECC completely + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR: ECC uncorrectable error + * @arg EXMC_NFC_FLAG_ECC_CALCULATING: Calculating ECC + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus1 = RESET; + en_flag_status_t enStatus2 = RESET; + + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + if (0UL != (u32Flag & NFC_NFC_ISTR_MASK)) { + if (0UL != READ_REG32_BIT(CM_NFC->ISTR, (u32Flag & NFC_NFC_ISTR_MASK))) { + enStatus1 = SET; + } + } + + if (0UL != (u32Flag & EXMC_NFC_FLAG_ECC_CALCULATING)) { + if (0UL != READ_REG32_BIT(CM_PERIC->NFC_STSR, PERIC_NFC_STSR_PECC)) { + enStatus2 = SET; + } + } + + return (((SET == enStatus1) || (SET == enStatus2)) ? SET : RESET); +} + +/** + * @brief Clear the specified flag. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @arg EXMC_NFC_FLAG_ECC_ERR: ECC error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR: ECC uncorrectable error + * @retval None + */ +void EXMC_NFC_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_NFC->ISTR, u32Flag); +} + +/** + * @brief Get the interrupt result status. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @arg EXMC_NFC_FLAG_ECC_ERR: ECC error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR: ECC uncorrectable error + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_NFC->IRSR, u32Flag) > 0UL) ? SET : RESET); +} + +/** + * @brief Get the 1BIT ECC result of the specified section. + * @param [in] u32Section The specified section + * This parameter can be one of the macros group @ref EXMC_NFC_ECC_Section + * @arg EXMC_NFC_ECC_SECTION0: ECC section 0 + * @arg EXMC_NFC_ECC_SECTION1: ECC section 1 + * @arg EXMC_NFC_ECC_SECTION2: ECC section 2 + * @arg EXMC_NFC_ECC_SECTION3: ECC section 3 + * @arg EXMC_NFC_ECC_SECTION4: ECC section 4 + * @arg EXMC_NFC_ECC_SECTION5: ECC section 5 + * @arg EXMC_NFC_ECC_SECTION6: ECC section 6 + * @arg EXMC_NFC_ECC_SECTION7: ECC section 7 + * @arg EXMC_NFC_ECC_SECTION8: ECC section 8 + * @arg EXMC_NFC_ECC_SECTION9: ECC section 9 + * @arg EXMC_NFC_ECC_SECTION10: ECC section 10 + * @arg EXMC_NFC_ECC_SECTION11: ECC section 11 + * @arg EXMC_NFC_ECC_SECTION12: ECC section 12 + * @arg EXMC_NFC_ECC_SECTION13: ECC section 13 + * @arg EXMC_NFC_ECC_SECTION14: ECC section 14 + * @arg EXMC_NFC_ECC_SECTION15: ECC section 15 + * @retval Return one of the macros group @ref EXMC_NFC_1Bit_ECC_Result + * - EXMC_NFC_1BIT_ECC_NONE_ERR: None error + * - EXMC_NFC_1BIT_ECC_SINGLE_BIT_ERR: Single bit error + * - EXMC_NFC_1BIT_ECC_MULTIPLE_BITS_ERR: Multiple bit error + */ +uint32_t EXMC_NFC_Get1BitEccResult(uint32_t u32Section) +{ + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + return READ_REG32_BIT(NFC_ECCR_REG32(u32Section), (NFC_ECCR_SE | NFC_ECCR_ME)); +} + +/** + * @brief Get the 1BIT ECC error bit of the specified section. + * @param [in] u32Section The specified section + * This parameter can be one of the macros group @ref EXMC_NFC_ECC_Section + * @arg EXMC_NFC_ECC_SECTION0: ECC section 0 + * @arg EXMC_NFC_ECC_SECTION1: ECC section 1 + * @arg EXMC_NFC_ECC_SECTION2: ECC section 2 + * @arg EXMC_NFC_ECC_SECTION3: ECC section 3 + * @arg EXMC_NFC_ECC_SECTION4: ECC section 4 + * @arg EXMC_NFC_ECC_SECTION5: ECC section 5 + * @arg EXMC_NFC_ECC_SECTION6: ECC section 6 + * @arg EXMC_NFC_ECC_SECTION7: ECC section 7 + * @arg EXMC_NFC_ECC_SECTION8: ECC section 8 + * @arg EXMC_NFC_ECC_SECTION9: ECC section 9 + * @arg EXMC_NFC_ECC_SECTION10: ECC section 10 + * @arg EXMC_NFC_ECC_SECTION11: ECC section 11 + * @arg EXMC_NFC_ECC_SECTION12: ECC section 12 + * @arg EXMC_NFC_ECC_SECTION13: ECC section 13 + * @arg EXMC_NFC_ECC_SECTION14: ECC section 14 + * @arg EXMC_NFC_ECC_SECTION15: ECC section 15 + * @retval Return one of the macros group @ref EXMC_NFC_1Bit_ECC_Error_Bit_Location + * - EXMC_NFC_1BIT_ECC_ERR_BIT0: Bit0 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT1: Bit1 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT2: Bit2 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT3: Bit3 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT4: Bit4 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT5: Bit5 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT6: Bit6 error + * - EXMC_NFC_1BIT_ECC_ERR_BIT7: Bit7 error + */ +uint32_t EXMC_NFC_Get1BitEccErrBitLocation(uint32_t u32Section) +{ + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + return READ_REG32_BIT(NFC_ECCR_REG32(u32Section), NFC_1BIT_ECC_ERR_BIT_MASK); +} + +/** + * @brief Get the 1BIT ECC error byte of the specified section. + * @param [in] u32Section The specified section + * This parameter can be one of the macros group @ref EXMC_NFC_ECC_Section + * @arg EXMC_NFC_ECC_SECTION0: ECC section 0 + * @arg EXMC_NFC_ECC_SECTION1: ECC section 1 + * @arg EXMC_NFC_ECC_SECTION2: ECC section 2 + * @arg EXMC_NFC_ECC_SECTION3: ECC section 3 + * @arg EXMC_NFC_ECC_SECTION4: ECC section 4 + * @arg EXMC_NFC_ECC_SECTION5: ECC section 5 + * @arg EXMC_NFC_ECC_SECTION6: ECC section 6 + * @arg EXMC_NFC_ECC_SECTION7: ECC section 7 + * @arg EXMC_NFC_ECC_SECTION8: ECC section 8 + * @arg EXMC_NFC_ECC_SECTION9: ECC section 9 + * @arg EXMC_NFC_ECC_SECTION10: ECC section 10 + * @arg EXMC_NFC_ECC_SECTION11: ECC section 11 + * @arg EXMC_NFC_ECC_SECTION12: ECC section 12 + * @arg EXMC_NFC_ECC_SECTION13: ECC section 13 + * @arg EXMC_NFC_ECC_SECTION14: ECC section 14 + * @arg EXMC_NFC_ECC_SECTION15: ECC section 15 + * @retval Return the 1BIT ECC error byte. + */ +uint32_t EXMC_NFC_Get1BitEccErrByteLocation(uint32_t u32Section) +{ + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + return (READ_REG32_BIT(NFC_ECCR_REG32(u32Section), NFC_ECCR_ERRLOC) >> NFC_1BIT_ECC_ERR_BYTE_POS); +} + +/** + * @brief Set NFC spare area size. + * @param [in] u8SpareSizeForUserData NFC spare area size for user data + * @retval None + */ +void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData) +{ + MODIFY_REG32(CM_NFC->BACR, NFC_BACR_SCS, ((((uint32_t)u8SpareSizeForUserData) << NFC_BACR_SCS_POS) & NFC_BACR_SCS)); +} + +/** + * @brief Set NFC ECC mode. + * @param [in] u32EccMode ECC mode + * This parameter can be one of the macros group @ref EXMC_NFC_ECC_Mode + * @arg EXMC_NFC_1BIT_ECC: 1 bit ECC + * @arg EXMC_NFC_4BIT_ECCS: 4 bit ECC + * @retval None + */ +void EXMC_NFC_SetEccMode(uint32_t u32EccMode) +{ + DDL_ASSERT(IS_EXMC_NFC_ECC_MD(u32EccMode)); + + MODIFY_REG32(CM_NFC->BACR, NFC_BACR_ECCM, u32EccMode); +} + +/** + * @brief Get the 4 bits ECC syndrome register value. + * @param [in] u32Section The syndrome section + * This parameter can be one of the macros group @ref EXMC_NFC_ECC_Section + * @arg EXMC_NFC_ECC_SECTION0: ECC section 0 + * @arg EXMC_NFC_ECC_SECTION1: ECC section 1 + * @arg EXMC_NFC_ECC_SECTION2: ECC section 2 + * @arg EXMC_NFC_ECC_SECTION3: ECC section 3 + * @arg EXMC_NFC_ECC_SECTION4: ECC section 4 + * @arg EXMC_NFC_ECC_SECTION5: ECC section 5 + * @arg EXMC_NFC_ECC_SECTION6: ECC section 6 + * @arg EXMC_NFC_ECC_SECTION7: ECC section 7 + * @arg EXMC_NFC_ECC_SECTION8: ECC section 8 + * @arg EXMC_NFC_ECC_SECTION9: ECC section 9 + * @arg EXMC_NFC_ECC_SECTION10: ECC section 10 + * @arg EXMC_NFC_ECC_SECTION11: ECC section 11 + * @arg EXMC_NFC_ECC_SECTION12: ECC section 12 + * @arg EXMC_NFC_ECC_SECTION13: ECC section 13 + * @arg EXMC_NFC_ECC_SECTION14: ECC section 14 + * @arg EXMC_NFC_ECC_SECTION15: ECC section 15 + * @param [out] au16Synd The syndrome value + * @param [in] u8Len The length to be read(unit: half-word) + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer au16Synd value is NULL or u8Len is out of range. + * @note u8Len value don't be greater than 8 + */ +int32_t EXMC_NFC_GetSyndrome(uint32_t u32Section, uint16_t au16Synd[], uint8_t u8Len) +{ + uint8_t i; + uint32_t u32SyndVal; + uint8_t u8LoopWords; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != au16Synd) && (u8Len <= NFC_SYND_MAX_LEN)) { + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + u8LoopWords = (u8Len >> 1U); + for (i = 0U; i < u8LoopWords; i++) { + u32SyndVal = READ_REG32(NFC_SYND_REG32(u32Section, i)); + RW_MEM16(&au16Synd[i * 2U]) = (uint16_t)(u32SyndVal); + RW_MEM16(&au16Synd[i * 2U + 1U ]) = (uint16_t)(u32SyndVal >> 16U); + } + + if ((u8Len % 2U) != 0U) { + u32SyndVal = READ_REG32(NFC_SYND_REG32(u32Section, i)); + RW_MEM16(&au16Synd[i * 2U]) = (uint16_t)(u32SyndVal); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Read NFC device status + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @retval NFC device status + */ +uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank) +{ + uint32_t u32Status; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + /* Write 0x81000M70 to NFC_CMDR, M = bank number */ + WRITE_REG32(CM_NFC->CMDR, CMD_READ_STATUS(u32Bank)); + + u32Status = READ_REG32(CM_NFC->DATR_BASE); + + EXMC_NFC_DeselectChip(); + + return u32Status; +} + +/** + * @brief Read status enhanced + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32RowAddr The row address + * @retval NFC device status enhanced + */ +uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank, uint32_t u32RowAddr) +{ + uint32_t u32Status; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + /* Erase block step: + 1. Write 0x81000M78 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Read Data Register */ + WRITE_REG32(CM_NFC->CMDR, CMD_READ_STATUS_ENHANCED(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddr)); + + u32Status = READ_REG32(CM_NFC->DATR_BASE); + + EXMC_NFC_DeselectChip(); + + return u32Status; +} + +/** + * @brief Reset NFC device + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset step: + 1. Write 0x00000MFF to NFC_CMDR, M = bank number + 2. Wait RB signal until high level */ + WRITE_REG32(CM_NFC->CMDR, CMD_RESET(u32Bank)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + + EXMC_NFC_DeselectChip(); + + return i32Ret; +} + +/** + * @brief Asynchronous reset + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset step: + 1. Write 0x00000MFC to NFC_CMDR, M = bank number + 2. Wait RB signal until high level */ + WRITE_REG32(CM_NFC->CMDR, CMD_ASYNC_RESET(u32Bank)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + EXMC_NFC_DeselectChip(); + return i32Ret; +} + +/** + * @brief Reset lun of NFC device + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32RowAddr The row address + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_ResetLun(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset lun step: + 1. Write 0x82000MFA to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Wait RB signal until high level */ + WRITE_REG32(CM_NFC->CMDR, CMD_RESET_LUN(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddr)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + return i32Ret; +} + +/** + * @brief Read ID + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32IdAddr The address + * @param [in] au8DevId The id buffer + * @param [in] u32NumBytes The number of bytes to read + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Read timeout. + * - LL_ERR_INVD_PARAM: The pointer au8DevId value is NULL or u32NumBytes value is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_ReadId(uint32_t u32Bank, uint32_t u32IdAddr, + uint8_t au8DevId[], uint32_t u32NumBytes, uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Value; + const uint32_t u32LoopWords = u32NumBytes / 4UL; + const uint32_t u32RemainBytes = u32NumBytes % 4UL; + uint32_t u32TmpId; + uint32_t u32CapacityIndex; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != au8DevId) && (u32NumBytes > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(u32IdAddr <= 0xFFUL); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERR | EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_ERR); + + /* 1. Write 0x00000000 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_RD_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + u64Value = (NFC_IDXR_VAL(u32Bank, 0UL, 0UL, u32CapacityIndex) & NFC_IDXR_MASK); + WRITE_REG32(CM_NFC->IDXR0, (uint32_t)(u64Value & 0xFFFFFFFFUL)); + WRITE_REG32(CM_NFC->IDXR1, (uint32_t)(u64Value >> 32U)); + + /* 3. Write 0x000000E0 to NFC_CMDR */ + WRITE_REG32(CM_NFC->CMDR, EXMC_NFC_CMD_RD_2ND); + + /* 4. Wait RB signal until high level */ + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + if (LL_OK == i32Ret) { + /* Read Id step: + 1. Write 0x81000M90 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB=ID address + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(CM_NFC->CMDR, CMD_READ_ID(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_READ_ID_ADDR(u32Bank, u32IdAddr)); + for (i = 0UL; i < u32LoopWords; i++) { + u32TmpId = NFC_DATR_REG32(i); + (void)memcpy(&au8DevId[i * 4UL], &u32TmpId, 4UL); + } + + if (u32RemainBytes > 0UL) { + u32TmpId = NFC_DATR_REG32(i); + (void)memcpy(&au8DevId[i * 4UL], &u32TmpId, u32RemainBytes); + } + + i32Ret = LL_OK; + } + + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief Read Unique ID + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] au32UniqueId The id buffer + * @param [in] u8NumWords The number of words to read + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Read timeout. + * - LL_ERR_INVD_PARAM: The pointer au32UniqueId value is NULL or u8NumWords value is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +int32_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank, uint32_t au32UniqueId[], uint8_t u8NumWords, uint32_t u32Timeout) +{ + uint8_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != au32UniqueId) && (u8NumWords > 0U)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Read Id step: + 1. Write 0x81000M90 to NFC_CMDR, M = bank number + 2. Write 0x40000M00 to NFC_CMDR, M = bank number, AB=ID address + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(CM_NFC->CMDR, CMD_READ_UNIQUEID(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_READ_UNIQUEID_ADDR(u32Bank)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + if (LL_OK == i32Ret) { + for (i = 0U; i < u8NumWords; i++) { + au32UniqueId[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief Read parameter page + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] au32Data The data buffer + * @param [in] u16NumWords The number of words to read + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Read timeout. + * - LL_ERR_INVD_PARAM: The pointer au32Data value is NULL or u16NumWords value is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank, + uint32_t au32Data[], uint16_t u16NumWords, uint32_t u32Timeout) +{ + uint16_t i; + int32_t i32Ret = LL_ERR; + + if ((NULL != au32Data) && (u16NumWords > 0U)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Read parameter page step: + 1. Write 0x81000MEC to NFC_CMDR, M = bank number + 2. Write 0x40000M00 to NFC_CMDR, M = bank number + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(CM_NFC->CMDR, CMD_READ_PARAMETER_PAGE(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_READ_PARAMETER_PAGE_ADDR(u32Bank)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + if (LL_OK == i32Ret) { + for (i = 0U; i < u16NumWords; i++) { + au32Data[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief Set feature + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u8FeatrueAddr The featrue address + * @param [in] au32Data The data buffer + * @param [in] u8NumWords The number of words to set + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Set timeout. + * - LL_ERR_INVD_PARAM: The pointer au32Data value is NULL or u8NumWords value is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_SetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr, + const uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout) +{ + uint8_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != au32Data) && (u8NumWords > 0U)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + WRITE_REG32(CM_NFC->CMDR, CMD_SET_FEATURE(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_SET_FEATURE_ADDR(u32Bank, u8FeatrueAddr)); + + for (i = 0U; i < u8NumWords; i++) { + NFC_DATR_REG32(i) = au32Data[i]; + } + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief Get feature + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u8FeatrueAddr The featrue address + * @param [out] au32Data The data buffer + * @param [in] u8NumWords The number of words to get + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Get timeout. + * - LL_ERR_INVD_PARAM: The pointer au32Data value is NULL or u8NumWords value is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_GetFeature(uint32_t u32Bank, uint8_t u8FeatrueAddr, + uint32_t au32Data[], uint8_t u8NumWords, uint32_t u32Timeout) +{ + uint8_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != au32Data) && (u8NumWords > 0U)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + WRITE_REG32(CM_NFC->CMDR, CMD_GET_FEATURE(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_GET_FEATURE_ADDR(u32Bank, u8FeatrueAddr)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + if (LL_OK == i32Ret) { + for (i = 0U; i < u8NumWords; i++) { + au32Data[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return i32Ret; +} + +/** + * @brief Erase NFC device block + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32RowAddr The row address + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Erase timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT. + */ +int32_t EXMC_NFC_EraseBlock(uint32_t u32Bank, uint32_t u32RowAddr, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Erase block step: + 1. Write 0x81000M60 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Write 0x00000MD0 to NFC_CMDR, M = bank number + 6. Wait RB signal until high level */ + WRITE_REG32(CM_NFC->CMDR, CMD_ERASE_BLOCK_1ST_CYCLE(u32Bank)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddr)); + WRITE_REG32(CM_NFC->CMDR, CMD_ERASE_BLOCK_2ND_CYCLE(u32Bank)); + + i32Ret = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), SET, u32Timeout); + return i32Ret; +} + +/** + * @brief NFC page read + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [out] pu8Data The buffer for reading + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer pu8Data value value is NULL or u32NumBytes is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +int32_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank, uint32_t u32Page, uint8_t *pu8Data, + uint32_t u32NumBytes, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(pu8Data)); + + i32Ret = EXMC_NFC_Read(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes / 4UL), DISABLE, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief NFC page write + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] pu8Data The buffer for writing + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer pu8Data value is NULL or u32NumBytes is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +int32_t EXMC_NFC_WritePageMeta(uint32_t u32Bank, uint32_t u32Page, + const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(pu8Data)); + + i32Ret = EXMC_NFC_Write(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes / 4UL), DISABLE, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief NFC page read by hardware ECC + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [out] pu8Data The buffer for reading + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer pu8Data value is NULL or u32NumBytes is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +int32_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank, uint32_t u32Page, + uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; +#ifdef __DEBUG + const uint32_t u32PageSize = NFC_PAGE_SIZE; + const uint32_t u32SpareSizeUserData = NFC_SPARE_SIZE_FOR_USER_DATA; +#endif + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(pu8Data)); + DDL_ASSERT(u32NumBytes <= (u32PageSize + u32SpareSizeUserData)); + + i32Ret = EXMC_NFC_Read(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes / 4UL), ENABLE, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief NFC page write by hardware ECC + * @param [in] u32Bank The specified bank + * This parameter can be one of the macros group @ref EXMC_NFC_Bank + * @arg EXMC_NFC_BANK0: NFC device bank 0 + * @arg EXMC_NFC_BANK1: NFC device bank 1 + * @arg EXMC_NFC_BANK2: NFC device bank 2 + * @arg EXMC_NFC_BANK3: NFC device bank 3 + * @arg EXMC_NFC_BANK4: NFC device bank 4 + * @arg EXMC_NFC_BANK5: NFC device bank 5 + * @arg EXMC_NFC_BANK6: NFC device bank 6 + * @arg EXMC_NFC_BANK7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] pu8Data The buffer for writing + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value(Max value @ref EXMC_NFC_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Write timeout. + * - LL_ERR_INVD_PARAM: The pointer pu8Data value is NULL or u32NumBytes is 0. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +int32_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank, uint32_t u32Page, + const uint8_t *pu8Data, uint32_t u32NumBytes, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; +#ifdef __DEBUG + const uint32_t u32PageSize = NFC_PAGE_SIZE; + const uint32_t u32SpareSizeUserData = NFC_SPARE_SIZE_FOR_USER_DATA; +#endif + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) { + DDL_ASSERT(IS_EXMC_NFC_BANK(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD((uint32_t)pu8Data)); + DDL_ASSERT(u32NumBytes <= (u32PageSize + u32SpareSizeUserData)); + + i32Ret = EXMC_NFC_Write(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes / 4UL), ENABLE, u32Timeout); + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_NFC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c new file mode 100644 index 0000000000..d4fedefdab --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c @@ -0,0 +1,405 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.c + * @brief This file provides firmware functions to manage the OTS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_ots.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_OTS OTS + * @brief OTS Driver Library + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Macros OTS Local Macros + * @{ + */ + +/** + * @defgroup OTS_Configuration_Bit_Mask OTS Configuration Bit Mask + * @{ + */ +#define OTS_CTL_INIT_MSK (OTS_CTL_OTSCK | OTS_CTL_TSSTP) +/** + * @} + */ + +/** + * @defgroup OTS_Ext_Reg_Address OTS Extension Register Address + * @{ + */ +#define OTS_PDR1_ADDR ((uint32_t)(&CM_OTS->PDR1)) +#define OTS_PDR2_ADDR ((uint32_t)(&CM_OTS->PDR2)) +#define OTS_PDR3_ADDR ((uint32_t)(&CM_OTS->PDR3)) +/** + * @} + */ + +/** + * @defgroup OTS_Factor OTS Factor + * @{ + */ +#define OTS_DR1_FACTOR (1.7F) + +#define OTS_DR2_FACTOR (1.0F) +#define OTS_ECR_XTAL_FACTOR (1.0F) +/** + * @} + */ + +/** + * @defgroup OTS_Check_Parameters_Validity OTS check parameters validity + * @{ + */ +#define IS_OTS_CLK(x) (((x) == OTS_CLK_HRC) || ((x) == OTS_CLK_XTAL)) + +#define IS_OTS_AUTO_OFF_EN(x) (((x) == OTS_AUTO_OFF_DISABLE) || ((x) == OTS_AUTO_OFF_ENABLE)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Variables OTS Local Variables + * @{ + */ +static float32_t m_f32SlopeK = 0.0F; +static float32_t m_f32OffsetM = 0.0F; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup OTS_Local_Functions OTS Local Functions + * @{ + */ +/** + * @brief Get built-in slope K and offset M. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval None + */ +static void OTS_GetDfltPara(const stc_ots_init_t *pstcOTSInit) +{ +#define OTS_SCAL_T1 (ai8Temp[pstcOTSInit->stcParaCond.u8T1]) +#define OTS_SCAL_T2 (ai8Temp[pstcOTSInit->stcParaCond.u8T2]) +#define OTS_SCAL_A1 (af32A[0U]) +#define OTS_SCAL_A2 (af32A[1U]) + + uint8_t i; + int8_t ai8Temp[] = {-40, 25, 125}; + uint32_t au32PDRAddr[3U]; + uint32_t au32PDR[2U]; + uint16_t u16D1; + uint16_t u16D2; + uint32_t u32PDRAddrT1; + uint32_t u32PDRAddrT2; + float32_t f32D1; + float32_t f32D2; + float32_t af32A[2U]; + float32_t f32Ehrc = OTS_ECR_XTAL_FACTOR; + float32_t f32ClkFactor = (float32_t)pstcOTSInit->stcParaCond.u16ClockFreq / 8.0F; + + /* Intermediate variables: avoid misrac2012-13.2_c, 13.1 */ + au32PDRAddr[0U] = OTS_PDR3_ADDR; + au32PDRAddr[1U] = OTS_PDR1_ADDR; + au32PDRAddr[2U] = OTS_PDR2_ADDR; + u32PDRAddrT1 = au32PDRAddr[pstcOTSInit->stcParaCond.u8T1]; + u32PDRAddrT2 = au32PDRAddr[pstcOTSInit->stcParaCond.u8T2]; + + au32PDR[0U] = RW_MEM32(u32PDRAddrT1); + au32PDR[1U] = RW_MEM32(u32PDRAddrT2); + + if (pstcOTSInit->u16ClockSrc == OTS_CLK_HRC) { + f32Ehrc = (float32_t)pstcOTSInit->stcParaCond.u16ClockFreq / 0.032768F; + } + + for (i = 0U; i < 2U; i++) { + u16D1 = (uint16_t)au32PDR[i]; + u16D2 = (uint16_t)(au32PDR[i] >> 16U); + f32D1 = ((float32_t)u16D1) * f32ClkFactor; + f32D2 = ((float32_t)u16D2) * f32ClkFactor; + af32A[i] = ((OTS_DR1_FACTOR / f32D1) - (OTS_DR2_FACTOR / f32D2)) * f32Ehrc; + } + m_f32SlopeK = ((float32_t)OTS_SCAL_T2 - (float32_t)OTS_SCAL_T1) / (OTS_SCAL_A2 - OTS_SCAL_A1); + m_f32OffsetM = (float32_t)OTS_SCAL_T2 - (m_f32SlopeK * OTS_SCAL_A2); +} +/** + * @} + */ + +/** + * @defgroup OTS_Global_Functions OTS Global Functions + * @{ + */ + +/** + * @brief Initializes OTS according to the specified parameters in the structure stc_ots_init_t. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + DDL_ASSERT(IS_OTS_CLK(pstcOTSInit->u16ClockSrc)); + DDL_ASSERT(IS_OTS_AUTO_OFF_EN(pstcOTSInit->u16AutoOffEn)); + + /* Stop OTS sampling. */ + OTS_Stop(); + WRITE_REG16(CM_OTS->CTL, (pstcOTSInit->u16ClockSrc | pstcOTSInit->u16AutoOffEn)); + if ((pstcOTSInit->f32SlopeK == 0.0F) && (pstcOTSInit->f32OffsetM == 0.0F)) { + OTS_GetDfltPara(pstcOTSInit); + } else { + m_f32SlopeK = pstcOTSInit->f32SlopeK; + m_f32OffsetM = pstcOTSInit->f32OffsetM; + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for OTS initialization structure. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + pstcOTSInit->u16ClockSrc = OTS_CLK_HRC; + pstcOTSInit->f32SlopeK = 0.0F; + pstcOTSInit->f32OffsetM = 0.0F; + pstcOTSInit->u16AutoOffEn = OTS_AUTO_OFF_ENABLE; + pstcOTSInit->stcParaCond.u16ClockFreq = 8U; + pstcOTSInit->stcParaCond.u8T1 = OTS_PARAM_TEMP_COND_T25; + pstcOTSInit->stcParaCond.u8T2 = OTS_PARAM_TEMP_COND_T125; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initializes OTS peripheral. Reset the registers of OTS. + * @param None + * @retval None + */ +void OTS_DeInit(void) +{ + /* Stop OTS. */ + OTS_Stop(); + /* Set the value of all registers to the reset value. */ + WRITE_REG16(CM_OTS->CTL, 0U); + WRITE_REG16(CM_OTS->DR1, 0U); + WRITE_REG16(CM_OTS->DR2, 0U); + WRITE_REG16(CM_OTS->ECR, 0U); +} + +/** + * @brief Get temperature via normal mode. + * @param [out] pf32Temp Pointer to a float32_t type address that the temperature value to be stored. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pf32Temp == NULL. + */ +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pf32Temp != NULL) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + *pf32Temp = OTS_CalculateTemp(); + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + } + + return i32Ret; +} + +/** + * @brief Enable or disable the OTS interrutp. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void OTS_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_OTS->CTL_b.OTSIE, enNewState); +} + +/** + * @brief OTS scaling experiment. Get the value of the data register at the specified temperature to calculate K and M. + * @param [out] pu16Dr1: Pointer to an address to store the value of data register 1. + * @param [out] pu16Dr2: Pointer to an address to store the value of data register 2. + * @param [out] pu16Ecr: Pointer to an address to store the value of register ECR. + * @param [out] pf32A: Pointer to an address to store the parameter A. + * @param [in] u32Timeout: Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - pu16Dr1 == NULL. + * - pu16Dr2 == NULL. + * - pu16Ecr == NULL. + * - pf32A == NULL. + */ +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + + if (i32Ret == LL_OK) { + *pu16Dr1 = READ_REG16(CM_OTS->DR1); + *pu16Dr2 = READ_REG16(CM_OTS->DR2); + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_HRC) { + *pu16Ecr = READ_REG16(CM_OTS->ECR); + f32Ecr = (float32_t)(*pu16Ecr); + } else { + *pu16Ecr = 1U; + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + *pf32A = ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate the temperature value. + * @param None + * @retval A float32_t type value of temperature. + */ +float32_t OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0F; + uint16_t u16Dr1 = READ_REG16(CM_OTS->DR1); + uint16_t u16Dr2 = READ_REG16(CM_OTS->DR2); + uint16_t u16Ecr = READ_REG16(CM_OTS->ECR); + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_XTAL) { + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + f32Ret = m_f32SlopeK * ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c new file mode 100644 index 0000000000..ac1f866db3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c @@ -0,0 +1,1289 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.c + * @brief This file provides firmware functions to manage the Power Control(PWC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_pwc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_PWC PWC + * @brief Power Control Driver Library + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Macros PWC Local Macros + * @{ + */ + +/* Get the backup register address of PWC */ +#define PWC_BKRx(x) ((uint32_t)(&(CM_PWC->BKR0)) + ((uint32_t)(x) << 2U)) + +#define PWC_MD_SWITCH_TIMEOUT (30UL) +#define PWC_MD_SWITCH_TIMEOUT2 (0x1000UL) + +#define PWC_LVD_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EN_BIT (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_EXT_INPUT_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EXT_INPUT_EN_BIT (PWC_PVDCR0_EXVCCINEN) +#define PWC_LVD_CMP_OUTPUT_EN_REG (CM_PWC->PVDCR1) +#define PWC_LVD_CMP_OUTPUT_EN_BIT (PWC_PVDCR1_PVD1CMPOE) +#define PWC_LVD_FILTER_EN_REG (CM_PWC->PVDFCR) +#define PWC_LVD_FILTER_EN_BIT (PWC_PVDFCR_PVD1NFDIS) +#define PWC_LVD_STATUS_REG (CM_PWC->PVDDSR) + +#define PWC_LVD2_POS (4U) +#define PWC_LVD_BIT_OFFSET(x) ((uint8_t)((x) * PWC_LVD2_POS)) +#define PWC_LVD_EN_BIT_OFFSET(x) (x) + +#define PWC_RAM_MASK (PWC_RAMPC0_RAMPDC0 | PWC_RAMPC0_RAMPDC1 | \ + PWC_RAMPC0_RAMPDC2 | PWC_RAMPC0_RAMPDC3 | \ + PWC_RAMPC0_RAMPDC4 | PWC_RAMPC0_RAMPDC5 | \ + PWC_RAMPC0_RAMPDC6 | PWC_RAMPC0_RAMPDC7 | \ + PWC_RAMPC0_RAMPDC8 | PWC_RAMPC0_RAMPDC9 | \ + PWC_RAMPC0_RAMPDC10) + +#define PWC_PRAM_MASK (PWC_RAM_PD_CAN1 | PWC_RAM_PD_CAN2 | \ + PWC_RAM_PD_ETHERRX | PWC_RAM_PD_CACHE | \ + PWC_RAM_PD_SDIO1 | PWC_RAM_PD_USBFS | \ + PWC_RAM_PD_SDIO2 | PWC_RAM_PD_USBHS | \ + PWC_RAM_PD_NFC | PWC_RAM_PD_ETHERTX) + +#define PWC_LVD_FLAG_MASK (PWC_LVD1_FLAG_MON | PWC_LVD1_FLAG_DETECT | \ + PWC_LVD2_FLAG_MON | PWC_LVD2_FLAG_DETECT) + +#define PWC_LVD_EXP_NMI_POS (8U) + +/** + * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity + * @{ + */ + +/* Check PWC register lock status. */ +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +/* Check PWC LVD register lock status. */ +#define IS_PWC_LVD_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3) +/* Parameter validity check for EFM lock status. */ +#define IS_PWC_EFM_UNLOCKED() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for internal RAM setting of power mode control */ +#define IS_PWC_RAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_RAM_MASK) == PWC_RAM_MASK)) + +/* Parameter validity check for peripheral RAM setting of power mode control */ +#define IS_PWC_PRAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_PRAM_MASK) == PWC_PRAM_MASK)) + +/* Parameter validity check for RAM setting of MCU operating mode */ +#define IS_PWC_RAM_MD(x) \ +( ((x) == PWC_RAM_HIGH_SPEED) || \ + ((x) == PWC_RAM_ULOW_SPEED)) + +/* Parameter validity check for LVD channel. */ +#define IS_PWC_LVD_CH(x) \ +( ((x) == PWC_LVD_CH1) || \ + ((x) == PWC_LVD_CH2)) + +/* Parameter validity check for LVD function setting. */ +#define IS_PWC_LVD_EN(x) \ +( ((x) == PWC_LVD_ON) || \ + ((x) == PWC_LVD_OFF)) + +/* Parameter validity check for LVD compare output setting. */ +#define IS_PWC_LVD_CMP_EN(x) \ +( ((x) == PWC_LVD_CMP_ON) || \ + ((x) == PWC_LVD_CMP_OFF)) + +/* Parameter validity check for PWC LVD exception type. */ +#define IS_PWC_LVD_EXP_TYPE(x) \ +( ((x) == PWC_LVD_EXP_TYPE_NONE) || \ + ((x) == PWC_LVD_EXP_TYPE_INT) || \ + ((x) == PWC_LVD_EXP_TYPE_NMI) || \ + ((x) == PWC_LVD_EXP_TYPE_RST)) + +/* Parameter validity check for LVD digital noise filter function setting. */ +#define IS_PWC_LVD_FILTER_EN(x) \ +( ((x) == PWC_LVD_FILTER_ON) || \ + ((x) == PWC_LVD_FILTER_OFF)) + +/* Parameter validity check for LVD digital noise filter clock setting. */ +#define IS_PWC_LVD_FILTER_CLK(x) \ +( ((x) == PWC_LVD_FILTER_LRC_DIV1) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV2) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV4) || \ + ((x) == PWC_LVD_FILTER_LRC_MUL2)) + +/* Parameter validity check for LVD detect voltage setting. */ +#define IS_PWC_LVD_THRESHOLD_VOLTAGE(x) \ +( ((x) == PWC_LVD_THRESHOLD_LVL0) || \ + ((x) == PWC_LVD_THRESHOLD_LVL1) || \ + ((x) == PWC_LVD_THRESHOLD_LVL2) || \ + ((x) == PWC_LVD_THRESHOLD_LVL3) || \ + ((x) == PWC_LVD_THRESHOLD_LVL4) || \ + ((x) == PWC_LVD_THRESHOLD_LVL5) || \ + ((x) == PWC_LVD_THRESHOLD_LVL6) || \ + ((x) == PWC_LVD_THRESHOLD_LVL7)) + +/* Parameter validity check for LVD NMI function setting. */ +#define IS_PWC_LVD_NMI(x) \ +( ((x) == PWC_LVD_INT_MASK) || \ + ((x) == PWC_LVD_INT_NONMASK)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_TRIG_EDGE(x) \ +( ((x) == PWC_LVD_TRIG_FALLING) || \ + ((x) == PWC_LVD_TRIG_RISING) || \ + ((x) == PWC_LVD_TRIG_BOTH)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_CLR_FLAG(x) \ +( ((x) == PWC_LVD1_FLAG_DETECT) || \ + ((x) == PWC_LVD2_FLAG_DETECT)) + +/* Parameter validity check for LVD flag. */ +#define IS_PWC_LVD_GET_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LVD_FLAG_MASK) == PWC_LVD_FLAG_MASK)) + +/* Parameter validity check for power down mode wakeup event with trigger. */ +#define IS_PWC_WAKEUP_TRIG_EVT(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_TRIG_ALL) == PWC_PD_WKUP_TRIG_ALL)) + +/* Parameter validity check for power down mode wakeup trigger edge. */ +#define IS_PWC_WAKEUP_TRIG(x) \ +( ((x) == PWC_PD_WKUP_TRIG_FALLING) || \ + ((x) == PWC_PD_WKUP_TRIG_RISING)) + +/* Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_FLAG_ALL) == PWC_PD_WKUP_FLAG_ALL)) + +/* Parameter validity check for stop mode drive capacity. */ +#define IS_PWC_STOP_DRV(drv) \ +( ((drv) == PWC_STOP_DRV_HIGH) || \ + ((drv) == PWC_STOP_DRV_LOW)) + +/* Parameter validity check for clock setting after wake-up from stop mode. */ +#define IS_PWC_STOP_CLK(x) \ +( ((x) == PWC_STOP_CLK_KEEP) || \ + ((x) == PWC_STOP_CLK_MRC)) + +/* Parameter validity check for flash wait setting after wake-up from stop mode. */ +#define IS_PWC_STOP_FLASH_WAIT(x) \ +( ((x)== PWC_STOP_FLASH_WAIT_ON) || \ + ((x)== PWC_STOP_FLASH_WAIT_OFF)) + +/* Parameter validity check for ex-bus setting in stop mode. */ +#define IS_PWC_STOP_EXBUS(x) \ +( ((x)== PWC_STOP_EXBUS_HIZ) || \ + ((x)== PWC_STOP_EXBUS_HOLD)) + +/* Parameter validity check for power monitor sel. */ +#define IS_PWC_PWR_MON_SEL(x) \ +( ((x) == PWC_PWR_MON_IREF) || \ + ((x) == PWC_PWR_MON_VBAT_DIV2)) + +/* Parameter validity check for VBAT Reference Voltage. */ +#define IS_PWC_VBAT_REF_VOL(x) \ +( ((x) == PWC_VBAT_REF_VOL_2P1V) || \ + ((x) == PWC_VBAT_REF_VOL_1P8V)) + +/* Parameter validity check for BACKUP RAM Flag. */ +#define IS_PWC_BACKUP_RAM_FLAG(x) \ +( 0U != ((x) & (PWC_BACKUP_RAM_FLAG_RAMPDF | PWC_BACKUP_RAM_FLAG_RAMVALID))) + +/* Parameter validity check for Backup Register Number. */ +#define IS_PWC_BACKUP_REGISTER_NUMBER(x) ((x) <= 127U) + +#define IS_PWC_LDO_SEL(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LDO_MASK) == PWC_LDO_MASK)) + +/* Parameter validity check for WKT Clock Source. */ +#define IS_PWC_WKT_CLK_SRC(x) \ +( ((x)== PWC_WKT_CLK_SRC_64HZ) || \ + ((x)== PWC_WKT_CLK_SRC_XTAL32) || \ + ((x)== PWC_WKT_CLK_SRC_RTCLRC)) + +/* Parameter validity check for WKT Comparision Value. */ +#define IS_PWC_WKT_COMPARISION_VALUE(x) ((x) <= 0x0FFFU) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup PWC_Global_Functions PWC Global Functions + * @{ + */ +/** + * @brief Enter power down mode. + * @param None + * @retval None + */ +void PWC_PD_Enter(void) +{ + WRITE_REG16(CM_PWC->FPRC, PWC_UNLOCK_CODE1); + + CLR_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD2IRS); + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); +} + +/** + * @brief Enter stop mode. + * @param None + * @retval None + */ +void PWC_STOP_Enter(void) +{ + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); + +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval None + */ +void PWC_SLEEP_Enter(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); +} + +/** + * @brief Configure ram run mode. + * @param [in] u16Mode Specifies the mode to run. + * @arg PWC_RAM_HIGH_SPEED + * @arg PWC_RAM_ULOW_SPEED + * @retval None + */ +void PWC_RamModeConfig(uint16_t u16Mode) +{ + DDL_ASSERT(IS_PWC_RAM_MD(u16Mode)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->RAMOPM, u16Mode); +} + +/** + * @brief Initialize LVD config structure. Fill each pstcLvdInit with default value + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET LVD init structure parameters values */ + pstcLvdInit->u32State = PWC_LVD_OFF; + pstcLvdInit->u32CompareOutputState = PWC_LVD_CMP_OFF; + pstcLvdInit->u32ExceptionType = PWC_LVD_EXP_TYPE_NONE; + pstcLvdInit->u32Filter = PWC_LVD_FILTER_OFF; + pstcLvdInit->u32FilterClock = PWC_LVD_FILTER_LRC_MUL2; + pstcLvdInit->u32ThresholdVoltage = PWC_LVD_THRESHOLD_LVL0; + pstcLvdInit->u32TriggerEdge = PWC_LVD_TRIG_FALLING; + } + return i32Ret; +} + +/** + * @brief LVD configuration. + * @param [in] u8Ch LVD channel + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_EN(pstcLvdInit->u32State)); + DDL_ASSERT(IS_PWC_LVD_EXP_TYPE(pstcLvdInit->u32ExceptionType)); + DDL_ASSERT(IS_PWC_LVD_CMP_EN(pstcLvdInit->u32CompareOutputState)); + DDL_ASSERT(IS_PWC_LVD_FILTER_EN(pstcLvdInit->u32Filter)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(pstcLvdInit->u32FilterClock)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(pstcLvdInit->u32ThresholdVoltage)); + DDL_ASSERT(IS_PWC_LVD_TRIG_EDGE(pstcLvdInit->u32TriggerEdge)); + + /* disable filter function in advance */ + SET_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS << PWC_LVD_BIT_OFFSET(u8Ch))); + MODIFY_REG8(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32Filter | pstcLvdInit->u32FilterClock) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Config LVD threshold voltage */ + MODIFY_REG8(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32ThresholdVoltage << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Enable LVD */ + MODIFY_REG8(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch, pstcLvdInit->u32State << u8Ch); + /* Enable compare output */ + MODIFY_REG8(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1CMPOE << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32CompareOutputState << PWC_LVD_BIT_OFFSET(u8Ch)); + MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1EDGS << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32TriggerEdge << PWC_LVD_BIT_OFFSET(u8Ch)); + /* config PVDIRE & PWC_PVDCR1_PVD1IRS while PVDEN & PVDCMPOE enable */ + MODIFY_REG8(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32ExceptionType & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1NMIS << PWC_LVD_BIT_OFFSET(u8Ch), \ + ((pstcLvdInit->u32ExceptionType >> PWC_LVD_EXP_NMI_POS) & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + + } + return i32Ret; +} + +/** + * @brief Enable or disable LVD. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD external input. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note While enable external input, should choose PWC_LVD_CH2 to initialize, + * and threshold voltage must set PWC_LVD1_2V9_LVD2_1V1. + */ +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } else { + CLR_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD digital filter. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + SET_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] u32Clock Specifies filter clock. + * @arg PWC_LVD_FILTER_LRC_DIV4 + * @arg PWC_LVD_FILTER_LRC_DIV2 + * @arg PWC_LVD_FILTER_LRC_DIV1 + * @arg PWC_LVD_FILTER_LRC_MUL2 + * @retval None + */ +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(u32Clock)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + MODIFY_REG8(CM_PWC->PVDFCR, PWC_PVDFCR_PVD1NFCKS << PWC_LVD_BIT_OFFSET(u8Ch), \ + u32Clock << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] u32Voltage Specifies threshold voltage. @ref PWC_LVD_Detection_Voltage_Sel + * @retval None + * @note While PWC_LVD_CH2, PWC_LVD1_2V9_LVD2_1V1 only valid while EXTINPUT enable. + */ +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(u32Voltage)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)), \ + u32Voltage << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Get LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @retval An @ref en_flag_status_t enumeration value + + * @note PVDxDETFLG is avaliable when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1' + */ +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_GET_FLAG(u8Flag)); + return ((0x00U != READ_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag)) ? SET : RESET); +} + +/** + * @brief Clear LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @arg PWC_LVD1_FLAG_DETECT + * @arg PWC_LVD2_FLAG_DETECT + * @retval None + * @note PWC_LVD2_FLAG_DETECT only valid while HC32F460, HC32M423, HC32F451, HC32F452 + * PWC_LVD1_FLAG_DETECT could clear both LVD1 & LVD2 flag while HC32F4A0 + */ +void PWC_LVD_ClearStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CLR_FLAG(u8Flag)); + + if (PWC_LVD2_FLAG_DETECT == u8Flag) { + u8Flag = PWC_PVDDSR_PVD1DETFLG; + } + CLR_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag); +} + +/** + * @brief LDO(HRC & PLL) command. + * @param [in] u16Ldo Specifies the ldo to command. + * @arg PWC_LDO_PLL + * @arg PWC_LDO_HRC + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LDO_SEL(u16Ldo)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } else { + SET_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } +} + +/** + * @brief Switch high speed to ultra low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighSpeedToLowSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS, 0x01UL); + WRITE_REG8(CM_PWC->PWRC3, 0x00UL); + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DVS, PWC_PWRC2_DVS_1); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +int32_t PWC_LowSpeedToHighSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS, PWC_PWRC2_DDAS); + WRITE_REG8(CM_PWC->PWRC3, 0xFFUL); + SET_REG8_BIT(CM_PWC->PWRC2, PWC_PWRC2_DVS); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Ram area power down commond. + * @param [in] u32Ram Specifies whitch ram to operate. @ref PWC_PD_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_RAM_CONTROL(u32Ram)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CM_PWC->RAMPC0 |= u32Ram; + } else { + CM_PWC->RAMPC0 &= ~u32Ram; + } +} + +/** + * @brief Ram area power down commond. + * @param [in] u32PeriphRam Specifies whitch ram to operate. @ref PWC_PD_Periph_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_PRAM_CONTROL(u32PeriphRam)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CM_PWC->PRAMLPC |= u32PeriphRam; + } else { + CM_PWC->PRAMLPC &= ~u32PeriphRam; + } +} + +/** + * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPDModeConfig->u8IOState = PWC_PD_IO_KEEP1; + pstcPDModeConfig->u8Mode = PWC_PD_MD1; + pstcPDModeConfig->u8VcapCtrl = PWC_PD_VCAP_0P1UF; + } + return i32Ret; +} + +/** + * @brief Power down mode config structure. + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \ + (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8Mode)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_PDTS, pstcPDModeConfig->u8VcapCtrl << PWC_PWRC1_PDTS_POS); + } + return i32Ret; +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u32Event Wakeup Event. @ref PWC_WKUP_Event_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + uint8_t u8Event0 = (uint8_t)u32Event; + uint8_t u8Event1 = (uint8_t)(u32Event >> PWC_PD_WKUP1_POS); + uint8_t u8Event2 = (uint8_t)(u32Event >> PWC_PD_WKUP2_POS); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + SET_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + SET_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } else { + CLR_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + CLR_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + CLR_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } +} + +/** + * @brief Power down mode wake up event trigger config. + * @param [in] u8Event PVD and wakeup pin. @ref PWC_WKUP_Trigger_Event_Sel + * @param [in] u8TrigEdge The trigger edge. + * @arg PWC_PD_WKUP_TRIG_FALLING + * @arg PWC_PD_WKUP_TRIG_RISING + * @retval None + */ +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge) +{ + DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVT(u8Event)); + DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (PWC_PD_WKUP_TRIG_RISING == u8TrigEdge) { + SET_REG8_BIT(CM_PWC->PDWKES, u8Event); + } else { + CLR_REG8_BIT(CM_PWC->PDWKES, u8Event); + } +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = READ_REG8_BIT(CM_PWC->PDWKF0, u16Flag); + u8Flag1 = READ_REG8_BIT(CM_PWC->PDWKF1, (u16Flag >> PWC_PD_WKUP_FLAG1_POS)); + + return (((0U != u8Flag0) || (0U != u8Flag1)) ? SET : RESET); +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval None + */ +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = (uint8_t)u16Flag; + u8Flag1 = (uint8_t)(u16Flag >> PWC_PD_WKUP_FLAG1_POS); + + CLR_REG8_BIT(CM_PWC->PDWKF0, u8Flag0); + CLR_REG8_BIT(CM_PWC->PDWKF1, u8Flag1); +} + +/** + * @brief Stop mode config. + * @param [in] pstcStopConfig Chip config before entry stop mode. + * @arg u8StopDrv, MCU from which speed mode entry stop mode. + * @arg u16Clock, System clock setting after wake-up from stop mode. + * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode. + * @arg u16ExBusHold, ExBus status in stop mode. + * @retval int32_t: + * - LL_OK: Stop mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + DDL_ASSERT(IS_PWC_STOP_DRV(pstcStopConfig->u8StopDrv)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, pstcStopConfig->u8StopDrv); + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait)); + DDL_ASSERT(IS_PWC_STOP_EXBUS(pstcStopConfig->u16ExBusHold)); + + MODIFY_REG16(CM_PWC->STPMCR, (PWC_STPMCR_EXBUSOE | PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT), \ + (pstcStopConfig->u16ExBusHold | pstcStopConfig->u16Clock | pstcStopConfig->u16FlashWait)); + } + return i32Ret; +} + +/** + * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value + * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Stop down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcStopConfig->u16Clock = PWC_STOP_CLK_KEEP; + pstcStopConfig->u8StopDrv = PWC_STOP_DRV_HIGH; + pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT_ON; + pstcStopConfig->u16ExBusHold = PWC_STOP_EXBUS_HIZ; + } + return i32Ret; +} + +/** + * @brief Stop mode wake up clock config. + * @param [in] u8Clock System clock setting after wake-up from stop mode. + * @arg PWC_STOP_CLK_KEEP + * @arg PWC_STOP_CLK_MRC or PWC_STOP_CLK_HRC + * @retval None + * @note PWC_STOP_CLK_HRC only valid while HC32F160. + */ +void PWC_STOP_ClockSelect(uint8_t u8Clock) +{ + DDL_ASSERT(IS_PWC_STOP_CLK(u8Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC, (uint16_t)u8Clock); + +} + +/** + * @brief Stop mode wake up flash wait config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + MODIFY_REG8(CM_PWC->STPMCR, PWC_STPMCR_FLNWT, PWC_STOP_FLASH_WAIT_ON); + } else { + MODIFY_REG8(CM_PWC->STPMCR, PWC_STPMCR_FLNWT, PWC_STOP_FLASH_WAIT_OFF); + } +} + +/** + * @brief Stop mode ex-bus status config. + * @param [in] u16ExBusHold ExBus status in stop mode. + * @arg PWC_STOP_EXBUS_HIZ + * @arg PWC_STOP_EXBUS_HOLD + * @retval None + */ +void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold) +{ + DDL_ASSERT(IS_PWC_STOP_EXBUS(u16ExBusHold)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_EXBUSOE, u16ExBusHold); +} + +/** + * @brief Stop mode driver capacity config. + * @param [in] u8StopDrv Drive capacity while enter stop mode. + * @arg PWC_STOP_DRV_HIGH + * @arg PWC_STOP_DRV_LOW + * @retval None + */ +void PWC_STOP_SetDrv(uint8_t u8StopDrv) +{ + DDL_ASSERT(IS_PWC_STOP_DRV(u8StopDrv)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, u8StopDrv); +} + +/** + * @brief PWC power monitor command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This monitor power is used for ADC and output to REGC pin. + */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE); + } else { + CLR_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE); + } + +} + +/** + * @brief PWC power monitor voltage config. + * @param [in] u8VoltageSrc PWC power monitor voltage config @ref PWC_Monitor_Power. + * This parameter can be one of the following values + * @arg PWC_PWR_MON_IREF + * @arg PWC_PWR_MON_TSENSOR or PWC_PWR_MON_VBAT_DIV2 + * @retval None + * @note This monitor power is used for ADC and output to REGC pin. + * PWC_PWR_MON_VBAT_DIV2 is only valid while HC32F4A0. + */ +void PWC_SetPowerMonitorVoltageSrc(uint8_t u8VoltageSrc) +{ + DDL_ASSERT(IS_PWC_PWR_MON_SEL(u8VoltageSrc)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC4, PWC_PWRC4_ADBUFS, u8VoltageSrc); +} + +/** + * @brief VBAT monitor reference voltage selection. + * @param [in] u8RefVoltage VBAT monitor reference voltage. + * This parameter can be one of the following values: + * @arg PWC_VBAT_REF_VOL_1P8V: Vbat reference voltage is 1.8V + * @arg PWC_VBAT_REF_VOL_2P1V: Vbat reference voltage is 2.1V + * @retval None + */ +void PWC_VBAT_SetMonitorVoltage(uint8_t u8RefVoltage) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_VBAT_REF_VOL(u8RefVoltage)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bCM_PWC->PWRC4_b.VBATREFSEL, u8RefVoltage); +} + +/** + * @brief ENABLE or DISABLE VBAT monitor. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bCM_PWC->PWRC4_b.VBATME, enNewState); +} + +/** + * @brief Get VBAT voltage status. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + * - SET: Flag is set, VBAT < VBATREF + * - RESET: Flag is reset, VBAT > VBATREF + */ +en_flag_status_t PWC_VBAT_GetVoltageStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + return ((0UL != READ_REG32(bCM_PWC->PWRC4_b.VBATMON)) ? SET : RESET); +} + +/** + * @brief ENABLE or DISABLE VBAT voltage divide monitor. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_VBAT_VoltageDivMonitorCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bCM_PWC->VBATCR_b.VBATDIVMONE, enNewState); +} + +/** + * @brief RESET the VBAT area. + * @param None + * @retval None + */ +void PWC_VBAT_Reset(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + WRITE_REG8(CM_PWC->VBATRSTR, 0xA5U); +} + +/** + * @brief ENABLE or DISABLE VBAT power. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_VBAT_PowerCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bCM_PWC->VBATCR_b.CSDIS, enNewState); +} + +/** + * @brief ENABLE or DISABLE Backup RAM power. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_BKR_PowerCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + WRITE_REG32(bCM_PWC->VBATCR_b.VBTRSD, 0UL); + } else { + WRITE_REG32(bCM_PWC->VBATCR_b.VBTRSD, 1UL); + } +} + +/** + * @brief Get Backup RAM flag. + * @param [in] u8Flag Backup RAM flag. + * This parameter can be one or any combination of the following values: + * @arg PWC_BACKUP_RAM_FLAG_RAMPDF: Backup RAM power down flag + * @arg PWC_BACKUP_RAM_FLAG_RAMVALID: Backup RAM read/write flag + * @retval An @ref en_flag_status_t enumeration type value. enumeration value: + + */ +en_flag_status_t PWC_BKR_GetStatus(uint8_t u8Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_RAM_FLAG(u8Flag)); + + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (0U != (READ_REG8_BIT(CM_PWC->VBATCR, u8Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Write Backup register. + * @param [in] u8RegNum Backup register number. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 127. + * @param [in] u8RegVal Value written to register + * @retval None + */ +void PWC_BKR_Write(uint8_t u8RegNum, uint8_t u8RegVal) +{ + __IO uint8_t *BKR; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_REGISTER_NUMBER(u8RegNum)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + BKR = (__IO uint8_t *)PWC_BKRx(u8RegNum); + WRITE_REG8(*BKR, u8RegVal); +} + +/** + * @brief Read Backup register. + * @param [in] u8RegNum Backup register number. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 127. + * @retval uint8_t Register value + */ +uint8_t PWC_BKR_Read(uint8_t u8RegNum) +{ + uint8_t u8RegVal; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_REGISTER_NUMBER(u8RegNum)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + u8RegVal = READ_REG8(*((__IO uint8_t *)PWC_BKRx(u8RegNum))); + + return u8RegVal; +} + +/** + * @brief WKT Timer Initialize. + * @param [in] u16ClkSrc Clock source. + * This parameter can be one of the following values: + * @arg PWC_WKT_CLK_SRC_64HZ: 64Hz Clock + * @arg PWC_WKT_CLK_SRC_XTAL32: XTAL32 Clock + * @arg PWC_WKT_CLK_SRC_RTCLRC: RTCLRC Clock + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u16ClkSrc)); + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->WKTC2, PWC_WKTC2_WKCKS, u16ClkSrc); + WRITE_REG8(CM_PWC->WKTC0, (u16CmpVal & PWC_WKTC0_WKTMCMP)); + WRITE_REG8(CM_PWC->WKTC1, ((u16CmpVal >> 8U) & PWC_WKTC1_WKTMCMP)); +} + +/** + * @brief SET WKT Timer compare value. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + WRITE_REG8(CM_PWC->WKTC0, (u16CmpVal & PWC_WKTC0_WKTMCMP)); + WRITE_REG8(CM_PWC->WKTC1, ((u16CmpVal >> 8U) & PWC_WKTC1_WKTMCMP)); +} + +/** + * @brief Get WKT Timer compare value. + * @param None + * @retval uint16_t WKT Compara value + */ +uint16_t PWC_WKT_GetCompareValue(void) +{ + uint16_t u16CmpVal; + + u16CmpVal = (uint16_t)(READ_REG16_BIT(CM_PWC->WKTC1, PWC_WKTC1_WKTMCMP) << 8U); + u16CmpVal |= READ_REG8(CM_PWC->WKTC0); + + return u16CmpVal; +} + +/** + * @brief ENABLE or DISABLE WKT Timer. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_WKT_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bCM_PWC->WKTC2_b.WKTCE, enNewState); +} + +/** + * @brief Get WKT Timer count match flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. enumeration value: + + */ +en_flag_status_t PWC_WKT_GetStatus(void) +{ + en_flag_status_t enFlagState; + + enFlagState = (0U != READ_REG8_BIT(CM_PWC->WKTC2, PWC_WKTC2_WKOVF)) ? SET : RESET; + + return enFlagState; +} + +/** + * @brief Clear WKT Timer count match flag. + * @param None + * @retval None + */ +void PWC_WKT_ClearStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + CLR_REG8_BIT(CM_PWC->WKTC2, PWC_WKTC2_WKOVF); +} + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c new file mode 100644 index 0000000000..8d0cdb8fb2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c @@ -0,0 +1,471 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.c + * @brief This file provides firmware functions to manage the QSPI. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_qspi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_QSPI QSPI + * @brief QSPI Driver Library + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Macros QSPI Local Macros + * @{ + */ + +/* QSPI registers Mask */ +#define QSPI_CR_CLR_MASK (QSPI_CR_DIV | QSPI_CR_SPIMD3 | QSPI_CR_PFSAE | \ + QSPI_CR_PFE | QSPI_CR_MDSEL) +#define QSPI_FCR_CLR_MASK (QSPI_FCR_DUTY | QSPI_FCR_DMCYCN | QSPI_FCR_SSNLD | \ + QSPI_FCR_SSNHD | QSPI_FCR_FOUR_BIC | QSPI_FCR_AWSL) +#define QSPI_CUSTOM_MD_CLR_MASK (QSPI_CR_IPRSL | QSPI_CR_APRSL | QSPI_CR_DPRSL) + +/** + * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity + * @{ + */ + +#define IS_QSPI_CLK_DIV(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_CLK_DIV64) == QSPI_CLK_DIV64)) + +#define IS_QSPI_SPI_MD(x) \ +( ((x) == QSPI_SPI_MD0) || \ + ((x) == QSPI_SPI_MD3)) + +#define IS_QSPI_PREFETCH_MD(x) \ +( ((x) == QSPI_PREFETCH_MD_INVD) || \ + ((x) == QSPI_PREFETCH_MD_EDGE_STOP) || \ + ((x) == QSPI_PREFETCH_MD_IMMED_STOP)) + +#define IS_QSPI_READ_MD(x) \ +( ((x) == QSPI_RD_MD_STD_RD) || \ + ((x) == QSPI_RD_MD_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_STANDARD_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_FAST_RD)) + +#define IS_QSPI_DUMMY_CYCLE(x) (((x) | QSPI_DUMMY_CYCLE18) == QSPI_DUMMY_CYCLE18) + +#define IS_QSPI_ADDR_WIDTH(x) \ +( ((x) == QSPI_ADDR_WIDTH_8BIT) || \ + ((x) == QSPI_ADDR_WIDTH_16BIT) || \ + ((x) == QSPI_ADDR_WIDTH_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT)) + +#define IS_QSPI_QSSN_SETUP_TIME(x) \ +( ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK0P5) || \ + ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK1P5)) + +#define IS_QSPI_QSSN_RELEASE_TIME(x) \ +( ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK0P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK1P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK32) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK128) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_INFINITE)) + +#define IS_QSPI_QSSN_INTERVAL_TIME(x) ((x) <= QSPI_QSSN_INTERVAL_QSCK16) + +#define IS_QSPI_INSTR_PROTOCOL(x) \ +( ((x) == QSPI_INSTR_PROTOCOL_1LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_2LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_4LINE)) + +#define IS_QSPI_ADDR_PROTOCOL(x) \ +( ((x) == QSPI_ADDR_PROTOCOL_1LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_2LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_4LINE)) + +#define IS_QSPI_DATA_PROTOCOL(x) \ +( ((x) == QSPI_DATA_PROTOCOL_1LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_2LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_4LINE)) + +#define IS_QSPI_WP_PIN_LVL(x) \ +( ((x) == QSPI_WP_PIN_LOW) || \ + ((x) == QSPI_WP_PIN_HIGH)) + +#define IS_QSPI_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_ALL) == QSPI_FLAG_ALL)) + +#define IS_QSPI_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_CLR_ALL) == QSPI_FLAG_CLR_ALL)) + +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= (QSPI_EXAR_EXADR >> QSPI_EXAR_EXADR_POS)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Variable QSPI Local Variable + * @{ + */ + +/* Current read mode */ +static uint8_t m_u8ReadMode = 0U; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Functions QSPI Global Functions + * @{ + */ + +/** + * @brief De-initializes QSPI. + * @param None + * @retval None + */ +void QSPI_DeInit(void) +{ + WRITE_REG32(CM_QSPI->CR, 0x003F0000UL); + WRITE_REG32(CM_QSPI->CSCR, 0x0FUL); + WRITE_REG32(CM_QSPI->FCR, 0x80B3UL); + WRITE_REG32(CM_QSPI->CCMD, 0x0UL); + WRITE_REG32(CM_QSPI->XCMD, 0xFFUL); + WRITE_REG32(CM_QSPI->SR2, QSPI_FLAG_ROM_ACCESS_ERR); + WRITE_REG32(CM_QSPI->EXAR, 0UL); +} + +/** + * @brief Initialize QSPI. + * @param [in] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Duty = 0UL; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLK_DIV(pstcQspiInit->u32ClockDiv)); + DDL_ASSERT(IS_QSPI_SPI_MD(pstcQspiInit->u32SpiMode)); + DDL_ASSERT(IS_QSPI_PREFETCH_MD(pstcQspiInit->u32PrefetchMode)); + DDL_ASSERT(IS_QSPI_READ_MD(pstcQspiInit->u32ReadMode)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLE(pstcQspiInit->u32DummyCycle)); + DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcQspiInit->u32AddrWidth)); + DDL_ASSERT(IS_QSPI_QSSN_SETUP_TIME(pstcQspiInit->u32SetupTime)); + DDL_ASSERT(IS_QSPI_QSSN_RELEASE_TIME(pstcQspiInit->u32ReleaseTime)); + DDL_ASSERT(IS_QSPI_QSSN_INTERVAL_TIME(pstcQspiInit->u32IntervalTime)); + + /* Duty cycle compensation */ + if (0UL == (pstcQspiInit->u32ClockDiv & QSPI_CLK_DIV2)) { + u32Duty = QSPI_FCR_DUTY; + } + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_CLR_MASK, (pstcQspiInit->u32ClockDiv | pstcQspiInit->u32SpiMode | + pstcQspiInit->u32PrefetchMode | pstcQspiInit->u32ReadMode)); + WRITE_REG32(CM_QSPI->CSCR, ((pstcQspiInit->u32ReleaseTime >> 8U) | pstcQspiInit->u32IntervalTime)); + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_CLR_MASK, (pstcQspiInit->u32DummyCycle | pstcQspiInit->u32AddrWidth | + pstcQspiInit->u32SetupTime | (pstcQspiInit->u32ReleaseTime & 0xFFU) | u32Duty)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_qspi_init_t member with default value. + * @param [out] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: stc_qspi_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcQspiInit->u32ClockDiv = QSPI_CLK_DIV2; + pstcQspiInit->u32SpiMode = QSPI_SPI_MD0; + pstcQspiInit->u32PrefetchMode = QSPI_PREFETCH_MD_INVD; + pstcQspiInit->u32ReadMode = QSPI_RD_MD_STD_RD; + pstcQspiInit->u32DummyCycle = QSPI_DUMMY_CYCLE3; + pstcQspiInit->u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; + pstcQspiInit->u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5; + pstcQspiInit->u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK0P5; + pstcQspiInit->u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1; + } + + return i32Ret; +} + +/** + * @brief Set the level of WP pin. + * @param [in] u32Level The level value. + * This parameter can be one of the following values: + * @arg QSPI_WP_PIN_LOW: WP(QSIO2) pin output low + * @arg QSPI_WP_PIN_HIGH: WP(QSIO2) pin output high + * @retval None + */ +void QSPI_SetWpPinLevel(uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_WP_PIN_LVL(u32Level)); + + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_WPOL, u32Level); +} + +/** + * @brief Set the prefetch mode. + * @param [in] u32Mode The prefetch mode. + * This parameter can be one of the following values: + * @arg QSPI_PREFETCH_MD_INVD: Disable prefetch + * @arg QSPI_PREFETCH_MD_EDGE_STOP: Stop prefetch at the edge of byte + * @arg QSPI_PREFETCH_MD_IMMED_STOP: Stop prefetch at current position immediately + * @retval None + */ +void QSPI_SetPrefetchMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_PREFETCH_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, (QSPI_CR_PFE | QSPI_CR_PFSAE), u32Mode); +} + +/** + * @brief Selects the block to access. + * @param [in] u8Block Memory block number (range is 0 to 63) + * @retval None + */ +void QSPI_SelectMemoryBlock(uint8_t u8Block) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_BLOCK_SIZE(u8Block)); + + WRITE_REG32(CM_QSPI->EXAR, ((uint32_t)u8Block << QSPI_EXAR_EXADR_POS)); +} + +/** + * @brief Set the read mode. + * @param [in] u32Mode Read mode. + * This parameter can be one of the following values: + * @arg QSPI_RD_MD_STD_RD: Standard read mode (no dummy cycles) + * @arg QSPI_RD_MD_FAST_RD: Fast read mode (dummy cycles between address and data) + * @arg QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: Fast read dual output mode (data on 2 lines) + * @arg QSPI_RD_MD_DUAL_IO_FAST_RD: Fast read dual I/O mode (address and data on 2 lines) + * @arg QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: Fast read quad output mode (data on 4 lines) + * @arg QSPI_RD_MD_QUAD_IO_FAST_RD: Fast read quad I/O mode (address and data on 4 lines) + * @arg QSPI_RD_MD_CUSTOM_STANDARD_RD: Custom standard read mode + * @arg QSPI_RD_MD_CUSTOM_FAST_RD: Custom fast read mode + * @retval None + */ +void QSPI_SetReadMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_READ_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_MDSEL, u32Mode); +} + +/** + * @brief Configure the custom read. + * @param [in] pstcCustomMode Pointer to a @ref stc_qspi_custom_mode_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCustomMode) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_INSTR_PROTOCOL(pstcCustomMode->u32InstrProtocol)); + DDL_ASSERT(IS_QSPI_ADDR_PROTOCOL(pstcCustomMode->u32AddrProtocol)); + DDL_ASSERT(IS_QSPI_DATA_PROTOCOL(pstcCustomMode->u32DataProtocol)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CUSTOM_MD_CLR_MASK, (pstcCustomMode->u32InstrProtocol | + pstcCustomMode->u32AddrProtocol | pstcCustomMode->u32DataProtocol)); + WRITE_REG32(CM_QSPI->CCMD, pstcCustomMode->u8InstrCode); + } + + return i32Ret; +} + +/** + * @brief Enable or disable XIP mode. + * @param [in] u8ModeCode Enter or exit XIP mode code + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(CM_QSPI->XCMD, u8ModeCode); + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } else { + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } +} + +/** + * @brief Enter direct communication mode. + * @param None + * @retval None + */ +void QSPI_EnterDirectCommMode(void) +{ + /* Backup the read mode */ + m_u8ReadMode = (uint8_t)READ_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + /* Set standard read mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + /* Enter direct communication mode */ + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Exit direct communication mode. + * @param None + * @retval None + */ +void QSPI_ExitDirectCommMode(void) +{ + /* Exit direct communication mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); + /* Recovery the read mode */ + SET_REG32_BIT(CM_QSPI->CR, m_u8ReadMode); +} + +/** + * @brief Get the size of prefetched buffer. + * @param None + * @retval uint8_t Prefetched buffer size. + */ +uint8_t QSPI_GetPrefetchBufSize(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS); +} + +/** + * @brief Get QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed + * @arg QSPI_FLAG_XIP_MD: XIP mode + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full + * @arg QSPI_FLAG_PREFETCH_STOP: Prefetch function operating + * @arg QSPI_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_QSPI_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(CM_QSPI->SR, u32Flag)) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_CLR_ALL: All of the above + * @retval None + */ +void QSPI_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLR_FLAG(u32Flag)); + + SET_REG32_BIT(CM_QSPI->SR2, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c new file mode 100644 index 0000000000..61824d0acd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c @@ -0,0 +1,152 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.c + * @brief This file provides firmware functions to manage the Reset Manage Unit + * (RMU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rmu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RMU RMU + * @brief RMU Driver Library + * @{ + */ + +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Local_Macros RMU Local Macros + * @{ + */ + +/** + * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for RMU reset cause. */ +#define IS_VALID_RMU_RST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FLAG_ALL) == RMU_FLAG_ALL)) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Functions RMU Global Functions + * @{ + */ + +/** + * @brief Get the reset cause. + * @param [in] u32RmuResetCause Reset flags that need to be queried, @ref RMU_ResetCause in details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause) +{ + en_flag_status_t enStatus; + DDL_ASSERT(IS_VALID_RMU_RST_FLAG(u32RmuResetCause)); + + enStatus = ((0UL == READ_REG32_BIT(CM_RMU->RSTF0, u32RmuResetCause)) ? RESET : SET); + return enStatus; +} + +/** + * @brief Clear reset Status. + * @param None + * @retval NOne + * @note Clear reset flag should be done after read RMU_RSTF0 register. + * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first. + */ +void RMU_ClearStatus(void) +{ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + SET_REG_BIT(CM_RMU->RSTF0, RMU_RSTF0_CLRF); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/** + * @brief Enable or disable LOCKUP reset. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_PRSTCR0 register first. + */ +void RMU_CPULockUpCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_RMU->PRSTCR0_b.LKUPREN, enNewState); +} + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c new file mode 100644 index 0000000000..e023f20447 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c @@ -0,0 +1,1139 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.c + * @brief This file provides firmware functions to manage the Real-Time + * Clock(RTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rtc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RTC RTC + * @brief Real-Time Clock Driver Library + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Local_Macros RTC Local Macros + * @{ + */ + +/* RTC TPCR register Mask */ +#define RTC_TPCR_CLR_MASK (RTC_TPCR0_TPCT0 | RTC_TPCR0_TPNF0 | \ + RTC_TPCR0_TPRSTE0 | RTC_TPCR0_TSTPE0) +/* Get the specified register address of the RTC Intrusion Control */ +#define RTC_TPCRx(__CH__) ((uint32_t)(&(CM_RTC->TPCR0)) + (uint32_t)(__CH__)) + +/* RTC software reset timeout(ms) */ +#define RTC_SW_RST_TIMEOUT (100UL) +/* RTC mode switch timeout(ms) */ +#define RTC_MD_SWITCH_TIMEOUT (100UL) + +/** + * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity + * @{ + */ +#define IS_RTC_DATA_FMT(x) \ +( ((x) == RTC_DATA_FMT_DEC) || \ + ((x) == RTC_DATA_FMT_BCD)) + +#define IS_RTC_CLK_SRC(x) \ +( ((x) == RTC_CLK_SRC_XTAL32) || \ + ((x) == RTC_CLK_SRC_LRC)) + +#define IS_RTC_HOUR_FMT(x) \ +( ((x) == RTC_HOUR_FMT_12H) || \ + ((x) == RTC_HOUR_FMT_24H)) + +#define IS_RTC_INT_PERIOD(x) \ +( ((x) == RTC_INT_PERIOD_INVD) || \ + ((x) == RTC_INT_PERIOD_PER_HALF_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_MINUTE) || \ + ((x) == RTC_INT_PERIOD_PER_HOUR) || \ + ((x) == RTC_INT_PERIOD_PER_DAY) || \ + ((x) == RTC_INT_PERIOD_PER_MONTH)) + +#define IS_RTC_CLK_COMPEN(x) \ +( ((x) == RTC_CLK_COMPEN_DISABLE) || \ + ((x) == RTC_CLK_COMPEN_ENABLE)) + +#define IS_RTC_CLK_COMPEN_MD(x) \ +( ((x) == RTC_CLK_COMPEN_MD_DISTRIBUTED) || \ + ((x) == RTC_CLK_COMPEN_MD_UNIFORM)) + +#define IS_RTC_HOUR_12H_AM_PM(x) \ +( ((x) == RTC_HOUR_12H_AM) || \ + ((x) == RTC_HOUR_12H_PM)) + +#define IS_RTC_INTRU_CH(x) \ +( ((x) == RTC_INTRU_CH0) || \ + ((x) == RTC_INTRU_CH1)) + +#define IS_RTC_INTRU_TIMESTAMP(x) \ +( ((x) == RTC_INTRU_TS_DISABLE) || \ + ((x) == RTC_INTRU_TS_ENABLE)) + +#define IS_RTC_INTRU_RST_BACKUP_REG(x) \ +( ((x) == RTC_INTRU_RST_BACKUP_REG_DISABLE) || \ + ((x) == RTC_INTRU_RST_BACKUP_REG_ENABLE)) + +#define IS_RTC_INTRU_FILTER(x) \ +( ((x) == RTC_INTRU_FILTER_INVD) || \ + ((x) == RTC_INTRU_FILTER_THREE_TIME) || \ + ((x) == RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32)) + +#define IS_RTC_INTRU_TRIG_EDGE(x) \ +( ((x) == RTC_INTRU_TRIG_EDGE_NONE) || \ + ((x) == RTC_INTRU_TRIG_EDGE_RISING) || \ + ((x) == RTC_INTRU_TRIG_EDGE_FALLING) || \ + ((x) == RTC_INTRU_TRIG_EDGE_RISING_FALLING)) + +#define IS_RTC_GET_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_ALL) == RTC_FLAG_ALL)) + +#define IS_RTC_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_CLR_ALL) == RTC_FLAG_CLR_ALL)) + +#define IS_RTC_INT(x) \ +( ((x) != 0U) && \ + (((x) | RTC_INT_ALL) == RTC_INT_ALL)) + +#define IS_RTC_YEAR(x) ((x) <= 99U) + +#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U)) + +#define IS_RTC_HOUR_12H(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_HOUR_24H(x) ((x) <= 23U) + +#define IS_RTC_MINUTE(x) ((x) <= 59U) + +#define IS_RTC_SEC(x) ((x) <= 59U) + +#define IS_RTC_WEEKDAY(x) ((x) <= 6U) + +#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU)) + +#define IS_RTC_COMPEN_VALUE(x) ((x) <= 0x1FFU) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Functions RTC Global Functions + * @{ + */ + +/** + * @brief De-Initialize RTC. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t RTC_DeInit(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_RTC->CR0_b.RESET, RESET); + /* Waiting for normal count status or end of RTC software reset */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + /* Reset all RTC registers */ + WRITE_REG32(bCM_RTC->CR0_b.RESET, SET); + /* Waiting for RTC software reset to complete */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + + return i32Ret; +} + +/** + * @brief Initialize RTC. + * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(pstcRtcInit->u8ClockSrc)); + DDL_ASSERT(IS_RTC_HOUR_FMT(pstcRtcInit->u8HourFormat)); + DDL_ASSERT(IS_RTC_INT_PERIOD(pstcRtcInit->u8IntPeriod)); + DDL_ASSERT(IS_RTC_CLK_COMPEN(pstcRtcInit->u8ClockCompen)); + DDL_ASSERT(IS_RTC_COMPEN_VALUE(pstcRtcInit->u16CompenValue)); + DDL_ASSERT(IS_RTC_CLK_COMPEN_MD(pstcRtcInit->u8CompenMode)); + + /* RTC CR3 Configuration */ + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSrc); + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL), + (pstcRtcInit->u8IntPeriod | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode)); + /* RTC Compensation Configuration */ + MODIFY_REG8(CM_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8), + (pstcRtcInit->u8ClockCompen | (uint8_t)((pstcRtcInit->u16CompenValue >> 8U) & 0x01U))); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16CompenValue & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_rtc_init_t member with default value. + * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: stc_rtc_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRtcInit->u8ClockSrc = RTC_CLK_SRC_LRC; + pstcRtcInit->u8HourFormat = RTC_HOUR_FMT_24H; + pstcRtcInit->u8IntPeriod = RTC_INT_PERIOD_INVD; + pstcRtcInit->u8ClockCompen = RTC_CLK_COMPEN_DISABLE; + pstcRtcInit->u8CompenMode = RTC_CLK_COMPEN_MD_DISTRIBUTED; + pstcRtcInit->u16CompenValue = 0U; + } + + return i32Ret; +} + +/** + * @brief Enter RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Enter mode success + * - LL_ERR_TIMEOUT: Enter mode timeout + */ +int32_t RTC_EnterRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Exit RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Exit mode success + * - LL_ERR_TIMEOUT: Exit mode timeout + */ +int32_t RTC_ExitRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Confirm the condition for RTC to enter low power mode. + * @param None + * @retval int32_t: + * - LL_OK: Can enter low power mode + * - LL_ERR_TIMEOUT: Can't enter low power mode + */ +int32_t RTC_ConfirmLPMCond(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check RTC work status */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RTC RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RTC RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Set the RTC interrupt period. + * @param [in] u8Period Specifies the interrupt period. + * This parameter can be one of the following values: + * @arg RTC_INT_PERIOD_INVD: Period interrupt invalid + * @arg RTC_INT_PERIOD_PER_HALF_SEC: Interrupt per half second + * @arg RTC_INT_PERIOD_PER_SEC: Interrupt per second + * @arg RTC_INT_PERIOD_PER_MINUTE: Interrupt per minute + * @arg RTC_INT_PERIOD_PER_HOUR: Interrupt per hour + * @arg RTC_INT_PERIOD_PER_DAY: Interrupt per day + * @arg RTC_INT_PERIOD_PER_MONTH: Interrupt per month + * @retval None + */ +void RTC_SetIntPeriod(uint8_t u8Period) +{ + uint32_t u32RtcSta; + uint32_t u32IntSta; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT_PERIOD(u8Period)); + + u32RtcSta = READ_REG32(bCM_RTC->CR1_b.START); + u32IntSta = READ_REG32(bCM_RTC->CR2_b.PRDIE); + /* Disable period interrupt when START=1 and clear period flag after write */ + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, RESET); + } + + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, RTC_CR1_PRDS, u8Period); + WRITE_REG32(bCM_RTC->CR2_b.PRDF, RESET); + + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, SET); + } +} + +/** + * @brief Set the RTC clock source. + * @param [in] u8Src Specifies the clock source. + * This parameter can be one of the following values: + * @arg RTC_CLK_SRC_XTAL32: XTAL32 Cloc + * @arg RTC_CLK_SRC_LRC: LRC/RTCLRC Clock + * @retval None + */ +void RTC_SetClockSrc(uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(u8Src)); + + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), u8Src); +} + +/** + * @brief Set RTC clock compensation value. + * @param [in] u16Value Specifies the clock compensation value of RTC. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF. + * @retval None + */ +void RTC_SetClockCompenValue(uint16_t u16Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_COMPEN_VALUE(u16Value)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMP8, ((uint32_t)u16Value >> 8U) & 0x01U); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(u16Value & 0x00FFU)); +} + +/** + * @brief Get RTC counter status. + * @param None + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: RTC counter started + * - DISABLE: RTC counter stopped + */ +en_functional_state_t RTC_GetCounterState(void) +{ + en_functional_state_t enState = DISABLE; + + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + enState = ENABLE; + } + + return enState; +} + +/** + * @brief Enable or disable RTC count. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.START, enNewState); +} + +/** + * @brief Enable or disable RTC LRC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_LrcCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR3_b.LRCEN, enNewState); +} + +/** + * @brief Enable or disable RTC 1HZ output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_OneHzOutputCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.ONEHZOE, enNewState); +} + +/** + * @brief Enable or disable clock compensation. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_ClockCompenCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMPEN, enNewState); +} + +/** + * @brief Set RTC current date. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Set date success + * - LL_ERR: Set date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + DDL_ASSERT(IS_RTC_YEAR(RTC_BCD2DEC(pstcRtcDate->u8Year))); + DDL_ASSERT(IS_RTC_MONTH(RTC_BCD2DEC(pstcRtcDate->u8Month))); + DDL_ASSERT(IS_RTC_DAY(RTC_BCD2DEC(pstcRtcDate->u8Day))); + } else { + DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year)); + DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month)); + DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day)); + } + DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday)); + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_DEC2BCD(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_DEC2BCD(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_DEC2BCD(pstcRtcDate->u8Day); + } + + WRITE_REG8(CM_RTC->YEAR, pstcRtcDate->u8Year); + WRITE_REG8(CM_RTC->MON, pstcRtcDate->u8Month); + WRITE_REG8(CM_RTC->DAY, pstcRtcDate->u8Day); + WRITE_REG8(CM_RTC->WEEK, pstcRtcDate->u8Weekday); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current date. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Get date success + * - LL_ERR: Get date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC date registers */ + pstcRtcDate->u8Year = READ_REG8(CM_RTC->YEAR); + pstcRtcDate->u8Month = READ_REG8(CM_RTC->MON); + pstcRtcDate->u8Day = READ_REG8(CM_RTC->DAY); + pstcRtcDate->u8Weekday = READ_REG8(CM_RTC->WEEK); + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_BCD2DEC(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_BCD2DEC(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_BCD2DEC(pstcRtcDate->u8Day); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC current time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Set time success + * - LL_ERR: Set time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcTime->u8Minute))); + DDL_ASSERT(IS_RTC_SEC(RTC_BCD2DEC(pstcRtcTime->u8Second))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcTime->u8Hour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcTime->u8Hour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute)); + DDL_ASSERT(IS_RTC_SEC(pstcRtcTime->u8Second)); + } + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_DEC2BCD(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_DEC2BCD(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_DEC2BCD(pstcRtcTime->u8Second); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcTime->u8AmPm)) { + SET_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->HOUR, pstcRtcTime->u8Hour); + WRITE_REG8(CM_RTC->MIN, pstcRtcTime->u8Minute); + WRITE_REG8(CM_RTC->SEC, pstcRtcTime->u8Second); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Get time success + * - LL_ERR: Get time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC time registers */ + pstcRtcTime->u8Hour = READ_REG8(CM_RTC->HOUR); + pstcRtcTime->u8Minute = READ_REG8(CM_RTC->MIN); + pstcRtcTime->u8Second = READ_REG8(CM_RTC->SEC); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcTime->u8Hour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + pstcRtcTime->u8AmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_BCD2DEC(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_BCD2DEC(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_BCD2DEC(pstcRtcTime->u8Second); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC alarm time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Set RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcAlarm->u8AlarmHour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcAlarm->u8AlarmHour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute)); + } + DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday)); + + /* Configure alarm registers */ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmMinute); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcAlarm->u8AlarmAmPm)) { + SET_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour); + WRITE_REG8(CM_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute); + WRITE_REG8(CM_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday); + } + + return i32Ret; +} + +/** + * @brief Get RTC alarm time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Get RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + + /* Get RTC date and time register */ + pstcRtcAlarm->u8AlarmWeekday = READ_REG8(CM_RTC->ALMWEEK); + pstcRtcAlarm->u8AlarmMinute = READ_REG8(CM_RTC->ALMMIN); + pstcRtcAlarm->u8AlarmHour = READ_REG8(CM_RTC->ALMHOUR); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable RTC alarm. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_AlarmCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR2_b.ALME, enNewState); +} + +/** + * @brief De-Initialize RTC intrusion function.. + * @param [in] u8Ch Specifies the RTC intrusion channel. + * This parameter can be one of the following values: + * @arg RTC_INTRU_CH0: Intrusion channel 0 + * @arg RTC_INTRU_CH1: Intrusion channel 1 + * @retval None + */ +void RTC_INTRU_DeInit(uint8_t u8Ch) +{ + __IO uint8_t *TPCR; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTRU_CH(u8Ch)); + + TPCR = (__IO uint8_t *)RTC_TPCRx(u8Ch); + WRITE_REG8(*TPCR, 0U); + WRITE_REG8(CM_RTC->TPSR, 0U); +} + +/** + * @brief Initialize RTC intrusion function. + * @param [in] u8Ch Specifies the RTC intrusion channel. + * This parameter can be one of the following values: + * @arg RTC_INTRU_CH0: Intrusion channel 0 + * @arg RTC_INTRU_CH1: Intrusion channel 1 + * @param [in] pstcIntru Pointer to a @ref stc_rtc_intrusion_t structure + * @retval int32_t: + * - LL_OK: Configure RTC intrusion function success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_INTRU_Init(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t *TPCR; + + if (NULL == pstcIntru) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTRU_CH(u8Ch)); + DDL_ASSERT(IS_RTC_INTRU_TIMESTAMP(pstcIntru->u8Timestamp)); + DDL_ASSERT(IS_RTC_INTRU_RST_BACKUP_REG(pstcIntru->u8ResetBackupReg)); + DDL_ASSERT(IS_RTC_INTRU_FILTER(pstcIntru->u8Filter)); + DDL_ASSERT(IS_RTC_INTRU_TRIG_EDGE(pstcIntru->u8TriggerEdge)); + + TPCR = (__IO uint8_t *)RTC_TPCRx(u8Ch); + /* RTC Intrusion control Configuration */ + MODIFY_REG8(*TPCR, RTC_TPCR_CLR_MASK, + (pstcIntru->u8Timestamp | pstcIntru->u8ResetBackupReg | + pstcIntru->u8Filter | pstcIntru->u8TriggerEdge)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_rtc_intrusion_t member with default value. + * @param [out] pstcIntru Pointer to a @ref stc_rtc_intrusion_t structure + * @retval int32_t: + * - LL_OK: stc_rtc_intrusion_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_INTRU_StructInit(stc_rtc_intrusion_t *pstcIntru) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcIntru) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcIntru->u8Timestamp = RTC_INTRU_TS_DISABLE; + pstcIntru->u8ResetBackupReg = RTC_INTRU_RST_BACKUP_REG_DISABLE; + pstcIntru->u8Filter = RTC_INTRU_FILTER_INVD; + pstcIntru->u8TriggerEdge = RTC_INTRU_TRIG_EDGE_NONE; + } + + return i32Ret; +} + +/** + * @brief Get RTC intrusion timestamp. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcTimestamp Pointer to a @ref stc_rtc_timestamp_t structure + * @retval int32_t: + * - LL_OK: Get RTC intrusion timestamp success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_INTRU_GetTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTimestamp) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + + /* Get RTC Timestamp registers */ + pstcTimestamp->stcTime.u8Hour = READ_REG8(CM_RTC->HOURTP); + pstcTimestamp->stcTime.u8Minute = READ_REG8(CM_RTC->MINTP); + pstcTimestamp->stcTime.u8Second = READ_REG8(CM_RTC->SECTP); + pstcTimestamp->u8Month = READ_REG8(CM_RTC->MONTP); + pstcTimestamp->u8Day = READ_REG8(CM_RTC->DAYTP); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcTimestamp->stcTime.u8Hour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcTimestamp->stcTime.u8Hour, RTC_HOUR_12H_PM); + pstcTimestamp->stcTime.u8AmPm = RTC_HOUR_12H_PM; + } else { + pstcTimestamp->stcTime.u8AmPm = RTC_HOUR_12H_AM; + } + } else { + pstcTimestamp->stcTime.u8AmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcTimestamp->stcTime.u8Hour = RTC_BCD2DEC(pstcTimestamp->stcTime.u8Hour); + pstcTimestamp->stcTime.u8Minute = RTC_BCD2DEC(pstcTimestamp->stcTime.u8Minute); + pstcTimestamp->stcTime.u8Second = RTC_BCD2DEC(pstcTimestamp->stcTime.u8Second); + pstcTimestamp->u8Month = RTC_BCD2DEC(pstcTimestamp->u8Month); + pstcTimestamp->u8Day = RTC_BCD2DEC(pstcTimestamp->u8Day); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable RTC intrusion. + * @param [in] u8Ch Specifies the RTC intrusion channel. + * This parameter can be one of the following values: + * @arg RTC_INTRU_CH0: Intrusion channel 0 + * @arg RTC_INTRU_CH1: Intrusion channel 1 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_INTRU_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTRU_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (RTC_INTRU_CH0 != u8Ch) { + WRITE_REG32(bCM_RTC->TPCR1_b.TPEN1, enNewState); + } else { + WRITE_REG32(bCM_RTC->TPCR0_b.TPEN0, enNewState); + } +} + +/** + * @brief Enable or disable specified RTC interrupt. + * @param [in] u32IntType Specifies the RTC interrupt source. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32IntTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntTemp = u32IntType & 0x0000FFUL; + if (0UL != u32IntTemp) { + if (DISABLE != enNewState) { + SET_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } else { + CLR_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } + } + + /* Intrusion interrupt */ + if (0UL != (u32IntType & 0x00FF00UL)) { + WRITE_REG32(bCM_RTC->TPCR0_b.TPIE0, enNewState); + } + if (0UL != (u32IntType & 0xFF0000UL)) { + WRITE_REG32(bCM_RTC->TPCR1_b.TPIE1, enNewState); + } +} + +/** + * @brief Get RTC flag status. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RTC_GetStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + if (0U != (READ_REG8_BIT(CM_RTC->CR2, u8FlagTemp))) { + enFlagSta = SET; + } + } + + /* Intrusion interrupt flag */ + u8FlagTemp = (uint8_t)((u32Flag >> 16U) & 0xFFU); + if ((0U != u8FlagTemp) && (SET != enFlagSta)) { + if (0U != (READ_REG8_BIT(CM_RTC->TPSR, u8FlagTemp))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear RTC flag. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_CLR_ALL: All of the above + * @retval None + */ +void RTC_ClearStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLR_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + CLR_REG8_BIT(CM_RTC->CR2, u8FlagTemp); + } + + u8FlagTemp = (uint8_t)((u32Flag >> 16U) & 0xFFU); + /* Intrusion interrupt flag */ + if (0U != u8FlagTemp) { + CLR_REG8_BIT(CM_RTC->TPSR, u8FlagTemp); + } +} + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c new file mode 100644 index 0000000000..4b0b3309ac --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c @@ -0,0 +1,2676 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.c + * @brief This file provides firmware functions to manage the Secure Digital + * Input and Output Controller(SDIOC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sdioc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SDIOC SDIOC + * @brief SDIOC Driver Library + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Local_Macros SDIOC Local Macros + * @{ + */ + +/* Masks for R6 Response */ +#define SDMMC_R6_GEN_UNKNOWN_ERR (0x00002000UL) +#define SDMMC_R6_ILLEGAL_CMD (0x00004000UL) +#define SDMMC_R6_COM_CRC_FAIL (0x00008000UL) + +/* SDMMC command parameters */ +#define SDMMC_CMD8_CHECK_PATTERN (0x000001AAUL) +/* 3.2V-3.3V */ +#define SDMMC_ACMD41_VOLT_WIN (0x80100000UL) + +/* Command send and response timeout(ms) */ +#define SDMMC_CMD_TIMEOUT (5000UL) +/* Max erase Timeout 60s */ +#define SDMMC_MAX_ERASE_TIMEOUT (60000UL) +/* SDIOC software reset timeout(ms) */ +#define SDIOC_SW_RST_TIMEOUT (50UL) + +/* SDIOC NORINTSGEN register Mask */ +#define SDIOC_NORINTSGEN_CLR_MASK (0x01F7U) +/* SDIOC ERRINTSGEN register Mask */ +#define SDIOC_ERRINTSGEN_CLR_MASK (0x017FU) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->ARG0))) +#define SDIOC_BUF_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->BUF0))) +#define SDIOC_RESP_ADDR(__UNIT__, __RESP__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->RESP0)) + (__RESP__)) + +/** + * @defgroup SDIOC_Check_Parameters_Validity SDIOC Check Parameters Validity + * @{ + */ +#define IS_SDIOC_UNIT(x) \ +( ((x) == CM_SDIOC1) || \ + ((x) == CM_SDIOC2)) + +#define IS_SDIOC_MD(x) \ +( ((x) == SDIOC_MD_SD) || \ + ((x) == SDIOC_MD_MMC)) + +#define IS_SDIOC_CARD_DETECT_WAY(x) \ +( ((x) == SDIOC_CARD_DETECT_CD_PIN_LVL) || \ + ((x) == SDIOC_CARD_DETECT_TEST_SIGNAL)) + +#define IS_SDIOC_CARD_DETECT_TEST_LEVEL(x) \ +( ((x) == SDIOC_CARD_DETECT_TEST_LVL_LOW) || \ + ((x) == SDIOC_CARD_DETECT_TEST_LVL_HIGH)) + +#define IS_SDIOC_SPEED_MD(x) \ +( ((x) == SDIOC_SPEED_MD_NORMAL) || \ + ((x) == SDIOC_SPEED_MD_HIGH)) + +#define IS_SDIOC_BUS_WIDTH(x) \ +( ((x) == SDIOC_BUS_WIDTH_1BIT) || \ + ((x) == SDIOC_BUS_WIDTH_4BIT) || \ + ((x) == SDIOC_BUS_WIDTH_8BIT)) + +#define IS_SDIOC_CLK_DIV(x) \ +( ((x) == SDIOC_CLK_DIV1) || \ + ((x) == SDIOC_CLK_DIV2) || \ + ((x) == SDIOC_CLK_DIV4) || \ + ((x) == SDIOC_CLK_DIV8) || \ + ((x) == SDIOC_CLK_DIV16) || \ + ((x) == SDIOC_CLK_DIV32) || \ + ((x) == SDIOC_CLK_DIV64) || \ + ((x) == SDIOC_CLK_DIV128) || \ + ((x) == SDIOC_CLK_DIV256)) + +#define IS_SDIOC_CMD_TYPE(x) \ +( ((x) == SDIOC_CMD_TYPE_NORMAL) || \ + ((x) == SDIOC_CMD_TYPE_SUSPEND) || \ + ((x) == SDIOC_CMD_TYPE_RESUME) || \ + ((x) == SDIOC_CMD_TYPE_ABORT)) + +#define IS_SDIOC_DATA_LINE(x) \ +( ((x) == SDIOC_DATA_LINE_DISABLE) || \ + ((x) == SDIOC_DATA_LINE_ENABLE)) + +#define IS_SDIOC_TRANS_DIR(x) \ +( ((x) == SDIOC_TRANS_DIR_TO_CARD) || \ + ((x) == SDIOC_TRANS_DIR_TO_HOST)) + +#define IS_SDIOC_AUTO_SEND_CMD12(x) \ +( ((x) == SDIOC_AUTO_SEND_CMD12_DISABLE) || \ + ((x) == SDIOC_AUTO_SEND_CMD12_ENABLE)) + +#define IS_SDIOC_TRANS_MD(x) \ +( ((x) == SDIOC_TRANS_MD_SINGLE) || \ + ((x) == SDIOC_TRANS_MD_INFINITE) || \ + ((x) == SDIOC_TRANS_MD_MULTI) || \ + ((x) == SDIOC_TRANS_MD_STOP_MULTI)) + +#define IS_SDIOC_DATA_TIMEOUT_TIME(x) ((x) <= SDIOC_DATA_TIMEOUT_CLK_2E27) + +#define IS_SDIOC_RESP_REG(x) \ +( ((x) == SDIOC_RESP_REG_BIT0_31) || \ + ((x) == SDIOC_RESP_REG_BIT32_63) || \ + ((x) == SDIOC_RESP_REG_BIT64_95) || \ + ((x) == SDIOC_RESP_REG_BIT96_127)) + +#define IS_SDIOC_SW_RST_TYPE(x) \ +( ((x) == SDIOC_SW_RST_DATA_LINE) || \ + ((x) == SDIOC_SW_RST_CMD_LINE) || \ + ((x) == SDIOC_SW_RST_ALL)) + +#define IS_SDIOC_OUTPUT_CLK_FREQ(x) \ +( ((x) == SDIOC_OUTPUT_CLK_FREQ_400K) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_25M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_26M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_50M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_52M)) + +#define IS_SDIOC_GET_HOST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_HOST_FLAG_ALL) == SDIOC_HOST_FLAG_ALL)) + +#define IS_SDIOC_GET_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_ALL) == SDIOC_INT_FLAG_ALL)) + +#define IS_SDIOC_CLR_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_CLR_ALL) == SDIOC_INT_FLAG_CLR_ALL)) + +#define IS_SDIOC_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_ALL) == SDIOC_INT_ALL)) + +#define IS_SDIOC_AUTO_CMD_ERR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_AUTO_CMD_ERR_FLAG_ALL) == SDIOC_AUTO_CMD_ERR_FLAG_ALL)) + +#define IS_SDIOC_FORCE_AUTO_CMD_ERR(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_AUTO_CMD_ERR_ALL) == SDIOC_FORCE_AUTO_CMD_ERR_ALL)) + +#define IS_SDIOC_FORCE_ERR_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_ERR_INT_ALL) == SDIOC_FORCE_ERR_INT_ALL)) + +#define IS_SDIOC_RESP_TYPE(x) \ +( ((x) == SDIOC_RESP_TYPE_NO) || \ + ((x) == SDIOC_RESP_TYPE_R2) || \ + ((x) == SDIOC_RESP_TYPE_R3_R4) || \ + ((x) == SDIOC_RESP_TYPE_R1_R5_R6_R7) || \ + ((x) == SDIOC_RESP_TYPE_R1B_R5B)) + +#define IS_SDIOC_CMD_INDEX(x) ((x) < 0x40U) + +#define IS_SDIOC_BLOCK_SIZE(x) (((x) >= 1U) && ((x) <= 512U)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Functions SDIOC Global Functions + * @{ + */ + +/** + * @brief Wait for command response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32CheckFlag Check flags + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_CC: Command Complete status + * @arg SDIOC_INT_FLAG_CIE: Command Index error status + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error status + * @arg SDIOC_INT_FLAG_CCE: Command CRC error status + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error status + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_WaitResponse(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32CheckFlag, + uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + uint32_t u32Temp; + + *pu32ErrStatus = 0UL; + /* The u32Timeout is expressed in ms */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, u32CheckFlag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + u32Temp = CLR_REG32_BIT(u32CheckFlag, SDIOC_INT_FLAG_CC); + if (RESET == SDIOC_GetIntStatus(SDIOCx, u32Temp)) { + /* No error flag set */ + *pu32ErrStatus = SDMMC_ERR_NONE; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + i32Ret = LL_OK; + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE)) && + (SDIOC_INT_FLAG_CIE == (u32CheckFlag & SDIOC_INT_FLAG_CIE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_INDEX; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE)) && + (SDIOC_INT_FLAG_CEBE == (u32CheckFlag & SDIOC_INT_FLAG_CEBE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_STOP_BIT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE)) && + (SDIOC_INT_FLAG_CCE == (u32CheckFlag & SDIOC_INT_FLAG_CCE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_CRC_FAIL; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE); + } else { + *pu32ErrStatus = SDMMC_ERR_CMD_TIMEOUT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CTOE); + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for no response command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdError(CM_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* The SDMMC_CMD_TIMEOUT is expressed in ms */ + u32Count = SDMMC_CMD_TIMEOUT * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CC)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + if (LL_OK == i32Ret) { + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response with busy. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1Busy(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } else { + /* Wait for busy status to release */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetHostStatus(SDIOCx, SDIOC_HOST_FLAG_DATL_D0)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R2(CID or CSD) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp2(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CCE | + SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R3(OCR) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp3(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CTOE), + SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R6(RCA) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to a value of device RCA + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp6(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL == (u32RespVal & (SDMMC_R6_GEN_UNKNOWN_ERR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAIL))) { + i32Ret = LL_OK; + *pu16RCA = (uint16_t)(u32RespVal >> 16U); + } else if (SDMMC_R6_GEN_UNKNOWN_ERR == (u32RespVal & SDMMC_R6_GEN_UNKNOWN_ERR)) { + *pu32ErrStatus = SDMMC_ERR_GENERAL_UNKNOWN_ERR; + } else if (SDMMC_R6_ILLEGAL_CMD == (u32RespVal & SDMMC_R6_ILLEGAL_CMD)) { + *pu32ErrStatus = SDMMC_ERR_ILLEGAL_CMD; + } else { + *pu32ErrStatus = SDMMC_ERR_COM_CRC_FAILED; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R7 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp7(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief De-Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: SDIOC De-Initialize success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx) +{ + return SDIOC_SWReset(SDIOCx, SDIOC_SW_RST_ALL); +} + +/** + * @brief Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_MD(pstcSdiocInit->u32Mode)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(pstcSdiocInit->u8CardDetect)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(pstcSdiocInit->u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(pstcSdiocInit->u8BusWidth)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(pstcSdiocInit->u16ClockDiv)); + + /* Set the SDIOC mode */ + if (CM_SDIOC1 == SDIOCx) { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC1, pstcSdiocInit->u32Mode); + } else { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC2, pstcSdiocInit->u32Mode); + } + /* Set the SDIOC clock control value */ + WRITE_REG16(SDIOCx->CLKCON, (pstcSdiocInit->u16ClockDiv | SDIOC_CLKCON_ICE | SDIOC_CLKCON_CE)); + /* Set the SDIOC host control value */ + WRITE_REG8(SDIOCx->HOSTCON, (pstcSdiocInit->u8CardDetect | pstcSdiocInit->u8BusWidth | + pstcSdiocInit->u8SpeedMode)); + /* Enable normal interrupt status */ + WRITE_REG16(SDIOCx->NORINTSTEN, SDIOC_NORINTSGEN_CLR_MASK); + /* Enable error interrupt status */ + WRITE_REG16(SDIOCx->ERRINTSTEN, SDIOC_ERRINTSGEN_CLR_MASK); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_init_t to default values. + * @param [out] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcSdiocInit->u32Mode = SDIOC_MD_SD; + pstcSdiocInit->u8CardDetect = SDIOC_CARD_DETECT_CD_PIN_LVL; + pstcSdiocInit->u8SpeedMode = SDIOC_SPEED_MD_NORMAL; + pstcSdiocInit->u8BusWidth = SDIOC_BUS_WIDTH_1BIT; + pstcSdiocInit->u16ClockDiv = SDIOC_CLK_DIV1; + } + + return i32Ret; +} + +/** + * @brief Set software reset. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Type Software reset type + * This parameter can be one of the following values: + * @arg SDIOC_SW_RST_DATA_LINE: Only part of data circuit is reset + * @arg SDIOC_SW_RST_CMD_LINE: Only part of command circuit is reset + * @arg SDIOC_SW_RST_ALL: Reset the entire Host Controller except for the card detection circuit + * @retval int32_t: + * - LL_OK: Software reset success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SW_RST_TYPE(u8Type)); + + WRITE_REG8(SDIOCx->SFTRST, u8Type); + /* Wait for reset finish */ + u32Count = SDIOC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0U != READ_REG8_BIT(SDIOCx->SFTRST, u8Type)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Enable or disable power. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } else { + CLR_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } +} + +/** + * @brief Get power state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_functional_state_t enumeration value. + * - DISABLE: Power off or SDIOCx == NULL + * - ENABLE: Power on + */ +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_functional_state_t enPowerSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0U != (READ_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON))) { + enPowerSta = ENABLE; + } + + return enPowerSta; +} + +/** + * @brief Get SDIOC work mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval uint32_t value: + * - SDIOC_MD_SD: SDIOCx selects SD mode + * - SDIOC_MD_MMC: SDIOCx selects MMC mode + */ +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx) +{ + uint32_t u32SdMode; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + u32SdMode = READ_REG32_BIT(CM_PERIC->SDIOC_SYCTLREG, ((CM_SDIOC1 == SDIOCx) ? + PERIC_SDIOC_SYCTLREG_SELMMC1 : PERIC_SDIOC_SYCTLREG_SELMMC2)); + if (0UL != u32SdMode) { /* MMC mode */ + u32SdMode = SDIOC_MD_MMC; + } else { + u32SdMode = SDIOC_MD_SD; + } + + return u32SdMode; +} + +/** + * @brief Enable or disable clock output. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } else { + CLR_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } +} + +/** + * @brief Set clock division. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Div Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval None + */ +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16Div)); + + MODIFY_REG16(SDIOCx->CLKCON, SDIOC_CLKCON_FS, u16Div); +} + +/** + * @brief Find the most suitable clock division for the set clock frequency. + * @note More clock values can be set as needed, but the maximum cannot exceed 50MHz. + * @param [in] u32ClockFreq SDIOCx_CK clock frequency + * This parameter can be one of the following values: + * @arg SDIOC_OUTPUT_CLK_FREQ_400K: SDIOC clock: 400KHz + * @arg SDIOC_OUTPUT_CLK_FREQ_25M: SDIOC clock: 25MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_26M: SDIOC clock: 26MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_50M: SDIOC clock: 50MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_52M: SDIOC clock: 52MHz + * @arg Any other value + * @param [out] pu16Div Pointer to a value of clock division + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR: The Bus clock frequency is too high + * - LL_ERR_INVD_PARAM: pu16Div == NULL or 0UL == u32ClockFreq + */ +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockDiv; + uint32_t u32Temp; + + if ((NULL == pu16Div) || (0UL == u32ClockFreq)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Get BUS frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + u32ClockDiv = u32BusClock / u32ClockFreq; + if (0UL != (u32BusClock % u32ClockFreq)) { + u32ClockDiv++; + } + /* Check the effectiveness of clock division */ + if (u32ClockDiv > 256U) { /* Maximum division is 256 */ + i32Ret = LL_ERR; + } else { + if (1U == u32ClockDiv) { + *pu16Div = SDIOC_CLK_DIV1; + } else { + for (u32Temp = SDIOC_CLK_DIV2; u32Temp <= SDIOC_CLK_DIV256; u32Temp <<= 1U) { + if (u32ClockDiv <= (u32Temp >> (SDIOC_CLKCON_FS_POS - 1U))) { + break; + } + } + *pu16Div = (uint16_t)u32Temp; + } + } + } + + return i32Ret; +} + +/** + * @brief Verify the validity of the clock division. + * @param [in] u32Mode SDIOC work mode + * This parameter can be one of the following values: + * @arg SDIOC_MD_SD: SDIOCx selects SD mode + * @arg SDIOC_MD_MMC: SDIOCx selects MMC mode + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @param [in] u16ClockDiv Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval int32_t: + * - LL_OK: The clock division is valid + * - LL_ERR: The Bus clock frequency is too high + */ +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockFreq; + uint32_t u32MaxFreq; + uint32_t u32DivValue; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_MD(u32Mode)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16ClockDiv)); + + /* Get Bus frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + u32DivValue = ((uint32_t)u16ClockDiv >> (SDIOC_CLKCON_FS_POS - 1U)); + if (0UL == u32DivValue) { + u32ClockFreq = u32BusClock; + } else { + u32ClockFreq = u32BusClock / u32DivValue; + } + + if (SDIOC_SPEED_MD_NORMAL == u8SpeedMode) { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_26M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_25M; + } + } else { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_52M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_50M; + } + } + if (u32ClockFreq > u32MaxFreq) { + i32Ret = LL_ERR; + } + + return i32Ret; +} + +/** + * @brief Get device insert status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CSS))) { + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CIN))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Set speed mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @retval None + */ +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + + if (SDIOC_SPEED_MD_NORMAL != u8SpeedMode) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } +} + +/** + * @brief Set bus width. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8BusWidth Bus width + * This parameter can be one of the following values: + * @arg SDIOC_BUS_WIDTH_1BIT: The Bus width is 1 bit + * @arg SDIOC_BUS_WIDTH_4BIT: The Bus width is 4 bit + * @arg SDIOC_BUS_WIDTH_8BIT: The Bus width is 8 bit + * @retval None + */ +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(u8BusWidth)); + + MODIFY_REG8(SDIOCx->HOSTCON, (SDIOC_HOSTCON_DW | SDIOC_HOSTCON_EXDW), u8BusWidth); +} + +/** + * @brief Set card detect line select. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Src Card detect source + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_CD_PIN_LVL: SDIOCx_CD(x=1~2) line is selected (for normal use) + * @arg SDIOC_CARD_DETECT_TEST_SIGNAL: The Card Detect Test Level is selected(for test purpose) + * @retval None + */ +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(u8Src)); + + if (SDIOC_CARD_DETECT_CD_PIN_LVL != u8Src) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } +} + +/** + * @brief Set card detect test level. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Level Card test level + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_TEST_LVL_LOW: Card identification test signal is low level (with device insertion) + * @arg SDIOC_CARD_DETECT_TEST_LVL_HIGH: Card identification test signal is high level (no device insertion) + * @retval None + */ +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_TEST_LEVEL(u8Level)); + + if (SDIOC_CARD_DETECT_TEST_LVL_LOW != u8Level) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } +} + +/** + * @brief Configure the SDIOCx command parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx command parameters success + * - LL_ERR_INVD_PARAM: pstcCmdConfig == NULL + */ +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *pu32Temp; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CMD_INDEX(pstcCmdConfig->u16CmdIndex)); + DDL_ASSERT(IS_SDIOC_CMD_TYPE(pstcCmdConfig->u16CmdType)); + DDL_ASSERT(IS_SDIOC_DATA_LINE(pstcCmdConfig->u16DataLine)); + DDL_ASSERT(IS_SDIOC_RESP_TYPE(pstcCmdConfig->u16ResponseType)); + + /* Set the SDIOC Command parameters value */ + pu32Temp = SDIOC_ARG_ADDR(SDIOCx); + WRITE_REG32(*pu32Temp, pstcCmdConfig->u32Argument); + /* Set the SDIOC Command controller value */ + WRITE_REG16(SDIOCx->CMD, ((uint16_t)(pstcCmdConfig->u16CmdIndex << SDIOC_CMD_IDX_POS) | + pstcCmdConfig->u16CmdType | pstcCmdConfig->u16DataLine | + pstcCmdConfig->u16ResponseType)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_cmd_config_t to default values. + * @param [out] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcCmdConfig->u32Argument = 0U; + pstcCmdConfig->u16CmdIndex = 0U; + pstcCmdConfig->u16CmdType = SDIOC_CMD_TYPE_NORMAL; + pstcCmdConfig->u16DataLine = SDIOC_DATA_LINE_DISABLE; + pstcCmdConfig->u16ResponseType = SDIOC_RESP_TYPE_NO; + } + + return i32Ret; +} + +/** + * @brief Get the response received from the card for the last command + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Reg SDIOC response register + * This parameter can be one of the following values: + * @arg SDIOC_RESP_REG_BIT0_31: Command Response Register 0-31bit + * @arg SDIOC_RESP_REG_BIT32_63: Command Response Register 32-63bit + * @arg SDIOC_RESP_REG_BIT64_95: Command Response Register 64-95bit + * @arg SDIOC_RESP_REG_BIT96_127: Command Response Register 96-127bit + * @param [out] pu32Value Pointer to a Response value + * @retval int32_t: + * - LL_OK: Get response success + * - LL_ERR_INVD_PARAM: pu32Value == NULL + */ +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pu32Value) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_RESP_REG(u8Reg)); + + *pu32Value = READ_REG32(*SDIOC_RESP_ADDR(SDIOCx, u8Reg)); + } + + return i32Ret; +} + +/** + * @brief Configure the SDIOCx data parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx data parameters success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + uint16_t u16BlkCnt; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BLOCK_SIZE(pstcDataConfig->u16BlockSize)); + DDL_ASSERT(IS_SDIOC_TRANS_DIR(pstcDataConfig->u16TransDir)); + DDL_ASSERT(IS_SDIOC_AUTO_SEND_CMD12(pstcDataConfig->u16AutoCmd12)); + DDL_ASSERT(IS_SDIOC_TRANS_MD(pstcDataConfig->u16TransMode)); + DDL_ASSERT(IS_SDIOC_DATA_TIMEOUT_TIME(pstcDataConfig->u16DataTimeout)); + + if (SDIOC_TRANS_MD_STOP_MULTI == pstcDataConfig->u16TransMode) { + u16BlkCnt = 0U; + } else { + u16BlkCnt = pstcDataConfig->u16BlockCount; + } + /* Set the SDIOC Data Transfer Timeout value */ + WRITE_REG8(SDIOCx->TOUTCON, pstcDataConfig->u16DataTimeout); + /* Set the SDIOC Block Count value */ + WRITE_REG16(SDIOCx->BLKSIZE, pstcDataConfig->u16BlockSize); + /* Set the SDIOC Block Size value */ + WRITE_REG16(SDIOCx->BLKCNT, u16BlkCnt); + /* Set the SDIOC Data Transfer Mode */ + WRITE_REG16(SDIOCx->TRANSMODE, ((pstcDataConfig->u16TransDir | pstcDataConfig->u16AutoCmd12 | + pstcDataConfig->u16TransMode) & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_data_config_t to default values. + * @param [out] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDataConfig->u16BlockSize = 512U; + pstcDataConfig->u16BlockCount = 0U; + pstcDataConfig->u16TransDir = SDIOC_TRANS_DIR_TO_CARD; + pstcDataConfig->u16AutoCmd12 = SDIOC_AUTO_SEND_CMD12_DISABLE; + pstcDataConfig->u16TransMode = SDIOC_TRANS_MD_SINGLE; + pstcDataConfig->u16DataTimeout = SDIOC_DATA_TIMEOUT_CLK_2E13; + } + + return i32Ret; +} + +/** + * @brief Read data from SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Read data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = READ_REG32(*BUF_REG); + au8Data[i] = (uint8_t)(u32Temp & 0xFFUL); + au8Data[i + 1U] = (uint8_t)((u32Temp >> 8U) & 0xFFUL); + au8Data[i + 2U] = (uint8_t)((u32Temp >> 16U) & 0xFFUL); + au8Data[i + 3U] = (uint8_t)((u32Temp >> 24U) & 0xFFUL); + } + } + + return i32Ret; +} + +/** + * @brief Write data to SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Write data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = ((uint32_t)au8Data[i + 3U] << 24U) | ((uint32_t)au8Data[i + 2U] << 16U) | + ((uint32_t)au8Data[i + 1U] << 8U) | au8Data[i]; + WRITE_REG32(*BUF_REG, u32Temp); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable block gap stop. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } +} + +/** + * @brief Restart data transfer. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval None + */ +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_CR); +} + +/** + * @brief Enable or disable read wait. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } +} + +/** + * @brief Enable or disable data block gap interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } +} + +/** + * @brief Enable or disable interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } +} + +/** + * @brief Get interrupt enable state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: The interrupt is enable + * - DISABLE: The interrupt is disable + */ +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + en_functional_state_t enIntSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (0U != u16NormalInt) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt))) { + enIntSta = ENABLE; + } + } + if ((0U != u16ErrorInt) && (enIntSta != ENABLE)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt))) { + enIntSta = ENABLE; + } + } + + return enIntSta; +} + +/** + * @brief Get interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_EI: Error interrupt flag + * @arg SDIOC_INT_FLAG_CINT: Card interrupt flag + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_ALL: All of the above + * @arg SDIOC_NORMAL_INT_FLAG_ALL: All of the normal interrupt flag + * @arg SDIOC_ERR_INT_FLAG_ALL: All of the error interrupt flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTST, u16NormalFlag))) { + enFlagSta = SET; + } + } + if ((0U != u16ErrorFlag) && (enFlagSta != SET)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTST, u16ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_CLR_ALL: All of the above + * @retval None + */ +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLR_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + WRITE_REG16(SDIOCx->NORINTST, u16NormalFlag); + } + if (0U != u16ErrorFlag) { + WRITE_REG16(SDIOCx->ERRINTST, u16ErrorFlag); + } +} + +/** + * @brief Enable or disable interrupt status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } +} + +/** + * @brief Get Host status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Host flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_HOST_FLAG_CMDL: CMD Line Level flag + * @arg SDIOC_HOST_FLAG_DATL: DAT[3:0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D0: DAT[0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D1: DAT[1] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D2: DAT[2] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D3: DAT[3] Line Level flag + * @arg SDIOC_HOST_FLAG_WPL: Write Protect Line Level flag + * @arg SDIOC_HOST_FLAG_CDL: Card Detect Line Level flag + * @arg SDIOC_HOST_FLAG_CSS: Device Stable flag + * @arg SDIOC_HOST_FLAG_CIN: Device Inserted flag + * @arg SDIOC_HOST_FLAG_BRE: Data buffer full flag + * @arg SDIOC_HOST_FLAG_BWE: Data buffer empty flag + * @arg SDIOC_HOST_FLAG_RTA: Read operation flag + * @arg SDIOC_HOST_FLAG_WTA: Write operation flag + * @arg SDIOC_HOST_FLAG_DA: DAT Line transfer flag + * @arg SDIOC_HOST_FLAG_CID: Command Inhibit with data flag + * @arg SDIOC_HOST_FLAG_CIC: Command Inhibit flag + * @arg SDIOC_HOST_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_HOST_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Get auto CMD12 error status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Flag Auto CMD12 error flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CMDE: Command Not Issued By Auto CMD12 error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_IE: Auto CMD12 Index error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_EBE: Auto CMD12 End Bit error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CE: Auto CMD12 CRC error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_TOE: Auto CMD12 Timeout error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_NE: Auto CMD12 Not Executed flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_AUTO_CMD_ERR_FLAG(u16Flag)); + + if (0U != (READ_REG16_BIT(SDIOCx->ATCERRST, u16Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Force the specified auto CMD12 error event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Auto CMD12 error event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCMDE: Force Event for Command Not Issued By Auto CMD12 error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FIE: Force Event for Auto CMD12 Index error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FEBE: Force Event for Auto CMD12 End Bit error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCE: Force Event for Auto CMD12 CRC error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FTOE: Force Event for Auto CMD12 Timeout error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FNE: Force Event for Auto CMD12 Not Executed + * @arg SDIOC_FORCE_AUTO_CMD_ERR_ALL: All of the above + * @retval None + */ +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_AUTO_CMD_ERR(u16Event)); + + WRITE_REG16(SDIOCx->FEA, u16Event); +} + +/** + * @brief Force the specified error interrupt event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Error interrupt event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_ERR_INT_FACE: Force Event for Auto CMD12 error + * @arg SDIOC_FORCE_ERR_INT_FDEBE: Force Event for Data End Bit error + * @arg SDIOC_FORCE_ERR_INT_FDCE: Force Event for Data CRC error + * @arg SDIOC_FORCE_ERR_INT_FDTOE: Force Event for Data Timeout error + * @arg SDIOC_FORCE_ERR_INT_FCIE: Force Event for Command Index error + * @arg SDIOC_FORCE_ERR_INT_FCEBE: Force Event for Command End Bit error + * @arg SDIOC_FORCE_ERR_INT_FCCE: Force Event for Command CRC error + * @arg SDIOC_FORCE_ERR_INT_FCTOE: Force Event for Command Timeout error + * @arg SDIOC_FORCE_ERR_INT_ALL: All of the above + * @retval None + */ +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_ERR_INT(u16Event)); + + WRITE_REG16(SDIOCx->FEE, u16Event); +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32ErrStatus = SDMMC_ERR_NONE; + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD0_GO_IDLE_STATE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_NO; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdError(SDIOCx); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CID command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD2_ALL_SEND_CID; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command for asking the card to publish a new relative address(RCA). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to the new RCA value + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu16RCA == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if ((NULL == pu16RCA) || (NULL == pu32ErrStatus)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD3_SEND_RELATIVE_ADDR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp6(SDIOCx, pu16RCA, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Checks switchable function and switch card function. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD6_SWITCH_FUNC; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD7_SELECT_DESELECT_CARD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Interface Condition command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + stcCmdConfig.u32Argument = SDMMC_CMD8_CHECK_PATTERN; + stcCmdConfig.u16CmdIndex = SDIOC_CMD8_SEND_IF_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp7(SDIOCx, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD9_SEND_CSD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD12_STOP_TRANSMISSION; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT * 1000UL, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD13_SEND_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Data Block Length command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BlockLen Block length + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BlockLen; + stcCmdConfig.u16CmdIndex = SDIOC_CMD16_SET_BLOCKLEN; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD17_READ_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD18_READ_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD24_WRITE_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD25_WRITE_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD32_ERASE_WR_BLK_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD33_ERASE_WR_BLK_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Erase command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD38_ERASE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_MAX_ERASE_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD55_APP_CMD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BusWidth The data bus width + * This parameter can be one of the following values: + * @arg SDMMC_SCR_BUS_WIDTH_1BIT: 1 bit bus + * @arg SDMMC_SCR_BUS_WIDTH_4BIT: 4 bits bus + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BusWidth; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD6_SET_BUS_WIDTH; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status register command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD13_SD_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command asking the accessed card to send its operating condition register(OCR). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD41_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument | SDMMC_ACMD41_VOLT_WIN; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD41_SD_APP_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD51_SEND_SCR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Sends host capacity support information command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD1_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD1_SEND_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD35_ERASE_GROUP_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD36_ERASE_GROUP_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c new file mode 100644 index 0000000000..9eb5fb00a1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c @@ -0,0 +1,549 @@ +/** + ******************************************************************************* + * @file hc32_ll_smc.c + * @brief This file provides firmware functions to manage the EXMC_SMC + * (External Memory Controller: Static Memory Controller). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_smc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EXMC EXMC + * @brief External Memory Controller Driver Library + * @{ + */ + +/** + * @defgroup LL_SMC SMC + * @brief Static Memory Controller Driver Library + * @{ + */ + +#if (LL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Local_Macros EXMC_SMC Local Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Check_Parameters_Validity EXMC_SMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_SMC_MEMORY_WIDTH(x) \ +( ((x) == EXMC_SMC_MEMORY_WIDTH_16BIT) || \ + ((x) == EXMC_SMC_MEMORY_WIDTH_32BIT)) + +#define IS_EXMC_SMC_READ_MD(x) \ +( ((x) == EXMC_SMC_READ_SYNC) || \ + ((x) == EXMC_SMC_READ_ASYNC)) + +#define IS_EXMC_SMC_WRITE_MD(x) \ +( ((x) == EXMC_SMC_WRITE_SYNC) || \ + ((x) == EXMC_SMC_WRITE_ASYNC)) + +#define IS_EXMC_SMC_CHIP(x) \ +( ((x) == EXMC_SMC_CHIP0) || \ + ((x) == EXMC_SMC_CHIP1) || \ + ((x) == EXMC_SMC_CHIP2) || \ + ((x) == EXMC_SMC_CHIP3)) + +#define IS_EXMC_SMC_READ_BURST(x) \ +( ((x) == EXMC_SMC_READ_BURST_1BEAT) || \ + ((x) == EXMC_SMC_READ_BURST_4BEAT) || \ + ((x) == EXMC_SMC_READ_BURST_8BEAT) || \ + ((x) == EXMC_SMC_READ_BURST_16BEAT) || \ + ((x) == EXMC_SMC_READ_BURST_32BEAT) || \ + ((x) == EXMC_SMC_READ_BURST_CONTINUOUS)) + +#define IS_EXMC_SMC_WRITE_BURST(x) \ +( ((x) == EXMC_SMC_WRITE_BURST_1BEAT) || \ + ((x) == EXMC_SMC_WRITE_BURST_4BEAT) || \ + ((x) == EXMC_SMC_WRITE_BURST_8BEAT) || \ + ((x) == EXMC_SMC_WRITE_BURST_16BEAT) || \ + ((x) == EXMC_SMC_WRITE_BURST_32BEAT) || \ + ((x) == EXMC_SMC_WRITE_BURST_CONTINUOUS)) + +#define IS_EXMC_SMC_BLS_SYNC(x) \ +( ((x) == EXMC_SMC_BLS_SYNC_CS) || \ + ((x) == EXMC_SMC_BLS_SYNC_WE)) + +#define IS_EXMC_SMC_BAA_PORT(x) \ +( ((x) == EXMC_SMC_BAA_PORT_DISABLE) || \ + ((x) == EXMC_SMC_BAA_PORT_ENABLE)) + +#define IS_EXMC_SMC_ADV_PORT(x) \ +( ((x) == EXMC_SMC_ADV_PORT_DISABLE) || \ + ((x) == EXMC_SMC_ADV_PORT_ENABLE)) + +#define IS_EXMC_SMC_CMD(x) \ +( ((x) == EXMC_SMC_CMD_MDREGCONFIG) || \ + ((x) == EXMC_SMC_CMD_UPDATEREGS) || \ + ((x) == EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS)) + +#define IS_EXMC_SMC_CRE_POLARITY(x) \ +( ((x) == EXMC_SMC_CRE_POLARITY_LOW) || \ + ((x) == EXMC_SMC_CRE_POLARITY_HIGH)) + +#define IS_EXMC_SMC_SAMPLE_CLK(x) \ +( ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK) || \ + ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT) || \ + ((x) == EXMC_SMC_SAMPLE_CLK_EXTCLK)) + +#define IS_EXMC_SMC_MAP_ADDR(match, msk) \ +( (EXMC_SMC_MAP_ADDR((match), (msk)) >= EXMC_SMC_ADDR_MIN) && \ + (EXMC_SMC_MAP_ADDR((match), (msk)) <= EXMC_SMC_ADDR_MAX)) + +#define IS_EXMC_SMC_REFRESH_PERIOD(x) ((x) <= (uint8_t)SMC_RFTR_REFPRD) + +#define IS_EXMC_SMC_CMD_ADDR(x) ((x) <= 0xFFFFFUL) + +#define IS_EXMC_SMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_WC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_CEOE_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_WP_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_PC_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_TR_CYCLE(x) ((x) <= 7UL) + +/** + * @} + */ + +/* EXMC_SMC map address */ +#define EXMC_SMC_MAP_ADDR(MATCH, MSK) ((~((MATCH) ^ (MSK))) << 24U) + +/** + * @defgroup EXMC_SMC_Register EXMC_SMC Register + * @{ + */ +#define EXMC_SMC_CPSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->CPSR0)) + (0x20UL * (__CHIPx__)))) +#define EXMC_SMC_TMSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->TMSR0)) + (0x20UL * (__CHIPx__)))) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Register_Bit_Mask EXMC_SMC Register Bit Mask + * @{ + */ +#define SMC_CSCR0_ADDMSKx_POS(__CHIPx__) (((__CHIPx__) & EXMC_SMC_CHIP3) << 3U) +#define SMC_CSCR0_ADDMSKx(__CHIPx__) (SMC_CSCR0_ADDMSK0 << SMC_CSCR0_ADDMSKx_POS((__CHIPx__))) + +#define SMC_CSCR1_ADDMATx_POS(__CHIPx__) (((__CHIPx__) & EXMC_SMC_CHIP3) << 3U) +#define SMC_CSCR1_ADDMATx(__CHIPx__) (SMC_CSCR1_ADDMAT0 << SMC_CSCR1_ADDMATx_POS((__CHIPx__))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Functions EXMC_SMC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure @ref stc_exmc_smc_init_t to default values + * @param [out] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL. + */ +int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmcInit) { + pstcSmcInit->stcChipConfig.u32ReadMode = EXMC_SMC_READ_ASYNC; + pstcSmcInit->stcChipConfig.u32ReadBurstLen = EXMC_SMC_READ_BURST_1BEAT; + pstcSmcInit->stcChipConfig.u32WriteMode = EXMC_SMC_WRITE_ASYNC; + pstcSmcInit->stcChipConfig.u32WriteBurstLen = EXMC_SMC_WRITE_BURST_1BEAT; + pstcSmcInit->stcChipConfig.u32MemoryWidth = EXMC_SMC_MEMORY_WIDTH_16BIT; + pstcSmcInit->stcChipConfig.u32BAA = EXMC_SMC_BAA_PORT_DISABLE; + pstcSmcInit->stcChipConfig.u32ADV = EXMC_SMC_ADV_PORT_DISABLE; + pstcSmcInit->stcChipConfig.u32BLS = EXMC_SMC_BLS_SYNC_CS; + pstcSmcInit->stcChipConfig.u32AddrMask = 0xF8UL; /* Address space 128M: 0x60000000 ~ 0x67FFFFFF */ + pstcSmcInit->stcChipConfig.u32AddrMatch = 0x60UL; + + pstcSmcInit->stcTimingConfig.u8RC = 7U; + pstcSmcInit->stcTimingConfig.u8WC = 7U; + pstcSmcInit->stcTimingConfig.u8CEOE = 1U; + pstcSmcInit->stcTimingConfig.u8WP = 5U; + pstcSmcInit->stcTimingConfig.u8PC = 0U; + pstcSmcInit->stcTimingConfig.u8TR = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EXMC_SMC function. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @param [in] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL. + */ +int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit) +{ + uint32_t u32RegVal; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmcInit) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_READ_MD(pstcSmcInit->stcChipConfig.u32ReadMode)); + DDL_ASSERT(IS_EXMC_SMC_WRITE_MD(pstcSmcInit->stcChipConfig.u32WriteMode)); + DDL_ASSERT(IS_EXMC_SMC_READ_BURST(pstcSmcInit->stcChipConfig.u32ReadBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_WRITE_BURST(pstcSmcInit->stcChipConfig.u32WriteBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_MEMORY_WIDTH(pstcSmcInit->stcChipConfig.u32MemoryWidth)); + DDL_ASSERT(IS_EXMC_SMC_BAA_PORT(pstcSmcInit->stcChipConfig.u32BAA)); + DDL_ASSERT(IS_EXMC_SMC_ADV_PORT(pstcSmcInit->stcChipConfig.u32ADV)); + DDL_ASSERT(IS_EXMC_SMC_BLS_SYNC(pstcSmcInit->stcChipConfig.u32BLS)); + DDL_ASSERT(IS_EXMC_SMC_MAP_ADDR(pstcSmcInit->stcChipConfig.u32AddrMatch, pstcSmcInit->stcChipConfig.u32AddrMask)); + + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcSmcInit->stcTimingConfig.u8RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WC_CYCLE(pstcSmcInit->stcTimingConfig.u8WC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_CEOE_CYCLE(pstcSmcInit->stcTimingConfig.u8CEOE)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WP_CYCLE(pstcSmcInit->stcTimingConfig.u8WP)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcSmcInit->stcTimingConfig.u8RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_TR_CYCLE(pstcSmcInit->stcTimingConfig.u8TR)); + + /* Set SMC timing.*/ + u32RegVal = (((uint32_t)pstcSmcInit->stcTimingConfig.u8RC << SMC_TMCR_T_RC_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8WC << SMC_TMCR_T_WC_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8CEOE << SMC_TMCR_T_CEOE_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8WP << SMC_TMCR_T_WP_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8PC << SMC_TMCR_T_PC_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8TR << SMC_TMCR_T_TR_POS)); + WRITE_REG32(CM_SMC->TMCR, u32RegVal); + + /* Set SMC chip configuration.*/ + u32RegVal = (pstcSmcInit->stcChipConfig.u32ReadMode | \ + pstcSmcInit->stcChipConfig.u32ReadBurstLen | \ + pstcSmcInit->stcChipConfig.u32WriteMode | \ + pstcSmcInit->stcChipConfig.u32WriteBurstLen | \ + pstcSmcInit->stcChipConfig.u32MemoryWidth | \ + pstcSmcInit->stcChipConfig.u32BAA | \ + pstcSmcInit->stcChipConfig.u32ADV | \ + pstcSmcInit->stcChipConfig.u32BLS); + WRITE_REG32(CM_SMC->CPCR, u32RegVal); + + /* Set chip selection address match/mask spacefor SMC.*/ + MODIFY_REG32(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip), \ + (pstcSmcInit->stcChipConfig.u32AddrMask << SMC_CSCR0_ADDMSKx_POS(u32Chip))); + MODIFY_REG32(CM_SMC->CSCR1, SMC_CSCR0_ADDMSKx(u32Chip), \ + (pstcSmcInit->stcChipConfig.u32AddrMatch << SMC_CSCR1_ADDMATx_POS(u32Chip))); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EXMC_SMC function. + * @param None + * @retval None + */ +void EXMC_SMC_DeInit(void) +{ + /* Disable SMC */ + CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + + /* Set SMC timing.*/ + WRITE_REG32(CM_SMC->TMCR, 0UL); + + /* Set SMC chip configuration.*/ + WRITE_REG32(CM_SMC->CPCR, 0UL); +} + +/** + * @brief Enable/Disable SMC. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_SMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + } else { + CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + } +} + +/** + * @brief Enable or disable SMC pin mux. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD); + } else { + CLR_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD); + } +} + +/** + * @brief Set SMC sample clock. + * @param [in] u32SampleClock Sample clock + * This parameter can be one of the macros group @ref EXMC_SMC_Command + * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK: Internal EXCLK + * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT: Invert internal EXCLK + * @arg EXMC_SMC_SAMPLE_CLK_EXTCLK: External clock from EXMC_CLK port + * @retval None + */ +void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock) +{ + DDL_ASSERT(IS_EXMC_SMC_SAMPLE_CLK(u32SampleClock)); + + MODIFY_REG32(CM_SMC->BACR, SMC_BACR_CKSEL, u32SampleClock); +} + +/** + * @brief Set SMC refresh period value + * @param [in] u8PeriodVal The SMC refresh period value + * @arg This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F + * @retval None + */ +void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal) +{ + DDL_ASSERT(IS_EXMC_SMC_REFRESH_PERIOD(u8PeriodVal)); + + WRITE_REG32(CM_SMC->RFTR, u8PeriodVal); +} + +/** + * @brief Set EXMC_SMC command. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @param [in] u32Cmd The command. + * This parameter can be one of the macros group @ref EXMC_SMC_Command + * @arg EXMC_SMC_CMD_MDREGCONFIG: Configure mode register + * @arg EXMC_SMC_CMD_UPDATEREGS: Update mode register + * @arg EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS: Configure mode register and update + * @param [in] u32CrePolarity The command. + * This parameter can be one of the macros group @ref EXMC_SMC_CRE_Polarity + * @arg EXMC_SMC_CRE_POLARITY_LOW: CRE is LOW + * @arg EXMC_SMC_CRE_POLARITY_HIGH: CRE is HIGH when ModeReg write occurs + * @param [in] u32Addr The address parameter is valid when CMD type is MdRegConfig or MdRegConfig + * and UpdateRegs only. + * @retval None + */ +void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr) +{ + uint32_t u32SmcCmdr; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_CMD(u32Cmd)); + DDL_ASSERT(IS_EXMC_SMC_CRE_POLARITY(u32CrePolarity)); + DDL_ASSERT(IS_EXMC_SMC_CMD_ADDR(u32Addr)); + + /* Set SMC_CMDR register for SMC.*/ + u32SmcCmdr = (u32Addr | u32CrePolarity | u32Cmd | (u32Chip << SMC_CMDR_CMDCHIP_POS)); + WRITE_REG32(CM_SMC->CMDR, u32SmcCmdr); +} + +/** + * @brief Get the start address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @retval The start address of the specified SMC chip. + */ +uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip) +{ + uint32_t u32Match; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32Match = READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip); + return (u32Match << 24U); +} + +/** + * @brief Get the end address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @retval The end address of the specified SMC chip + */ +uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip) +{ + uint32_t u32Mask; + uint32_t u32Match; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32Mask = (READ_REG32_BIT(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip)) >> SMC_CSCR0_ADDMSKx_POS(u32Chip)); + u32Match = (READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip)); + + return (~((u32Match ^ u32Mask) << 24U)); +} + +/** + * @brief Get SMC chip configure. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @param [in] pstcChipConfig Pointer to a @ref stc_exmc_smc_chip_config_t structure. + * @retval int32_t: + * - LL_OK: Get successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcChipConfig value is NULL. + */ +int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig) +{ + __IO uint32_t *SMC_CPSRx; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcChipConfig) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + SMC_CPSRx = EXMC_SMC_CPSRx(u32Chip); + pstcChipConfig->u32ReadMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_RSYN); + pstcChipConfig->u32ReadBurstLen = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_RBL); + pstcChipConfig->u32WriteMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_WSYN); + pstcChipConfig->u32WriteBurstLen = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_WBL); + pstcChipConfig->u32MemoryWidth = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_MW); + pstcChipConfig->u32BAA = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BAAS); + pstcChipConfig->u32ADV = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADVS); + pstcChipConfig->u32BLS = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BLSS); + pstcChipConfig->u32AddrMask = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMSK) >> SMC_CPSR_ADDMSK_POS; + pstcChipConfig->u32AddrMatch = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMAT) >> SMC_CPSR_ADDMAT_POS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get SMC timing configure. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @arg EXMC_SMC_CHIP0: Chip 0 + * @arg EXMC_SMC_CHIP1: Chip 1 + * @arg EXMC_SMC_CHIP2: Chip 2 + * @arg EXMC_SMC_CHIP3: Chip 3 + * @param [in] pstcTimingConfig Pointer to a @ref stc_exmc_smc_timing_config_t structure. + * @retval int32_t: + * - LL_OK: Get successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTimingConfig value is NULL. + */ +int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig) +{ + __IO uint32_t *SMC_TMSRx; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTimingConfig) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + SMC_TMSRx = EXMC_SMC_TMSRx(u32Chip); + pstcTimingConfig->u8RC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_RC) >> SMC_TMCR_T_RC_POS); + pstcTimingConfig->u8WC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WC) >> SMC_TMCR_T_WC_POS); + pstcTimingConfig->u8CEOE = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_CEOE) >> SMC_TMCR_T_CEOE_POS); + pstcTimingConfig->u8WP = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WP) >> SMC_TMCR_T_WP_POS); + pstcTimingConfig->u8PC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_PC) >> SMC_TMCR_T_PC_POS); + pstcTimingConfig->u8TR = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_TR) >> SMC_TMCR_T_TR_POS); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SMC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c new file mode 100644 index 0000000000..e140c5d2a7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c @@ -0,0 +1,884 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_spi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ + +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +#define SPI_SR_DEFAULT (0x00000020UL) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( (CM_SPI1 == (x)) || \ + (CM_SPI2 == (x)) || \ + (CM_SPI3 == (x)) || \ + (CM_SPI4 == (x)) || \ + (CM_SPI5 == (x)) || \ + (CM_SPI6 == (x))) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MD(x) \ +( ((x) == SPI_4_WIRE) || \ + ((x) == SPI_3_WIRE)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MD(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_LOOPBACK_INVD) || \ + ((x) == SPI_LOOPBACK_MOSI_INVT) || \ + ((x) == SPI_LOOPBACK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSPD_MD_STD(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_1_FRAME) || \ + ((x) == SPI_2_FRAME) || \ + ((x) == SPI_3_FRAME) || \ + ((x) == SPI_4_FRAME)) + +/*! Parameter valid check for SPI fault dectet function status */ +#define IS_SPI_MD_FAULT_DETECT_CMD(x) \ +( ((x) == SPI_MD_FAULT_DETECT_DISABLE) || \ + ((x) == SPI_MD_FAULT_DETECT_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVD) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK) || \ + ((x) == SPI_INTERVAL_TIME_2SCK) || \ + ((x) == SPI_INTERVAL_TIME_3SCK) || \ + ((x) == SPI_INTERVAL_TIME_4SCK) || \ + ((x) == SPI_INTERVAL_TIME_5SCK) || \ + ((x) == SPI_INTERVAL_TIME_6SCK) || \ + ((x) == SPI_INTERVAL_TIME_7SCK) || \ + ((x) == SPI_INTERVAL_TIME_8SCK)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MD(x) \ +( ((x) == SPI_MD_0) || \ + ((x) == SPI_MD_1) || \ + ((x) == SPI_MD_2) || \ + ((x) == SPI_MD_3)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_BIT_RATE_DIV(x) \ +( ((x) == SPI_BR_CLK_DIV2) || \ + ((x) == SPI_BR_CLK_DIV4) || \ + ((x) == SPI_BR_CLK_DIV8) || \ + ((x) == SPI_BR_CLK_DIV16) || \ + ((x) == SPI_BR_CLK_DIV32) || \ + ((x) == SPI_BR_CLK_DIV64) || \ + ((x) == SPI_BR_CLK_DIV128) || \ + ((x) == SPI_BR_CLK_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for SPI Communication mode */ +#define IS_SPI_COMM_MD(x) \ +( ((x) == SPI_COMM_MD_NORMAL) || \ + ((x) == SPI_COMM_MD_CONTINUE)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_IRQ_ALL) == SPI_IRQ_ALL)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_ALL) == SPI_FLAG_ALL)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_CLR_ALL) == SPI_FLAG_CLR_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Func SPI Local Functions + * @{ + */ + +/** + * @brief SPI check status. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32FlagMask Bit mask of status flag. + * @param [in] u32Value Valid value of the status. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_WaitStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32FlagMask, uint32_t u32Value, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + + while (READ_REG32_BIT(SPIx->SR, u32FlagMask) != u32Value) { + if (u32Timeout == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Timeout--; + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Len The length of the data in byte or half word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + */ +static int32_t SPI_TxRx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32BitSize; + __IO uint32_t u32Count = 0U; + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Len) { + if (pvTxBuf != NULL) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + } else { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + } + + /* Check RX buffer. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_RX_BUF_FULL, SPI_FLAG_RX_BUF_FULL, u32Timeout); + if (i32Ret == LL_OK) { + u32Tmp = READ_REG32(SPIx->DR); + if (pvRxBuf != NULL) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32Count] = (uint8_t)u32Tmp; + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32Count] = (uint16_t)u32Tmp; + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32Count] = (uint32_t)u32Tmp; + } + } else { + /* Dummy read */ + u32Read = READ_REG32(SPIx->DR); + } + u32Count++; + } + } + if (i32Ret == LL_OK) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Len The length of the data in byte or half word or word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_Tx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + __IO uint32_t u32Count = 0U; + uint32_t u32BitSize; + int32_t i32Ret = LL_OK; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Len) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, u32Timeout); + if (i32Ret != LL_OK) { + break; + } + u32Count++; + } + if (i32Ret == LL_OK) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL or configuration parameter error. + */ + +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcSpiInit) { + DDL_ASSERT(IS_SPI_WIRE_MD(pstcSpiInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MD(pstcSpiInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcSpiInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_MD_FAULT_DETECT_CMD(pstcSpiInit->u32ModeFaultDetect)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcSpiInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MD(pstcSpiInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_BIT_RATE_DIV(pstcSpiInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcSpiInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcSpiInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_SUSPD_MD_STD(pstcSpiInit->u32SuspendMode)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcSpiInit->u32FrameLevel)); + + /* Configuration parameter check */ + if ((SPI_MASTER == pstcSpiInit->u32MasterSlave) && (SPI_MD_FAULT_DETECT_ENABLE == pstcSpiInit->u32ModeFaultDetect)) { + /* pstcSpiInit->u32ModeFaultDetect can not be SPI_MD_FAULT_DETECT_ENABLE in master mode */ + } else if ((SPI_3_WIRE == pstcSpiInit->u32WireMode) && (SPI_SLAVE == pstcSpiInit->u32MasterSlave) + && ((SPI_MD_0 == pstcSpiInit->u32SpiMode) || (SPI_MD_2 == pstcSpiInit->u32SpiMode))) { + /* SPI_3_WIRE can not support SPI_MD_0 and SPI_MD_2 */ + } else { + WRITE_REG32(SPIx->CR1, pstcSpiInit->u32WireMode | pstcSpiInit->u32TransMode | pstcSpiInit->u32MasterSlave + | pstcSpiInit->u32SuspendMode | pstcSpiInit->u32ModeFaultDetect | pstcSpiInit->u32Parity); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcSpiInit->u32FrameLevel); + WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32BaudRatePrescaler | pstcSpiInit->u32DataBits + | pstcSpiInit->u32FirstBit); + i32Ret = LL_OK; + } + } + return i32Ret; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval None + */ +void SPI_DeInit(CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + WRITE_REG32(SPIx->CR1, 0UL); + WRITE_REG32(SPIx->CFG1, SPI_CFG1_DEFAULT); + WRITE_REG32(SPIx->CFG2, SPI_CFG2_DEFAULT); + WRITE_REG32(SPIx->SR, SPI_SR_DEFAULT); +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL. + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSpiInit) { + pstcSpiInit->u32WireMode = SPI_4_WIRE; + pstcSpiInit->u32TransMode = SPI_FULL_DUPLEX; + pstcSpiInit->u32MasterSlave = SPI_MASTER; + pstcSpiInit->u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; + pstcSpiInit->u32Parity = SPI_PARITY_INVD; + pstcSpiInit->u32SpiMode = SPI_MD_0; + pstcSpiInit->u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + pstcSpiInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcSpiInit->u32FirstBit = SPI_FIRST_MSB; + pstcSpiInit->u32SuspendMode = SPI_COM_SUSP_FUNC_OFF; + pstcSpiInit->u32FrameLevel = SPI_1_FRAME; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Int_Type_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_INT(u32IntType)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(SPIx->CR1, u32IntType); + } else { + CLR_REG32_BIT(SPIx->CR1, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval uint32_t A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = RESET; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_STD_FLAG(u32Flag)); + + if (0U != READ_REG32_BIT(SPIx->SR, u32Flag)) { + enFlag = SET; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_MD_FAULT + * @arg SPI_FLAG_PARITY_ERR + * @arg SPI_FLAG_UNDERLOAD + * @retval None + */ +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_STD_FLAG(u32Flag)); + + CLR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Mode Loopback mode. Can be one parameter @ref SPI_Loopback_Selection_Define + * @retval None + */ +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->CR1, SPI_CR1_SPLPBK | SPI_CR1_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ + +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL + */ +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayConfig) { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayConfig->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayConfig->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayConfig->u32SetupDelay)); + + /* Interval delay */ + if (SPI_INTERVAL_TIME_1SCK == pstcDelayConfig->u32IntervalDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } else { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayConfig->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if (SPI_RELEASE_TIME_1SCK == pstcDelayConfig->u32ReleaseDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayConfig->u32ReleaseDelay); + } + + /* Setup delay */ + if (SPI_SETUP_TIME_1SCK == pstcDelayConfig->u32SetupDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayConfig->u32SetupDelay); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL. + */ +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDelayConfig) { + pstcDelayConfig->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK; + pstcDelayConfig->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayConfig->u32SetupDelay = SPI_SETUP_TIME_1SCK; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } else { + CLR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegConfig; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) { + case SPI_PIN_SS0: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegConfig = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegConfig = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegConfig = SPI_SS3_VALID_CFG; + break; + + default: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegConfig); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buf_Define + * @retval None + */ +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLen The length of the data to be sent. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit timeout. + * - LL_ERR_INVD_PARAM: pvTxBuf == NULL or u32TxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function supports full duplex mode and send only mode. + */ +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout) +{ + uint32_t u32Flags; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (u32TxLen != 0U)) { + u32Flags = READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); + if (u32Flags == SPI_SEND_ONLY) { + /* Transmit data in send only mode. */ + i32Ret = SPI_Tx(SPIx, pvTxBuf, u32TxLen, u32Timeout); + } else { + /* Transmit data in full duplex mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLen, u32Timeout); + } + } + return i32Ret; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLen The length of the data to be received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or u32RxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function only works in full duplex master mode. + */ +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvRxBuf != NULL) && (u32RxLen != 0U)) { + /* Receives data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLen, u32Timeout); + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Len The length of the data(in byte or half word) to be sent and received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or pvRxBuf == NULL or u32Len == 0U + * @note SPI receives data while sending data. Only works in full duplex master mode. + */ +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Len != 0U)) { + /* Transmit and receive data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Len, u32Timeout); + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c new file mode 100644 index 0000000000..28b9b47d46 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c @@ -0,0 +1,307 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.c + * @brief This file provides firmware functions to manage the SRAM. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sram.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SRAM SRAM + * @brief SRAM Driver Library + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Local_Macros SRAM Local Macros + * @{ + */ + +/** + * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask + * @{ + */ +#define SRAM_ECC_MD_MASK (SRAMC_CKCR_ECCMOD) +#define SRAM_CYCLE_MASK (0x00000007UL) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity + * @{ + */ +#define IS_SRAM_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_SRAM_ERR_MD(x) (((x) == SRAM_ERR_MD_NMI) || ((x) == SRAM_ERR_MD_RST)) + +#define IS_SRAM_WAIT_CYCLE(x) ((x) <= SRAM_WAIT_CYCLE7) + +#define IS_SRAM_SEL(x) IS_SRAM_BIT_MASK(x, SRAM_SRAM_ALL) + +#define IS_SRAM_ECC_SRAM(x) IS_SRAM_BIT_MASK(x, SRAM_ECC_SRAM4 | SRAM_ECC_SRAMB) + +#define IS_SRAM_FLAG(x) IS_SRAM_BIT_MASK(x, SRAM_FLAG_ALL) + +#define IS_SRAM_WTPR_UNLOCK() (CM_SRAMC->WTPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_CKPR_UNLOCK() (CM_SRAMC->CKPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_ECC_MD(x) \ +( ((x) == SRAM_ECC_MD_INVD) || \ + ((x) == SRAM_ECC_MD1) || \ + ((x) == SRAM_ECC_MD2) || \ + ((x) == SRAM_ECC_MD3)) + +/* Error injection */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Functions SRAM Global Functions + * @{ + */ + +/** + * @brief Initializes SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief De-initializes SRAM. RESET the registers of SRAM. + * @param None + * @retval None + * @note Call SRAM_REG_Unlock to unlock registers WTCR and CKCR first. + */ +void SRAM_DeInit(void) +{ + /* Call SRAM_REG_Unlock to unlock register WTCR and CKCR. */ + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + WRITE_REG32(CM_SRAMC->WTCR, 0U); + WRITE_REG32(CM_SRAMC->CKCR, 0U); + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief Specifies access wait cycle for SRAM. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [in] u32WriteCycle The write access wait cycle for the specified SRAM + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @param [in] u32ReadCycle The read access wait cycle for the specified SRAM. + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @arg SRAM_WAIT_CYCLE0: Wait 0 CPU cycle. + * @arg SRAM_WAIT_CYCLE1: Wait 1 CPU cycle. + * @arg SRAM_WAIT_CYCLE2: Wait 2 CPU cycles. + * @arg SRAM_WAIT_CYCLE3: Wait 3 CPU cycles. + * @arg SRAM_WAIT_CYCLE4: Wait 4 CPU cycles. + * @arg SRAM_WAIT_CYCLE5: Wait 5 CPU cycles. + * @arg SRAM_WAIT_CYCLE6: Wait 6 CPU cycles. + * @arg SRAM_WAIT_CYCLE7: Wait 7 CPU cycles. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register WTCR first. + */ +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle) +{ + uint8_t i = 0U; + uint8_t u8OfsWt; + uint8_t u8OfsRd; + + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32WriteCycle)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32ReadCycle)); + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + + while (u32SramSel != 0UL) { + if ((u32SramSel & 0x1UL) != 0UL) { + u8OfsWt = i * 8U; + u8OfsRd = u8OfsWt + 4U; + MODIFY_REG32(CM_SRAMC->WTCR, + ((SRAM_CYCLE_MASK << u8OfsWt) | (SRAM_CYCLE_MASK << u8OfsRd)), + ((u32WriteCycle << u8OfsWt) | (u32ReadCycle << u8OfsRd))); + } + u32SramSel >>= 1U; + i++; + } +} + +/** + * @brief Specifies ECC mode. + * @param [in] u32SramSel The SRAM selection. This function is used to specify the + * ECC mode for members SRAM_ECC_XXXX of @ref SRAM_Sel + * @param [in] u32EccMode The ECC mode. + * This parameter can be a value of @ref SRAM_ECC_Mode + * @arg SRAM_ECC_MD_INVD: The ECC mode is invalid. + * @arg SRAM_ECC_MD1: When 1-bit error occurred: + * ECC error corrects. + * No 1-bit-error status flag setting, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD2: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD3: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets and interrupt or reset occurred. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode) +{ + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32SramSel)); + DDL_ASSERT(IS_SRAM_ECC_MD(u32EccMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & SRAM_SRAM4) != 0U) { + MODIFY_REG32(CM_SRAMC->CKCR, SRAM_ECC_MD_MASK, u32EccMode); + } + + if ((u32SramSel & SRAM_SRAMB) != 0U) { + MODIFY_REG32(CM_SRAMC->CKCR, SRAM_ECC_MD_MASK << 2U, u32EccMode << 2U); + } +} + +/** + * @brief Specifies the operation which is operated after check error occurred. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [out] u32ErrMode The operation after check error occurred. + * This parameter can be a value of @ref SRAM_Err_Mode + * @arg SRAM_ERR_MD_NMI: Check error generates NMI(non-maskable interrupt). + * @arg SRAM_ERR_MD_RST: Check error generates system reset. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode) +{ + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_ERR_MD(u32ErrMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & (SRAM_SRAM123 | SRAM_SRAMH)) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.PYOAD, u32ErrMode); + } + + if ((u32SramSel & SRAM_SRAM4) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.ECCOAD, u32ErrMode); + } + + if ((u32SramSel & SRAM_SRAMB) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.BECCOAD, u32ErrMode); + } +} + +/** + * @brief Get the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value of @ref SRAM_Err_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + if (READ_REG32_BIT(CM_SRAMC->CKSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be values of @ref SRAM_Err_Status_Flag + * @retval None + */ +void SRAM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + SET_REG32_BIT(CM_SRAMC->CKSR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c new file mode 100644 index 0000000000..048acc0db9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c @@ -0,0 +1,256 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.c + * @brief This file provides firmware functions to manage the Specialized Watch + * Dog Timer(SWDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_swdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SWDT SWDT + * @brief Specialized Watch Dog Timer + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Local_Macros SWDT Local Macros + * @{ + */ + +/* SWDT Refresh Key */ +#define SWDT_REFRESH_KEY_START (0x0123UL) +#define SWDT_REFRESH_KEY_END (0x3210UL) + +/* SWDT clear flag timeout(ms) */ +#define SWDT_CLR_FLAG_TIMEOUT (5UL) + +/* SWDT Registers Clear Mask */ +#define SWDT_CR_CLR_MASK (SWDT_CR_PERI | SWDT_CR_CKS | SWDT_CR_WDPT | \ + SWDT_CR_SLPOFF | SWDT_CR_ITS) + +/** + * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity + * @{ + */ + +#define IS_SWDT_CNT_PERIOD(x) \ +( ((x) == SWDT_CNT_PERIOD256) || \ + ((x) == SWDT_CNT_PERIOD4096) || \ + ((x) == SWDT_CNT_PERIOD16384) || \ + ((x) == SWDT_CNT_PERIOD65536)) + +#define IS_SWDT_CLK_DIV(x) \ +( ((x) == SWDT_CLK_DIV1) || \ + ((x) == SWDT_CLK_DIV16) || \ + ((x) == SWDT_CLK_DIV32) || \ + ((x) == SWDT_CLK_DIV64) || \ + ((x) == SWDT_CLK_DIV128) || \ + ((x) == SWDT_CLK_DIV256) || \ + ((x) == SWDT_CLK_DIV2048)) + +#define IS_SWDT_REFRESH_RANGE(x) \ +( ((x) == SWDT_RANGE_0TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT) || \ + ((x) == SWDT_RANGE_50TO75PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == SWDT_RANGE_25TO75PCT) || \ + ((x) == SWDT_RANGE_0TO75PCT) || \ + ((x) == SWDT_RANGE_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_50TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == SWDT_RANGE_25TO100PCT)) + +#define IS_SWDT_LPM_CNT(x) \ +( ((x) == SWDT_LPM_CNT_CONTINUE) || \ + ((x) == SWDT_LPM_CNT_STOP)) + +#define IS_SWDT_EXP_TYPE(x) \ +( ((x) == SWDT_EXP_TYPE_INT) || \ + ((x) == SWDT_EXP_TYPE_RST)) + +#define IS_SWDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SWDT_FLAG_ALL) == SWDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Initializes SWDT. + * @param [in] pstcSwdtInit Pointer to a @ref stc_swdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcSwdtInit == NULL + */ +int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSwdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SWDT_CNT_PERIOD(pstcSwdtInit->u32CountPeriod)); + DDL_ASSERT(IS_SWDT_CLK_DIV(pstcSwdtInit->u32ClockDiv)); + DDL_ASSERT(IS_SWDT_REFRESH_RANGE(pstcSwdtInit->u32RefreshRange)); + DDL_ASSERT(IS_SWDT_LPM_CNT(pstcSwdtInit->u32LPMCount)); + DDL_ASSERT(IS_SWDT_EXP_TYPE(pstcSwdtInit->u32ExceptionType)); + + /* SWDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_SWDT->CR, SWDT_CR_CLR_MASK, + (pstcSwdtInit->u32CountPeriod | pstcSwdtInit->u32ClockDiv | + pstcSwdtInit->u32RefreshRange | pstcSwdtInit->u32LPMCount | + pstcSwdtInit->u32ExceptionType)); + } + + return i32Ret; +} + +/** + * @brief SWDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void SWDT_FeedDog(void) +{ + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_START); + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_END); +} + +/** + * @brief Get SWDT flag status. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_SWDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear SWDT flag. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t SWDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_SWDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = SWDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_SWDT->SR, u32Flag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c new file mode 100644 index 0000000000..0cb858b1fe --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c @@ -0,0 +1,626 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.c + * @brief This file provides firmware functions to manage the TMR0 + * (TMR0). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr0.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR0 TMR0 + * @brief TMR0 Driver Library + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Local_Macros TMR0 Local Macros + * @{ + */ +/* Max channel number */ +#define TMR0_CH_MAX (2UL) + +#define TMR0_CLK_SRC_MASK (TMR0_BCONR_SYNSA | TMR0_BCONR_SYNCLKA | TMR0_BCONR_ASYNCLKA) +#define TMR0_BCONR_CLR_MASK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | TMR0_BCONR_HICPA | TMR0_CLK_SRC_MASK) + +/** + * @defgroup TMR0_Register_Address TMR0 Register Address + * @{ + */ +#define TMR0_CNTR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CNTAR)) + ((__CH__) << 2UL)) +#define TMR0_CMPR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CMPAR)) + ((__CH__) << 2UL)) +/** + * @} + */ +#define TMR0_CH_OFFSET(__CH__) ((__CH__) << 4U) + +/** + * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity + * @{ + */ +#define IS_TMR0_UNIT(x) \ +( ((x) == CM_TMR0_1) || \ + ((x) == CM_TMR0_2)) + +#define IS_TMR0_CH(x) \ +( ((x) == TMR0_CH_A) || \ + ((x) == TMR0_CH_B)) + +#define IS_TMR0_CLK_SRC(x) \ +( ((x) == TMR0_CLK_SRC_INTERN_CLK) || \ + ((x) == TMR0_CLK_SRC_SPEC_EVT) || \ + ((x) == TMR0_CLK_SRC_LRC) || \ + ((x) == TMR0_CLK_SRC_XTAL32)) + +#define IS_TMR0_CLK_DIV(x) \ +( ((x) == TMR0_CLK_DIV1) || \ + ((x) == TMR0_CLK_DIV2) || \ + ((x) == TMR0_CLK_DIV4) || \ + ((x) == TMR0_CLK_DIV8) || \ + ((x) == TMR0_CLK_DIV16) || \ + ((x) == TMR0_CLK_DIV32) || \ + ((x) == TMR0_CLK_DIV64) || \ + ((x) == TMR0_CLK_DIV128) || \ + ((x) == TMR0_CLK_DIV256) || \ + ((x) == TMR0_CLK_DIV512) || \ + ((x) == TMR0_CLK_DIV1024)) + +#define IS_TMR0_FUNC(x) \ +( ((x) == TMR0_FUNC_CMP) || \ + ((x) == TMR0_FUNC_CAPT)) + +#define IS_TMR0_INT(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_INT_ALL) == TMR0_INT_ALL)) + +#define IS_TMR0_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_FLAG_ALL) == TMR0_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Functions TMR0 Global Functions + * @{ + */ + +/** + * @brief De-Initialize TMR0 function + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @retval None + */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x) +{ + uint32_t u32Ch; + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + + WRITE_REG32(TMR0x->BCONR, 0UL); + WRITE_REG32(TMR0x->STFLR, 0UL); + for (u32Ch = 0UL; u32Ch < TMR0_CH_MAX; u32Ch++) { + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, 0x0000FFFFUL); + } +} + +/** + * @brief Initialize TMR0 function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init) +{ + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(pstcTmr0Init->u32ClockSrc)); + DDL_ASSERT(IS_TMR0_CLK_DIV(pstcTmr0Init->u32ClockDiv)); + DDL_ASSERT(IS_TMR0_FUNC(pstcTmr0Init->u32Func)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, pstcTmr0Init->u16CompareValue); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CLR_MASK << TMR0_CH_OFFSET(u32Ch)), + ((pstcTmr0Init->u32ClockSrc | pstcTmr0Init->u32ClockDiv | + pstcTmr0Init->u32Func) << TMR0_CH_OFFSET(u32Ch))); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr0_init_t to default values. + * @param [out] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTmr0Init->u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; + pstcTmr0Init->u32ClockDiv = TMR0_CLK_DIV1; + pstcTmr0Init->u32Func = TMR0_FUNC_CMP; + pstcTmr0Init->u16CompareValue = 0xFFFFU; + } + return i32Ret; +} + +/** + * @brief Start TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Stop TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 counter value. + * @note Setting the count requires stop tmr0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the counter register + * @retval None + */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, u16Value); +} + +/** + * @brief Get Tmr0 counter value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval uint16_t The counter register data + */ +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CNTR); +} + +/** + * @brief Set Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the compare register + * @retval None + */ +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, u16Value); +} + +/** + * @brief Get Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval The compare register data + */ +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CMPR); +} + +/** + * @brief Set clock source. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Src Specifies the clock source + * This parameter can be a value of the following: + * @arg @ref TMR0_Clock_Source + * @retval None + */ +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(u32Src)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_CLK_SRC_MASK << TMR0_CH_OFFSET(u32Ch)), (u32Src << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set the division of clock. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Div Specifies the clock source division + * This parameter can be a value of the following: + * @arg TMR0_CLK_DIV1: Clock source / 1 + * @arg TMR0_CLK_DIV2: Clock source / 2 + * @arg TMR0_CLK_DIV4: Clock source / 4 + * @arg TMR0_CLK_DIV8: Clock source / 8 + * @arg TMR0_CLK_DIV16: Clock source / 16 + * @arg TMR0_CLK_DIV32: Clock source / 32 + * @arg TMR0_CLK_DIV64: Clock source / 64 + * @arg TMR0_CLK_DIV128: Clock source / 128 + * @arg TMR0_CLK_DIV256: Clock source / 256 + * @arg TMR0_CLK_DIV512: Clock source / 512 + * @arg TMR0_CLK_DIV1024: Clock source / 1024 + * @retval None. + */ +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << TMR0_CH_OFFSET(u32Ch)), (u32Div << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 Function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Func Select TMR0 function + * This parameter can be a value of the following: + * @arg TMR0_FUNC_CMP: Select the Compare function for TMR0 + * @arg TMR0_FUNC_CAPT: Select the Capture function for TMR0 + * @retval None + */ +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_FUNC(u32Func)); + + MODIFY_REG32(TMR0x->BCONR, ((TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) << TMR0_CH_OFFSET(u32Ch)), + (u32Func << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Enable or disable HardWare trigger capture function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger start function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger stop function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger clear function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable specified Tmr0 interrupt. + * @note The comparison matching interrupt of channel 'TMR0_INT_CMP_A' in unit 'CM_TMR0_1' of 'HC32F460,HC32F451,HC32F452'. + * is only available in asynchronous counting mode. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32IntType TMR0 interrupt type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(TMR0x->BCONR, u32IntType); + } else { + CLR_REG32_BIT(TMR0x->BCONR, u32IntType); + } +} + +/** + * @brief Get Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(TMR0x->STFLR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval None + */ +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR0x->STFLR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr2.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr2.c new file mode 100644 index 0000000000..62f35ccecd --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr2.c @@ -0,0 +1,810 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr2.c + * @brief This file provides firmware functions to manage the TMR2(Timer2). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr2.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR2 TMR2 + * @brief TMR2 Driver Library + * @{ + */ +#if (LL_TMR2_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR2_Local_Macros TMR2 Local Macros + * @{ + */ + +/** + * @defgroup TMR2_Configuration_Bit_Mask TMR2 Configuration Bit Mask + * @{ + */ +#define TMR2_BCONR_INIT_MASK (TMR2_BCONR_CAPMDA | TMR2_BCONR_SYNSA | TMR2_BCONR_SYNCLKA | \ + TMR2_BCONR_ASYNCLKA | TMR2_BCONR_CKDIVA | TMR2_BCONR_SYNCLKAT) +#define TMR2_BCONR_CLK_CFG_MASK (TMR2_BCONR_SYNSA | TMR2_BCONR_SYNCLKA | \ + TMR2_BCONR_ASYNCLKA | TMR2_BCONR_SYNCLKAT) + +#define TMR2_PWM_POLARITY_MASK (TMR2_PCONR_STACA | TMR2_PCONR_STPCA | TMR2_PCONR_CMPCA) +#define TMR2_FILTER_CLK_DIV_MASK (TMR2_PCONR_NOFICKA) +/** + * @} + */ + +/** + * @defgroup TMR2_Channel_Cfg_Bit_Field_Offset TMR2 Channel Configuration Bit Field Offset + * @{ + */ +#define TMR2_CH_OFFSET (16U) + +#define TMR2_PWM_POLARITY_OFFSET (2U) + +/** + * @} + */ + +/** + * @defgroup TMR2_Check_Parameters_Validity TMR2 check parameters validity + * @{ + */ +#define IS_TMR2_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* Unit and channel */ +#define IS_TMR2_UNIT(x) \ +( ((x) == CM_TMR2_1) || \ + ((x) == CM_TMR2_2) || \ + ((x) == CM_TMR2_3) || \ + ((x) == CM_TMR2_4)) + +#define IS_TMR2_CH(x) ((x) <= TMR2_CH_B) + +#define IS_TMR2_FUNC(x) (((x) == TMR2_FUNC_CMP) || ((x) == TMR2_FUNC_CAPT)) + +/* Clock source */ +#define IS_TMR2_CLK_SRC(x) \ +( ((x) == TMR2_CLK_PCLK1) || \ + ((x) == TMR2_CLK_TRIG_RISING) || \ + ((x) == TMR2_CLK_TRIG_FALLING) || \ + ((x) == TMR2_CLK_EVT) || \ + ((x) == TMR2_CLK_TMR6_OVF) || \ + ((x) == TMR2_CLK_TMR6_UDF) || \ + ((x) == TMR2_CLK_TMR6_OVF_UDF) || \ + ((x) == TMR2_CLK_LRC) || \ + ((x) == TMR2_CLK_XTAL32) || \ + ((x) == TMR2_CLK_PIN_CLK)) + +#define IS_TMR2_CLK_DIV(x) \ +( ((x) == TMR2_CLK_DIV1) || \ + ((x) == TMR2_CLK_DIV2) || \ + ((x) == TMR2_CLK_DIV4) || \ + ((x) == TMR2_CLK_DIV8) || \ + ((x) == TMR2_CLK_DIV16) || \ + ((x) == TMR2_CLK_DIV32) || \ + ((x) == TMR2_CLK_DIV64) || \ + ((x) == TMR2_CLK_DIV128) || \ + ((x) == TMR2_CLK_DIV256) || \ + ((x) == TMR2_CLK_DIV512) || \ + ((x) == TMR2_CLK_DIV1024)) + +#define IS_TMR2_INT(x) IS_TMR2_BIT_MASK((x), TMR2_INT_ALL) + +#define IS_TMR2_FLAG(x) IS_TMR2_BIT_MASK((x), TMR2_FLAG_ALL) + +#define IS_TMR2_PWM_START_POLARITY(x) \ +( ((x) == TMR2_PWM_LOW) || \ + ((x) == TMR2_PWM_HIGH) || \ + ((x) == TMR2_PWM_HOLD)) + +#define IS_TMR2_PWM_STOP_POLARITY(x) \ +( ((x) == TMR2_PWM_LOW) || \ + ((x) == TMR2_PWM_HIGH) || \ + ((x) == TMR2_PWM_HOLD)) + +#define IS_TMR2_PWM_MATCH_CMP_POLARITY(x) \ +( ((x) == TMR2_PWM_LOW) || \ + ((x) == TMR2_PWM_HIGH) || \ + ((x) == TMR2_PWM_HOLD) || \ + ((x) == TMR2_PWM_INVT)) + +#define IS_TMR2_PWM_POLARITY(st, pol) \ +( (((st) == TMR2_CNT_STAT_START) && IS_TMR2_PWM_START_POLARITY(pol)) || \ + (((st) == TMR2_CNT_STAT_STOP) && IS_TMR2_PWM_STOP_POLARITY(pol)) || \ + (((st) == TMR2_CNT_STAT_MATCH_CMP) && IS_TMR2_PWM_MATCH_CMP_POLARITY(pol))) + +#define IS_TMR2_START_COND(x) IS_TMR2_BIT_MASK((x), TMR2_START_COND_ALL) + +#define IS_TMR2_STOP_COND(x) IS_TMR2_BIT_MASK((x), TMR2_STOP_COND_ALL) + +#define IS_TMR2_CLR_COND(x) IS_TMR2_BIT_MASK((x), TMR2_CLR_COND_ALL) + +#define IS_TMR2_CAPT_COND(x) IS_TMR2_BIT_MASK((x), TMR2_CAPT_COND_ALL) + +#define IS_TMR2_FILTER_CLK_DIV(x) \ +( ((x) == TMR2_FILTER_CLK_DIV1) || \ + ((x) == TMR2_FILTER_CLK_DIV4) || \ + ((x) == TMR2_FILTER_CLK_DIV16) || \ + ((x) == TMR2_FILTER_CLK_DIV64)) + +#define IS_TMR2_VALID_VAL(x) ((x) <= 0xFFFFUL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR2_Global_Functions TMR2 Global Functions + * @{ + */ + +/** + * @brief Initializes the specified TMR2 channel according to the specified parameters + * in the structure stc_tmr2_init_t + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] pstcTmr2Init Pointer to a stc_tmr2_init_t structure value that + * contains the configuration information for the TMR2 channel. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL. + */ +int32_t TMR2_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_init_t *pstcTmr2Init) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t *reg32CMPR; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + if (pstcTmr2Init != NULL) { + DDL_ASSERT(IS_TMR2_CLK_SRC(pstcTmr2Init->u32ClockSrc)); + DDL_ASSERT(IS_TMR2_CLK_DIV(pstcTmr2Init->u32ClockDiv)); + DDL_ASSERT(IS_TMR2_FUNC(pstcTmr2Init->u32Func)); + DDL_ASSERT(IS_TMR2_VALID_VAL(pstcTmr2Init->u32CompareValue)); + + u32Tmp = pstcTmr2Init->u32Func | pstcTmr2Init->u32ClockSrc | + pstcTmr2Init->u32ClockDiv; + reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR); + WRITE_REG32(reg32CMPR[u32Ch], pstcTmr2Init->u32CompareValue); + /* Channel bit filed offset. */ + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_INIT_MASK << u32Ch), (u32Tmp << u32Ch)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for TMR2 initialization structure. + * @param [in] pstcTmr2Init Pointer to a stc_tmr2_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL. + */ +int32_t TMR2_StructInit(stc_tmr2_init_t *pstcTmr2Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcTmr2Init != NULL) { + pstcTmr2Init->u32ClockSrc = TMR2_CLK_PCLK1; + pstcTmr2Init->u32ClockDiv = TMR2_CLK_DIV1; + pstcTmr2Init->u32Func = TMR2_FUNC_CMP; + pstcTmr2Init->u32CompareValue = 0xFFFFUL; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initializes the specified TMR2 unit. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @retval None + */ +void TMR2_DeInit(CM_TMR2_TypeDef *TMR2x) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + + TMR2_Stop(TMR2x, TMR2_CH_A); + TMR2_Stop(TMR2x, TMR2_CH_B); + WRITE_REG32(TMR2x->CMPBR, 0xFFFFU); + CLR_REG32(TMR2x->CNTBR); + CLR_REG32(TMR2x->CNTAR); + CLR_REG32(TMR2x->BCONR); + CLR_REG32(TMR2x->ICONR); + CLR_REG32(TMR2x->PCONR); + CLR_REG32(TMR2x->HCONR); + CLR_REG32(TMR2x->STFLR); + WRITE_REG32(TMR2x->CMPAR, 0xFFFFU); +} + +/** + * @brief Specifies the function mode for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Func Function mode. + * This parameter can be a value of @ref TMR2_Function + * @arg TMR2_FUNC_CMP: The function of TMR2 channel is ouput compare. + * @arg TMR2_FUNC_CAPT: The function of TMR2 channel is input capture. + * @retval None + */ +void TMR2_SetFunc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Func) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_FUNC(u32Func)); + + /* Channel bit filed offset. */ + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CAPMDA << u32Ch), (u32Func << u32Ch)); +} + +/** + * @brief Specifies the clock source for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Src Clock source. + * This parameter can be a value of @ref TMR2_Clock_Source + * @retval None + */ +void TMR2_SetClockSrc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Src) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_CLK_SRC(u32Src)); + + /* Channel bit filed offset. */ + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CLK_CFG_MASK << u32Ch), (u32Src << u32Ch)); +} + +/** + * @brief Specifies the clock divider for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Div Clock divider. + * This parameter can be a value of @ref TMR2_Clock_Divider + * @retval None + */ +void TMR2_SetClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_CLK_DIV(u32Div)); + + /* Channel bit filed offset. */ + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CKDIVA << u32Ch), (u32Div << u32Ch)); +} + +/** + * @brief Set a default value for the TMR2 output compare configuration structure. + * @param [in] pstPwmInit Pointer to a stc_tmr2_pwm_init_t structure value that + * contains the configuration information for the TMR2 PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL. + */ +int32_t TMR2_PWM_StructInit(stc_tmr2_pwm_init_t *pstPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstPwmInit != NULL) { + pstPwmInit->u32StartPolarity = TMR2_PWM_HIGH; + pstPwmInit->u32StopPolarity = TMR2_PWM_LOW; + pstPwmInit->u32CompareMatchPolarity = TMR2_PWM_INVT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configures the PWM of the specified TMR2 channel + * according to the specified parameters in the structure @ref stc_tmr2_pwm_init_t + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] pstPwmInit Pointer to a @ref stc_tmr2_pwm_init_t structure value that + * contains the configuration information for the TMR2 PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL. + */ +int32_t TMR2_PWM_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_pwm_init_t *pstPwmInit) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + if (pstPwmInit != NULL) { + DDL_ASSERT(IS_TMR2_PWM_START_POLARITY(pstPwmInit->u32StartPolarity)); + DDL_ASSERT(IS_TMR2_PWM_STOP_POLARITY(pstPwmInit->u32StopPolarity)); + DDL_ASSERT(IS_TMR2_PWM_MATCH_CMP_POLARITY(pstPwmInit->u32CompareMatchPolarity)); + /* Configures PWM polarity. */ + u32Tmp = (pstPwmInit->u32StartPolarity << TMR2_PCONR_STACA_POS) | \ + (pstPwmInit->u32StopPolarity << TMR2_PCONR_STPCA_POS) | \ + (pstPwmInit->u32CompareMatchPolarity << TMR2_PCONR_CMPCA_POS); + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->PCONR, (TMR2_PWM_POLARITY_MASK << u32Ch), (u32Tmp << u32Ch)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable PWM output of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_PWM_OutputCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + uint8_t au8EnPos[] = {TMR2_PCONR_OUTENA_POS, TMR2_PCONR_OUTENB_POS}; + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMR2x->PCONR; + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, au8EnPos[u32Ch]), enNewState); +} + +/** + * @brief Enable or disable the specified hardware capture condition. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Cond Hardware capture condition. + * This parameter can be a value of @ref TMR2_Capture_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_HWCaptureCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_CAPT_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Cond <<= (u32Ch * TMR2_CH_OFFSET); + + if (enNewState == ENABLE) { + SET_REG32_BIT(TMR2x->HCONR, u32Cond); + } else { + CLR_REG32_BIT(TMR2x->HCONR, u32Cond); + } +} + +/** + * @brief Enable or disable the specified hardware start condition. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Cond Hardware start condition. + * This parameter can be a value of @ref TMR2_Start_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_HWStartCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_START_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Cond <<= (u32Ch * TMR2_CH_OFFSET); + + if (enNewState == ENABLE) { + SET_REG32_BIT(TMR2x->HCONR, u32Cond); + } else { + CLR_REG32_BIT(TMR2x->HCONR, u32Cond); + } +} + +/** + * @brief Enable or disable the specified hardware stop condition. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Cond Hardware stop condition. + * This parameter can be a value of @ref TMR2_Stop_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_HWStopCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_STOP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Cond <<= (u32Ch * TMR2_CH_OFFSET); + + if (enNewState == ENABLE) { + SET_REG32_BIT(TMR2x->HCONR, u32Cond); + } else { + CLR_REG32_BIT(TMR2x->HCONR, u32Cond); + } +} + +/** + * @brief Enable or disable the specified hardware clear condition. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Cond Hardware clear condition. + * This parameter can be a value of @ref TMR2_Clear_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_HWClearCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_CLR_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Cond <<= (u32Ch * TMR2_CH_OFFSET); + + if (enNewState == ENABLE) { + SET_REG32_BIT(TMR2x->HCONR, u32Cond); + } else { + CLR_REG32_BIT(TMR2x->HCONR, u32Cond); + } +} + +/** + * @brief Specifies the clock divider of filter. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Div The clock source divider of the filter. + * This parameter can be a value of @ref TMR2_Filter_Clock_Divider + * @arg TMR2_FILTER_CLK_DIV1: The filter clock is the clock of timer2 / 1. + * @arg TMR2_FILTER_CLK_DIV4: The filter clock is the clock of timer2 / 4. + * @arg TMR2_FILTER_CLK_DIV16: The filter clock is the clock of timer2 / 16. + * @arg TMR2_FILTER_CLK_DIV64: The filter clock is the clock of timer2 / 64. + * @retval None + */ +void TMR2_SetFilterClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_FILTER_CLK_DIV(u32Div)); + + u32Ch *= TMR2_CH_OFFSET; + MODIFY_REG32(TMR2x->PCONR, TMR2_FILTER_CLK_DIV_MASK << u32Ch, u32Div << u32Ch); +} + +/** + * @brief Enable or disable the filter of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_FilterCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + uint8_t au8EnPos[] = {TMR2_PCONR_NOFIENA_POS, TMR2_PCONR_NOFIENB_POS}; + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMR2x->PCONR; + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, au8EnPos[u32Ch]), enNewState); +} + +/** + * @brief Enable or disable the interrupt of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32IntType The interrupt type. + * This parameter can be values of @ref TMR2_Interrupt_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR2_IntCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(TMR2x->ICONR, u32IntType); + } else { + CLR_REG32_BIT(TMR2x->ICONR, u32IntType); + } +} + +/** + * @brief Start the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @retval None + */ +void TMR2_Start(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + SET_REG32_BIT(TMR2x->BCONR, TMR2_BCONR_CSTA << (u32Ch * TMR2_CH_OFFSET)); +} + +/** + * @brief Stop the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @retval None + */ +void TMR2_Stop(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + CLR_REG32_BIT(TMR2x->BCONR, TMR2_BCONR_CSTA << (u32Ch * TMR2_CH_OFFSET)); +} + +/** + * @brief Get the status of the specified TMR2 flag. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Flag TMR2 status flag. + * This parameter can be values of @ref TMR2_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR2_GetStatus(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_FLAG(u32Flag)); + + if (READ_REG32_BIT(TMR2x->STFLR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified TMR2 flag. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Flag TMR2 status flag. + * This parameter can be values of @ref TMR2_Status_Flag + * @retval None + */ +void TMR2_ClearStatus(CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_FLAG(u32Flag)); + CLR_REG32_BIT(TMR2x->STFLR, u32Flag); +} + +/** + * @brief Set compare value for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch The TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Value The compare reference value of the specified TMR2 channel. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMR2_SetCompareValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value) +{ + __IO uint32_t *reg32CMPR; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_VALID_VAL(u32Value)); + + reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR); + WRITE_REG32(reg32CMPR[u32Ch], u32Value); +} + +/** + * @brief Get compare value of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch The TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @retval The compare value of the specified TMR2 channel. A number between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMR2_GetCompareValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch) +{ + __IO uint32_t *reg32CMPR; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR); + return reg32CMPR[u32Ch]; +} + +/** + * @brief Set counter value for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch The TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @param [in] u32Value The counter value for the specified TMR2 channel. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMR2_SetCountValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value) +{ + __IO uint32_t *reg32CNTR; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_VALID_VAL(u32Value)); + + reg32CNTR = (__IO uint32_t *)((uint32_t)&TMR2x->CNTAR); + WRITE_REG32(reg32CNTR[u32Ch], u32Value); +} + +/** + * @brief Get counter value of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch The TMR2 channel. + * This parameter can be a value of @ref TMR2_Channel + * @retval The counter value of the specified TMR2 channel. A number between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMR2_GetCountValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch) +{ + __IO uint32_t *reg32CNTR; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + + reg32CNTR = (__IO uint32_t *)((uint32_t)&TMR2x->CNTAR); + return reg32CNTR[u32Ch]; +} + +/** + * @brief Specifies the ouput polarity of the PWM at the specified state of counter. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg CM_TMR2_x or CM_TMR2 + * @param [in] u32Ch TMR2 channel. + * This parameter can be a value @ref TMR2_Channel + * @param [in] u8CountState TMR2 counter state. + * This parameter can be a value @ref TMR2_Counter_State + * @param [in] u32Polarity The polarity of PWM. + * This parameter can be a value @ref TMR2_PWM_Polarity + * @retval None + */ +void TMR2_PWM_SetPolarity(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint8_t u8CountState, uint32_t u32Polarity) +{ + uint32_t u32PolarityPos; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u32Ch)); + DDL_ASSERT(IS_TMR2_PWM_POLARITY(u8CountState, u32Polarity)); + + u32PolarityPos = ((uint32_t)u8CountState * TMR2_PWM_POLARITY_OFFSET) + (u32Ch * TMR2_CH_OFFSET); + MODIFY_REG32(TMR2x->PCONR, TMR2_PCONR_STACA << u32PolarityPos, u32Polarity << u32PolarityPos); +} + +/** + * @} + */ + +#endif /* LL_TMR2_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c new file mode 100644 index 0000000000..1da47994df --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c @@ -0,0 +1,2306 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.c + * @brief This file provides firmware functions to manage the TMR4(Timer4) + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr4.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR4 TMR4 + * @brief TMR4 Driver Library + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Local_Macros TMR4 Local Macros + * @{ + */ + +/** + * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity + * @{ + */ +#define IS_TMR4_UNIT(x) \ +( ((x) == CM_TMR4_1) || \ + ((x) == CM_TMR4_2) || \ + ((x) == CM_TMR4_3)) + +#define IS_TMR4_CLK_DIV(x) \ +( ((x) == TMR4_CLK_DIV1) || \ + ((x) == TMR4_CLK_DIV2) || \ + ((x) == TMR4_CLK_DIV4) || \ + ((x) == TMR4_CLK_DIV8) || \ + ((x) == TMR4_CLK_DIV16) || \ + ((x) == TMR4_CLK_DIV32) || \ + ((x) == TMR4_CLK_DIV64) || \ + ((x) == TMR4_CLK_DIV128) || \ + ((x) == TMR4_CLK_DIV256) || \ + ((x) == TMR4_CLK_DIV512) || \ + ((x) == TMR4_CLK_DIV1024)) + +#define IS_TMR4_MD(x) \ +( ((x) == TMR4_MD_SAWTOOTH) || \ + ((x) == TMR4_MD_TRIANGLE)) + +#define IS_TMR4_CLK_SRC(x) \ +( ((x) == TMR4_CLK_SRC_INTERNCLK) || \ + ((x) == TMR4_CLK_SRC_EXTCLK)) + +#define IS_TMR4_INT_CNT_MASKTIME(x) ((x) <= TMR4_INT_CNT_MASK15) + +#define IS_TMR4_INT_CNT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_CNT_MASK) == TMR4_INT_CNT_MASK)) + +#define IS_TMR4_INT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_ALL) == TMR4_INT_ALL)) + +#define IS_TMR4_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_FLAG_ALL) == TMR4_FLAG_ALL)) + +#define IS_TMR4_OC_HIGH_CH(x) (((x) & 0x1UL) == 0UL) +#define IS_TMR4_OC_LOW_CH(x) (((x) & 0x1UL) == 1UL) + +#define IS_TMR4_OC_BUF_OBJECT(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_OC_BUF_OBJECT_MASK) == TMR4_OC_BUF_OBJECT_MASK)) + +#define IS_TMR4_OC_BUF_COND(x) \ +( ((x) == TMR4_OC_BUF_COND_IMMED) || \ + ((x) == TMR4_OC_BUF_COND_PEAK) || \ + ((x) == TMR4_OC_BUF_COND_VALLEY) || \ + ((x) == TMR4_OC_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_INVD_POLARITY(x) \ +( ((x) == TMR4_OC_INVD_LOW) || \ + ((x) == TMR4_OC_INVD_HIGH)) + +#define IS_TMR4_PWM_MD(x) \ +( ((x) == TMR4_PWM_MD_THROUGH) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR_FILTER)) + +#define IS_TMR4_PWM_POLARITY(x) \ +( ((x) == TMR4_PWM_OXH_HOLD_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_HOLD_OXL_INVT) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_INVT)) + +#define IS_TMR4_PWM_CLK_DIV(x) (((x) | TMR4_PWM_CLK_DIV128) == TMR4_PWM_CLK_DIV128) + +#define IS_TMR4_PWM_DEADTIME_REG_IDX(x) \ +( ((x) == TMR4_PWM_PDAR_IDX) || \ + ((x) == TMR4_PWM_PDBR_IDX)) + +#define IS_TMR4_PWM_OE_EFFECT(x) \ +( ((x) == TMR4_PWM_OE_EFFECT_IMMED) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_PEAK) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_VALLEY)) + +#define IS_TMR4_PWM_PIN_MD(x) \ +( ((x) == TMR4_PWM_PIN_OUTPUT_OS) || \ + ((x) == TMR4_PWM_PIN_OUTPUT_NORMAL)) + +#define IS_TMR4_EVT_CH(x) ((x) <= TMR4_EVT_CH_WL) + +#define IS_TMR4_EVT_MATCH_COND(x) (((x) | TMR4_EVT_MATCH_CNT_ALL) == TMR4_EVT_MATCH_CNT_ALL) + +#define IS_TMR4_EVT_MASK_TYPE(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_EVT_MASK_TYPE_ALL) == TMR4_EVT_MASK_TYPE_ALL)) + +#define IS_TMR4_EVT_DELAY_OBJECT(x) \ +( ((x) == TMR4_EVT_DELAY_OCCRXH) || \ + ((x) == TMR4_EVT_DELAY_OCCRXL)) + +#define IS_TMR4_EVT_MD(x) \ +( ((x) == TMR4_EVT_MD_DELAY) || \ + ((x) == TMR4_EVT_MD_CMP)) + +#define IS_TMR4_EVT_MASK(x) (((x) | TMR4_EVT_MASK15) == TMR4_EVT_MASK15) + +#define IS_TMR4_EVT_BUF_COND(x) \ +( ((x) == TMR4_EVT_BUF_COND_IMMED) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK) || \ + ((x) == TMR4_EVT_BUF_COND_VALLEY) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_CH(x) ((x) <= TMR4_OC_CH_WL) +#define IS_TMR4_PWM_CH(x) ((x) <= TMR4_PWM_CH_W) +#define IS_TMR4_PWM_PIN(x) ((x) <= TMR4_PWM_PIN_OWL) +#define IS_TMR4_EVT_OUTPUT_EVT(x) \ +( ((x) >> TMR4_SCSR_EVTOS_POS) <= (TMR4_EVT_OUTPUT_EVT5 >> TMR4_SCSR_EVTOS_POS)) +#define IS_TMR4_EVT_OUTPUT_SIGNAL(x) ((x) <= TMR4_EVT_OUTPUT_EVT5_SIGNAL) + +#define IS_TMR4_PWM_ABNORMAL_PIN_STAT(x) ((x) <= TMR4_PWM_ABNORMAL_PIN_HIGH) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag_Interrupt_Mask TMR4 Flag and Interrupt Mask + * @{ + */ +#define TMR4_FLAG_CNT_MASK (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY) +#define TMR4_INT_CNT_MASK (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY) + +#define TMR4_FLAG_OC_MASK (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \ + TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +#define TMR4_INT_OC_MASK (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \ + TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) + +#define TMR4_FLAG_RELOAD_TMR_MASK (TMR4_FLAG_RELOAD_TMR_U | TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W) +#define TMR4_INT_RELOAD_TMR_MASK (TMR4_INT_RELOAD_TMR_U | TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W) + +/** + * @} + */ + +/** + * @defgroup TMR4_Registers_Reset_Value TMR4 Registers Reset Value + * @{ + */ +#define TMR4_CCSR_RST_VALUE (0x0040U) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object_Mask TMR4 OC Buffer Object Mask + * @{ + */ +#define TMR4_OC_BUF_OBJECT_MASK (TMR4_OC_BUF_CMP_VALUE | TMR4_OC_BUF_CMP_MD) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx_MASK(CH) (((uint16_t)TMR4_OCSR_OCEH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCPx_MASK(CH) (((uint16_t)TMR4_OCSR_OCPH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIE_MASK (TMR4_OCSR_OCIEH | TMR4_OCSR_OCIEL) +#define TMR4_OCSR_OCF_MASK (TMR4_OCSR_OCFH | TMR4_OCSR_OCFL) +#define TMR4_OCSR_MASK(CH) \ +( ((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << (((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx(CH, OCEx) (((uint16_t)OCEx) << (((uint16_t)((CH) % 2UL)) + TMR4_OCSR_OCEH_POS)) +#define TMR4_OCSR_OCPx(CH, OCPx) (((uint16_t)OCPx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIEx(CH, OCIEx) (((uint16_t)OCIEx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCFx(CH, OCFx) (((uint16_t)OCFx) << ((CH) % 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_CHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_MxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_MHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_LMCx_MASK(CH) (((uint16_t)TMR4_OCER_LMCH) << ((CH) % 2UL)) +#define TMR4_OCER_LMMx_MASK(CH) (((uint16_t)TMR4_OCER_LMMH) << ((CH) % 2UL)) +#define TMR4_OCER_MCECx_MASK(CH) (((uint16_t)TMR4_OCER_MCECH) << ((CH) % 2UL)) +#define TMR4_OCER_MASK(CH) \ +( (((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << (((CH) % 2UL) << 1U)) | \ + (((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << (((CH) % 2UL) << 1U))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit TMR4_OCER Bit + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN(CH, CxBUFEN) ((uint16_t)((uint16_t)(CxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_CHBUFEN_POS))) +#define TMR4_OCER_MxBUFEN(CH, MxBUFEN) ((uint16_t)((uint16_t)(MxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_MHBUFEN_POS))) +#define TMR4_OCER_LMCx(CH, LMCx) ((uint16_t)(LMCx) << ((((CH) % 2UL)) + TMR4_OCER_LMCH_POS)) +#define TMR4_OCER_LMMx(CH, LMMx) ((uint16_t)(LMMx) << ((((CH) % 2UL)) + TMR4_OCER_LMMH_POS)) +#define TMR4_OCER_MCECx(CH, MCECx) ((uint16_t)(MCECx) << ((((CH) % 2UL)) + TMR4_OCER_MCECH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask + * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel + * @note The parameter CH value is TMR4_PWM_CH_x (x=U/V/W) + * @{ + */ +#define TMR4_RCSR_RTIDx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIDU) << (CH))) +#define TMR4_RCSR_RTIFx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIFU) << ((CH) << 2U))) +#define TMR4_RCSR_RTICx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTICU) << ((CH) << 2U))) +#define TMR4_RCSR_RTEx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTEU) << ((CH) << 2U))) +#define TMR4_RCSR_RTSx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTSU) << ((CH) << 2U))) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit_Mask TMR4_PSCR Bit Mask + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @note The parameter PORT value is TMR4_PWM_PIN_Oxy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_PSCR_OExy_MASK(PORT) (TMR4_PSCR_OEUH << (PORT)) +#define TMR4_PSCR_OSxy_MASK(PORT) (TMR4_PSCR_OSUH << ((PORT) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit TMR4_PSCR Bit + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @note The parameter PORT value is TMR4_PWM_PIN_Oxy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_PSCR_OExy(PORT, OExy) ((OExy) << (PORT)) +#define TMR4_PSCR_OSxy(PORT, OSxy) ((OSxy) << (((PORT) << 1U) + TMR4_PSCR_OSUH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_Register TMR4 Register + * @{ + */ +#define TMR4_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define TMR4_REG16(_ADDR_) ((__IO uint16_t *)(_ADDR_)) +#define TMR4_REG32(_ADDR_) ((__IO uint32_t *)(_ADDR_)) + +/** + * @defgroup TMR4_OC_Register_UVW TMR4 OC Register + * @brief Get the specified OC register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_OC_xy (x=U/V/W, y=H/L) + * @{ + */ +#define _TMR4_OCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCCRUH) + ((CH) << 2U)) +#define _TMR4_OCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCMRHUH) + ((CH) << 2U)) +#define _TMR4_OCER(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCERU) + (((CH) & 0x06UL) << 1U)) +#define _TMR4_OCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCSRU) + (((CH) & 0x06UL) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register_UVW TMR4 PWM Register + * @brief Get the specified PWM register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_PWM_CH_x (x=U/V/W) + * @{ + */ +#define _TMR4_RCSR(UNIT) TMR4_REG16(TMR4_REG_ADDR((UNIT)->RCSR)) +#define _TMR4_POCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->POCRU) + ((CH) << 2U)) +#define _TMR4_PFSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PFSRU) + ((CH) << 3U)) +#define _TMR4_PDR(UNIT, CH, IDX) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PDARU) + ((CH) << 3U) + ((IDX) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register_UVW TMR4 Event Register + * @brief Get the specified event register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_EVT_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define _TMR4_SCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCCRUH) + ((CH) << 2U)) +#define _TMR4_SCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCSRUH) + ((CH) << 2U)) +#define _TMR4_SCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCMRUH) + ((CH) << 2U)) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Register TMR4 OC Register + * @{ + */ +#define TMR4_OCCR(UNIT, CH) _TMR4_OCCR(UNIT, CH) +#define TMR4_OCMR(UNIT, CH) _TMR4_OCMR(UNIT, CH) +#define TMR4_OCER(UNIT, CH) _TMR4_OCER(UNIT, CH) +#define TMR4_OCSR(UNIT, CH) _TMR4_OCSR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register TMR4 PWM Register + * @{ + */ +#define TMR4_RCSR(UNIT) _TMR4_RCSR(UNIT) +#define TMR4_POCR(UNIT, CH) _TMR4_POCR(UNIT, CH) +#define TMR4_PFSR(UNIT, CH) _TMR4_PFSR(UNIT, CH) +#define TMR4_PDR(UNIT, CH, IDX) _TMR4_PDR(UNIT, CH, IDX) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register TMR4 Event Register + * @{ + */ +#define TMR4_SCCR(UNIT, CH) _TMR4_SCCR(UNIT, CH) +#define TMR4_SCSR(UNIT, CH) _TMR4_SCSR(UNIT, CH) +#define TMR4_SCMR(UNIT, CH) _TMR4_SCMR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_ECER_Register EMB Expand Control Register + * @brief Get the specified EVT register address of the specified TMR4 unit + * @{ + */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR4_Global_Functions TMR4 Global Functions + * @{ + */ + +/** + * @defgroup TMR4_Counter_Global_Functions TMR4 Counter Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_init_t to default values + * @param [out] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + pstcTmr4Init->u16PeriodValue = 0xFFFFU; + pstcTmr4Init->u16CountMode = TMR4_MD_SAWTOOTH; + pstcTmr4Init->u16ClockSrc = TMR4_CLK_SRC_INTERNCLK; + pstcTmr4Init->u16ClockDiv = TMR4_CLK_DIV1; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init) +{ + uint16_t u16Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(pstcTmr4Init->u16ClockSrc)); + DDL_ASSERT(IS_TMR4_CLK_DIV(pstcTmr4Init->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_MD(pstcTmr4Init->u16CountMode)); + + /* Set TMR4_CCSR */ + u16Value = (pstcTmr4Init->u16ClockDiv | pstcTmr4Init->u16ClockSrc | \ + pstcTmr4Init->u16CountMode | TMR4_CCSR_CLEAR | TMR4_CCSR_STOP); + WRITE_REG16(TMR4x->CCSR, u16Value); + + /* Set TMR4_CVPR: default value */ + WRITE_REG16(TMR4x->CVPR, 0x0000U); + + /* Set TMR4 period */ + WRITE_REG16(TMR4x->CPSR, pstcTmr4Init->u16PeriodValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize TMR4 counter function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_DeInit(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + /* Configures the registers to reset value. */ + WRITE_REG16(TMR4x->CCSR, TMR4_CCSR_RST_VALUE); + WRITE_REG16(TMR4x->CPSR, 0xFFFFU); + WRITE_REG16(TMR4x->CVPR, 0x0000U); +} + +/** + * @brief Set TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Src TMR4 counter clock source + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Source + * @arg TMR4_CLK_SRC_INTERNCLK: Uses the internal clock as counter's count clock + * @arg TMR4_CLK_SRC_EXTCLK: Uses an external input clock as counter's count clock + * @retval None + * @note The clock division function is valid when clock source is internale clock. + */ +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(u16Src)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16Src); +} + +/** + * @brief Set TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Div TMR4 clock division + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Division + * @arg TMR4_CLK_DIV1: CLK + * @arg TMR4_CLK_DIV2: CLK/2 + * @arg TMR4_CLK_DIV4: CLK/4 + * @arg TMR4_CLK_DIV8: CLK/8 + * @arg TMR4_CLK_DIV16: CLK/16 + * @arg TMR4_CLK_DIV32: CLK/32 + * @arg TMR4_CLK_DIV64: CLK/64 + * @arg TMR4_CLK_DIV128: CLK/128 + * @arg TMR4_CLK_DIV256: CLK/256 + * @arg TMR4_CLK_DIV512: CLK/512 + * @arg TMR4_CLK_DIV1024: CLK/1024 + * @retval None + * @note The clock division function is valid when clock source is the internal clock. + */ +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_DIV(u16Div)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div); +} + +/** + * @brief Set TMR4 counter count mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Mode TMR4 counter count mode + * This parameter can be one of the macros group @ref TMR4_Count_Mode + * @arg TMR4_MD_SAWTOOTH: TMR4 count mode sawtooth wave + * @arg TMR4_MD_TRIANGLE: TMR4 count mode triangular + * @retval None + */ +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_MD(u16Mode)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode); +} + +/** + * @brief Get the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The period value of the TMR4 counter + */ +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CPSR); +} + +/** + * @brief Set the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The period value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CPSR, u16Value); +} + +/** + * @brief Get the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The count value of the TMR4 counter + */ +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CNTR); +} + +/** + * @brief Set the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The count value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CNTR, u16Value); +} + +/** + * @brief Clear TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR); +} + +/** + * @brief Start TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Start(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Stop TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Clear TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval None + */ +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ClearFlag; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag */ + if ((u32Flag & TMR4_FLAG_CNT_MASK) > 0UL) { + CLR_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)); + } + + /* Output-compare flag */ + u32ClearFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ClearFlag > 0UL) { + /* TMR4_OCSRU */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRV */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRW */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + } + + /* PWM reload timer flag */ + u32ClearFlag = ((u32Flag & TMR4_FLAG_RELOAD_TMR_MASK) << 5U); + if (u32ClearFlag > 0UL) { + SET_REG16_BIT(TMR4x->RCSR, u32ClearFlag); + } + +} + +/** + * @brief Get TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ReadFlag; + uint8_t u8FlagSetCount = 0; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag status */ + if (READ_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)) > 0U) { + u8FlagSetCount++; + } + + /* Output-compare interrupt */ + u32ReadFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ReadFlag > 0UL) { + /* TMR4_OCSRU */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRV */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRW */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + } + + /* PWM reload timer flag status */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_RELOAD_TMR_MASK)) << 4U); + if (READ_REG16_BIT(TMR4x->RCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + return (u8FlagSetCount == 0U) ? RESET : SET; +} + +/** + * @brief Enable or disable the specified TMR4 interrupt + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be any composed value of the macros group @ref TMR4_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Counter interrupt */ + u32Type = (u32IntType & TMR4_INT_CNT_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->CCSR, u32Type) : CLR_REG16_BIT(TMR4x->CCSR, u32Type); + } + + /* Output-compare interrupt */ + u32Type = (u32IntType & TMR4_INT_OC_MASK); + if (u32Type > 0UL) { + /* TMR4_OCSRU */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL)) >> 12U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRV */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL)) >> 14U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRW */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)) >> 16U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + } + + /* PWM reload timer interrupt */ + u32Type = (u32IntType & TMR4_INT_RELOAD_TMR_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? CLR_REG16_BIT(TMR4x->RCSR, u32Type) : SET_REG16_BIT(TMR4x->RCSR, u32Type); + } + +} + +/** + * @brief Enable or disable the TMR4 counter period buffer function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } +} + +/** + * @brief Get TMR4 count interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) + */ +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u16IntType)); + + if (TMR4_INT_CNT_VALLEY == u16IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Set TMR4 counter interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @param [in] u16MaskTime TMR4 counter interrupt mask times + * This parameter can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * @arg TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * @arg TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) + * @arg TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) + * @arg TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) + * @arg TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) + * @arg TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) + * @arg TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) + * @arg TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) + * @arg TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) + * @arg TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) + * @arg TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) + * @arg TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) + * @arg TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) + * @arg TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) + * @arg TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) + * @arg TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) + * @retval None + */ +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + DDL_ASSERT(IS_TMR4_INT_CNT_MASKTIME(u16MaskTime)); + + if (TMR4_INT_CNT_VALLEY == (u32IntType & TMR4_INT_CNT_VALLEY)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (u16MaskTime << TMR4_CVPR_ZIM_POS)); + } + + if (TMR4_INT_CNT_PEAK == (u32IntType & TMR4_INT_CNT_PEAK)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (u16MaskTime << TMR4_CVPR_PIM_POS)); + } +} + +/** + * @brief Get TMR4 counter current interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16IntType TMR4 interrupt source + * This parameter can be one of the macros group @ref TMR4_Interrupt + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skiping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skiping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skiping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skiping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skiping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skiping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skiping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skiping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skiping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skiping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skiping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skiping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skiping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skiping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skiping 15 count) + */ +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u16IntType)); + + if (TMR4_INT_CNT_VALLEY == u16IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Enable or disable port output TMR4 counter direction signal + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } else { + CLR_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Global_Functions TMR4 Output-Compare Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_oc_init_t to default values + * @param [out] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + pstcTmr4OcInit->u16CompareValue = 0U; + pstcTmr4OcInit->u16OcInvalidPolarity = TMR4_OC_INVD_LOW; + pstcTmr4OcInit->u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16BufLinkTransObject = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + uint16_t u16Value; + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(pstcTmr4OcInit->u16OcInvalidPolarity)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareModeBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareValueBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(pstcTmr4OcInit->u16BufLinkTransObject)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Set output polarity when OC is disabled. */ + MODIFY_REG16(*OCSR, TMR4_OCSR_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, pstcTmr4OcInit->u16OcInvalidPolarity)); + + /* Set OCMR&&OCCR buffer function */ + u16Value = (TMR4_OCER_MxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareModeBufCond) | \ + TMR4_OCER_CxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareValueBufCond)); + if (TMR4_OC_BUF_CMP_VALUE == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_VALUE)) { + u16Value |= TMR4_OCER_LMCx_MASK(u32Ch); + } + + if (TMR4_OC_BUF_CMP_MD == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_MD)) { + u16Value |= TMR4_OCER_LMMx_MASK(u32Ch); + } + + MODIFY_REG16(*OCER, TMR4_OCER_MASK(u32Ch), u16Value); + + /* Set OC compare value */ + WRITE_REG16(*OCCR, pstcTmr4OcInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval None + */ +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Clear bits: port output valid && OP level && interrupt */ + CLR_REG16_BIT(*OCSR, TMR4_OCSR_MASK(u32Ch)); + + /* Clear bits: OCMR&&OCCR buffer */ + CLR_REG16_BIT(*OCER, TMR4_OCER_MASK(u32Ch)); + + /* Set OC compare match value */ + WRITE_REG16(*OCCR, 0x0000U); +} + +/** + * @brief Get TMR4 OC OCCR compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The compare value of the TMR4 OC OCCR register + */ +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + return READ_REG16(*OCCR); +} + +/** + * @brief Set TMR4 OC compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Value The compare value of the TMR4 OC OCCR register + * @arg number of 16bit + * @retval None + */ +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + WRITE_REG16(*OCCR, u16Value); +} + +/** + * @brief Enable or disable the TMR4 OC of the specified channel. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR port output compare */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCEx_MASK(u32Ch), TMR4_OCSR_OCEx(u32Ch, enNewState)); +} + +/** + * @brief Extend the matching conditions of TMR4 OC channel + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + /* Set OCER register: Extend match function */ + MODIFY_REG16(*OCER, TMR4_OCER_MCECx_MASK(u32Ch), TMR4_OCER_MCECx(u32Ch, enNewState)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer interval response function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer: OCCR/OCMR + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the OCMR/OCMR register buffer function. + * @arg DISABLE: Disable the OCMR/OCMR register buffer function. + * @retval None + */ +void TMR4_OC_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMCx_MASK(u32Ch), TMR4_OCER_LMCx(u32Ch, enNewState)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMMx_MASK(u32Ch), TMR4_OCER_LMMx(u32Ch, enNewState)); + } +} + +/** + * @brief Get TMR4 OC output current polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval Returned value can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * - TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * - TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + */ +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCSR; + uint16_t u16Polarity; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Get OCSR register: OC output polarity */ + u16Polarity = READ_REG16_BIT(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch)); + return (u16Polarity >> (u32Ch % 2UL)); +} + +/** + * @brief Set TMR4 OC invalid output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Polarity TMR4 OC invalid output polarity. + * This parameter can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * @arg TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * @arg TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + * @retval None + */ +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(u16Polarity)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR register: OC invalid output polarity */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, u16Polarity)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer type: OCCR/OCMR + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] u16BufCond TMR4 OC OCCR/OCMR buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Transfer_Condition + * @arg TMR4_OC_BUF_COND_IMMED: Buffer transfer is made when writing to the OCCR/OCMR register. + * @arg TMR4_OC_BUF_COND_VALLEY: Buffer transfer is made when counter count valley. + * @arg TMR4_OC_BUF_COND_PEAK: Buffer transfer is made when counter count peak. + * @arg TMR4_OC_BUF_COND_PEAK_VALLEY: Buffer transfer is made when counter count peak or valley. + * @retval None + */ +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(u16BufCond)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch), TMR4_OCER_CxBUFEN(u32Ch, u16BufCond)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch), TMR4_OCER_MxBUFEN(u32Ch, u16BufCond)); + } +} + +/** + * @brief Get the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @retval The TMR4 OC high channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + return READ_REG16(*OCMRxH); +} + +/** + * @brief Set the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @param [in] unTmr4Ocmrh The TMR4 OC high channel mode @ref un_tmr4_oc_ocmrh_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh) +{ + __IO uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, unTmr4Ocmrh.OCMRx); +} + +/** + * @brief Get the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @retval The TMR4 OC low channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + return READ_REG32(*OCMRxL); +} + +/** + * @brief Set the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @param [in] unTmr4Ocmrl The TMR4 OC low channel mode @ref un_tmr4_oc_ocmrl_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl) +{ + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, unTmr4Ocmrl.OCMRx); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + pstcTmr4PwmInit->u16Mode = TMR4_PWM_MD_THROUGH; + pstcTmr4PwmInit->u16ClockDiv = TMR4_PWM_CLK_DIV1; + pstcTmr4PwmInit->u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + uint16_t u16Value; + __IO uint16_t *POCR; + __IO uint16_t *RCSR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_MD(pstcTmr4PwmInit->u16Mode)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(pstcTmr4PwmInit->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(pstcTmr4PwmInit->u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + u16Value = (pstcTmr4PwmInit->u16Mode | pstcTmr4PwmInit->u16ClockDiv | pstcTmr4PwmInit->u16Polarity); + WRITE_REG16(*POCR, u16Value); + + /* Set RCSR register */ + u16Value = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG16(*RCSR, TMR4_RCSR_RTEx_MASK(u32Ch), u16Value); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *POCR; + __IO uint16_t *RCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + WRITE_REG16(*POCR, (TMR4_PWM_CLK_DIV1 | TMR4_PWM_MD_THROUGH | TMR4_PWM_OXH_HOLD_OXL_HOLD)); + + /* Set RCSR register */ + MODIFY_REG16(*RCSR, TMR4_RCSR_RTEx_MASK(u32Ch), \ + (TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch))); +} + +/** + * @brief Set TMR4 PWM clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Div TMR4 PWM internal clock division + * This parameter can be one of the macros group @ref TMR4_PWM_Clock_Division + * @arg TMR4_PWM_CLK_DIV1: CLK + * @arg TMR4_PWM_CLK_DIV2: CLK/2 + * @arg TMR4_PWM_CLK_DIV4: CLK/4 + * @arg TMR4_PWM_CLK_DIV8: CLK/8 + * @arg TMR4_PWM_CLK_DIV16: CLK/16 + * @arg TMR4_PWM_CLK_DIV32: CLK/32 + * @arg TMR4_PWM_CLK_DIV64: CLK/64 + * @arg TMR4_PWM_CLK_DIV128: CLK/128 + * @retval None + */ +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(u16Div)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_DIVCK, u16Div); +} + +/** + * @brief Set TMR4 PWM output polarity. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Polarity TMR4 PWM output polarity + * This parameter can be one of the macros group @ref TMR4_PWM_Polarity + * @arg TMR4_PWM_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OXH_INVERT_OXL_INVERT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OXH_INVERT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OXH_HOLD_OXL_INVERT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + * @retval None + */ +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_LVLS, u16Polarity); +} + +/** + * @brief Start TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch)); +} + +/** + * @brief Stop TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch)); +} + +/** + * @brief Set TMR4 PWM filter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Value TMR4 PWM filter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + WRITE_REG16(*PFSR, u16Value); +} + +/** + * @brief Set TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @param [in] u16Value TMR4 PWM dead time register value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value) +{ + __IO uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + WRITE_REG16(*PDR, u16Value); +} + +/** + * @brief Get TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @retval TMR4 PWM dead time register value + */ +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex) +{ + __I uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + return READ_REG16(*PDR); +} + +/** + * @brief Set TMR4 PWM reister TMR4_PSCR.OE bit effect time + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Time Effect time + * This parameter can be one of the macros group @ref TMR4_PWM_OE_Bit_Effect_Time + * @arg TMR4_PWM_OE_EFFECT_IMMED: TMR4 PWM reister TMR4_PSCR.OE bit immediate effect immediate + * @arg TMR4_PWM_OE_EFFECT_COUNT_PEAK: TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count peak + * @arg TMR4_PWM_OE_EFFECT_COUNT_VALLEY: TMR4 PWM reister TMR4_PSCR.OE bit effect when TMR4 counter count valley + * @retval None + */ +void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_OE_EFFECT(u32Time)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_ODT, u32Time); +} + +/** + * @brief Enable or disable the TMR4 PWM main output by hardware after clear EMB event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: The TMR4_PSCR.MOE bit automatically set to 1 by hardware to restore the PWM normal output. + * @arg DISABLE: The TMR4_PSCR.MOE bit can only be set to 1 by software to restore the PWM normal output. + * @retval None + */ +void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } else { + CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } +} + +/** + * @brief Enable or disable the TMR4 PWM main output function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } else { + CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } +} + +/** + * @brief Set TMR4 PWM port output mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32Mode The PWM port output mode + * This parameter can be one of the macros group @ref TMR4_PWM_Pin_Output_Mode + * @arg TMR4_PWM_PIN_OUTPUT_OS: TIM4__Oxy(x=U/V/W,y=H/L) output polarity by specified OSxy + * @arg TMR4_PWM_PIN_OUTPUT_NORMAL: TIM4__Oxy(x=U/V/W,y=H/L) output normal PWM + * @retval None + */ +void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin)); + DDL_ASSERT(IS_TMR4_PWM_PIN_MD(u32Mode)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OExy_MASK(u32PwmPin), TMR4_PSCR_OExy(u32PwmPin, u32Mode)); +} + +/** + * @brief Set TMR4 PWM pin status when below conditions occur:1.EMB 2.MOE=0 3.MOE=1&OExy=0 + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32PinStatus TMR4 PWM pin status + * This parameter can be one of the macros group @ref TMR4_PWM_Abnormal_Pin_Status. + * @retval None + */ +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus) +{ + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_ABNORMAL_PIN_STAT(u32PinStatus)); + + DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin)); + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OSxy_MASK(u32PwmPin), TMR4_PSCR_OSxy(u32PwmPin, u32PinStatus)); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Global_Functions TMR4 Event Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_evt_init_t to default values + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + pstcTmr4EventInit->u16Mode = TMR4_EVT_MD_CMP; + pstcTmr4EventInit->u16CompareValue = 0U; + pstcTmr4EventInit->u16OutputEvent = TMR4_EVT_OUTPUT_EVT0; + pstcTmr4EventInit->u16MatchCond = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + uint16_t u16Value; + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MD(pstcTmr4EventInit->u16Mode)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(pstcTmr4EventInit->u16OutputEvent)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(pstcTmr4EventInit->u16MatchCond)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCSR register */ + u16Value = (pstcTmr4EventInit->u16Mode | pstcTmr4EventInit->u16OutputEvent | pstcTmr4EventInit->u16MatchCond); + WRITE_REG16(*SCSR, u16Value); + + /* Set SCMR register */ + WRITE_REG16(*SCMR, 0xFF00U); + + /* Set SCCR register: compare value */ + WRITE_REG16(*SCCR, pstcTmr4EventInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval None + */ +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*SCCR, 0x0U); + WRITE_REG16(*SCSR, 0x0000U); + WRITE_REG16(*SCMR, 0xFF00U); +} + +/** + * @brief Set TMR4 event delay object + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Object TMR4 event delay object + * This parameter can be one of the macros group @ref TMR4_Event_Delay_Object + * @arg TMR4_EVT_DELAY_OCCRXH: TMR4 event delay object - OCCRxh + * @arg TMR4_EVT_DELAY_OCCRXL: TMR4 event delay object - OCCRxl + * @retval None + */ +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_DELAY_OBJECT(u16Object)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTDS, u16Object); +} + +/** + * @brief Set TMR4 event trigger event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskTime Mask times + * This parameter can be one of the macros group @ref TMR4_Event_Mask_Times + * @arg TMR4_EVT_MASK0: Mask 0 times + * @arg TMR4_EVT_MASK1: Mask 1 times + * @arg TMR4_EVT_MASK2: Mask 2 times + * @arg TMR4_EVT_MASK3: Mask 3 times + * @arg TMR4_EVT_MASK4: Mask 4 times + * @arg TMR4_EVT_MASK5: Mask 5 times + * @arg TMR4_EVT_MASK6: Mask 6 times + * @arg TMR4_EVT_MASK7: Mask 7 times + * @arg TMR4_EVT_MASK8: Mask 8 times + * @arg TMR4_EVT_MASK9: Mask 9 times + * @arg TMR4_EVT_MASK10: Mask 10 times + * @arg TMR4_EVT_MASK11: Mask 11 times + * @arg TMR4_EVT_MASK12: Mask 12 times + * @arg TMR4_EVT_MASK13: Mask 13 times + * @arg TMR4_EVT_MASK14: Mask 14 times + * @arg TMR4_EVT_MASK15: Mask 15 times + * @retval None + */ +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK(u16MaskTime)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCMR register */ + MODIFY_REG16(*SCMR, TMR4_SCMR_AMC, u16MaskTime); +} + +/** + * @brief Get TMR4 event SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval Returned value can be one of the macros group @ref TMR4_Event_Mask_Times + * - TMR4_EVT_MASK0: Mask 0 times + * - TMR4_EVT_MASK1: Mask 1 times + * - TMR4_EVT_MASK2: Mask 2 times + * - TMR4_EVT_MASK3: Mask 3 times + * - TMR4_EVT_MASK4: Mask 4 times + * - TMR4_EVT_MASK5: Mask 5 times + * - TMR4_EVT_MASK6: Mask 6 times + * - TMR4_EVT_MASK7: Mask 7 times + * - TMR4_EVT_MASK8: Mask 8 times + * - TMR4_EVT_MASK9: Mask 9 times + * - TMR4_EVT_MASK10: Mask 10 times + * - TMR4_EVT_MASK11: Mask 11 times + * - TMR4_EVT_MASK12: Mask 12 times + * - TMR4_EVT_MASK13: Mask 13 times + * - TMR4_EVT_MASK14: Mask 14 times + * - TMR4_EVT_MASK15: Mask 15 times + */ +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + return READ_REG16_BIT(*SCMR, TMR4_SCMR_AMC); +} + +/** + * @brief Set TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Value SCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + /* Set SCCR register */ + WRITE_REG16(*SCCR, u16Value); +} + +/** + * @brief Get TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval SCCR register value + */ +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + return READ_REG16(*SCCR); +} + +/** + * @brief Set TMR4 output event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Event TMR4 event output event + * This parameter can be one of the macros group @ref TMR4_Event_Output_Event + * @retval None + */ +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(u16Event)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTOS, u16Event); +} + +/** + * @brief Set the SCCR&SCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16BufCond The buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_Event_Buffer_Transfer_Condition + * @arg TMR4_EVT_BUF_COND_IMMED: Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register + * @arg TMR4_EVT_BUF_COND_VALLEY: Register SCCR&SCMR buffer transfer when counter count valley + * @arg TMR4_EVT_BUF_COND_PEAK: Register SCCR&SCMR buffer transfer when counter count peak + * @arg TMR4_EVT_BUF_COND_PEAK_VALLEY: Register SCCR&SCMR buffer transfer when counter count peak or valley + * @retval None + */ +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_BUF_COND(u16BufCond)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + MODIFY_REG16(*SCSR, TMR4_SCSR_BUFEN, u16BufCond); +} + +/** + * @brief Enable or disable the buffer interval response function of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } else { + CLR_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } +} + +/** + * @brief Enable or disable the specified interval response of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskType The specified mask compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Mask + * @arg TMR4_EVT_MASK_VALLEY: Compare with the counter valley interrupt mask counter + * @arg TMR4_EVT_MASK_PEAK: Compare with the counter peak interrupt mask counter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_EventIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK_TYPE(u16MaskType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCMR, u16MaskType); + } else { + CLR_REG16_BIT(*SCMR, u16MaskType); + } +} + +/** + * @brief Enable or disable the specified count compare type of TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Cond The specified count compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Match_Condition + * @arg TMR4_EVT_MATCH_CNT_UP: Start event operate when match with SCCR&SCMR and TMR4 counter count up + * @arg TMR4_EVT_MATCH_CNT_DOWN: Start event operate when match with SCCR&SCMR and TMR4 counter count down + * @arg TMR4_EVT_MATCH_CNT_VALLEY: Start event operate when match with SCCR&SCMR and TMR4 counter count valley + * @arg TMR4_EVT_MATCH_CNT_PEAK: Start event operate when match with SCCR&SCMR and TMR4 counter count peak + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, u16Cond); + } else { + CLR_REG16_BIT(*SCSR, u16Cond); + } +} + +/** + * @brief Set TMR4 event signal output to port + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Signal TMR4 event signal selection + * This parameter can be one of the macros group @ref TMR4_Event_Output_Signal + * @retval None + */ +void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_SIGNAL(u16Signal)); + + MODIFY_REG16(TMR4x->SCER, TMR4_SCER_EVTRS, u16Signal); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c new file mode 100644 index 0000000000..57656c21bf --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c @@ -0,0 +1,1935 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.c + * @brief This file provides firmware functions to manage the TMR6 (TMR6). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr6.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR6 TMR6 + * @brief TMR6 Driver Library + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Local_Macros TMR6 Local Macros + * @{ + */ + +/* Timer6 registers reset value */ +#define TMR6_REG_RST_VALUE_U32 (0xFFFFFFFFUL) +#define TMR6_REG_RST_VALUE_U16 (0xFFFFU) +#define TMR6_REG_GCONR_RST_VALUE (0x00000100UL) + +/* Define for BCONR register configuration */ +#define BCONR_FUNC_CMD_MASK (0x01UL) +#define BCONR_GEN_CFG_MASK (0x0000000EUL) +#define BCONR_GEN_CFG_CHB_OFS (0x04UL) +#define BCONR_PERIOD_CFG_MASK (0x0000000EUL) +#define BCONR_PERIOD_CFG_OFS (0x08UL) +#define BCONR_SPECIAL_CFG_MASK (0x0000000EUL) +#define BCONR_SPECIAL_CFG_CHA_OFS (0x10UL) +#define BCONR_SPECIAL_CFG_CHB_OFS (0x14UL) + +/* Define mask value for PWM output configuration for PCNAR/PCNBR register */ +#define PCNA_BR_REG_OUTPUT_CFG_MASK (0x8000FFFFUL) +#define PCNA_BR_REG_EMB_CFG_MASK (TMR6_PCNAR_EMBSA | TMR6_PCNAR_EMBRA | TMR6_PCNAR_EMBCA) +#define PCONR_REG_POLARITY_MASK (0x03UL) + +/* Define mask value for GCONR register */ +#define TMR6_INIT_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV) +#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV) + +/** + * @defgroup TMR6_Check_Param_Validity TMR6 Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for normal timer6 unit */ +#define IS_VALID_TMR6_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2) || \ + ((x) == CM_TMR6_3) || \ + ((x) == CM_TMR6_4) || \ + ((x) == CM_TMR6_5) || \ + ((x) == CM_TMR6_6) || \ + ((x) == CM_TMR6_7) || \ + ((x) == CM_TMR6_8)) + +/*! Parameter valid check for timer6 count source */ +#define IS_TMR6_CNT_SRC(x) \ +( ((x) == TMR6_CNT_SRC_SW) || \ + ((x) == TMR6_CNT_SRC_HW)) + +/*! Parameter valid check for interrupt source configuration */ +#define IS_VALID_IRQ(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_INT_ALL) == TMR6_INT_ALL)) + +/*! Parameter valid check for status bit read */ +#define IS_VALID_GET_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_ALL) == TMR6_FLAG_ALL)) + +/*! Parameter valid check for status bit clear */ +#define IS_VALID_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_CLR_ALL) == TMR6_FLAG_CLR_ALL)) + +/*! Parameter valid check for period register */ +#define IS_VALID_PERIOD_REG(x) \ +( (x) <= TMR6_PERIOD_REG_C) + +/*! Parameter valid check for general compare register */ +#define IS_VALID_CMP_REG(x) \ +( (x) <= TMR6_CMP_REG_F) + +/*! Parameter valid check for general/special compare channel */ +#define IS_VALID_CNT_CH(x) \ +( ((x) == TMR6_CH_A) || \ + ((x) == TMR6_CH_B)) + +/*! Parameter valid check for buffer function number */ +#define IS_VALID_BUF_NUM(x) \ +( ((x) == TMR6_BUF_SINGLE) || \ + ((x) == TMR6_BUF_DUAL)) + +/*! Parameter valid check for buffer transfer timer configuration */ +#define IS_VALID_BUF_TRANS_TRIG(x) \ +( ((x) == TMR6_BUF_TRANS_INVD) || \ + ((x) == TMR6_BUF_TRANS_OVF) || \ + ((x) == TMR6_BUF_TRANS_UDF) || \ + ((x) == TMR6_BUF_TRANS_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period function */ +#define IS_VALID_PERIOD_CNT_COND(x) \ +( ((x) == TMR6_VALID_PERIOD_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_UDF) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_OVF) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period count */ +#define IS_VALID_PERIOD_CNT(x) \ +( ((x) == TMR6_VALID_PERIOD_CNT_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT1) || \ + ((x) == TMR6_VALID_PERIOD_CNT2) || \ + ((x) == TMR6_VALID_PERIOD_CNT3) || \ + ((x) == TMR6_VALID_PERIOD_CNT4) || \ + ((x) == TMR6_VALID_PERIOD_CNT5) || \ + ((x) == TMR6_VALID_PERIOD_CNT6) || \ + ((x) == TMR6_VALID_PERIOD_CNT7)) + +/*! Parameter valid check for count register data range */ +#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL) + +/*! Parameter valid check for dead time register */ +#define IS_VALID_DEADTIME_REG(x) \ +( ((x) == TMR6_DEADTIME_REG_UP_A) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_A) || \ + ((x) == TMR6_DEADTIME_REG_UP_B) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_B)) + +/*! Parameter valid check for pin */ +#define IS_VALID_PIN(x) \ +( ((x) == TMR6_IO_PWMA) || \ + ((x) == TMR6_IO_PWMB) || \ + ((x) == TMR6_INPUT_TRIGA) || \ + ((x) == TMR6_INPUT_TRIGB) || \ + ((x) == TMR6_INPUT_TRIGC) || \ + ((x) == TMR6_INPUT_TRIGD)) + +/*! Parameter valid check for input pin filter clock */ +#define IS_VALID_FILTER_CLK(x) \ +( ((x) == TMR6_FILTER_CLK_DIV1) || \ + ((x) == TMR6_FILTER_CLK_DIV4) || \ + ((x) == TMR6_FILTER_CLK_DIV16) || \ + ((x) == TMR6_FILTER_CLK_DIV64)) + +/*! Parameter valid check for PWM pin status */ +#define IS_VALID_PWM_POLARITY(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD) || \ + ((x) == TMR6_PWM_INVT)) + +/*! Parameter valid check for force PWM output pin */ +#define IS_VALID_PWM_FORCE_POLARITY(x) \ +( ((x) == TMR6_PWM_FORCE_INVD) || \ + ((x) == TMR6_PWM_FORCE_LOW) || \ + ((x) == TMR6_PWM_FORCE_HIGH)) + +/*! Parameter valid check for PWM pin status for count start and stop */ +#define IS_VALID_PWM_POLARITY_START_STOP(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD)) + +#define IS_VALID_CNT_STAT(x) \ +( ((x) == TMR6_STAT_START) || \ + ((x) == TMR6_STAT_STOP) || \ + ((x) == TMR6_STAT_OVF) || \ + ((x) == TMR6_STAT_UDF) || \ + ((x) == TMR6_STAT_UP_CNT_MATCH_A) || \ + ((x) == TMR6_STAT_DOWN_CNT_MATCH_A) || \ + ((x) == TMR6_STAT_UP_CNT_MATCH_B) || \ + ((x) == TMR6_STAT_DOWN_CNT_MATCH_B)) + +/*! Parameter valid check for pin mode */ +#define IS_VALID_PIN_MD(x) \ +( ((x) == TMR6_PIN_CMP_OUTPUT) || \ + ((x) == TMR6_PIN_CAPT_INPUT)) + +/*! Parameter valid check for EMB event valid channel */ +#define IS_VALID_EMB_CH(x) \ +( ((x) == TMR6_EMB_EVT_CH0) || \ + ((x) == TMR6_EMB_EVT_CH1) || \ + ((x) == TMR6_EMB_EVT_CH2) || \ + ((x) == TMR6_EMB_EVT_CH3)) + +/*! Parameter valid check for EMB release mode when EMB event invalid */ +#define IS_VALID_EMB_RELEASE_MD(x) \ +( ((x) == TMR6_EMB_RELEASE_IMMED) || \ + ((x) == TMR6_EMB_RELEASE_OVF) || \ + ((x) == TMR6_EMB_RELEASE_UDF) || \ + ((x) == TMR6_EMB_RELEASE_OVF_UDF)) + +/*! Parameter valid check for pin output status when EMB event valid */ +#define IS_VALID_EMB_VALID_PIN_POLARITY(x) \ +( ((x) == TMR6_EMB_PIN_NORMAL) || \ + ((x) == TMR6_EMB_PIN_HIZ) || \ + ((x) == TMR6_EMB_PIN_LOW) || \ + ((x) == TMR6_EMB_PIN_HIGH)) + +/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_UP_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_UP_BUF_ON)) + +/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_ON)) + +/*! Parameter valid check for dead time buffer transfer condition */ +#define IS_VALID_DEADTIME_BUF_TRANS_COND_REG(x) \ +( ((x) == TMR6_DEADTIME_BUF_COND_INVD) || \ + ((x) == TMR6_DEADTIME_BUF_COND_OVF) || \ + ((x) == TMR6_DEADTIME_BUF_COND_UDF) || \ + ((x) == TMR6_DEADTIME_BUF_COND_OVF_UDF)) + +/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */ +#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \ +( ((x) == TMR6_DEADTIME_EQUAL_OFF) || \ + ((x) == TMR6_DEADTIME_EQUAL_ON)) + +/*! Parameter valid check for start condition */ +#define IS_VALID_START_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_START_COND_ALL) == TMR6_START_COND_ALL)) + +/*! Parameter valid check for stop condition */ +#define IS_VALID_STOP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_STOP_COND_ALL) == TMR6_STOP_COND_ALL)) + +/*! Parameter valid check for clear condition */ +#define IS_VALID_CLR_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CLR_COND_ALL) == TMR6_CLR_COND_ALL)) + +/*! Parameter valid check for update condition */ +#define IS_VALID_UPD_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_UPD_COND_ALL) == TMR6_UPD_COND_ALL)) + +/*! Parameter valid check for capture condition */ +#define IS_VALID_CAPT_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CAPT_COND_ALL) == TMR6_CAPT_COND_ALL)) + +/*! Parameter valid check for hardware count up condition */ +#define IS_VALID_CNT_UP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_UP_COND_ALL) == TMR6_CNT_UP_COND_ALL)) + +/*! Parameter valid check for hardware count down condition */ +#define IS_VALID_CNT_DOWN_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_DOWN_COND_ALL) == TMR6_CNT_DOWN_COND_ALL)) + +/*! Parameter valid check for count Mode */ +#define IS_VALID_CNT_MD(x) \ +( ((x) == TMR6_MD_SAWTOOTH) || \ + ((x) == TMR6_MD_TRIANGLE)) + +/*! Parameter valid check for count direction */ +#define IS_VALID_CNT_DIR(x) \ +( ((x) == TMR6_CNT_UP) || \ + ((x) == TMR6_CNT_DOWN)) + +/*! Parameter valid check for count clock division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( ((x) == TMR6_CLK_DIV1) || \ + ((x) == TMR6_CLK_DIV2) || \ + ((x) == TMR6_CLK_DIV4) || \ + ((x) == TMR6_CLK_DIV8) || \ + ((x) == TMR6_CLK_DIV16) || \ + ((x) == TMR6_CLK_DIV32) || \ + ((x) == TMR6_CLK_DIV64) || \ + ((x) == TMR6_CLK_DIV128) || \ + ((x) == TMR6_CLK_DIV256) || \ + ((x) == TMR6_CLK_DIV512) || \ + ((x) == TMR6_CLK_DIV1024)) + +/*! Parameter valid check for count reload mode */ +#define IS_VALID_CNT_RELOAD_MD(x) \ +( ((x) == TMR6_CNT_RELOAD_ON) || \ + ((x) == TMR6_CNT_RELOAD_OFF)) + +/*! Parameter valid check for Z Mask input function mask cycles number */ +#define IS_VALID_ZMASK_CYCLES(x) \ +( ((x) == TMR6_ZMASK_FUNC_INVD) || \ + ((x) == TMR6_ZMASK_CYCLE_4) || \ + ((x) == TMR6_ZMASK_CYCLE_8) || \ + ((x) == TMR6_ZMASK_CYCLE_16)) + +/*! Parameter valid check for Z Mask function of timer6 position unit */ +#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_POS_CLR_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_POS_CLR_ZMASK_FUNC_ON)) + +/*! Parameter valid check for Z Mask function of timer6 revolution unit */ +#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_REVO_CNT_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_REVO_CNT_ZMASK_FUNC_ON)) + +/*! Parameter valid check for software sync control unit */ +#define IS_VALID_SW_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_SW_SYNC_ALL) == TMR6_SW_SYNC_ALL)) + +/*! Unit check for TMR6 which data width is 32 bit */ +#define IS_TMR6_32BIT_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2) || \ + ((x) == CM_TMR6_3) || \ + ((x) == CM_TMR6_4)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR6_Global_Functions TMR6 Global Functions + * @{ + */ + +/** + * @brief Initialize the timer6 count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcTmr6Init Pointer of configuration structure @ref stc_timer6_init_t + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_timer6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6Init) { + /* Check parameters */ + DDL_ASSERT(IS_TMR6_CNT_SRC(pstcTmr6Init->u8CountSrc)); + + if (pstcTmr6Init->u8CountSrc == TMR6_CNT_SRC_SW) { + /* Normal count */ + DDL_ASSERT(IS_VALID_CNT_MD(pstcTmr6Init->sw_count.u32CountMode)); + DDL_ASSERT(IS_VALID_CNT_DIR(pstcTmr6Init->sw_count.u32CountDir)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcTmr6Init->sw_count.u32ClockDiv)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_INIT_MASK, (pstcTmr6Init->sw_count.u32CountMode | pstcTmr6Init->sw_count.u32CountDir | \ + pstcTmr6Init->sw_count.u32ClockDiv)); + } else { + /* Hardware count */ + if (0U != pstcTmr6Init->hw_count.u32CountUpCond) { + DDL_ASSERT(IS_VALID_CNT_UP_COND(pstcTmr6Init->hw_count.u32CountUpCond)); + } + if (0U != pstcTmr6Init->hw_count.u32CountDownCond) { + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(pstcTmr6Init->hw_count.u32CountDownCond)); + } + + WRITE_REG32(TMR6x->HCUPR, pstcTmr6Init->hw_count.u32CountUpCond); + WRITE_REG32(TMR6x->HCDOR, pstcTmr6Init->hw_count.u32CountDownCond); + } + + DDL_ASSERT(IS_VALID_CNT_RELOAD_MD(pstcTmr6Init->u32CountReload)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_OVSTP, pstcTmr6Init->u32CountReload); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + WRITE_REG32(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue); + } else { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcTmr6Init->u32PeriodValue)); + WRITE_REG16(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set timer6 base count mode + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Mode @ref TMR6_Count_Mode_Define + * @retval None + */ +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_MD(u32Mode)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_MODE, u32Mode); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Dir @ref TMR6_Count_Dir_Define + * @retval None + */ +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DIR(u32Dir)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_DIR, u32Dir); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Count direction @ref TMR6_Count_Dir_Define + */ +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + return READ_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_DIR); +} + +/** + * @brief Set timer6 clock division + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Div @ref TMR6_Count_Clock_Define + * @retval None + */ +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_CKDIV, u32Div); +} + +/** + * @brief Timer6 count reload function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP); + } else { + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP); + } +} + +/** + * @brief Hardware increase conditon command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Up_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_UP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCUPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCUPR, u32Cond); + } +} + +/** + * @brief Hardware decrease condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Down_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCDOR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCDOR, u32Cond); + } +} + +/** + * @brief Initialize the timer6 hardware count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] pstcPwmInit Pointer of initialize structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + __IO uint32_t *TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Ch); + + if (NULL != pstcPwmInit) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StartPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StopPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchBPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchBPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchAPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchAPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32UdfPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32OvfPolarity)); + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + WRITE_REG32(*TMR6_GCMxR, pstcPwmInit->u32CompareValue); + } else { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcPwmInit->u32CompareValue)); + WRITE_REG16(*TMR6_GCMxR, pstcPwmInit->u32CompareValue); + } + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, PCNA_BR_REG_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNAR_CMBDCA_POS \ + | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNAR_CMBUCA_POS \ + | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNAR_CMADCA_POS \ + | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNAR_CMAUCA_POS \ + | pstcPwmInit->u32UdfPolarity << TMR6_PCNAR_UDFCA_POS \ + | pstcPwmInit->u32OvfPolarity << TMR6_PCNAR_OVFCA_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCNAR_STPCA_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCNAR_STACA_POS); + } else { + MODIFY_REG32(TMR6x->PCNBR, PCNA_BR_REG_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNBR_CMBDCB_POS \ + | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNBR_CMBUCB_POS \ + | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNBR_CMADCB_POS \ + | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNBR_CMAUCB_POS \ + | pstcPwmInit->u32UdfPolarity << TMR6_PCNBR_UDFCB_POS \ + | pstcPwmInit->u32OvfPolarity << TMR6_PCNBR_OVFCB_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCNBR_STPCB_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCNBR_STACB_POS); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 PWM output command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32Tmp; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + u32Tmp = 0xFFFFFFFFUL; + } else { + u32Tmp = 0UL; + } + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_OUTENA, u32Tmp); + } else { + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_OUTENB, u32Tmp); + } +} + +/** + * @brief Timer6 set pin polarity + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32CountState Polarity set for @ref TMR6_Count_State_Define + * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity) +{ + uint32_t u32PolarityMask = PCONR_REG_POLARITY_MASK; + + uint8_t au8Pos[8] = {TMR6_PCNAR_STACA_POS, TMR6_PCNAR_STPCA_POS, TMR6_PCNAR_OVFCA_POS, TMR6_PCNAR_UDFCA_POS, \ + TMR6_PCNAR_CMAUCA_POS, TMR6_PCNAR_CMADCA_POS, TMR6_PCNAR_CMBUCA_POS, TMR6_PCNAR_CMBDCA_POS + }; + DDL_ASSERT(IS_VALID_PWM_POLARITY(u32Polarity)); + DDL_ASSERT(IS_VALID_CNT_STAT(u32CountState)); + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + u32Polarity <<= au8Pos[u32CountState]; + u32PolarityMask <<= au8Pos[u32CountState]; + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, u32PolarityMask, u32Polarity); + } else { + MODIFY_REG32(TMR6x->PCNBR, u32PolarityMask, u32Polarity); + } +} + +/** + * @brief Timer6 set force polarity when next period + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PWM_FORCE_POLARITY(u32Polarity)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_FORCA, u32Polarity << TMR6_PCNAR_FORCA_POS); + } else { + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_FORCB, u32Polarity << TMR6_PCNBR_FORCB_POS); + } +} + +/** + * @brief Hardware capture condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Input pin select @ref TMR6_Count_Ch_Define + * @param [in] u32Cond Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_capture_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_CAPT_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + __IO uint32_t *HCPxR = (__IO uint32_t *)((uint32_t)&TMR6x->HCPAR + (u32Ch * 4UL)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*HCPxR, u32Cond); + } else { + CLR_REG32_BIT(*HCPxR, u32Cond); + } +} + +/** + * @brief Port input filter function configuration(Trig) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Pin to be configured @ref TMR6_Pin_Define + * @param [in] u32Div Filter clock @ref TMR6_Input_Filter_Clock + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +int32_t TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_VALID_FILTER_CLK(u32Div)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGA, u32Div << TMR6_FCNGR_NOFICKGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGB, u32Div << TMR6_FCNGR_NOFICKGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFICKTA, u32Div << TMR6CR_FCNTR_NOFICKTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFICKTB, u32Div << TMR6CR_FCNTR_NOFICKTB_POS); + break; + case TMR6_INPUT_TRIGC: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFICKTC, u32Div << TMR6CR_FCNTR_NOFICKTC_POS); + break; + case TMR6_INPUT_TRIGD: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFICKTD, u32Div << TMR6CR_FCNTR_NOFICKTD_POS); + break; + + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Port input filter function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Input port to be configured @ref TMR6_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGA, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGB, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFIENTA, ((uint32_t)enNewState) << TMR6CR_FCNTR_NOFIENTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFIENTB, ((uint32_t)enNewState) << TMR6CR_FCNTR_NOFIENTB_POS); + break; + case TMR6_INPUT_TRIGC: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFIENTC, ((uint32_t)enNewState) << TMR6CR_FCNTR_NOFIENTC_POS); + break; + case TMR6_INPUT_TRIGD: + MODIFY_REG32(CM_TMR6CR->FCNTR, TMR6CR_FCNTR_NOFIENTD, ((uint32_t)enNewState) << TMR6CR_FCNTR_NOFIENTD_POS); + break; + + default: + break; + } +} + +/** + * @brief Set channel function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] u32Func IO mode @ref TMR6_Pin_Mode_Define + * @retval None + */ +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PIN_MD(u32Func)); + + switch (u32Ch) { + case TMR6_CH_A: + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_CAPMDA, u32Func); + break; + case TMR6_CH_B: + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_CAPMDB, u32Func); + break; + + default: + break; + } +} + +/** + * @brief Timer6 interrupt enable or disable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32IntType Irq flag, Can be one or any combination of the values from + * @ref TMR6_Int_Flag_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->ICONR, u32IntType); + } else { + CLR_REG32_BIT(TMR6x->ICONR, u32IntType); + } +} + +/** + * @brief Get Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GET_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(TMR6x->STFLR, u32Flag)) { + enStatus = SET; + } + return enStatus; +} + +/** + * @brief Clear Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval None + */ +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR6x->STFLR, u32Flag); +} + +/** + * @brief Get Timer6 period number when valid period function enable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for periods number + */ +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS); +} + +/** + * @brief De-initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x) +{ + uint32_t u32RefRegRstValue; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + u32RefRegRstValue = TMR6_REG_RST_VALUE_U32; + } else { + u32RefRegRstValue = TMR6_REG_RST_VALUE_U16; + } + + WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RST_VALUE); + WRITE_REG32(TMR6x->CNTER, 0UL); + WRITE_REG32(TMR6x->UPDAR, 0UL); + WRITE_REG32(TMR6x->PERAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->ICONR, 0UL); + WRITE_REG32(TMR6x->BCONR, 0UL); + WRITE_REG32(TMR6x->DCONR, 0UL); + WRITE_REG32(TMR6x->PCNAR, 0UL); + WRITE_REG32(TMR6x->PCNBR, 0UL); + WRITE_REG32(TMR6x->FCNGR, 0UL); + WRITE_REG32(CM_TMR6CR->FCNTR, 0UL); + WRITE_REG32(TMR6x->VPERR, 0UL); + WRITE_REG32(TMR6x->STFLR, 0UL); + WRITE_REG32(TMR6x->HSTAR, 0UL); + WRITE_REG32(TMR6x->HSTPR, 0UL); + WRITE_REG32(TMR6x->HCLRR, 0UL); + WRITE_REG32(TMR6x->HUPDR, 0UL); + WRITE_REG32(TMR6x->HCPAR, 0UL); + WRITE_REG32(TMR6x->HCPBR, 0UL); + WRITE_REG32(TMR6x->HCUPR, 0UL); + WRITE_REG32(TMR6x->HCDOR, 0UL); + + WRITE_REG32(CM_TMR6CR->SSTAR, 0UL); + WRITE_REG32(CM_TMR6CR->SSTPR, 0UL); + WRITE_REG32(CM_TMR6CR->SCLRR, 0UL); + WRITE_REG32(CM_TMR6CR->SUPDR, 0UL); +} + +/** + * @brief Timer6 count start + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Start(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 count stop + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 counter register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + WRITE_REG32(TMR6x->CNTER, u32Value); + } else { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(TMR6x->CNTER, u32Value); + } +} + +/** + * @brief Timer6 update register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + WRITE_REG32(TMR6x->UPDAR, u32Value); + } else { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(TMR6x->UPDAR, u32Value); + } +} + +/** + * @brief Timer6 get counter register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for the count register value + */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->CNTER); +} + +/** + * @brief Timer6 get update register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for register value + */ +uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->UPDAR); +} + +/** + * @brief Timer6 set period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @param [in] u32Value Period value for write + * @retval None + */ +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + /* 32bit */ + WRITE_REG32(*TMR6_PERxR, u32Value); + } else { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_PERxR, u32Value); + } +} + +/** + * @brief Timer6 set general compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + /* 32bit */ + WRITE_REG32(*TMR6_GCMxR, u32Value); + } else { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_GCMxR, u32Value); + } +} + +/** + * @brief Timer6 set special compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + /* 32bit */ + WRITE_REG32(*TMR6_SCMxR, u32Value); + } else { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_SCMxR, u32Value); + } +} + +/** + * @brief Timer6 set dead time registerr + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_DeadTime_Reg_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + if (IS_TMR6_32BIT_UNIT(TMR6x)) { + /* 32bit */ + WRITE_REG32(*TMR6_DTxyR, u32Value); + } else { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_DTxyR, u32Value); + } +} + +/** + * @brief Timer6 get general compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_GCMxR); +} + +/** + * @brief Timer6 get special compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_SCMxR); +} + +/** + * @brief Timer6 Get period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + return READ_REG32(*TMR6_PERxR); +} + +/** + * @brief Timer6 get dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Dead time register to be write, @ref TMR6_DeadTime_Reg_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + return READ_REG32(*TMR6_DTxyR); +} + +/** + * @brief Timer6 general compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK, (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond)); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK << BCONR_GEN_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_GEN_CFG_CHB_OFS); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 general compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK, enNewState); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_GEN_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 special compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Special compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHB_OFS); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 special compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_PERIOD_CFG_MASK << BCONR_PERIOD_CFG_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_PERIOD_CFG_OFS); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_PERIOD_CFG_OFS, + ((uint32_t)enNewState) << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 valid period function configuration for special compare function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcValidperiodConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcValidperiodConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidperiodConfig->u32CountCond)); + DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidperiodConfig->u32PeriodInterval)); + + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_PCNTS | TMR6_VPERR_PCNTE, \ + pstcValidperiodConfig->u32CountCond | pstcValidperiodConfig->u32PeriodInterval); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 valid period function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIA, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIA_POS); + } else { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIB, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIB_POS); + } +} + +/** + * @brief Timer6 dead time function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } else { + CLR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } +} + +/** + * @brief DeadTime function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcDeadTimeConfig Timer6 dead time config pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcDeadTimeConfig) { + DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcDeadTimeConfig->u32EqualUpDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcDeadTimeConfig->u32BufUp)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcDeadTimeConfig->u32BufDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_TRANS_COND_REG(pstcDeadTimeConfig->u32UpdateCond)); + + WRITE_REG32(TMR6x->DCONR, pstcDeadTimeConfig->u32EqualUpDown | pstcDeadTimeConfig->u32BufUp \ + | pstcDeadTimeConfig->u32BufDown | pstcDeadTimeConfig->u32UpdateCond); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 unit Z phase input mask config + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcZMaskConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcZMaskConfig) { + DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcZMaskConfig->u32ZMaskCycle)); + DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32PosCountMaskFunc)); + DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32RevoCountMaskFunc)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_ZMASK_CFG_MASK, pstcZMaskConfig->u32ZMaskCycle | \ + pstcZMaskConfig->u32PosCountMaskFunc | pstcZMaskConfig->u32RevoCountMaskFunc); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief EMB function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] pstcEmbConfig Point EMB function Config Pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig) +{ + __IO uint32_t *PCNXR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcEmbConfig) { + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_EMB_CH(pstcEmbConfig->u32ValidCh)); + DDL_ASSERT(IS_VALID_EMB_RELEASE_MD(pstcEmbConfig->u32ReleaseMode)); + DDL_ASSERT(IS_VALID_EMB_VALID_PIN_POLARITY(pstcEmbConfig->u32PinStatus)); + + if (TMR6_CH_A == u32Ch) { + PCNXR = (__IO uint32_t *)&TMR6x->PCNAR; + } else { + PCNXR = (__IO uint32_t *)&TMR6x->PCNBR; + } + + MODIFY_REG32(*PCNXR, PCNA_BR_REG_EMB_CFG_MASK, pstcEmbConfig->u32ValidCh | pstcEmbConfig->u32ReleaseMode \ + | pstcEmbConfig->u32PinStatus); + i32Ret = LL_OK; + } + return i32Ret; + +} + +/** + * @brief Software Sync Start + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStart(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTAR, u32Unit); +} + +/** + * @brief Software Sync Stop + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStop(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTPR, u32Unit); +} + +/** + * @brief Software Sync clear + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncClear(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SCLRR, u32Unit); +} + +/** + * @brief Software Sync update + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncUpdate(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SUPDR, u32Unit); +} + +/** + * @brief Hardware start function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, ((uint32_t)enNewState) << TMR6_HSTAR_STAS_POS); +} + +/** + * @brief Hardware stop function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, ((uint32_t)enNewState) << TMR6_HSTPR_STPS_POS); +} + +/** + * @brief Hardware clear function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, ((uint32_t)enNewState) << TMR6_HCLRR_CLES_POS); +} + +/** + * @brief Hardware update function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HUPDR, TMR6_HUPDR_UPDS, ((uint32_t)enNewState) << TMR6_HUPDR_UPDS_POS); +} + +/** + * @brief Hardware start condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware start, maybe one or any combination of the parameter + * @ref TMR6_hardware_start_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_START_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTAR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTAR, u32Cond); + } +} + +/** + * @brief Hardware stop condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware stop, maybe one or any combination of the parameter + * @ref TMR6_hardware_stop_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STOP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTPR, u32Cond); + } +} + +/** + * @brief Hardware clear condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware clear, maybe one or any combination of the parameter + * @ref TMR6_hardware_clear_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCLRR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCLRR, u32Cond); + } +} + +/** + * @brief Hardware update condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware update, maybe one or any combination of the parameter + * @ref TMR6_hardware_update_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_UPD_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HUPDR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HUPDR, u32Cond); + } +} + +/** + * @brief Set the fields of structure stc_timer6_init_t to default values + * @param [out] pstcTmr6Init Pointer to a @ref stc_timer6_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_StructInit(stc_timer6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegRstValue; + + /* Check structure pointer */ + if (NULL != pstcTmr6Init) { + pstcTmr6Init->u8CountSrc = TMR6_CNT_SRC_SW; + pstcTmr6Init->sw_count.u32ClockDiv = TMR6_CLK_DIV1; + pstcTmr6Init->sw_count.u32CountMode = TMR6_MD_SAWTOOTH; + pstcTmr6Init->sw_count.u32CountDir = TMR6_CNT_UP; + + u32RefRegRstValue = TMR6_REG_RST_VALUE_U32; + pstcTmr6Init->u32CountReload = TMR6_CNT_RELOAD_ON; + pstcTmr6Init->u32PeriodValue = u32RefRegRstValue; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_buf_config_t to default values + * @param [out] pstcBufConfig Pointer to a @ref stc_tmr6_buf_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcBufConfig) { + pstcBufConfig->u32BufNum = TMR6_BUF_SINGLE; + pstcBufConfig->u32BufTransCond = TMR6_BUF_TRANS_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_valid_period_config_t to default values + * @param [out] pstcValidperiodConfig Pointer to a @ref stc_tmr6_valid_period_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcValidperiodConfig) { + pstcValidperiodConfig->u32CountCond = TMR6_VALID_PERIOD_INVD; + pstcValidperiodConfig->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_emb_config_t to default values + * @param [out] pstcEmbConfig Pointer to a @ref stc_tmr6_emb_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcEmbConfig) { + pstcEmbConfig->u32ValidCh = TMR6_EMB_EVT_CH0; + pstcEmbConfig->u32ReleaseMode = TMR6_EMB_RELEASE_IMMED; + pstcEmbConfig->u32PinStatus = TMR6_EMB_PIN_NORMAL; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_deadtime_config_t to default values + * @param [out] pstcDeadTimeConfig Pointer to a @ref stc_tmr6_deadtime_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcDeadTimeConfig) { + pstcDeadTimeConfig->u32EqualUpDown = TMR6_DEADTIME_EQUAL_OFF; + pstcDeadTimeConfig->u32BufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF; + pstcDeadTimeConfig->u32BufDown = TMR6_DEADTIME_CNT_DOWN_BUF_OFF; + pstcDeadTimeConfig->u32UpdateCond = TMR6_DEADTIME_BUF_COND_INVD; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_zmask_config_t to default values + * @param [out] pstcZMaskConfig Pointer to a @ref stc_tmr6_zmask_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcZMaskConfig) { + pstcZMaskConfig->u32ZMaskCycle = TMR6_ZMASK_FUNC_INVD; + pstcZMaskConfig->u32PosCountMaskFunc = TMR6_POS_CLR_ZMASK_FUNC_OFF; + pstcZMaskConfig->u32RevoCountMaskFunc = TMR6_REVO_CNT_ZMASK_FUNC_OFF; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_pwm_init_t to default values + * @param [out] pstcPwmInit Pointer to a @ref stc_tmr6_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegRstValue; + + /* Check structure pointer */ + if (NULL != pstcPwmInit) { + pstcPwmInit->u32StartPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StopPolarity = TMR6_PWM_LOW; + + u32RefRegRstValue = TMR6_REG_RST_VALUE_U32; + pstcPwmInit->u32CountDownMatchBPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountUpMatchBPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountDownMatchAPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountUpMatchAPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32UdfPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32OvfPolarity = TMR6_PWM_LOW; + + pstcPwmInit->u32CompareValue = u32RefRegRstValue; + i32Ret = LL_OK; + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c new file mode 100644 index 0000000000..3906eed6ee --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c @@ -0,0 +1,1178 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.c + * @brief This file provides firmware functions to manage the TMRA(TimerA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmra.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMRA TMRA + * @brief TMRA Driver Library + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Local_Macros TMRA Local Macros + * @{ + */ +/** + * @defgroup TMRA_Registers_Setting_definition TMRA Registers setting definition + * @{ + */ +#define TMRA_REG_TYPE uint16_t +#define TMRA_REG_VALUE_MAX (0xFFFFUL) + +#define SET_VAL_BY_ADDR(addr, v) (*(__IO TMRA_REG_TYPE *)(addr)) = (TMRA_REG_TYPE)(v) +#define GET_VAL_BY_ADDR(addr) (*(__IO TMRA_REG_TYPE *)(addr)) +/** + * @} + */ + +/** + * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask + * @{ + */ +#define TMRA_BCSTR_INT_MASK (TMRA_BCSTR_ITENUDF | TMRA_BCSTR_ITENOVF) +#define TMRA_BCSTR_FLAG_MASK (TMRA_BCSTR_UDFF | TMRA_BCSTR_OVFF) +#define TMRA_FCONR_FILTER_CLK_MASK (0x3UL) +#define TMRA_CCONR_FILTER_CLK_MASK (TMRA_CCONR_NOFICKCP) +#define TMRA_PWM_POLARITY_MASK (TMRA_PCONR_STAC) +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin_Max TMRA Pin With Filter Max + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain pin TMRA_PIN_PWM2. + * @{ + */ +#define TMRA_PIN_MAX (TMRA_PIN_PWM4) +/** + * @} + */ + +/** + * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity + * @{ + */ +#define IS_TMRA_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* Unit check */ +#define IS_TMRA_UNIT(x) \ +( ((x) == CM_TMRA_1) || \ + ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5) || \ + ((x) == CM_TMRA_6) || \ + ((x) == CM_TMRA_7) || \ + ((x) == CM_TMRA_8) || \ + ((x) == CM_TMRA_9) || \ + ((x) == CM_TMRA_10) || \ + ((x) == CM_TMRA_11) || \ + ((x) == CM_TMRA_12)) + +/* Sync unit check */ +#define IS_TMRA_SYNC_UNIT(x) \ +( ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_6) || \ + ((x) == CM_TMRA_8) || \ + ((x) == CM_TMRA_10) || \ + ((x) == CM_TMRA_12)) + +#define IS_TMRA_CH(x) ((x) <= TMRA_CH4) + +/* Unit and channel */ +#define IS_TMRA_UNIT_CH(unit, ch) (IS_TMRA_UNIT(unit) && IS_TMRA_CH(ch)) + +#define IS_TMRA_CNT_SRC(x) (((x) == TMRA_CNT_SRC_SW) || ((x) == TMRA_CNT_SRC_HW)) + +#define IS_TMRA_FUNC(x) (((x) == TMRA_FUNC_CMP) || ((x) == TMRA_FUNC_CAPT)) + +#define IS_TMRA_DIR(x) (((x) == TMRA_DIR_DOWN) || ((x) == TMRA_DIR_UP)) + +#define IS_TMRA_MD(x) (((x) == TMRA_MD_SAWTOOTH) || ((x) == TMRA_MD_TRIANGLE)) + +/* Counter reload */ +#define IS_TMRA_CNT_RELOAD(x) (((x) == TMRA_CNT_RELOAD_DISABLE) || ((x) == TMRA_CNT_RELOAD_ENABLE)) + +#define IS_TMRA_CMPVAL_BUF_CH(x) (((x) == TMRA_CH1) || ((x) == TMRA_CH3)) + +#define IS_TMRA_CLK_DIV(x) \ +( ((x) == TMRA_CLK_DIV1) || \ + ((x) == TMRA_CLK_DIV2) || \ + ((x) == TMRA_CLK_DIV4) || \ + ((x) == TMRA_CLK_DIV8) || \ + ((x) == TMRA_CLK_DIV16) || \ + ((x) == TMRA_CLK_DIV32) || \ + ((x) == TMRA_CLK_DIV64) || \ + ((x) == TMRA_CLK_DIV128) || \ + ((x) == TMRA_CLK_DIV256) || \ + ((x) == TMRA_CLK_DIV512) || \ + ((x) == TMRA_CLK_DIV1024)) + +#define IS_TMRA_FILTER_PIN(x) ((x) <= TMRA_PIN_MAX) + +#define IS_TMRA_CNT_UP_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_UP_COND_ALL) + +#define IS_TMRA_CNT_DOWN_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_DOWN_COND_ALL) + +#define IS_TMRA_INT(x) IS_TMRA_BIT_MASK(x, TMRA_INT_ALL) + +#define IS_TMRA_EVT(x) IS_TMRA_BIT_MASK(x, TMRA_EVT_ALL) + +#define IS_TMRA_FLAG(x) IS_TMRA_BIT_MASK(x, TMRA_FLAG_ALL) + +#define IS_TMRA_CAPT_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CAPT_COND_ALL) + +#define IS_TMRA_FILTER_CLK_DIV(x) ((x) <= TMRA_FILTER_CLK_DIV64) + +/* Special check of TMRA_1 & TMRA_2 of HC32M423 */ + +/* Unit and interrupt */ +#define IS_TMRA_UNIT_INT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_INT(x)) + +/* Unit and event of channel */ +#define IS_TMRA_CH_EVT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_EVT(x)) + +/* Unit and pin with filter */ +#define IS_TMRA_UNIT_FPIN(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FILTER_PIN(x)) + +/* Unit and flag */ +#define IS_TMRA_UNIT_FLAG(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FLAG(x)) + +#define IS_TMRA_CMPVAL_BUF_COND(x) \ +( ((x) == TMRA_BUF_TRANS_COND_OVF_UDF_CLR) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK) || \ + ((x) == TMRA_BUF_TRANS_COND_VALLEY) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK_VALLEY)) + +#define IS_TMRA_PWM_START_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_STOP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_CMP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_PERIOD_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_FORCE_POLARITY(x) \ +( ((x) == TMRA_PWM_FORCE_INVD) || \ + ((x) == TMRA_PWM_FORCE_LOW) || \ + ((x) == TMRA_PWM_FORCE_HIGH)) + +#define IS_TMRA_PWM_POLARITY(st, pol) \ +( (((st) == TMRA_CNT_STAT_START) && IS_TMRA_PWM_START_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_STOP) && IS_TMRA_PWM_STOP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_CMP) && IS_TMRA_PWM_CMP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_PERIOD) && IS_TMRA_PWM_PERIOD_POLARITY(pol))) + +#define IS_TMRA_START_COND(x) IS_TMRA_BIT_MASK((x), TMRA_START_COND_ALL) + +#define IS_TMRA_STOP_COND(x) IS_TMRA_BIT_MASK((x), TMRA_STOP_COND_ALL) + +#define IS_TMRA_CLR_COND(x) IS_TMRA_BIT_MASK((x), TMRA_CLR_COND_ALL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros + * @{ + */ +#define TMRA_PIN_PWM_OFFSET (3U) + +#define TMRA_CH_NUM (4U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Functions TMRA Global Functions + * @{ + */ +/** + * @brief Initializes the specified TMRA peripheral according to the specified parameters + * in the structure stc_tmra_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + if (pstcTmraInit != NULL) { + DDL_ASSERT(IS_TMRA_CNT_SRC(pstcTmraInit->u8CountSrc)); + + if (pstcTmraInit->u8CountSrc == TMRA_CNT_SRC_SW) { + DDL_ASSERT(IS_TMRA_MD(pstcTmraInit->sw_count.u16CountMode)); + DDL_ASSERT(IS_TMRA_DIR(pstcTmraInit->sw_count.u16CountDir)); + DDL_ASSERT(IS_TMRA_CLK_DIV(pstcTmraInit->sw_count.u16ClockDiv)); + + WRITE_REG16(TMRAx->BCSTR, pstcTmraInit->sw_count.u16CountMode | \ + pstcTmraInit->sw_count.u16CountDir | \ + pstcTmraInit->sw_count.u16ClockDiv); + } else { + DDL_ASSERT(IS_TMRA_CNT_UP_COND(pstcTmraInit->hw_count.u16CountUpCond) || \ + (pstcTmraInit->hw_count.u16CountUpCond == TMRA_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(pstcTmraInit->hw_count.u16CountDownCond) || \ + (pstcTmraInit->hw_count.u16CountDownCond == TMRA_CNT_DOWN_COND_INVD)); + WRITE_REG16(TMRAx->HCUPR, pstcTmraInit->hw_count.u16CountUpCond); + WRITE_REG16(TMRAx->HCDOR, pstcTmraInit->hw_count.u16CountDownCond); + } + + /* Counter reload */ + DDL_ASSERT(IS_TMRA_CNT_RELOAD(pstcTmraInit->u16CountReload)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_OVSTP, pstcTmraInit->u16CountReload); + + /* Specifies period value. */ + TMRA_SetPeriodValue(TMRAx, pstcTmraInit->u32PeriodValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the TMRA initialization structure. + * @param [out] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcTmraInit != NULL) { + pstcTmraInit->u8CountSrc = TMRA_CNT_SRC_SW; + pstcTmraInit->sw_count.u16ClockDiv = TMRA_CLK_DIV1; + pstcTmraInit->sw_count.u16CountMode = TMRA_MD_SAWTOOTH; + pstcTmraInit->sw_count.u16CountDir = TMRA_DIR_UP; + pstcTmraInit->u32PeriodValue = (TMRA_REG_TYPE)0xFFFFFFFFUL; + /* Counter reload */ + pstcTmraInit->u16CountReload = TMRA_CNT_RELOAD_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the counting mode for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Mode Count mode. + * This parameter can be a value of @ref TMRA_Count_Mode + * @arg TMRA_MD_SAWTOOTH: Count mode is sawtooth wave. + * @arg TMRA_MD_TRIANGLE: Count mode is triangle wave. + * @retval None + */ +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_MD(u16Mode)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_MODE, u16Mode); +} + +/** + * @brief Specifies the counting direction for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Dir Count direction. + * This parameter can be a value of @ref TMRA_Count_Dir + * @arg TMRA_DIR_DOWN: TMRA count down. + * @arg TMRA_DIR_UP: TMRA count up. + * @retval None + */ +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint16_t u16Dir) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_DIR(u16Dir)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_DIR, u16Dir); +} + +/** + * @brief Specifies the clcok divider for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Div Clcok divider. + * This parameter can be a value of @ref TMRA_Clock_Divider + * @retval None + */ +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLK_DIV(u16Div)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_CKDIV, u16Div); +} + +/** + * @brief Enable or disable the specified hardware count up condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count up condition. + * This parameter can be values of @ref TMRA_Hard_Count_Up_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_UP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCUPR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCUPR, u16Cond); + } +} + +/** + * @brief Enable or disable the specified hardware count down condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count down condition. + * This parameter can be values of @ref TMRA_Hard_Count_Down_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCDOR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCDOR, u16Cond); + } +} + +/** + * @brief Specifies function mode of TMRA. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Func Function mode of TRMA. + * This parameter can be a value of @ref TMRA_Function_Mode + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval None + */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_FUNC(u16Func)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32CCONRAddr), TMRA_CCONR_CAPMD, u16Func); +} + +/** + * @brief Initializes the PWM according to the specified parameters + * in the structure stc_tmra_pwm_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit) +{ + uint32_t u32CMPARAddr; + uint32_t u32PCONRAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + if (pstcPwmInit != NULL) { + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcPwmInit->u16StartPolarity)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcPwmInit->u16StopPolarity)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcPwmInit->u16CompareMatchPolarity)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcPwmInit->u16PeriodMatchPolarity)); + + u32Ch *= 4U; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch; + SET_VAL_BY_ADDR(u32CMPARAddr, pstcPwmInit->u32CompareValue); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + u32Ch; + RW_MEM16(u32PCONRAddr) = (uint16_t)((pstcPwmInit->u16StartPolarity << TMRA_PCONR_STAC_POS) | \ + (pstcPwmInit->u16StopPolarity << TMRA_PCONR_STPC_POS) | \ + (pstcPwmInit->u16CompareMatchPolarity << TMRA_PCONR_CMPC_POS) | \ + (pstcPwmInit->u16PeriodMatchPolarity << TMRA_PCONR_PERC_POS)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the PWM initialization structure. + * @param [out] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcPwmInit != NULL) { + pstcPwmInit->u32CompareValue = TMRA_REG_VALUE_MAX; + pstcPwmInit->u16StartPolarity = TMRA_PWM_HIGH; + pstcPwmInit->u16StopPolarity = TMRA_PWM_LOW; + pstcPwmInit->u16CompareMatchPolarity = TMRA_PWM_INVT; + pstcPwmInit->u16PeriodMatchPolarity = TMRA_PWM_INVT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the PWM ouput of the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS), enNewState); +} + +/** + * @brief Specifies the ouput polarity of the PWM at the specified state of counter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u8CountState TMRA counter state. + * This parameter can be a value @ref TMRA_Counter_State + * @param [in] u16Polarity The polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Polarity + * @retval None + * @note The polarity(high or low) of couting start is only valid when the clock is not divided(BCSTR.CKDIV == 0). + */ +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_POLARITY(u8CountState, u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), + (uint16_t)TMRA_PWM_POLARITY_MASK << (u8CountState * 2U), + u16Polarity << (u8CountState * 2U)); +} + +/** + * @brief Specifies the force polarity of the PWM. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Polarity The force polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Force_Polarity + * @retval None + */ +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), TMRA_PCONR_FORC, u16Polarity); +} + +/** + * @brief Enable or disable the specified capture condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Cond The capture condition. + * This parameter can be a value @ref TMRA_Capture_Cond + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_CAPT_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + +#if defined __DEBUG + if ((u16Cond & (TMRA_CAPT_COND_TRIG_RISING | TMRA_CAPT_COND_TRIG_FALLING)) != 0U) { + DDL_ASSERT(u32Ch == TMRA_CH3); + } +#endif + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + if (enNewState == ENABLE) { + SET_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } else { + CLR_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } +} + +/** + * @brief Enable or disable hardware start condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware start condition. + * This parameter can be a value @ref TMRA_Hardware_Start_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_START_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware stop condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware stop condition. + * This parameter can be a value @ref TMRA_Hardware_Stop_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_STOP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware clear condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware clear condition. + * This parameter can be a value @ref TMRA_Hardware_Clear_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLR_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Specifies the clock divider of filter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be a value of @ref TMRA_Filter_Pin + * @param [in] u16Div The clock source divider of the filter. + * This parameter can be a value of @ref TMRA_Filter_Clock_Divider + * @arg TMRA_FILTER_CLK_DIV1: The filter clock is the clock of timerA / 1. + * @arg TMRA_FILTER_CLK_DIV4: The filter clock is the clock of timerA / 4. + * @arg TMRA_FILTER_CLK_DIV16: The filter clock is the clock of timerA / 16. + * @arg TMRA_FILTER_CLK_DIV64: The filter clock is the clock of timerA / 64. + * @retval None + */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div) +{ + uint32_t u32Ch; + uint32_t u32CCONRAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u16Div)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + MODIFY_REG16(TMRAx->FCONR, + (TMRA_FCONR_FILTER_CLK_MASK << au8Offset[u32Pin]), + (u16Div << au8Offset[u32Pin])); + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32CCONRAddr), + TMRA_CCONR_FILTER_CLK_MASK, + (u16Div << TMRA_CCONR_NOFICKCP_POS)); + } +} + +/** + * @brief Enable or disable the filter function of the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be values of @ref TMRA_Filter_Pin + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState) +{ + uint8_t u8EnPos; + uint32_t u32Ch; + uint32_t u32RegAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + u32RegAddr = (uint32_t)&TMRAx->FCONR; + u8EnPos = au8Offset[u32Pin]; + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32RegAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + u8EnPos = TMRA_CCONR_NOFIENCP_POS; + } + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, u8EnPos), enNewState); +} + +/** + * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx) +{ + uint32_t i; + uint32_t u32ChNum = TMRA_CH_NUM; + uint32_t u32AddrOffset; + uint32_t u32PERARAddr; + uint32_t u32CNTERAddr; + uint32_t u32CMPARAddr; + uint32_t u32CCONRAddr; + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1; + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1; + + for (i = 0U; i < u32ChNum; i++) { + u32AddrOffset = i * 4U; + RW_MEM16(u32CMPARAddr + u32AddrOffset) = 0xFFFFU; + RW_MEM16(u32CCONRAddr + u32AddrOffset) = 0x0U; + RW_MEM16(u32PCONRAddr + u32AddrOffset) = 0x0U; + } + + SET_VAL_BY_ADDR(u32PERARAddr, 0xFFFFFFFFUL); + SET_VAL_BY_ADDR(u32CNTERAddr, 0x0U); + WRITE_REG16(TMRAx->BCSTR, 0x2U); + WRITE_REG16(TMRAx->ICONR, 0x0U); + WRITE_REG16(TMRAx->ECONR, 0x0U); + WRITE_REG16(TMRAx->FCONR, 0x0U); + WRITE_REG16(TMRAx->STFLR, 0x0U); + WRITE_REG16(TMRAx->HCONR, 0x0U); + WRITE_REG16(TMRAx->HCUPR, 0x0U); + WRITE_REG16(TMRAx->HCDOR, 0x0U); + + WRITE_REG16(TMRAx->BCONR1, 0x0U); + WRITE_REG16(TMRAx->BCONR2, 0x0U); +} + +/** + * @brief Get the counting direction of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint16_t type value of counting direction. + * -TMRA_DIR_DOWN: TMRA count down. + * -TMRA_DIR_UP: TMRA count up. + */ +uint16_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return READ_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_DIR); +} + +/** + * @brief Set period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The period value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32PERARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + SET_VAL_BY_ADDR(u32PERARAddr, u32Value); +} + +/** + * @brief Get period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of period value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->PERAR); +} + +/** + * @brief Set general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The general counter value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32CNTERAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + SET_VAL_BY_ADDR(u32CNTERAddr, u32Value); +} + +/** + * @brief Get general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of counter value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->CNTER); +} + +/** + * @brief Set comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] u32Value The comparison value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + SET_VAL_BY_ADDR(u32CMPARAddr, u32Value); +} + +/** + * @brief Get comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval An uint32_t type type value of comparison value value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + return GET_VAL_BY_ADDR(u32CMPARAddr); +} + +/* Sync start. */ +/** + * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function, + * start the symmetric odd unit can start the even unit at the same time. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x(x is an even number) + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_SYNC_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMRAx->BCSTR; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, TMRA_BCSTR_SYNST_POS), enNewState); +} + +/* Reload and continue counting when overflow/underflow? */ +/** + * @brief Enable or disable reload and continue counting when overflow/underflow. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + CLR_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_OVSTP); + } else { + SET_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_OVSTP); + } +} + +/** + * @brief Specifies the condition of compare value buffer transmission. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] u16Cond Buffer condition of the specified TMRA unit. + * This parameter can be a value of @ref TMRA_Cmp_Value_Buf_Trans_Cond + * @arg TMRA_BUF_TRANS_COND_OVF_UDF_CLR: This configuration value applies to non-triangular wave counting mode. + * When counting overflow or underflow or counting register was cleared, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK: In triangle wave count mode, when count reached peak, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_VALLEY: In triangle wave count mode, when count reached valley, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @retval None + */ +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_COND(u16Cond)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32BCONRAddr), TMRA_BUF_TRANS_COND_PEAK_VALLEY, u16Cond); +} + +/** + * @brief Enable or disable compare value buffer. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS), enNewState); +} + +/** + * @brief Get the status of the specified flag. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be a value of @ref TMRA_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + uint16_t u16BCSTR; + uint16_t u16STFLR; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + u16BCSTR = (uint16_t)(u32Flag & TMRA_BCSTR_FLAG_MASK); + u16STFLR = (uint16_t)(u32Flag >> 16U); + u16BCSTR = READ_REG16_BIT(TMRAx->BCSTR, u16BCSTR); + u16STFLR = READ_REG16_BIT(TMRAx->STFLR, u16STFLR); + + if ((u16BCSTR != 0U) || (u16STFLR != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flags. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be values of @ref TMRA_Status_Flag + * @retval None + */ +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + CLR_REG16_BIT(TMRAx->BCSTR, u32Flag & TMRA_BCSTR_FLAG_MASK); + CLR_REG16_BIT(TMRAx->STFLR, u32Flag >> 16U); +} + +/** + * @brief Enable of disable the specified interrupts of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32IntType The interrupt type of TMRA. + * This parameter can be values of @ref TMRA_Interrupt_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32BCSTR; + uint32_t u32ICONR; + + DDL_ASSERT(IS_TMRA_UNIT_INT(TMRAx, u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCSTR = u32IntType & TMRA_BCSTR_INT_MASK; + u32ICONR = u32IntType >> 16U; + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->BCSTR, u32BCSTR); + SET_REG16_BIT(TMRAx->ICONR, u32ICONR); + } else { + CLR_REG16_BIT(TMRAx->BCSTR, u32BCSTR); + CLR_REG16_BIT(TMRAx->ICONR, u32ICONR); + } +} + +/** + * @brief Enable of disable the specified event of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32EventType The event type of TMRA. + * This parameter can be values of @ref TMRA_Event_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_CH_EVT(TMRAx, u32EventType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->ECONR, u32EventType); + } else { + CLR_REG16_BIT(TMRAx->ECONR, u32EventType); + } +} + +/** + * @brief Start the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Start(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + SET_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} + +/** + * @brief Stop the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + CLR_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c new file mode 100644 index 0000000000..ef9ca161f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c @@ -0,0 +1,216 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.c + * @brief This file provides firmware functions to manage the True Random + * Number Generator(TRNG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_trng.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TRNG TRNG + * @brief TRNG Driver Library + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TRNG_Local_Macros TRNG Local Macros + * @{ + */ +#define TRNG_TIMEOUT (20000UL) + +/** + * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity + * @{ + */ +#define IS_TRNG_SHIFT_CNT(x) \ +( ((x) == TRNG_SHIFT_CNT32) || \ + ((x) == TRNG_SHIFT_CNT64) || \ + ((x) == TRNG_SHIFT_CNT128) || \ + ((x) == TRNG_SHIFT_CNT256)) + +#define IS_RNG_RELOAD_INIT_VAL_EN(x) \ +( ((x) == TRNG_RELOAD_INIT_VAL_ENABLE) || \ + ((x) == TRNG_RELOAD_INIT_VAL_DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TRNG_Global_Functions TRNG Global Functions + * @{ + */ + +/** + * @brief Initializes TRNG. + * @param [in] u32ShiftCount TRNG shift control. This parameter can be a value of @ref TRNG_Shift_Ctrl + * @arg TRNG_SHIFT_CNT32: Shift 32 times when capturing random noise. + * @arg TRNG_SHIFT_CNT64: Shift 64 times when capturing random noise. + * @arg TRNG_SHIFT_CNT128: Shift 128 times when capturing random noise. + * @arg TRNG_SHIFT_CNT256: Shift 256 times when capturing random noise. + * @param [in] u32ReloadInitValueEn Enable or disable load new initial value. + * This parameter can be a value of @ref TRNG_Reload_Init_Value + * @arg TRNG_RELOAD_INIT_VAL_ENABLE: Enable load new initial value. + * @arg TRNG_RELOAD_INIT_VAL_DISABLE: Disable load new initial value. + * @retval None + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn) +{ + DDL_ASSERT(IS_TRNG_SHIFT_CNT(u32ShiftCount)); + DDL_ASSERT(IS_RNG_RELOAD_INIT_VAL_EN(u32ReloadInitValueEn)); + WRITE_REG32(CM_TRNG->MR, u32ShiftCount | u32ReloadInitValueEn); +} + +/** + * @brief Start TRNG and get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t u32TimeCount = TRNG_TIMEOUT; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Enable TRNG circuit. */ + WRITE_REG32(bCM_TRNG->CR_b.EN, 1U); + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); + /* Wait generating done. */ + i32Ret = LL_ERR_TIMEOUT; + while (u32TimeCount-- != 0UL) { + if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) { + i32Ret = LL_OK; + break; + } + } + + if (i32Ret == LL_OK) { + /* Get the random number. */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0); + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1); + } + } else { + /* Stop TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 0U); + } + /* Disable TRNG circuit. */ + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } + + return i32Ret; +} + +/** + * @brief Start TRNG + * @param None + * @retval None + */ +void TRNG_Start(void) +{ + /* Enable TRNG circuit. */ + WRITE_REG32(bCM_TRNG->CR_b.EN, 1U); + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); +} + +/** + * @brief Get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Get the random number. */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0); + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1); + } + /* Disable TRNG circuit. */ + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c new file mode 100644 index 0000000000..ef49f34c89 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c @@ -0,0 +1,2359 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.c + * @brief This file provides firmware functions to manage the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USART USART + * @brief USART Driver Library + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Local_Macros USART Local Macros + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Unit USART Check Parameters Validity Unit + * @{ + */ +#define IS_USART_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART3) || \ + ((x) == CM_USART4) || \ + ((x) == CM_USART5) || \ + ((x) == CM_USART6) || \ + ((x) == CM_USART7) || \ + ((x) == CM_USART8) || \ + ((x) == CM_USART9) || \ + ((x) == CM_USART10)) +#define IS_USART_INTEGER_UNIT(x) \ +( ((x) == CM_USART5) || \ + ((x) == CM_USART10)) +#define IS_USART_SMARTCARD_UNIT(x) \ +( ((x) != CM_USART5) && \ + ((x) != CM_USART10)) +#define IS_USART_LIN_UNIT(x) \ +( ((x) == CM_USART5) || \ + ((x) == CM_USART10)) +#define IS_USART_STOP_MD_UNIT(x) ((x) == CM_USART1) +#define IS_USART_TIMEOUT_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART6) || \ + ((x) == CM_USART7)) +/** + * @} + */ + +#define IS_USART_FUNC(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FUNC_ALL) == USART_FUNC_ALL)) + +#define IS_USART_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FLAG_ALL) == USART_FLAG_ALL)) + +#define IS_USART_TRANS_TYPE(x) \ +( ((x) == USART_TRANS_ID) || \ + ((x) == USART_TRANS_DATA)) + +#define IS_USART_PARITY(x) \ +( ((x) == USART_PARITY_ODD) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_NONE)) + +#define IS_USART_DATA_WIDTH(x) \ +( ((x) == USART_DATA_WIDTH_8BIT) || \ + ((x) == USART_DATA_WIDTH_9BIT)) + +#define IS_USART_STOPBIT(x) \ +( ((x) == USART_STOPBIT_1BIT) || \ + ((x) == USART_STOPBIT_2BIT)) + +#define IS_USART_FIRST_BIT(x) \ +( ((x) == USART_FIRST_BIT_MSB) || \ + ((x) == USART_FIRST_BIT_LSB)) + +#define IS_USART_OVER_SAMPLE_BIT(x) \ +( ((x) == USART_OVER_SAMPLE_8BIT) || \ + ((x) == USART_OVER_SAMPLE_16BIT)) + +#define IS_USART_START_BIT_POLARITY(x) \ +( ((x) == USART_START_BIT_LOW) || \ + ((x) == USART_START_BIT_FALLING)) + +#define IS_USART_CLK_SRC(x) \ +( ((x) == USART_CLK_SRC_EXTCLK) || \ + ((x) == USART_CLK_SRC_INTERNCLK)) + +#define IS_USART_CK_OUTPUT(x) \ +( ((x) == USART_CK_OUTPUT_ENABLE) || \ + ((x) == USART_CK_OUTPUT_DISABLE)) + +#define IS_USART_CLK_DIV(x) \ +( ((x) == USART_CLK_DIV1) || \ + ((x) == USART_CLK_DIV4) || \ + ((x) == USART_CLK_DIV16) || \ + ((x) == USART_CLK_DIV64)) + +#define IS_USART_DATA(x) ((x) <= 0x01FFUL) + +/** + * @defgroup USART_Check_Parameters_Validity_Hardware_Flow_Control USART Check Parameters Validity Hardware Flow Control + * @{ + */ +#define IS_USART_HW_FLOWCTRL(x) \ +( ((x) == USART_HW_FLOWCTRL_NONE) || \ + ((x) == USART_HW_FLOWCTRL_CTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS_CTS)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Smartcard_Clock USART Check Parameters Validity Smartcard Clock + * @{ + */ +#define IS_USART_SMARTCARD_ETU_CLK(x) \ +( ((x) == USART_SC_ETU_CLK32) || \ + ((x) == USART_SC_ETU_CLK64) || \ + ((x) == USART_SC_ETU_CLK128) || \ + ((x) == USART_SC_ETU_CLK256) || \ + ((x) == USART_SC_ETU_CLK372)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Stopmode_Filter USART Check Parameters Validity Stopmode Filter + * @{ + */ +#define IS_USART_STOP_MD_FILTER(x) \ +( ((x) == USART_STOP_MD_FILTER_LVL1) || \ + ((x) == USART_STOP_MD_FILTER_LVL2) || \ + ((x) == USART_STOP_MD_FILTER_LVL3) || \ + ((x) == USART_STOP_MD_FILTER_LVL4)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Timeout_Function USART Check Parameters Validity Timeout Function + * @{ + */ +#define IS_USART_TIMEOUT_FUNC(x, func) \ +( IS_USART_TIMEOUT_UNIT(x) || \ + ((!IS_USART_TIMEOUT_UNIT(x)) && (((func) & (USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT)) == 0UL))) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_LIN_Function USART Check Parameters Validity LIN Function + * @{ + */ +#define IS_USART_LIN_FUNC(x, func) \ +( IS_USART_LIN_UNIT(x) || \ + ((!IS_USART_LIN_UNIT(x)) && (((func) & USART_LIN_FUNC_MASK) == 0UL))) + +#define IS_USART_LIN_BMC_CLK_DIV(x) \ +( ((x) == USART_LIN_BMC_CLK_DIV1) || \ + ((x) == USART_LIN_BMC_CLK_DIV2) || \ + ((x) == USART_LIN_BMC_CLK_DIV4) || \ + ((x) == USART_LIN_BMC_CLK_DIV8)) + +#define IS_USART_LIN_SEND_BREAK_MD(x) \ +( ((x) == USART_LIN_SEND_BREAK_MD_SBK) || \ + ((x) == USART_LIN_SEND_BREAK_MD_TDR)) + +#define IS_USART_LIN_DETECT_BREAK_LEN(x) \ +( ((x) == USART_LIN_DETECT_BREAK_10BIT) || \ + ((x) == USART_LIN_DETECT_BREAK_11BIT)) + +#define IS_USART_LIN_SEND_BREAK_LEN(x) \ +( ((x) == USART_LIN_SEND_BREAK_10BIT) || \ + ((x) == USART_LIN_SEND_BREAK_11BIT) || \ + ((x) == USART_LIN_SEND_BREAK_13BIT) || \ + ((x) == USART_LIN_SEND_BREAK_14BIT)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup USART_Flag_Error_Mask USART Flag Error Mask + * @{ + */ +#define USART_FLAG_ERR_MASK (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | \ + USART_FLAG_PARITY_ERR) +/** + * @} + */ + +/** + * @defgroup USART_Registers_Reset_Value_definition USART Registers Reset Value + * @{ + */ +#define USART_CR1_RST_VALUE (0x80000000UL) + +#define USART_CR2_RST_VALUE (0x0600UL) +/** + * @} + */ + +/** + * @defgroup USART_LIN_Function_Mask USART LIN Function Mask + * @{ + */ +#define USART_LIN_FUNC_OFFSET (16U) + +#define USART_LIN_FUNC_MASK (USART_LIN | \ + USART_LIN_ERR | \ + USART_LIN_WKUP | \ + USART_LIN_INT_WKUP | \ + USART_LIN_INT_BREAK | \ + USART_LIN_INT_ERR) +/** + * @} + */ + +/** + * @defgroup USART_Data_Register USART Data Register + * @{ + */ +#define USART_TXD_ADDR(_UNITx_) ((uint32_t)(&(_UNITx_)->DR)) +#define USART_RXD_ADDR(_UNITx_) ((uint32_t)(&(_UNITx_)->DR) + 2UL) + +#define USART_TXD(_UNITx_) ((__IO uint16_t *)USART_TXD_ADDR(_UNITx_)) +#define USART_RXD(_UNITx_) ((__IO uint16_t *)USART_RXD_ADDR(_UNITx_)) +/** + * @} + */ + +/** + * @defgroup USART_Redefine_Bits USART Redefine Bits + * @{ + */ +#define USART_CR_SCEN (0x00000020UL) +#define USART_CR_FBME (0x20000000UL) +#define USART_BRR_DIV_FRACTION_MASK (0x0000007FUL) +/** + * @} + */ + +/** + * @defgroup USART_BRR_Division_Max USART BRR Register Division Max + * @{ + */ +#define USART_BRR_DIV_INTEGER_MAX (0xFFUL) +#define USART_BRR_DIV_FRACTION_MAX (0x7FUL) +/** + * @} + */ + +/** + * @defgroup USART_Default_Baudrate USART Default Baudrate + * @{ + */ +#define USART_DEFAULT_BAUDRATE (9600UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Functions USART Local Functions + * @{ + */ +/** + * @brief Try to wait the expected status of specified flags + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag + * This parameter can be one of the following values: + * @arg USART_FLAG_RX_FULL: Receive data register not empty flag + * @arg USART_FLAG_TX_CPLT: Transmission complete flag + * @arg USART_FLAG_TX_EMPTY: Transmit data register empty flag + * @arg USART_FLAG_OVERRUN: Overrun error flag + * @arg USART_FLAG_FRAME_ERR: Framing error flag + * @arg USART_FLAG_PARITY_ERR:Parity error flag + * @arg USART_FLAG_RX_TIMEOUT: Receive timeout flag + * @arg USART_FLAG_MX_PROCESSOR: Receive processor ID flag + * @arg USART_FLAG_LIN_ERR: LIN bus error flag + * @arg USART_FLAG_LIN_WKUP: LIN wakeup signal detection flag + * @arg USART_FLAG_LIN_BREAK: LIN break signal detection flag + * @param [in] enStatus Expected status + * This parameter can be one of the following values: + * @arg SET: Wait flag set + * @arg RESET: Wait flag reset + * @param [in] u32Timeout Maximum count(Max value @ref USART_Max_Timeout) of trying to get status + * @retval int32_t: + * - LL_OK: Complete wait the expected status of the specified flags. + * - LL_ERR_TIMEOUT: Wait timeout. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +static int32_t USART_WaitStatus(const CM_USART_TypeDef *USARTx, + uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32To = 0UL; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + while (USART_GetStatus(USARTx, u32Flag) != enStatus) { + /* Block checking flag if timeout value is USART_TIMEOUT_MAX */ + if ((u32To > u32Timeout) && (u32Timeout < USART_MAX_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + + u32To++; + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t UART_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + uint64_t u64Temp; + uint32_t DIV_Integer; + float32_t f32Err; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + OVER8 = (0UL == READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8)) ? 0UL : 1UL; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = ((((C * 10UL) / (B * 8UL * (2UL - OVER8))) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + float32_t f32Err; + uint64_t u64Temp; + uint32_t DIV_Integer; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = ((((C * 10UL) / (B * 4UL)) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if ((DIV_Integer > 0UL) && (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX)) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for smart-card mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + uint64_t u64Temp; + uint32_t DIV_Integer; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + float32_t f32Err; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + + DIV_Integer = (((C * 10UL) / (B * BCN * 2UL) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t UART_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check parameter */ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + OVER8 = (0UL == READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8)) ? 0UL : 1UL; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = (C / (B * 8UL * (2UL - OVER8))) - 1UL; + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check parameter */ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = (C / (B * 4UL)) - 1UL; + + if ((DIV_Integer > 0UL) && (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX)) { + /* Clock sync mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B) / C - 128 */ + + /* u64Temp = (4 * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + DIV_Integer = (C / (B * BCN * 2UL)) - 1UL; + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + /* Smartcard mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (2 * BCN * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t UART_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = UART_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = UART_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t ClockSync_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = ClockSync_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = ClockSync_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t SmartCard_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = SmartCard_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = SmartCard_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + return i32Ret; +} + +/** + * @brief Get USART clock frequency value. + * @retval USART clock frequency value + */ +static uint32_t USART_GetBusClockFreq(void) +{ + uint32_t u32BusClock; + + u32BusClock = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + + return u32BusClock; +} + +/** + * @brief Get USART clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetUsartClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartDiv; + uint32_t u32UsartClock; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(); + u32UsartDiv = (1UL << (READ_REG32_BIT((USARTx)->PR, USART_PR_PSC) * 2UL)); + + u32UsartClock = u32BusClock / u32UsartDiv; + return u32UsartClock; +} + +/** + * @brief Get USART BMC clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART BMC clock frequency value + */ +static uint32_t USART_GetLinBmcClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartBmcDiv; + uint32_t u32UsartBmcClock; + + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(); + u32UsartBmcDiv = (1UL << (READ_REG32_BIT((USARTx)->PR, USART_PR_LBMPSC) >> USART_PR_LBMPSC_POS)); + + u32UsartBmcClock = u32BusClock / u32UsartBmcDiv; + return u32UsartBmcClock; +} + +/** + * @} + */ + +/** + * @defgroup USART_Global_Functions USART Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_usart_clocksync_init_t to default values. + * @param [out] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL. + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + pstcClockSyncInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcClockSyncInit->u32ClockDiv = USART_CLK_DIV1; + pstcClockSyncInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcClockSyncInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcClockSyncInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize clock synchronization function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcClockSyncInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcClockSyncInit->u32FirstBit)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcClockSyncInit->u32HWFlowControl)); + + u32CR1Value = (pstcClockSyncInit->u32FirstBit | USART_CR1_MS | USART_CR1_SBS); + u32CR2Value = (pstcClockSyncInit->u32ClockSrc | USART_CR2_RST_VALUE); + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + u32CR2Value |= USART_CK_OUTPUT_ENABLE; + } + u32CR3Value = pstcClockSyncInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcClockSyncInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcClockSyncInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcClockSyncInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values. + * @param [out] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMultiProcessorInit value is NULL. + */ +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + pstcMultiProcessorInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcMultiProcessorInit->u32ClockDiv = USART_CLK_DIV1; + pstcMultiProcessorInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcMultiProcessorInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcMultiProcessorInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcMultiProcessorInit->u32StopBit = USART_STOPBIT_1BIT; + pstcMultiProcessorInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcMultiProcessorInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcMultiProcessorInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcMultiProcessorInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMxProcessorInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcMultiProcessorInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcMultiProcessorInit->u32CKOutput)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcMultiProcessorInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcMultiProcessorInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcMultiProcessorInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcMultiProcessorInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcMultiProcessorInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcMultiProcessorInit->u32HWFlowControl)); + + u32CR1Value = (pstcMultiProcessorInit->u32DataWidth | pstcMultiProcessorInit->u32OverSampleBit | \ + pstcMultiProcessorInit->u32FirstBit | pstcMultiProcessorInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcMultiProcessorInit->u32ClockSrc | \ + pstcMultiProcessorInit->u32CKOutput | pstcMultiProcessorInit->u32StopBit); + u32CR3Value = pstcMultiProcessorInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcMultiProcessorInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcMultiProcessorInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcMultiProcessorInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcMultiProcessorInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_uart_init_t to default values. + * @param [out] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL. + */ +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + pstcUartInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcUartInit->u32ClockDiv = USART_CLK_DIV1; + pstcUartInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcUartInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcUartInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcUartInit->u32StopBit = USART_STOPBIT_1BIT; + pstcUartInit->u32Parity = USART_PARITY_NONE; + pstcUartInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcUartInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcUartInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcUartInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcUartInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcUartInit->u32CKOutput)); + DDL_ASSERT(IS_USART_PARITY(pstcUartInit->u32Parity)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcUartInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcUartInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcUartInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcUartInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcUartInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcUartInit->u32HWFlowControl)); + + u32CR1Value = (pstcUartInit->u32Parity | pstcUartInit->u32DataWidth | pstcUartInit->u32FirstBit | \ + pstcUartInit->u32OverSampleBit | pstcUartInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcUartInit->u32ClockSrc | \ + pstcUartInit->u32CKOutput | pstcUartInit->u32StopBit); + u32CR3Value = pstcUartInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcUartInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcUartInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcUartInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcUartInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Initialize UART half duplex function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + i32Ret = USART_UART_Init(USARTx, pstcUartInit, pf32Error); + if (LL_OK == i32Ret) { + /* Set CR3: UART half duplex */ + SET_REG32_BIT(USARTx->CR3, USART_CR3_HDSEL); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_lin_init_t to default values. + * @param [out] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcLinInit is NULL. + */ +int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcLinInit) { + pstcLinInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcLinInit->u32ClockDiv = USART_CLK_DIV1; + pstcLinInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcLinInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcLinInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcLinInit->u32BmcClockDiv = USART_LIN_BMC_CLK_DIV1; + pstcLinInit->u32DetectBreakLen = USART_LIN_DETECT_BREAK_10BIT; + pstcLinInit->u32SendBreakLen = USART_LIN_SEND_BREAK_10BIT; + pstcLinInit->u32SendBreakMode = USART_LIN_SEND_BREAK_MD_SBK; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize LIN function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcLinInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32PRValue; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcLinInit) { + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcLinInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcLinInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcLinInit->u32OverSampleBit)); + + u32CR1Value = (pstcLinInit->u32OverSampleBit | USART_CR1_SBS); + u32CR2Value = (pstcLinInit->u32ClockSrc | pstcLinInit->u32CKOutput | USART_CR2_LINEN | USART_CR2_RST_VALUE); + + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(pstcLinInit->u32DetectBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(pstcLinInit->u32SendBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(pstcLinInit->u32SendBreakMode)); + u32CR2Value |= (pstcLinInit->u32DetectBreakLen | pstcLinInit->u32SendBreakLen | pstcLinInit->u32SendBreakMode); + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, 0UL); + + if (USART_CLK_SRC_INTERNCLK == pstcLinInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv)); + u32PRValue = pstcLinInit->u32ClockDiv; + + DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(pstcLinInit->u32BmcClockDiv)); + u32PRValue |= pstcLinInit->u32BmcClockDiv; + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, u32PRValue); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcLinInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_smartcard_init_t to default values. + * @param [out] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL. + */ +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + pstcSmartCardInit->u32ClockDiv = USART_CLK_DIV1; + pstcSmartCardInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcSmartCardInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcSmartCardInit->u32StopBit = USART_STOPBIT_1BIT; + pstcSmartCardInit->u32FirstBit = USART_FIRST_BIT_LSB; + i32Ret = LL_OK; + } + + return i32Ret; +} +/** + * @brief Initialize smartcard function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcSmartCardInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcSmartCardInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcSmartCardInit->u32FirstBit)); + DDL_ASSERT(IS_USART_STOPBIT(pstcSmartCardInit->u32StopBit)); + + u32CR1Value = (pstcSmartCardInit->u32FirstBit | USART_CR1_PCE | USART_CR1_SBS); + u32CR2Value = (pstcSmartCardInit->u32CKOutput | pstcSmartCardInit->u32StopBit | USART_CR2_RST_VALUE); + u32CR3Value = USART_CR3_SCEN | USART_SC_ETU_CLK372; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcSmartCardInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcSmartCardInit->u32Baudrate, pf32Error); + } + + return i32Ret; +} + +/** + * @brief De-Initialize USART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval None + */ +void USART_DeInit(CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(USARTx->CR1, USART_CR1_RST_VALUE); + WRITE_REG32(USARTx->CR2, USART_CR2_RST_VALUE); + WRITE_REG32(USARTx->CR3, 0UL); + WRITE_REG32(USARTx->PR, 0UL); +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the macros group @ref USART_Function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState) +{ + uint32_t u32BaseFunc; + uint32_t u32LinFunc; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_FUNC(u32Func)); + DDL_ASSERT(IS_USART_LIN_FUNC(USARTx, u32Func)); + DDL_ASSERT(IS_USART_TIMEOUT_FUNC(USARTx, u32Func)); + + u32BaseFunc = (u32Func & 0xFFFFUL); + if (u32BaseFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32BaseFunc) : CLR_REG32_BIT(USARTx->CR1, u32BaseFunc); + } + + u32LinFunc = ((u32Func & USART_LIN_FUNC_MASK) >> USART_LIN_FUNC_OFFSET); + if (u32LinFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR2, u32LinFunc) : CLR_REG32_BIT(USARTx->CR2, u32LinFunc); + } +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + return (0UL == (READ_REG32_BIT(USARTx->SR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the following values: + * @arg USART_FLAG_OVERRUN: Overrun error flag + * @arg USART_FLAG_FRAME_ERR: Framing error flag + * @arg USART_FLAG_PARITY_ERR:Parity error flag + * @arg USART_FLAG_RX_TIMEOUT: Receive timeout flag + * @arg USART_FLAG_LIN_ERR: LIN bus error flag + * @arg USART_FLAG_LIN_WKUP: LIN wakeup signal detection flag + * @arg USART_FLAG_LIN_BREAK: LIN break signal detection flag + * @retval None + * @note Check whether the paramter u32Flag value is valid by @ref USART_Flag. + */ +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + if ((u32Flag & USART_FLAG_ERR_MASK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, (u32Flag & USART_FLAG_ERR_MASK) << USART_CR1_CPE_POS); + } + + /* Timeout flag */ + if ((u32Flag & USART_FLAG_RX_TIMEOUT) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CRTOF); + } + + /* LIN flag */ + if ((u32Flag & USART_FLAG_LIN_ERR) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CBE); + } + + if ((u32Flag & USART_FLAG_LIN_WKUP) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CWKUP); + } + + if ((u32Flag & USART_FLAG_LIN_BREAK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CLBD); + } +} + +/** + * @brief Set USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Parity USART parity + * This parameter can be one of the macros group @ref USART_Parity_Control + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + * @retval None + */ +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_PARITY(u32Parity)); + + MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity); +} + +/** + * @brief Set USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32FirstBit USART bit direction + * This parameter can be one of the macros group @ref USART_First_Bit + * @arg USART_FIRST_BIT_MSB: MSB(Most Significant Bit) + * @arg USART_FIRST_BIT_LSB: LSB(Least Significant Bit) + * @retval None + */ +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FIRST_BIT(u32FirstBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32FirstBit); +} + +/** + * @brief Set USART stop bit. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32StopBit USART stop bits + * This parameter can be one of the macros group @ref USART_Stop_Bit + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bit + * @retval None + */ +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOPBIT(u32StopBit)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBit); +} + +/** + * @brief Set USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32DataWidth USART data width + * This parameter can be one of the macros group @ref USART_Data_Width_Bit + * @arg USART_DATA_WIDTH_8BIT: 8 bits word width + * @arg USART_DATA_WIDTH_9BIT: 9 bits word width + * @retval None + */ +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth); +} + +/** + * @brief Set USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32OverSampleBit USART over sample bit + * This parameter can be one of the macros group @ref USART_Over_Sample_Bit + * @arg USART_OVER_SAMPLE_8BIT: Oversampling by 8 bit + * @arg USART_OVER_SAMPLE_16BIT: Oversampling by 16 bit + * @retval None + */ +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(u32OverSampleBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OverSampleBit); +} + +/** + * @brief Set USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Polarity USART start bit detect polarity + * This parameter can be one of the macros group @ref USART_Start_Bit_Polarity + * @arg USART_START_BIT_LOW: Detect RX pin low level + * @arg USART_START_BIT_FALLING: Detect RX pin falling edge + * @retval None + */ +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(u32Polarity)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity); +} + +/** + * @brief Set USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Type USART transmission content type + * This parameter can be one of the macros group @ref USART_Transmission_Type + * @arg USART_TRANS_ID: USART transmission content type is processor ID + * @arg USART_TRANS_DATA: USART transmission content type is frame data + * @retval None + */ +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint32_t u32Type) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_TRANS_TYPE(u32Type)); + + MODIFY_REG32(USARTx->DR, USART_DR_MPID, u32Type); +} + +/** + * @brief Set USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_Clock_Division + * @arg USART_CLK_DIV1: CLK + * @arg USART_CLK_DIV4: CLK/4 + * @arg USART_CLK_DIV16: CLK/16 + * @arg USART_CLK_DIV64: CLK/64 + * @retval None + * @note The clock division function is valid only when clock source is internal clock. + */ +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_PSC, u32ClockDiv); +} + +/** + * @brief Get USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_DIV1: CLK + * - USART_CLK_DIV4: CLK/4 + * - USART_CLK_DIV16: CLK/16 + * - USART_CLK_DIV64: CLK/64 + * @note The clock division function is valid only when clock source is internal clock. + */ +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_PSC); +} + +/** + * @brief Set USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockSrc USART clock source + * This parameter can be one of the macros group @ref USART_Clock_Source + * @arg USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * @arg USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + * @retval None + */ +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(u32ClockSrc)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC_1, u32ClockSrc); +} + +/** + * @brief Get USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * - USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + */ +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC_1); +} + +/** + * @brief Enable or disable USART noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } +} + +/** + * @brief Enable or disable USART silence. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } +} + +/** + * @brief Set UART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32HWFlowControl USART hardware flow control CTS/RTS selection + * This parameter can be one of the macros group @ref USART_Hardware_Flow_Control. + * @retval None + */ +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(u32HWFlowControl)); + + MODIFY_REG32(USARTx->CR3, (USART_CR3_CTSE | USART_CR3_RTSE), u32HWFlowControl); +} + +/** + * @brief USART receive data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Receive data + */ +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG16(*USART_RXD(USARTx)); +} + +/** + * @brief USART send data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Data Transmit data + * @retval None + */ +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data) +{ + __IO uint16_t *TXD = USART_TXD(USARTx); + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16Data)); + + WRITE_REG16(*TXD, u16Data); +} + +/** + * @brief USART send processor ID. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + ** @param [in] u16ID Processor ID + * @retval None + */ +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID) +{ + __IO uint16_t *TXD = USART_TXD(USARTx); + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16ID)); + + WRITE_REG16(*TXD, (USART_DR_MPID | u16ID)); +} + +/** + * @brief Set USART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Baudrate UART baudrate + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + * @note The function uses fraction division to ensure baudrate accuracy if USART unit supports baudrate fraction division. + */ +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error) +{ + uint32_t u32Mode; + uint32_t u32UsartClock; + uint32_t u32Integer = 0UL; + uint32_t u32Fraction = 0xFFFFUL; + int32_t i32Ret; + + DDL_ASSERT(u32Baudrate > 0UL); + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Get USART clock frequency */ + u32UsartClock = USART_GetUsartClockFreq(USARTx); + + /* Calculate baudrate for BRR */ + u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS); + if (0UL == u32Mode) { + u32Mode = READ_REG32_BIT(USARTx->CR3, USART_CR_SCEN); + if (0UL == u32Mode) { + i32Ret = UART_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } else { + /* Smartcard function */ + i32Ret = SmartCard_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } + } else { + i32Ret = ClockSync_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } + + if (LL_OK == i32Ret) { + MODIFY_REG32(USARTx->BRR, USART_BRR_DIV_INTEGER, (u32Integer << USART_BRR_DIV_INTEGER_POS)); + + if (u32Fraction <= USART_BRR_DIV_FRACTION_MASK) { + SET_REG32_BIT(USARTx->CR1, USART_CR_FBME); + MODIFY_REG32(USARTx->BRR, USART_BRR_DIV_FRACTION_MASK, u32Fraction); + } + } + + return i32Ret; +} + +/** + * @brief Set USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32EtuClock USART Smartcard ETU Clock. + * This parameter can be one of the macros group @ref USART_Smartcard_ETU_Clock + * @arg USART_SC_ETU_CLK32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK372: 1 etu = 372/f + * @retval None + */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock) +{ + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClock)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClock); +} + +/** + * @brief Enable/disable stop mode noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE); + } else { + CLR_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE); + } +} + +/** + * @brief Set stop mode noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Level The noise filter width level value + * This parameter can be one of the macros group @ref USART_Stop_Mode_Noise_Filter_Width_Level + * @arg USART_STOP_MD_FILTER_LVL1: Filter width level 1 + * @arg USART_STOP_MD_FILTER_LVL2: Filter width level 2 + * @arg USART_STOP_MD_FILTER_LVL3: Filter width level 3 + * @arg USART_STOP_MD_FILTER_LVL4: Filter width level 4 + * @retval None + */ +void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level) +{ + DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOP_MD_FILTER(u32Level)); + + MODIFY_REG32(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USASRT1_NFS, u32Level); +} + +/** + * @brief Enable or disable USART loopback function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } else { + CLR_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } +} + +/** + * @brief Set USART LIN counter clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART USART LIN counter clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_BMC_Clock_Division + * @arg USART_LIN_BMC_CLK_DIV1: CLK + * @arg USART_LIN_BMC_CLK_DIV2: CLK/2 + * @arg USART_LIN_BMC_CLK_DIV4: CLK/4 + * @arg USART_LIN_BMC_CLK_DIV8: CLK/8 + * @retval None + * @note The clock division function is valid when clock source is internal clock. + */ +void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_LBMPSC, u32ClockDiv); +} + +/** + * @brief LIN Request break sending + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval None + */ +void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + SET_REG32_BIT(USARTx->CR2, USART_CR2_SBK); +} + +/** + * @brief Get request break sending status + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return (0UL == READ_REG32_BIT(USARTx->CR2, USART_CR2_SBK)) ? RESET : SET; +} + +/** + * @brief Set send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Mode USART send break mode + * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Mode + * @arg USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value + * @arg USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value + * @retval None + */ +void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(u32Mode)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKM, u32Mode); +} + +/** + * @brief Get send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value + * - USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value + */ +uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBKM); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval LIN baudrate measure count value + */ +uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval LIN baudrate measure count value + */ +uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BmClk; + uint32_t u32LBMC; + + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + u32BmClk = USART_GetLinBmcClockFreq(USARTx); + u32LBMC = READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); + + return (u32LBMC > 0UL) ? (u32BmClk / u32LBMC) : 0UL; +} + +/** + * @brief Set USART LIN break detection length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_Detect_Break_Length + * @arg USART_LIN_DETECT_BREAK_10BIT: 10-bit break detection + * @arg USART_LIN_DETECT_BREAK_11BIT: 11-bit break detection + * @retval None + */ +void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_LBDL, u32Len); +} + +/** + * @brief Set USART LIN break sending length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Length + * @arg USART_LIN_SEND_BREAK_10BIT: Send break 10-bit + * @arg USART_LIN_SEND_BREAK_11BIT: Send break 11-bit + * @arg USART_LIN_SEND_BREAK_13BIT: Send break 13-bit + * @arg USART_LIN_SEND_BREAK_14BIT: Send break 14-bit + * @retval None + */ +void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKL, u32Len); +} + +/** + * @brief UART transmit data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data transmitted buffer + * @param [in] u32Len Amount of frame to be sent. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or pvBuf is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint32_t u32DataWidth; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + if ((USART_DATA_WIDTH_8BIT == u32DataWidth) || (USART_DATA_WIDTH_9BIT == u32DataWidth)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (u32DataWidth == USART_DATA_WIDTH_8BIT) { + USART_WriteData(USARTx, ((const uint8_t *)pvBuf)[i]); + } else { + USART_WriteData(USARTx, ((const uint16_t *)pvBuf)[i]); + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + } + + return i32Ret; +} + +/** + * @brief UART receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data received buffer + * @param [in] u32Len Amount of frame to be received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer pvBuf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32Count; + uint32_t u32DataWidth; + uint16_t u16ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + for (u32Count = 0UL; u32Count < u32Len; u32Count++) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u16ReceiveData = USART_ReadData(USARTx); + if (USART_DATA_WIDTH_8BIT == u32DataWidth) { + ((uint8_t *)pvBuf)[u32Count] = (uint8_t)(u16ReceiveData & 0xFFU); + } else { + ((uint16_t *)pvBuf)[u32Count] = (uint16_t)(u16ReceiveData & 0x1FFU); + } + } else { + break; + } + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8Buf The pointer to data transmitted buffer + * @param [in] u32Len Amount of data to be transmitted. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + USART_WriteData(USARTx, au8Buf[i]); + if (READ_REG32_BIT(USARTx->CR1, USART_RX) != 0UL) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + (void)USART_ReadData(USARTx); + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] au8Buf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + en_functional_state_t enTX; + en_functional_state_t enMasterMode; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + i32Ret = LL_OK; + enTX = (READ_REG32_BIT(USARTx->CR1, USART_TX) == 0UL) ? DISABLE : ENABLE; + enMasterMode = (USART_CLK_SRC_EXTCLK == READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC)) ? DISABLE : ENABLE; + + for (i = 0UL; i < u32Len; i++) { + if ((ENABLE == enMasterMode) || (ENABLE == enTX)) { + USART_WriteData(USARTx, 0xFFU); + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + au8Buf[i] = (uint8_t)USART_ReadData(USARTx); + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8TxBuf The pointer to data transmitted buffer + * @param [out] au8RxBuf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint8_t u8ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if (u32Len > 0UL) { + for (i = 0UL; i < u32Len; i++) { + if (NULL != au8TxBuf) { + USART_WriteData(USARTx, au8TxBuf[i]); + } else { + USART_WriteData(USARTx, 0xFFU); + } + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u8ReceiveData = (uint8_t)USART_ReadData(USARTx); + if (NULL != au8RxBuf) { + au8RxBuf[i] = u8ReceiveData; + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c new file mode 100644 index 0000000000..c658779448 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c @@ -0,0 +1,1362 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.c + * @brief USB core driver + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usb.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USB USB + * @brief USB Driver Library + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USB_Global_Functions USB Global Functions + * @{ + */ + +/** + * @brief core software reset + * @param [in] USBx usb instance + * @retval None + */ +void usb_coresoftrst(LL_USB_TypeDef *USBx) +{ + __IO uint8_t u8Status = USB_OK;; + __IO uint32_t u32grstctl = 0UL; + __IO uint32_t u32Count = 0UL; + + /* Wait for AHB master to be idle. */ + do { + usb_udelay(1UL); + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (++u32Count > 100000UL) { + u8Status = USB_ERROR; + } + } while (0UL == (u32grstctl & USBFS_GRSTCTL_AHBIDL)); + + if (USB_OK == u8Status) { + /* Write the Core Soft Reset bit to reset the USB core */ + u32Count = 0UL; + u32grstctl |= USBFS_GRSTCTL_CSRST; + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* Wait for the reset finishing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Count > 100000UL) { + break; + } + u32Count++; + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_CSRST)); + /* Wait for at least 3 PHY clocks after the core resets */ + usb_udelay(3UL); + } +} + +/** + * @brief Writes a packet whose byte number is len into the Tx FIFO associated + * with the EP + * @param [in] USBx usb instance + * @param [in] src source pointer used to hold the transmited data + * @param [in] ch_ep_num end point index + * @param [in] len length in bytes + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn) +{ + __IO uint32_t u32pAddr; + __IO uint32_t *fifo; + uint32_t u32Count32b; + uint32_t u32Tmp; + if (u8DmaEn == 0U) { + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + fifo = USBx->DFIFO[ch_ep_num]; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + WRITE_REG32(*fifo, *((uint32_t *)src)); + u32pAddr = (uint32_t)src; + src = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } + } +} + +/** + * @brief Reads a packet whose byte number is len from the Rx FIFO + * @param [in] USBx usb instance + * @param [in] dest destination pointer that point to the received data + * @param [in] len number of bytes + * @retval None + */ +void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t u32Tmp; + __IO uint32_t u32Count32b; + __IO uint32_t u32pAddr; + + __IO uint32_t *fifo = USBx->DFIFO[0]; + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + u32pAddr = 0UL; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + *(uint32_t *)dest = READ_REG32(*fifo); + u32pAddr = (uint32_t)dest; + dest = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } +} + +/** + * @brief Initialize the addresses of the core registers. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_setregaddr(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + uint32_t u32Tmp = 0UL; + uint32_t u32baseAddr; + + basic_cfgs->dmaen = 0U; + /* initialize device cfg following its address */ + basic_cfgs->host_chnum = USB_MAX_CH_NUM; + basic_cfgs->dev_epnum = USB_MAX_EP_NUM; + basic_cfgs->core_type = 0U; /* FS */ + basic_cfgs->phy_type = 0U; +#ifdef USB_FS_MODE + u32baseAddr = CM_USBFS_BASE; + basic_cfgs->core_type = 0U; /* FS */ +#endif /* USB_FS_MODE */ + +#ifdef USB_HS_MODE + u32baseAddr = CM_USBHS_BASE; + basic_cfgs->core_type = 1U; /* HS */ +#ifdef USB_HS_EXTERNAL_PHY + basic_cfgs->phy_type = 1U; +#endif +#endif /* USB_HS_MODE */ + + USBx->GREGS = (USB_CORE_GREGS *)(u32baseAddr + 0UL); + USBx->DREGS = (USB_CORE_DREGS *)(u32baseAddr + 0x800UL); + + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->INEP_REGS[u32Tmp] = (USB_CORE_INEPREGS *)(u32baseAddr + 0x900UL + (u32Tmp * 0x20UL)); + USBx->OUTEP_REGS[u32Tmp] = (USB_CORE_OUTEPREGS *)(u32baseAddr + 0xb00UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->DFIFO[u32Tmp] = (uint32_t *)(u32baseAddr + 0x1000UL + (u32Tmp * 0x1000UL)); + u32Tmp++; + } + USBx->GCCTL = (uint32_t *)(u32baseAddr + 0xe00UL); +#ifdef USE_HOST_MODE /* if the application mode is host */ + USBx->HREGS = (USB_CORE_HREGS *)(u32baseAddr + 0x400UL); + USBx->HPRT = (uint32_t *)(u32baseAddr + 0x440UL); + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->host_chnum) { + USBx->HC_REGS[u32Tmp] = (USB_CORE_HC_REGS *)(u32baseAddr + 0x500UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } +#endif /* USE_HOST_MODE */ +} + +/** + * @brief Initializes the USB controller registers and prepares the core + * device mode or host mode operation. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + + /* Select PHY for USB core*/ + usb_PhySelect(USBx, basic_cfgs->phy_type); + if ((basic_cfgs->phy_type == 0U) && (basic_cfgs->core_type == 1U)) { + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; + } + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + usb_mdelay(20UL); + if (basic_cfgs->dmaen == 1U) { + /* burst length/type(HBstLen) 64-words x32-bit, core operates in a DMA mode*/ + usb_BurstLenConfig(USBx, 5U); + usb_DmaCmd(USBx, 1U); + } +} + +/** + * @brief Flush a Tx FIFO whose index is num + * @param [in] USBx usb instance + * @param [in] num txFIFO index + * @retval None + */ +void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_TXFFLSH | ((num & 0x1FUL) << USBFS_GRSTCTL_TXFNUM_POS); + /* set the TxFIFO Flush bit, set TxFIFO Number */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* wait for the finishing of txFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_TXFFLSH)); + /* Wait for at least 3 PHY clocks after the txfifo has been flushed */ + usb_udelay(3UL); +} + +/** + * @brief Flush the whole rxFIFO + * @param [in] USBx usb instance + * @retval None + */ +void usb_rxfifoflush(LL_USB_TypeDef *USBx) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_RXFFLSH; /* set the RxFIFO Flush bit */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + /* wait for the finishing of rxFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_RXFFLSH)); + /* Wait for at least 3 PHY clocks after the rxfifo has been flushed */ + usb_udelay(3UL); +} + +/** + * @brief set the core to be host mode or device mode through the second + * input parameter. + * @param [in] USBx usb instance + * @param [in] mode mode of HOST_MODE or DEVICE_MODE that the core would be + * @retval None + */ +void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode) +{ + if (mode == HOST_MODE) { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FHMOD); + } else { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FDMOD); + } + /* wate for the change to take effect */ + usb_mdelay(50UL); +} + +#ifdef USE_DEVICE_MODE + +/** + * @brief initializes the initial status of all endpoints of the device to be + * disable. + * @param [in] USBx usb instance + * @param [in] u8EpNum EP number + * @retval None + */ +void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum) +{ + uint8_t u8Tmp = 0U; + + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPENA)) { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPDIS | USBFS_DIEPCTL_SNAK); + } else { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, 0UL); + } + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPTSIZ, 0UL); + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPINT, 0xFFUL); + u8Tmp++; + } + + u8Tmp = 0U; + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPENA)) { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPDIS | USBFS_DOEPCTL_SNAK); + } else { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, 0UL); + } + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPTSIZ, 0UL); + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPINT, 0xFFUL); + u8Tmp++; + } +} + +#ifdef USB_FS_MODE +static void usb_DevFSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP6 */ + u32StardAddr += TX5_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[5], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX6_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP7 */ + u32StardAddr += TX6_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[6], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX7_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP8 */ + u32StardAddr += TX7_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[7], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX8_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP9 */ + u32StardAddr += TX8_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[8], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX9_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP10 */ + u32StardAddr += TX9_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[9], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX10_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP11 */ + u32StardAddr += TX10_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[10], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX11_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP12 */ + u32StardAddr += TX11_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[11], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX12_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP13 */ + u32StardAddr += TX12_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[12], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX13_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP14 */ + u32StardAddr += TX13_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[13], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX14_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP15 */ + u32StardAddr += TX14_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[14], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX15_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +#ifdef USB_HS_MODE +static void usb_DevHSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP6 */ + u32StardAddr += TX5_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[5], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX6_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP7 */ + u32StardAddr += TX6_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[6], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX7_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP8 */ + u32StardAddr += TX7_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[7], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX8_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP9 */ + u32StardAddr += TX8_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[8], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX9_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP10 */ + u32StardAddr += TX9_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[9], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX10_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP11 */ + u32StardAddr += TX10_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[10], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX11_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP12 */ + u32StardAddr += TX11_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[11], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX12_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP13 */ + u32StardAddr += TX12_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[12], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX13_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP14 */ + u32StardAddr += TX13_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[13], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX14_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP15 */ + u32StardAddr += TX14_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[14], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX15_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +/** + * @brief initializes the USB controller, include the size of txFIFO, rxFIFO + * status of endpoints, interrupt register etc. Details are shown as + * follows. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + usb_FrameIntervalConfig(USBx, USB_FRAME_INTERVAL_80); + usb_DevPhySelect(USBx, basic_cfgs->phy_type); + + if (basic_cfgs->core_type == 0U) { +#ifdef USB_FS_MODE + usb_DevFSFifoConfig(USBx); +#endif + } else { +#ifdef USB_HS_MODE + usb_DevHSFifoConfig(USBx); +#endif + } + + usb_clrandmskepint(USBx); + usb_devepdis(USBx, basic_cfgs->dev_epnum); + usb_coreconn(USBx); + usb_devinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief Enable the interrupt setting when in device mode. + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gintmskTmp = 0UL; + + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + /* Enable the normal interrupt setting */ + usb_normalinten(USBx); + if (u8DmaEn == 0U) { + u32gintmskTmp |= USBFS_GINTMSK_RXFNEM; + } + /* Enable interrupts bits corresponding to the Device mode */ + u32gintmskTmp |= (USBFS_GINTMSK_USBSUSPM | USBFS_GINTMSK_USBRSTM | USBFS_GINTMSK_ENUMDNEM + | USBFS_GINTMSK_IEPIM | USBFS_GINTMSK_OEPIM | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IISOIXFRM | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); +#ifdef VBUS_SENSING_ENABLED + u32gintmskTmp |= USBFS_GINTMSK_VBUSVIM; +#endif + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gintmskTmp); +} + +/** + * @brief get the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval current status of the endpoint + */ +uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + __IO uint32_t u32Status = 0UL; + uint32_t u32dxepctl; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + u32Status = USB_EP_TX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DIEPCTL_NAKSTS)) { + u32Status = USB_EP_TX_NAK; + } else { + u32Status = USB_EP_TX_VALID; + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + u32Status = USB_EP_RX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DOEPCTL_NAKSTS)) { + u32Status = USB_EP_RX_NAK; + } else { + u32Status = USB_EP_RX_VALID; + } + } + + return u32Status; +} + +/** + * @brief set the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] Status new Status that the endpoint would be + * @retval None + */ +void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status) +{ + uint32_t u32dxepctl; + uint8_t u8RetFlag = 0U; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + switch (Status) { + case USB_EP_TX_STALL: + usb_setepstall(USBx, ep); + u8RetFlag = 1U; + break; + case USB_EP_TX_NAK: + u32dxepctl |= USBFS_DIEPCTL_SNAK; + break; + case USB_EP_TX_VALID: + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_USBAEP | USBFS_DIEPCTL_EPENA); + break; + case USB_EP_TX_DIS: + u32dxepctl &= (~USBFS_DIEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32dxepctl); + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + + switch (Status) { + case USB_EP_RX_STALL: + u32dxepctl |= USBFS_DOEPCTL_STALL; + break; + case USB_EP_RX_NAK: + u32dxepctl |= USBFS_DOEPCTL_SNAK; + break; + case USB_EP_RX_VALID: + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_USBAEP | USBFS_DOEPCTL_EPENA); + break; + case USB_EP_RX_DIS: + u32dxepctl &= (~USBFS_DOEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32dxepctl); + } + } +} + +/** + * @brief enable the EP0 to be actiove + * @param [in] USBx usb instance + * @retval None + */ +void usb_ep0activate(LL_USB_TypeDef *USBx) +{ + uint32_t u32EnumSpeed; + uint32_t u32DiepctlTmp; + + u32EnumSpeed = READ_REG32(USBx->DREGS->DSTS) & USBFS_DSTS_ENUMSPD; + u32DiepctlTmp = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Set the MPS of the DIEPCTL0 based on the enumeration speed */ + if ((DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_48MHZ == u32EnumSpeed)) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + } else if (DSTS_ENUMSPD_LS_PHY_6MHZ == u32EnumSpeed) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + u32DiepctlTmp |= (3UL << USBFS_DIEPCTL_MPSIZ_POS); + } else { + ; + } + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32DiepctlTmp); + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_CGINAK); +} + +/** + * @brief enable an EP to be active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Addr; + uint32_t u32dxepctl; + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + u32Addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + u32Daintmsk = 1UL << ep->epidx; + } else { + u32Addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + u32dxepctl = READ_REG32(*(__IO uint32_t *)u32Addr); + if (0UL == (u32dxepctl & USBFS_DIEPCTL_USBAEP)) { + u32dxepctl = ((ep->maxpacket << USBFS_DIEPCTL_MPSIZ_POS) + | (((uint32_t)ep->trans_type) << USBFS_DIEPCTL_EPTYP_POS) + | (((uint32_t)ep->tx_fifo_num) << USBFS_DIEPCTL_TXFNUM_POS) + | USBFS_DIEPCTL_SD0PID_SEVNFRM + | USBFS_DIEPCTL_USBAEP); + + WRITE_REG32(*(__IO uint32_t *)u32Addr, u32dxepctl); + } + SET_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief enable an EP to be deactive state if it is active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + CLR_REG32_BIT(USBx->INEP_REGS[ep->epidx]->DIEPCTL, USBFS_DIEPCTL_USBAEP); + u32Daintmsk = 1UL << ep->epidx; + } else { + CLR_REG32_BIT(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, USBFS_DOEPCTL_USBAEP); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + CLR_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief Setup the data into the EP and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0UL) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + u32Xfersize = ep->xfer_len; + u32Pktcnt = (ep->xfer_len - 1U + ep->maxpacket) / ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + if (ep->trans_type == EP_TYPE_ISOC) { + u32DeptsizTmp |= (1UL << USBFS_DIEPTSIZ_MCNT_POS); + } + } + MODIFY_REG32(USBx->INEP_REGS[ep->epidx]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } else { + if (ep->trans_type != EP_TYPE_ISOC) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (((READ_REG32(USBx->DREGS->DSTS) >> USBFS_DSTS_FNSOF_POS) & 0x1U) == 0U) { + u32depctl |= USBFS_DIEPCTL_SODDFRM; + } else { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + + if (ep->trans_type == EP_TYPE_ISOC) { + usb_wrpkt(USBx, ep->xfer_buff, ep->epidx, (uint16_t)ep->xfer_len, u8DmaEn); + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0U) { + u32Xfersize = ep->maxpacket; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + } else { + u32Pktcnt = (ep->xfer_len + (ep->maxpacket - 1U)) / ep->maxpacket; + u32Xfersize = u32Pktcnt * ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + ep->xfer_len = u32Xfersize; + } + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (0U != ep->datax_pid) { + u32depctl |= USBFS_DOEPCTL_SD1PID; + } else { + u32depctl |= USBFS_DOEPCTL_SD0PID; + } + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Setup the data into the EP0 and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + if (ep->xfer_len > ep->maxpacket) { + ep->xfer_len = ep->maxpacket; + u32Xfersize = ep->maxpacket; + } else { + u32Xfersize = ep->xfer_len; + } + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } + MODIFY_REG32(USBx->INEP_REGS[0]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32depctl); + + if (u8DmaEn == 0U) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + } else { + ep->xfer_len = LL_MIN(ep->rem_data_len, ep->maxpacket); + u32Xfersize = ep->xfer_len; + u32Pktcnt = 1UL; + } + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Set the EP to be stall status + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32depctl; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + if (0UL != (u32depctl & USBFS_DIEPCTL_EPENA)) { + u32depctl |= USBFS_DIEPCTL_EPDIS; + } + u32depctl |= USBFS_DIEPCTL_STALL; + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + u32depctl |= USBFS_DOEPCTL_STALL; + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief clear the stall status of a EP + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t tmp_depctl_addr; + uint32_t u32depctl; + + if (ep->ep_dir == 1U) { + tmp_depctl_addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + } else { + tmp_depctl_addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + } + u32depctl = READ_REG32(tmp_depctl_addr); + + u32depctl &= (~USBFS_DIEPCTL_STALL); + if ((ep->trans_type == EP_TYPE_INTR) || (ep->trans_type == EP_TYPE_BULK)) { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + + WRITE_REG32(*(__IO uint32_t *)tmp_depctl_addr, u32depctl); +} + +/** + * @brief configure the EPO to receive data packets + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf) +{ + uint32_t u32deptsize; + uint32_t u32doepctl; + + u32deptsize = (3UL << USBFS_DOEPTSIZ0_STUPCNT_POS) + | (1UL << USBFS_DOEPTSIZ0_PKTCNT_POS) + | (64UL << USBFS_DOEPTSIZ0_XFRSIZ_POS); + + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPTSIZ, u32deptsize); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPDMA, (uint32_t)&u8RevBuf); + u32doepctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + u32doepctl |= (USBFS_DOEPCTL_EPENA | USBFS_DOEPCTL_USBAEP); + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPCTL, u32doepctl); + } +} + +/** + * @brief enable remote wakeup active + * @param [in] USBx usb instance + * @retval None + */ +void usb_remotewakeupen(LL_USB_TypeDef *USBx) +{ + uint32_t u32dsts; + + u32dsts = READ_REG32(USBx->DREGS->DSTS); + if (0UL != (u32dsts & USBFS_DSTS_SUSPSTS)) { + /* un-gate USB Core clock */ + CLR_REG32_BIT(*USBx->GCCTL, USBFS_GCCTL_GATEHCLK | USBFS_GCCTL_STPPCLK); + } + + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); + usb_mdelay(5UL); + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); +} + +/** + * @brief control the device to connect or disconnect + * @param [in] USBx usb instance + * @param [in] link 0(conn) or 1(disconn) + * @retval None + */ +void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link) +{ + if (0U == link) { + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } else { + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } + usb_mdelay(3UL); +} +#endif + +#ifdef USE_HOST_MODE +/** + * @brief Initializes the USB controller when it is host mode + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + __IO uint8_t u8Tmp = 0U; + WRITE_REG32(*USBx->GCCTL, 0UL); /* reset the register-GCCTL */ +#ifdef USB_HS_EXTERNAL_PHY + usb_fslspclkselset(USBx, HCFG_30_60_MHZ); /* PHY clock is running at 6MHz */ +#else + usb_fslspclkselset(USBx, HCFG_6_MHZ); /* PHY clock is running at 6MHz */ +#endif + usb_hprtrst(USBx); /* reset the port */ + usb_enumspeed(USBx); /* FS or LS bases on the maximum speed supported by the connected device */ + usb_sethostfifo(USBx); + /* Flush all the txFIFO and the whole rxFIFO */ + usb_txfifoflush(USBx, 0x10UL); + usb_rxfifoflush(USBx); + /* Clear all HC Interrupt bits that are pending */ + while (u8Tmp < basic_cfgs->host_chnum) { + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINTMSK, 0UL); + u8Tmp++; + } + usb_hostinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief set the vbus if state is 1 or reset the vbus if state is 0. + * @param [in] USBx usb instance + * @param [in] u8State the vbus state it would be. + * @retval None + */ +void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State) +{ + uint32_t u32hprt; + + /* enable or disable the external charge pump */ + usb_bsp_drivevbus(USBx, u8State); + u32hprt = usb_rdhprt(USBx); + if ((0UL == (u32hprt & USBFS_HPRT_PWPR)) && (1U == u8State)) { + u32hprt |= USBFS_HPRT_PWPR; + WRITE_REG32(*USBx->HPRT, u32hprt); + } + if ((0UL != (u32hprt & USBFS_HPRT_PWPR)) && (0U == u8State)) { + u32hprt &= (~USBFS_HPRT_PWPR); + WRITE_REG32(*USBx->HPRT, u32hprt); + } +} + +/** + * @brief Enables the related interrupts when the core is host mode + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gIntmsk = 0UL; + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + /* Clear the pending interrupt bits */ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xFFFFFFFFUL); + + /* Enable the normal interrupt bits */ + usb_normalinten(USBx); + + if (u8DmaEn == 0U) { + u32gIntmsk |= USBFS_GINTMSK_RXFNEM; + } + u32gIntmsk |= (USBFS_GINTMSK_HPRTIM + | USBFS_GINTMSK_HCIM + | USBFS_GINTMSK_DISCIM + | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gIntmsk); +} + +/** + * @brief Reset the port, the 1'b0 state must last at lease 10ms. + * @param [in] USBx usb instance + * @retval None + */ +void usb_hprtrst(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + usb_mdelay(10UL); + u32hprt &= ~USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + usb_mdelay(20UL); + + //SET_REG32_BIT(*USBx->HPRT, USBFS_HPRT_PRST); + //usb_mdelay(10UL); + //CLR_REG32_BIT(*USBx->HPRT, USBFS_HPRT_PRST); + //usb_mdelay(20UL); +} + +/** + * @brief Prepares transferring packets on a host channel + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in byte + */ +uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcintmsk = 0UL; + uint32_t u32hcchar = 0UL; + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINT, 0xFFFFFFFFUL); + if (u8DmaEn == 1U) { + u32hcintmsk |= USBFS_HCINTMSK_AHBERRM; + } + switch (pCh->ep_type) { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_NAKM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } else { + u32hcintmsk |= USBHS_HCINT_NYET; + if (0U != pCh->do_ping) { + u32hcintmsk |= USBFS_HCINTMSK_ACKM; + } + } + break; + case EP_TYPE_INTR: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_NAKM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_FRMORM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } + break; + case EP_TYPE_ISOC: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_FRMORM + | USBFS_HCINTMSK_ACKM); + + if (0U != pCh->is_epin) { + u32hcintmsk |= (USBFS_HCINTMSK_TXERRM | USBFS_HCINTMSK_BBERRM); + } + break; + default: + break; + } + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINTMSK, u32hcintmsk); + SET_REG32_BIT(USBx->HREGS->HAINTMSK, 1UL << hc_num); + + /* enable the host channel interrupts */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_HCIM); + + /* modify HCCHAR */ + u32hcchar |= (((uint32_t)pCh->dev_addr) << USBFS_HCCHAR_DAD_POS); + u32hcchar |= (((uint32_t)pCh->ep_idx) << USBFS_HCCHAR_EPNUM_POS); + u32hcchar |= (((uint32_t)pCh->is_epin) << USBFS_HCCHAR_EPDIR_POS); + u32hcchar |= (((uint32_t)pCh->ep_type) << USBFS_HCCHAR_EPTYP_POS); + u32hcchar |= (((uint32_t)pCh->max_packet) << USBFS_HCCHAR_MPSIZ_POS); + if (PRTSPD_LOW_SPEED == pCh->ch_speed) { + u32hcchar |= USBFS_HCCHAR_LSDEV; + } else { + u32hcchar &= ~USBFS_HCCHAR_LSDEV; + } + + if (pCh->ep_type == EP_TYPE_INTR) { + u32hcchar |= USBFS_HCCHAR_ODDFRM; + } + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + return USB_OK; +} + +/** + * @brief Start transfer on the channel whose index is hc_num. + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in 8 bits + */ +uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcchar; + uint32_t u32hctsiz = 0UL; + uint32_t u32hnptxsts; + uint32_t u32hptxsts; + uint16_t u16LenWords; + uint16_t u16NumPacket; + uint16_t u16MaxHcPktCount = 256U; + + /* Compute the expected number of packets associated to the transfer */ + if (pCh->xfer_len > 0U) { + u16NumPacket = (uint16_t)((pCh->xfer_len + + (uint32_t)pCh->max_packet - 1UL) / (uint32_t)pCh->max_packet); + + if (u16NumPacket > u16MaxHcPktCount) { + u16NumPacket = u16MaxHcPktCount; + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + } else { + u16NumPacket = 1U; + } + if (0U != pCh->is_epin) { + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + + u32hctsiz |= (((uint32_t)pCh->xfer_len) << USBFS_HCTSIZ_XFRSIZ_POS); + u32hctsiz |= (((uint32_t)u16NumPacket) << USBFS_HCTSIZ_PKTCNT_POS); + u32hctsiz |= (((uint32_t)pCh->pid_type) << USBFS_HCTSIZ_DPID_POS); + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, u32hctsiz); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->HC_REGS[hc_num]->HCDMA, pCh->xfer_buff); + } + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar |= (usb_ifevenframe(USBx) << USBFS_HCCHAR_ODDFRM_POS); + + /* enable this host channel whose number is hc_num */ + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + + if (u8DmaEn == 0U) { + if ((pCh->is_epin == 0U) && (pCh->xfer_len > 0U)) { + switch (pCh->ep_type) { + /* Non-periodic transmit */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hnptxsts = READ_REG32(USBx->GREGS->HNPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the amount of free space available in the non-periodic txFIFO is enough */ + if (u16LenWords > ((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) >> USBFS_HNPTXSTS_NPTXFSAV_POS)) { + /* enable interrrupt of nptxfempty of GINTMSK*/ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_NPTXFEM); + } + break; + /* Periodic trnsmit */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + u32hptxsts = READ_REG32(USBx->HREGS->HPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the space of periodic TxFIFO is enough */ + if (u16LenWords > ((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) >> USBFS_HPTXSTS_PTXFSAVL_POS)) { + /* enable interrrupt of ptxfempty of GINTMSK */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM); + } + break; + default: + break; + } + + usb_wrpkt(USBx, pCh->xfer_buff, hc_num, (uint16_t)pCh->xfer_len, u8DmaEn); + } + } + return USB_OK; +} + +/** + * @brief Stop the host and flush all the txFIFOs and the whole rxFIFO. + * @param [in] USBx usb instance + * @param [in] u8ChNum Host channel number + * @retval None + */ +void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum) +{ + __IO uint32_t u32Tmp = 0UL; + + WRITE_REG32(USBx->HREGS->HAINTMSK, 0UL); + WRITE_REG32(USBx->HREGS->HAINT, 0xFFFFFFFFUL); + + do { + usb_chrst(USBx, (uint8_t)u32Tmp); + u32Tmp++; + } while (u32Tmp < u8ChNum); + /* flush all the txFIFOs and the whole rxFIFO */ + usb_rxfifoflush(USBx); + usb_txfifoflush(USBx, 0x10UL); +} + +/** + * @brief make the channel to halt + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @retval None + */ +void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + uint32_t u32hcchar; + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar |= (USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS); + /* Check for space in the request queue to issue the halt. */ + if ((EP_TYPE_CTRL == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS)) + || (EP_TYPE_BULK == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS))) { + if (0UL == (READ_REG32(USBx->GREGS->HNPTXSTS) & USBFS_HNPTXSTS_NPTQXSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + } + } else { + if (0UL == (READ_REG32(USBx->HREGS->HPTXSTS) & USBFS_HPTXSTS_PTXQSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + } + } + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); +} + +#endif + +/** + * @} +*/ + +#endif /* LL_USB_ENABLE */ + +/** + * @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c new file mode 100644 index 0000000000..0900b3232b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c @@ -0,0 +1,396 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.c + * @brief This file provides utility functions for DDL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_UTILITY UTILITY + * @brief DDL Utility Driver + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Variables UTILITY Local Variables + * @{ + */ + +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (LL_PRINT_ENABLE == DDL_ON) +static void *m_pvPrintDevice = NULL; +static uint32_t m_u32PrintTimeout = 0UL; +#endif + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ +#if (LL_PRINT_ENABLE == DDL_ON) + +/** + * @brief Set print device. + * @param [in] pvPrintDevice Pointer to print device + * @retval None + */ +__STATIC_INLINE void LL_SetPrintDevice(void *pvPrintDevice) +{ + m_pvPrintDevice = pvPrintDevice; +} + +/** + * @brief Get print device. + * @param None + * @retval Pointer to print device + */ +__STATIC_INLINE void *LL_GetPrintDevice(void) +{ + return m_pvPrintDevice; +} + +/** + * @brief Set print timeout. + * @param [in] u32Timeout Print timeout value + * @retval None + */ +__STATIC_INLINE void LL_SetPrintTimeout(uint32_t u32Timeout) +{ + m_u32PrintTimeout = u32Timeout; +} + +/** + * @brief Get print timeout. + * @param None + * @retval Print timeout value + */ +__STATIC_INLINE uint32_t LL_GetPrintTimeout(void) +{ + return m_u32PrintTimeout; +} +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @defgroup UTILITY_Global_Functions UTILITY Global Functions + * @{ + */ + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +void DDL_DelayMS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000UL - 1UL) / 10000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +void DDL_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000000UL - 1UL) / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief This function Initializes the interrupt frequency of the SysTick. + * @param [in] u32Freq SysTick interrupt frequency (1 to 1000). + * @retval int32_t: + * - LL_OK: SysTick Initializes succeed + * - LL_ERR: SysTick Initializes failed + */ +__WEAKDEF int32_t SysTick_Init(uint32_t u32Freq) +{ + int32_t i32Ret = LL_ERR; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief This function provides minimum delay (in milliseconds). + * @param [in] u32Delay Delay specifies the delay time. + * @retval None + */ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd = u32Delay; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) { + tickEnd = tickMax; + } + while ((SysTick_GetTick() - tickStart) < tickEnd) { + } + } +} + +/** + * @brief This function is called to increment a global variable "u32TickCount". + * @note This variable is incremented in SysTick ISR. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + * @brief Provides a tick value in millisecond. + * @param None + * @retval Tick value + */ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + * @brief Suspend SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +#ifdef __DEBUG +/** + * @brief DDL assert error handle function + * @param [in] file Point to the current assert the wrong file. + * @param [in] line Point line assert the wrong file in the current. + * @retval None + */ +__WEAKDEF void DDL_AssertHandler(const char *file, int line) +{ + /* Users can re-implement this function to print information */ + DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line); + + for (;;) { + } +} +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (LL_OK == DDL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (LL_OK != DDL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param [in] vpDevice Pointer to print device + * @param [in] u32Param Print device parameter + * @param [in] pfnPreinit The function pointer for initializing clock, port, print device etc. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: The callback function pfnPreinit occurs error. + * - LL_ERR_INVD_PARAM: The pointer pfnPreinit is NULL. + */ +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pfnPreinit) { + i32Ret = pfnPreinit(vpDevice, u32Param); /* The callback function initialize clock, port, print device etc */ + if (LL_OK == i32Ret) { + LL_SetPrintDevice(vpDevice); + LL_SetPrintTimeout((u32Param == 0UL) ? 0UL : (HCLK_VALUE / u32Param)); + } else { + i32Ret = LL_ERR; + DDL_ASSERT(i32Ret == LL_OK); /* Initialize unsuccessfully */ + } + } + + return i32Ret; +} + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval int32_t: + * - LL_OK: Transmit successfully. + * - LL_ERR_TIMEOUT: Transmit timeout. + * - LL_ERR_INVD_PARAM: The print device is invalid. + */ +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData) +{ + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Timeout = LL_GetPrintTimeout(); + CM_USART_TypeDef *USARTx = (CM_USART_TypeDef *)LL_GetPrintDevice(); + + if (NULL != USARTx) { + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG32(USARTx->DR, (uint32_t)cData); + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_TIMEOUT; + } + } + + return i32Ret; +} + +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c new file mode 100644 index 0000000000..b16d46024d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c @@ -0,0 +1,256 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.c + * @brief This file provides firmware functions to manage the General Watch Dog + * Timer(WDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_wdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_WDT WDT + * @brief General Watch Dog Timer + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Local_Macros WDT Local Macros + * @{ + */ + +/* WDT Refresh Key */ +#define WDT_REFRESH_KEY_START (0x0123UL) +#define WDT_REFRESH_KEY_END (0x3210UL) + +/* WDT clear flag timeout(ms) */ +#define WDT_CLR_FLAG_TIMEOUT (5UL) + +/* WDT Registers Clear Mask */ +#define WDT_CR_CLR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \ + WDT_CR_SLPOFF | WDT_CR_ITS) + +/** + * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity + * @{ + */ +#define IS_WDT_CNT_PERIOD(x) \ +( ((x) == WDT_CNT_PERIOD256) || \ + ((x) == WDT_CNT_PERIOD4096) || \ + ((x) == WDT_CNT_PERIOD16384) || \ + ((x) == WDT_CNT_PERIOD65536)) + +#define IS_WDT_CLK_DIV(x) \ +( ((x) == WDT_CLK_DIV4) || \ + ((x) == WDT_CLK_DIV64) || \ + ((x) == WDT_CLK_DIV128) || \ + ((x) == WDT_CLK_DIV256) || \ + ((x) == WDT_CLK_DIV512) || \ + ((x) == WDT_CLK_DIV1024) || \ + ((x) == WDT_CLK_DIV2048) || \ + ((x) == WDT_CLK_DIV8192)) + +#define IS_WDT_REFRESH_RANGE(x) \ +( ((x) == WDT_RANGE_0TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT) || \ + ((x) == WDT_RANGE_25TO50PCT) || \ + ((x) == WDT_RANGE_0TO50PCT) || \ + ((x) == WDT_RANGE_50TO75PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == WDT_RANGE_25TO75PCT) || \ + ((x) == WDT_RANGE_0TO75PCT) || \ + ((x) == WDT_RANGE_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_50TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == WDT_RANGE_25TO100PCT)) + +#define IS_WDT_LPM_CNT(x) \ +( ((x) == WDT_LPM_CNT_CONTINUE) || \ + ((x) == WDT_LPM_CNT_STOP)) + +#define IS_WDT_EXP_TYPE(x) \ +( ((x) == WDT_EXP_TYPE_INT) || \ + ((x) == WDT_EXP_TYPE_RST)) + +#define IS_WDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | WDT_FLAG_ALL) == WDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Functions WDT Global Functions + * @{ + */ + +/** + * @brief Initializes WDT. + * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcWdtInit == NULL + */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcWdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_WDT_CNT_PERIOD(pstcWdtInit->u32CountPeriod)); + DDL_ASSERT(IS_WDT_CLK_DIV(pstcWdtInit->u32ClockDiv)); + DDL_ASSERT(IS_WDT_REFRESH_RANGE(pstcWdtInit->u32RefreshRange)); + DDL_ASSERT(IS_WDT_LPM_CNT(pstcWdtInit->u32LPMCount)); + DDL_ASSERT(IS_WDT_EXP_TYPE(pstcWdtInit->u32ExceptionType)); + + /* WDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_WDT->CR, WDT_CR_CLR_MASK, + (pstcWdtInit->u32CountPeriod | pstcWdtInit->u32ClockDiv | + pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPMCount | + pstcWdtInit->u32ExceptionType)); + } + + return i32Ret; +} + +/** + * @brief WDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void WDT_FeedDog(void) +{ + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_START); + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_END); +} + +/** + * @brief Get WDT flag status. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_WDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear WDT flag. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t WDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_WDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = WDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_WDT->SR, u32Flag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c new file mode 100644 index 0000000000..50a193779e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c @@ -0,0 +1,4719 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ll_interrupts_share.c + * @brief This file provides firmware functions to manage the Share Interrupt + * Controller (SHARE_INTERRUPTS). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_ll_interrupts_share.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HC32F4A0_SHARE_INTERRUPTS SHARE_INTERRUPTS + * @brief Share Interrupts Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup Share_Interrupts_Global_Functions Share Interrupts Global Functions + * @{ + */ +/** + * @brief Share IRQ configure + * @param [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Share IRQ configure successfully + */ +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) +{ + __IO uint32_t *INTC_VSSELx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + INTC_VSSELx = (__IO uint32_t *)(((uint32_t)&CM_INTC->VSSEL128) + (4U * ((uint32_t)enIntSrc / 0x20U))); + if (ENABLE == enNewState) { + SET_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } else { + CLR_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } + return LL_OK; +} + +/** + * @brief Interrupt No.128 share IRQ handler + * @param None + * @retval None + */ +void IRQ128_Handler(void) +{ + const uint32_t VSSEL128 = CM_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR0) && (0UL != (VSSEL128 & BIT_MASK_00))) { + EXTINT00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR1) && (0UL != (VSSEL128 & BIT_MASK_01))) { + EXTINT01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR2) && (0UL != (VSSEL128 & BIT_MASK_02))) { + EXTINT02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR3) && (0UL != (VSSEL128 & BIT_MASK_03))) { + EXTINT03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR4) && (0UL != (VSSEL128 & BIT_MASK_04))) { + EXTINT04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR5) && (0UL != (VSSEL128 & BIT_MASK_05))) { + EXTINT05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR6) && (0UL != (VSSEL128 & BIT_MASK_06))) { + EXTINT06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR7) && (0UL != (VSSEL128 & BIT_MASK_07))) { + EXTINT07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR8) && (0UL != (VSSEL128 & BIT_MASK_08))) { + EXTINT08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR9) && (0UL != (VSSEL128 & BIT_MASK_09))) { + EXTINT09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR10) && (0UL != (VSSEL128 & BIT_MASK_10))) { + EXTINT10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR11) && (0UL != (VSSEL128 & BIT_MASK_11))) { + EXTINT11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR12) && (0UL != (VSSEL128 & BIT_MASK_12))) { + EXTINT12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR13) && (0UL != (VSSEL128 & BIT_MASK_13))) { + EXTINT13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR14) && (0UL != (VSSEL128 & BIT_MASK_14))) { + EXTINT14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR15) && (0UL != (VSSEL128 & BIT_MASK_15))) { + EXTINT15_IrqHandler(); + } +} + +/** + * @brief Interrupt No.129 share IRQ handler + * @param None + * @retval None + */ +void IRQ129_Handler(void) +{ + const uint32_t VSSEL129 = CM_INTC->VSSEL129; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* DMA1 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL0_b.IE) { + /* DMA1 Ch.0 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_00))) { + DMA1_TC0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_08))) { + DMA1_BTC0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error0_IrqHandler(); + } + } + /* DMA1 Ch.1 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL1_b.IE) { + /* DMA1 Ch.1 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_01))) { + DMA1_TC1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_09))) { + DMA1_BTC1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error1_IrqHandler(); + } + } + /* DMA1 Ch.2 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL2_b.IE) { + /* DMA1 Ch.2 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_02))) { + DMA1_TC2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_10))) { + DMA1_BTC2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error2_IrqHandler(); + } + } + /* DMA1 Ch.3 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL3_b.IE) { + /* DMA1 Ch.3 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_03))) { + DMA1_TC3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_11))) { + DMA1_BTC3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error3_IrqHandler(); + } + } + /* DMA1 Ch.4 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL4_b.IE) { + /* DMA1 Ch.4 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC4) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC4) && (0UL != (VSSEL129 & BIT_MASK_04))) { + DMA1_TC4_IrqHandler(); + } + } + /* DMA1 ch.4 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC4) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC4) && (0UL != (VSSEL129 & BIT_MASK_12))) { + DMA1_BTC4_IrqHandler(); + } + } + /* DMA1 ch.4 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_04 | BIT_MASK_20); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_04 | BIT_MASK_20)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error4_IrqHandler(); + } + } + /* DMA1 Ch.5 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL5_b.IE) { + /* DMA1 Ch.5 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC5) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC5) && (0UL != (VSSEL129 & BIT_MASK_05))) { + DMA1_TC5_IrqHandler(); + } + } + /* DMA1 ch.5 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC5) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC5) && (0UL != (VSSEL129 & BIT_MASK_13))) { + DMA1_BTC5_IrqHandler(); + } + } + /* DMA1 ch.5 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_05 | BIT_MASK_21); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_05 | BIT_MASK_21)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error5_IrqHandler(); + } + } + /* DMA1 Ch.6 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL6_b.IE) { + /* DMA1 Ch.6 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC6) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC6) && (0UL != (VSSEL129 & BIT_MASK_06))) { + DMA1_TC6_IrqHandler(); + } + } + /* DMA1 ch.6 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC6) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC6) && (0UL != (VSSEL129 & BIT_MASK_14))) { + DMA1_BTC6_IrqHandler(); + } + } + /* DMA1 ch.6 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_06 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_06 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error6_IrqHandler(); + } + } + /* DMA1 Ch.7 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL7_b.IE) { + /* DMA1 Ch.7 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC7) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC7) && (0UL != (VSSEL129 & BIT_MASK_07))) { + DMA1_TC7_IrqHandler(); + } + } + /* DMA1 ch.7 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC7) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC7) && (0UL != (VSSEL129 & BIT_MASK_15))) { + DMA1_BTC7_IrqHandler(); + } + } + /* DMA1 ch.7 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_07 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_07 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error7_IrqHandler(); + } + } + /* EFM error */ + if (1UL == bCM_EFM->FITE_b.PEERRITE) { + /* EFM program/erase/protect/otp error */ + u32Tmp1 = CM_EFM->FSR & (EFM_FSR_PRTWERR0 | EFM_FSR_PGSZERR0 | EFM_FSR_MISMTCH0 | \ + EFM_FSR_PRTWERR1 | EFM_FSR_PGSZERR1 | EFM_FSR_MISMTCH1 | \ + EFM_FSR_OTPWERR0); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_17))) { + EFM_ProgramEraseError_IrqHandler(); + } + } + /* EFM read collision error*/ + if (1UL == bCM_EFM->FITE_b.COLERRITE) { + /* EFM read collision */ + u32Tmp1 = CM_EFM->FSR & (EFM_FSR_COLERR0 | EFM_FSR_COLERR1); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_18))) { + EFM_ColError_IrqHandler(); + } + } + /* EFM operate end */ + if (1UL == bCM_EFM->FITE_b.OPTENDITE) { + /* EFM operate end */ + u32Tmp1 = CM_EFM->FSR & (EFM_FSR_OPTEND0 | EFM_FSR_OPTEND1); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_19))) { + EFM_OpEnd_IrqHandler(); + } + } + /* QSPI access error */ + u32Tmp1 = CM_QSPI->SR & QSPI_SR_RAER; + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_22))) { + QSPI_Error_IrqHandler(); + } + /*DCU1 */ + u32Tmp1 = CM_DCU1->INTSEL; + u32Tmp2 = CM_DCU1->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_23))) { + DCU1_IrqHandler(); + } + /*DCU2 */ + u32Tmp1 = CM_DCU2->INTSEL; + u32Tmp2 = CM_DCU2->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_24))) { + DCU2_IrqHandler(); + } + /*DCU3 */ + u32Tmp1 = CM_DCU3->INTSEL; + u32Tmp2 = CM_DCU3->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_25))) { + DCU3_IrqHandler(); + } + /*DCU4 */ + u32Tmp1 = CM_DCU4->INTSEL; + u32Tmp2 = CM_DCU4->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_26))) { + DCU4_IrqHandler(); + } + /*DCU5 */ + u32Tmp1 = CM_DCU5->INTSEL; + u32Tmp2 = CM_DCU5->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_27))) { + DCU5_IrqHandler(); + } + /*DCU6 */ + u32Tmp1 = CM_DCU6->INTSEL; + u32Tmp2 = CM_DCU6->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_28))) { + DCU6_IrqHandler(); + } + /*DCU7 */ + u32Tmp1 = CM_DCU7->INTSEL; + u32Tmp2 = CM_DCU7->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_29))) { + DCU7_IrqHandler(); + } + /*DCU8 */ + u32Tmp1 = CM_DCU8->INTSEL; + u32Tmp2 = CM_DCU8->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_30))) { + DCU8_IrqHandler(); + } +} + +/** + * @brief Interrupt No.130 share IRQ handler + * @param None + * @retval None + */ +void IRQ130_Handler(void) +{ + const uint32_t VSSEL130 = CM_INTC->VSSEL130; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* MAU square */ + if (0UL != (VSSEL130 & BIT_MASK_19)) { + MAU_Sqrt_IrqHandler(); + } else { + /* DMA2 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL0_b.IE) { + /* DMA2 Ch.0 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC0) && (0UL != (VSSEL130 & BIT_MASK_00))) { + DMA2_TC0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC0) && (0UL != (VSSEL130 & BIT_MASK_08))) { + DMA2_BTC0_IrqHandler(); + } + } + /* DMA2 ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error0_IrqHandler(); + } + } + /* DMA2 Ch.1 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL1_b.IE) { + /* DMA2 Ch.1 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC1) && (0UL != (VSSEL130 & BIT_MASK_01))) { + DMA2_TC1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC1) && (0UL != (VSSEL130 & BIT_MASK_09))) { + DMA2_BTC1_IrqHandler(); + } + } + /* DMA2 ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error1_IrqHandler(); + } + } + /* DMA2 Ch.2 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL2_b.IE) { + /* DMA2 Ch.2 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC2) && (0UL != (VSSEL130 & BIT_MASK_02))) { + DMA2_TC2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC2) && (0UL != (VSSEL130 & BIT_MASK_10))) { + DMA2_BTC2_IrqHandler(); + } + } + /* DMA2 ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error2_IrqHandler(); + } + } + /* DMA2 Ch.3 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL3_b.IE) { + /* DMA2 Ch.3 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC3) && (0UL != (VSSEL130 & BIT_MASK_03))) { + DMA2_TC3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC3) && (0UL != (VSSEL130 & BIT_MASK_11))) { + DMA2_BTC3_IrqHandler(); + } + } + /* DMA2 ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error3_IrqHandler(); + } + } + /* DMA2 Ch.4 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL4_b.IE) { + /* DMA2 Ch.4 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC4) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC4) && (0UL != (VSSEL130 & BIT_MASK_04))) { + DMA2_TC4_IrqHandler(); + } + } + /* DMA2 ch.4 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC4) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC4) && (0UL != (VSSEL130 & BIT_MASK_12))) { + DMA2_BTC4_IrqHandler(); + } + } + /* DMA2 ch.4 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_04 | BIT_MASK_20); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_04 | BIT_MASK_20)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error4_IrqHandler(); + } + } + /* DMA2 Ch.5 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL5_b.IE) { + /* DMA2 Ch.5 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC5) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC5) && (0UL != (VSSEL130 & BIT_MASK_05))) { + DMA2_TC5_IrqHandler(); + } + } + /* DMA2 ch.5 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC5) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC5) && (0UL != (VSSEL130 & BIT_MASK_13))) { + DMA2_BTC5_IrqHandler(); + } + } + /* DMA2 ch.5 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_05 | BIT_MASK_21); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_05 | BIT_MASK_21)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error5_IrqHandler(); + } + } + /* DMA2 Ch.6 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL6_b.IE) { + /* DMA2 Ch.6 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC6) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC6) && (0UL != (VSSEL130 & BIT_MASK_06))) { + DMA2_TC6_IrqHandler(); + } + } + /* DMA2 ch.6 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC6) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC6) && (0UL != (VSSEL130 & BIT_MASK_14))) { + DMA2_BTC6_IrqHandler(); + } + } + /* DMA2 ch.6 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_06 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_06 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error6_IrqHandler(); + } + } + /* DMA2 Ch.7 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL7_b.IE) { + /* DMA2 Ch.7 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC7) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC7) && (0UL != (VSSEL130 & BIT_MASK_07))) { + DMA2_TC7_IrqHandler(); + } + } + /* DMA2 ch.7 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC7) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC7) && (0UL != (VSSEL130 & BIT_MASK_15))) { + DMA2_BTC7_IrqHandler(); + } + } + /* DMA2 ch.7 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_07 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_07 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) { + DMA2_Error7_IrqHandler(); + } + } + /* DVP frame start */ + if (1UL == bCM_DVP->IER_b.FSIEN) { + if ((1UL == bCM_DVP->STR_b.FSF) && (0UL != (VSSEL130 & BIT_MASK_20))) { + DVP_FrameStart_IrqHandler(); + } + } + /* DVP line start */ + if (1UL == bCM_DVP->IER_b.LSIEN) { + if ((1UL == bCM_DVP->STR_b.LSF) && (0UL != (VSSEL130 & BIT_MASK_21))) { + DVP_LineStart_IrqHandler(); + } + } + /* DVP line end */ + if (1UL == bCM_DVP->IER_b.LEIEN) { + if ((1UL == bCM_DVP->STR_b.LEF) && (0UL != (VSSEL130 & BIT_MASK_22))) { + DVP_LineEnd_IrqHandler(); + } + } + /* DVP frame end */ + if (1UL == bCM_DVP->IER_b.FEIEN) { + if ((1UL == bCM_DVP->STR_b.FEF) && (0UL != (VSSEL130 & BIT_MASK_23))) { + DVP_FrameEnd_IrqHandler(); + } + } + /* DVP software sync err */ + if (1UL == bCM_DVP->IER_b.SQUERIEN) { + if ((1UL == bCM_DVP->STR_b.SQUERF) && (0UL != (VSSEL130 & BIT_MASK_24))) { + DVP_SWSyncError_IrqHandler(); + } + } + /* DVP fifo overfolw err */ + if (1UL == bCM_DVP->IER_b.FIFOERIEN) { + if ((1UL == bCM_DVP->STR_b.FIFOERF) && (0UL != (VSSEL130 & BIT_MASK_25))) { + DVP_FifoError_IrqHandler(); + } + } + /* FMAC 1 */ + if (1UL == bCM_FMAC1->IER_b.INTEN) { + if ((1UL == bCM_FMAC1->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_27))) { + FMAC1_IrqHandler(); + } + } + /* FMAC 2 */ + if (1UL == bCM_FMAC2->IER_b.INTEN) { + if ((1UL == bCM_FMAC2->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_28))) { + FMAC2_IrqHandler(); + } + } + /* FMAC 3 */ + if (1UL == bCM_FMAC3->IER_b.INTEN) { + if ((1UL == bCM_FMAC3->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_29))) { + FMAC3_IrqHandler(); + } + } + /* FMAC 4 */ + if (1UL == bCM_FMAC4->IER_b.INTEN) { + if ((1UL == bCM_FMAC4->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_30))) { + FMAC4_IrqHandler(); + } + } + } +} + +/** + * @brief Interrupt No.131 share IRQ handler + * @param None + * @retval None + */ +void IRQ131_Handler(void) +{ + const uint32_t VSSEL131 = CM_INTC->VSSEL131; + uint32_t u32Tmp1; + + /* Timer0 unit1, Ch.A compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_00))) { + TMR0_1_CmpA_IrqHandler(); + } + } + /* Timer0 unit1, Ch.B compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_01))) { + TMR0_1_CmpB_IrqHandler(); + } + } + /* Timer0 unit2, Ch.A compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_02))) { + TMR0_2_CmpA_IrqHandler(); + } + } + /* Timer0 unit2, Ch.B compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_03))) { + TMR0_2_CmpB_IrqHandler(); + } + } + /* Timer2 unit1, Ch.A compare match */ + if (1UL == bCM_TMR2_1->ICONR_b.CMENA) { + if ((1UL == bCM_TMR2_1->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_04))) { + TMR2_1_CmpA_IrqHandler(); + } + } + /* Timer2 unit1, Ch.B compare match */ + if (1UL == bCM_TMR2_1->ICONR_b.CMENB) { + if ((1UL == bCM_TMR2_1->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_05))) { + TMR2_1_CmpB_IrqHandler(); + } + } + /* Timer2 unit1, Ch.A overflow */ + if (1UL == bCM_TMR2_1->ICONR_b.OVENA) { + if ((1UL == bCM_TMR2_1->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_06))) { + TMR2_1_OvfA_IrqHandler(); + } + } + /* Timer2 unit1, Ch.B overflow */ + if (1UL == bCM_TMR2_1->ICONR_b.OVENB) { + if ((1UL == bCM_TMR2_1->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_07))) { + TMR2_1_OvfB_IrqHandler(); + } + } + /* Timer2 unit2, Ch.A compare match */ + if (1UL == bCM_TMR2_2->ICONR_b.CMENA) { + if ((1UL == bCM_TMR2_2->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_08))) { + TMR2_2_CmpA_IrqHandler(); + } + } + /* Timer2 unit2, Ch.B compare match */ + if (1UL == bCM_TMR2_2->ICONR_b.CMENB) { + if ((1UL == bCM_TMR2_2->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_09))) { + TMR2_2_CmpB_IrqHandler(); + } + } + /* Timer2 unit2, Ch.A overflow */ + if (1UL == bCM_TMR2_2->ICONR_b.OVENA) { + if ((1UL == bCM_TMR2_2->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_10))) { + TMR2_2_OvfA_IrqHandler(); + } + } + /* Timer2 unit2, Ch.B overflow */ + if (1UL == bCM_TMR2_2->ICONR_b.OVENB) { + if ((1UL == bCM_TMR2_2->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_11))) { + TMR2_2_OvfB_IrqHandler(); + } + } + /* Timer2 unit3, Ch.A compare match */ + if (1UL == bCM_TMR2_3->ICONR_b.CMENA) { + if ((1UL == bCM_TMR2_3->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_12))) { + TMR2_3_CmpA_IrqHandler(); + } + } + /* Timer2 unit3, Ch.B compare match */ + if (1UL == bCM_TMR2_3->ICONR_b.CMENB) { + if ((1UL == bCM_TMR2_3->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_13))) { + TMR2_3_CmpB_IrqHandler(); + } + } + /* Timer2 unit3, Ch.A overflow */ + if (1UL == bCM_TMR2_3->ICONR_b.OVENA) { + if ((1UL == bCM_TMR2_3->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_14))) { + TMR2_3_OvfA_IrqHandler(); + } + } + /* Timer2 unit3, Ch.B overflow */ + if (1UL == bCM_TMR2_3->ICONR_b.OVENB) { + if ((1UL == bCM_TMR2_3->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_15))) { + TMR2_3_OvfB_IrqHandler(); + } + } + /* Timer2 unit4, Ch.A compare match */ + if (1UL == bCM_TMR2_4->ICONR_b.CMENA) { + if ((1UL == bCM_TMR2_4->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_16))) { + TMR2_4_CmpA_IrqHandler(); + } + } + /* Timer2 unit4, Ch.B compare match */ + if (1UL == bCM_TMR2_4->ICONR_b.CMENB) { + if ((1UL == bCM_TMR2_4->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_17))) { + TMR2_4_CmpB_IrqHandler(); + } + } + /* Timer2 unit4, Ch.A overflow */ + if (1UL == bCM_TMR2_4->ICONR_b.OVENA) { + if ((1UL == bCM_TMR2_4->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_18))) { + TMR2_4_OvfA_IrqHandler(); + } + } + /* Timer2 unit4, Ch.B overflow */ + if (1UL == bCM_TMR2_4->ICONR_b.OVENB) { + if ((1UL == bCM_TMR2_4->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_19))) { + TMR2_4_OvfB_IrqHandler(); + } + } + /* RTC time stamp 0 */ + if (1UL == bCM_RTC->TPCR0_b.TPIE0) { + if ((1UL == bCM_RTC->TPSR_b.TPF0) && (0UL != (VSSEL131 & BIT_MASK_24))) { + RTC_TimeStamp0_IrqHandler(); + } + } + /* RTC time stamp 1 */ + if (1UL == bCM_RTC->TPCR1_b.TPIE1) { + if ((1UL == bCM_RTC->TPSR_b.TPF1) && (0UL != (VSSEL131 & BIT_MASK_24))) { + RTC_TimeStamp1_IrqHandler(); + } + } + /* RTC alarm */ + if (1UL == bCM_RTC->CR2_b.ALMIE) { + if ((1UL == bCM_RTC->CR2_b.ALMF) && (0UL != (VSSEL131 & BIT_MASK_25))) { + RTC_Alarm_IrqHandler(); + } + } + /* RTC period */ + if (1UL == bCM_RTC->CR2_b.PRDIE) { + if ((1UL == bCM_RTC->CR2_b.PRDF) && (0UL != (VSSEL131 & BIT_MASK_26))) { + RTC_Period_IrqHandler(); + } + } + /* XTAL stop */ + if (1UL == bCM_CMU->XTALSTDCR_b.XTALSTDIE) { + if ((1UL == bCM_CMU->XTALSTDSR_b.XTALSTDF) && (0UL != (VSSEL131 & BIT_MASK_29))) { + CLK_XtalStop_IrqHandler(); + } + } + /* Wakeup timer overflow */ + if (1UL == bCM_PWC->WKTC2_b.WKTCE) { + if ((1UL == bCM_PWC->WKTC2_b.WKOVF) && (0UL != (VSSEL131 & BIT_MASK_30))) { + PWC_WakeupTimer_IrqHandler(); + } + } + /* SWDT underflow or refresh error */ + u32Tmp1 = CM_SWDT->SR & (SWDT_SR_UDF | SWDT_SR_REF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL131 & BIT_MASK_31))) { + SWDT_IrqHandler(); + } +} + +/** + * @brief Interrupt No.132 share IRQ handler + * @param None + * @retval None + */ +void IRQ132_Handler(void) +{ + const uint32_t VSSEL132 = CM_INTC->VSSEL132; + + /* Timer6 Ch.1 general compare match A */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_00))) { + TMR6_1_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match B */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_01))) { + TMR6_1_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match C */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_02))) { + TMR6_1_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match D */ + if (1UL == bCM_TMR6_1->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_03))) { + TMR6_1_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match E */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_04))) { + TMR6_1_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match F */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_05))) { + TMR6_1_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_1->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_06))) { + TMR6_1_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_1->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_07))) { + TMR6_1_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase higher compare match */ + if (1UL == bCM_TMR4_1->OCSRU_b.OCIEH) { + if ((1UL == bCM_TMR4_1->OCSRU_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_08))) { + TMR4_1_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase lower compare match */ + if (1UL == bCM_TMR4_1->OCSRU_b.OCIEL) { + if ((1UL == bCM_TMR4_1->OCSRU_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_09))) { + TMR4_1_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase higher compare match */ + if (1UL == bCM_TMR4_1->OCSRV_b.OCIEH) { + if ((1UL == bCM_TMR4_1->OCSRV_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_10))) { + TMR4_1_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase lower compare match */ + if (1UL == bCM_TMR4_1->OCSRV_b.OCIEL) { + if ((1UL == bCM_TMR4_1->OCSRV_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_11))) { + TMR4_1_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase higher compare match */ + if (1UL == bCM_TMR4_1->OCSRW_b.OCIEH) { + if ((1UL == bCM_TMR4_1->OCSRW_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_12))) { + TMR4_1_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase lower compare match */ + if (1UL == bCM_TMR4_1->OCSRW_b.OCIEL) { + if ((1UL == bCM_TMR4_1->OCSRW_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_13))) { + TMR4_1_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.1 overflow */ + if (1UL == bCM_TMR4_1->CCSR_b.IRQPEN) { + if ((1UL == bCM_TMR4_1->CCSR_b.IRQPF) && (0UL != (VSSEL132 & BIT_MASK_14))) { + TMR4_1_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.1 underflow */ + if (1UL == bCM_TMR4_1->CCSR_b.IRQZEN) { + if ((1UL == bCM_TMR4_1->CCSR_b.IRQZF) && (0UL != (VSSEL132 & BIT_MASK_15))) { + TMR4_1_Udf_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match A */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_16))) { + TMR6_2_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match B */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_17))) { + TMR6_2_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match C */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_18))) { + TMR6_2_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match D */ + if (1UL == bCM_TMR6_2->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_19))) { + TMR6_2_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match E */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_20))) { + TMR6_2_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match F */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_21))) { + TMR6_2_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_2->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_22))) { + TMR6_2_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_2->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_23))) { + TMR6_2_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase higher compare match */ + if (1UL == bCM_TMR4_2->OCSRU_b.OCIEH) { + if ((1UL == bCM_TMR4_2->OCSRU_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_24))) { + TMR4_2_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase lower compare match */ + if (1UL == bCM_TMR4_2->OCSRU_b.OCIEL) { + if ((1UL == bCM_TMR4_2->OCSRU_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_25))) { + TMR4_2_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase higher compare match */ + if (1UL == bCM_TMR4_2->OCSRV_b.OCIEH) { + if ((1UL == bCM_TMR4_2->OCSRV_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_26))) { + TMR4_2_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase lower compare match */ + if (1UL == bCM_TMR4_2->OCSRV_b.OCIEL) { + if ((1UL == bCM_TMR4_2->OCSRV_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_27))) { + TMR4_2_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase higher compare match */ + if (1UL == bCM_TMR4_2->OCSRW_b.OCIEH) { + if ((1UL == bCM_TMR4_2->OCSRW_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_28))) { + TMR4_2_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase lower compare match */ + if (1UL == bCM_TMR4_2->OCSRW_b.OCIEL) { + if ((1UL == bCM_TMR4_2->OCSRW_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_29))) { + TMR4_2_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.2 overflow */ + if (1UL == bCM_TMR4_2->CCSR_b.IRQPEN) { + if ((1UL == bCM_TMR4_2->CCSR_b.IRQPF) && (0UL != (VSSEL132 & BIT_MASK_30))) { + TMR4_2_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.2 underflow */ + if (1UL == bCM_TMR4_2->CCSR_b.IRQZEN) { + if ((1UL == bCM_TMR4_2->CCSR_b.IRQZF) && (0UL != (VSSEL132 & BIT_MASK_31))) { + TMR4_2_Udf_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.133 share IRQ handler + * @param None + * @retval None + */ +void IRQ133_Handler(void) +{ + const uint32_t VSSEL133 = CM_INTC->VSSEL133; + + /* Timer6 Ch.3 general compare match A */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMAF) && (0UL != (VSSEL133 & BIT_MASK_00))) { + TMR6_3_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match B */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMBF) && (0UL != (VSSEL133 & BIT_MASK_01))) { + TMR6_3_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match C */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMCF) && (0UL != (VSSEL133 & BIT_MASK_02))) { + TMR6_3_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match D */ + if (1UL == bCM_TMR6_3->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMDF) && (0UL != (VSSEL133 & BIT_MASK_03))) { + TMR6_3_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match E */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMEF) && (0UL != (VSSEL133 & BIT_MASK_04))) { + TMR6_3_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match F */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMFF) && (0UL != (VSSEL133 & BIT_MASK_05))) { + TMR6_3_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_3->STFLR_b.OVFF) && (0UL != (VSSEL133 & BIT_MASK_06))) { + TMR6_3_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_3->STFLR_b.UDFF) && (0UL != (VSSEL133 & BIT_MASK_07))) { + TMR6_3_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase higher compare match */ + if (1UL == bCM_TMR4_3->OCSRU_b.OCIEH) { + if ((1UL == bCM_TMR4_3->OCSRU_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_08))) { + TMR4_3_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase lower compare match */ + if (1UL == bCM_TMR4_3->OCSRU_b.OCIEL) { + if ((1UL == bCM_TMR4_3->OCSRU_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_09))) { + TMR4_3_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase higher compare match */ + if (1UL == bCM_TMR4_3->OCSRV_b.OCIEH) { + if ((1UL == bCM_TMR4_3->OCSRV_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_10))) { + TMR4_3_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase lower compare match */ + if (1UL == bCM_TMR4_3->OCSRV_b.OCIEL) { + if ((1UL == bCM_TMR4_3->OCSRV_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_11))) { + TMR4_3_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase higher compare match */ + if (1UL == bCM_TMR4_3->OCSRW_b.OCIEH) { + if ((1UL == bCM_TMR4_3->OCSRW_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_12))) { + TMR4_3_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase lower compare match */ + if (1UL == bCM_TMR4_3->OCSRW_b.OCIEL) { + if ((1UL == bCM_TMR4_3->OCSRW_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_13))) { + TMR4_3_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.3 overflow */ + if (1UL == bCM_TMR4_3->CCSR_b.IRQPEN) { + if ((1UL == bCM_TMR4_3->CCSR_b.IRQPF) && (0UL != (VSSEL133 & BIT_MASK_14))) { + TMR4_3_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.3 underflow */ + if (1UL == bCM_TMR4_3->CCSR_b.IRQZEN) { + if ((1UL == bCM_TMR4_3->CCSR_b.IRQZF) && (0UL != (VSSEL133 & BIT_MASK_15))) { + TMR4_3_Udf_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_1->STFLR_b.DTEF) && (0UL != (VSSEL133 & BIT_MASK_16))) { + TMR6_1_GDte_IrqHandler(); + } + } + /* Timer6 Ch.1 specified up compare match A*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMSAUF) && (0UL != (VSSEL133 & BIT_MASK_19))) { + TMR6_1_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.1 specified down compare match A*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMSADF) && (0UL != (VSSEL133 & BIT_MASK_19))) { + TMR6_1_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.1 specified up compare match B*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMSBUF) && (0UL != (VSSEL133 & BIT_MASK_20))) { + TMR6_1_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.1 specified down compare match B*/ + if (1UL == bCM_TMR6_1->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMSBDF) && (0UL != (VSSEL133 & BIT_MASK_20))) { + TMR6_1_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase reload */ + if (0UL == bCM_TMR4_1->RCSR_b.RTIDU) { + if ((1UL == bCM_TMR4_1->RCSR_b.RTIFU) && (0UL != (VSSEL133 & BIT_MASK_21))) { + TMR4_1_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase reload */ + if (0UL == bCM_TMR4_1->RCSR_b.RTIDV) { + if ((1UL == bCM_TMR4_1->RCSR_b.RTIFV) && (0UL != (VSSEL133 & BIT_MASK_22))) { + TMR4_1_ReloadV_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase reload */ + if (0UL == bCM_TMR4_1->RCSR_b.RTIDW) { + if ((1UL == bCM_TMR4_1->RCSR_b.RTIFW) && (0UL != (VSSEL133 & BIT_MASK_23))) { + TMR4_1_ReloadW_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_2->STFLR_b.DTEF) && (0UL != (VSSEL133 & BIT_MASK_24))) { + TMR6_2_GDte_IrqHandler(); + } + } + /* Timer6 Ch.2 specified up compare match A*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMSAUF) && (0UL != (VSSEL133 & BIT_MASK_27))) { + TMR6_2_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.2 specified down compare match A*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMSADF) && (0UL != (VSSEL133 & BIT_MASK_27))) { + TMR6_2_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.2 specified up compare match B*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMSBUF) && (0UL != (VSSEL133 & BIT_MASK_28))) { + TMR6_2_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.2 specified down compare match B*/ + if (1UL == bCM_TMR6_2->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMSBDF) && (0UL != (VSSEL133 & BIT_MASK_28))) { + TMR6_2_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase reload */ + if (0UL == bCM_TMR4_2->RCSR_b.RTIDU) { + if ((1UL == bCM_TMR4_2->RCSR_b.RTIFU) && (0UL != (VSSEL133 & BIT_MASK_29))) { + TMR4_2_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase reload */ + if (0UL == bCM_TMR4_2->RCSR_b.RTIDV) { + if ((1UL == bCM_TMR4_2->RCSR_b.RTIFV) && (0UL != (VSSEL133 & BIT_MASK_30))) { + TMR4_2_ReloadV_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase reload */ + if (0UL == bCM_TMR4_2->RCSR_b.RTIDW) { + if ((1UL == bCM_TMR4_2->RCSR_b.RTIFW) && (0UL != (VSSEL133 & BIT_MASK_31))) { + TMR4_2_ReloadW_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.134 share IRQ handler + * @param None + * @retval None + */ +void IRQ134_Handler(void) +{ + const uint32_t VSSEL134 = CM_INTC->VSSEL134; + + /* Timer6 Ch.3 dead time */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_3->STFLR_b.DTEF) && (0UL != (VSSEL134 & BIT_MASK_00))) { + TMR6_3_GDte_IrqHandler(); + } + } + /* Timer6 Ch.3 specified up compare match A*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMSAUF) && (0UL != (VSSEL134 & BIT_MASK_03))) { + TMR6_3_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.3 specified down compare match A*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMSADF) && (0UL != (VSSEL134 & BIT_MASK_03))) { + TMR6_3_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.3 specified up compare match B*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMSBUF) && (0UL != (VSSEL134 & BIT_MASK_04))) { + TMR6_3_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.3 specified down compare match B*/ + if (1UL == bCM_TMR6_3->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMSBDF) && (0UL != (VSSEL134 & BIT_MASK_04))) { + TMR6_3_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase reload */ + if (0UL == bCM_TMR4_3->RCSR_b.RTIDU) { + if ((1UL == bCM_TMR4_3->RCSR_b.RTIFU) && (0UL != (VSSEL134 & BIT_MASK_05))) { + TMR4_3_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase reload */ + if (0UL == bCM_TMR4_3->RCSR_b.RTIDV) { + if ((1UL == bCM_TMR4_3->RCSR_b.RTIFV) && (0UL != (VSSEL134 & BIT_MASK_06))) { + TMR4_3_ReloadV_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase reload */ + if (0UL == bCM_TMR4_3->RCSR_b.RTIDW) { + if ((1UL == bCM_TMR4_3->RCSR_b.RTIFW) && (0UL != (VSSEL134 & BIT_MASK_07))) { + TMR4_3_ReloadW_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match A */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMAF) && (0UL != (VSSEL134 & BIT_MASK_16))) { + TMR6_4_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match B */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMBF) && (0UL != (VSSEL134 & BIT_MASK_17))) { + TMR6_4_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match C */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMCF) && (0UL != (VSSEL134 & BIT_MASK_18))) { + TMR6_4_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match D */ + if (1UL == bCM_TMR6_4->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMDF) && (0UL != (VSSEL134 & BIT_MASK_19))) { + TMR6_4_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match E */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMEF) && (0UL != (VSSEL134 & BIT_MASK_20))) { + TMR6_4_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match F */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMFF) && (0UL != (VSSEL134 & BIT_MASK_21))) { + TMR6_4_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.4 overflow*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_4->STFLR_b.OVFF) && (0UL != (VSSEL134 & BIT_MASK_22))) { + TMR6_4_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.4 underflow*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_4->STFLR_b.UDFF) && (0UL != (VSSEL134 & BIT_MASK_23))) { + TMR6_4_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.4 dead time */ + if (1UL == bCM_TMR6_4->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_4->STFLR_b.DTEF) && (0UL != (VSSEL134 & BIT_MASK_24))) { + TMR6_4_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.4 specified up compare match A*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMSAUF) && (0UL != (VSSEL134 & BIT_MASK_27))) { + TMR6_4_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.4 specified down compare match A*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMSADF) && (0UL != (VSSEL134 & BIT_MASK_27))) { + TMR6_4_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.4 specified up compare match B*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMSBUF) && (0UL != (VSSEL134 & BIT_MASK_28))) { + TMR6_4_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.4 specified down compare match B*/ + if (1UL == bCM_TMR6_4->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_4->STFLR_b.CMSBDF) && (0UL != (VSSEL134 & BIT_MASK_28))) { + TMR6_4_SCmpDownB_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.135 share IRQ handler + * @param None + * @retval None + */ +void IRQ135_Handler(void) +{ + const uint32_t VSSEL135 = CM_INTC->VSSEL135; + + /* Timer6 Ch.5 general compare match A */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMAF) && (0UL != (VSSEL135 & BIT_MASK_00))) { + TMR6_5_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match B */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMBF) && (0UL != (VSSEL135 & BIT_MASK_01))) { + TMR6_5_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match C */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMCF) && (0UL != (VSSEL135 & BIT_MASK_02))) { + TMR6_5_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match D */ + if (1UL == bCM_TMR6_5->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMDF) && (0UL != (VSSEL135 & BIT_MASK_03))) { + TMR6_5_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match E */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMEF) && (0UL != (VSSEL135 & BIT_MASK_04))) { + TMR6_5_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match F */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMFF) && (0UL != (VSSEL135 & BIT_MASK_05))) { + TMR6_5_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.5 overflow*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_5->STFLR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_06))) { + TMR6_5_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.5 underflow*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_5->STFLR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_07))) { + TMR6_5_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.5 dead time */ + if (1UL == bCM_TMR6_5->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_5->STFLR_b.DTEF) && (0UL != (VSSEL135 & BIT_MASK_08))) { + TMR6_5_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.5 specified up compare match A*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMSAUF) && (0UL != (VSSEL135 & BIT_MASK_11))) { + TMR6_5_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.5 specified down compare match A*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMSADF) && (0UL != (VSSEL135 & BIT_MASK_11))) { + TMR6_5_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.5 specified up compare match B*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMSBUF) && (0UL != (VSSEL135 & BIT_MASK_12))) { + TMR6_5_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.5 specified down compare match B*/ + if (1UL == bCM_TMR6_5->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_5->STFLR_b.CMSBDF) && (0UL != (VSSEL135 & BIT_MASK_12))) { + TMR6_5_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.1 overflow */ + if (1UL == bCM_TMRA_1->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_1->BCSTR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_13))) { + TMRA_1_Ovf_IrqHandler(); + } + } + /* TimerA Ch.1 underflow */ + if (1UL == bCM_TMRA_1->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_1->BCSTR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_14))) { + TMRA_1_Udf_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 1 */ + if (1UL == bCM_TMRA_1->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_1->STFLR_b.CMPF1) && (0UL != (VSSEL135 & BIT_MASK_15))) { + TMRA_1_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 2 */ + if (1UL == bCM_TMRA_1->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_1->STFLR_b.CMPF2) && (0UL != (VSSEL135 & BIT_MASK_15))) { + TMRA_1_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 3 */ + if (1UL == bCM_TMRA_1->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_1->STFLR_b.CMPF3) && (0UL != (VSSEL135 & BIT_MASK_15))) { + TMRA_1_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 4 */ + if (1UL == bCM_TMRA_1->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_1->STFLR_b.CMPF4) && (0UL != (VSSEL135 & BIT_MASK_15))) { + TMRA_1_Cmp4_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match A */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMAF) && (0UL != (VSSEL135 & BIT_MASK_16))) { + TMR6_6_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match B */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMBF) && (0UL != (VSSEL135 & BIT_MASK_17))) { + TMR6_6_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match C */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMCF) && (0UL != (VSSEL135 & BIT_MASK_18))) { + TMR6_6_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match D */ + if (1UL == bCM_TMR6_6->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMDF) && (0UL != (VSSEL135 & BIT_MASK_19))) { + TMR6_6_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match E */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMEF) && (0UL != (VSSEL135 & BIT_MASK_20))) { + TMR6_6_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match F */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMFF) && (0UL != (VSSEL135 & BIT_MASK_21))) { + TMR6_6_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.6 overflow*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_6->STFLR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_22))) { + TMR6_6_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.6 underflow*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_6->STFLR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_23))) { + TMR6_6_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.6 dead time */ + if (1UL == bCM_TMR6_6->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_6->STFLR_b.DTEF) && (0UL != (VSSEL135 & BIT_MASK_24))) { + TMR6_6_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.6 specified up compare match A*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMSAUF) && (0UL != (VSSEL135 & BIT_MASK_27))) { + TMR6_6_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.6 specified down compare match A*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMSADF) && (0UL != (VSSEL135 & BIT_MASK_27))) { + TMR6_6_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.6 specified up compare match B*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMSBUF) && (0UL != (VSSEL135 & BIT_MASK_28))) { + TMR6_6_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.6 specified down compare match B*/ + if (1UL == bCM_TMR6_6->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_6->STFLR_b.CMSBDF) && (0UL != (VSSEL135 & BIT_MASK_28))) { + TMR6_6_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.2 overflow */ + if (1UL == bCM_TMRA_2->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_2->BCSTR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_29))) { + TMRA_2_Ovf_IrqHandler(); + } + } + /* TimerA Ch.2 underflow */ + if (1UL == bCM_TMRA_2->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_2->BCSTR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_30))) { + TMRA_2_Udf_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 1 */ + if (1UL == bCM_TMRA_2->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_2->STFLR_b.CMPF1) && (0UL != (VSSEL135 & BIT_MASK_31))) { + TMRA_2_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 2 */ + if (1UL == bCM_TMRA_2->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_2->STFLR_b.CMPF2) && (0UL != (VSSEL135 & BIT_MASK_31))) { + TMRA_2_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 3 */ + if (1UL == bCM_TMRA_2->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_2->STFLR_b.CMPF3) && (0UL != (VSSEL135 & BIT_MASK_31))) { + TMRA_2_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 4 */ + if (1UL == bCM_TMRA_2->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_2->STFLR_b.CMPF4) && (0UL != (VSSEL135 & BIT_MASK_31))) { + TMRA_2_Cmp4_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.136 share IRQ handler + * @param None + * @retval None + */ +void IRQ136_Handler(void) +{ + const uint32_t VSSEL136 = CM_INTC->VSSEL136; + + /* Timer6 Ch.7 general compare match A */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMAF) && (0UL != (VSSEL136 & BIT_MASK_00))) { + TMR6_7_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match B */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMBF) && (0UL != (VSSEL136 & BIT_MASK_01))) { + TMR6_7_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match C */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMCF) && (0UL != (VSSEL136 & BIT_MASK_02))) { + TMR6_7_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match D */ + if (1UL == bCM_TMR6_7->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMDF) && (0UL != (VSSEL136 & BIT_MASK_03))) { + TMR6_7_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match E */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMEF) && (0UL != (VSSEL136 & BIT_MASK_04))) { + TMR6_7_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match F */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMFF) && (0UL != (VSSEL136 & BIT_MASK_05))) { + TMR6_7_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.7 overflow*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_7->STFLR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_06))) { + TMR6_7_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.7 underflow*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_7->STFLR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_07))) { + TMR6_7_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.7 dead time */ + if (1UL == bCM_TMR6_7->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_7->STFLR_b.DTEF) && (0UL != (VSSEL136 & BIT_MASK_08))) { + TMR6_7_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.7 specified up compare match A*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMSAUF) && (0UL != (VSSEL136 & BIT_MASK_11))) { + TMR6_7_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.7 specified down compare match A*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMSADF) && (0UL != (VSSEL136 & BIT_MASK_11))) { + TMR6_7_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.7 specified up compare match B*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMSBUF) && (0UL != (VSSEL136 & BIT_MASK_12))) { + TMR6_7_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.7 specified down compare match B*/ + if (1UL == bCM_TMR6_7->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_7->STFLR_b.CMSBDF) && (0UL != (VSSEL136 & BIT_MASK_12))) { + TMR6_7_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.3 overflow */ + if (1UL == bCM_TMRA_3->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_3->BCSTR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_13))) { + TMRA_3_Ovf_IrqHandler(); + } + } + /* TimerA Ch.3 underflow */ + if (1UL == bCM_TMRA_3->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_3->BCSTR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_14))) { + TMRA_3_Udf_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 1 */ + if (1UL == bCM_TMRA_3->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_3->STFLR_b.CMPF1) && (0UL != (VSSEL136 & BIT_MASK_15))) { + TMRA_3_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 2 */ + if (1UL == bCM_TMRA_3->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_3->STFLR_b.CMPF2) && (0UL != (VSSEL136 & BIT_MASK_15))) { + TMRA_3_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 3 */ + if (1UL == bCM_TMRA_3->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_3->STFLR_b.CMPF3) && (0UL != (VSSEL136 & BIT_MASK_15))) { + TMRA_3_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 4 */ + if (1UL == bCM_TMRA_3->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_3->STFLR_b.CMPF4) && (0UL != (VSSEL136 & BIT_MASK_15))) { + TMRA_3_Cmp4_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match A */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMAF) && (0UL != (VSSEL136 & BIT_MASK_16))) { + TMR6_8_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match B */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMBF) && (0UL != (VSSEL136 & BIT_MASK_17))) { + TMR6_8_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match C */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMCF) && (0UL != (VSSEL136 & BIT_MASK_18))) { + TMR6_8_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match D */ + if (1UL == bCM_TMR6_8->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMDF) && (0UL != (VSSEL136 & BIT_MASK_19))) { + TMR6_8_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match E */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMEF) && (0UL != (VSSEL136 & BIT_MASK_20))) { + TMR6_8_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match F */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMFF) && (0UL != (VSSEL136 & BIT_MASK_21))) { + TMR6_8_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.8 overflow*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_8->STFLR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_22))) { + TMR6_8_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.8 underflow*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_8->STFLR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_23))) { + TMR6_8_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.8 dead time */ + if (1UL == bCM_TMR6_8->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_8->STFLR_b.DTEF) && (0UL != (VSSEL136 & BIT_MASK_24))) { + TMR6_8_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.8 specified up compare match A*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENSAU) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMSAUF) && (0UL != (VSSEL136 & BIT_MASK_27))) { + TMR6_8_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.8 specified down compare match A*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENSAD) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMSADF) && (0UL != (VSSEL136 & BIT_MASK_27))) { + TMR6_8_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.8 specified up compare match B*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENSBU) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMSBUF) && (0UL != (VSSEL136 & BIT_MASK_28))) { + TMR6_8_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.8 specified down compare match B*/ + if (1UL == bCM_TMR6_8->ICONR_b.INTENSBD) { + if ((1UL == bCM_TMR6_8->STFLR_b.CMSBDF) && (0UL != (VSSEL136 & BIT_MASK_28))) { + TMR6_8_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.4 overflow */ + if (1UL == bCM_TMRA_4->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_4->BCSTR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_29))) { + TMRA_4_Ovf_IrqHandler(); + } + } + /* TimerA Ch.4 underflow */ + if (1UL == bCM_TMRA_4->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_4->BCSTR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_30))) { + TMRA_4_Udf_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 1 */ + if (1UL == bCM_TMRA_4->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_4->STFLR_b.CMPF1) && (0UL != (VSSEL136 & BIT_MASK_31))) { + TMRA_4_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 2 */ + if (1UL == bCM_TMRA_4->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_4->STFLR_b.CMPF2) && (0UL != (VSSEL136 & BIT_MASK_31))) { + TMRA_4_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 3 */ + if (1UL == bCM_TMRA_4->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_4->STFLR_b.CMPF3) && (0UL != (VSSEL136 & BIT_MASK_31))) { + TMRA_4_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 4 */ + if (1UL == bCM_TMRA_4->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_4->STFLR_b.CMPF4) && (0UL != (VSSEL136 & BIT_MASK_31))) { + TMRA_4_Cmp4_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.137 share IRQ handler + * @param None + * @retval None + */ +void IRQ137_Handler(void) +{ + const uint32_t VSSEL137 = CM_INTC->VSSEL137; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* EMB0 */ + u32Tmp1 = CM_EMB0->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB0->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_00))) { + EMB_GR0_IrqHandler(); + } + /* EMB1 */ + u32Tmp1 = CM_EMB1->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB1->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_01))) { + EMB_GR1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = CM_EMB2->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB2->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_02))) { + EMB_GR2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = CM_EMB3->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB3->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_03))) { + EMB_GR3_IrqHandler(); + } + /* EMB4 */ + u32Tmp1 = CM_EMB4->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB4->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_04))) { + EMB_GR4_IrqHandler(); + } + /* EMB5 */ + u32Tmp1 = CM_EMB5->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB5->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_05))) { + EMB_GR5_IrqHandler(); + } + /* EMB6 */ + u32Tmp1 = CM_EMB6->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = CM_EMB6->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_06))) { + EMB_GR6_IrqHandler(); + } + /* USB HS EP1 out */ + + /* USB HS EP1 in */ + + /* USB HS global */ + + /* USB HS wakeup */ + + if (1UL == bCM_USART1->CR1_b.RIE) { + /* USART Ch.1 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART1->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_12))) { + USART1_RxError_IrqHandler(); + } + /* USART Ch.1 Rx end */ + if ((1UL == bCM_USART1->SR_b.RXNE) && (0UL != (VSSEL137 & BIT_MASK_13))) { + USART1_RxFull_IrqHandler(); + } + } + /* USART Ch.1 Tx buffer empty */ + if (1UL == bCM_USART1->CR1_b.TXEIE) { + if ((1UL == bCM_USART1->SR_b.TXE) && (0UL != (VSSEL137 & BIT_MASK_14))) { + USART1_TxEmpty_IrqHandler(); + } + } + /* USART Ch.1 Tx end */ + if (1UL == bCM_USART1->CR1_b.TCIE) { + if ((1UL == bCM_USART1->SR_b.TC) && (0UL != (VSSEL137 & BIT_MASK_15))) { + USART1_TxComplete_IrqHandler(); + } + } + /* USART Ch.1 Tx timeout */ + if (1UL == bCM_USART1->CR1_b.RTOIE) { + if ((1UL == bCM_USART1->SR_b.RTOF) && (0UL != (VSSEL137 & BIT_MASK_16))) { + USART1_RxTO_IrqHandler(); + } + } + if (1UL == bCM_USART2->CR1_b.RIE) { + /* USART Ch.2 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART2->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_17))) { + USART2_RxError_IrqHandler(); + } + /* USART Ch.2 Rx end */ + if ((1UL == bCM_USART2->SR_b.RXNE) && (0UL != (VSSEL137 & BIT_MASK_18))) { + USART2_RxFull_IrqHandler(); + } + } + /* USART Ch.2 Tx buffer empty */ + if (1UL == bCM_USART2->CR1_b.TXEIE) { + if ((1UL == bCM_USART2->SR_b.TXE) && (0UL != (VSSEL137 & BIT_MASK_19))) { + USART2_TxEmpty_IrqHandler(); + } + } + /* USART Ch.2 Tx end */ + if (1UL == bCM_USART2->CR1_b.TCIE) { + if ((1UL == bCM_USART2->SR_b.TC) && (0UL != (VSSEL137 & BIT_MASK_20))) { + USART2_TxComplete_IrqHandler(); + } + } + /* USART Ch.2 Tx timeout */ + if (1UL == bCM_USART2->CR1_b.RTOIE) { + if ((1UL == bCM_USART2->SR_b.RTOF) && (0UL != (VSSEL137 & BIT_MASK_21))) { + USART2_RxTO_IrqHandler(); + } + } + /* SPI Ch.1 Rx end */ + if (1UL == bCM_SPI1->CR1_b.RXIE) { + if ((1UL == bCM_SPI1->SR_b.RDFF) && (0UL != (VSSEL137 & BIT_MASK_22))) { + SPI1_RxFull_IrqHandler(); + } + } + /* SPI Ch.1 Tx buffer empty */ + if (1UL == bCM_SPI1->CR1_b.TXIE) { + if ((1UL == bCM_SPI1->SR_b.TDEF) && (0UL != (VSSEL137 & BIT_MASK_23))) { + SPI1_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.1 Bus idle */ + if (1UL == bCM_SPI1->CR1_b.IDIE) { + if ((0UL == bCM_SPI1->SR_b.IDLNF) && (0UL != (VSSEL137 & BIT_MASK_24))) { + SPI1_Idle_IrqHandler(); + } + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI1->CR1_b.EIE) { + u32Tmp1 = CM_SPI1->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_25))) { + SPI1_Error_IrqHandler(); + } + } + /* SPI Ch.2 Rx end */ + if (1UL == bCM_SPI2->CR1_b.RXIE) { + if ((1UL == bCM_SPI2->SR_b.RDFF) && (0UL != (VSSEL137 & BIT_MASK_27))) { + SPI2_RxFull_IrqHandler(); + } + } + /* SPI Ch.2 Tx buffer empty */ + if (1UL == bCM_SPI2->CR1_b.TXIE) { + if ((1UL == bCM_SPI2->SR_b.TDEF) && (0UL != (VSSEL137 & BIT_MASK_28))) { + SPI2_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.2 Bus idle */ + if (1UL == bCM_SPI2->CR1_b.IDIE) { + if ((0UL == bCM_SPI2->SR_b.IDLNF) && (0UL != (VSSEL137 & BIT_MASK_29))) { + SPI2_Idle_IrqHandler(); + } + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI2->CR1_b.EIE) { + u32Tmp1 = CM_SPI2->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_30))) { + SPI2_Error_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.138 share IRQ handler + * @param None + * @retval None + */ +void IRQ138_Handler(void) +{ + const uint32_t VSSEL138 = CM_INTC->VSSEL138; + uint32_t u32Tmp1; + uint8_t RTIF; + uint8_t RTIE; + uint8_t ERRINT; + uint8_t TTCFG; + + /* TimerA Ch.5 overflow */ + if (1UL == bCM_TMRA_5->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_5->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_00))) { + TMRA_5_Ovf_IrqHandler(); + } + } + /* TimerA Ch.5 underflow */ + if (1UL == bCM_TMRA_5->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_5->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_01))) { + TMRA_5_Udf_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 1 */ + if (1UL == bCM_TMRA_5->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_5->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_02))) { + TMRA_5_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 2 */ + if (1UL == bCM_TMRA_5->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_5->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_02))) { + TMRA_5_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 3 */ + if (1UL == bCM_TMRA_5->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_5->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_02))) { + TMRA_5_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 4 */ + if (1UL == bCM_TMRA_5->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_5->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_02))) { + TMRA_5_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.6 overflow */ + if (1UL == bCM_TMRA_6->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_6->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_03))) { + TMRA_6_Ovf_IrqHandler(); + } + } + /* TimerA Ch.6 underflow */ + if (1UL == bCM_TMRA_6->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_6->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_04))) { + TMRA_6_Udf_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 1 */ + if (1UL == bCM_TMRA_6->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_6->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_05))) { + TMRA_6_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 2 */ + if (1UL == bCM_TMRA_6->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_6->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_05))) { + TMRA_6_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 3 */ + if (1UL == bCM_TMRA_6->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_6->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_05))) { + TMRA_6_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 4 */ + if (1UL == bCM_TMRA_6->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_6->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_05))) { + TMRA_6_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.7 overflow */ + if (1UL == bCM_TMRA_7->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_7->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_06))) { + TMRA_7_Ovf_IrqHandler(); + } + } + /* TimerA Ch.7 underflow */ + if (1UL == bCM_TMRA_7->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_7->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_07))) { + TMRA_7_Udf_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 1 */ + if (1UL == bCM_TMRA_7->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_7->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_08))) { + TMRA_7_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 2 */ + if (1UL == bCM_TMRA_7->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_7->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_08))) { + TMRA_7_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 3 */ + if (1UL == bCM_TMRA_7->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_7->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_08))) { + TMRA_7_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 4 */ + if (1UL == bCM_TMRA_7->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_7->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_08))) { + TMRA_7_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.8 overflow */ + if (1UL == bCM_TMRA_8->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_8->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_09))) { + TMRA_8_Ovf_IrqHandler(); + } + } + /* TimerA Ch.8 underflow */ + if (1UL == bCM_TMRA_8->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_8->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_10))) { + TMRA_8_Udf_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 1 */ + if (1UL == bCM_TMRA_8->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_8->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_11))) { + TMRA_8_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 2 */ + if (1UL == bCM_TMRA_8->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_8->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_11))) { + TMRA_8_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 3 */ + if (1UL == bCM_TMRA_8->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_8->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_11))) { + TMRA_8_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 4 */ + if (1UL == bCM_TMRA_8->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_8->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_11))) { + TMRA_8_Cmp4_IrqHandler(); + } + } + if (1UL == bCM_USART3->CR1_b.RIE) { + /* USART Ch.3 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART3->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_12))) { + USART3_RxError_IrqHandler(); + } + /* USART Ch.3 Rx end */ + if ((1UL == bCM_USART3->SR_b.RXNE) && (0UL != (VSSEL138 & BIT_MASK_13))) { + USART3_RxFull_IrqHandler(); + } + } + /* USART Ch.3 Tx buffer empty */ + if (1UL == bCM_USART3->CR1_b.TXEIE) { + if ((1UL == bCM_USART3->SR_b.TXE) && (0UL != (VSSEL138 & BIT_MASK_14))) { + USART3_TxEmpty_IrqHandler(); + } + } + /* USART Ch.3 Tx end */ + if (1UL == bCM_USART3->CR1_b.TCIE) { + if ((1UL == bCM_USART3->SR_b.TC) && (0UL != (VSSEL138 & BIT_MASK_15))) { + USART3_TxComplete_IrqHandler(); + } + } + if (1UL == bCM_USART4->CR1_b.RIE) { + /* USART Ch.4 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART4->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_16))) { + USART4_RxError_IrqHandler(); + } + /* USART Ch.4 Rx end */ + if ((1UL == bCM_USART4->SR_b.RXNE) && (0UL != (VSSEL138 & BIT_MASK_17))) { + USART4_RxFull_IrqHandler(); + } + } + /* USART Ch.4 Tx buffer empty */ + if (1UL == bCM_USART4->CR1_b.TXEIE) { + if ((1UL == bCM_USART4->SR_b.TXE) && (0UL != (VSSEL138 & BIT_MASK_18))) { + USART4_TxEmpty_IrqHandler(); + } + } + /* USART Ch.4 Tx end */ + if (1UL == bCM_USART4->CR1_b.TCIE) { + if ((1UL == bCM_USART4->SR_b.TC) && (0UL != (VSSEL138 & BIT_MASK_19))) { + USART4_TxComplete_IrqHandler(); + } + } + /* CAN Ch.1 */ + if (0UL != (VSSEL138 & BIT_MASK_20)) { + RTIF = CM_CAN1->RTIF; + RTIE = CM_CAN1->RTIE; + ERRINT = CM_CAN1->ERRINT; + TTCFG = CM_CAN1->TTCFG; + if ((0U != (TTCFG & CAN_TTCFG_TEIF)) || \ + (0U != (RTIF & CAN_RTIF_AIF)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & CAN_ERRINT_BEIE)) && \ + (0U != (ERRINT & CAN_ERRINT_BEIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_ALIE)) && \ + (0U != (ERRINT & CAN_ERRINT_ALIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_EPIE)) && \ + (0U != (ERRINT & CAN_ERRINT_EPIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_TTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_TTIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_WTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_WTIF)))) { + CAN1_IrqHandler(); + } + } + /* CAN Ch.2 */ + if (0UL != (VSSEL138 & BIT_MASK_21)) { + RTIF = CM_CAN2->RTIF; + RTIE = CM_CAN2->RTIE; + ERRINT = CM_CAN2->ERRINT; + TTCFG = CM_CAN2->TTCFG; + if ((0U != (TTCFG & CAN_TTCFG_TEIF)) || \ + (0U != (RTIF & CAN_RTIF_AIF)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & CAN_ERRINT_BEIE)) && \ + (0U != (ERRINT & CAN_ERRINT_BEIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_ALIE)) && \ + (0U != (ERRINT & CAN_ERRINT_ALIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_EPIE)) && \ + (0U != (ERRINT & CAN_ERRINT_EPIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_TTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_TTIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_WTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_WTIF)))) { + CAN2_IrqHandler(); + } + } + /* SPI Ch.3 Rx end */ + if (1UL == bCM_SPI3->CR1_b.RXIE) { + if ((1UL == bCM_SPI3->SR_b.RDFF) && (0UL != (VSSEL138 & BIT_MASK_22))) { + SPI3_RxFull_IrqHandler(); + } + } + /* SPI Ch.3 Tx buffer empty */ + if (1UL == bCM_SPI3->CR1_b.TXIE) { + if ((1UL == bCM_SPI3->SR_b.TDEF) && (0UL != (VSSEL138 & BIT_MASK_23))) { + SPI3_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.3 Bus idle */ + if (1UL == bCM_SPI3->CR1_b.IDIE) { + if ((0UL == bCM_SPI3->SR_b.IDLNF) && (0UL != (VSSEL138 & BIT_MASK_24))) { + SPI3_Idle_IrqHandler(); + } + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI3->CR1_b.EIE) { + u32Tmp1 = CM_SPI3->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_25))) { + SPI3_Error_IrqHandler(); + } + } + /* SPI Ch.4 Rx end */ + if (1UL == bCM_SPI4->CR1_b.RXIE) { + if ((1UL == bCM_SPI4->SR_b.RDFF) && (0UL != (VSSEL138 & BIT_MASK_27))) { + SPI4_RxFull_IrqHandler(); + } + } + /* SPI Ch.4 Tx buffer empty */ + if (1UL == bCM_SPI4->CR1_b.TXIE) { + if ((1UL == bCM_SPI4->SR_b.TDEF) && (0UL != (VSSEL138 & BIT_MASK_28))) { + SPI4_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.4 Bus idle */ + if (1UL == bCM_SPI4->CR1_b.IDIE) { + if ((0UL == bCM_SPI4->SR_b.IDLNF) && (0UL != (VSSEL138 & BIT_MASK_29))) { + SPI4_Idle_IrqHandler(); + } + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI4->CR1_b.EIE) { + u32Tmp1 = CM_SPI4->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_30))) { + SPI4_Error_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.139 share IRQ handler + * @param None + * @retval None + */ +void IRQ139_Handler(void) +{ + const uint32_t VSSEL139 = CM_INTC->VSSEL139; + uint32_t u32Tmp1; + + /* TimerA Ch.9 overflow */ + if (1UL == bCM_TMRA_9->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_9->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_00))) { + TMRA_9_Ovf_IrqHandler(); + } + } + /* TimerA Ch.9 underflow */ + if (1UL == bCM_TMRA_9->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_9->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_01))) { + TMRA_9_Udf_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 1 */ + if (1UL == bCM_TMRA_9->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_9->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_02))) { + TMRA_9_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 2 */ + if (1UL == bCM_TMRA_9->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_9->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_02))) { + TMRA_9_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 3 */ + if (1UL == bCM_TMRA_9->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_9->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_02))) { + TMRA_9_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 4 */ + if (1UL == bCM_TMRA_9->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_9->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_02))) { + TMRA_9_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.10 overflow */ + if (1UL == bCM_TMRA_10->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_10->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_03))) { + TMRA_10_Ovf_IrqHandler(); + } + } + /* TimerA Ch.10 underflow */ + if (1UL == bCM_TMRA_10->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_10->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_04))) { + TMRA_10_Udf_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 1 */ + if (1UL == bCM_TMRA_10->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_10->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_05))) { + TMRA_10_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 2 */ + if (1UL == bCM_TMRA_10->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_10->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_05))) { + TMRA_10_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 3 */ + if (1UL == bCM_TMRA_10->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_10->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_05))) { + TMRA_10_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 4 */ + if (1UL == bCM_TMRA_10->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_10->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_05))) { + TMRA_10_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.11 overflow */ + if (1UL == bCM_TMRA_11->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_11->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_06))) { + TMRA_11_Ovf_IrqHandler(); + } + } + /* TimerA Ch.11 underflow */ + if (1UL == bCM_TMRA_11->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_11->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_07))) { + TMRA_11_Udf_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 1 */ + if (1UL == bCM_TMRA_11->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_11->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_08))) { + TMRA_11_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 2 */ + if (1UL == bCM_TMRA_11->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_11->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_08))) { + TMRA_11_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 3 */ + if (1UL == bCM_TMRA_11->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_11->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_08))) { + TMRA_11_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 4 */ + if (1UL == bCM_TMRA_11->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_11->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_08))) { + TMRA_11_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.12 overflow */ + if (1UL == bCM_TMRA_12->BCSTR_b.ITENOVF) { + if ((1UL == bCM_TMRA_12->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_09))) { + TMRA_12_Ovf_IrqHandler(); + } + } + /* TimerA Ch.12 underflow */ + if (1UL == bCM_TMRA_12->BCSTR_b.ITENUDF) { + if ((1UL == bCM_TMRA_12->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_10))) { + TMRA_12_Udf_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 1 */ + if (1UL == bCM_TMRA_12->ICONR_b.ITEN1) { + if ((1UL == bCM_TMRA_12->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_11))) { + TMRA_12_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 2 */ + if (1UL == bCM_TMRA_12->ICONR_b.ITEN2) { + if ((1UL == bCM_TMRA_12->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_11))) { + TMRA_12_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 3 */ + if (1UL == bCM_TMRA_12->ICONR_b.ITEN3) { + if ((1UL == bCM_TMRA_12->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_11))) { + TMRA_12_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 4 */ + if (1UL == bCM_TMRA_12->ICONR_b.ITEN4) { + if ((1UL == bCM_TMRA_12->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_11))) { + TMRA_12_Cmp4_IrqHandler(); + } + } + /* USART Ch.5 LIN bus break */ + if (1UL == bCM_USART5->CR2_b.LBDIE) { + if ((1UL == bCM_USART5->SR_b.LBD) && (0UL != (VSSEL139 & BIT_MASK_12))) { + USART5_LinBreakField_IrqHandler(); + } + } + /* USART Ch.5 LIN bus wakeup */ + if (1UL == bCM_USART5->CR2_b.WKUPE) { + if ((1UL == bCM_USART5->SR_b.WKUP) && (0UL != (VSSEL139 & BIT_MASK_12))) { + USART5_LinWakeup_IrqHandler(); + } + } + if (1UL == bCM_USART5->CR1_b.RIE) { + /* USART Ch.5 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART5->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_13))) { + USART5_RxError_IrqHandler(); + } + /* USART Ch.5 Rx end */ + if ((1UL == bCM_USART5->SR_b.RXNE) && (0UL != (VSSEL139 & BIT_MASK_14))) { + USART5_RxFull_IrqHandler(); + } + } + /* USART Ch.5 Tx buffer empty */ + if (1UL == bCM_USART5->CR1_b.TXEIE) { + if ((1UL == bCM_USART5->SR_b.TXE) && (0UL != (VSSEL139 & BIT_MASK_15))) { + USART5_TxEmpty_IrqHandler(); + } + } + /* USART Ch.5 Tx end */ + if (1UL == bCM_USART5->CR1_b.TCIE) { + if ((1UL == bCM_USART5->SR_b.TC) && (0UL != (VSSEL139 & BIT_MASK_16))) { + USART5_TxComplete_IrqHandler(); + } + } + if (1UL == bCM_USART6->CR1_b.RIE) { + /* USART Ch.6 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART6->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_17))) { + USART6_RxError_IrqHandler(); + } + /* USART Ch.6 Rx end */ + if ((1UL == bCM_USART6->SR_b.RXNE) && (0UL != (VSSEL139 & BIT_MASK_18))) { + USART6_RxFull_IrqHandler(); + } + } + /* USART Ch.6 Tx buffer empty */ + if (1UL == bCM_USART6->CR1_b.TXEIE) { + if ((1UL == bCM_USART6->SR_b.TXE) && (0UL != (VSSEL139 & BIT_MASK_19))) { + USART6_TxEmpty_IrqHandler(); + } + } + /* USART Ch.6 Tx end */ + if (1UL == bCM_USART6->CR1_b.TCIE) { + if ((1UL == bCM_USART6->SR_b.TC) && (0UL != (VSSEL139 & BIT_MASK_20))) { + USART6_TxComplete_IrqHandler(); + } + } + /* USART Ch.6 Tx timeout */ + if (1UL == bCM_USART6->CR1_b.RTOIE) { + if ((1UL == bCM_USART6->SR_b.RTOF) && (0UL != (VSSEL139 & BIT_MASK_21))) { + USART6_RxTO_IrqHandler(); + } + } + /* SPI Ch.5 Rx end */ + if (1UL == bCM_SPI5->CR1_b.RXIE) { + if ((1UL == bCM_SPI5->SR_b.RDFF) && (0UL != (VSSEL139 & BIT_MASK_22))) { + SPI5_RxFull_IrqHandler(); + } + } + /* SPI Ch.5 Tx buffer empty */ + if (1UL == bCM_SPI5->CR1_b.TXIE) { + if ((1UL == bCM_SPI5->SR_b.TDEF) && (0UL != (VSSEL139 & BIT_MASK_23))) { + SPI5_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.5 Bus idle */ + if (1UL == bCM_SPI5->CR1_b.IDIE) { + if ((0UL == bCM_SPI5->SR_b.IDLNF) && (0UL != (VSSEL139 & BIT_MASK_24))) { + SPI5_Idle_IrqHandler(); + } + } + /* SPI Ch.5 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI5->CR1_b.EIE) { + u32Tmp1 = CM_SPI5->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_25))) { + SPI5_Error_IrqHandler(); + } + } + /* SPI Ch.6 Rx end */ + if (1UL == bCM_SPI6->CR1_b.RXIE) { + if ((1UL == bCM_SPI6->SR_b.RDFF) && (0UL != (VSSEL139 & BIT_MASK_27))) { + SPI6_RxFull_IrqHandler(); + } + } + /* SPI Ch.6 Tx buffer empty */ + if (1UL == bCM_SPI6->CR1_b.TXIE) { + if ((1UL == bCM_SPI6->SR_b.TDEF) && (0UL != (VSSEL139 & BIT_MASK_28))) { + SPI6_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.6 Bus idle */ + if (1UL == bCM_SPI6->CR1_b.IDIE) { + if ((0UL == bCM_SPI6->SR_b.IDLNF) && (0UL != (VSSEL139 & BIT_MASK_29))) { + SPI6_Idle_IrqHandler(); + } + } + /* SPI Ch.6 parity/overflow/underflow/mode error */ + if (1UL == bCM_SPI6->CR1_b.EIE) { + u32Tmp1 = CM_SPI6->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_30))) { + SPI6_Error_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.140 share IRQ handler + * @param None + * @retval None + */ +void IRQ140_Handler(void) +{ + const uint32_t VSSEL140 = CM_INTC->VSSEL140; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + uint16_t NORINTST; + uint16_t NORINTSGEN; + uint16_t ERRINTSGEN; + uint32_t MMC_REVSTSR; + uint32_t MMC_TRSSTSR; + uint32_t MMC_RITCTLR; + uint32_t MMC_TITCTLR; + uint32_t DMA_DMASTSR; + uint32_t DMA_INTENAR; + uint32_t PTP_INTE; + uint32_t PMT_INTMASK; + uint32_t PMT_INTSTSR; + uint32_t PTP_INTMASK; + uint32_t PTP_INTSTSR; + + /* I2S Ch.1 Tx */ + if (1UL == bCM_I2S1->CTRL_b.TXIE) { + if ((1UL == bCM_I2S1->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_00))) { + I2S1_Tx_IrqHandler(); + } + } + /* I2S Ch.1 Rx */ + if (1UL == bCM_I2S1->CTRL_b.RXIE) { + if ((1UL == bCM_I2S1->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_01))) { + I2S1_Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if (1UL == bCM_I2S1->CTRL_b.EIE) { + u32Tmp1 = CM_I2S1->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_02))) { + I2S1_Error_IrqHandler(); + } + } + /* I2S Ch.2 Tx */ + if (1UL == bCM_I2S2->CTRL_b.TXIE) { + if ((1UL == bCM_I2S2->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_03))) { + I2S2_Tx_IrqHandler(); + } + } + /* I2S Ch.2 Rx */ + if (1UL == bCM_I2S2->CTRL_b.RXIE) { + if ((1UL == bCM_I2S2->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_04))) { + I2S2_Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if (1UL == bCM_I2S2->CTRL_b.EIE) { + u32Tmp1 = CM_I2S2->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_05))) { + I2S2_Error_IrqHandler(); + } + } + if (1UL == bCM_USART7->CR1_b.RIE) { + /* USART Ch.7 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART7->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_06))) { + USART7_RxError_IrqHandler(); + } + /* USART Ch.7 Rx end */ + if ((1UL == bCM_USART7->SR_b.RXNE) && (0UL != (VSSEL140 & BIT_MASK_07))) { + USART7_RxFull_IrqHandler(); + } + } + /* USART Ch.7 Tx buffer empty */ + if (1UL == bCM_USART7->CR1_b.TXEIE) { + if ((1UL == bCM_USART7->SR_b.TXE) && (0UL != (VSSEL140 & BIT_MASK_08))) { + USART7_TxEmpty_IrqHandler(); + } + } + /* USART Ch.7 Tx end */ + if (1UL == bCM_USART7->CR1_b.TCIE) { + if ((1UL == bCM_USART7->SR_b.TC) && (0UL != (VSSEL140 & BIT_MASK_09))) { + USART7_TxComplete_IrqHandler(); + } + } + /* USART Ch.7 Tx timeout */ + if (1UL == bCM_USART7->CR1_b.RTOIE) { + if ((1UL == bCM_USART7->SR_b.RTOF) && (0UL != (VSSEL140 & BIT_MASK_10))) { + USART7_RxTO_IrqHandler(); + } + } + if (1UL == bCM_USART8->CR1_b.RIE) { + /* USART Ch.8 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART8->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_11))) { + USART8_RxError_IrqHandler(); + } + /* USART Ch.8 Rx end */ + if ((1UL == bCM_USART8->SR_b.RXNE) && (0UL != (VSSEL140 & BIT_MASK_12))) { + USART8_RxFull_IrqHandler(); + } + } + /* USART Ch.8 Tx buffer empty */ + if (1UL == bCM_USART8->CR1_b.TXEIE) { + if ((1UL == bCM_USART8->SR_b.TXE) && (0UL != (VSSEL140 & BIT_MASK_13))) { + USART8_TxEmpty_IrqHandler(); + } + } + /* USART Ch.8 Tx end */ + if (1UL == bCM_USART8->CR1_b.TCIE) { + if ((1UL == bCM_USART8->SR_b.TC) && (0UL != (VSSEL140 & BIT_MASK_14))) { + USART8_TxComplete_IrqHandler(); + } + } + /* USB FS global interrupt */ + if (1UL == bCM_USBFS->GAHBCFG_b.GINTMSK) { + u32Tmp1 = CM_USBFS->GINTMSK & 0xF77CFCFBUL; + u32Tmp2 = CM_USBFS->GINTSTS & 0xF77CFCFBUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_15))) { + USBFS_Global_IrqHandler(); + } + } + /* SDIO unit 1 */ + if (0UL != (VSSEL140 & BIT_MASK_20)) { + NORINTST = CM_SDIOC1->NORINTST & (SDIOC_NORINTST_CINT | SDIOC_NORINTST_CRM | SDIOC_NORINTST_CIST | \ + SDIOC_NORINTST_BRR | SDIOC_NORINTST_BWR | SDIOC_NORINTST_BGE | \ + SDIOC_NORINTST_TC | SDIOC_NORINTST_CC); + NORINTSGEN = CM_SDIOC1->NORINTSGEN & (SDIOC_NORINTSTEN_CINTEN | SDIOC_NORINTSTEN_CRMEN | \ + SDIOC_NORINTSTEN_CISTEN | SDIOC_NORINTSTEN_BRREN | \ + SDIOC_NORINTSTEN_BWREN | SDIOC_NORINTSTEN_BGEEN | \ + SDIOC_NORINTSTEN_TCEN | SDIOC_NORINTSTEN_CCEN); + ERRINTSGEN = CM_SDIOC1->ERRINTSGEN & (SDIOC_ERRINTSTEN_ACEEN | SDIOC_ERRINTSTEN_DEBEEN | \ + SDIOC_ERRINTSTEN_DCEEN | SDIOC_ERRINTSTEN_DTOEEN | \ + SDIOC_ERRINTSTEN_CIEEN | SDIOC_ERRINTSTEN_CEBEEN | \ + SDIOC_ERRINTSTEN_CCEEN | SDIOC_ERRINTSTEN_CTOEEN); + if (0U != (NORINTST & NORINTSGEN)) { + SDIOC1_Normal_IrqHandler(); + } + if ((1UL == bCM_SDIOC1->NORINTST_b.EI) && (0U != ERRINTSGEN)) { + SDIOC1_Error_IrqHandler(); + } + } + /* SDIO unit 2 */ + if (0UL != (VSSEL140 & BIT_MASK_23)) { + NORINTST = CM_SDIOC2->NORINTST & (SDIOC_NORINTST_CINT | SDIOC_NORINTST_CRM | SDIOC_NORINTST_CIST | \ + SDIOC_NORINTST_BRR | SDIOC_NORINTST_BWR | SDIOC_NORINTST_BGE | \ + SDIOC_NORINTST_TC | SDIOC_NORINTST_CC); + NORINTSGEN = CM_SDIOC2->NORINTSGEN & (SDIOC_NORINTSTEN_CINTEN | SDIOC_NORINTSTEN_CRMEN | \ + SDIOC_NORINTSTEN_CISTEN | SDIOC_NORINTSTEN_BRREN | \ + SDIOC_NORINTSTEN_BWREN | SDIOC_NORINTSTEN_BGEEN | \ + SDIOC_NORINTSTEN_TCEN | SDIOC_NORINTSTEN_CCEN); + ERRINTSGEN = CM_SDIOC2->ERRINTSGEN & (SDIOC_ERRINTSTEN_ACEEN | SDIOC_ERRINTSTEN_DEBEEN | \ + SDIOC_ERRINTSTEN_DCEEN | SDIOC_ERRINTSTEN_DTOEEN | \ + SDIOC_ERRINTSTEN_CIEEN | SDIOC_ERRINTSTEN_CEBEEN | \ + SDIOC_ERRINTSTEN_CCEEN | SDIOC_ERRINTSTEN_CTOEEN); + if (0U != (NORINTST & NORINTSGEN)) { + SDIOC2_Normal_IrqHandler(); + } + if ((1UL == bCM_SDIOC2->NORINTST_b.EI) && (0U != ERRINTSGEN)) { + SDIOC2_Error_IrqHandler(); + } + } + /* Ethernat global */ + MMC_REVSTSR = CM_ETH->MMC_REVSTSR & (ETH_MMC_REVSTSR_RXOEIS | ETH_MMC_REVSTSR_RXLEIS | \ + ETH_MMC_REVSTSR_RXUGIS | ETH_MMC_REVSTSR_RXREIS | \ + ETH_MMC_REVSTSR_RXAEIS | ETH_MMC_REVSTSR_RXCEIS | \ + ETH_MMC_REVSTSR_RXMGIS | ETH_MMC_REVSTSR_RXBGIS); + MMC_TRSSTSR = CM_ETH->MMC_TRSSTSR & (ETH_MMC_TRSSTSR_TXEDEIS | ETH_MMC_TRSSTSR_TXUGIS | \ + ETH_MMC_TRSSTSR_TXCAEIS | ETH_MMC_TRSSTSR_TXECEIS | \ + ETH_MMC_TRSSTSR_TXLCEIS | ETH_MMC_TRSSTSR_TXDEEIS | \ + ETH_MMC_TRSSTSR_TXMGIS | ETH_MMC_TRSSTSR_TXBGIS); + MMC_RITCTLR = CM_ETH->MMC_RITCTLR & (ETH_MMC_RITCTLR_RXBGIM | ETH_MMC_RITCTLR_RXMGIM | \ + ETH_MMC_RITCTLR_RXCEIM | ETH_MMC_RITCTLR_RXAEIM | \ + ETH_MMC_RITCTLR_RXREIM | ETH_MMC_RITCTLR_RXUGIM | \ + ETH_MMC_RITCTLR_RXLEIM | ETH_MMC_RITCTLR_RXOEIM); + MMC_TITCTLR = CM_ETH->MMC_TITCTLR & (ETH_MMC_TITCTLR_TXBGIM | ETH_MMC_TITCTLR_TXMGIM | \ + ETH_MMC_TITCTLR_TXDEEIM | ETH_MMC_TITCTLR_TXLCEIM | \ + ETH_MMC_TITCTLR_TXECEIM | ETH_MMC_TITCTLR_TXCAEIM | \ + ETH_MMC_TITCTLR_TXUGIM | ETH_MMC_TITCTLR_TXEDEIM); + PMT_INTMASK = bCM_ETH->MAC_INTMSKR_b.PMTIM; + PMT_INTSTSR = bCM_ETH->MAC_INTSTSR_b.PMTIS; + PTP_INTMASK = bCM_ETH->MAC_INTMSKR_b.TSPIM; + PTP_INTSTSR = bCM_ETH->MAC_INTSTSR_b.TSPIS; + PTP_INTE = bCM_ETH->PTP_TSPCTLR_b.TSPINT; + + DMA_DMASTSR = CM_ETH->DMA_DMASTSR & (ETH_DMA_DMASTSR_AIS | ETH_DMA_DMASTSR_NIS); + DMA_INTENAR = CM_ETH->DMA_INTENAR & (ETH_DMA_INTENAR_AIE | ETH_DMA_INTENAR_NIE); + if (0UL != (VSSEL140 & BIT_MASK_28)) { + if ((0UL != (MMC_REVSTSR & (~MMC_RITCTLR))) || \ + (0UL != (MMC_TRSSTSR & (~MMC_TITCTLR))) || \ + (0UL != (PMT_INTSTSR & (~PMT_INTMASK))) || \ + (0UL != (PTP_INTSTSR & (~PTP_INTMASK) & PTP_INTE)) || \ + (0UL != (DMA_DMASTSR & DMA_INTENAR))) { + ETH_Global_IrqHandler(); + } + } + + /* Ethernat wakeup */ + if (0UL == bCM_ETH->MAC_INTMSKR_b.PMTIM) { + if ((1UL == bCM_ETH->MAC_INTSTSR_b.PMTIS) && (0UL != (VSSEL140 & BIT_MASK_29))) { + ETH_Wakeup_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.141 share IRQ handler + * @param None + * @retval None + */ +void IRQ141_Handler(void) +{ + const uint32_t VSSEL141 = CM_INTC->VSSEL141; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* I2S Ch.3 Tx */ + if (1UL == bCM_I2S3->CTRL_b.TXIE) { + if ((1UL == bCM_I2S3->SR_b.TXBA) && (0UL != (VSSEL141 & BIT_MASK_00))) { + I2S3_Tx_IrqHandler(); + } + } + /* I2S Ch.3 Rx */ + if (1UL == bCM_I2S3->CTRL_b.RXIE) { + if ((1UL == bCM_I2S3->SR_b.RXBA) && (0UL != (VSSEL141 & BIT_MASK_01))) { + I2S3_Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if (1UL == bCM_I2S3->CTRL_b.EIE) { + u32Tmp1 = CM_I2S3->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_02))) { + I2S3_Error_IrqHandler(); + } + } + /* I2S Ch.4 Tx */ + if (1UL == bCM_I2S4->CTRL_b.TXIE) { + if ((1UL == bCM_I2S4->SR_b.TXBA) && (0UL != (VSSEL141 & BIT_MASK_03))) { + I2S4_Tx_IrqHandler(); + } + } + /* I2S Ch.4 Rx */ + if (1UL == bCM_I2S4->CTRL_b.RXIE) { + if ((1UL == bCM_I2S4->SR_b.RXBA) && (0UL != (VSSEL141 & BIT_MASK_04))) { + I2S4_Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if (1UL == bCM_I2S4->CTRL_b.EIE) { + u32Tmp1 = CM_I2S4->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_05))) { + I2S4_Error_IrqHandler(); + } + } + if (1UL == bCM_USART9->CR1_b.RIE) { + /* USART Ch.9 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART9->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_06))) { + USART9_RxError_IrqHandler(); + } + /* USART Ch.9 Rx end */ + if ((1UL == bCM_USART9->SR_b.RXNE) && (0UL != (VSSEL141 & BIT_MASK_07))) { + USART9_RxFull_IrqHandler(); + } + } + /* USART Ch.9 Tx buffer empty */ + if (1UL == bCM_USART9->CR1_b.TXEIE) { + if ((1UL == bCM_USART9->SR_b.TXE) && (0UL != (VSSEL141 & BIT_MASK_08))) { + USART9_TxEmpty_IrqHandler(); + } + } + /* USART Ch.9 Tx end */ + if (1UL == bCM_USART9->CR1_b.TCIE) { + if ((1UL == bCM_USART9->SR_b.TC) && (0UL != (VSSEL141 & BIT_MASK_09))) { + USART9_TxComplete_IrqHandler(); + } + } + /* USART Ch.10 LIN bus break */ + if (1UL == bCM_USART10->CR2_b.LBDIE) { + if ((1UL == bCM_USART10->SR_b.LBD) && (0UL != (VSSEL141 & BIT_MASK_10))) { + USART10_LinBreakField_IrqHandler(); + } + } + /* USART Ch.10 LIN bus wakeup */ + if (1UL == bCM_USART10->CR2_b.WKUPE) { + if ((1UL == bCM_USART10->SR_b.WKUP) && (0UL != (VSSEL141 & BIT_MASK_10))) { + USART10_LinWakeup_IrqHandler(); + } + } + if (1UL == bCM_USART10->CR1_b.RIE) { + /* USART Ch.10 Rx ORE/FE/PE error */ + u32Tmp1 = CM_USART10->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_11))) { + USART10_RxError_IrqHandler(); + } + /* USART Ch.10 Rx end */ + if ((1UL == bCM_USART10->SR_b.RXNE) && (0UL != (VSSEL141 & BIT_MASK_12))) { + USART10_RxFull_IrqHandler(); + } + } + /* USART Ch.10 Tx buffer empty */ + if (1UL == bCM_USART10->CR1_b.TXEIE) { + if ((1UL == bCM_USART10->SR_b.TXE) && (0UL != (VSSEL141 & BIT_MASK_13))) { + USART10_TxEmpty_IrqHandler(); + } + } + /* USART Ch.10 Tx end */ + if (1UL == bCM_USART10->CR1_b.TCIE) { + if ((1UL == bCM_USART10->SR_b.TC) && (0UL != (VSSEL141 & BIT_MASK_14))) { + USART10_TxComplete_IrqHandler(); + } + } + /* I2C Ch.1 Rx end */ + if (1UL == bCM_I2C1->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C1->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_16))) { + I2C1_RxFull_IrqHandler(); + } + } + /* I2C Ch.1 Tx buffer empty */ + if (1UL == bCM_I2C1->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C1->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_17))) { + I2C1_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Tx end */ + if (1UL == bCM_I2C1->CR2_b.TENDIE) { + if ((1UL == bCM_I2C1->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_18))) { + I2C1_TxComplete_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = CM_I2C1->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C1->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_19))) { + I2C1_Error_IrqHandler(); + } + /* I2C Ch.2 Rx end */ + if (1UL == bCM_I2C2->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C2->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_20))) { + I2C2_RxFull_IrqHandler(); + } + } + /* I2C Ch.2 Tx buffer empty */ + if (1UL == bCM_I2C2->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C2->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_21))) { + I2C2_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Tx end */ + if (1UL == bCM_I2C2->CR2_b.TENDIE) { + if ((1UL == bCM_I2C2->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_22))) { + I2C2_TxComplete_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = CM_I2C2->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C2->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_23))) { + I2C2_Error_IrqHandler(); + } + /* I2C Ch.3 Rx end */ + if (1UL == bCM_I2C3->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C3->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_24))) { + I2C3_RxFull_IrqHandler(); + } + } + /* I2C Ch.3 Tx buffer empty */ + if (1UL == bCM_I2C3->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C3->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_25))) { + I2C3_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Tx end */ + if (1UL == bCM_I2C3->CR2_b.TENDIE) { + if ((1UL == bCM_I2C3->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_26))) { + I2C3_TxComplete_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = CM_I2C3->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C3->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_27))) { + I2C3_Error_IrqHandler(); + } +} + +/** + * @brief Interrupt No.142 share IRQ handler + * @param None + * @retval None + */ +void IRQ142_Handler(void) +{ + const uint32_t VSSEL142 = CM_INTC->VSSEL142; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* I2C Ch.4 Rx end */ + if (1UL == bCM_I2C4->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C4->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_00))) { + I2C4_RxFull_IrqHandler(); + } + } + /* I2C Ch.4 Tx buffer empty */ + if (1UL == bCM_I2C4->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C4->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_01))) { + I2C4_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.4 Tx end */ + if (1UL == bCM_I2C4->CR2_b.TENDIE) { + if ((1UL == bCM_I2C4->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_02))) { + I2C4_TxComplete_IrqHandler(); + } + } + /* I2C Ch.4 Error */ + u32Tmp1 = CM_I2C4->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C4->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_03))) { + I2C4_Error_IrqHandler(); + } + /* I2C Ch.5 Rx end */ + if (1UL == bCM_I2C5->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C5->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_04))) { + I2C5_RxFull_IrqHandler(); + } + } + /* I2C Ch.5 Tx buffer empty */ + if (1UL == bCM_I2C5->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C5->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_05))) { + I2C5_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.5 Tx end */ + if (1UL == bCM_I2C5->CR2_b.TENDIE) { + if ((1UL == bCM_I2C5->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_06))) { + I2C5_TxComplete_IrqHandler(); + } + } + /* I2C Ch.5 Error */ + u32Tmp1 = CM_I2C5->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C5->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_07))) { + I2C5_Error_IrqHandler(); + } + /* I2C Ch.6 Rx end */ + if (1UL == bCM_I2C6->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C6->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_08))) { + I2C6_RxFull_IrqHandler(); + } + } + /* I2C Ch.6 Tx buffer empty */ + if (1UL == bCM_I2C6->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C6->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_09))) { + I2C6_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.6 Tx end */ + if (1UL == bCM_I2C6->CR2_b.TENDIE) { + if ((1UL == bCM_I2C6->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_10))) { + I2C6_TxComplete_IrqHandler(); + } + } + /* I2C Ch.6 Error */ + u32Tmp1 = CM_I2C6->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMBHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = CM_I2C6->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_11))) { + I2C6_Error_IrqHandler(); + } + /* LVD Ch.1 */ + if (1UL == bCM_PWC->PVDCR1_b.PVD1IRE) { + if ((1UL == bCM_PWC->PVDDSR_b.PVD1DETFLG) && (0UL != (VSSEL142 & BIT_MASK_13))) { + PWC_LVD1_IrqHandler(); + } + } + /* LVD Ch.2 */ + if (1UL == bCM_PWC->PVDCR1_b.PVD2IRE) { + if ((1UL == bCM_PWC->PVDDSR_b.PVD2DETFLG) && (0UL != (VSSEL142 & BIT_MASK_14))) { + PWC_LVD2_IrqHandler(); + } + } + /* FCM error */ + if (1UL == bCM_FCM->RIER_b.ERRIE) { + if ((1UL == bCM_FCM->SR_b.ERRF) && (0UL != (VSSEL142 & BIT_MASK_16))) { + FCM_Error_IrqHandler(); + } + } + /* FCM end */ + if (1UL == bCM_FCM->RIER_b.MENDIE) { + if ((1UL == bCM_FCM->SR_b.MENDF) && (0UL != (VSSEL142 & BIT_MASK_17))) { + FCM_End_IrqHandler(); + } + } + /* FCM overflow */ + if (1UL == bCM_FCM->RIER_b.OVFIE) { + if ((1UL == bCM_FCM->SR_b.OVF) && (0UL != (VSSEL142 & BIT_MASK_18))) { + FCM_Ovf_IrqHandler(); + } + } + /* WDT underflow or refresh error */ + u32Tmp1 = CM_WDT->SR & (WDT_SR_UDF | WDT_SR_REF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL142 & BIT_MASK_19))) { + WDT_IrqHandler(); + } + /* CTC overflow or underflow error */ + if (1UL == bCM_CTC->CR1_b.ERRIE) { + /* underflow */ + if ((1UL == bCM_CTC->STR_b.TRMUDF) && (0UL != (VSSEL142 & BIT_MASK_20))) { + CTC_Udf_IrqHandler(); + } + /* overflow */ + if ((1UL == bCM_CTC->STR_b.TRMOVF) && (0UL != (VSSEL142 & BIT_MASK_20))) { + CTC_Ovf_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.143 share IRQ handler + * @param None + * @retval None + */ +void IRQ143_Handler(void) +{ + const uint32_t VSSEL143 = CM_INTC->VSSEL143; + uint32_t u32Tmp1; + + /* ADC unit1 sequence A */ + if (1UL == bCM_ADC1->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_00))) { + ADC1_SeqA_IrqHandler(); + } + } + /* ADC unit1 sequence B */ + if (1UL == bCM_ADC1->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_01))) { + ADC1_SeqB_IrqHandler(); + } + } + /* ADC unit1 window 0 compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWD0IEN) { + if ((1UL == bCM_ADC1->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_02))) { + ADC1_Cmp0_IrqHandler(); + } + } + /* ADC unit1 window 1 compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWD1IEN) { + /* independence use */ + u32Tmp1 = (uint16_t)(CM_ADC1->AWDCR & ADC_AWDCR_AWDCM); + if ((1UL == bCM_ADC1->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_03))) { + ADC1_Cmp1_IrqHandler(); + } + /* combination use */ + if ((1UL == bCM_ADC1->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_03))) { + ADC1_CmpComb_IrqHandler(); + } + } + /* ADC unit2 sequence A */ + if (1UL == bCM_ADC2->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_04))) { + ADC2_SeqA_IrqHandler(); + } + } + /* ADC unit2 sequence B */ + if (1UL == bCM_ADC2->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_05))) { + ADC2_SeqB_IrqHandler(); + } + } + /* ADC unit2 window 0 compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWD0IEN) { + if ((1UL == bCM_ADC2->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_06))) { + ADC2_Cmp0_IrqHandler(); + } + } + /* ADC unit2 window 1 compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWD1IEN) { + /* independence use */ + u32Tmp1 = ((uint16_t)(CM_ADC2->AWDCR & ADC_AWDCR_AWDCM)); + if ((1UL == bCM_ADC2->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (0UL != (VSSEL143 & BIT_MASK_07)))) { + ADC2_Cmp1_IrqHandler(); + } + /* combination use */ + if ((1UL == bCM_ADC2->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (0UL != (VSSEL143 & BIT_MASK_07)))) { + ADC2_CmpComb_IrqHandler(); + } + } + /* ADC unit3 sequence A */ + if (1UL == bCM_ADC3->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC3->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_08))) { + ADC3_SeqA_IrqHandler(); + } + } + /* ADC unit3 sequence B */ + if (1UL == bCM_ADC3->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC3->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_09))) { + ADC3_SeqB_IrqHandler(); + } + } + /* ADC unit3 window 0 compare */ + if (1UL == bCM_ADC3->AWDCR_b.AWD0IEN) { + if ((1UL == bCM_ADC3->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_10))) { + ADC3_Cmp0_IrqHandler(); + } + } + /* ADC unit3 window 1 compare */ + if (1UL == bCM_ADC3->AWDCR_b.AWD1IEN) { + /* independence use */ + u32Tmp1 = (uint16_t)(CM_ADC3->AWDCR & ADC_AWDCR_AWDCM); + if ((1UL == bCM_ADC3->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_11))) { + ADC3_Cmp1_IrqHandler(); + } + /* combination use */ + if ((1UL == bCM_ADC3->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_11))) { + ADC3_CmpComb_IrqHandler(); + } + } + if (0UL != (VSSEL143 & BIT_MASK_16)) { + if (0UL != (CM_NFC->IRSR & (NFC_IRSR_RBRS | NFC_IRSR_ECCERS | \ + NFC_IRSR_ECCCRS | NFC_IRSR_ECCECRS | NFC_IRSR_ECCEURS))) { + NFC_IrqHandler(); + } + } +} +/** + * @} + */ + +/** + * @defgroup Share_Interrupts_Weakdef_Prototypes Share Interrupts weak function prototypes + * @{ + */ +__WEAKDEF void EXTINT00_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT01_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT02_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT03_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT04_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT05_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT06_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT07_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT08_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT09_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT10_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT11_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT12_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT13_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT14_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT15_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC4_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC5_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC6_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC7_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC4_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC5_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC6_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC7_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error4_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error5_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error6_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error7_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC4_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC5_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC6_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC7_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC4_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC5_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC6_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC7_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error4_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error5_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error6_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error7_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ProgramEraseError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ColError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_OpEnd_IrqHandler(void) +{ +} +__WEAKDEF void QSPI_Error_IrqHandler(void) +{ +} +__WEAKDEF void MAU_Sqrt_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FrameStart_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FrameEnd_IrqHandler(void) +{ +} +__WEAKDEF void DVP_LineStart_IrqHandler(void) +{ +} +__WEAKDEF void DVP_LineEnd_IrqHandler(void) +{ +} +__WEAKDEF void DVP_SWSyncError_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FifoError_IrqHandler(void) +{ +} +__WEAKDEF void FMAC1_IrqHandler(void) +{ +} +__WEAKDEF void FMAC2_IrqHandler(void) +{ +} +__WEAKDEF void FMAC3_IrqHandler(void) +{ +} +__WEAKDEF void FMAC4_IrqHandler(void) +{ +} +__WEAKDEF void DCU1_IrqHandler(void) +{ +} +__WEAKDEF void DCU2_IrqHandler(void) +{ +} +__WEAKDEF void DCU3_IrqHandler(void) +{ +} +__WEAKDEF void DCU4_IrqHandler(void) +{ +} +__WEAKDEF void DCU5_IrqHandler(void) +{ +} +__WEAKDEF void DCU6_IrqHandler(void) +{ +} +__WEAKDEF void DCU7_IrqHandler(void) +{ +} +__WEAKDEF void DCU8_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void RTC_TimeStamp0_IrqHandler(void) +{ +} +__WEAKDEF void RTC_TimeStamp1_IrqHandler(void) +{ +} +__WEAKDEF void RTC_Alarm_IrqHandler(void) +{ +} +__WEAKDEF void RTC_Period_IrqHandler(void) +{ +} +__WEAKDEF void CLK_XtalStop_IrqHandler(void) +{ +} +__WEAKDEF void SWDT_IrqHandler(void) +{ +} +__WEAKDEF void WDT_IrqHandler(void) +{ +} +__WEAKDEF void PWC_WakeupTimer_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR0_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR1_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR2_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR3_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR4_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR5_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR6_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART5_LinBreakField_IrqHandler(void) +{ +} +__WEAKDEF void USART5_LinWakeup_IrqHandler(void) +{ +} +__WEAKDEF void USART5_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART5_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART5_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART6_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART6_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART6_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART6_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART7_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART7_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART7_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART7_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART7_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART8_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART8_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART8_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART8_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART9_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART9_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART9_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART9_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART10_LinBreakField_IrqHandler(void) +{ +} +__WEAKDEF void USART10_LinWakeup_IrqHandler(void) +{ +} +__WEAKDEF void USART10_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART10_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART10_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART10_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI5_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI5_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI5_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI6_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI6_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI6_Idle_IrqHandler(void) +{ +} +__WEAKDEF void CAN1_IrqHandler(void) +{ +} +__WEAKDEF void CAN2_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Error_IrqHandler(void) +{ +} +__WEAKDEF void USBFS_Global_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC1_Normal_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC1_Error_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC2_Normal_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC2_Error_IrqHandler(void) +{ +} +__WEAKDEF void ETH_Global_IrqHandler(void) +{ +} +__WEAKDEF void ETH_Wakeup_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C4_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C4_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C5_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C5_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C5_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C6_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C6_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C6_Error_IrqHandler(void) +{ +} + +__WEAKDEF void PWC_LVD1_IrqHandler(void) +{ +} +__WEAKDEF void PWC_LVD2_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Error_IrqHandler(void) +{ +} +__WEAKDEF void FCM_End_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void CTC_Udf_IrqHandler(void) +{ +} +__WEAKDEF void CTC_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_CmpComb_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_CmpComb_IrqHandler(void) +{ +} +__WEAKDEF void ADC3_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC3_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC3_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC3_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void ADC3_CmpComb_IrqHandler(void) +{ +} +__WEAKDEF void NFC_IrqHandler(void) +{ +} +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h new file mode 100644 index 0000000000..222201cf65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h @@ -0,0 +1,145 @@ +/** + ******************************************************************************* + * @file stl_common.h + * @brief This file contains STL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_COMMON_H__ +#define __STL_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_Common_Global_Macros STL Common Global Macros + * @{ + */ + +/** + * @defgroup STL_Generic_Error_Codes STL Generic Error Codes + * @{ + */ +#define STL_OK (0UL) /*!< No error occurs */ +#define STL_ERR (1UL) /*!< Error occurs */ +/** + * @} + */ + +/** + * @defgroup STL_Module_Switch STL Module Switch + * @{ + */ +#define STL_ON (1U) +#define STL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifdef __CC_ARM /*!< ARM Compiler */ +/* CPU will start executing at the program entry label __main when the CPU is reset */ +extern void __main(void); + +/* CC */ +#define STL_SECTION(x) __attribute__((section(x))) +#define STL_UNUSED __attribute__((unused)) +#define STL_USED __attribute__((used)) +#define STL_ALIGN(n) __attribute__((aligned(n))) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static __inline + +#define CallApplicationStartUp( ) __main() + +#elif defined (__ICCARM__) /*!< IAR Compiler */ +/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */ +extern void __iar_program_start(void); + +/* CC */ +#define STL_SECTION(x) @ x +#define STL_UNUSED +#define STL_USED __root +#define STL_PRAGMA(x) _Pragma(#x) +#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static inline + +#define CallApplicationStartUp( ) __iar_program_start() +#else +#error Unsupported tool chain +#endif +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h new file mode 100644 index 0000000000..ff08ef50f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h @@ -0,0 +1,106 @@ +/** + ******************************************************************************* + * @file stl_conf.h + * @brief This file contains STL resource configure. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_CONF_H__ +#define __STL_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_bsp_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Configure + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters + * @{ + */ +#define STL_ROM_CRC32_START (STL_ROM_START) +#define STL_ROM_CRC32_END ((uint32_t)&__checksum - 1UL) +#define STL_ROM_CRC32_SIZE (STL_ROM_CRC32_END - STL_ROM_CRC32_START + 1UL) +#define STL_ROM_CRC32_BLOCK_SIZE (128UL) +#define STL_ROM_CRC32_CC_CHECKSUM (__checksum) +/** + * @} + */ + +/** + * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters + * @{ + */ +#define STL_MARCH_RAM_SIZE (32UL) +#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2) +#define STL_MARCH_RAM_BUF_SIZE (16UL) +#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2) + +#define STL_MARCH_RAM_BCKGRND (0x00000000UL) +#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL) + +#define STL_STACK_BOUNDARY_WORDS (4UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h new file mode 100644 index 0000000000..6e5a06539c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h @@ -0,0 +1,95 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_SW_CRC32_H__ +#define __STL_SW_CRC32_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CRC32 + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros + * @{ + */ +#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CRC32_Global_Functions + * @{ + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_SW_CRC32_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h new file mode 100644 index 0000000000..0a5bfdd362 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h @@ -0,0 +1,86 @@ +/** + ******************************************************************************* + * @file stl_test_cpu.h + * @brief This file contains all the functions prototypes of the CPU test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_CPU_H__ +#define __STL_TEST_CPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CPU + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CPU_Global_Functions + * @{ + */ +uint32_t STL_CpuTestStartup(void); +uint32_t STL_CpuTestRuntime(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_CPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h new file mode 100644 index 0000000000..a13b329f0b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h @@ -0,0 +1,87 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_FLASH_H__ +#define __STL_TEST_FLASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Flash + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Flash_Global_Functions + * @{ + */ +uint32_t STL_FlashStartupTest(void); +uint32_t STL_FlashRuntimeTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_FLASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h new file mode 100644 index 0000000000..a3c6ce396a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h @@ -0,0 +1,100 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.h + * @brief This file contains all the functions prototypes of the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_INTERRUPT_H__ +#define __STL_TEST_INTERRUPT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Interrupt + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ +/** + * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type + * @{ + */ +typedef struct stc_stl_int_params { + uint32_t u32FreqInitVal; + uint32_t u32FreqLowerVal; + uint32_t u32FreqUpperVal; + uint32_t u32PrivateParam; +} stc_stl_int_params_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Interrupt_Global_Functions + * @{ + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize); +uint32_t STL_IntRuntimeTest(void); +void STL_IntUpdateCount(uint8_t u8ParamIndex); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_INTERRUPT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h new file mode 100644 index 0000000000..834d26d4f1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h @@ -0,0 +1,85 @@ +/** + ******************************************************************************* + * @file stl_test_pc.h + * @brief This file contains all the functions prototypes of the PC test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_PC_H__ +#define __STL_TEST_PC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_PC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_PC_Global_Functions + * @{ + */ +uint32_t STL_PcTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_PC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h new file mode 100644 index 0000000000..f104dc8b4f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h @@ -0,0 +1,89 @@ +/** + ******************************************************************************* + * @file stl_test_ram.h + * @brief This file contains all the functions prototypes of the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RAM_H__ +#define __STL_TEST_RAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_RAM + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_RAM_Global_Functions + * @{ + */ +uint32_t STL_StackRuntimeInit(void); +uint32_t STL_StackRuntimeTest(void); +uint32_t STL_RamRuntimeInit(void); +uint32_t STL_RamRuntimeTest(void); +uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_RAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..199c25c3ff --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s @@ -0,0 +1,245 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + + ; Exported function + EXPORT STL_CpuTestRuntime + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestRuntime: + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s new file mode 100644 index 0000000000..186c49e205 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s @@ -0,0 +1,357 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 + + ; Exported function + EXPORT STL_CpuTestStartup + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestStartup: + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; PRIMASK register + MRS R1, PRIMASK + LDR R0, =data0x00000000 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #0 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x00000001 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #1 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R1 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..1c9addd769 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s @@ -0,0 +1,186 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + SECTION constdata:CONST(2) +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + + ; Exported function + EXPORT STL_FullRamTestStartup + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_FullRamTestStartup: + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop: + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2: + MOVS R5, R0 +_step_2_loop: + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3: + MOVS R5, R0 +_step_3_loop: + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop: + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop: + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6: + MOVS R5, R0 +_step_6_loop: + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail: + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass: + MOVS R0, R4 + BX LR ; return to the caller + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s new file mode 100644 index 0000000000..5704246cc0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s @@ -0,0 +1,147 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + ; Exported function + EXPORT STL_PcTest + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + + SECTION .text:CODE(2) + THUMB +STL_PcTest + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit: + POP {R4-R7} ; Restore registers + BX R3 ; return + + SECTION .pctestaddr1:CODE(2) +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr2:CODE(2) +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr3:CODE(2) +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr4:CODE(2) +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr5:CODE(2) +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr6:CODE(2) +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr7:CODE(2) +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr8:CODE(2) +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subrouitne address in R1 + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..c20034361b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s @@ -0,0 +1,251 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestRuntime PROC + EXPORT STL_CpuTestRuntime + + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s new file mode 100644 index 0000000000..cf779fb02b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s @@ -0,0 +1,363 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestStartup PROC + EXPORT STL_CpuTestStartup + + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; PRIMASK register + MRS R1, PRIMASK + LDR R0, =data0x00000000 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #0 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x00000001 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #1 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R1 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..b5d6501147 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s @@ -0,0 +1,191 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_FullRamTestStartup PROC + EXPORT STL_FullRamTestStartup + + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2 + MOVS R5, R0 +_step_2_loop + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3 + MOVS R5, R0 +_step_3_loop + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6 + MOVS R5, R0 +_step_6_loop + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass + MOVS R0, R4 + BX LR ; return to the caller + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s new file mode 100644 index 0000000000..598d9ebd6f --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s @@ -0,0 +1,146 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + +STL_PcTest PROC + EXPORT STL_PcTest + + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit + POP {R4-R7} ; Restore registers + BX R3 ; return + +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subrouitne address in R1 + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c new file mode 100644 index 0000000000..15a1021b82 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c @@ -0,0 +1,156 @@ +/** + ******************************************************************************* + * @file stl_sw_crc32.c + * @brief This file provides firmware functions to manage the software CRC32. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_sw_crc32.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32 + * @brief IEC60730 software CRC32 + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables + * @{ + */ +static const uint32_t m_au32Crc32Table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, + 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, + 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, + 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, + 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, + 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, + 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, + 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, + 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, + 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, + 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, + 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, + 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, + 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, + 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, + 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, + 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, + 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, + 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, + 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, + 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, + 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions + * @{ + */ + +/** + * @brief Calculate CRC32 value. + * @param [in] u32Crc32Value CRC32 value + * @param [in] pu8Data Pointer to data buffer + * @param [in] u32Len Data length + * @retval None + * @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000 + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t octet; + const uint8_t *p, *q; + uint32_t u32CurrCrc32Value = u32Crc32Value; + + q = pu8Data + u32Len; + for (p = pu8Data; p < q; p++) { + octet = *p; + u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ octet]; + } + + return u32CurrCrc32Value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c new file mode 100644 index 0000000000..ed6c344807 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c @@ -0,0 +1,164 @@ +/** + ******************************************************************************* + * @file stl_test_flash.c + * @brief This file provides firmware functions to manage the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_sw_crc32.h" +#include "stl_test_flash.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Flash STL IEC60730 Flash + * @brief IEC60730 flash test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CC_BULID_CRC32_VALUE (*(volatile uint32_t *)(&STL_ROM_CRC32_CC_CHECKSUM)) + +#if defined (__CC_ARM) /* keil Compiler */ +#define STL_CRC32_XOR_VALUE (0xFFFFFFFFUL) +#elif defined (__IAR_SYSTEMS_ICC__) /* IAR Compiler */ +#define STL_CRC32_XOR_VALUE (0x00000000UL) +#endif + +#define SW_CRC32_VALUE_XOR(x) ((x) ^ STL_CRC32_XOR_VALUE) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables + * @{ + */ +STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL; +/** + * @} + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions + * @{ + */ + +/** + * @brief Flash test in startup. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Flash CRC value error. + */ +uint32_t STL_FlashStartupTest(void) +{ + uint32_t u32CalcCrc32Value; + uint32_t u32Ret = STL_ERR; + + u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, (uint8_t *)STL_ROM_CRC32_START, STL_ROM_CRC32_SIZE); + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (CC_BULID_CRC32_VALUE == u32CalcCrc32Value) { + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Flash test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_OK: Flash CRC32 value error. + */ +uint32_t STL_FlashRuntimeTest(void) +{ + uint32_t u32Ret = STL_OK; + const uint32_t u32CheckEndAddr = STL_ROM_CRC32_END + 4UL - STL_ROM_CRC32_BLOCK_SIZE; + static uint32_t u32CalcLen; + static uint32_t u32CheckAddr = STL_ROM_CRC32_START; + static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE; + + if (u32CheckAddr < STL_ROM_CRC32_END) { + if (u32CheckAddr == STL_ROM_CRC32_START) { + u32CalcCrc32Value = STL_CRC32_INIT_VALUE; /* Update CRC32 init value */ + } + + if (u32CheckAddr < u32CheckEndAddr) { + u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE; + } else { + u32CalcLen = STL_ROM_CRC32_END - u32CheckAddr + 1UL; + } + u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen); + + u32CheckAddr += u32CalcLen; /* Update address */ + } else { + u32CheckAddr = STL_ROM_CRC32_START; /* Update address */ + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (CC_BULID_CRC32_VALUE == u32CalcCrc32Value) { + STL_Printf("******** CRC32 verify ok in runtime ********\r\n"); + } else { + STL_Printf("******** CRC32 verify error in runtime ********\r\n"); + STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, CC_BULID_CRC32_VALUE); + u32Ret = STL_ERR; + } + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c new file mode 100644 index 0000000000..4cc1ef2f11 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c @@ -0,0 +1,169 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.c + * @brief This file provides firmware functions to manage the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_interrupt.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime + * @brief IEC60730 interrupt runtime test + * @{ + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +static uint32_t m_u32TestParamTableSize; +static stc_stl_int_params_t *m_pstcTestParamTable; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions + * @{ + */ + +/** + * @brief Interrupt test table initialize in runtime. + * @param [in] pstcParamsTable Test case table + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Initialize successfully. + * - STL_ERR: Initialize unsuccessfully. + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize) +{ + uint32_t i; + uint32_t u32Ret = STL_ERR; + + if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + pstcParamsTable[i].u32PrivateParam = 0UL; + } + + m_pstcTestParamTable = pstcParamsTable; + m_u32TestParamTableSize = u32TableSize; + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Interrupt test initialize in runtime. + * @param [in] pstcParamsTable Test case table + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test error. + */ +uint32_t STL_IntRuntimeTest(void) +{ + uint32_t i; + uint32_t u32Ret = STL_OK; + stc_stl_int_params_t *pstcTestParam; + static uint32_t u32SystickCount; + + if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) { + for (i = 0UL; i < m_u32TestParamTableSize; i++) { + pstcTestParam = &m_pstcTestParamTable[i]; + + if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \ + (pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) { + u32Ret = STL_ERR; + } + pstcTestParam->u32PrivateParam = 0UL; + } + u32SystickCount = 0UL; + } + + return u32Ret; +} + +/** + * @brief Update interrupt count in runtime. + * @param [in] u8Num Params index + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test error. + */ +void STL_IntUpdateCount(uint8_t u8ParamIndex) +{ + stc_stl_int_params_t *pstcTestParam; + + if (u8ParamIndex < m_u32TestParamTableSize) { + pstcTestParam = &m_pstcTestParamTable[u8ParamIndex]; + pstcTestParam->u32PrivateParam++; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c new file mode 100644 index 0000000000..74cc57f0c5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c @@ -0,0 +1,268 @@ +/** + ******************************************************************************* + * @file stl_test_ram_runtime.c + * @brief This file provides firmware functions to manage the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_ram.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime + * @brief IEC60730 RAM runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +STL_USED uint32_t m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram"); +STL_USED uint32_t m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf"); +STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer"); +STL_USED uint32_t m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary"); +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions + * @{ + */ + +/** + * @brief Stack test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_StackRuntimeInit(void) +{ + m_au32StackBoundary[0] = 0x5A5A5A5AUL; + m_au32StackBoundary[1] = 0xA5A5A5A5UL; + m_au32StackBoundary[2] = 0xAAAAAAAAUL; + m_au32StackBoundary[3] = 0x55555555UL; + return STL_OK; +} + +/** + * @brief Stack test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Stack boundary value error. + */ +uint32_t STL_StackRuntimeTest(void) +{ + if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \ + (m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \ + (m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \ + (m_au32StackBoundary[3] != 0x55555555UL)) { + return STL_ERR; + } + + return STL_OK; +} + +/** + * @brief RAM test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_RamRuntimeInit(void) +{ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + return STL_OK; +} + +/** + * @brief RAM test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test fail. + */ +uint32_t STL_RamRuntimeTest(void) +{ + uint32_t i; /* Index for RAM physical addressing */ + uint32_t u32Ret = STL_OK; + + if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) { + /*------------- March C- to the RAM Buffer itself --------------- */ + m_pu32MarchRAM = &m_au32MarchRAMBuf[0]; + + /*---------------------------- STEP 1 --------------------------------- */ + /* Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + } + + /* Prepare next Tranparent RAM test from the beginning of Class A area */ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + } else { + /*---------------------------- STEP 1 --------------------------------- */ + /* Save the content of the 6 words to be tested and start MarchC - + Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + m_au32MarchRAMBuf[i] = *(m_pu32MarchRAM + i); + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + /* and restore the content of the 6 tested words */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = m_au32MarchRAMBuf[i]; + } + + /* Prepare next Row Tranparent RAM test */ + m_pu32MarchRAM += STL_MARCH_RAM_BUF_WORDS; + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c new file mode 100644 index 0000000000..9ec2bf7100 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.c + * @brief This file provides firmware functions to manage the runtime self-test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_test_runtime.h" +#include "stl_conf.h" +#include "stl_utility.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime + * @brief IEC60730 runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros + * @{ + */ + +/** + * @brief Self-test initialization in runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + +#if (STL_PRINT_ENABLE == STL_ON) + (void)STL_PrintfInit(); /* startup debug print */ +#endif + + STL_Printf("******** Self-test runtime initialize ********\r\n"); + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnInit != NULL) { + if (pstcCaseTable[i].pfnInit() != STL_OK) { + STL_Printf("%s test initialization unsuccessfully in runtime\r\n", pstcCaseTable[i].pcCaseName); + } + } + } + } +} + +/** + * @brief Self-test on runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("******** %s test fail in runtime ********\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + + if (pstcCaseTable[i].pfnFeedDog != NULL) { + pstcCaseTable[i].pfnFeedDog(); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h new file mode 100644 index 0000000000..e98b6c1a6b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h @@ -0,0 +1,116 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.h + * @brief This file contains all the functions prototypes of runtime test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RUNTIME_H__ +#define __STL_TEST_RUNTIME_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Runtime + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_runtime { + const char *pcCaseName; + uint32_t (*pfnInit)(void); + uint32_t (*pfnTest)(void); + + void (*pfnFeedDog)(void); + void (*pfnFailHandler)(void); +} stc_stl_case_runtime_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Case STL IEC60730 Runtime Case + * @{ + */ +#define STL_RUNTIME_CASE(CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler) \ + { #CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Runtime_Global_Functions + * @{ + */ + +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* #include "stl_common.h" */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c new file mode 100644 index 0000000000..3b22da222e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * @file stl_test_startup.c + * @brief This file provides firmware functions to manage the startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_test_startup.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Startup STL IEC60730 Startup + * @brief IEC60730 startup test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Global_Macros STL IEC60730 Startup Global Macros + * @{ + */ + +/** + * @brief Power on self-test. + * @param None + * @retval None + */ +STL_WEAK void STL_StartupTest(void) +{ + /* please implement this function. */ + for (;;) { + } +} + +/** + * @brief Power on self-test. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("%s test fail in startup\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h new file mode 100644 index 0000000000..fb877e8ff0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file stl_test_startup.h + * @brief This file contains all the functions prototypes of startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_STARTUP_H__ +#define __STL_TEST_STARTUP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Startup + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_startup { + const char *pcCaseName; + uint32_t (*pfnTest)(void); + + void (*pfnFailHandler)(void); +} stc_stl_case_startup_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Case STL IEC60730 Startup Case + * @{ + */ +#define STL_STARTUP_CASE(CaseName, pfnTest, pfnFailHandler) \ + { #CaseName, pfnTest, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Startup_Global_Functions + * @{ + */ +void STL_StartupTest(void); +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_STARTUP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c new file mode 100644 index 0000000000..cf87f388ef --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c @@ -0,0 +1,234 @@ +/** + ******************************************************************************* + * @file stl_utility.c + * @brief This file provides utility functions for STL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_utility.h" +#include "hc32_ll_fcg.h" +#include "hc32_ll_gpio.h" +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @defgroup IEC60730_STL_Utility IEC60730 STL Utility + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +void STL_DelayUS(uint32_t u32Count) +{ + DDL_DelayUS(u32Count); +} + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +void STL_DelayMS(uint32_t u32Count) +{ + DDL_DelayMS(u32Count); +} + +/** + * @brief STL test safety failure handle + * @param None + * @retval None + */ +void STL_SafetyFailure(void) +{ +#if (STL_RESET_AT_FAILURE == STL_ON) + NVIC_SystemReset(); /* Generate system reset */ +#endif +} + +#if (STL_PRINT_ENABLE == STL_ON) + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval uint32_t: + * - STL_OK: Transmit successfully. + * - STL_ERR: Transmit timeout. + */ +__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData) +{ + uint32_t u32Ret = STL_ERR; + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + uint32_t u32Timeout = 10000UL; + + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG32(STL_PRINTF_DEVICE->DR, (uint32_t)cData); + u32Ret = STL_OK; + } + + return u32Ret; +} + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif defined (__GNUC__) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (STL_OK != STL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param None + * @retval None + */ +uint32_t STL_PrintfInit(void) +{ + uint32_t u32Div; + float32_t f32Error; + uint32_t u32Ret = STL_ERR; + stc_usart_uart_init_t stcUartInit; + + /* Set TX port function */ + GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC); + + /* Enable clock */ + STL_PRINTF_DEVICE_FCG_ENALBE(); + + /*************************************************************************** + * Configure UART + *************************************************************************** + * Baud rate: STL_PRINTF_BAUDRATE + * Bit direction: LSB + * Data bits: 8 + * Stop bits: 1 + * Parity: None + * Sampling bits: 8 + **************************************************************************/ + /* Configure UART */ + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + (void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL); + + for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) { + USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div); + if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \ + ((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) { + USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE); + u32Ret = STL_OK; + break; + } + } + + return u32Ret; +} + +#endif /* STL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h new file mode 100644 index 0000000000..1dd50c4357 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h @@ -0,0 +1,107 @@ +/** + ******************************************************************************* + * @file stl_utility.h + * @brief This file contains all the functions prototypes of utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_UTILITY_H__ +#define __STL_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Utility + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @addtogroup STL_UTILITY_Global_Functions + * @{ + */ + +#if (STL_PRINT_ENABLE == STL_ON) +#include +uint32_t STL_ConsoleOutputChar(char cData); +#define STL_Printf (void)printf +#else +#define STL_Printf(...) +#endif + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addgroup STL_Utility_Global_Functions + * @{ + */ +void STL_DelayUS(uint32_t u32Count); +void STL_DelayMS(uint32_t u32Count); + +void STL_SafetyFailure(void); + +uint32_t STL_PrintfInit(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c new file mode 100644 index 0000000000..0da412ed76 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c @@ -0,0 +1,334 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_msc_wrapper.c + * @brief USB composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_cdc_class.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_cdc_msc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS LL USB Device Class + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CDC_MSC_COMPOSITE USB Device CDC MSC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_msc_cdc_init(void *pdev); +void usb_dev_msc_cdc_deinit(void *pdev); +uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum); +void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum); +uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length); +uint8_t usb_dev_msc_cdc_sof(void *pdev); +void usb_dev_msc_cdc_ctrlep_rxready(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_composite_cbk = { + &usb_dev_msc_cdc_init, + &usb_dev_msc_cdc_deinit, + &usb_dev_msc_cdc_setup, + NULL, + &usb_dev_msc_cdc_ctrlep_rxready, + &usb_dev_msc_cdc_getcfgdesc, + &usb_dev_msc_cdc_sof, + &usb_dev_msc_cdc_datain, + &usb_dev_msc_cdc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cdc_cfgdesc[USB_MSC_CDC_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_CDC_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + + /* IAD for CDC configuration descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + /* CDC configuration descriptor */ + /* interface descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: Interface */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, + + /* Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /* Mass Storage Endpoints ********************/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds*/ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_cdc_init(void *pdev) +{ + usb_dev_cdc_init(pdev); + usb_dev_msc_init(pdev); +} + +/** + * @brief de-initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_cdc_deinit(void *pdev) +{ + usb_dev_cdc_deinit(pdev); + usb_dev_msc_deinit(pdev); +} + +/** + * @brief process the setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == 0x02U) { + u8Res = usb_dev_msc_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == CDC_IN_EP) { + u8Res = usb_dev_cdc_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Data received on control endpoint + * @param [in] pdev device device instance + * @retval None + */ +void usb_dev_msc_cdc_ctrlep_rxready(void *pdev) +{ + usb_dev_cdc_ctrlep_rxready(pdev); +} + +/** + * @brief process the sof + * @param [in] pdev device instance + * @retval status + */ +uint8_t usb_dev_msc_cdc_sof(void *pdev) +{ + return usb_dev_cdc_sof(pdev); +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_datain(pdev, epnum); + } else { + usb_dev_cdc_datain(pdev, epnum); + } +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_dataout(pdev, epnum); + } else { + usb_dev_cdc_dataout(pdev, epnum); + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_cdc_cfgdesc); + return usb_dev_msc_cdc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h new file mode 100644 index 0000000000..a10762e898 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h @@ -0,0 +1,79 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_msc_wrapper.h + * @brief header file for the usb_dev_cdc_msc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CDC_MSC_WRAPPER_H__ +#define __USB_DEV_CDC_MSC_WRAPPER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_CDC_MSC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_MSC_CDC_CONFIG_DESC_SIZ (USB_CDC_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CDC_MSC_WRAPPER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c new file mode 100644 index 0000000000..76c55e7e08 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c @@ -0,0 +1,381 @@ +/** + ******************************************************************************* + * @file usb_dev_custom_hid_class.c + * @brief CUSTOM HID core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CUSTOM_HID USB Device Custom HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_hid_init(void *pdev); +void usb_dev_hid_deinit(void *pdev); +uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length); +void usb_dev_hid_datain(void *pdev, uint8_t epnum); +void usb_dev_hid_dataout(void *pdev, uint8_t epnum); +void usb_dev_hid_ctrlep_rxready(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t Report_buf[64]; +uint8_t Send_Buf[64]; +static __IO uint32_t IsReportAvailable = 0UL; + +usb_dev_class_func class_customhid_cbk = { + &usb_dev_hid_init, + &usb_dev_hid_deinit, + &usb_dev_hid_setup, + NULL, + &usb_dev_hid_ctrlep_rxready, + &usb_dev_hid_getcfgdesc, + NULL, + &usb_dev_hid_datain, + &usb_dev_hid_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_AltSet = 0UL; + +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_Protocol = 0UL; + +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_IdleState = 0UL; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_hid_cfgdesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] = { + 0x09, + USB_CFG_DESCRIPTOR_TYPE, + USB_CUSTOM_HID_CONFIG_DESC_SIZ, + 0x00, + 0x01, + 0x01, + 0x00, + 0xC0, + 0x32, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x00, + 0x00, + 0x02, + 0x03, + 0x00, + 0x00, + 0x00, + + 0x09, + CUSTOM_HID_DESCRIPTOR_TYPE, + 0x10, + 0x01, + 0x21, + 0x01, + 0x22, + CUSTOM_HID_REPORT_DESC_SIZE, + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + HID_IN_EP, + 0x03, + HID_IN_PACKET, + 0x00, + 0x0A, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + + HID_OUT_EP, + 0x03, + HID_OUT_PACKET, + 0x00, + 0x0A, +} ; + + +__USB_ALIGN_BEGIN static uint8_t CUSTOM_HID_ReportDesc[CUSTOM_HID_REPORT_DESC_SIZE] = { + 0x05, 0x8C, 0x09, 0x06, 0xA1, 0x01, 0x09, 0x06, 0x15, 0x00, 0x26, 0x00, + 0xFF, 0x75, 0x08, 0x95, 0x40, 0x91, 0x82, 0x09, 0x06, 0x15, 0x00, 0x26, + 0x00, 0xFF, 0x75, 0x08, 0x95, 0X40, 0x81, 0x82, 0xC0 +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the HID application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, Report_buf, HID_OUT_PACKET); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief Deinitialize the HID application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t hid_report_length; + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Ret = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case CUSTOM_HID_REQ_SET_PROTOCOL: + USB_DEV_HID_Protocol = (uint8_t)(req->wValue); + break; + case CUSTOM_HID_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_Protocol, 1U); + break; + case CUSTOM_HID_REQ_SET_IDLE: + USB_DEV_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + case CUSTOM_HID_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_IdleState, 1U); + break; + case CUSTOM_HID_REQ_SET_REPORT: + IsReportAvailable = 1UL; + hid_report_length = (uint8_t)(req->wLength); + usb_ctrldatarx(pdev, Report_buf, (uint16_t)hid_report_length); + break; + default: + usb_ctrlerr(pdev); + u8Ret = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if (req->wValue >> 8U == CUSTOM_HID_REPORT_DESC) { + len = LL_MIN((uint16_t)CUSTOM_HID_REPORT_DESC_SIZE, req->wLength); + pbuf = (uint8_t *)CUSTOM_HID_ReportDesc; + } else if (req->wValue >> 8U == CUSTOM_HID_DESCRIPTOR_TYPE) { + pbuf = (uint8_t *)usb_dev_hid_cfgdesc + 0x12U; + len = LL_MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength); + } else { + ; + } + + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_HID_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Ret; +} + +/** + * @brief Send HID Report + * @param [in] pdev Device instance + * @param [in] report pointer to report + * @param [in] len the length in bytes would be sent + * @retval status + */ +uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len); + } + return USB_DEV_OK; +} + +/** + * @brief return configuration descriptor + * @param [in] length length of configuration descriptor in bytes + * @retval pointer to configuration descriptor buffer + */ +uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length) +{ + *length = (uint8_t)sizeof(usb_dev_hid_cfgdesc); + return usb_dev_hid_cfgdesc; +} + +/** + * @brief processing for data in + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_hid_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); + + if (epnum == (HID_IN_EP & (uint8_t)~0x80U)) { + PrevXferDone = 1U; + } +} + +/** + * @brief processing for data out + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_hid_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == HID_OUT_EP) { + switch (Report_buf[0]) { + case 1: /* Led 1 */ + if (Report_buf[1U] == 0U) { + /* RED LED on */ + BSP_LED_Off(LED_RED); + } else { + /* RED LED off */ + BSP_LED_On(LED_RED); + } + break; + + case 2: /* Led 2 */ + if (Report_buf[1U] == 0U) { + /* BLUE LED on */ + BSP_LED_Off(LED_BLUE); + } else { + /* BLUE LED off */ + BSP_LED_On(LED_BLUE); + } + break; + default: + BSP_LED_Off(LED_RED); + BSP_LED_Off(LED_BLUE); + break; + } + } + + usb_readytorx(pdev, HID_OUT_EP, Report_buf, 2U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); + usb_deveptx(pdev, HID_IN_EP, Report_buf, 2); +} + +/** + * @brief processing for request data in control endpoint + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_ctrlep_rxready(void *pdev) +{ + if (IsReportAvailable == 1UL) { + IsReportAvailable = 0UL; + switch (Report_buf[0]) { + case 1: /* Led 1 */ + if (Report_buf[1] == 0U) { + /* RED LED on */ + BSP_LED_Off(LED_RED); + } else { + /* RED LED off */ + BSP_LED_On(LED_RED); + } + break; + + case 2: /* Led 2 */ + if (Report_buf[1] == 0U) { + /* BLUE LED on */ + BSP_LED_Off(LED_BLUE); + } else { + /* BLUE LED off */ + BSP_LED_On(LED_BLUE); + } + break; + default: + BSP_LED_Off(LED_RED); + BSP_LED_Off(LED_BLUE); + break; + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h new file mode 100644 index 0000000000..022eefdae8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file usb_dev_custom_hid_class.h + * @brief Head file for usb_dev_custom_hid_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CUSTOMHID_HID_CORE_H__ +#define __USB_DEV_CUSTOMHID_HID_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CUSTOM_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CUSTOM_HID_REPORT_DESC_SIZE (0x21) + +#define USB_CUSTOM_HID_CONFIG_DESC_SIZ (41U) +#define USB_CUSTOM_HID_DESC_SIZ (9U) + +#define CUSTOM_HID_DESCRIPTOR_TYPE (0x21U) +#define CUSTOM_HID_REPORT_DESC (0x22U) + +#define CUSTOM_HID_REQ_SET_PROTOCOL (0x0BU) +#define CUSTOM_HID_REQ_GET_PROTOCOL (0x03U) + +#define CUSTOM_HID_REQ_SET_IDLE (0x0AU) +#define CUSTOM_HID_REQ_GET_IDLE (0x02U) + +#define CUSTOM_HID_REQ_SET_REPORT (0x09U) +#define CUSTOM_HID_REQ_GET_REPORT (0x01U) + +#define LED1_REPORT_ID (0x01U) +#define LED1_REPORT_COUNT (0x01U) + +#define LED2_REPORT_ID (0x02U) +#define LED2_REPORT_COUNT (0x01U) + +#define LED3_REPORT_ID (0x03U) +#define LED3_REPORT_COUNT (0x01U) + +#define LED4_REPORT_ID (0x04U) +#define LED4_REPORT_COUNT (0x01U) + +#define KEY_REPORT_ID (0x05U) +#define TAMPER_REPORT_ID (0x06U) +#define ADC_REPORT_ID (0x07U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_customhid_cbk; +extern uint8_t Report_buf[64]; +extern uint8_t Send_Buf[64]; +extern uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/* HID Device library callbacks */ +extern void usb_dev_hid_init(void *pdev); +extern void usb_dev_hid_deinit(void *pdev); +extern uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req); +extern uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length); +extern void usb_dev_hid_datain(void *pdev, uint8_t epnum); +extern void usb_dev_hid_dataout(void *pdev, uint8_t epnum); +extern void usb_dev_hid_ctrlep_rxready(void *pdev); + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CUSTOMHID_HID_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c new file mode 100644 index 0000000000..d984583767 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c @@ -0,0 +1,364 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_cdc_wrapper.c + * @brief HID CDC composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_cdc_class.h" +#include "usb_dev_hid_cdc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE USB Device HID CDC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_COMPOSITE_CFGDESC_SIZE (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_CDC_CONFIG_DESC_SIZ + 8U) + +#define HID_INTERFACE (0x0U) +#define CDC_COM_INTERFACE (0x1U) + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_composite_init(void *pdev); +void usb_dev_composite_deinit(void *pdev); +uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_composite_rxready(void *pdev); +void usb_dev_composite_datain(void *pdev, uint8_t epnum); +void usb_dev_composite_dataout(void *pdev, uint8_t epnum); +uint8_t usb_dev_composite_sof(void *pdev); +uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length); + + +/******************************************************************************* + * Global variable definitions + ******************************************************************************/ +usb_dev_class_func class_composite_cbk = { + &usb_dev_composite_init, + &usb_dev_composite_deinit, + &usb_dev_composite_setup, + NULL, + &usb_dev_composite_rxready, + &usb_dev_composite_getcfgdesc, + &usb_dev_composite_sof, + &usb_dev_composite_datain, + &usb_dev_composite_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_composite_cfgdesc[USB_COMPOSITE_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_COMPOSITE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 for HID) */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /* 09 */ + /************** Descriptor of HID interface ****************/ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + HID_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /* 18 */ + /******************** Descriptor of HID ********************/ + 0x09, /* bLength: HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID*/ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /* 27 */ + /******************** Descriptor of HID endpoint ********************/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 64 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 64 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ + /******** IAD should be positioned just before the CDC interfaces *******/ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x01, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + /*49*/ + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x01, /* iInterface: */ + /*58*/ + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + /*63*/ + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x02, /* bDataInterface: 2 */ + /*68*/ + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /*72*/ + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x01, /* bMasterInterface: Communication class interface */ + 0x02, /* bSlaveInterface0: Data Class Interface */ + /*77*/ + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + /*84*/ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /*93*/ + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + /*100*/ + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval */ + /*107*/ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite app + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_init(void *pdev) +{ + usb_dev_hid_init(pdev); + usb_dev_cdc_init(pdev); +} + +/** + * @brief Deinitialize the composite app + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_deinit(void *pdev) +{ + usb_dev_hid_deinit(pdev); + usb_dev_cdc_deinit(pdev); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief get the configuration descriptor and return the its pointer + * @param [in] length length of configuration descriptor + * @retval the pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_composite_cfgdesc); + return usb_dev_composite_cfgdesc; +} + +/** + * @brief processing for data in + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_composite_datain(void *pdev, uint8_t epnum) +{ + if (epnum == ((uint8_t)CDC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_cdc_datain(pdev, epnum); + } else { + usb_dev_hid_datain(pdev, epnum); + } +} + +/** + * @brief processing for data out + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_composite_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == ((uint8_t)CDC_OUT_EP & (uint8_t)~0x80U)) { + usb_dev_cdc_dataout(pdev, epnum); + } else { + usb_dev_hid_dataout(pdev, epnum); + } +} + +/** + * @brief processing for sof + * @param [in] pdev Device instance + * @retval status + */ +uint8_t usb_dev_composite_sof(void *pdev) + +{ + return (usb_dev_cdc_sof(pdev)); +} + +/** + * @brief processing for rxready of control endpoint + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_rxready(void *pdev) +{ + usb_dev_cdc_ctrlep_rxready(pdev); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h new file mode 100644 index 0000000000..1f9a5468aa --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h @@ -0,0 +1,74 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_cdc_wrapper.h + * @brief Head file for usb_dev_hid_cdc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_HID_CDC_WRAPPER_H_ +#define __USB_DEV_HID_CDC_WRAPPER_H_ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_HID_CDC_WRAPPER_H_ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c new file mode 100644 index 0000000000..fcb8efd20c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c @@ -0,0 +1,330 @@ +/** + ******************************************************************************* + * @file usb_dev_keyboard_class.c + * @brief HID keyboard functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_keyboard_class.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_KEYBOARD USB Device HID Keyboard + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_keyboard_init(void *pdev); +void usb_dev_keyboard_deinit(void *pdev); +uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length); +void usb_dev_keyboard_datain(void *pdev, uint8_t epnum); +void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_keyboard_cbk = { + &usb_dev_keyboard_init, + &usb_dev_keyboard_deinit, + &usb_dev_keyboard_setup, + NULL, + NULL, + &usb_dev_keyboard_getcfgdesc, + NULL, + &usb_dev_keyboard_datain, + &usb_dev_keyboard_dataout, + NULL, + NULL +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_AltSet = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_Protocol = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_IdleState = 0UL; + +/* USB HID device Configuration Descriptor */ +__USB_ALIGN_BEGIN static uint8_t USB_DEV_KEYBOARD_CfgDesc[KEYBOARD_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + KEYBOARD_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus*/ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x10, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x21, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + 0x08, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms)*/ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType:*/ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms)*/ + /* 41 */ +} ; + +__USB_ALIGN_BEGIN static uint8_t HID_KEYBOARD_ReportDesc[KEYBOARD_REPORT_DESC_SIZE] = { + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x06, /* USAGE (Keyboard) */ + 0xA1, 0x01, /* COLLECTION (Application) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0x00, /* USAGE_MAXIMUM (Reserved (no event indicated)) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs) */ + 0x95, 0x06, /* REPORT_COUNT (6) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0xE7, /* USAGE_MAXIMUM (Keyboard Right GUI) */ + 0x81, 0x00, /* INPUT (Data,Ary,Abs) */ + 0x15, 0x01, /* LOGICAL_MINIMUM (1) */ + 0x95, 0x05, /* REPORT_COUNT (5) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x05, 0x08, /* USAGE_PAGE (LEDs) */ + 0x19, 0x01, /* USAGE_MINIMUM (Num Lock) */ + 0x29, 0x05, /* USAGE_MAXIMUM (Kana) */ + 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x03, /* REPORT_SIZE (3) */ + 0x91, 0x03, /* OUTPUT (Cnst,Var,Abs) */ + 0xC0 /* END_COLLECTION */ +}; + +__IO static uint8_t u8KeyRevBuf[64]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the interface of KEYBOARD HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_keyboard_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, 8U, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief DeInitialize the interface of KEYBOARD HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_keyboard_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the KEYBOARD HID SETUP request + * @param [in] pdev device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case KEYBOARD_REQ_SET_PROTOCOL: + USB_DEV_KEYBOARD_Protocol = (uint8_t)(req->wValue); + break; + case KEYBOARD_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_Protocol, 1U); + break; + case KEYBOARD_REQ_SET_IDLE: + USB_DEV_KEYBOARD_IdleState = (uint8_t)(req->wValue >> 8U); + break; + case KEYBOARD_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_IdleState, 1U); + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_REPORT_DESC) { + len = (uint16_t)LL_MIN(KEYBOARD_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_KEYBOARD_ReportDesc; + } else if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_DESCRIPTOR_TYPE) { + pbuf = USB_DEV_KEYBOARD_CfgDesc + 0x12; + len = (uint16_t)LL_MIN(KEYBOARD_DESC_SIZE, req->wLength); + } else { + ; + } + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_KEYBOARD_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Send KEYBOARD HID report to the host + * @param [in] pdev device instance + * @param [in] report pointer to the report buffer + * @param [in] len the length of the report buffer in bytes + * @retval status + */ +uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len); + } + return USB_DEV_OK; +} + +/** + * @brief get the configuration descriptor + * @param [in] length pointer data length of the configuration descriptor in bytes + * @retval pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USB_DEV_KEYBOARD_CfgDesc); + return USB_DEV_KEYBOARD_CfgDesc; +} + +/** + * @brief handle the IN data Stage + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_keyboard_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); +} + +/** + * @brief handle the OUT data Stage + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum) +{ + usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h new file mode 100644 index 0000000000..be1ac78613 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h @@ -0,0 +1,101 @@ +/** + ******************************************************************************* + * @file usb_dev_keyboard_class.h + * @brief Head file for usb_dev_keyboard_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_KEYBOARD_CLASS_H__ +#define __USB_DEV_KEYBOARD_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_KEYBOARD + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define KEYBOARD_CFGDESC_SIZE (41U) +#define KEYBOARD_DESC_SIZE (9U) +#define KEYBOARD_REPORT_DESC_SIZE (66U) + +#define KEYBOARD_DESCRIPTOR_TYPE (0x21U) +#define KEYBOARD_REPORT_DESC (0x22U) + + +#define KEYBOARD_REQ_SET_PROTOCOL (0x0BU) +#define KEYBOARD_REQ_GET_PROTOCOL (0x03U) + +#define KEYBOARD_REQ_SET_IDLE (0x0AU) +#define KEYBOARD_REQ_GET_IDLE (0x02U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_keyboard_cbk; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_KEYBOARD_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c new file mode 100644 index 0000000000..df92d3caaf --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c @@ -0,0 +1,345 @@ +/** + ******************************************************************************* + * @file usb_dev_mouse_class.c + * @brief HID mouse functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_mouse_class.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_desc.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MOUSE USB Device HID Mouse + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_mouse_init(void *pdev); +void usb_dev_mouse_deinit(void *pdev); +uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length); +void usb_dev_mouse_datain(void *pdev, uint8_t epnum); +void usb_dev_mouse_dataout(void *pdev, uint8_t epnum); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_mouse_cbk = { + &usb_dev_mouse_init, + &usb_dev_mouse_deinit, + &usb_dev_mouse_setup, + NULL, + NULL, + &usb_dev_mouse_getcfgdesc, + NULL, + &usb_dev_mouse_datain, + &usb_dev_mouse_dataout, + NULL, + NULL +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_AltSet = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_Protocol = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_IdleState = 0UL; + +/* USB HID device Configuration Descriptor */ +__USB_ALIGN_BEGIN static uint8_t USB_DEV_MOUSE_CfgDesc[MOUSE_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + MOUSE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ +} ; + +__USB_ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, + 0x09, 0x02, + 0xA1, 0x01, + 0x09, 0x01, + + 0xA1, 0x00, + 0x05, 0x09, + 0x19, 0x01, + 0x29, 0x03, + + 0x15, 0x00, + 0x25, 0x01, + 0x95, 0x03, + 0x75, 0x01, + + 0x81, 0x02, + 0x95, 0x01, + 0x75, 0x05, + 0x81, 0x01, + + 0x05, 0x01, + 0x09, 0x30, + 0x09, 0x31, + 0x09, 0x38, + + 0x15, 0x81, + 0x25, 0x7F, + 0x75, 0x08, + 0x95, 0x03, + + 0x81, 0x06, + 0xC0, 0x09, + 0x3C, 0x05, + 0xFF, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xB1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xB1, + + 0x01, 0xC0 +}; + +static uint8_t u8HidRevBuf[4]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the interface of MOUSE HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_mouse_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief DeInitialize the interface of MOUSE HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_mouse_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the MOUSE HID SETUP request + * @param [in] pdev device instance + * @param [in] req: usb requests + * @retval status + */ +uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case MOUSE_REQ_SET_PROTOCOL: + USB_DEV_MOUSE_Protocol = (uint8_t)(req->wValue); + break; + case MOUSE_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_Protocol, 1U); + break; + case MOUSE_REQ_SET_IDLE: + USB_DEV_MOUSE_IdleState = (uint8_t)(req->wValue >> 8U); + break; + case MOUSE_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_IdleState, 1U); + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8U) == (uint16_t)MOUSE_REPORT_DESC) { + len = (uint16_t)LL_MIN(MOUSE_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } else if ((req->wValue >> 8U) == (uint16_t)MOUSE_DESCRIPTOR_TYPE) { + pbuf = USB_DEV_MOUSE_CfgDesc + 0x12; + len = (uint16_t)LL_MIN(MOUSE_DESC_SIZE, req->wLength); + } else { + ; + } + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_MOUSE_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Send MOUSE HID report to the host + * @param [in] pdev device instance + * @param [in] report pointer to the report buffer + * @param [in] length the length of the report buffer in bytes + * @retval status + */ +uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t length) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)length); + } + return USB_DEV_OK; +} + +/** + * @brief get the configuration descriptor + * @param [in] length pointer data length of the configuration descriptor in bytes + * @retval pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USB_DEV_MOUSE_CfgDesc); + return USB_DEV_MOUSE_CfgDesc; +} + +/** + * @brief handle the IN data Stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_mouse_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); +} + +/** + * @brief handle the OUT data Stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_mouse_dataout(void *pdev, uint8_t epnum) +{ + usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h new file mode 100644 index 0000000000..9a6dbb6806 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h @@ -0,0 +1,101 @@ +/** + ******************************************************************************* + * @file usb_dev_mouse_class.h + * @brief header file for the usb_dev_mouse_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MOUSE_CLASS_H__ +#define __USB_DEV_MOUSE_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MOUSE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MOUSE_CFGDESC_SIZE (41U) +#define MOUSE_DESC_SIZE (9U) +#define MOUSE_REPORT_DESC_SIZE (74U) + +#define MOUSE_DESCRIPTOR_TYPE (0x21U) +#define MOUSE_REPORT_DESC (0x22U) + + +#define MOUSE_REQ_SET_PROTOCOL (0x0BU) +#define MOUSE_REQ_GET_PROTOCOL (0x03U) + +#define MOUSE_REQ_SET_IDLE (0x0AU) +#define MOUSE_REQ_GET_IDLE (0x02U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_mouse_cbk; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MOUSE_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c new file mode 100644 index 0000000000..1151aa2161 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c @@ -0,0 +1,273 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_msc_wrapper.c + * @brief MSC_HID composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_hid_msc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE USB Device HID MSC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_msc_hid_init(void *pdev); +void usb_dev_msc_hid_deinit(void *pdev); +uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum); +void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum); +uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_composite_cbk = { + &usb_dev_msc_hid_init, + &usb_dev_msc_hid_deinit, + &usb_dev_msc_hid_setup, + NULL, + NULL, + &usb_dev_msc_hid_getcfgdesc, + NULL, + &usb_dev_msc_hid_datain, + &usb_dev_msc_hid_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_hid_cfgdesc[USB_MSC_HID_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_HID_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /************** Descriptor of HID interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of HID endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 41 */ + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds */ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_hid_init(void *pdev) +{ + usb_dev_hid_init(pdev); + usb_dev_msc_init(pdev); +} + +/** + * @brief de-initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_hid_deinit(void *pdev) +{ + usb_dev_hid_deinit(pdev); + usb_dev_msc_deinit(pdev); +} + +/** + * @brief process the setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == 0U) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_datain(pdev, epnum); + } else { + usb_dev_hid_datain(pdev, epnum); + } +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_dataout(pdev, epnum); + } else { + usb_dev_hid_dataout(pdev, epnum); + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_hid_cfgdesc); + return usb_dev_msc_hid_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h new file mode 100644 index 0000000000..dfcf66c191 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h @@ -0,0 +1,80 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_msc_wrapper.h + * @brief header file for the usb_dev_hid_msc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_HID_MSC_WRAPPER_H__ +#define __USB_DEV_HID_MSC_WRAPPER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_HID_MSC_WRAPPER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c new file mode 100644 index 0000000000..9917749fcb --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c @@ -0,0 +1,267 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_bot.c + * @brief USB DEV bulk only transfer functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_bot.h" +#include "usb_dev_msc_scsi.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_msc_mem.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC USB Device MSC + * @{ + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +uint16_t MSC_BOT_DataLen; +uint8_t MSC_BOT_State; +static uint8_t MSC_BOT_Status; + +__USB_ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET]; + +__USB_ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw; + +__USB_ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Send the requested data + * @param [in] pdev device instance + * @param [in] buf pointer for data buffer + * @param [in] length data Length in bytes + * @retval None + */ +static void msc_bot_txdata(usb_core_instance *pdev, uint8_t *buf, uint16_t length) +{ + length = (uint16_t)LL_MIN(MSC_BOT_cbw.dDataLength, length); + MSC_BOT_csw.dDataResidue -= length; + MSC_BOT_csw.bStatus = CSW_CMD_PASSED; + MSC_BOT_State = BOT_SEND_DATA; + usb_deveptx(pdev, MSC_IN_EP, buf, (uint32_t)length); +} + +/** + * @brief abort current transfer + * @param [in] pdev device instance + * @retval None + */ +static void msc_bot_abort(usb_core_instance *pdev) +{ + if ((MSC_BOT_cbw.bmFlags == (uint8_t)0) && + (MSC_BOT_cbw.dDataLength != (uint32_t)0) && + (MSC_BOT_Status == BOT_STATE_NORMAL)) { + usb_stalldevep(pdev, MSC_OUT_EP); + } + usb_stalldevep(pdev, MSC_IN_EP); + if (MSC_BOT_Status == BOT_STATE_ERROR) { + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); + } +} + +/** + * @brief decodes the CBW command and set the BOT state machine accordingly + * @param [in] pdev device instance + * @retval None + */ +static void msc_bot_decode_cbw(usb_core_instance *pdev) +{ + + MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; + MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; + + if ((usb_getrxcnt(pdev, MSC_OUT_EP) != BOT_CBW_LENGTH) || + (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE) || + (MSC_BOT_cbw.bLUN > 1U) || + (MSC_BOT_cbw.bCBLength < 1U) || + (MSC_BOT_cbw.bCBLength > 16U)) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + MSC_BOT_Status = BOT_STATE_ERROR; + msc_bot_abort(pdev); + + } else { + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_abort(pdev); + } else if ((MSC_BOT_State != BOT_DATA_IN) && + (MSC_BOT_State != BOT_DATA_OUT) && + (MSC_BOT_State != BOT_LAST_DATA_IN)) { + if (MSC_BOT_DataLen > (uint16_t)0) { + msc_bot_txdata(pdev, MSC_BOT_Data, MSC_BOT_DataLen); + } else { + msc_bot_txcsw(pdev, CSW_CMD_PASSED); + } + } else { + ; + } + } +} + +/** + * @brief initialize the BOT Process + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_init(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_NORMAL; + msc_fops->Init(0U); + + usb_flsdevep(pdev, MSC_OUT_EP); + usb_flsdevep(pdev, MSC_IN_EP); + /* Prapare EP to Receive First BOT command */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief resets the BOT Machine + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_rst(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_RECOVERY; + /* Prapare OUT EP to Receive First BOT command */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief deinitialize the BOT Machine + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_deinit(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; +} + +/** + * @brief process BOT IN data stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) { + case BOT_DATA_IN: + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } + break; + case BOT_SEND_DATA: + case BOT_LAST_DATA_IN: + msc_bot_txcsw(pdev, CSW_CMD_PASSED); + break; + default: + break; + } +} + +/** + * @brief proccess MSC OUT data stage + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) { + case BOT_IDLE: + msc_bot_decode_cbw(pdev); + break; + case BOT_DATA_OUT: + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } + break; + default: + break; + } +} + +/** + * @brief send the Command Status Wrapper + * @param [in] pdev device instance + * @param [in] CSW_Status CSW status + * @retval None + */ +void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status) +{ + MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; + MSC_BOT_csw.bStatus = CSW_Status; + MSC_BOT_State = BOT_IDLE; + usb_deveptx(pdev, MSC_IN_EP, (uint8_t *)&MSC_BOT_csw, BOT_CSW_LENGTH); + /* Prapare EP to Receive next Cmd */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief Complete the clear feature request + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum) +{ + if (MSC_BOT_Status == BOT_STATE_ERROR) { + usb_stalldevep(pdev, MSC_IN_EP); + MSC_BOT_Status = BOT_STATE_NORMAL; + } else if (((epnum & 0x80U) == 0x80U) && (MSC_BOT_Status != BOT_STATE_RECOVERY)) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } else { + ; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h new file mode 100644 index 0000000000..a9fb1d0c33 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h @@ -0,0 +1,137 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_bot.h + * @brief header file for the usb_dev_msc_bot.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_BOT_H__ +#define __USB_DEV_MSC_BOT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_core.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} MSC_BOT_CBW_TypeDef; + +typedef struct { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} MSC_BOT_CSW_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define BOT_IDLE (0U) /* Idle state */ +#define BOT_DATA_OUT (1U) /* Data Out state */ +#define BOT_DATA_IN (2U) /* Data In state */ +#define BOT_LAST_DATA_IN (3U) /* Last Data In Last */ +#define BOT_SEND_DATA (4U) /* Send Immediate data */ + +#define BOT_CBW_SIGNATURE (0x43425355UL) +#define BOT_CSW_SIGNATURE (0x53425355UL) +#define BOT_CBW_LENGTH (31U) +#define BOT_CSW_LENGTH (13U) + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED (0x00U) +#define CSW_CMD_FAILED (0x01U) +#define CSW_PHASE_ERROR (0x02U) + +/* BOT Status */ +#define BOT_STATE_NORMAL (0U) +#define BOT_STATE_RECOVERY (1U) +#define BOT_STATE_ERROR (2U) + +#define DIR_IN (0U) +#define DIR_OUT (1U) +#define BOTH_DIR (2U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET]; +extern uint16_t MSC_BOT_DataLen; +extern uint8_t MSC_BOT_State; +extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; +extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern void msc_bot_init(usb_core_instance *pdev); +extern void msc_bot_rst(usb_core_instance *pdev); +extern void msc_bot_deinit(usb_core_instance *pdev); +extern void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum); +extern void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum); +extern void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status); +extern void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_BOT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c new file mode 100644 index 0000000000..2254ddf68e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c @@ -0,0 +1,264 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_class.c + * @brief USB MSC device class + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_mem.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_msc_bot.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_msc_cbk = { + &usb_dev_msc_init, + &usb_dev_msc_deinit, + &usb_dev_msc_setup, + NULL, + NULL, + &usb_dev_msc_getcfgdesc, + NULL, + &usb_dev_msc_datain, + &usb_dev_msc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint8_t dev_msc_maxlun = 0U; +static uint8_t dev_msc_altset = 0U; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cfgdesc[USB_MSC_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_MSC_CONFIG_DESC_SIZ, + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + /******************** Mass Storage interface descriptor**********/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints descriptor**********/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds */ +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the mass storage interface configuration + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_init(void *pdev) +{ + usb_dev_msc_deinit(pdev); + usb_opendevep(pdev, MSC_IN_EP, MSC_EPIN_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, MSC_OUT_EP, MSC_EPOUT_SIZE, EP_TYPE_BULK); + msc_bot_init(pdev); +} + +/** + * @brief deinitilaize the mass storage interface configuration + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_deinit(void *pdev) +{ + usb_shutdevep(pdev, MSC_IN_EP); + usb_shutdevep(pdev, MSC_OUT_EP); + msc_bot_deinit(pdev); +} + +/** + * @brief process the msc setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) { + case BOT_GET_MAX_LUN: + if ((req->wValue == (uint16_t)0) && + (req->wLength == (uint16_t)1) && + ((req->bmRequest & 0x80U) == (uint8_t)0x80)) { + dev_msc_maxlun = msc_fops->GetMaxLun(); + if (dev_msc_maxlun > 0U) { + usb_ctrldatatx(pdev, &dev_msc_maxlun, 1U); + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + break; + case BOT_RESET: + if ((req->wValue == (uint16_t)0) && + (req->wLength == (uint16_t)0) && + ((req->bmRequest & 0x80U) != (uint8_t)0x80)) { + msc_bot_rst(pdev); + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_INTERFACE: + usb_ctrldatatx(pdev, &dev_msc_altset, 1U); + break; + case USB_REQ_SET_INTERFACE: + dev_msc_altset = (uint8_t)(req->wValue); + break; + case USB_REQ_CLEAR_FEATURE: + usb_flsdevep(pdev, (uint8_t)req->wIndex); + usb_shutdevep(pdev, (uint8_t)req->wIndex); + if ((((uint8_t)req->wIndex) & (uint16_t)0x80U) == (uint16_t)0x80) { + usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPIN_SIZE, EP_TYPE_BULK); + } else { + usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPOUT_SIZE, EP_TYPE_BULK); + } + msc_bot_complete_clearfeature(pdev, (uint8_t)req->wIndex); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_datain(void *pdev, uint8_t epnum) +{ + msc_bot_datain(pdev, epnum); +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_dataout(void *pdev, uint8_t epnum) +{ + msc_bot_dataout(pdev, epnum); +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_cfgdesc); + return usb_dev_msc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h new file mode 100644 index 0000000000..81f8b1cd57 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h @@ -0,0 +1,94 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_class.h + * @brief header file for the usb_dev_msc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_CLASS_H__ +#define __USB_DEV_MSC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define BOT_GET_MAX_LUN (0xFEU) +#define BOT_RESET (0xFFU) +#define USB_MSC_CONFIG_DESC_SIZ (32U) + +#define MSC_EPIN_SIZE (MSC_MAX_PACKET) +#define MSC_EPOUT_SIZE (MSC_MAX_PACKET) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern usb_dev_class_func usb_dev_msc_cbk; + +/* MSC Device library callbacks */ +extern void usb_dev_msc_init(void *pdev); +extern void usb_dev_msc_deinit(void *pdev); +extern uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req); +extern void usb_dev_msc_datain(void *pdev, uint8_t epnum); +extern void usb_dev_msc_dataout(void *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c new file mode 100644 index 0000000000..a29cec1307 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_data.c + * @brief This file provides all the vital inquiry pages and sense data. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_data.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/* USB Mass storage Page 0 Inquiry Data */ +const uint8_t MSC_Page00_Inquiry_Data[] = { /* 7 */ + 0x00, + 0x00, + 0x00, + (LENGTH_INQUIRY_PAGE00 - 4U), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +const uint8_t MSC_Mode_Sense6_data[] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +const uint8_t MSC_Mode_Sense10_data[] = { + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h new file mode 100644 index 0000000000..5f9c8b2c80 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h @@ -0,0 +1,92 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_data.h + * @brief header file for the usb_dev_msc_data.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_DATA_H__ +#define __USB_DEV_MSC_DATA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MODE_SENSE6_LEN (8U) +#define MODE_SENSE10_LEN (8U) +#define LENGTH_INQUIRY_PAGE00 (7U) +#define LENGTH_FORMAT_CAPACITIES (20U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern const uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00]; +extern const uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN]; +extern const uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN]; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_DATA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h new file mode 100644 index 0000000000..b301967a89 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h @@ -0,0 +1,90 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_mem.h + * @brief header file for the usb_dev_msc_mem.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_MEM_H__ +#define __USB_DEV_MSC_MEM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + int8_t (* Init)(uint8_t lun); + int8_t (* GetCapacity)(uint8_t lun, uint32_t *block_num, uint32_t *block_size); + int8_t (* GetMaxLun)(void); + int8_t (* IsReady)(uint8_t lun); + int8_t (* Read)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* IsWriteProtected)(uint8_t lun); + int8_t *pInquiry; +} USB_DEV_MSC_cbk_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_DEV_INQUIRY_LENGTH (36U) + +extern USB_DEV_MSC_cbk_TypeDef *msc_fops; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_MEM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c new file mode 100644 index 0000000000..bdbda3a025 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c @@ -0,0 +1,553 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_scsi.c + * @brief This file provides all the USBD SCSI layer functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_bot.h" +#include "usb_dev_msc_scsi.h" +#include "usb_dev_msc_mem.h" +#include "usb_dev_msc_data.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t SCSI_blk_size; +static uint32_t SCSI_blk_nbr; +static uint64_t SCSI_blk_addr; +static uint32_t SCSI_blk_len; +static usb_core_instance *cdev; + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +SCSI_Sense_TypeDef SCSI_Sense[SENSE_LIST_DEEPTH]; +uint8_t SCSI_Sense_Head; +uint8_t SCSI_Sense_Tail; + +/******************************************************************************* + * Local function prototypes + ******************************************************************************/ +int8_t scsi_testunitready(uint8_t lun); +int8_t scsi_inquiry(uint8_t lun, uint8_t *params); +int8_t scsi_readformatcapacity(uint8_t lun); +int8_t scsi_readcapacity10(uint8_t lun); +int8_t scsi_requestsense(uint8_t *params); +int8_t scsi_startstopuint(void); +int8_t scsi_modesense6(uint8_t lun); +int8_t scsi_modesense10(void); +int8_t scsi_write10(uint8_t lun, uint8_t *params); +int8_t scsi_read10(uint8_t lun, uint8_t *params); +int8_t scsi_verify10(uint8_t lun, uint8_t *params); +int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr); +int8_t scsi_processread(uint8_t lun); +int8_t scsi_processwrite(uint8_t lun); + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Processes SCSI commands + * @param [in] pdev device instance + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params) +{ + int8_t Res; + cdev = pdev; + + if (params[0] == SCSI_TEST_UNIT_READY) { + Res = scsi_testunitready(lun); + } else if (params[0] == SCSI_REQUEST_SENSE) { + Res = scsi_requestsense(params); + } else if (params[0] == SCSI_INQUIRY) { + Res = scsi_inquiry(lun, params); + } else if (params[0] == SCSI_START_STOP_UNIT) { + Res = scsi_startstopuint(); + } else if (params[0] == SCSI_ALLOW_MEDIUM_REMOVAL) { + Res = scsi_startstopuint(); + } else if (params[0] == SCSI_MODE_SENSE6) { + Res = scsi_modesense6(lun); + } else if (params[0] == SCSI_MODE_SENSE10) { + Res = scsi_modesense10(); + } else if (params[0] == SCSI_READ_FORMAT_CAPACITIES) { + Res = scsi_readformatcapacity(lun); + } else if (params[0] == SCSI_READ_CAPACITY10) { + Res = scsi_readcapacity10(lun); + } else if (params[0] == SCSI_READ10) { + Res = scsi_read10(lun, params); + } else if (params[0] == SCSI_WRITE10) { + Res = scsi_write10(lun, params); + } else if (params[0] == SCSI_VERIFY10) { + Res = scsi_verify10(lun, params); + } else { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + Res = (int8_t) -1; + } + return Res; +} + +/** + * @brief Processes SCSI Test Unit Ready Command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_testunitready(uint8_t lun) +{ + int8_t i8Ret; + i8Ret = (int8_t)0; + /* case 9 : Hi > D0 */ + if (MSC_BOT_cbw.dDataLength != 0U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_DataLen = 0U; + } + } + return i8Ret; +} + +/** + * @brief Processes inquiry command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_inquiry(uint8_t lun, uint8_t *params) +{ + const uint8_t *pPage; + uint16_t len; + + if ((params[1] & 0x01U) != 0U) { + pPage = (const uint8_t *)MSC_Page00_Inquiry_Data; + len = LENGTH_INQUIRY_PAGE00; + } else { + + pPage = (uint8_t *)&msc_fops->pInquiry[lun * USB_DEV_INQUIRY_LENGTH]; + len = (uint16_t)pPage[4] + (uint16_t)5; + + if (params[4] <= len) { + len = params[4]; + } + } + MSC_BOT_DataLen = len; + + while (len != 0U) { + len--; + MSC_BOT_Data[len] = pPage[len]; + } + return (int8_t)0; +} + +/** + * @brief Processes Read Capacity10 command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_readcapacity10(uint8_t lun) +{ + int8_t i8Ret = (int8_t)0; + if (msc_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1U) >> 24U); + MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1U) >> 16U); + MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1U) >> 8U); + MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1U); + + MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24U); + MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16U); + MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8U); + MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); + MSC_BOT_DataLen = 8U; + } + return i8Ret; +} + +/** + * @brief Processes Read Format Capacity command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_readformatcapacity(uint8_t lun) +{ + int8_t i8Ret = (int8_t)0; + uint32_t blk_size; + uint32_t blk_nbr; + uint16_t i; + + i = 0U; + while (i < 12U) { + MSC_BOT_Data[i++] = 0U; + } + + if (msc_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_Data[3] = 0x08U; + MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1U) >> 24U); + MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1U) >> 16U); + MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1U) >> 8U); + MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1U); + + MSC_BOT_Data[8] = 0x02U; + MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16U); + MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8U); + MSC_BOT_Data[11] = (uint8_t)(blk_size); + + MSC_BOT_DataLen = 12U; + } + return i8Ret; +} + +/** + * @brief Processes Mode Sense6 command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_modesense6(uint8_t lun) +{ + uint16_t len; + len = 8U; + MSC_BOT_DataLen = len; + while (0U != len) { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; + } + return (int8_t)0; +} + +/** + * @brief processes Mode Sense10 command + * @param None + * @retval status + */ +int8_t scsi_modesense10(void) +{ + uint16_t len = 8U; + + MSC_BOT_DataLen = len; + while (0U != len) { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; + } + return (int8_t)0; +} + +/** + * @brief processes Request Sense command + * @param [in] params command + * @retval status + */ +int8_t scsi_requestsense(uint8_t *params) +{ + uint8_t i; + + i = 0U; + while (i < REQUEST_SENSE_DATA_LEN) { + MSC_BOT_Data[i++] = 0U; + } + MSC_BOT_Data[0] = 0x70U; + MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6U; + if ((SCSI_Sense_Head != SCSI_Sense_Tail)) { + MSC_BOT_Data[2] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].Skey; + MSC_BOT_Data[12] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; + MSC_BOT_Data[13] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASC; + SCSI_Sense_Head++; + if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) { + SCSI_Sense_Head = 0U; + } + } + MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; + if (params[4] <= REQUEST_SENSE_DATA_LEN) { + MSC_BOT_DataLen = params[4]; + } + return (int8_t)0; +} + +/** + * @brief Loads the last error code in the error list + * @param [in] sKey Sense Key + * @param [in] ASC Additional Sense Key + * @retval None + */ +void scsi_sensecode(uint8_t sKey, uint8_t ASC) +{ + SCSI_Sense[SCSI_Sense_Tail].Skey = (char)sKey; + SCSI_Sense[SCSI_Sense_Tail].w.ASC = (uint32_t)ASC << 8U; + SCSI_Sense_Tail++; + if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) { + SCSI_Sense_Tail = 0U; + } +} + +/** + * @brief processes Start Stop Unit command + * @param None + * @retval status + */ +int8_t scsi_startstopuint(void) +{ + MSC_BOT_DataLen = 0U; + return (int8_t)0; +} + +/** + * @brief processes Read10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_read10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret = (int8_t)0; + if (MSC_BOT_State == BOT_IDLE) { + /* case 10 : Ho <> Di */ + if ((MSC_BOT_cbw.bmFlags & 0x80U) != 0x80U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \ + ((uint64_t)params[3] << 16U) | \ + ((uint64_t)params[4] << 8U) | \ + (uint64_t)params[5]; + + SCSI_blk_len = ((uint32_t)params[7] << 8U) | \ + (uint32_t)params[8]; + + + if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) { + i8Ret = (int8_t) -1; /* error */ + } else { + MSC_BOT_State = BOT_DATA_IN; + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + /* cases 4,5 : Hi <> Dn */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } + } + } + } + if (((int8_t) -1) != i8Ret) { + MSC_BOT_DataLen = (uint16_t)MSC_MEDIA_PACKET; + i8Ret = scsi_processread(lun); + } + return i8Ret; +} + +/** + * @brief processes Write10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_write10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret = (int8_t)0; + if (MSC_BOT_State == BOT_IDLE) { + /* case 8 : Hi <> Do */ + if ((MSC_BOT_cbw.bmFlags & 0x80U) == 0x80U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } + /* Check If media is write-protected */ + else if (msc_fops->IsWriteProtected(lun) != 0U) { + scsi_sensecode(NOT_READY, WRITE_PROTECTED); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \ + ((uint64_t)params[3] << 16U) | \ + ((uint64_t)params[4] << 8U) | \ + (uint64_t)params[5]; + SCSI_blk_len = ((uint32_t)params[7] << 8U) | \ + (uint32_t)params[8]; + /* check if LBA address is in the right range */ + if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) { + i8Ret = (int8_t) -1; /* error */ + } else { + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + /* Prepare EP to receive first data packet */ + MSC_BOT_State = BOT_DATA_OUT; + usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET)); + } + } + } + } + } else { /* Write Process ongoing */ + i8Ret = scsi_processwrite(lun); + } + return i8Ret; +} + +/** + * @brief processes Verify10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_verify10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret; + + i8Ret = (int8_t)0; + if ((params[1] & 0x02U) == 0x02U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + i8Ret = (int8_t) -1; /* Error, Verify Mode Not supported */ + } else if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < (int8_t)0) { + i8Ret = (int8_t) -1; /* error */ + } else { + MSC_BOT_DataLen = 0U; + } + return i8Ret; +} + +/** + * @brief checks the address range + * @param [in] blk_offset first block address + * @param [in] blk_nbr number of block to be processed + * @retval status + */ +int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr) +{ + int8_t i8Ret = (int8_t)0; + if ((blk_offset + blk_nbr) > SCSI_blk_nbr) { + scsi_sensecode(ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + i8Ret = (int8_t) -1; + } + return i8Ret; +} + +/** + * @brief handles Read Process + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_processread(uint8_t lun) +{ + uint32_t len; + int8_t i8Ret = (int8_t)0; + + len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET); + + if (SCSI_blk_size == 0U) { + i8Ret = (int8_t) -1; + } else if (msc_fops->Read(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) { + scsi_sensecode(HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + i8Ret = (int8_t) -1; + } else { + usb_deveptx(cdev, MSC_IN_EP, MSC_BOT_Data, len); + SCSI_blk_addr += len; + SCSI_blk_len -= len; + /* case 6 : Hi = Di */ + MSC_BOT_csw.dDataResidue -= len; + if (SCSI_blk_len == 0U) { + MSC_BOT_State = BOT_LAST_DATA_IN; + } + } + return i8Ret; +} + +/** + * @brief handles Write Process + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_processwrite(uint8_t lun) +{ + uint32_t len; + int8_t i8Ret = (int8_t)0; + + len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET); + + if (SCSI_blk_size == 0U) { + i8Ret = (int8_t) -1; + } else if (msc_fops->Write(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) { + scsi_sensecode(HARDWARE_ERROR, WRITE_FAULT); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr += len; + SCSI_blk_len -= len; + /* case 12 : Ho = Do */ + MSC_BOT_csw.dDataResidue -= len; + if (SCSI_blk_len == 0U) { + msc_bot_txcsw(cdev, CSW_CMD_PASSED); + } else { + /* Prapare EP to Receive next packet */ + usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET)); + } + } + return i8Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h new file mode 100644 index 0000000000..e8b62cdbb0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h @@ -0,0 +1,167 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_scsi.h + * @brief header file for the usb_dev_msc_scsi.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_SCSI_H__ +#define __USB_DEV_MSC_SCSI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct _SENSE_ITEM { + char Skey; + union { + struct _ASCs { + char ASC; + char ASCQ; + } b; + unsigned int ASC; + char *pData; + } w; +} SCSI_Sense_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define SENSE_LIST_DEEPTH (4U) + +/* SCSI Commands */ +#define SCSI_FORMAT_UNIT (0x04U) +#define SCSI_INQUIRY (0x12U) +#define SCSI_MODE_SELECT6 (0x15U) +#define SCSI_MODE_SELECT10 (0x55U) +#define SCSI_MODE_SENSE6 (0x1AU) +#define SCSI_MODE_SENSE10 (0x5AU) +#define SCSI_ALLOW_MEDIUM_REMOVAL (0x1EU) +#define SCSI_READ6 (0x08U) +#define SCSI_READ10 (0x28U) +#define SCSI_READ12 (0xA8U) +#define SCSI_READ16 (0x88U) + +#define SCSI_READ_CAPACITY10 (0x25U) +#define SCSI_READ_CAPACITY16 (0x9EU) + +#define SCSI_REQUEST_SENSE (0x03U) +#define SCSI_START_STOP_UNIT (0x1BU) +#define SCSI_TEST_UNIT_READY (0x00U) +#define SCSI_WRITE6 (0x0AU) +#define SCSI_WRITE10 (0x2AU) +#define SCSI_WRITE12 (0xAAU) +#define SCSI_WRITE16 (0x8AU) + +#define SCSI_VERIFY10 (0x2FU) +#define SCSI_VERIFY12 (0xAFU) +#define SCSI_VERIFY16 (0x8FU) + +#define SCSI_SEND_DIAGNOSTIC (0x1DU) +#define SCSI_READ_FORMAT_CAPACITIES (0x23U) + +#define NO_SENSE (0U) +#define RECOVERED_ERROR (1U) +#define NOT_READY (2U) +#define MEDIUM_ERROR (3U) +#define HARDWARE_ERROR (4U) +#define ILLEGAL_REQUEST (5U) +#define UNIT_ATTENTION (6U) +#define DATA_PROTECT (7U) +#define BLANK_CHECK (8U) +#define VENDOR_SPECIFIC (9U) +#define COPY_ABORTED (10U) +#define ABORTED_COMMAND (11U) +#define VOLUME_OVERFLOW (13U) +#define MISCOMPARE (14U) + +#define INVALID_CDB (0x20U) +#define INVALID_FIELED_IN_COMMAND (0x24U) +#define PARAMETER_LIST_LENGTH_ERROR (0x1AU) +#define INVALID_FIELD_IN_PARAMETER_LIST (0x26U) +#define ADDRESS_OUT_OF_RANGE (0x21U) +#define MEDIUM_NOT_PRESENT (0x3AU) +#define MEDIUM_HAVE_CHANGED (0x28U) +#define WRITE_PROTECTED (0x27U) +#define UNRECOVERED_READ_ERROR (0x11U) +#define WRITE_FAULT (0x03U) + +#define READ_FORMAT_CAPACITY_DATA_LEN (0x0Cu) +#define READ_CAPACITY10_DATA_LEN (0x08U) +#define MODE_SENSE10_DATA_LEN (0x08U) +#define MODE_SENSE6_DATA_LEN (0x04U) +#define REQUEST_SENSE_DATA_LEN (0x12U) +#define STANDARD_INQUIRY_DATA_LEN (0x24U) +#define BLKVFY (0x04U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +extern uint8_t SCSI_Sense_Head; +extern uint8_t SCSI_Sense_Tail; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params); +extern void scsi_sensecode(uint8_t sKey, uint8_t ASC); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_SCSI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c new file mode 100644 index 0000000000..aabb0371e6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c @@ -0,0 +1,427 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_class.c + * @brief The CDC VCP core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_cdc_class.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_desc.h" +#include "cdc_data_process.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_SINGLE_CDC USB Device CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length); +void process_asynchdata_uart2usb(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func class_cdc_cbk = { + &usb_dev_cdc_init, + &usb_dev_cdc_deinit, + &usb_dev_cdc_setup, + NULL, + &usb_dev_cdc_ctrlep_rxready, + &usb_dev_cdc_getcfgdesc, + &usb_dev_cdc_sof, + &usb_dev_cdc_datain, + &usb_dev_cdc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t alternate_setting = 0UL; +__USB_ALIGN_BEGIN static uint8_t usb_rx_buffer[MAX_CDC_PACKET_SIZE]; +uint8_t uart_rx_buffer[APP_RX_DATA_SIZE]; /* used as a buffer for receiving data from uart port */ +__USB_ALIGN_BEGIN static uint8_t CmdBuff[CDC_CMD_PACKET_SIZE]; +uint32_t APP_Rx_ptr_in = 0UL; +uint32_t APP_Rx_ptr_out = 0UL; +static uint32_t APP_Rx_length = 0UL; +static uint8_t USB_Tx_State = 0U; +static uint32_t cdcCmd = 0xFFUL; +static uint32_t cdcLen = 0UL; +static uint32_t LastPackLen = 0UL; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_cdc_cfgdesc[USB_CDC_CONFIG_DESC_SIZ] = { + 0x09, + USB_CFG_DESCRIPTOR_TYPE, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, + 0x01, + 0x00, + 0xC0, + 0x32, + + 0x08, + 0x0B, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x04, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x00, + 0x00, + 0x01, + 0x02, + 0x02, + 0x01, + 0x00, + + 0x05, + 0x24, + 0x00, + 0x10, + 0x01, + + 0x05, + 0x24, + 0x01, + 0x00, + 0x01, + + 0x04, + 0x24, + 0x02, + 0x02, + + 0x05, + 0x24, + 0x06, + 0x00, + 0x01, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_CMD_EP, + 0x03, + LOBYTE(CDC_CMD_PACKET_SIZE), + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x01, + 0x00, + 0x02, + 0x0A, + 0x00, + 0x00, + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_OUT_EP, + 0x02, + LOBYTE(MAX_CDC_PACKET_SIZE), + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_IN_EP, + 0x02, + LOBYTE(MAX_CDC_PACKET_SIZE), + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00 +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Initilaize the CDC application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_cdc_init(void *pdev) +{ + usb_opendevep(pdev, CDC_IN_EP, MAX_CDC_IN_PACKET_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, CDC_OUT_EP, MAX_CDC_OUT_PACKET_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, CDC_CMD_EP, CDC_CMD_PACKET_SIZE, EP_TYPE_INTR); + vcp_init(); + usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE); +} + +/** + * @brief Deinitialize the CDC application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_cdc_deinit(void *pdev) +{ + usb_shutdevep(pdev, CDC_IN_EP); + usb_shutdevep(pdev, CDC_OUT_EP); + usb_shutdevep(pdev, CDC_CMD_EP); + vcp_deinit(); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = USB_CDC_DESC_SIZ; + uint8_t *pbuf = usb_dev_cdc_cfgdesc + 9; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + if (req->wLength != 0U) { + if ((req->bmRequest & 0x80U) != 0U) { + vcp_ctrlpare(req->bRequest, CmdBuff, req->wLength); + usb_ctrldatatx(pdev, CmdBuff, req->wLength); + } else { + cdcCmd = req->bRequest; + cdcLen = req->wLength; + usb_ctrldatarx(pdev, CmdBuff, req->wLength); + } + } else { + vcp_ctrlpare(req->bRequest, NULL, 0UL); + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == CDC_DESCRIPTOR_TYPE) { + pbuf = usb_dev_cdc_cfgdesc + 9U + (9U * USBD_ITF_MAX_NUM); + len = LL_MIN(USB_CDC_DESC_SIZ, req->wLength); + } + usb_ctrldatatx(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&alternate_setting, 1U); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) { + alternate_setting = (uint8_t)(req->wValue); + } else { + usb_ctrlerr(pdev); + } + break; + default: + break; + } + break; + + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + return u8Res; +} + +/** + * @brief Data received on control endpoint + * @param [in] pdev device device instance + * @retval None + */ +void usb_dev_cdc_ctrlep_rxready(void *pdev) +{ + if (cdcCmd != NO_CMD) { + vcp_ctrlpare(cdcCmd, CmdBuff, cdcLen); + cdcCmd = NO_CMD; + } +} + +/** + * @brief Data sent on non-control IN endpoint + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_cdc_datain(void *pdev, uint8_t epnum) +{ + uint16_t tx2usb_ptr; + uint16_t tx2usb_length; + + if (USB_Tx_State == 1U) { + if (APP_Rx_length == 0U) { + if (LastPackLen == MAX_CDC_IN_PACKET_SIZE) { + usb_deveptx(pdev, CDC_IN_EP, NULL, 0UL); + LastPackLen = 0UL; + } else { + USB_Tx_State = 0U; + } + } else { + if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)MAX_CDC_IN_PACKET_SIZE - 1U; + APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1U; + APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1U; + } else { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)APP_Rx_length; + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0U; + } + usb_deveptx(pdev, + CDC_IN_EP, + (uint8_t *)&uart_rx_buffer[tx2usb_ptr], + (uint32_t)tx2usb_length); + LastPackLen = (uint32_t)tx2usb_length; + } + } +} + +/** + * @brief Data received on non-control Out endpoint + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_cdc_dataout(void *pdev, uint8_t epnum) +{ + uint16_t usb_rx_cnt; + + usb_rx_cnt = (uint16_t)((usb_core_instance *)pdev)->dev.out_ep[epnum].xfer_count; + vcp_rxdata(usb_rx_buffer, usb_rx_cnt); + usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE); +} + +/** + * @brief Start Of Frame event management + * @param [in] pdev Device instance + * @retval status + */ +uint8_t usb_dev_cdc_sof(void *pdev) +{ + static uint32_t FrameCount = 0UL; + + if (FrameCount++ == CDC_IN_FRAME_INTERVAL) { + FrameCount = 0UL; + process_asynchdata_uart2usb(pdev); + } + return USB_DEV_OK; +} + +/** + * @brief process the data received from usart and send through USB to host + * @param [in] pdev device instance + * @retval None + */ +void process_asynchdata_uart2usb(void *pdev) +{ + uint16_t tx2usb_ptr; /* the location of the pointer in buffer that would be sent to USB */ + uint16_t tx2usb_length; /* the length in bytes that would be sent to USB */ + + if (USB_Tx_State != 1U) { + if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) { + APP_Rx_ptr_out = 0UL; + } + if (APP_Rx_ptr_out == APP_Rx_ptr_in) { + USB_Tx_State = 0U; + } else { + if (APP_Rx_ptr_out > APP_Rx_ptr_in) { + APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; + } else { + APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; + } + + if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = MAX_CDC_IN_PACKET_SIZE - 1U; + + APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1UL; + APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1UL; + } else { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0UL; + } + USB_Tx_State = 1U; + + usb_deveptx(pdev, + CDC_IN_EP, + (uint8_t *)&uart_rx_buffer[tx2usb_ptr], + (uint32_t)tx2usb_length); + LastPackLen = (uint32_t)tx2usb_length; + } + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of configuration descriptor in bytes + * @retval the pointer to configuration descriptor buffer + */ +uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_cdc_cfgdesc); + return usb_dev_cdc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h new file mode 100644 index 0000000000..5d19559dfc --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h @@ -0,0 +1,121 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_class.h + * @brief Head file for usb_dev_cdc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CDC_CLASS_H__ +#define __USB_DEV_CDC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_SINGLE_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_CDC_CONFIG_DESC_SIZ (75U) +#define USB_CDC_DESC_SIZ (75U-9U) + +#define CDC_DESCRIPTOR_TYPE (0x21U) + +#define DEVICE_CLASS_CDC (0x02U) +#define DEVICE_SUBCLASS_CDC (0x00U) + +#define STANDARD_ENDPOINT_DESC_SIZE (0x09U) + +#define MAX_CDC_IN_PACKET_SIZE (MAX_CDC_PACKET_SIZE) + +#define MAX_CDC_OUT_PACKET_SIZE (MAX_CDC_PACKET_SIZE) + +/**************************************************/ +/* CDC Requests */ +/**************************************************/ +#define SEND_ENCAPSULATED_COMMAND (0x00U) +#define GET_ENCAPSULATED_RESPONSE (0x01U) +#define SET_COMM_FEATURE (0x02U) +#define GET_COMM_FEATURE (0x03U) +#define CLEAR_COMM_FEATURE (0x04U) +#define SET_LINE_CODING (0x20U) +#define GET_LINE_CODING (0x21U) +#define SET_CONTROL_LINE_STATE (0x22U) +#define SEND_BREAK (0x23U) +#define NO_CMD (0xFFU) + +extern uint8_t uart_rx_buffer[APP_RX_DATA_SIZE]; +extern uint32_t APP_Rx_ptr_in; +extern uint32_t APP_Rx_ptr_out; +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_cdc_cbk; + +/* CDC Device library callbacks */ +extern void usb_dev_cdc_init(void *pdev);; +extern void usb_dev_cdc_deinit(void *pdev); +extern uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req); +extern void usb_dev_cdc_datain(void *pdev, uint8_t epnum); +extern void usb_dev_cdc_dataout(void *pdev, uint8_t epnum); +extern void usb_dev_cdc_ctrlep_rxready(void *pdev); +extern uint8_t usb_dev_cdc_sof(void *pdev); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CDC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c new file mode 100644 index 0000000000..c22ad83280 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c @@ -0,0 +1,339 @@ +/** + ******************************************************************************* + * @file usb_dev_core.c + * @brief USBD core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_core.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_driver.h" +#include "usb_dev_int.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE LL USB Device Core + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_setup_process(usb_core_instance *pdev); +void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum); +void usb_datain_process(usb_core_instance *pdev, uint8_t epnum); +void usb_sof_process(usb_core_instance *pdev); +void usb_dev_rst(usb_core_instance *pdev); +void usb_dev_susp(usb_core_instance *pdev); +void usb_dev_resume(usb_core_instance *pdev); +void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn); +void usb_isoinincomplt_process(usb_core_instance *pdev); +void usb_isooutincomplt_process(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__IO uint32_t SET_TEST_MODE; +static usb_dev_int_cbk_typedef dev_int_cbk = { + &usb_dev_rst, + &usb_ctrlconn, + &usb_dev_susp, + &usb_dev_resume, + &usb_sof_process, + &usb_setup_process, + &usb_dataout_process, + &usb_datain_process, + &usb_isoinincomplt_process, + &usb_isooutincomplt_process +}; + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initailizes the device stack and load the class driver + * @param [in] pdev device instance + * @param [in] pdesc Device Descriptor + * @param [in] class_cb Class callback structure address + * @param [in] usr_cb User callback structure address + * @retval None + */ +void usb_dev_init(usb_core_instance *pdev, + usb_dev_desc_func *pdesc, + usb_dev_class_func *class_cb, + usb_dev_user_func *usr_cb) +{ + usb_bsp_init(pdev); + pdev->dev.class_callback = class_cb; + pdev->dev.user_callback = usr_cb; + pdev->dev.desc_callback = pdesc; + usb_initdev(pdev); + pdev->dev.user_callback->user_init(); + pdev->dev.device_state = USB_EP0_IDLE; + usb_bsp_nvicconfig(); +} + +/** + * @brief De-initailizes the device stack and load the class driver + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_deinit(usb_core_instance *pdev) +{ + (void)(pdev); +} + +/** + * @brief Handle Reset event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_rst(usb_core_instance *pdev) +{ + usb_opendevep(pdev, 0x00U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + usb_opendevep(pdev, 0x80U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + pdev->dev.device_cur_status = USB_DEV_DEFAULT; + pdev->dev.user_callback->user_devrst(); +} + +/** + * @brief Handle device connection and disconnection event + * @param [in] pdev device instance + * @param [in] conn 1 or 0 + * @retval None + */ +void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn) +{ + __IO uint8_t tmp_1; + tmp_1 = conn; + if (tmp_1 != 0U) { + pdev->dev.user_callback->user_devconn(); + pdev->dev.connection_status = 1U; + } else { + pdev->dev.user_callback->user_devdisconn(); + pdev->dev.class_callback->class_deinit(pdev); + pdev->dev.connection_status = 0U; + } +} + +/** + * @brief Handle Suspend event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_susp(usb_core_instance *pdev) +{ + pdev->dev.device_old_status = pdev->dev.device_cur_status; + pdev->dev.device_cur_status = USB_DEV_SUSPENDED; + pdev->dev.user_callback->user_devsusp(); +} + +/** + * @brief Handle Resume event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_resume(usb_core_instance *pdev) +{ + pdev->dev.user_callback->user_devresume(); + pdev->dev.device_cur_status = pdev->dev.device_old_status; + pdev->dev.device_cur_status = USB_DEV_CONFIGURED; +} + +/** + * @brief Handle SOF event + * @param [in] pdev device instance + * @retval None + */ +void usb_sof_process(usb_core_instance *pdev) +{ + if (0U != pdev->dev.class_callback->class_sof) { + pdev->dev.class_callback->class_sof(pdev); + } +} + +/** + * @brief Handle the setup stage + * @param [in] pdev device instance + * @retval None + */ +void usb_setup_process(usb_core_instance *pdev) +{ + USB_SETUP_REQ req; + + usb_parsesetupreq(pdev, &req); + + switch (req.bmRequest & 0x1FU) { + case USB_REQ_RECIPIENT_DEVICE: + usb_standarddevreq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + usb_standarditfreq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + usb_standardepreq(pdev, &req); + break; + + default: + usb_stalldevep(pdev, req.bmRequest & 0x80U); + break; + } +} + +/** + * @brief Handle data out stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + + if (epnum == 0U) { + ep = &pdev->dev.out_ep[0]; + if (pdev->dev.device_state == USB_EP0_DATA_OUT) { + if (ep->rem_data_len > ep->maxpacket) { + ep->rem_data_len -= ep->maxpacket; + + if (pdev->basic_cfgs.dmaen == 1U) { + /* in slave mode this, is handled by the RxSTSQLvl ISR */ + ep->xfer_buff += ep->maxpacket; + } + usb_readytorx(pdev, 0U, ep->xfer_buff, (uint16_t)LL_MIN(ep->rem_data_len, ep->maxpacket)); + } else { + if (ep->xfer_count > ep->rem_data_len) { + + } + ep->rem_data_len = 0UL; + if ((pdev->dev.class_callback->ep0_dataout != NULL) && + (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->ep0_dataout(pdev); + } + usb_ctrlstatustx(pdev); + } + } + } else if ((pdev->dev.class_callback->class_dataout != NULL) && (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->class_dataout(pdev, epnum); + } else { + ; + } +} + +/** + * @brief Handle data in stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_datain_process(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + + if (epnum == 0U) { + ep = &pdev->dev.in_ep[0]; + if (pdev->dev.device_state == USB_EP0_DATA_IN) { + if (ep->rem_data_len > ep->maxpacket) { + ep->rem_data_len -= ep->maxpacket; + if (pdev->basic_cfgs.dmaen == 1U) { + /* in slave mode this, is handled by the TxFifoEmpty ISR */ + ep->xfer_buff += ep->maxpacket; + } + usb_deveptx(pdev, 0U, ep->xfer_buff, ep->rem_data_len); + } else { + /* last packet is MPS multiple, so send ZLP packet */ + if ((ep->total_data_len % ep->maxpacket == 0U) && + (ep->total_data_len >= ep->maxpacket) && + (ep->total_data_len < ep->ctl_data_len)) { + usb_deveptx(pdev, 0U, NULL, 0UL); + ep->ctl_data_len = 0UL; + } else { + if ((pdev->dev.class_callback->ep0_datain != NULL) && + (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->ep0_datain(pdev); + } + usb_ctrlstatusrx(pdev); + } + } + } + if (pdev->dev.test_mode == 1U) { + usb_runtestmode(&pdev->regs, SET_TEST_MODE); + pdev->dev.test_mode = 0U; + } else { + } + } else if ((pdev->dev.class_callback->class_datain != NULL) && (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->class_datain(pdev, epnum); + } else { + ; + } +} + +/** + * @brief Handle iso in incomplete event + * @param [in] pdev device instance + * @retval None + */ +void usb_isoinincomplt_process(usb_core_instance *pdev) +{ + pdev->dev.class_callback->class_syn_in_incomplt(pdev); +} + +/** + * @brief Handle iso out incomplete event + * @param [in] pdev device instance + * @retval None + */ +void usb_isooutincomplt_process(usb_core_instance *pdev) +{ + pdev->dev.class_callback->class_syn_out_incomplt(pdev); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h new file mode 100644 index 0000000000..92a5590268 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h @@ -0,0 +1,82 @@ +/** + ******************************************************************************* + * @file usb_dev_core.h + * @brief header file for the usb_dev_core.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CORE_H__ +#define __USB_DEV_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern __IO uint32_t SET_TEST_MODE; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_dev_init(usb_core_instance *pdev, + usb_dev_desc_func *pdesc, + usb_dev_class_func *class_cb, + usb_dev_user_func *usr_cb); +extern void usb_dev_deinit(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c new file mode 100644 index 0000000000..87aa1eae41 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c @@ -0,0 +1,159 @@ +/** + ******************************************************************************* + * @file usb_dev_ctrleptrans.c + * @brief The IO requests APIs for control endpoints. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief send data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be sent + * @retval None + */ +void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + pdev->dev.in_ep[0].total_data_len = (uint32_t)len; + pdev->dev.in_ep[0].rem_data_len = (uint32_t)len; + pdev->dev.device_state = USB_EP0_DATA_IN; + + usb_deveptx(pdev, 0U, pbuf, (uint32_t)len); +} + +/** + * @brief continue sending data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be sent + * @retval None + */ +void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + usb_deveptx(pdev, 0U, pbuf, (uint32_t)len); +} + +/** + * @brief receive data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be received + * @retval status + */ +void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + pdev->dev.out_ep[0].total_data_len = len; + pdev->dev.out_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_EP0_DATA_OUT; + + usb_readytorx(pdev, 0U, pbuf, len); +} + +/** + * @brief continue receive data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be received + * @retval status + */ +void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + usb_readytorx(pdev, 0U, pbuf, len); +} +/** + * @brief send zero lzngth packet on the ctl pipe + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlstatustx(usb_core_instance *pdev) +{ + pdev->dev.device_state = USB_EP0_STATUS_IN; + usb_deveptx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U); +} + +/** + * @brief receive zero lzngth packet on the ctl pipe + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlstatusrx(usb_core_instance *pdev) +{ + pdev->dev.device_state = USB_EP0_STATUS_OUT; + usb_readytorx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U); +} + +/** + * @brief get the received data length + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval Rx Data blength + */ +uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum) +{ + return (uint16_t)pdev->dev.out_ep[epnum].xfer_count; +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h new file mode 100644 index 0000000000..087d6c9565 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h @@ -0,0 +1,83 @@ +/** + ******************************************************************************* + * @file usb_dev_ctrleptrans.h + * @brief header file for the usb_dev_ctrleptrans.c file + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CTRLEPTRANS_H__ +#define __USB_DEV_CTRLEPTRANS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrlstatustx(usb_core_instance *pdev); +extern void usb_ctrlstatusrx(usb_core_instance *pdev); +extern uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CTRLEPTRANS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h new file mode 100644 index 0000000000..0e1f4c62a2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h @@ -0,0 +1,155 @@ +/** + ******************************************************************************* + * @file usb_dev_def.h + * @brief general defines for the usb device library + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_DEF_H__ +#define __USB_DEV_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_lib.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#ifndef NULL +#define NULL (0U) +#endif + +/* Function return status */ +#define USB_DEV_OK (0U) +#define USB_DEV_BUSY (1U) +#define USB_DEV_FAIL (2U) + +/* Device Status */ +#define USB_DEV_DEFAULT (1U) +#define USB_DEV_ADDRESSED (2U) +#define USB_DEV_CONFIGURED (3U) +#define USB_DEV_SUSPENDED (4U) + +/* String descriptor type */ +#define LANGID_STR_IDX (0x00U) +#define MFC_STR_IDX (0x01U) +#define PRODUCT_STR_IDX (0x02U) +#define SERIAL_STR_IDX (0x03U) +#define CONFIG_STR_IDX (0x04U) +#define INTERFACE_STR_IDX (0x05U) + +/* Request type */ +#define USB_REQ_TYPE_STANDARD (0x00U) +#define USB_REQ_TYPE_CLASS (0x20U) +#define USB_REQ_TYPE_VENDOR (0x40U) +#define USB_REQ_TYPE_MASK (0x60U) + +/* Request recipient */ +#define USB_REQ_RECIPIENT_DEVICE (0x00U) +#define USB_REQ_RECIPIENT_INTERFACE (0x01U) +#define USB_REQ_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQ_RECIPIENT_MASK (0x03U) + +/* Standart request type */ +#define USB_REQ_GET_STATUS (0x00U) +#define USB_REQ_CLEAR_FEATURE (0x01U) +#define USB_REQ_SET_FEATURE (0x03U) +#define USB_REQ_SET_ADDRESS (0x05U) +#define USB_REQ_GET_DESCRIPTOR (0x06U) +#define USB_REQ_SET_DESCRIPTOR (0x07U) +#define USB_REQ_GET_CONFIGURATION (0x08U) +#define USB_REQ_SET_CONFIGURATION (0x09U) +#define USB_REQ_GET_INTERFACE (0x0AU) +#define USB_REQ_SET_INTERFACE (0x0BU) +#define USB_REQ_SYNCH_FRAME (0x0CU) + +/* Descriptor type */ +#define USB_DESC_TYPE_DEVICE (1U) +#define USB_DESC_TYPE_CONFIGURATION (2U) +#define USB_DESC_TYPE_STRING (3U) +#define USB_DESC_TYPE_INTERFACE (4U) +#define USB_DESC_TYPE_ENDPOINT (5U) +#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U) +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U) + +/* Configuration status */ +#define USB_CONFIG_REMOTE_WAKEUP (2U) +#define USB_CONFIG_SELF_POWERED (1U) + +/* USB device feature */ +#define USB_FEATURE_EP_HALT (0U) +#define USB_FEATURE_REMOTE_WAKEUP (1U) +#define USB_FEATURE_TEST_MODE (2U) + +/* USB device configuration status */ +#define USB_DEV_CONFIG_CLEAR (0U) +#define USB_DEV_CONFIG_SET (1U) +#define USB_DEV_CONFIG_GET (2U) + +/* USB EP0 state */ +#define USB_EP0_IDLE (0U) +#define USB_EP0_SETUP (1U) +#define USB_EP0_DATA_IN (2U) +#define USB_EP0_DATA_OUT (3U) +#define USB_EP0_STATUS_IN (4U) +#define USB_EP0_STATUS_OUT (5U) +#define USB_EP0_STALL (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c new file mode 100644 index 0000000000..9fe480605d --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c @@ -0,0 +1,400 @@ +/** + ******************************************************************************* + * @file usb_dev_driver.c + * @brief Peripheral Device Interface Layer + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Device intialize + * @param [in] pdev device instance + * @retval None + */ +void usb_initdev(usb_core_instance *pdev) +{ + uint32_t tmp_1; + USB_DEV_EP *iep, *oep; + + usb_setregaddr(&pdev->regs, &pdev->basic_cfgs); + pdev->dev.device_cur_status = (uint8_t)USB_DEV_DEFAULT; + pdev->dev.device_address = 0U; + tmp_1 = 0UL; + do { + iep = &pdev->dev.in_ep[tmp_1]; + oep = &pdev->dev.out_ep[tmp_1]; + iep->ep_dir = 1U; + oep->ep_dir = 0U; + iep->epidx = (uint8_t)tmp_1; + oep->epidx = iep->epidx; + iep->tx_fifo_num = (uint16_t)tmp_1; + oep->tx_fifo_num = iep->tx_fifo_num; + iep->trans_type = EP_TYPE_CTRL; + oep->trans_type = iep->trans_type; + iep->maxpacket = USB_MAX_EP0_SIZE; + oep->maxpacket = iep->maxpacket; + iep->xfer_buff = 0U; + oep->xfer_buff = iep->xfer_buff; + iep->xfer_len = 0UL; + oep->xfer_len = iep->xfer_len; + tmp_1++; + } while (tmp_1 < pdev->basic_cfgs.dev_epnum); + + usb_gintdis(&pdev->regs); + /*Init the Core (common init.) */ + usb_initusbcore(&pdev->regs, &pdev->basic_cfgs); + /* Force Device Mode*/ + usb_modeset(&pdev->regs, DEVICE_MODE); + /* Init Device */ + usb_devmodeinit(&pdev->regs, &pdev->basic_cfgs); + /* Enable USB Global interrupt */ + usb_ginten(&pdev->regs); +} + +/** + * @brief Configure and open an endpoint + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [in] ep_mps endpoint mps + * @param [in] ep_type endpoint type + * @retval None + */ +void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = ep_addr & 0x7FU; /* EP number */ + if (tmp_1 == 1U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->epidx = tmp_2; + + ep->ep_dir = tmp_1; + ep->maxpacket = ep_mps; + ep->trans_type = ep_type; + if (tmp_1 == 1U) { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = tmp_2; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) { + ep->data_pid_start = 0U; + } + usb_epactive(&pdev->regs, ep); +} + +/** + * @brief called when an EP is disabled + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @retval None + */ +void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = ep_addr & 0x7FU; /* EP number */ + if (tmp_1 == 1U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + ep->epidx = tmp_2; + ep->ep_dir = tmp_1; + usb_epdeactive(&pdev->regs, ep); +} + +/** + * @brief usb_readytorx + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [out] pbuf pointer to Rx buffer + * @param [in] buf_len data length + * @retval status + */ +void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1; + + tmp_1 = ep_addr & 0x7FU; /* EP number */ + ep = &pdev->dev.out_ep[tmp_1]; + /*setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = (uint32_t)buf_len; + ep->xfer_count = 0UL; + ep->ep_dir = 0U; + ep->epidx = tmp_1; + + if (pdev->basic_cfgs.dmaen == 1U) { + ep->dma_addr = (uint32_t)pbuf; + } + + if (tmp_1 == 0U) { + usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } else { + usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } +} + +/** + * @brief configures EPO to receive SETUP packets from host + * @param [in] pdev device instance + * @retval None + */ +void usb_ep0outstart(usb_core_instance *pdev) +{ + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); +} + +/** + * @brief Transmit data over USB + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [in] pbuf pointer to Tx buffer + * @param [in] buf_len data length + * @retval None + */ +void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1; + + tmp_1 = ep_addr & 0x7FU; /* EP number */ + ep = &pdev->dev.in_ep[tmp_1]; + + /* Setup and start the Transfer */ + ep->ep_dir = 1U; + ep->epidx = tmp_1; + ep->xfer_buff = pbuf; + ep->dma_addr = (uint32_t)pbuf; + ep->xfer_count = 0UL; + ep->xfer_len = buf_len; + + if (tmp_1 == 0U) { + usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } else { + usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } +} + +/** + * @brief Stall an endpoint. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval None + */ +void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->ep_stall = 1U; + ep->epidx = tmp_2; + if (tmp_1 != 0U) { + ep->ep_dir = 1U; + } else { + ep->ep_dir = 0U; + } + + usb_setepstall(&pdev->regs, ep); +} + +/** + * @brief Clear stall condition on endpoints. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval status + */ +void usb_clrstall(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->ep_stall = 0U; + ep->epidx = tmp_2; + if (tmp_1 != 0U) { + ep->ep_dir = 1U; + } else { + ep->ep_dir = 0U; + } + + usb_clearepstall(&pdev->regs, ep); +} + +/** + * @brief This Function flushes the FIFOs. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval status + */ +void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum) +{ + __IO uint8_t tmp_1; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + if (tmp_1 != 0U) { + usb_txfifoflush(&pdev->regs, (uint32_t)epnum & (uint32_t)0x7F); + } else { + usb_rxfifoflush(&pdev->regs); + } +} + +/** + * @brief This Function set USB device address + * @param [in] pdev device instance + * @param [in] devaddr new device address + * @retval None + */ +void usb_addrset(usb_core_instance *pdev, uint8_t devaddr) +{ + usb_devaddrset(&pdev->regs, devaddr); +} + +/** + * @brief control device connect or disconnect + * @param [in] pdev device instance + * @param [in] link 0(conn) or 1(disconn) + * @retval None + */ +void usb_conndevctrl(usb_core_instance *pdev, uint8_t link) +{ + usb_ctrldevconnect(&pdev->regs, link); +} + +/** + * @brief returns the EP Status + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval EP status + */ +uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + uint32_t Status; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + Status = usb_epstatusget(&pdev->regs, ep); + /* Return the current status */ + return Status; +} + +/** + * @brief Set the EP Status + * @param [in] pdev device instance + * @param [in] status new Status + * @param [in] epnum EP address + * @retval None + */ +void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + usb_epstatusset(&pdev->regs, ep, status); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h new file mode 100644 index 0000000000..2cb904a73c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h @@ -0,0 +1,89 @@ +/** + ******************************************************************************* + * @file usb_dev_driver.h + * @brief Peripheral Driver Header file + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_DRIVER_H__ +#define __USB_DEV_DRIVER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_initdev(usb_core_instance *pdev); +extern void usb_conndevctrl(usb_core_instance *pdev, uint8_t link); +extern void usb_addrset(usb_core_instance *pdev, uint8_t devaddr); +extern void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +extern void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr); +extern void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +extern void usb_ep0outstart(usb_core_instance *pdev); +extern void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); +extern void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum); +extern void usb_clrstall(usb_core_instance *pdev, uint8_t epnum); +extern void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum); +extern uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum); +extern void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_DRIVER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c new file mode 100644 index 0000000000..fa53d98549 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c @@ -0,0 +1,456 @@ +/** + ******************************************************************************* + * @file usb_dev_int.c + * @brief Peripheral Device interrupt subroutines. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_int.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief read the endpoint flags + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval status + */ +static uint32_t usb_rddevinep(usb_core_instance *pdev, uint8_t epnum) +{ + uint32_t u32diepmsk; + uint32_t u32diepempmsk; + u32diepmsk = READ_REG32(pdev->regs.DREGS->DIEPMSK); + u32diepempmsk = READ_REG32(pdev->regs.DREGS->DIEPEMPMSK); + u32diepmsk |= (((u32diepempmsk >> epnum) & 0x1UL) << 7U); + return (READ_REG32(pdev->regs.INEP_REGS[epnum]->DIEPINT) & u32diepmsk); +} + +/** + * @brief check FIFO for the next packet to be loaded + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) +{ + USB_DEV_EP *ep; + uint32_t u32Len; + uint32_t u32Len32b; + uint16_t u16spclen; + uint32_t u32diepempmsk; + + ep = &pdev->dev.in_ep[epnum]; + u32Len = ep->xfer_len - ep->xfer_count; + if (u32Len > ep->maxpacket) { + u32Len = ep->maxpacket; + } + u32Len32b = (u32Len + 3UL) >> 2; + u16spclen = usb_rdineptxfspcavail(pdev, epnum); + while ((u16spclen >= u32Len32b) && (ep->xfer_count < ep->xfer_len)) { + u32Len = ep->xfer_len - ep->xfer_count; + + if (u32Len > ep->maxpacket) { + u32Len = ep->maxpacket; + } + u32Len32b = (u32Len + 3UL) >> 2; + usb_wrpkt(&pdev->regs, ep->xfer_buff, (uint8_t)epnum, (uint16_t)u32Len, pdev->basic_cfgs.dmaen); + ep->xfer_buff += u32Len; + ep->xfer_count += u32Len; + u16spclen = usb_rdineptxfspcavail(pdev, epnum); + } + + if (u32Len == 0UL) { + u32diepempmsk = 0x01UL << epnum; + CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk); + } +} + +#ifdef VBUS_SENSING_ENABLED +/** + * @brief Indicates that the USB_OTG controller has detected a connection + * @param [in] pdev device instance + * @retval None + */ +static void usb_sessionrequest_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->devctrlconnect(pdev, 1U); + + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_VBUSVINT); + + if (0U != pdev->basic_cfgs.low_power) { + CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK); + } +} +#endif + +/** + * @brief Indicates that the controller has detected a resume or remote Wake-up sequence + * @param [in] pdev device instance + * @retval None + */ +static void usb_resume_isr(usb_core_instance *pdev) +{ + if (0U != pdev->basic_cfgs.low_power) { + CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK); + } + + CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG); + + dev_int_cbkpr->Resume(pdev); + + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_WKUINT); +} + +/** + * @brief Indicates that SUSPEND state has been detected on the USB + * @param [in] pdev device instance + * @retval None + */ +static void usb_susp_isr(usb_core_instance *pdev) +{ + uint32_t u32dsts; + uint8_t u8PrevStatus; + + dev_int_cbkpr->Suspend(pdev); + u32dsts = READ_REG32(pdev->regs.DREGS->DSTS); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBSUSP); + + u8PrevStatus = pdev->dev.device_cur_status; + if ((u8PrevStatus == USB_DEV_CONFIGURED) && + (0U != pdev->basic_cfgs.low_power) && ((u32dsts & 1UL) != 0UL) && + (pdev->dev.connection_status == 1U)) { + SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK); + SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_GATEHCLK); + } +} + +/** + * @brief Indicates that at leadt one IN EP has a pending interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_inep_isr(usb_core_instance *pdev) +{ + uint32_t u32diepint; + uint32_t u32EpIntr; + uint8_t u8epnum; + uint32_t u32diepempmsk; + + u32EpIntr = usb_getalliepintr(&pdev->regs); + u8epnum = 0U; + while ((0U != u32EpIntr) && (u8epnum <= USB_MAX_TX_FIFOS)) { + if ((u32EpIntr & 0x1UL) != 0UL) { + u32diepint = usb_rddevinep(pdev, u8epnum); + if ((u32diepint & XFER_COMPL) != 0UL) { + u32diepempmsk = 1UL << u8epnum; + CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk); + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, XFER_COMPL); + dev_int_cbkpr->DataInStage(pdev, u8epnum); + if (pdev->basic_cfgs.dmaen == 1U) { + if ((u8epnum == 0U) && (pdev->dev.device_state == USB_EP0_STATUS_IN)) { + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + pdev->dev.device_state = USB_EP0_IDLE; + } + } + } + if ((u32diepint & EPDISABLED) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, EPDISABLED); + } + if ((u32diepint & TIME_OUT) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TIME_OUT); + } + if ((u32diepint & INTKNTXFEMP) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INTKNTXFEMP); + } + if ((u32diepint & INEPNAKEFF) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INEPNAKEFF); + } + if ((u32diepint & TXFEMP) != 0UL) { + usb_wrblanktxfifo(pdev, u8epnum); + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TXFEMP); + } + } + u8epnum++; + u32EpIntr >>= 1U; + } +} + +/** + * @brief Indicates that an OUT EP has a pending Interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_outep_isr(usb_core_instance *pdev) +{ + uint32_t u32EpIntr; + uint32_t u32doepint; + uint8_t u8epnum = 0U; + uint32_t u8Xfer; + uint32_t u32ReadEpSize; + + u32EpIntr = usb_getalloepintr(&pdev->regs); + while ((u32EpIntr != 0UL) && (u8epnum <= USB_MAX_TX_FIFOS)) { + if ((u32EpIntr & 0x1UL) != 0UL) { + u32doepint = usb_getoepintbit(&pdev->regs, u8epnum); + if ((u32doepint & XFER_COMPL) != 0UL) { + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, XFER_COMPL); + if (pdev->basic_cfgs.dmaen == 1U) { + u32ReadEpSize = (READ_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPTSIZ) & USBFS_DOEPTSIZ_XFRSIZ); + u8Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len); + pdev->dev.out_ep[u8epnum].xfer_count = u8Xfer - u32ReadEpSize; + if (u8epnum != 0U) { + pdev->dev.out_ep[u8epnum].xfer_count = pdev->dev.out_ep[u8epnum].xfer_len - u32ReadEpSize; + } + } + dev_int_cbkpr->DataOutStage(pdev, u8epnum); + if (pdev->basic_cfgs.dmaen == 1U) { + if ((u8epnum == 0U) && (pdev->dev.device_state == USB_EP0_STATUS_OUT)) { + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + pdev->dev.device_state = USB_EP0_IDLE; + } + } + } + if ((u32doepint & EPDISABLED) != 0UL) { + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, EPDISABLED); + } + if (u8epnum == 0U) { + u32doepint = usb_getoepintbit(&pdev->regs, u8epnum); + if ((u32doepint & SETUP_BIT) != 0UL) { + dev_int_cbkpr->SetupStage(pdev); + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, SETUP_BIT); + } + } + } + u8epnum++; + u32EpIntr >>= 1U; + } +} + +/** + * @brief Handles the SOF Interrupts + * @param [in] pdev device instance + * @retval None + */ +static void usb_sof_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->SOF(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF); +} + +/** + * @brief Handles the Rx Status Queue Level Interrupt + * @param [in] pdev device instance + * @retval status + */ +static void usb_rxstsqlvl_isr(usb_core_instance *pdev) +{ + uint32_t u32grxsts; + USB_DEV_EP *ep; + uint8_t u8epnum; + uint8_t u8PktStatus; + uint16_t u16ByteCnt; + + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM); + + u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); + u8epnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM); + u8PktStatus = (uint8_t)((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS); + u16ByteCnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS); + ep = &pdev->dev.out_ep[u8epnum]; + switch (u8PktStatus) { + case STS_DATA_UPDT: + if (0U != u16ByteCnt) { + usb_rdpkt(&pdev->regs, ep->xfer_buff, u16ByteCnt); + ep->xfer_buff += u16ByteCnt; + ep->xfer_count += u16ByteCnt; + } else { + ; + } + break; + case STS_SETUP_UPDT: + /* Copy the setup packet received in FIFO into the setup buffer in RAM */ + usb_rdpkt(&pdev->regs, pdev->dev.setup_pkt_buf, 8U); + ep->xfer_count += u16ByteCnt; + break; + case STS_GOUT_NAK: + case STS_XFER_COMP: + case STS_SETUP_COMP: + break; + default: + break; + } + SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM); +} + +/** + * @brief This interrupt occurs when a USB Reset is detected + * @param [in] pdev device instance + * @retval None + */ +static void usb_reset_isr(usb_core_instance *pdev) +{ + uint32_t i; + + CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG); + usb_txfifoflush(&pdev->regs, 0UL); + for (i = 0UL; i < pdev->basic_cfgs.dev_epnum ; i++) { + WRITE_REG32(pdev->regs.INEP_REGS[i]->DIEPINT, 0xFFUL); + WRITE_REG32(pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFFUL); + } + WRITE_REG32(pdev->regs.DREGS->DAINT, 0xFFFFFFFFUL); + WRITE_REG32(pdev->regs.DREGS->DAINTMSK, 1UL | (1UL << USBFS_DAINTMSK_OEPINTM_POS)); + //todo: bit5 if need be set? + WRITE_REG32(pdev->regs.DREGS->DOEPMSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + WRITE_REG32(pdev->regs.DREGS->DOUTEP1MSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM); +#endif + + WRITE_REG32(pdev->regs.DREGS->DIEPMSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + WRITE_REG32(pdev->regs.DREGS->DINEP1MSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM); +#endif + + CLR_REG32_BIT(pdev->regs.DREGS->DCFG, USBFS_DCFG_DAD); + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBRST); + + dev_int_cbkpr->Reset(pdev); +} + +/** + * @brief Read the device status register and set the device speed + * @param [in] pdev device instance + * @retval None + */ +static void usb_enumfinish_isr(usb_core_instance *pdev) +{ + usb_ep0activate(&pdev->regs); + usb_setaroundtim(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_ENUMDNE); +} + +/** + * @brief handle the ISO IN incomplete interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_isoinincomplt_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->IsoINIncomplete(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IISOIXFR); +} + +/** + * @brief handle the ISO OUT incomplete interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_isooutincomplt_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->IsoOUTIncomplete(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT); +} + +/** + * @brief handles all USB Interrupts + * @param [in] pdev device instance + * @retval None + */ +void usb_isr_handler(usb_core_instance *pdev) +{ + uint32_t u32gintsts; + + if (0U == usb_getcurmod(&pdev->regs)) { + u32gintsts = usb_getcoreintr(&pdev->regs); + if (u32gintsts == 0UL) { + return; + } + if ((u32gintsts & OUTEP_INT) != 0UL) { + usb_outep_isr(pdev); + } + if ((u32gintsts & INEP_INT) != 0UL) { + usb_inep_isr(pdev); + } + if ((u32gintsts & MODEMIS_INT) != 0UL) { + WRITE_REG32(pdev->regs.GREGS->GINTSTS, MODEMIS_INT); + } + if ((u32gintsts & WAKEUP_INT) != 0UL) { + usb_resume_isr(pdev); + } + if ((u32gintsts & USBSUSP_INT) != 0UL) { + usb_susp_isr(pdev); + } + if ((u32gintsts & SOF_INT) != 0UL) { + usb_sof_isr(pdev); + } + if ((u32gintsts & RXFLVL_INT) != 0UL) { + usb_rxstsqlvl_isr(pdev); + } + if ((u32gintsts & USBRST_INT) != 0UL) { + usb_reset_isr(pdev); + } + if ((u32gintsts & ENUMDONE_INT) != 0UL) { + usb_enumfinish_isr(pdev); + } + if ((u32gintsts & INCOMPLSOIN) != 0UL) { + usb_isoinincomplt_isr(pdev); + } + if ((u32gintsts & INCOMPLSOOUT) != 0UL) { + usb_isooutincomplt_isr(pdev); + } +#ifdef VBUS_SENSING_ENABLED + if ((u32gintsts & VBUSV_INT) != 0UL) { + usb_sessionrequest_isr(pdev); + } +#endif + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h new file mode 100644 index 0000000000..f8b2deea19 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file usb_dev_int.h + * @brief Peripheral Device Interface Layer + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_INT_H__ +#define __USB_DEV_INT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The bit of the diepint/doepint */ +#define XFER_COMPL (1UL) +#define EPDISABLED (1UL<<1) +#define TIME_OUT (1UL<<3) +#define SETUP_BIT (1UL<<3) +#define INTKNTXFEMP (1UL<<4) +#define INEPNAKEFF (1UL<<6) +#define TXFEMP (1UL<<7) + +/* The bit of the GINTSTS */ +#define MODEMIS_INT (1UL<<1) +#define SOF_INT (1UL<<3) +#define RXFLVL_INT (1UL<<4) +#define USBSUSP_INT (1UL<<11) +#define USBRST_INT (1UL<<12) +#define ENUMDONE_INT (1UL<<13) +#define INEP_INT (1UL<<18) +#define OUTEP_INT (1UL<<19) +#define INCOMPLSOIN (1UL<<20) +#define INCOMPLSOOUT (1UL<<21) +#define VBUSV_INT (1UL<<30) +#define WAKEUP_INT (1UL<<31) + +/* Data packet status for device mode */ +#define STS_GOUT_NAK (1U) +#define STS_DATA_UPDT (2U) +#define STS_XFER_COMP (3U) +#define STS_SETUP_COMP (4U) +#define STS_SETUP_UPDT (6U) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + void (* Reset)(usb_core_instance *pdev); + void (* devctrlconnect)(usb_core_instance *pdev, uint8_t conn); + void (* Suspend)(usb_core_instance *pdev); + void (* Resume)(usb_core_instance *pdev); + void (* SOF)(usb_core_instance *pdev); + void (* SetupStage)(usb_core_instance *pdev); + void (* DataOutStage)(usb_core_instance *pdev, uint8_t epnum); + void (* DataInStage)(usb_core_instance *pdev, uint8_t epnum); + void (* IsoINIncomplete)(usb_core_instance *pdev); + void (* IsoOUTIncomplete)(usb_core_instance *pdev); +} usb_dev_int_cbk_typedef; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @brief get the IN Endpoint TxFIFO avail space + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval the avail space in 32-bit words + */ +__STATIC_INLINE uint16_t usb_rdineptxfspcavail(usb_core_instance *pdev, uint32_t epnum) +{ + return (uint16_t)(READ_REG32(pdev->regs.INEP_REGS[epnum]->DTXFSTS) & USBFS_DTXFSTS_INEPTFSAV); +} + +/** + * @brief set the USB turn around time + * @param [in] pdev device instance + * @retval None + */ +__STATIC_INLINE void usb_setaroundtim(usb_core_instance *pdev) +{ + SET_REG32_BIT(pdev->regs.GREGS->GUSBCFG, USBFS_GUSBCFG_TRDT); +} + +extern usb_dev_int_cbk_typedef *dev_int_cbkpr; +extern void usb_isr_handler(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_INT_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c new file mode 100644 index 0000000000..c1e7cf7f3a --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c @@ -0,0 +1,606 @@ +/** + ******************************************************************************* + * @file usb_dev_stdreq.c + * @brief The standard USB requests following chapter 9. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_dev_core.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +static __USB_ALIGN_BEGIN uint32_t dev_ep_status = 0UL; +static __USB_ALIGN_BEGIN uint32_t dev_default_cfg = 0UL; +static __USB_ALIGN_BEGIN uint32_t dev_cfg_status = 0UL; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getintf(usb_core_instance *pdev); +void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req); +uint8_t usb_getlength(uint8_t *buf); +void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Handle standard usb device requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + if (req->bRequest == USB_REQ_GET_DESCRIPTOR) { + usb_getdesc(pdev, req) ; + } else if (req->bRequest == USB_REQ_SET_ADDRESS) { + usb_setaddr(pdev, req); + } else if (req->bRequest == USB_REQ_SET_CONFIGURATION) { + usb_setconfig(pdev, req); + } else if (req->bRequest == USB_REQ_GET_CONFIGURATION) { + usb_getconfig(pdev, req); + } else if (req->bRequest == USB_REQ_GET_STATUS) { + usb_getstatus(pdev, req); + } else if (req->bRequest == USB_REQ_SET_FEATURE) { + usb_setfeature(pdev, req); + } else if (req->bRequest == USB_REQ_CLEAR_FEATURE) { + usb_clrfeature(pdev, req); + } else { + if (0U != pdev->dev.class_callback->ep0_setup(pdev, req)) { + usb_ctrlerr(pdev); + } + } +} + +/** + * @brief Handle standard usb interface requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8RetFlag = 0U; + + if (req->bRequest == USB_REQ_GET_STATUS) { + usb_getstatus(pdev, req); + u8RetFlag = 1U; + } else if (req->bRequest == USB_REQ_GET_INTERFACE) { + if (req->bmRequest != 0x21U) { + usb_getintf(pdev); + u8RetFlag = 1U; + } + } else if (req->bRequest == 0xFEU) { + usb_getintf(pdev); + u8RetFlag = 1U; + } else { + ; + } + + if (1U != u8RetFlag) { + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + pdev->dev.class_callback->ep0_setup(pdev, req); + if (req->wLength == 0U) { + usb_ctrlstatustx(pdev); + } + } else { + usb_ctrlerr(pdev); + } + } else { + usb_ctrlerr(pdev); + } + } +} + +/** + * @brief Handle standard usb endpoint requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + __IO uint8_t ep_addr; + ep_addr = LOBYTE(req->wIndex); + + switch (req->bRequest) { + case USB_REQ_SET_FEATURE : + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + } + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + break; + default: + usb_ctrlerr(pdev); + break; + } + break; + case USB_REQ_CLEAR_FEATURE : + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_clrstall(pdev, ep_addr); + pdev->dev.class_callback->ep0_setup(pdev, req); + } + usb_ctrlstatustx(pdev); + } + break; + default: + usb_ctrlerr(pdev); + break; + } + break; + case USB_REQ_GET_STATUS: + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) { + if (0U != pdev->dev.in_ep[ep_addr % USB_MAX_TX_FIFOS].ep_stall) { + dev_ep_status = 0x0001U; + } else { + dev_ep_status = 0x0000U; + } + } else if ((ep_addr & 0x80U) == 0x00U) { + if (0U != pdev->dev.out_ep[ep_addr % USB_MAX_TX_FIFOS].ep_stall) { + dev_ep_status = 0x0001U; + } else { + dev_ep_status = 0x0000U; + } + } else { + ; + } + usb_ctrldatatx(pdev, (uint8_t *)&dev_ep_status, 2U); + break; + + default: + usb_ctrlerr(pdev); + break; + } + break; + default: + break; + } +} + +/** + * @brief Handle Get Descriptor requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval status + */ +void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8ErrFlag = 0U; + + switch (req->wValue >> 8U) { + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->dev.desc_callback->get_dev_desc(&len); + break; + case USB_DESC_TYPE_CONFIGURATION: + pbuf = (uint8_t *)pdev->dev.class_callback->class_getconfigdesc(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + break; + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) { + case LANGID_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_langiddesc(&len); + break; + case MFC_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_manufacturerstr(&len); + break; + case PRODUCT_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_productstr(&len); + break; + case SERIAL_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_serialstr(&len); + break; + case CONFIG_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_configstr(&len); + break; + case INTERFACE_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_interfacestr(&len); + break; + default: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + default: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + } + + if (0U == u8ErrFlag) { + if ((len != 0U) && (req->wLength != 0U)) { + len = LL_MIN(len, req->wLength); + usb_ctrldatatx(pdev, pbuf, len); + } + } +} + +/** + * @brief Set device address + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0U) && (req->wLength == 0U)) { + dev_addr = (uint8_t)(req->wValue) & 0x7Fu; + + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_ctrlerr(pdev); + } else { + pdev->dev.device_address = dev_addr; + usb_addrset(pdev, dev_addr); + usb_ctrlstatustx(pdev); + + if (dev_addr != 0U) { + pdev->dev.device_cur_status = USB_DEV_ADDRESSED; + } else { + pdev->dev.device_cur_status = USB_DEV_DEFAULT; + } + } + } else { + usb_ctrlerr(pdev); + } +} + +/** + * @brief Handle Set device configuration request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + static uint8_t tmp_cfgidx; + + tmp_cfgidx = (uint8_t)(req->wValue); + + if (tmp_cfgidx > DEV_MAX_CFG_NUM) { + usb_ctrlerr(pdev); + } else { + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if (0U != tmp_cfgidx) { + pdev->dev.device_config = tmp_cfgidx; + pdev->dev.device_cur_status = USB_DEV_CONFIGURED; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET); + usb_ctrlstatustx(pdev); + } else { + usb_ctrlstatustx(pdev); + } + break; + case USB_DEV_CONFIGURED: + if (tmp_cfgidx == 0U) { + pdev->dev.device_cur_status = USB_DEV_ADDRESSED; + pdev->dev.device_config = tmp_cfgidx; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_CLEAR); + usb_ctrlstatustx(pdev); + } else if (tmp_cfgidx != pdev->dev.device_config) { + /* Clear old configuration */ + usb_dev_ctrlconfig(pdev, pdev->dev.device_config, USB_DEV_CONFIG_CLEAR); + /* set new configuration */ + pdev->dev.device_config = tmp_cfgidx; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET); + usb_ctrlstatustx(pdev); + } else { + usb_ctrlstatustx(pdev); + } + break; + case USB_DEV_SUSPENDED: + + break; + default: + usb_ctrlerr(pdev); + break; + } + } +} + +/** + * @brief Handle Get device configuration request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + if (req->wLength != 1U) { + usb_ctrlerr(pdev); + } else { + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + usb_ctrldatatx(pdev, (uint8_t *)&dev_default_cfg, 1U); + break; + case USB_DEV_CONFIGURED: + usb_ctrldatatx(pdev, (uint8_t *)&pdev->dev.device_config, 1U); + break; + default: + usb_ctrlerr(pdev); + break; + } + } +} + +/** + * @brief Handle Get Status request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + (void)(req); + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + case USB_DEV_CONFIGURED: +#ifdef SELF_POWER + dev_cfg_status = USB_CONFIG_SELF_POWERED; +#else + dev_cfg_status = 0x00U; +#endif + if (0U != pdev->dev.device_remote_wakeup) { + dev_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; + } + usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 2U); + break; + default : + usb_ctrlerr(pdev); + break; + } +} + +/** + * @brief usb_getintf + * @param [in] pdev device instance + * @retval None + */ +void usb_getintf(usb_core_instance *pdev) +{ + dev_cfg_status = 0U; + usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 1U); +} + +/** + * @brief Handle Set device feature request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + uint32_t dctl; + uint8_t test_mode; + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev.device_remote_wakeup = 1U; + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + } else if ((req->wValue == USB_FEATURE_TEST_MODE) && ((req->wIndex & 0xFFU) == 0U)) { + dctl = READ_REG32(pdev->regs.DREGS->DCTL); + test_mode = (uint8_t)req->wIndex >> 8U; + test_mode = test_mode & (uint8_t)(~0xF8U); + dctl = (uint32_t)test_mode << 4U; + SET_TEST_MODE = dctl; + pdev->dev.test_mode = 1U; + usb_ctrlstatustx(pdev); + } else { + ; + } +} + +/** + * @brief Handle clear device feature request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev.device_remote_wakeup = 0U; + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + } + break; + default : + usb_ctrlerr(pdev); + break; + } +} + +/** + * @brief Copy buffer into setup structure + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + req->bmRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf); + req->bRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf + 1U); + req->wValue = SWAPBYTE(pdev->dev.setup_pkt_buf + 2U); + req->wIndex = SWAPBYTE(pdev->dev.setup_pkt_buf + 4U); + req->wLength = SWAPBYTE(pdev->dev.setup_pkt_buf + 6U); + + pdev->dev.in_ep[0].ctl_data_len = req->wLength; + pdev->dev.device_state = USB_EP0_SETUP; +} + +/** + * @brief Handle USB low level Error + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlerr(usb_core_instance *pdev) +{ + usb_stalldevep(pdev, 0x80U); + usb_stalldevep(pdev, 0U); + usb_ep0outstart(pdev); +} + +/** + * @brief Convert Ascii string into unicode one + * @param [in] desc descriptor buffer + * @param [in] unicode Formatted string buffer (unicode) + * @param [in] len descriptor length + * @retval None + */ +void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t tmp_idx = 0U; + + if (desc != NULL) { + *len = (uint16_t)usb_getlength(desc) * 2U + 2U; + unicode[tmp_idx++] = (uint8_t) * len; + unicode[tmp_idx++] = USB_DESC_TYPE_STRING; + + while (*desc != (uint8_t)0U) { + unicode[tmp_idx++] = *desc++; + unicode[tmp_idx++] = 0x00U; + } + } +} + +/** + * @brief get the string length + * @param [in] buf pointer to the ascii string buffer + * @retval string length + */ +uint8_t usb_getlength(uint8_t *buf) +{ + uint8_t tmp_len = 0U; + + while (*buf != (uint8_t)0U) { + tmp_len++; + buf++; + } + return tmp_len; +} + +/** + * @brief set current configuration or clear current configuration + * @param [in] pdev device instance + * @param [in] cfgidx configuration index + * @param [in] action USB_DEV_CONFIG_SET or USB_DEV_CONFIG_CLEAR + * @retval None + */ +void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action) +{ + __IO uint8_t tmp_1; + + (void)(cfgidx); + tmp_1 = action; + if (tmp_1 == USB_DEV_CONFIG_SET) { /* set configuration */ + pdev->dev.class_callback->class_init(pdev); + pdev->dev.user_callback->user_devconfig(); + } else if (tmp_1 == USB_DEV_CONFIG_CLEAR) { /* clear configuration */ + pdev->dev.class_callback->class_deinit(pdev); + } else { + ; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h new file mode 100644 index 0000000000..1b95c5de38 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h @@ -0,0 +1,82 @@ +/** + ******************************************************************************* + * @file usb_dev_stdreq.h + * @brief header file for the usb_dev_stdreq.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_STDREQ_H__ +#define __USB_DEV_STDREQ_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_ctrlerr(usb_core_instance *pdev); +void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_STDREQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c new file mode 100644 index 0000000000..38f730f606 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c @@ -0,0 +1,693 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_class.c + * @brief cdc class related functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_class.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC USB Host CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +CDC_Requests CDC_ReqState; +CDC_Usercb_TypeDef UserCb; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static CDC_Machine_TypeDef CDC_Machine; + +static CDC_Xfer_TypeDef CDC_TxParam; +static CDC_Xfer_TypeDef CDC_RxParam; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static uint8_t TxBuf[CDC_BUFFER_SIZE]; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static uint8_t RxBuf[CDC_BUFFER_SIZE]; + +static uint8_t RX_Enabled = 0; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void usb_host_cdc_txrxparam_init(void); + +static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data); + +static void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost); + +static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost); + +static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost); + +void usb_host_cdc_interface_deinit(usb_core_instance *pdev); + +static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost); + +static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost); + +usb_host_class_callback_func CDC_cb = { + usb_host_cdc_interface_init, + usb_host_cdc_interface_deinit, + usb_host_cdc_class_request, + usb_host_cdc_class_process +}; + +/** + * @brief init the vendor interface + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_vendor_interface_init(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_UNSUPPORTED; + uint8_t idxep; + uint8_t bulk_inep_cnt, bulk_inep_idx = 0U; + uint8_t bulk_outep_cnt, bulk_outep_idx = 0U; + uint8_t intr_inep_cnt = 0U, intr_inep_idx = 0U; + /* try to support vendor cdc device */ + if (pphost->device_prop.devitfdesc[0].bInterfaceClass == VENDOR_SPECIFIC) { + if (pphost->device_prop.devitfdesc[0].bNumEndpoints < 2U) { + return HSTATUS_UNSUPPORTED; + } + bulk_inep_cnt = 0; + bulk_outep_cnt = 0; + for (idxep = 0; idxep < pphost->device_prop.devitfdesc[0].bNumEndpoints; idxep++) { + if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK) { + if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) { + bulk_inep_cnt++; + bulk_inep_idx = idxep; + } else { + bulk_outep_cnt++; + bulk_outep_idx = idxep; + } + } else if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR) { + if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) { + intr_inep_cnt++; + intr_inep_idx = idxep; + } + } else { + ; + } + } + if ((bulk_inep_cnt != 1U) || (bulk_outep_cnt != 1U)) { + return HSTATUS_UNSUPPORTED; + } + + if (bulk_inep_cnt == 1U) { + /* fill the communication endpoint address and length */ + CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress; + CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][intr_inep_idx].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_CommItf.notificationEp = + (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress); + } + /* distribute a channel for communication endpoint */ + CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_CommItf.notificationEp); + + /* open channel for communication endpoint */ + usb_host_chopen(pdev, + CDC_Machine.CDC_CommItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + CDC_Machine.CDC_CommItf.length); + } + + /* fill cdc data endpoint address and length */ + CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress; + CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[0][bulk_inep_idx].wMaxPacketSize; + + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress); + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[0][bulk_outep_idx].bEndpointAddress); + + /* distribute channels for cdc data endpoints */ + CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcOutEp); + + CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcInEp); + + /* open cdc data endpoints */ + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + /* txrx parms init */ + usb_host_cdc_txrxparam_init(); + + /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + + status = HSTATUS_OK; + } + return status; +} + +/** + * @brief init the std cdc interface + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_OK; + uint8_t unsupport_cnt = 0; + + /* Communication Interface */ + if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == COMMUNICATION_DEVICE_CLASS_CODE) && + (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == ABSTRACT_CONTROL_MODEL) && + (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == COMMON_AT_COMMAND)) { + /* fill the communication endpoint address and length */ + CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress; + CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_CommItf.notificationEp = + (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + } + /* distribute a channel for communication endpoint */ + CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_CommItf.notificationEp); + + /* open channel for communication endpoint */ + usb_host_chopen(pdev, + CDC_Machine.CDC_CommItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + CDC_Machine.CDC_CommItf.length); + } else { + pphost->user_callbk->huser_devunsupported(); + unsupport_cnt++; + } + + /* Data Interface */ + if ((pphost->device_prop.devitfdesc[1].bInterfaceClass == DATA_INTERFACE_CLASS_CODE) && + (pphost->device_prop.devitfdesc[1].bInterfaceSubClass == RESERVED) && + (pphost->device_prop.devitfdesc[1].bInterfaceProtocol == NO_CLASS_SPECIFIC_PROTOCOL_CODE)) { + /* fill cdc data endpoint address and length */ + CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[1][0].bEndpointAddress; + CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[1][0].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[1][0].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress); + } else { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress); + } + + if (0U != (pphost->device_prop.devepdesc[1][1].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress); + } else { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress); + } + + /* distribute channels for cdc data endpoints */ + CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcOutEp); + + CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcInEp); + + /* open cdc data endpoints */ + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + /* txrx parms init */ + usb_host_cdc_txrxparam_init(); + + /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } else { + pphost->user_callbk->huser_devunsupported(); + unsupport_cnt++; + } + + /* not a stand CDC ACM device */ + if (2U == unsupport_cnt) { + if (HSTATUS_OK != usb_host_cdc_vendor_interface_init(pdev, phost)) { + pphost->user_callbk->huser_devunsupported(); + } + } + + return status; +} + +/** + * @brief deinit the cdc interface + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_interface_deinit(usb_core_instance *pdev) +{ + /* halt and free all channels */ + if (0U != CDC_Machine.CDC_CommItf.hc_num_in) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_CommItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_CommItf.hc_num_in); + CDC_Machine.CDC_CommItf.hc_num_in = 0; + } + + if (0U != CDC_Machine.CDC_DataItf.hc_num_out) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_out); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_out); + CDC_Machine.CDC_DataItf.hc_num_out = 0; + } + + if (0U != CDC_Machine.CDC_DataItf.hc_num_in) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + CDC_Machine.CDC_DataItf.hc_num_in = 0; + } +} + +/** + * @brief handing host class request state + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + + HOST_STATUS status = HSTATUS_BUSY; + HOST_STATUS ClassReqStatus; + + switch (CDC_ReqState) { + + case CDC_GET_LINE_CODING_RQUEST: + + ClassReqStatus = usb_host_cdc_getlinecoding(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + } + break; + + case CDC_SET_LINE_CODING_RQUEST: + + ClassReqStatus = usb_host_cdc_setlinecoding(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } + if (ClassReqStatus == HSTATUS_UNSUPPORTED) { + /* Clear Feature should be issued */ + CDC_ReqState = CDC_ERROR_STATE; + } + break; + + case CDC_SET_CONTROL_LINE_STATE_REQUEST: + + ClassReqStatus = usb_host_cdc_setcontrollinestate(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + /* change state to itself */ + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + /* change rx state to CDC_IDLE */ + CDC_RxParam.CDCState = CDC_IDLE; + + status = HSTATUS_OK; + } + break; + + case CDC_ERROR_STATE: + + ClassReqStatus = usb_host_clrfeature(pdev, + phost, + 0x00, + pphost->ctrlparam.hc_num_out); + + if (ClassReqStatus == HSTATUS_OK) { + /* change state to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } + break; + default: + break; + } + + return status; +} + +/** + * @brief process the cdc data send/receive state machine and user application + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status = HSTATUS_OK; + USBH_HOST *pphost = phost; + + /* application process */ + pphost->user_callbk->huser_application(); + + /* send data process */ + usb_host_cdc_senddata_process(pdev, pphost); + + /* receive data process */ + usb_host_cdc_receivedata_process(pdev, pphost); + + return status; +} + +/** + * @brief process the cdc data send state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost) +{ + static uint16_t len; + HOST_CH_XFER_STATE URB_StatusTx; + + URB_StatusTx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_out); + + switch (CDC_TxParam.CDCState) { + case CDC_IDLE: + break; + + case CDC_SEND_DATA: + + if ((URB_StatusTx == HOST_CH_XFER_DONE) || (URB_StatusTx == HOST_CH_XFER_IDLE)) { + /* check if send data len exceed CDC_DataItf.length */ + if (CDC_TxParam.DataLength > CDC_Machine.CDC_DataItf.length) { + + len = CDC_Machine.CDC_DataItf.length; + /* send data */ + usb_host_sendbulkdata(pdev, + CDC_TxParam.pRxTxBuff, + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } else { + len = CDC_TxParam.DataLength; + /* send all the remaining data */ + usb_host_sendbulkdata(pdev, + CDC_TxParam.pRxTxBuff, + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } + CDC_TxParam.CDCState = CDC_DATA_SENT; + } + + break; + + case CDC_DATA_SENT: + /* check send complete */ + if (URB_StatusTx == HOST_CH_XFER_DONE) { + /* move txbuffer point */ + CDC_TxParam.pRxTxBuff += len; + + /* ecrease data length */ + CDC_TxParam.DataLength -= len; + + if (CDC_TxParam.DataLength == 0U) { + CDC_TxParam.CDCState = CDC_IDLE; + } else { + CDC_TxParam.CDCState = CDC_SEND_DATA; + } + } else if (URB_StatusTx == HOST_CH_XFER_UNREADY) { + /* send again */ + usb_host_sendbulkdata(pdev, + (CDC_TxParam.pRxTxBuff), + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } else { + ; + } + + break; + + case CDC_READ_DATA: + break; + + case CDC_BUSY: + break; + + case CDC_GET_DATA: + break; + + case CDC_POLL: + break; + + case CDC_CTRL_STATE: + break; + default: + break; + } +} + +/** + * @brief process the cdc data receive state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost) +{ + + if (RX_Enabled == 1U) { + HOST_CH_XFER_STATE URB_StatusRx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + + switch (CDC_RxParam.CDCState) { + + case CDC_IDLE: + + /* check if free rxbuf exceed CDC_DataItf.length */ + if (CDC_RxParam.DataLength < (CDC_RxParam.BufferLen - CDC_Machine.CDC_DataItf.length)) { + /* receive data */ + usb_host_recvbulkdata(pdev, + CDC_RxParam.pFillBuff, + CDC_Machine.CDC_DataItf.length, + CDC_Machine.CDC_DataItf.hc_num_in); + + /* change sate to wait receive complete */ + CDC_RxParam.CDCState = CDC_GET_DATA; + } + break; + + case CDC_GET_DATA: + /* check XFER_DONE */ + if (URB_StatusRx == HOST_CH_XFER_DONE) { + /* increase rx data len */ + CDC_RxParam.DataLength += (uint16_t)pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count; + /* move rxbuff poinit */ + CDC_RxParam.pFillBuff += pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count; + + /* process the received data */ + usb_host_cdc_receivedata(&CDC_RxParam); + + /* chage state back to CDC_IDLE */ + CDC_RxParam.CDCState = CDC_IDLE; + } + break; + + case CDC_READ_DATA: + + break; + + case CDC_BUSY: + + break; + + case CDC_SEND_DATA: + + break; + + case CDC_DATA_SENT: + + break; + + case CDC_POLL: + + break; + + case CDC_CTRL_STATE: + + break; + default: + break; + } + } +} + +/** + * @brief init tx rx buffer for cdc + * @param None + * @retval None + */ +static void usb_host_cdc_txrxparam_init(void) +{ + /* init tx buffer */ + CDC_TxParam.CDCState = CDC_IDLE; + CDC_TxParam.DataLength = 0; + CDC_TxParam.pRxTxBuff = TxBuf; + + /* init rx buffer */ + CDC_RxParam.CDCState = CDC_IDLE; + CDC_RxParam.DataLength = 0; + CDC_RxParam.pFillBuff = RxBuf; + CDC_RxParam.pEmptyBuff = RxBuf; + CDC_RxParam.BufferLen = sizeof(RxBuf); +} + +/** + * @brief call user callback fucntion to process the received data + * @param [in] cdc_Data type of CDC_Xfer_TypeDef + * @retval None + */ +static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data) +{ + uint8_t *ptr; + + if (cdc_Data->pEmptyBuff < cdc_Data->pFillBuff) { + ptr = cdc_Data->pFillBuff; + *ptr = 0x00; + + /* callback user function to process received data */ + UserCb.Receive(cdc_Data->pEmptyBuff, cdc_Data->DataLength); + + cdc_Data->pFillBuff = cdc_Data->pEmptyBuff; + cdc_Data->DataLength = 0; + } +} + +/** + * @brief user call this function to send data to cdc device + * @param [in] data send data buffer + * @param [in] length send length + * @retval None + */ +void usb_host_cdc_senddata(uint8_t *data, uint16_t length) +{ + + if (CDC_TxParam.CDCState == CDC_IDLE) { + CDC_TxParam.pRxTxBuff = data; + CDC_TxParam.DataLength = length; + CDC_TxParam.CDCState = CDC_SEND_DATA; + } +} + +/** + * @brief user call this function to enable receive data from device + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_enable_receive(usb_core_instance *pdev) +{ + RX_Enabled = 1; +} + +/** + * @brief user call this function to disable receive data from device + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_disable_receive(usb_core_instance *pdev) +{ + RX_Enabled = 0; + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h new file mode 100644 index 0000000000..fe03e0ba61 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h @@ -0,0 +1,169 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_class.h + * @brief Head file for usb_host_cdc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CDC_CLASS_H__ +#define __USB_HOST_CDC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_ctrl.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef enum { + CDC_IDLE = 0, + CDC_READ_DATA, + CDC_SEND_DATA, + CDC_DATA_SENT, + CDC_BUSY, + CDC_GET_DATA, + CDC_POLL, + CDC_CTRL_STATE +} +CDC_State; + +typedef struct _CDCXfer { + volatile CDC_State CDCState; + uint8_t *pRxTxBuff; + uint8_t *pFillBuff; + uint8_t *pEmptyBuff; + uint32_t BufferLen; + uint16_t DataLength; +} CDC_Xfer_TypeDef; + +typedef struct CDC_UserCb { + void (*Send)(uint8_t *); + void (*Receive)(uint8_t *, uint32_t len); + +} CDC_Usercb_TypeDef; + +typedef struct _CDC_CommInterface { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t notificationEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_CommInterface_Typedef ; + +typedef struct _CDC_DataInterface { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t cdcOutEp; + uint8_t cdcInEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_DataInterface_Typedef ; + +typedef struct _CDC_Process { + CDC_CommInterface_Typedef CDC_CommItf; + CDC_DataInterface_Typedef CDC_DataItf; +} +CDC_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define COMMUNICATION_DEVICE_CLASS_CODE (0x02U) +#define COMMUNICATION_INTERFACE_CLASS_CODE (0x02U) + +#define DATA_INTERFACE_CLASS_CODE (0x0AU) + +#define RESERVED (0x00U) +#define DIRECT_LINE_CONTROL_MODEL (0x01U) +#define ABSTRACT_CONTROL_MODEL (0x02U) +#define TELEPHONE_CONTROL_MODEL (0x03U) +#define MULTICHANNEL_CONTROL_MODEL (0x04U) +#define CAPI_CONTROL_MODEL (0x05U) +#define ETHERNET_NETWORKING_CONTROL_MODEL (0x06U) +#define ATM_NETWORKING_CONTROL_MODEL (0x07U) + + +#define NO_CLASS_SPECIFIC_PROTOCOL_CODE (0x00U) +#define COMMON_AT_COMMAND (0x01U) +#define VENDOR_SPECIFIC (0xFFU) + + +#define CS_INTERFACE (0x24U) +#define CDC_PAGE_SIZE_64 (0x40U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func CDC_cb; +extern CDC_Usercb_TypeDef UserCb; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void usb_host_cdc_senddata(uint8_t *data, uint16_t length); +void usb_host_cdc_enable_receive(usb_core_instance *pdev); +void usb_host_cdc_disable_receive(usb_core_instance *pdev); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CDC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c new file mode 100644 index 0000000000..6a805d26d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c @@ -0,0 +1,175 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_ctrl.c + * @brief The CDC ctrl functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_ctrl.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern CDC_Requests CDC_ReqState; +CDC_LineCodingTypeDef CDC_SetLineCode; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static CDC_InterfaceDesc_Typedef CDC_Desc; +static CDC_LineCodingTypeDef CDC_GetLineCode; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief host send ctrl request to get line coding + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_GET_LINE_CODING; + phost->ctrlparam.setup.b.wValue.w = 0; + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + + return usb_host_ctrlreq(pdev, phost, CDC_GetLineCode.Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** + * @brief host send ctrl request to set line coding + * to config Baud rate/Stop bits/Parity/Data bits + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_SET_LINE_CODING; + phost->ctrlparam.setup.b.wValue.w = 0; + + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + + phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return usb_host_ctrlreq(pdev, phost, CDC_SetLineCode.Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** + * @brief host send ctrl request to set control line state + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_SET_CONTROL_LINE_STATE; + + phost->ctrlparam.setup.b.wValue.w = CDC_DEACTIVATE_CARRIER_SIGNAL_RTS | \ + CDC_DEACTIVATE_SIGNAL_DTR; + + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + + phost->ctrlparam.setup.b.wLength.w = 0; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief user call this function to issue set line coding request + * before call this funtion user need fill CDC_SetLineCode with config params + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state_backup = phost->host_state ; + phost->host_state = HOST_CLASS_REQ; + CDC_ReqState = CDC_SET_LINE_CODING_RQUEST; +} + +/** + * @brief user call this function to issue get line coding request + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state_backup = phost->host_state ; + phost->host_state = HOST_CLASS_REQ; + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h new file mode 100644 index 0000000000..1d27faea41 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h @@ -0,0 +1,221 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_ctrl.h + * @brief Head file for usb_host_cdc_ctrl.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __USB_HOST_CDC_CTRL_H__ +#define __USB_HOST_CDC_CTRL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_core.h" +#include "usb_host_stdreq.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_cfgch.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef enum { + CDC_SET_LINE_CODING_RQUEST = 0, + CDC_GET_LINE_CODING_RQUEST, + CDC_SET_CONTROL_LINE_STATE_REQUEST, + CDC_ERROR_STATE +} +CDC_Requests; + +#define LINE_CODING_STRUCTURE_SIZE (0x07U) +typedef union _CDC_LineCodingStructure { + uint8_t Array[LINE_CODING_STRUCTURE_SIZE]; + + struct { + + uint32_t dwDTERate; /* Data terminal rate, in bits per second */ + /* Data terminal rate: + such as 9600, 115200, ... */ + + uint8_t bCharFormat; /* Stop bits */ + /* Stop bits: + 0 - 1 Stop bit + 1 - 1.5 Stop bits + 2 - 2 Stop bits */ + + uint8_t bParityType; /* Parity */ + /* Parity: + 0 - None + 1 - Odd + 2 - Even + 3 - Mark + 4 - Space */ + + uint8_t bDataBits; /* Data bits */ + /* Data bits: + (5, 6, 7, 8 or 16) */ + } b; +} +CDC_LineCodingTypeDef; + +typedef struct _FunctionalDescriptorHeader { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) descriptor type */ + uint8_t bDescriptorSubType; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB Class Definitions for Communications + Devices Specification release number in + binary-coded decima */ +} +CDC_HeaderFuncDesc_TypeDef; + +typedef struct _CallMgmtFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Call Management functional descriptor subtype */ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ + /* capabilities: + D7..D2: RESERVED (Reset to zero) + D1: 0 - Device sends/receives call management + information only over the Communications Class + interface. + 1 - Device can send/receive call management + information over a Data Class interface. + D0: 0 - Device does not handle call management + itself. + 1 - Device handles call management itself + The previous bits, in combination, identify which call + management scenario is used. If bit D0 is reset to 0, then the + value of bit D1 is ignored. In this case, bit D1 is reset to zero + for future compatibility.*/ + uint8_t bDataInterface; /* Interface number of Data Class interface optionally used for call management */ + /* Interface number: + Zero based index of the interface in this configuration */ +} +CDC_CallMgmtFuncDesc_TypeDef; + +typedef struct _AbstractCntrlMgmtFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Abstract Control Management functional descriptor subtype */ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ + /* capabilities:(A bit valueof zero means that the request is not supported) + D7..D4: RESERVED (Reset to zero) + D3: 1 - Device supports the notification + Network_Connection. + D2: 1 - Device supports the request Send_Break + D1: 1 - Device supports the request combination of + Set_Line_Coding, Set_Control_Line_State, + Get_Line_Coding, and the notification + Serial_State. + D0: 1 - Device supports the request combination of + Set_Comm_Feature, Clear_Comm_Feature, and + Get_Comm_Feature. + The previous bits, in combination, identify which + requests/notifications are supported by a + CommunicationsClass interface with the SubClass code of + Abstract Control Model. */ +} +CDC_AbstCntrlMgmtFuncDesc_TypeDef; + +typedef struct _UnionFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Union Functional Descriptor SubType */ + uint8_t bControlInterface; /* The interface number of the Communications + or Data Class interface, designated as the + controlling interface for the union.*/ + uint8_t bSubordinateInterface0; /* Interface number of first subordinate interfacein the union. */ + /* ... */ + /* uint8_t bSubordinateInterfaceN-1; */ /* Interface number of N-1 subordinate interfacein the union. */ +} +CDC_UnionFuncDesc_TypeDef; + +typedef struct _USBH_CDCInterfaceDesc { + CDC_HeaderFuncDesc_TypeDef CDC_HeaderFuncDesc; + CDC_CallMgmtFuncDesc_TypeDef CDC_CallMgmtFuncDesc; + CDC_AbstCntrlMgmtFuncDesc_TypeDef CDC_AbstCntrlMgmtFuncDesc; + CDC_UnionFuncDesc_TypeDef CDC_UnionFuncDesc; +} +CDC_InterfaceDesc_Typedef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CDC_SET_LINE_CODING (0x20U) +#define CDC_GET_LINE_CODING (0x21U) +#define CDC_SET_CONTROL_LINE_STATE (0x22U) + +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS (0x0002U) +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS (0x0000U) +#define CDC_ACTIVATE_SIGNAL_DTR (0x0001U) +#define CDC_DEACTIVATE_SIGNAL_DTR (0x0000U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern CDC_LineCodingTypeDef CDC_SetLineCode; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CDC_CTRL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c new file mode 100644 index 0000000000..683f91a9bb --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c @@ -0,0 +1,443 @@ +/** + ******************************************************************************* + * @file usb_host_hid_class.c + * @brief The HID Layer Handlers for USB Host HID class. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" +#include "usb_host_hid_mouseapp.h" +#include "usb_host_hid_keyboardapp.h" +#include "usb_host_driver.h" +#include "usb_host_cfgch.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS LL USB Host Class + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID USB Host HID + * @{ + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost); +void usb_host_hid_itfdeinit(usb_core_instance *pdev); +void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf); +HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); +HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); +HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t duration, + uint8_t reportId); +HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_host_class_callback_func USBH_HID_cb = { + usb_host_hid_itfinit, + usb_host_hid_itfdeinit, + usb_host_hid_classreq, + usb_host_hid_process +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static HID_Machine_TypeDef HID_Machine; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static USB_HOST_HIDDesc_TypeDef HID_Desc; + +__IO static uint8_t start_toggle = 0U; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialize the hid class + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defination by HOST_STATUS + */ +HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost) +{ + uint8_t maxEP; + USBH_HOST *pphost = phost; + + uint8_t epnum; + HOST_STATUS status = HSTATUS_BUSY ; + HID_Machine.state = HID_ERROR; + + if (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == HID_BOOT_CODE) { + switch (pphost->device_prop.devitfdesc[0].bInterfaceProtocol) { + case HID_MOUSE_BOOT_CODE: + HID_Machine.cb = &HID_MOUSE_cb; + break; + case HID_KEYBRD_BOOT_CODE: + HID_Machine.cb = &HID_KEYBRD_cb; + break; + default: + break; + } + HID_Machine.state = HID_IDLE; + HID_Machine.ctl_state = HID_REQ_IDLE; + HID_Machine.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress; + HID_Machine.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + HID_Machine.poll = pphost->device_prop.devepdesc[0][0].bInterval ; + + if (HID_Machine.poll < HID_MIN_POLL) { + HID_Machine.poll = HID_MIN_POLL; + } + + /* Check fo available number of endpoints */ + /* Find the number of EPs in the Interface Descriptor */ + /* Choose the lower number in order not to overrun the buffer allocated */ + maxEP = ((pphost->device_prop.devitfdesc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ? + pphost->device_prop.devitfdesc[0].bNumEndpoints : + USBH_MAX_NUM_ENDPOINTS); + + /* Decode endpoint IN and OUT address from interface descriptor */ + for (epnum = 0U; epnum < maxEP; epnum++) { + if (0U != (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress & 0x80U)) { + HID_Machine.HIDIntInEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + HID_Machine.hc_num_in = usb_host_distrch(pdev, + pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + usb_host_chopen(pdev, + HID_Machine.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + HID_Machine.length); + } else { + HID_Machine.HIDIntOutEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + HID_Machine.hc_num_out = usb_host_distrch(pdev, + pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + usb_host_chopen(pdev, + HID_Machine.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + HID_Machine.length); + } + } + start_toggle = 0U; + status = HSTATUS_OK; + } else { + pphost->user_callbk->huser_devunsupported(); + } + return status; +} + +/** + * @brief deinitialize the channels for the hid class + * @param [in] pdev device instance + * @retval None + */ +void usb_host_hid_itfdeinit(usb_core_instance *pdev) +{ + if (HID_Machine.hc_num_in != 0x00U) { + usb_hchstop(&pdev->regs, HID_Machine.hc_num_in); + (void)usb_host_freech(pdev, HID_Machine.hc_num_in); + HID_Machine.hc_num_in = 0U; + } + + if (HID_Machine.hc_num_out != 0x00U) { + usb_hchstop(&pdev->regs, HID_Machine.hc_num_out); + (void)usb_host_freech(pdev, HID_Machine.hc_num_out); + HID_Machine.hc_num_out = 0U; + } + start_toggle = 0U; +} + +/** + * @brief This function is responsible for handling requests about HID class. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status; + HOST_STATUS classReqStatus; + USBH_HOST *pphost = phost; + status = HSTATUS_BUSY; + switch (HID_Machine.ctl_state) { + case HID_IDLE: + case HID_REQ_GET_HID_DESC: + if (usb_host_get_hiddesc(pdev, pphost, USB_HID_DESC_SIZE) == HSTATUS_OK) { + usb_host_parse_hiddesc(&HID_Desc, pdev->host.Rx_Buffer); + HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC; + } + break; + case HID_REQ_GET_REPORT_DESC: + if (usb_host_get_hidreportdesc(pdev, pphost, HID_Desc.wItemLength) == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_SET_IDLE; + } + break; + case HID_REQ_SET_IDLE: + classReqStatus = usb_host_set_hididle(pdev, pphost, 0U, 0U); + if (classReqStatus == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } else if (classReqStatus == HSTATUS_UNSUPPORTED) { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } else { + /*reserved*/ + } + break; + case HID_REQ_SET_PROTOCOL: + if (usb_host_set_hidprotocol(pdev, pphost, 0U) == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_IDLE; + status = HSTATUS_OK; + } + break; + default: + break; + } + return status; +} + +/** + * @brief This function is to process the state machine for HID data transmitting + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status; + USBH_HOST *pphost = phost; + status = HSTATUS_OK; + switch (HID_Machine.state) { + case HID_IDLE: + HID_Machine.cb->Init(); + HID_Machine.state = HID_SYNC; + case HID_SYNC: + if (usb_ifevenframe(&pdev->regs) == TRUE) { + HID_Machine.state = HID_GET_DATA; + } + break; + case HID_GET_DATA: + usb_host_recvintdata(pdev, + HID_Machine.buff, + HID_Machine.length, + HID_Machine.hc_num_in); + start_toggle = 1U; + HID_Machine.state = HID_POLL; + HID_Machine.timer = (uint16_t)host_driver_getcurrentfrm(pdev); + break; + case HID_POLL: + if ((host_driver_getcurrentfrm(pdev) - HID_Machine.timer) >= HID_Machine.poll) { + HID_Machine.state = HID_GET_DATA; + } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_DONE) { + if (start_toggle == 1U) { + start_toggle = 0U; + HID_Machine.cb->Decode(HID_Machine.buff); + } + } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_STALL) { + /* Issue Clear Feature on interrupt IN endpoint */ + if ((usb_host_clrfeature(pdev, + pphost, + HID_Machine.ep_addr, + HID_Machine.hc_num_in)) == HSTATUS_OK) { + HID_Machine.state = HID_GET_DATA; + } + } else { + /*reserved*/ + } + break; + default: + break; + } + return status; +} + +/** + * @brief Issue hid report descriptor command to the device, parse the report + * descriptor and update the status once the response received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] length the length of the hid descriptor in bytes + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD, + USB_DESC_HID_REPORT, + pdev->host.Rx_Buffer, + length); + return status; +} + +/** + * @brief Issue HID descriptor command to the device, parse the descriptor + * and update the status once the response received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] length length of HID descriptor in bytes + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE + | USB_REQ_TYPE_STANDARD, + USB_DESC_HID, + pdev->host.Rx_Buffer, + length); + return status; +} + +/** + * @brief Set hid application to be idle status. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] duration Duration for HID Idle request + * @param [in] reportId Targetted report ID for Set Idle request + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t duration, + uint8_t reportId) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_IDLE; + phost->ctrlparam.setup.b.wValue.w = ((uint16_t)duration << 8) | (uint16_t)reportId; + + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief Issues a command to set report + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] reportType the report type to be sent + * @param [in] reportId target report ID for set report request + * @param [in] reportLen length of data of report to be sent in bytes + * @param [in] reportBuff report buffer + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t reportType, + uint8_t reportId, + uint8_t reportLen, + uint8_t *reportBuff) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_REPORT; + phost->ctrlparam.setup.b.wValue.w = ((uint16_t)reportType << 8) | (uint16_t)reportId; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = reportLen; + return usb_host_ctrlreq(pdev, phost, reportBuff, reportLen); +} + +/** + * @brief Set protocol state of the hid application. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] protocol protocol for HID application + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_PROTOCOL; + if (protocol != 0U) { + /* Boot Protocol */ + phost->ctrlparam.setup.b.wValue.w = 0U; + } else { + /* Report Protocol */ + phost->ctrlparam.setup.b.wValue.w = 1U; + } + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief parse the HID descriptor + * @param [in] desc used to get the fields parsed from the data buffer + * @param [in] buf Buffer where the source descriptor is available + * @retval None + */ +void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf) +{ + desc->bLength = *(uint8_t *)(buf + 0); + desc->bDescriptorType = *(uint8_t *)(buf + 1); + desc->bcdHID = SMALL_END(buf + 2); + desc->bCountryCode = *(uint8_t *)(buf + 4); + desc->bNumDescriptors = *(uint8_t *)(buf + 5); + desc->bReportDescriptorType = *(uint8_t *)(buf + 6); + desc->wItemLength = SMALL_END(buf + 7); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h new file mode 100644 index 0000000000..101792f3f6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h @@ -0,0 +1,167 @@ +/** + ******************************************************************************* + * @file usb_host_hid_class.h + * @brief header file for the usb_host_hid_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_CLASS_H__ +#define __USB_HOST_HID_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* States for HID State Machine */ +typedef enum { + HID_IDLE = 0, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +} +HID_State; + +typedef enum { + HID_REQ_IDLE = 0, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, + +} +HID_CtlState; + +typedef struct { + void (*Init)(void); + void (*Decode)(uint8_t *data); + +} HID_cb_TypeDef; + +typedef struct { + uint8_t ReportID; + uint8_t ReportType; + uint16_t UsagePage; + uint32_t Usage[2]; + uint32_t NbrUsage; + uint32_t UsageMin; + uint32_t UsageMax; + int32_t LogMin; + int32_t LogMax; + int32_t PhyMin; + int32_t PhyMax; + int32_t UnitExp; + uint32_t Unit; + uint32_t ReportSize; + uint32_t ReportCnt; + uint32_t Flag; + uint32_t PhyUsage; + uint32_t AppUsage; + uint32_t LogUsage; +} HID_Report_TypeDef; + +/* Structure for HID process */ +typedef struct { + uint8_t buff[64]; + uint8_t hc_num_in; + uint8_t hc_num_out; + HID_State state; + uint8_t HIDIntOutEp; + uint8_t HIDIntInEp; + HID_CtlState ctl_state; + uint16_t length; + uint8_t ep_addr; + uint16_t poll; + __IO uint16_t timer; + HID_cb_TypeDef *cb; +} HID_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_HID_REQ_GET_REPORT (0x01) +#define USB_HID_GET_IDLE (0x02) +#define USB_HID_GET_PROTOCOL (0x03) +#define USB_HID_SET_REPORT (0x09) +#define USB_HID_SET_IDLE (0x0A) +#define USB_HID_SET_PROTOCOL (0x0B) + +#define HID_MIN_POLL (10U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func USBH_HID_cb; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t reportType, + uint8_t reportId, + uint8_t reportLen, + uint8_t *reportBuff); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_CLASS_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c new file mode 100644 index 0000000000..114b53c2fa --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c @@ -0,0 +1,277 @@ +/** + ******************************************************************************* + * @file usb_host_hid_keyboardapp.c + * @brief The application layer for USB Host HID Keyboard handling + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_keyboardapp.h" +#include "usb_host_user.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void keyboard_init(void); +void keyboard_decode(uint8_t *pbuf); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined (__CC_ARM) /*!< ARM Compiler */ +__align(4) +#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma pack(4) +#endif /* __CC_ARM */ +#endif + +HID_cb_TypeDef HID_KEYBRD_cb = { + keyboard_init, + keyboard_decode +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static const uint8_t HID_KEYBRD_Codes[] = { + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD +static const uint8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const uint8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const uint8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const uint8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; +#endif + +/** + * @brief Initialize the keyboard function. + * @param None + * @retval None + */ +void keyboard_init(void) +{ + user_keyboard_init(); +} + +/** + * @brief The function is to decode the pressed keys when receives key value. + * @param [in] pbuf buffer contain the HID IN report data. + * @retval None + */ +void keyboard_decode(uint8_t *pbuf) +{ + static uint8_t shift; + static uint8_t keys[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; + static uint8_t key_newest; + static uint8_t nbr_keys; + static uint8_t nbr_keys_new; + static uint8_t nbr_keys_last; + uint8_t ix; + uint8_t jx; + uint8_t error; + uint8_t output; + + nbr_keys = 0U; + nbr_keys_new = 0U; + nbr_keys_last = 0U; + key_newest = 0U; + + /* Check if Shift key is pressed */ + if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) { + shift = TRUE; + } else { + shift = FALSE; + } + + error = FALSE; + /* Check for the value of pressed key */ + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if ((pbuf[ix] == 0x01U) || (pbuf[ix] == 0x02U) || (pbuf[ix] == 0x03U)) { + error = TRUE; + } + } + if (error == TRUE) { + return; + } + nbr_keys = 0U; + nbr_keys_new = 0U; + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if (pbuf[ix] != 0U) { + keys[nbr_keys] = pbuf[ix]; + nbr_keys++; + for (jx = 0U; jx < nbr_keys_last; jx++) { + if (pbuf[ix] == keys_last[jx]) { + break; + } + } + if (jx == nbr_keys_last) { + keys_new[nbr_keys_new] = pbuf[ix]; + nbr_keys_new++; + } + } + } + if (nbr_keys_new == 1U) { + key_newest = keys_new[0]; + + if (shift == TRUE) { + output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; + } else { + output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; + } + /* call user process handle */ + user_keyboard_dataprocess(output); + } else { + key_newest = 0x00U; + } + nbr_keys_last = nbr_keys; + for (ix = 0U; ix < KBR_MAX_NBR_PRESSED; ix++) { + keys_last[ix] = keys[ix]; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h new file mode 100644 index 0000000000..8e662c1a19 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h @@ -0,0 +1,99 @@ +/** + ******************************************************************************* + * @file usb_host_hid_keyboardapp.h + * @brief Head file for usb_host_hid_keyboardapp.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_KEYBOARDAPP_H__ +#define __USB_HOST_HID_KEYBOARDAPP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define QWERTY_KEYBOARD +/* #define AZERTY_KEYBOARD */ + +#define KBD_LEFT_CTRL (0x01U) +#define KBD_LEFT_SHIFT (0x02U) +#define KBD_LEFT_ALT (0x04U) +#define KBD_LEFT_GUI (0x08U) +#define KBD_RIGHT_CTRL (0x10U) +#define KBD_RIGHT_SHIFT (0x20U) +#define KBD_RIGHT_ALT (0x40U) +#define KBD_RIGHT_GUI (0x80U) + +#define KBR_MAX_NBR_PRESSED (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern HID_cb_TypeDef HID_KEYBRD_cb; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_KEYBOARDAPP_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c new file mode 100644 index 0000000000..418db2c623 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file usb_host_hid_mouseapp.c + * @brief The application layer for USB Host HID Mouse Handling. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_mouseapp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +void mouse_init(void); +void mouse_decode(uint8_t *data); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined (__CC_ARM) /*!< ARM Compiler */ +__align(4) +#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma pack(4) +#elif defined (__TASKING__) /*!< TASKING Compiler */ +__align(4) +#endif /* __CC_ARM */ +#endif + +HID_MOUSE_Data_TypeDef HID_MOUSE_Data; +HID_cb_TypeDef HID_MOUSE_cb = { + mouse_init, + mouse_decode, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialize the mouse application of the hid class + * @param None + * @retval None + */ +void mouse_init(void) +{ + /* Call User Init*/ + user_mouse_init(); +} + +/** + * @brief decode the mouse report data + * @param [in] data buffer of the hid report data + * @retval None + */ +void mouse_decode(uint8_t *data) +{ + HID_MOUSE_Data.button = data[0]; + HID_MOUSE_Data.x = data[1]; + HID_MOUSE_Data.y = data[2]; + user_mouse_dataprocess(&HID_MOUSE_Data); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h new file mode 100644 index 0000000000..284eeba129 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h @@ -0,0 +1,92 @@ +/** + ******************************************************************************* + * @file usb_host_hid_mouseapp.h + * @brief Head file for usb_host_hid_mouseapp.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_MOUSEAPP_H__ +#define __USB_HOST_HID_MOUSEAPP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct _HID_MOUSE_Data { + uint8_t z; + uint8_t button; + uint8_t x; /* Not Supported */ + uint8_t y; +} +HID_MOUSE_Data_TypeDef; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern HID_cb_TypeDef HID_MOUSE_cb; +extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void user_mouse_init(void); +void user_mouse_dataprocess(HID_MOUSE_Data_TypeDef *data); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_MOUSEAPP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c new file mode 100644 index 0000000000..a01939e9df --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c @@ -0,0 +1,449 @@ +/** + ******************************************************************************* + * @file usb_host_msc_bot.c + * @brief mass storage related functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_def.h" +#include "usb_host_int.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC USB Host MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData; + +USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData; + +static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initializes original state of the mass storage parameters + * @param [in] pdev device instance + * @retval None + */ +void usb_host_msc_init(usb_core_instance *pdev) +{ + if (host_driver_ifdevconnected(pdev) != 0UL) { + USBH_MSC_CBWData.field.CBWSignature = HOST_MSC_BOT_CBW_SIGNATURE; + USBH_MSC_CBWData.field.CBWTag = HOST_MSC_BOT_CBW_TAG; + USBH_MSC_CBWData.field.CBWLUN = 0U; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + } + BOTStallErrorCount = 0UL; + MSCErrorCount = 0U; +} + +/** + * @brief manages the different states of BOT transfer and updates the + * status for the upper layer. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + uint8_t xferDirection, index; + static uint32_t remainingDataLength; + static uint8_t *datapointer, *datapointer_prev; + static uint8_t error_direction; + HOST_STATUS status; + + HOST_CH_XFER_STATE URB_Status; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + + switch (USBH_MSC_BOTXferParam.BOTState) { + case HOST_MSC_SEND_CBW: + /* send a CBW */ + usb_host_sendbulkdata(pdev, + &USBH_MSC_CBWData.CBWArray[0], + HOST_MSC_BOT_CBW_PACKET_LENGTH, + MSC_Machine.hc_num_out); + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SEND_CBW; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SENT_CBW; + break; + case HOST_MSC_SENT_CBW: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + BOTStallErrorCount = 0U; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SENT_CBW; + /* If the CBW packet is sent successful, then update the state */ + xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK); + if (USBH_MSC_CBWData.field.CBWTransferLength != 0UL) { + remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ; + datapointer = USBH_MSC_BOTXferParam.pRxTxBuff; + datapointer_prev = datapointer; + /* If there has data transfer stage, update the direction whether it is D2H or H2D */ + if (xferDirection == USB_D2H) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAIN_STATE; + } else { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAOUT_STATE; + } + } else { + /* If there has not data transfer stage also update the state */ + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } + break; + case HOST_CH_XFER_UNREADY: + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + break; + case HOST_CH_XFER_STALL: + error_direction = HOST_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + break; + default: + break; + } + break; + + case HOST_MSC_BOT_DATAIN_STATE: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in); + if ((URB_Status == HOST_CH_XFER_DONE) \ + || (USBH_MSC_BOTXferParam.BOTStateBkp != HOST_MSC_BOT_DATAIN_STATE)) { + BOTStallErrorCount = 0U; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAIN_STATE; + + if (remainingDataLength > MSC_Machine.MSC_BulkInEpSize) { + usb_host_recvbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkInEpSize, + MSC_Machine.hc_num_in); + remainingDataLength -= MSC_Machine.MSC_BulkInEpSize; + datapointer = datapointer + MSC_Machine.MSC_BulkInEpSize; + } else if (remainingDataLength == 0UL) { + /* If value was 0, and successful transfer, then change the state */ + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } else { + usb_host_recvbulkdata(pdev, + datapointer, + (uint16_t)remainingDataLength, + MSC_Machine.hc_num_in); + remainingDataLength = 0UL; + } + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + } else { + ; + } + break; + case HOST_MSC_BOT_DATAOUT_STATE: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out); + if (URB_Status == HOST_CH_XFER_DONE) { + BOTStallErrorCount = 0UL; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAOUT_STATE; + if (remainingDataLength > MSC_Machine.MSC_BulkOutEpSize) { + usb_host_sendbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + datapointer_prev = datapointer; + datapointer = datapointer + MSC_Machine.MSC_BulkOutEpSize; + + remainingDataLength = remainingDataLength - MSC_Machine.MSC_BulkOutEpSize; + } else if (remainingDataLength == 0UL) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } else { + usb_host_sendbulkdata(pdev, + datapointer, + (uint16_t)remainingDataLength, + MSC_Machine.hc_num_out); + remainingDataLength = 0UL; + } + } else if (URB_Status == HOST_CH_XFER_UNREADY) { + if (datapointer != datapointer_prev) { + usb_host_sendbulkdata(pdev, + (datapointer - MSC_Machine.MSC_BulkOutEpSize), + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + } else { + usb_host_sendbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + } + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + } else { + ; + } + break; + + case HOST_MSC_RECEIVE_CSW_STATE: + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH; + for (index = 0U; index < HOST_MSC_CSW_LENGTH; index++) { + USBH_MSC_CSWData.CSWArray[index] = 0U; + } + + USBH_MSC_CSWData.CSWArray[0] = 0U; + usb_host_recvbulkdata(pdev, + USBH_MSC_BOTXferParam.pRxTxBuff, + HOST_MSC_CSW_MAX_LENGTH, + MSC_Machine.hc_num_in); + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_DECODE_CSW; + + break; + + case HOST_MSC_DECODE_CSW: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in); + if (URB_Status == HOST_CH_XFER_DONE) { + BOTStallErrorCount = 0UL; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ; + USBH_MSC_BOTXferParam.BOTXferStatus = usb_host_msc_cswdecode(pdev, phost); + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN; + } else { + ; + } + break; + + case HOST_MSC_BOT_ERROR_IN: + status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_IN); + if (status == HSTATUS_OK) { + if (error_direction == HOST_MSC_BOTH_DIR) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + } else { + /* switch back to the original state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + } else if (status == HSTATUS_UNRECOVERED_ERROR) { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + break; + case HOST_MSC_BOT_ERROR_OUT: + status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_OUT); + if (status == HSTATUS_OK) { + /* switch back to the original state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } else if (status == HSTATUS_UNRECOVERED_ERROR) { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + break; + + default: + break; + } + } +} + +/** + * @brief manages the different Error handling for STALL + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] direction IN / OUT + * @retval None + */ +HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction) +{ + HOST_STATUS status; + + status = HSTATUS_BUSY; + + switch (direction) { + case HOST_MSC_DIR_IN: + /* send ClrFeture on Bulk IN endpoint */ + status = usb_host_clrfeature(pdev, + phost, + MSC_Machine.MSC_BulkInEp, + MSC_Machine.hc_num_in); + break; + case HOST_MSC_DIR_OUT: + /* send ClrFeature on Bulk OUT endpoint */ + status = usb_host_clrfeature(pdev, + phost, + MSC_Machine.MSC_BulkOutEp, + MSC_Machine.hc_num_out); + break; + default: + break; + } + BOTStallErrorCount++; + if (BOTStallErrorCount > 4UL) { + status = HSTATUS_UNRECOVERED_ERROR; + } + return status; +} + +/** + * @brief Decodes the CSW received by the device and updates the same to upper layer + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval On success USB_HOST_MSC_OK, on failure USB_HOST_MSC_FAIL + */ +uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost) +{ + USB_HOST_MSC_STATUS status; + uint32_t dataXferCount; + status = USB_HOST_MSC_FAIL; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + dataXferCount = host_driver_getxfercnt(pdev, MSC_Machine.hc_num_in); + if (dataXferCount != HOST_MSC_CSW_LENGTH) { + /*(4) Hi > Dn (Host expects to receive data from the device, + Device intends to transfer no data) + (5) Hi > Di (Host expects to receive data from the device, + Device intends to send data to the host) + (9) Ho > Dn (Host expects to send data to the device, + Device intends to transfer no data) + (11) Ho > Do (Host expects to send data to the device, + Device intends to receive data from the host)*/ + status = USB_HOST_MSC_PHASE_ERROR; + } else { + /* CSW length is Correct */ + + /* Check validity of the CSW Signature and CSWStatus */ + if (USBH_MSC_CSWData.field.dCSWSignature == HOST_MSC_BOT_CSW_SIGNATURE) { + /* Check Condition 1. dCSWSignature is equal to 53425355h */ + if (USBH_MSC_CSWData.field.dCSWTag == USBH_MSC_CBWData.field.CBWTag) { + /* Check Condition 3. dCSWTag matches the dCBWTag from the + corresponding CBW */ + if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_OK) { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + + Hn Host expects no data transfers + Hi Host expects to receive data from the device + Ho Host expects to send data to the device + + Dn Device intends to transfer no data + Di Device intends to send data to the host + Do Device intends to receive data from the host + + Section 6.7 + (1) Hn = Dn (Host expects no data transfers, + Device intends to transfer no data) + (6) Hi = Di (Host expects to receive data from the device, + Device intends to send data to the host) + (12) Ho = Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + status = USB_HOST_MSC_OK; + } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_FAIL) { + status = USB_HOST_MSC_FAIL; + } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_PHASE_ERROR) { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + Section 6.7 + (2) Hn < Di ( Host expects no data transfers, + Device intends to send data to the host) + (3) Hn < Do ( Host expects no data transfers, + Device intends to receive data from the host) + (7) Hi < Di ( Host expects to receive data from the device, + Device intends to send data to the host) + (8) Hi <> Do ( Host expects to receive data from the device, + Device intends to receive data from the host) + (10) Ho <> Di (Host expects to send data to the device, + Di Device intends to send data to the host) + (13) Ho < Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + status = USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + } + } else { + status = USB_HOST_MSC_PHASE_ERROR; + } + } + } + + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)status; + return (uint8_t)status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h new file mode 100644 index 0000000000..b51cc3bbd9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h @@ -0,0 +1,162 @@ +/** + ******************************************************************************* + * @file usb_host_msc_bot.h + * @brief Head file for usb_host_msc_bot.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_BOT_H__ +#define __USB_HOST_MSC_BOT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef union _USBH_CBW_Block { + struct __CBW { + uint32_t CBWSignature; + uint32_t CBWTag; + uint32_t CBWTransferLength; + uint8_t CBWFlags; + uint8_t CBWLUN; + uint8_t CBWLength; + uint8_t CBWCB[16]; + } field; + uint8_t CBWArray[31]; +} HostCBWPkt_TypeDef; + +typedef struct { + uint8_t MSCState; + uint8_t MSCStateBkp; + uint8_t MSCStateCurrent; + uint8_t CmdStateMachine; + uint8_t BOTState; + uint8_t BOTStateBkp; + uint8_t *pRxTxBuff; + uint16_t DataLength; + uint8_t BOTXferStatus; +} USB_HOST_BOTXFER_TypeDef; + +typedef union { + struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t dCSWStatus; + } field; + uint8_t CSWArray[13]; +} HOST_CSW_PACKET_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define HOST_MSC_BOT_INIT_STATE (0U) +#define HOST_MSC_BOT_RESET (1U) +#define HOST_MSC_GET_MAX_LUN (2U) +#define HOST_MSC_TEST_UNIT_READY (3U) +#define HOST_MSC_READ_CAPACITY10 (4U) +#define HOST_MSC_MODE_SENSE6 (5U) +#define HOST_MSC_REQUEST_SENSE (6U) +#define HOST_MSC_BOT_USB_TRANSFERS (7U) +#define HOST_MSC_DEFAULT_APPLI_STATE (8U) +#define HOST_MSC_CTRL_ERROR_STATE (9U) +#define HOST_MSC_UNRECOVERED_STATE (10U) + +#define HOST_MSC_SEND_CBW (1U) +#define HOST_MSC_SENT_CBW (2U) +#define HOST_MSC_BOT_DATAIN_STATE (3U) +#define HOST_MSC_BOT_DATAOUT_STATE (4U) +#define HOST_MSC_RECEIVE_CSW_STATE (5U) +#define HOST_MSC_DECODE_CSW (6U) +#define HOST_MSC_BOT_ERROR_IN (7U) +#define HOST_MSC_BOT_ERROR_OUT (8U) + +#define HOST_MSC_BOT_CBW_SIGNATURE (0x43425355UL) +#define HOST_MSC_BOT_CBW_TAG (0x20304050UL) +#define HOST_MSC_BOT_CSW_SIGNATURE (0x53425355UL) +#define HOST_MSC_CSW_DATA_LENGTH (13U) +#define HOST_MSC_BOT_CBW_PACKET_LENGTH (31U) +#define HOST_MSC_CSW_LENGTH (13U) +#define HOST_MSC_CSW_MAX_LENGTH (63U) +#define HOST_MSC_DIR_IN (0U) +#define HOST_MSC_DIR_OUT (1U) +#define HOST_MSC_BOTH_DIR (2U) +#define HOST_MSC_PAGE_LENGTH (512UL) + +#define CBW_CB_LENGTH (16U) +#define CBW_LENGTH (10U) +#define CBW_LENGTH_TEST_UNIT_READY (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam; +extern HostCBWPkt_TypeDef USBH_MSC_CBWData; +extern HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_msc_init(usb_core_instance *pdev); +extern void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost); +extern uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost); +extern HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_BOT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c new file mode 100644 index 0000000000..b1fe4e0d49 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c @@ -0,0 +1,395 @@ +/** + ******************************************************************************* + * @file usb_host_msc_class.c + * @brief The MSC class driver functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_core.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USBH_MSC_ERROR_RETRY_LIMIT (10U) + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost); +void usb_host_msc_itfdeinit(usb_core_instance *pdev); +HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost); + +HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_msc_error_process(USB_HOST_MSC_STATUS status); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +uint8_t MSCErrorCount = 0U; + +usb_host_class_callback_func USBH_MSC_cb = { + &usb_host_msc_itfinit, + &usb_host_msc_itfdeinit, + &usb_host_msc_classreq, + &usb_host_msc_process, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief This request is used to issue a request to reset the msc device and + * its related interface. This class-specific request shall prepare the + * device for the next CBW from the host. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + phost->ctrlparam.setup.b.bRequest = USB_REQ_BOT_RESET; + phost->ctrlparam.setup.b.wValue.w = 0U; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief this request is used to issue a request to get the max logic unit of + * the msc device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_MAX_LUN; + phost->ctrlparam.setup.b.wValue.w = 0U; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 1U; + return usb_host_ctrlreq(pdev, phost, MSC_Machine.buff, 1U); +} + +/** + * @brief The function is used for handling errors during processing the MSC + * state machine + * @param [in] status + * @retval None + */ +void usb_host_msc_error_process(USB_HOST_MSC_STATUS status) +{ + switch (status) { + case USB_HOST_MSC_FAIL: + MSCErrorCount++; + if (MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT) { + /* Try MSC level error recovery, Issue the request Sense to get + driver error reason */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_REQUEST_SENSE; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + } else { + /* Error trials exceeded the limit, go to unrecovered state */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE; + } + break; + case USB_HOST_MSC_PHASE_ERROR: + /* Phase error, Go to Unrecoovered state */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE; + break; + default: + break; + } +} + +/** + * @brief Interface initialization for msc class application, the channels for + * the IN and OUT EP will be distributed. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + + if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == MSC_CLASS) && \ + (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == MSC_PROTOCOL)) { + if ((pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U) == 0x80U) { + MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + } else { + MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0] [0].wMaxPacketSize; + } + if ((pphost->device_prop.devepdesc[0][1].bEndpointAddress & 0x80U) == 0x80U) { + MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress); + MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize; + } else { + MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress); + MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize; + } + /* distribute the channels for the EPs */ + MSC_Machine.hc_num_out = usb_host_distrch(pdev, MSC_Machine.MSC_BulkOutEp); + MSC_Machine.hc_num_in = usb_host_distrch(pdev, MSC_Machine.MSC_BulkInEp); + /* open the channels that have distributed */ + usb_host_chopen(pdev, + MSC_Machine.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + MSC_Machine.MSC_BulkOutEpSize); + usb_host_chopen(pdev, + MSC_Machine.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + MSC_Machine.MSC_BulkInEpSize); + } else { + pphost->user_callbk->huser_devunsupported(); + } + return HSTATUS_OK ; +} + +/** + * @brief deinitialize interface of msc class by freeing host channels + * @param [in] pdev device instance + * @retval None + */ +void usb_host_msc_itfdeinit(usb_core_instance *pdev) +{ + if (MSC_Machine.hc_num_out != 0U) { + usb_hchstop(&pdev->regs, MSC_Machine.hc_num_out); + (void)usb_host_freech(pdev, MSC_Machine.hc_num_out); + MSC_Machine.hc_num_out = 0U; + } + if (MSC_Machine.hc_num_in != 0U) { + usb_hchstop(&pdev->regs, MSC_Machine.hc_num_in); + (void)usb_host_freech(pdev, MSC_Machine.hc_num_in); + MSC_Machine.hc_num_in = 0U; + } +} + +/** + * @brief initialize the msc state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost) +{ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_INIT_STATE; + return HSTATUS_OK; +} + +/** + * @brief process the msc state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_BUSY; + USB_HOST_MSC_STATUS mscStatus; + uint8_t appliStatus; + static uint8_t maxLunExceed = FALSE; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.MSCState) { + case HOST_MSC_BOT_INIT_STATE: + usb_host_msc_init(pdev); + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_RESET; + break; + case HOST_MSC_BOT_RESET: + /* issue a request to reset the bot. */ + status = usb_host_msc_bot_reset(pdev, phost); + if (status == HSTATUS_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_GET_MAX_LUN; + } + if (status == HSTATUS_UNSUPPORTED) { + /* if the request fails, it needs to move to next state and should save the next state as backup */ + USBH_MSC_BOTXferParam.MSCStateBkp = HOST_MSC_GET_MAX_LUN; + /* a clear feature should be issued if the request fails. */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_CTRL_ERROR_STATE; + } + break; + case HOST_MSC_GET_MAX_LUN: + /* issue a request to get the max logical unit(MAXLUN). */ + status = usb_host_msc_maxlun_get(pdev, phost); + if (status == HSTATUS_OK) { + MSC_Machine.maxLun = *(MSC_Machine.buff) ; + if ((MSC_Machine.maxLun > 0U) && (maxLunExceed == FALSE)) { + maxLunExceed = TRUE; + pphost->user_callbk->huser_devunsupported(); + break; + } + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_TEST_UNIT_READY; + } + + if (status == HSTATUS_UNSUPPORTED) { + /* if the request fails, it needs to move to next state and should save the next state as backup */ + USBH_MSC_BOTXferParam.MSCStateBkp = HOST_MSC_TEST_UNIT_READY; + /* a clear feature should be issued if the request fails. */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_CTRL_ERROR_STATE; + } + break; + case HOST_MSC_CTRL_ERROR_STATE: + /* issue a request to clear feature */ + status = usb_host_clrfeature(pdev, + phost, + 0x00U, + pphost->ctrlparam.hc_num_out); + if (status == HSTATUS_OK) { + /* If GetMaxLun Request not support, assume Single LUN configuration */ + MSC_Machine.maxLun = 0U; + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + } + break; + case HOST_MSC_TEST_UNIT_READY: + /* issue the request Test Unit Ready[0] of SCSI command */ + mscStatus = usb_host_msc_TestUnitReady(pdev); + + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_READ_CAPACITY10; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + + case HOST_MSC_READ_CAPACITY10: + /* issue the request Read Capacity[0] of SCSI command. */ + mscStatus = usb_host_msc_ReadCapacity10(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_MODE_SENSE6; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_MODE_SENSE6: + /* issue the request ModeSense6 of SCSI command for detecting whelth the deviec is write-protected. */ + mscStatus = usb_host_msc_ModeSense6(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_REQUEST_SENSE: + /* issue the request RequestSense of SCSI command for retreiving error code. */ + mscStatus = usb_host_msc_RequestSense(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_BOT_USB_TRANSFERS: + /* handle the BOT state machine. */ + usb_host_msc_botxferprocess(pdev, phost); + break; + case HOST_MSC_DEFAULT_APPLI_STATE: + /* handle the user callback for the msc application. */ + appliStatus = pphost->user_callbk->huser_application(); + if (appliStatus == 0U) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE; + } else if (appliStatus == 1U) { + /* deinit requested from the application layer. */ + status = HSTATUS_APP_DEINIT; + } else { + ; + } + break; + case HOST_MSC_UNRECOVERED_STATE: + status = HSTATUS_UNRECOVERED_ERROR; + break; + default: + break; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h new file mode 100644 index 0000000000..d37111ce7e --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h @@ -0,0 +1,113 @@ +/** + ******************************************************************************* + * @file usb_host_msc_class.h + * @brief Head file for usb_host_msc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_CLASS_H__ +#define __USB_HOST_MSC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_core.h" +#include "usb_host_stdreq.h" +#include "usb_bsp.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_cfgch.h" +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* Structure for MSC process */ +typedef struct { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t MSC_BulkOutEp; + uint8_t MSC_BulkInEp; + uint16_t MSC_BulkInEpSize; + uint16_t MSC_BulkOutEpSize; + uint8_t buff[USBH_MSC_MPS_SIZE]; + uint8_t maxLun; +} MSC_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_REQ_BOT_RESET (0xFFU) +#define USB_REQ_GET_MAX_LUN (0xFEU) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func USBH_MSC_cb; +extern MSC_Machine_TypeDef MSC_Machine; +extern uint8_t MSCErrorCount; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c new file mode 100644 index 0000000000..d1e68d978c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c @@ -0,0 +1,241 @@ +/** + ******************************************************************************* + * @file usb_host_msc_fatfs.c + * @brief The fatfs functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_app_conf.h" +#include "usb_host_driver.h" +#ifdef USB_MSC_FAT_VALID +#include "ff.h" +#include "diskio.h" +#include "usb_host_msc_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +extern usb_core_instance usb_app_instance; +extern USBH_HOST usb_app_host; + +/** + * @brief Initialize Disk Drive + * @param [in] drv Physical drive number (0) + * @retval DSTATUS + */ +DSTATUS disk_initialize(BYTE drv) +{ + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + Stat &= (DSTATUS)~STA_NOINIT; + } + return Stat; +} + +/** + * @brief Get Disk Status + * @param [in] drv Physical drive number (0) + * @retval DSTATUS + */ +DSTATUS disk_status(BYTE drv) +{ + DSTATUS status = Stat; + if (drv != 0U) { + status = STA_NOINIT; /* Supports only single drive */ + } + return status; +} + +/** + * @brief Read Sector(s) + * @param [in] drv Physical drive number (0) + * @param [in] buff Pointer to the data buffer to store read data + * @param [in] sector Start sector number (LBA) + * @param [in] count Sector count (1..255) + * @retval DSTATUS + */ +DRESULT disk_read(BYTE pdrv, BYTE *buff, LBA_t sector, UINT count) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK; + + if ((pdrv != 0U) || (count == 0UL)) { + return RES_PARERR; + } + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + + do { + status = usb_host_msc_Read10(&usb_app_instance, buff, sector, 512UL * (uint32_t)count); + usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host); + + if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) { + return RES_ERROR; + } + } while (status == USB_HOST_MSC_BUSY); + } + + if (status == USB_HOST_MSC_OK) { + return RES_OK; + } + return RES_ERROR; + +} + + +#if _READONLY == 0 +/** + * @brief Write Sector(s) + * @param [in] drv Physical drive number (0) + * @param [in] buff Pointer to the data to be written + * @param [in] sector Start sector number (LBA) + * @param [in] count Sector count (1..255) + * @retval DSTATUS + */ +DRESULT disk_write(BYTE pdrv, const BYTE *buff, LBA_t sector, UINT count) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK; + + if ((pdrv != 0U) || (count == 0UL)) { + return RES_PARERR; + } + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + if ((Stat & STA_PROTECT) == STA_PROTECT) { + return RES_WRPRT; + } + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + do { + status = usb_host_msc_Write10(&usb_app_instance, (BYTE *)buff, sector, 512UL * (uint32_t)count); + usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host); + + if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) { + return RES_ERROR; + } + } while (status == USB_HOST_MSC_BUSY); + } + + if (status == USB_HOST_MSC_OK) { + return RES_OK; + } + return RES_ERROR; +} +#endif /* _READONLY == 0 */ + +//#if _USE_IOCTL != 0 +/** + * @brief Miscellaneous Functions + * @param [in] drv Physical drive number (0) + * @param [in] ctrl Control code + * @param [in] buff Buffer to send/receive control data + ** + * @retval DSTATUS + */ +DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) +{ + DRESULT res; + + if (pdrv != 0U) { + return RES_PARERR; + } + + res = RES_ERROR; + + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + + switch (cmd) { + case CTRL_SYNC : /* Make sure that no pending write process */ + res = RES_OK; + break; + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + *(DWORD *)buff = (DWORD) USB_HOST_MSC_Param.MSC_Capacity; + res = RES_OK; + break; + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD *)buff = 512U; + res = RES_OK; + break; + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + *(DWORD *)buff = 512UL; + break; + default: + res = RES_PARERR; + break; + } + return res; +} +//#endif +#endif /* _USE_IOCTL != 0 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c new file mode 100644 index 0000000000..78b89e5e1c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c @@ -0,0 +1,528 @@ +/** + ******************************************************************************* + * @file usb_host_msc_scsi.c + * @brief The SCSI commands。 + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_def.h" +#include "usb_host_driver.h" +#include + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +MSC_PARAMETER USB_HOST_MSC_Param; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) +#pragma data_alignment=4 +#endif +#endif +__USB_ALIGN_BEGIN static uint8_t USB_HOST_DataInBuf[512]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Issues 'Test Unit Ready' command to the device. Once the response + * received, it updates the status to upper layer, the length of the + * command are 31bytes. + * @param [in] pdev device instance + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + USBH_MSC_CBWData.field.CBWTransferLength = 0UL; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_TEST_UNIT_READY; + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + default: + break; + } + } + return status; +} + +/** + * @brief Issue the 'Read capacity10' command to the device. Once the response + * received, it updates the status to upper layer + * @param [in] pdev device instance + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_READ_CAPACITY10; + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine manage the other + transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /*assign the capacity*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[3]) = USB_HOST_DataInBuf[0]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[2]) = USB_HOST_DataInBuf[1]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[1]) = USB_HOST_DataInBuf[2]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[0]) = USB_HOST_DataInBuf[3]; + /*assign the page length*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[1]) = USB_HOST_DataInBuf[6]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[0]) = USB_HOST_DataInBuf[7]; + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief Issue the 'Mode Sense6' Command to the device. This function is used + * for reading the WriteProtect Status of the MSC device. + * @param [in] pdev device instance + * @retval status by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_MODE_SENSE6; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | \ + MODE_SENSE_PAGE_CODE; + + USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + + /* Start the transfer, then let the state machine manage the other + transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Assign the Write Protect status */ + /* If WriteProtect = 0, Writing is allowed + If WriteProtect != 0, Disk is Write Protected */ + if (0U != (USB_HOST_DataInBuf[2] & MASK_MODE_SENSE_WRITE_PROTECT)) { + USB_HOST_MSC_Param.MSC_WriteProtect = DISK_WRITE_PROTECTED; + } else { + USB_HOST_MSC_Param.MSC_WriteProtect = 0U; + } + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief usb_host_msc_RequestSense + * Issues the Request Sense command to the device. Once the response + * received, it updates the status to upper layer + * @param [in] pdev device instance + * @retval status defined by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint8_t index; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = \ + ALLOCATION_LENGTH_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_REQUEST_SENSE; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine magage + the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Get Sense data*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[3]) = USB_HOST_DataInBuf[0]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[2]) = USB_HOST_DataInBuf[1]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[1]) = USB_HOST_DataInBuf[2]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[0]) = USB_HOST_DataInBuf[3]; + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief issue the 'Write10 ' command to the device. Once the response received, + * it updates the status to upper layer + * @param [in] pdev device instance + * @param [in] dataBuffer data buffer contains the data to write + * @param [in] address address to which the data will be written + * @param [in] nbOfbytes NbOfbytes to be written + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint16_t nbOfPages; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10; + /*logical block address*/ + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]) ; + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]); + + /*HOST_MSC_PAGE_LENGTH = 512*/ + nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH); + + /*Tranfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief issue the read command to the device. Once the response received, + * it updates the status to upper layer + * @param [in] pdev device instance + * @param [in] dataBuffer data buffer will contain the data to be read + * @param [in] address Address from which the data will be read + * @param [in] nbOfbytes number of bytes to be read + * @retval status defined by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes) +{ + uint8_t index; + static USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint16_t nbOfPages; + status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10; + + /*logical block address*/ + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]); + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]); + /*HOST_MSC_PAGE_LENGTH = 512*/ + nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH); + /*Tranfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h new file mode 100644 index 0000000000..3ffeb3ee6b --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file usb_host_msc_scsi.h + * @brief Head file for usb_host_msc_scsi.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_SCSI_H__ +#define __USB_HOST_MSC_SCSI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* USBH_MSC_SCSI_Exported_Types */ +typedef enum { + USB_HOST_MSC_OK = 0U, + USB_HOST_MSC_FAIL, + USB_HOST_MSC_PHASE_ERROR, + USB_HOST_MSC_BUSY +} USB_HOST_MSC_STATUS; + +typedef struct { + uint32_t MSC_Capacity; + uint32_t MSC_Sense; + uint16_t MSC_PageLength; + uint8_t MSC_BulkOutEP; + uint8_t MSC_BulkInEP; + uint8_t MSC_WriteProtect; +} MSC_PARAMETER; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_HOST_MSC_CMD_SEND (1) +#define USB_HOST_MSC_CMD_WAIT (2) + +#define OPCODE_TEST_UNIT_READY (0x00U) +#define OPCODE_READ_CAPACITY10 (0x25U) +#define OPCODE_MODE_SENSE6 (0x1AU) +#define OPCODE_READ10 (0x28U) +#define OPCODE_WRITE10 (0x2AU) +#define OPCODE_REQUEST_SENSE (0x03U) + +#define DESC_REQUEST_SENSE (0x00U) +#define ALLOCATION_LENGTH_REQUEST_SENSE (63U) +#define XFER_LEN_READ_CAPACITY10 (8U) +#define XFER_LEN_MODE_SENSE6 (63U) + +#define MASK_MODE_SENSE_WRITE_PROTECT (0x80U) +#define MODE_SENSE_PAGE_CONTROL_FIELD (0x00U) +#define MODE_SENSE_PAGE_CODE (0x3FU) +#define DISK_WRITE_PROTECTED (0x01U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern MSC_PARAMETER USB_HOST_MSC_Param; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes); +extern USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_SCSI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c new file mode 100644 index 0000000000..3c4406566c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c @@ -0,0 +1,202 @@ +/** + ******************************************************************************* + * @file usb_host_cfgch.c + * @brief Functions for opening and closing host channels + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cfgch.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE LL USB Host Core + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint16_t usb_host_getfreech(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief configure and open a pipe + * @param [in] pdev device instance + * @param [in] hc_num host channel index + * @param [in] dev_address USB Device address allocated to attached device + * @param [in] speed core speed + * @param [in] ep_type communication type of the EP + * @param [in] mps max size of the packet + * @retval None + */ +void usb_host_chopen(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + pdev->host.hc[hc_num].ep_idx = (uint8_t) pdev->host.channel[hc_num] & 0x7Fu; + pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); + pdev->host.hc[hc_num].dev_addr = dev_address; + pdev->host.hc[hc_num].ep_type = ep_type; + pdev->host.hc[hc_num].max_packet = mps; + pdev->host.hc[hc_num].ch_speed = speed; + pdev->host.hc[hc_num].in_toggle = 0U; + pdev->host.hc[hc_num].out_toggle = 0U; + + (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief change a pipe on host + * @param [in] pdev device instance + * @param [in] hc_num host channel index + * @param [in] dev_address USB Device address allocated to attached device + * @param [in] speed core speed + * @param [in] ep_type communication type of EP + * @param [in] mps max size of packet + * @retval None + */ +void usb_host_mdfch(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + (void)(ep_type); + if (dev_address != 0U) { + pdev->host.hc[hc_num].dev_addr = dev_address; + } + if ((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0U)) { + pdev->host.hc[hc_num].max_packet = mps; + } + if ((pdev->host.hc[hc_num].ch_speed != speed) && (speed != 0U)) { + pdev->host.hc[hc_num].ch_speed = speed; + } + + (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief distribute a new channel for the pipe + * @param [in] pdev device instance + * @param [in] ep_addr EP index the channel distributed for + * @retval hc_num host channel index + */ +uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr) +{ + __IO uint16_t hc_num; + + hc_num = usb_host_getfreech(pdev); + if (hc_num != HC_ERROR) { + pdev->host.channel[hc_num & (USB_MAX_TX_FIFOS - 1U)] = HC_USED | ep_addr; + } + return (uint8_t)hc_num; +} + +/** + * @brief free the USB host channel assigned by idx + * @param [in] pdev device instance + * @param [in] idx Channel number to be freed + * @retval Status + */ +uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx) +{ + if (idx < MAX_CHNUM) { + pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] &= HC_USED_MASK; + } + return (uint8_t)HSTATUS_OK; +} + +/** + * @brief free all the USB host channels + * @param [in] pdev device instance + * @retval None + */ +void usb_host_dedistrallch(usb_core_instance *pdev) +{ + uint8_t idx; + + for (idx = 2U; idx < MAX_CHNUM ; idx ++) { + pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] = 0U; + } +} + +/** + * @brief Get a free channel number so that can be distributed to a device endpoint + * @param [in] pdev device instance + * @retval idx the free channel index + */ +uint16_t usb_host_getfreech(usb_core_instance *pdev) +{ + uint8_t tmp_idx; + uint16_t u16Ret = HC_ERROR; + + for (tmp_idx = 0U ; tmp_idx < MAX_CHNUM ; tmp_idx++) { + if ((pdev->host.channel[tmp_idx & (USB_MAX_TX_FIFOS - 1U)] & HC_USED) == 0U) { + u16Ret = HC_OK; + break; + } + } + + if (u16Ret == HC_OK) { + u16Ret = tmp_idx; + } else { + u16Ret = HC_ERROR; + } + + return u16Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h new file mode 100644 index 0000000000..0f641ef520 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h @@ -0,0 +1,103 @@ +/** + ******************************************************************************* + * @file usb_host_cfgch.h + * @brief header file for the usb_host_cfgch.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CFGCH_H__ +#define __USB_HOST_CFGCH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* USBH_HCS_Exported_Defines */ +#define MAX_CHNUM (12U) + +#define HC_OK (0x0000U) +#define HC_USED (0x8000U) +#define HC_ERROR (0xFFFFU) +#define HC_USED_MASK (0x7FFFU) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr); + +extern uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx); + +extern void usb_host_dedistrallch(usb_core_instance *pdev); + +extern void usb_host_chopen(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +extern void usb_host_mdfch(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CFGCH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c new file mode 100644 index 0000000000..ad2efc9581 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c @@ -0,0 +1,537 @@ +/** + ******************************************************************************* + * @file usb_host_core.c + * @brief The core state machine process the enumeration and the control transfer process + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_host_core.h" +#include "usb_host_cfgch.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_driver.h" +#include "usb_host_stdreq.h" +#include "usb_host_int.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint8_t Local_Buffer[ENUM_LOCAL_BUF]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialization for the host application + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] class_cbk the call back function for the class application + * @param [in] user_cbk the call back function for user + * @retval None + */ +void usb_host_init(usb_core_instance *pdev, + USBH_HOST *phost, + usb_host_class_callback_func *class_cbk, + usb_host_user_callback_func *user_cbk) +{ + usb_bsp_init(pdev); + usb_host_deinit(pdev, phost); + phost->class_callbk = class_cbk; + phost->user_callbk = user_cbk; + host_driver_init(pdev); + phost->user_callbk->huser_init(); + usb_bsp_nvicconfig(); +} + +/** + * @brief deinitialize the host application + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state = HOST_IDLE; + phost->host_state_backup = HOST_IDLE; + phost->enum_state = ENUM_IDLE; + phost->req_state = REQ_CMD_TX; + + phost->ctrlparam.ctrl_state = CTRL_SETUP; + phost->ctrlparam.ctrlmaxsize = USB_MAX_EP0_SIZE; + + phost->device_prop.devaddr = DEV_DEFAULT_ADDRESS; + phost->device_prop.devspeed = PRTSPD_FULL_SPEED; + + (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_in); + (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_out); +} + +/** + * @brief This is the main process function for the host core, it will process + * the main machine, such as connect,disconnect, emunation etc. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_mainprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + __IO HOST_STATUS tmp_status; + tmp_status = HSTATUS_FAIL; + HOST_HANDLE_STATE tmp_host_state; + + if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state != HOST_IDLE)) { + if (phost->host_state != HOST_DEV_DISCONNECTED) { + phost->host_state = HOST_DEV_DISCONNECTED; + } + } + + if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state == HOST_IDLE) + && (host_driver_getvbusdrivestate(pdev) == 0UL)) { + phost->host_state = HOST_DEV_DISCONNECTED; + } + + tmp_host_state = phost->host_state; + if (tmp_host_state == HOST_IDLE) { + if (0U != host_driver_ifdevconnected(pdev)) { + phost->host_state = HOST_DEV_CONNECTED; + usb_mdelay(50UL); + } + } else if (tmp_host_state == HOST_DEV_CONNECTED) { +#ifdef MSC_HID_COMPOSITE + if (host_driver_getcurrentspd(pdev) == 2) { + host_driver_init(pdev); + } +#endif /* MSC_HID_COMPOSITE */ + phost->user_callbk->huser_devattached(); + phost->ctrlparam.hc_num_out = usb_host_distrch(pdev, 0x00U); + phost->ctrlparam.hc_num_in = usb_host_distrch(pdev, 0x80U); + host_driver_portrst(pdev); + phost->user_callbk->huser_devreset(); + phost->device_prop.devspeed = (uint8_t)host_driver_getcurrentspd(pdev); + phost->host_state = HOST_ENUM; + phost->user_callbk->huser_devspddetected(phost->device_prop.devspeed); + usb_host_chopen(pdev, + phost->ctrlparam.hc_num_in, + phost->device_prop.devaddr, + phost->device_prop.devspeed, + EP_TYPE_CTRL, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + usb_host_chopen(pdev, + phost->ctrlparam.hc_num_out, + phost->device_prop.devaddr, + phost->device_prop.devspeed, + EP_TYPE_CTRL, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + } else if (tmp_host_state == HOST_ENUM) { + if (usb_host_enumprocess(pdev, phost) == HSTATUS_OK) { + phost->user_callbk->huser_enumcompl(); + phost->host_state = HOST_USER_INPUT; + } + } else if (tmp_host_state == HOST_USER_INPUT) { + if ((phost->class_callbk->host_class_init(pdev, phost)) == HSTATUS_OK) { + phost->host_state = HOST_CLASS_REQ; + } + } else if (tmp_host_state == HOST_CLASS_REQ) { + tmp_status = phost->class_callbk->host_class_request(pdev, phost); + if (tmp_status == HSTATUS_OK) { + phost->host_state = HOST_CLASS_PROCESS; + } else { + usb_host_errorprocess(phost, tmp_status); + } + } else if (tmp_host_state == HOST_CLASS_PROCESS) { + tmp_status = phost->class_callbk->host_class_process(pdev, phost); + usb_host_errorprocess(phost, tmp_status); + } else if (tmp_host_state == HOST_CTRL_TRANSMIT) { + (void)usb_host_ctrlprocess(pdev, phost); + } else if (tmp_host_state == HOST_ERROR_STATE) { + usb_host_deinit(pdev, phost); + phost->user_callbk->huser_deinit(); + phost->class_callbk->host_class_deinit(pdev); + } else if (tmp_host_state == HOST_DEV_DISCONNECTED) { + phost->user_callbk->huser_devdisconn(); + usb_host_deinit(pdev, phost); + phost->user_callbk->huser_deinit(); + phost->class_callbk->host_class_deinit(pdev); + usb_host_dedistrallch(pdev); + phost->host_state = HOST_IDLE; + + host_driver_init(pdev); + } else { + ; + } +} + +/** + * @brief process the status when related error status happens. + * @param [in] phost host state set + * @param [in] errType host status + * @retval None + */ +void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType) +{ + switch (errType) { + case HSTATUS_APP_DEINIT: + phost->host_state = HOST_ERROR_STATE; + phost->user_callbk->huser_init(); + break; + case HSTATUS_SPEED_UNKNOWN: + case HSTATUS_UNRECOVERED_ERROR: + phost->user_callbk->huser_unrecoverederror(); + phost->host_state = HOST_ERROR_STATE; + break; + default: + break; + } +} + +/** + * @brief this function process all the emunation steps. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status + */ +HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + HOST_STATUS tmp_status; + + ENUM_HANDLE_STATE tmp_enum_state; + tmp_status = HSTATUS_BUSY; + tmp_enum_state = phost->enum_state; + if (tmp_enum_state == ENUM_IDLE) { + if (usb_host_getdevdesc(pdev, phost, 8U) == HSTATUS_OK) { + phost->ctrlparam.ctrlmaxsize = phost->device_prop.devdesc.bMaxPacketSize0; + host_driver_portrst(pdev); + phost->enum_state = ENUM_GET_FULL_DEVDESC; + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_out, + 0U, + 0U, + 0U, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_in, + 0U, + 0U, + 0U, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + } + } + if (tmp_enum_state == ENUM_GET_FULL_DEVDESC) { + if (usb_host_getdevdesc(pdev, phost, USB_DEVICE_DESC_SIZE) == HSTATUS_OK) { + phost->user_callbk->huser_devdescavailable(&phost->device_prop.devdesc); + phost->enum_state = ENUM_SET_DEVADDR; + } + } + if (tmp_enum_state == ENUM_SET_DEVADDR) { + if (usb_host_setdevaddr(pdev, phost, DEV_ASSIGNED_ADDRESS) == HSTATUS_OK) { + usb_mdelay(2UL); + phost->device_prop.devaddr = DEV_ASSIGNED_ADDRESS; + phost->user_callbk->huser_devaddrdistributed(); + phost->enum_state = ENUM_GET_CFGDESC; + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_in, + phost->device_prop.devaddr, + 0U, + 0U, + 0U); + + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_out, + phost->device_prop.devaddr, + 0U, + 0U, + 0U); + } + } + if (tmp_enum_state == ENUM_GET_CFGDESC) { + if (usb_host_getcfgdesc(pdev, phost, USB_CONFIGURATION_DESC_SIZE) == HSTATUS_OK) { + phost->enum_state = ENUM_GET_FULL_CFGDESC; + } + } + if (tmp_enum_state == ENUM_GET_FULL_CFGDESC) { + if (usb_host_getcfgdesc(pdev, phost, phost->device_prop.devcfgdesc.wTotalLength) == HSTATUS_OK) { + phost->user_callbk->huser_cfgdescavailable(&phost->device_prop.devcfgdesc, + phost->device_prop.devitfdesc, + phost->device_prop.devepdesc[0]); + phost->enum_state = ENUM_GET_MFCSTRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_MFCSTRINGDESC) { + if (phost->device_prop.devdesc.iManufacturer != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iManufacturer, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_mfcstring(Local_Buffer); + phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC; + } + } else { + phost->user_callbk->huser_mfcstring("N/A"); + phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_PRODUCT_STRINGDESC) { + if (phost->device_prop.devdesc.iProduct != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iProduct, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_productstring(Local_Buffer); + phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC; + } + } else { + phost->user_callbk->huser_productstring("N/A"); + phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_SERIALNUM_STRINGDESC) { + if (phost->device_prop.devdesc.iSerialNumber != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iSerialNumber, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_serialnum(Local_Buffer); + phost->enum_state = ENUM_SET_CFG; + } + } else { + phost->user_callbk->huser_serialnum("N/A"); + phost->enum_state = ENUM_SET_CFG; + } + } + if (tmp_enum_state == ENUM_SET_CFG) { + if (usb_host_setconfig(pdev, phost, + (uint16_t)phost->device_prop.devcfgdesc.bConfigurationValue) == HSTATUS_OK) { + phost->enum_state = ENUM_DEV_CFG_OVER; + } + } + if (tmp_enum_state == ENUM_DEV_CFG_OVER) { + tmp_status = HSTATUS_OK; + } else { + ; + } + return tmp_status; +} + + +/** + * @brief process the state machine of control transfer + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status + */ +HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + uint8_t direction; + CTRL_HANDLE_STATE tmp_ctrl_state; + static uint16_t timeout = 0; + HOST_STATUS status = HSTATUS_OK; + HOST_CH_XFER_STATE URB_Status; + + phost->ctrlparam.ctrl_status = CTRL_START; + tmp_ctrl_state = phost->ctrlparam.ctrl_state; + + if (tmp_ctrl_state == CTRL_SETUP) { + /* transmit a setup packet to the device */ + usb_host_sendctrlsetup(pdev, phost->ctrlparam.setup.d8, phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_SETUP_WAIT; + timeout = DATA_STAGE_TIMEOUT * 6U; + phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev); + } else if (tmp_ctrl_state == CTRL_SETUP_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + /* case SETUP packet sent successfully */ + if (URB_Status == HOST_CH_XFER_DONE) { + /* parse the direction of the request from the setup just sent */ + direction = (phost->ctrlparam.setup.b.bmRequestType & USB_REQ_DIR_MASK); + /* judge if there is a data stage, if wLength is not zero, there may be a in or out + data stage */ + if (phost->ctrlparam.setup.b.wLength.w != 0U) { + timeout = DATA_STAGE_TIMEOUT; + if (direction == USB_D2H) { + /* Data Direction is IN, device should send data in */ + phost->ctrlparam.ctrl_state = CTRL_DATA_IN; + } else { + /* Data Direction is OUT, host will send data out for device */ + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT; + } + } + /* No DATA stage */ + else { + timeout = NODATA_STAGE_TIMEOUT; + /* If there is No Data Transfer Stage */ + if (direction == USB_D2H) { + /* Data Direction is IN */ + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + } else { + /* Data Direction is OUT */ + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN; + } + } + /* Set the delay timer to enable timeout for data stage completion */ + phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev); + } else if (URB_Status == HOST_CH_XFER_ERROR) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + phost->ctrlparam.ctrl_status = CTRL_XACTERR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { +#if (LL_PRINT_ENABLE == DDL_ON) + DDL_Printf("Device not responding\r\n"); +#endif + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_DATA_IN) { + /* Issue an IN token */ + usb_host_recvctrldata(pdev, phost->ctrlparam.buff, phost->ctrlparam.length, phost->ctrlparam.hc_num_in); + phost->ctrlparam.ctrl_state = CTRL_DATA_IN_WAIT; + } else if (tmp_ctrl_state == CTRL_DATA_IN_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in); + /* check is DATA packet transfered successfully */ + if (URB_Status == HOST_CH_XFER_DONE) { + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + } + /* manage error cases*/ + if (URB_Status == HOST_CH_XFER_STALL) { + /* In stall case, return to previous machine state*/ + phost->host_state = phost->host_state_backup; + } else if (URB_Status == HOST_CH_XFER_ERROR) { + /* Device error */ + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { + /* timeout for IN transfer */ + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_DATA_OUT) { + /* Start DATA out transfer (only one DATA packet)*/ + pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle = 1; + + usb_host_sendctrldata(pdev, + phost->ctrlparam.buff, + phost->ctrlparam.length, + phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT_WAIT; + } else if (tmp_ctrl_state == CTRL_DATA_OUT_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN; + break; + case HOST_CH_XFER_STALL: + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_STALLED; + break; + case HOST_CH_XFER_UNREADY: + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT; + break; + case HOST_CH_XFER_ERROR: + phost->ctrlparam.ctrl_state = CTRL_ERROR; + break; + default: + break; + } + } else if (tmp_ctrl_state == CTRL_STATUS_IN) { + /* receive a packet with 0 byte */ + usb_host_recvctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_in); + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN_WAIT; + } else if (tmp_ctrl_state == CTRL_STATUS_IN_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in); + if (URB_Status == HOST_CH_XFER_DONE) { + /* Control transfers completed, Exit the State Machine */ + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_COMPLETE; + } else if (URB_Status == HOST_CH_XFER_ERROR) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if (URB_Status == HOST_CH_XFER_STALL) { + /* Control transfers completed, Exit the State Machine */ + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_status = CTRL_STALL; + status = HSTATUS_UNSUPPORTED; + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_STATUS_OUT) { + pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle ^= 1U; + usb_host_sendctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT_WAIT; + } else if (tmp_ctrl_state == CTRL_STATUS_OUT_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_COMPLETE; + break; + case HOST_CH_XFER_UNREADY: + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + break; + case HOST_CH_XFER_ERROR: + phost->ctrlparam.ctrl_state = CTRL_ERROR; + break; + default: + break; + } + } else if (tmp_ctrl_state == CTRL_ERROR) { + if (++ phost->ctrlparam.err_cnt <= HOST_MAX_ERROR_CNT) { + /* re-start the transmission, starting from SETUP packet */ + phost->ctrlparam.ctrl_state = CTRL_SETUP; + } else { + phost->ctrlparam.ctrl_status = CTRL_FAIL; + phost->host_state = phost->host_state_backup; + + status = HSTATUS_FAIL; + } + } else { + ; + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h new file mode 100644 index 0000000000..1641d441b0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h @@ -0,0 +1,95 @@ +/** + ******************************************************************************* + * @file usb_host_core.h + * @brief header file for the usb_host_core.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CORE_H__ +#define __USB_HOST_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* USBH_CORE_Exported_Defines */ +#define MSC_CLASS (0x08U) +#define HID_CLASS (0x03U) +#define MSC_PROTOCOL (0x50U) +#define CBI_PROTOCOL (0x01U) + +#define DEV_DEFAULT_ADDRESS (0U) +#define DEV_ASSIGNED_ADDRESS (1U) + +#define HOST_MAX_ERROR_CNT (2U) + +#define ENUM_LOCAL_BUF (256U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_init(usb_core_instance *pdev, + USBH_HOST *phost, + usb_host_class_callback_func *class_cbk, + usb_host_user_callback_func *user_cbk); +extern void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost); +extern void usb_host_mainprocess(usb_core_instance *pdev, USBH_HOST *phost); +extern void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c new file mode 100644 index 0000000000..24411527a2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c @@ -0,0 +1,320 @@ +/** + ******************************************************************************* + * @file usb_host_ctrltrans.c + * @brief This file handles the issuing of the USB transactions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_ctrltrans.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Start a setup transfer by changing the state-machine and + * initializing the required variables needed for the Control Transfer + * @param [in] phost host state set + * @param [in] buff data buffer used for setup request + * @param [in] length data length in byte + * @retval status + */ +void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length) +{ + /* Save Global State */ + phost->host_state_backup = phost->host_state; + /* Prepare the Transactions */ + phost->host_state = HOST_CTRL_TRANSMIT; + phost->ctrlparam.buff = buff; + phost->ctrlparam.length = length; + phost->ctrlparam.ctrl_state = CTRL_SETUP; +} + +/** + * @brief send a control request and update the status after the request sent. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] buff data buffer whose data will be sent in the control pipe. + * @param [in] length length of the data sent. + * @retval status + */ +HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t *buff, + uint16_t length) +{ + HOST_STATUS status; + REQ_HANDLE_STATE tmp_req_state; + (void)(pdev); + status = HSTATUS_BUSY; + tmp_req_state = phost->req_state; + if (tmp_req_state == REQ_CMD_TX) { + /* prepare a setup packet for transferring */ + usb_host_submitsetupreq(phost, buff, length); + /* update the request state */ + phost->req_state = REQ_CMD_WAIT; + /* The status would be returned in this function */ + status = HSTATUS_BUSY; + } else if (tmp_req_state == REQ_CMD_WAIT) { + switch (phost->ctrlparam.ctrl_state) { + case CTRL_COMPLETE: + /* Commands have been successfully sent and Responses have been Received */ + phost->req_state = REQ_CMD_TX; + /* update the control state */ + phost->ctrlparam.ctrl_state = CTRL_IDLE; + status = HSTATUS_OK; + break; + case CTRL_ERROR: + /* fail transfer */ + phost->req_state = REQ_CMD_TX; + status = HSTATUS_FAIL; + break; + case CTRL_STALLED: + /* Commands have been successfully sent and Responses have been Received */ + phost->req_state = REQ_CMD_TX; + status = HSTATUS_UNSUPPORTED; + break; + default: + break; + } + } else { + ; + } + return status; +} + +/** + * @brief sends a setup packet to the control EP of the USB device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent in the control pipe to the control EP of the device. + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0U; + pdev->host.hc[hc_num].pid_type = PID_SETUP; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = 8; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief sends a data packet to the USB device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent to the USB device + * @param [in] length the data length in byte that would be sent + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + if (length == 0U) { + /* For Status OUT stage, Length==0, Status Out PID = 1 always */ + pdev->host.hc[hc_num].out_toggle = 1; + } + /* Set the Data Toggle bit */ + if (pdev->host.hc[hc_num].out_toggle == 0U) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1 ; + } + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief Receives the response data to the setup packet + * @param [in] pdev device instance + * @param [in] buff data buffer when received data. + * @param [in] length the length data in byte have received. + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].pid_type = PID_DATA1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief sent the bulk packet to the device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + /* Set the Data Toggle bit */ + if (pdev->host.hc[hc_num].out_toggle == 0U) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1 ; + } + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives bulk packet from device + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval status + */ +void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives the device response to the Interrupt IN token + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + /* toggle the DATA PID */ + pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief send the data on Interrupt OUT Endpoint + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + + pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives the Device Response to the Isochronous IN token + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + pdev->host.hc[hc_num].pid_type = PID_DATA0; + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief Sends the data through Isochronous OUT Endpoint + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + pdev->host.hc[hc_num].pid_type = PID_DATA0; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h new file mode 100644 index 0000000000..f3d8525c53 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h @@ -0,0 +1,86 @@ +/** + ******************************************************************************* + * @file usb_host_ctrltrans.h + * @brief header file for the usb_host_ctrltrans.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CTRLTRANS_H__ +#define __USB_HOST_CTRLTRANS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num); +extern void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length); +extern void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num); +extern void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CTRLTRANS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h new file mode 100644 index 0000000000..c4df0492a0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h @@ -0,0 +1,430 @@ +/** + ******************************************************************************* + * @file usb_host_def.h + * @brief Definitions used in the USB host library + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_DEF_H__ +#define __USB_HOST_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_app_conf.h" +#include "usb_lib.h" +#include "hc32_ll.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* This Union is copied from usb_core.h */ +typedef union { + uint16_t w; + struct BW { + uint8_t msb; + uint8_t lsb; + } + bw; +} uint16_t_uint8_t; +/* standard setup packet defination */ +typedef union { + uint8_t d8[8]; + struct _SetupPkt_Struc { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t_uint8_t wValue; + uint16_t_uint8_t wIndex; + uint16_t_uint8_t wLength; + } b; +} usb_setup_typedef; + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; +} USB_HOST_DescHeader_TypeDef; + +/* Standard Device Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* Device descriptor type */ + uint16_t bcdUSB; /* USB Specification Release Numbrer in Binary-Coded Decimal(i.e.,2.10 is 210H) */ + uint8_t bDeviceClass; /* Class code(assigned by the USB-IF) */ + uint8_t bDeviceSubClass; /* Subclass code(assigned by the USB-IF) this code is qualified by the value of the \ + bDeviceClass field. */ + uint8_t bDeviceProtocol; /* Protocol code(assigned by the USB-IF), this code is qualified by the value of the \ + bDeviceClass and the bDeviceSubClass fields. */ + uint8_t bMaxPacketSize0; /* Maximum packet size for EP0 */ + uint16_t idVendor; /* Vendor ID (assigned by the USB-IF) */ + uint16_t idProduct; /* Product ID (assigned by manufacturer) */ + uint16_t bcdDevice; /* Device Release Number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device's serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_host_devdesc_typedef; + +/* Standard Configuration Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CONFIGURATION descriptor type */ + uint16_t wTotalLength; /* Total length of data returned for this configuration */ + uint8_t bNumInterfaces; /* Number of interfaces supported by this configuration */ + uint8_t bConfigurationValue; /* Value to use as an argument to the SetConfiguration() request to select this configuration */ + uint8_t iConfiguration; /* Index of string descriptor describing this configuration */ + uint8_t bmAttributes; /* Configuration characteristics: D7:Reserved(set to one) D6:Self-powered D5:Remote Wakeup D4..0 Reserved(set to zero) */ + uint8_t bMaxPower; /* Maximum power consumption of the device from the bus in this specific configuration when the device is fully operational */ +} usb_host_cfgdesc_typedef; + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */ + uint8_t bCountryCode; /* specifies the transfer type. */ + uint8_t bNumDescriptors; /* specifies the transfer type. */ + uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */ + uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */ +} USB_HOST_HIDDesc_TypeDef; + +/* Standard Interface Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* INTERFACE Descriptor Type */ + uint8_t bInterfaceNumber; /* Number of this interface */ + uint8_t bAlternateSetting; /* Value used to select this alternate setting for the interface identifiled in the \ + prior field */ + uint8_t bNumEndpoints; /* Number of Endpoints used by this interface */ + uint8_t bInterfaceClass; /* Class code (assigned by the USB-IF) */ + uint8_t bInterfaceSubClass; /* Subclass code (assigned by the USB-IF) */ + uint8_t bInterfaceProtocol; /* Protocol code (assigned by the USB) */ + uint8_t iInterface; /* Index of string descriptor describing this interface */ +} usb_host_itfdesc_typedef; + +/* Standard Endpoint Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type */ + uint8_t bEndpointAddress; /* The address of the endpoint on the device described by this descriptor */ + uint8_t bmAttributes; /* refer to the related standard of USB 2.0 */ + uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving when this \ + configuration is selected */ + uint8_t bInterval; /* Interval for servicing the endpoint for data transfers */ +} USB_HOST_EPDesc_TypeDef; + +/* USBH_CORE_Exported_Types */ +/* Host status */ +typedef enum { + HSTATUS_OK = 0, + HSTATUS_BUSY, + HSTATUS_FAIL, + HSTATUS_UNSUPPORTED, + HSTATUS_UNRECOVERED_ERROR, + HSTATUS_SPEED_UNKNOWN, + HSTATUS_APP_DEINIT +} HOST_STATUS; + +/* states about the handle stages on the host side */ +typedef enum { + HOST_IDLE = 0, + HOST_DEV_CONNECTED, + HOST_DEV_DISCONNECTED, + HOST_GET_DEVSPEED, + HOST_ENUM, + HOST_CLASS_REQ, + HOST_CLASS_PROCESS, + HOST_CTRL_TRANSMIT, + HOST_USER_INPUT, + HOST_SUSPENDED, + HOST_ERROR_STATE +} HOST_HANDLE_STATE; + + +/* states of the enumeration stage on the host side */ +typedef enum { + ENUM_IDLE = 0, + ENUM_GET_FULL_DEVDESC, + ENUM_SET_DEVADDR, + ENUM_GET_CFGDESC, + ENUM_GET_FULL_CFGDESC, + ENUM_GET_MFCSTRINGDESC, + ENUM_GET_PRODUCT_STRINGDESC, + ENUM_GET_SERIALNUM_STRINGDESC, + ENUM_SET_CFG, + ENUM_DEV_CFG_OVER +} ENUM_HANDLE_STATE; + +/* states of the control stages on the host side */ +typedef enum { + CTRL_IDLE = 0, + CTRL_SETUP, + CTRL_SETUP_WAIT, + CTRL_DATA_IN, + CTRL_DATA_IN_WAIT, + CTRL_DATA_OUT, + CTRL_DATA_OUT_WAIT, + CTRL_STATUS_IN, + CTRL_STATUS_IN_WAIT, + CTRL_STATUS_OUT, + CTRL_STATUS_OUT_WAIT, + CTRL_ERROR, + CTRL_STALLED, + CTRL_COMPLETE +} CTRL_HANDLE_STATE; + +/* Following states are state machine for the request transferring */ +typedef enum { + REQ_CMD_IDLE = 0, + REQ_CMD_TX, + REQ_CMD_WAIT +} REQ_HANDLE_STATE; + +typedef enum { + USER_HAVE_RESP = 0, + USER_NONE_RESP +} HOST_USER_STATUS; + +typedef struct { + uint8_t hc_num_in; /* channel number for the IN EP */ + uint8_t hc_num_out; /* channel number for the OUT EP */ + uint8_t ctrlmaxsize; /* the max size of EP0 parsed from the device descriptor */ + uint8_t err_cnt; /* the error counter */ + uint16_t sof_num; /* the frame number for sof packet */ + uint16_t length; /* length of data in byte */ + uint8_t *buff; /* data buffer */ + CTRL_HANDLE_STATUS ctrl_status; /* status of control pipe */ + CTRL_HANDLE_STATE ctrl_state; /* running state of the control transfer */ + usb_setup_typedef setup; /* setup packet */ +} usb_host_ctrl_param; + +/* Device information parsed from the related descriptors requested from the connected device + the following data are all parsed from the data sent by the connnected device */ +typedef struct { + uint8_t devaddr; /* the address of the connected device */ + uint8_t devspeed; /* the core speed of the connected device */ + usb_host_devdesc_typedef devdesc; /* the device descriptor parsed from the data sent by device */ + usb_host_cfgdesc_typedef devcfgdesc; /* the device configuration descriptor parsed from the data sent by device */ + usb_host_itfdesc_typedef devitfdesc[USBH_MAX_NUM_INTERFACES]; /* the interface descritpor */ + USB_HOST_EPDesc_TypeDef devepdesc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; /* the endpoint descriptor */ + USB_HOST_HIDDesc_TypeDef hiddesc; /* the hid descriptor */ +} usb_host_devinformation; + +typedef struct { + HOST_STATUS(*host_class_init)(usb_core_instance *pdev, void *phost); + void (*host_class_deinit)(usb_core_instance *pdev); + HOST_STATUS(*host_class_request)(usb_core_instance *pdev, void *phost); + HOST_STATUS(*host_class_process)(usb_core_instance *pdev, void *phost); +} usb_host_class_callback_func; + +typedef struct { + void (*huser_init)(void); + void (*huser_deinit)(void); + void (*huser_devattached)(void); + void (*huser_devreset)(void); + void (*huser_devdisconn)(void); + void (*huser_overcurrent)(void); + void (*huser_devspddetected)(uint8_t DeviceSpeed); + void (*huser_devdescavailable)(void *); + void (*huser_devaddrdistributed)(void); + void (*huser_cfgdescavailable)(usb_host_cfgdesc_typedef *, + usb_host_itfdesc_typedef *, + USB_HOST_EPDesc_TypeDef *); + /* Configuration Descriptor available */ + void (*huser_mfcstring)(void *); + void (*huser_productstring)(void *); + void (*huser_serialnum)(void *); + void (*huser_enumcompl)(void); + HOST_USER_STATUS(*huser_userinput)(void); + int (*huser_application)(void); + void (*huser_devunsupported)(void); + void (*huser_unrecoverederror)(void); +} usb_host_user_callback_func; + +typedef struct { + /* states for the host, enumeration, request */ + REQ_HANDLE_STATE req_state; /* value of state machine about the request */ + ENUM_HANDLE_STATE enum_state; /* state machine while enumerating */ + HOST_HANDLE_STATE host_state_backup; /* backup value of state machine about the host */ + HOST_HANDLE_STATE host_state; /* value of state machine about the host */ + /* control informations */ + usb_host_ctrl_param ctrlparam; /* values about the control parameters */ + /* device information parsed from the descriptors from the device */ + usb_host_devinformation device_prop; + /* functions: call back functions for the class and user */ + usb_host_class_callback_func *class_callbk; + usb_host_user_callback_func *user_callbk; +} USBH_HOST; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef TRUE +#define TRUE 1U +#endif + +/* Get a 16bits data from buffer in little end mode. */ +#define SMALL_END(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define USB_LEN_CFG_DESC (0x09U) + +/* bmRequestType +D7: Data transfer direction + 0 = Host-to-device + 1 = Device-to-host +*/ +#define USB_REQ_DIR_MASK (0x80U) +#define USB_H2D (0x00U) +#define USB_D2H (0x80U) + +/* bmRequestType +D6...5: Type + 0 = Standard + 1 = Class + 2 = Vendor + 3 = Reserved +*/ +#define USB_REQ_TYPE_STANDARD (0x00U) +#define USB_REQ_TYPE_CLASS (0x20U) +#define USB_REQ_TYPE_VENDOR (0x40U) +#define USB_REQ_TYPE_RESERVED (0x60U) + +/* bmRequestType +D4...0: Recipient + 0 = Device + 1 = Interface + 2 = Endpoint + 3 = Other + 4...31 = Reserved +*/ +#define USB_REQ_RECIPIENT_DEVICE (0x00U) +#define USB_REQ_RECIPIENT_INTERFACE (0x01U) +#define USB_REQ_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQ_RECIPIENT_OTHER (0x03U) + +/* Table 9-4. Standard Request Codes [USB Specification] */ +/* bRequest Value */ +#define USB_REQ_GET_STATUS (0x00U) +#define USB_REQ_CLEAR_FEATURE (0x01U) +#define USB_REQ_SET_FEATURE (0x03U) +#define USB_REQ_SET_ADDRESS (0x05U) +#define USB_REQ_GET_DESCRIPTOR (0x06U) +#define USB_REQ_SET_DESCRIPTOR (0x07U) +#define USB_REQ_GET_CONFIGURATION (0x08U) +#define USB_REQ_SET_CONFIGURATION (0x09U) +#define USB_REQ_GET_INTERFACE (0x0AU) +#define USB_REQ_SET_INTERFACE (0x0BU) +#define USB_REQ_SYNCH_FRAME (0x0Cu) + +/* Table 9-5. Descriptor Types [USB Specification] */ +/* Descriptor Types Value */ +#define USB_DESC_TYPE_DEVICE (1U) +#define USB_DESC_TYPE_CONFIGURATION (2U) +#define USB_DESC_TYPE_STRING (3U) +#define USB_DESC_TYPE_INTERFACE (4U) +#define USB_DESC_TYPE_ENDPOINT (5U) +#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U) +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U) +#define USB_DESC_TYPE_INTERFACE_POWER (8U) +#define USB_DESC_TYPE_HID (0x21U) +#define USB_DESC_TYPE_HID_REPORT (0x22U) + +#define USB_DEVICE_DESC_SIZE (18U) +#define USB_CONFIGURATION_DESC_SIZE (9U) +#define USB_HID_DESC_SIZE (9U) +#define USB_INTERFACE_DESC_SIZE (9U) +#define USB_ENDPOINT_DESC_SIZE (7U) + +/* Descriptor Type and Descriptor Index */ +/* Use the following values when calling the function usb_host_getdesc */ +#define USB_DESC_DEVICE (((uint16_t)USB_DESC_TYPE_DEVICE << 8U) & 0xFF00U) +#define USB_DESC_CONFIGURATION (((uint16_t)USB_DESC_TYPE_CONFIGURATION << 8U) & 0xFF00U) +#define USB_DESC_STRING (((uint16_t)USB_DESC_TYPE_STRING << 8U) & 0xFF00U) +#define USB_DESC_INTERFACE (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U) +#define USB_DESC_ENDPOINT (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U) +#define USB_DESC_DEVICE_QUALIFIER (((uint16_t)USB_DESC_TYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) +#define USB_DESC_OTHER_SPEED_CONFIGURATION (((uint16_t)USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) +#define USB_DESC_INTERFACE_POWER (((uint16_t)USB_DESC_TYPE_INTERFACE_POWER << 8U) & 0xFF00U) +#define USB_DESC_HID_REPORT (((uint16_t)USB_DESC_TYPE_HID_REPORT << 8U) & 0xFF00U) +#define USB_DESC_HID (((uint16_t)USB_DESC_TYPE_HID << 8U) & 0xFF00U) + +#define USB_EP_DIR_OUT (0x00U) +#define USB_EP_DIR_IN (0x80U) +#define USB_EP_DIR_MSK (0x80U) + +/* supported classes */ +#define USB_MSC_CLASS (0x08U) +#define USB_HID_CLASS (0x03U) + +/* Interface Descriptor field values for HID Boot Protocol */ +#define HID_BOOT_CODE (0x01U) +#define HID_KEYBRD_BOOT_CODE (0x01U) +#define HID_MOUSE_BOOT_CODE (0x02U) + +/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec + Standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT (5000U) +#define NODATA_STAGE_TIMEOUT (50U) + +/* Macro definations for host mode */ +#define PID_DATA0 (0U) +#define PID_DATA2 (1U) +#define PID_DATA1 (2U) +#define PID_SETUP (3U) +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_DEF_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c new file mode 100644 index 0000000000..6ebc74afe7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c @@ -0,0 +1,231 @@ +/** + ******************************************************************************* + * @file usb_host_driver.c + * @brief Host Interface Layer. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_driver.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Initialize the driver for the host mode + * @param [in] pdev device instance + * @retval None + */ +void host_driver_init(usb_core_instance *pdev) +{ + uint8_t i; + + pdev->host.is_dev_connect = 0U; + for (i = 0U; i < USB_MAX_TX_FIFOS; i++) { + pdev->host.ErrCnt[i] = 0U; + pdev->host.XferCnt[i] = 0U; + pdev->host.HC_Status[i] = HOST_CH_IDLE; + } + pdev->host.hc[0].max_packet = 8U; + + usb_setregaddr(&pdev->regs, &pdev->basic_cfgs);; + + usb_gintdis(&pdev->regs); + usb_initusbcore(&pdev->regs, &pdev->basic_cfgs); + /* force to work in host mode*/ + usb_modeset(&pdev->regs, HOST_MODE); + /* configure charge pump IO */ + usb_bsp_cfgvbus(&pdev->regs); + usb_vbusctrl(&pdev->regs, 1U); + usb_mdelay(50UL); + + usb_hostmodeinit(&pdev->regs, &pdev->basic_cfgs); + usb_ginten(&pdev->regs); +} + +/** + * @brief get current speed when in host mode + * @param [in] pdev device instance + * @retval current speed + */ +uint32_t host_driver_getcurrentspd(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS); +} + +/** + * @brief get current DM DP state + * @param [in] pdev device instance + * @retval DM DP state + * 0x00 DM L, DP L + * 0x01 DM L, DP H + * 0x02 DM H, DP L + * 0x03 DM H, DP H + */ +uint32_t host_driver_getdmdpstate(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PLSTS) >> USBFS_HPRT_PLSTS_POS); +} + +/** + * @brief get vbus drive state + * @param [in] pdev device instance + * @retval vbus driver state + * 0x00 vbus driver disable + * 0x01 vbus driver enable + */ +uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PWPR) >> USBFS_HPRT_PWPR_POS); +} + +/** + * @brief reset the port + * @param [in] pdev device instance + * @retval None + */ +void host_driver_portrst(usb_core_instance *pdev) +{ + usb_hprtrst(&pdev->regs); +} + +/** + * @brief get the connected status of the device + * @param [in] pdev device instance + * @retval 1 connected or 0 disconnected + */ +uint32_t host_driver_ifdevconnected(usb_core_instance *pdev) +{ + return (pdev->host.is_dev_connect); +} + +/** + * @brief gets the frame number for of sof packet + * @param [in] pdev device instance + * @retval number of frame + */ +uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev) +{ + return (READ_REG32(pdev->regs.HREGS->HFNUM) & 0xFFFFUL) ; +} + +/** + * @brief gets the last xfer state + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval HOST_CH_XFER_STATE + */ +HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.URB_State[ch_num] ; +} + +/** + * @brief gets the xfer count + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval number of data trandmitted in bytes + */ +uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.XferCnt[ch_num] ; +} + +/** + * @brief gets the host channel status + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval HOST_CH_STATUS + */ +HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.HC_Status[ch_num] ; +} + +/** + * @brief prepare a host channel and start a transfer + * @param [in] pdev device instance + * @param [in] hc_num channel number + * @retval status + */ +uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num) +{ + return usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief prepare a host channel and start a transfer + * @param [in] pdev device instance + * @param [in] hc_num channel number + * @retval status + */ +uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num) +{ + pdev->host.URB_State[hc_num] = HOST_CH_XFER_IDLE; + pdev->host.hc[hc_num].xfer_count = 0U ; + return usb_hchtransbegin(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h new file mode 100644 index 0000000000..31bff9112c --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h @@ -0,0 +1,90 @@ +/** + ******************************************************************************* + * @file usb_host_driver.h + * @brief Head file for usb_host_driver.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_DRIVER_H__ +#define __USB_HOST_DRIVER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void host_driver_init(usb_core_instance *pdev); +extern uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num); +extern uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num); +extern uint32_t host_driver_getcurrentspd(usb_core_instance *pdev); +extern uint32_t host_driver_getdmdpstate(usb_core_instance *pdev); +extern uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev); +extern void host_driver_portrst(usb_core_instance *pdev); +extern uint32_t host_driver_ifdevconnected(usb_core_instance *pdev); +extern uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev); +extern HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num); +extern uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num); +extern HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_DRIVER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c new file mode 100644 index 0000000000..a547fefce9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c @@ -0,0 +1,575 @@ +/** + ******************************************************************************* + * @file usb_host_int.c + * @brief Host driver interrupt subroutines. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_int.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_host_hc_isr(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief processes interrupt for a specific host channel which is used for OUT EP + * @param [in] pdev device instance + * @param [in] chnum channel index + * @retval None + */ +static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) +{ + uint32_t u32hcchar; + uint32_t u32hcint; + uint32_t u32hcintmsk; + + u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR); + u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT); + u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK); + u32hcint = u32hcint & u32hcintmsk; + + if (0UL != (u32hcint & USBFS_HCINT_ACK)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); + } +#if defined (HC32F4A0) + else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); + usb_host_int_unmskchhltd(pdev, chnum); + } +#endif + else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR); + } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC); + pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL; + } else if (0UL != (u32hcint & USBFS_HCINT_STALL)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL); + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + pdev->host.HC_Status[chnum] = HOST_CH_STALL; + } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_NAK; + } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + pdev->host.ErrCnt[chnum] ++; + pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); + } else if (0UL != (u32hcint & HCINT_NYET)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, HCINT_NYET); + pdev->host.HC_Status[chnum] = HOST_CH_NYET; + } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR); + } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) { + usb_host_int_mskchhltd(pdev, chnum); + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + + if (((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS) == EP_TYPE_BULK) { + pdev->host.hc[chnum].out_toggle ^= 1U; + } + } else if (pdev->host.HC_Status[chnum] == HOST_CH_NAK) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_NYET) { + if (pdev->host.hc[chnum].do_ping == 1U) { + usb_pingtokenissue(&pdev->regs, chnum); + } + pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) { + if (pdev->host.ErrCnt[chnum] == 3UL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + pdev->host.ErrCnt[chnum] = 0UL; + } + } else { + ; + } + usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH); + } else { + ; + } +} + +/** + * @brief processes interrupt for a specific host Channel which is used for IN EP + * @param [in] pdev device instance + * @param [in] chnum channel index + * @retval None + */ +static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) +{ + uint32_t u32hcchar; + uint32_t u32hctsiz; + uint32_t u32eptypetmp; + uint32_t u32hcint; + uint32_t u32hcintmsk; + + u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR); + u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT); + u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK); + u32hcint = u32hcint & u32hcintmsk; + + u32eptypetmp = (u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS; + if (0UL != (u32hcint & USBFS_HCINT_ACK)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); + } +#if defined (HC32F4A0) + else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); + usb_host_int_unmskchhltd(pdev, chnum); + } +#endif + else if (0UL != (u32hcint & USBFS_HCINT_STALL)) { + usb_host_int_unmskchhltd(pdev, chnum); + pdev->host.HC_Status[chnum] = HOST_CH_STALL; + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL); + usb_hchstop(&pdev->regs, chnum); + } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR); + } else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR); + } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) { + if (pdev->basic_cfgs.dmaen == 1U) { + u32hctsiz = READ_REG32(pdev->regs.HC_REGS[chnum]->HCTSIZ); + pdev->host.XferCnt[chnum] = pdev->host.hc[chnum].xfer_len - (u32hctsiz & USBFS_HCTSIZ_XFRSIZ); + } + pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL; + pdev->host.ErrCnt [chnum] = 0U; + usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC); + switch (u32eptypetmp) { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.hc[chnum].in_toggle ^= (uint8_t)1; + break; + case EP_TYPE_INTR: + u32hcchar |= USBFS_HCCHAR_ODDFRM; + WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar); + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + break; + case EP_TYPE_ISOC: + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + } + break; + default: + break; + } + } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) { + usb_host_int_mskchhltd(pdev, chnum); + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) { + pdev->host.ErrCnt[chnum] = 0U; + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_DATATGLERR) { + pdev->host.ErrCnt[chnum] = 0U; + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + } else if (u32eptypetmp == EP_TYPE_INTR) { + pdev->host.hc[chnum].in_toggle ^= (uint8_t)1; + } else { + ; + } + usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH); + } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + pdev->host.ErrCnt[chnum] ++; + pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); + } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) { + if (u32eptypetmp == EP_TYPE_INTR) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + } else if ((u32eptypetmp == EP_TYPE_CTRL) || (u32eptypetmp == EP_TYPE_BULK)) { + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar); + } else { + ; + } + pdev->host.HC_Status[chnum] = HOST_CH_NAK; + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + } else { + ; + } +} + +/** + * @brief this function processes the channel interrupt + * @param [in] pdev device instance + * @retval None + */ +void usb_host_hc_isr(usb_core_instance *pdev) +{ + uint32_t u32hcchar; + uint8_t u8Cnt; + uint32_t u32haint; + + u32haint = READ_REG32(pdev->regs.HREGS->HAINT); + for (u8Cnt = 0U; u8Cnt < pdev->basic_cfgs.host_chnum; u8Cnt++) { + if (0UL != (u32haint & (1UL << u8Cnt))) { + u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8Cnt]->HCCHAR); + if (0UL != ((u32hcchar & USBFS_HCCHAR_EPDIR) >> USBFS_HCCHAR_EPDIR_POS)) { + usb_host_chx_in_isr(pdev, u8Cnt); + } else { + usb_host_chx_out_isr(pdev, u8Cnt); + } + } + } +} + +/** + * @brief process the start-of-frame interrupt in host mode. + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_sof_isr(usb_core_instance *pdev) +{ + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF); +} + +/** + * @brief processes disconnect interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_disconn_isr(usb_core_instance *pdev) +{ + usb_gintdis(&pdev->regs); + usb_vbusctrl(&pdev->regs, 0U); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_DISCINT); + + pdev->host.is_dev_connect = 0U; +} + +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS (27U) +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM (0x78000000UL) +/** + * @brief processes non-periodic txFIFO empty interrupt. + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_nptxfifoempty_isr(usb_core_instance *pdev) +{ + uint32_t u32hnptxsts; + uint16_t u16LenWord; + uint16_t u16Len; + uint8_t u8ChNum; + + u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS); + u8ChNum = (uint8_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM) >> USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS); + + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + while (((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) { + u16Len = (uint16_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) * 4UL); + if (u16Len > pdev->host.hc[u8ChNum].xfer_len) { + u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len; + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_NPTXFE); + } + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen); + pdev->host.hc[u8ChNum].xfer_buff += u16Len; + pdev->host.hc[u8ChNum].xfer_len -= u16Len; + pdev->host.hc[u8ChNum].xfer_count += u16Len; + u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS); + } +} +#define USBFS_HPTXSTS_PTXQTOP_CHNUM_POS (27U) +#define USBFS_HPTXSTS_PTXQTOP_CHNUM (0x78000000UL) +/** + * @brief processes periodic txFIFO empty interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_ptxfifoempty_isr(usb_core_instance *pdev) +{ + uint32_t u32hptxsts; + uint16_t u16LenWord; + uint16_t u16Len; + uint8_t u8ChNum; + + u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS); + u8ChNum = (uint8_t)((u32hptxsts & USBFS_HPTXSTS_PTXQTOP_CHNUM) >> USBFS_HPTXSTS_PTXQTOP_CHNUM_POS); + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + while ((((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL)) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) { + u16Len = (uint16_t)((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) * 4UL); + if (u16Len > pdev->host.hc[u8ChNum].xfer_len) { + u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len; + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM); + } + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen); + pdev->host.hc[u8ChNum].xfer_buff += u16Len; + pdev->host.hc[u8ChNum].xfer_len -= u16Len; + pdev->host.hc[u8ChNum].xfer_count += u16Len; + u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS); + } +} + +/** + * @brief This function determines which interrupt conditions have occurred + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_port_isr(usb_core_instance *pdev) +{ + uint32_t u32hprt; + uint32_t u32hprt_bk; + uint8_t u8fslspclksel; + uint32_t do_reset = 0UL; + uint8_t u8PortSpeed; + + u32hprt = READ_REG32(*pdev->regs.HPRT); + u32hprt_bk = u32hprt; + /* Clear the interrupt bits in GINTSTS */ + //tmp_hprt_bk.b.prtovrcurrchng = 0U; //todo don't have this bit + u32hprt_bk &= ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG); + + /* check if a port connect have been detected */ + if ((u32hprt & USBFS_HPRT_PCDET) != 0UL) { + u32hprt_bk |= USBFS_HPRT_PCDET; + if (host_driver_getvbusdrivestate(pdev) != 0UL) { + pdev->host.is_dev_connect = 1U; + } + } + /* check if port enable or disable change */ + if ((u32hprt & USBFS_HPRT_PENCHNG) != 0UL) { + u32hprt_bk |= USBFS_HPRT_PENCHNG; + + if ((u32hprt & USBFS_HPRT_PENA) != 0UL) { + u8PortSpeed = (uint8_t)((u32hprt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS); + if ((u8PortSpeed == PRTSPD_LOW_SPEED) || (u8PortSpeed == PRTSPD_FULL_SPEED)) { + u8fslspclksel = (uint8_t)(READ_REG32(pdev->regs.HREGS->HCFG) & USBFS_HCFG_FSLSPCS); + if (u8PortSpeed == PRTSPD_LOW_SPEED) { + if (u8fslspclksel != HCFG_6_MHZ) { + do_reset = 1U; + } + } else { + /* 1ms*(PHY clock frequency for FS/LS)-1 */ + WRITE_REG32(pdev->regs.HREGS->HFIR, 48000UL); + if (u8fslspclksel != HCFG_48_MHZ) { + usb_fslspclkselset(&pdev->regs, HCFG_48_MHZ); + do_reset = 1U; + } + } + } else { + do_reset = 1U; + } + } + } + + //todo don't have this bit + //if ((u32hprt & USBFS_HPRT_PRTOVRCURRCHNG) != 0UL) { + // u32hprt_bk |= USBFS_HPRT_PRTOVRCURRCHNG; + //} + + if (0UL != do_reset) { + usb_hprtrst(&pdev->regs); + } + WRITE_REG32(*pdev->regs.HPRT, u32hprt_bk); +} + +/** + * @brief processes the rxFIFO non-empty interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_rxflvl_isr(usb_core_instance *pdev) +{ + uint32_t u32grxsts; + uint32_t u32hctsiz; + uint32_t u32hcchar; + uint8_t u8chnum; + uint8_t *pu8Tmp; + uint16_t u16bcnt; + + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE); + + u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); + u8chnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM); + u16bcnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS); + u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR); + + switch ((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS) { + case 2: /* IN dat packet received */ + pu8Tmp = pdev->host.hc[u8chnum].xfer_buff; + if ((u16bcnt > 0U) && (pu8Tmp != (void *)0U)) { + usb_rdpkt(&pdev->regs, pdev->host.hc[u8chnum].xfer_buff, u16bcnt); + pdev->host.hc[u8chnum].xfer_buff += u16bcnt; + pdev->host.hc[u8chnum].xfer_count += u16bcnt; + pdev->host.XferCnt[u8chnum] = pdev->host.hc[u8chnum].xfer_count; + + u32hctsiz = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCTSIZ); + if (((u32hctsiz & USBFS_HCTSIZ_PKTCNT) >> USBFS_HCTSIZ_PKTCNT_POS) > 0U) { + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR, u32hcchar); + } + } + break; + + case 3: /* IN transfer completed(trigger an interrupt) */ + break; + case 5: /* Daat toggle error(trigger an interrupt) */ + break; + case 7: /* Channel halted(trigger an interrupt) */ + break; + default: + break; + } + + SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE); +} + +/** + * @brief process the incomplete periodic transfer interrupt(incompIP) + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_incomplisoout_isr(usb_core_instance *pdev) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[0]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT); +} + +/** + * @brief process the resume/remote wakeup detected interrupt(WkUpInt) + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_wkupint_isr(usb_core_instance *pdev) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(&pdev->regs); + u32hprt &= ~USBFS_HPRT_PRES; + WRITE_REG32(*pdev->regs.HPRT, u32hprt); +} + +/** + * @brief This function process all interrupt of USB in host mode + * @param [in] pdev device instance + * @retval None + */ +void usb_host_isr(usb_core_instance *pdev) +{ + uint32_t gintstsval; + if (0U != usb_getcurmod(&pdev->regs)) { + gintstsval = usb_getcoreintr(&pdev->regs); + if (0UL != (gintstsval & USBFS_GINTSTS_SOF)) { + usb_host_sof_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_RXFNE)) { + usb_host_rxflvl_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_NPTXFE)) { + usb_host_nptxfifoempty_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_PTXFE)) { + usb_host_ptxfifoempty_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_HCINT)) { + usb_host_hc_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_HPRTINT)) { + usb_host_port_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_DISCINT)) { + usb_host_disconn_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_IPXFR_INCOMPISOOUT)) { + usb_host_incomplisoout_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_WKUINT)) { + usb_host_wkupint_isr(pdev); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h new file mode 100644 index 0000000000..4d3093fbd1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h @@ -0,0 +1,128 @@ +/** + ******************************************************************************* + * @file usb_host_int.h + * @brief Head file for usb_host_int.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_INT_H__ +#define __USB_HOST_INT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define HCINT_NYET (1UL << 6) + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @brief clear the interrupt flag bit + * @param [in] pdev device instance + * @param [in] ch_num the channel index + * @param [in] intbit the interrupt bit of the register HCINTn + * @retval None + */ +__STATIC_INLINE void usb_host_clrint(usb_core_instance *pdev, uint32_t ch_num, uint32_t intbit) +{ + WRITE_REG32(pdev->regs.HC_REGS[ch_num]->HCINT, intbit); +} + +/** + * @brief mask the interrupt of ChHltd + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_mskchhltd(usb_core_instance *pdev, uint32_t ch_num) +{ + CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM); +} + +/** + * @brief unmask the interrupt of ChHltd + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_unmskchhltd(usb_core_instance *pdev, uint32_t ch_num) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM); +} + +/** + * @brief mask the interrupt of ACK + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_mskack(usb_core_instance *pdev, uint32_t ch_num) +{ + CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM); +} + +/** + * @brief unmask the interrupt of ACK + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_unmskack(usb_core_instance *pdev, uint32_t ch_num) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM); +} + +void usb_host_isr(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_INT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c new file mode 100644 index 0000000000..e24712a2f4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c @@ -0,0 +1,482 @@ +/** + ******************************************************************************* + * @file usb_host_stdreq.c + * @brief Standard requests for device enumeration + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" +#include "usb_host_ctrltrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes declared in the last part. + ******************************************************************************/ +void usb_host_parsedevdesc(usb_host_devdesc_typedef *, uint8_t *buf, uint16_t length); + +void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc, + usb_host_itfdesc_typedef *itf_desc, + USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length); +void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf); +void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf); +void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief issue a command descriptor from the connected device. parses the + * descriptor and updates the status once the response has been received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] req_type type of the descriptor + * @param [in] value_idx wValue of setup for the request to get Descriptr + * @param [in] buff: buffer to save the the descriptor + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | req_type; + phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; + phost->ctrlparam.setup.b.wValue.w = value_idx; + + if ((value_idx & 0xff00U) == USB_DESC_STRING) { + phost->ctrlparam.setup.b.wIndex.w = 0x0409U; + } else { + phost->ctrlparam.setup.b.wIndex.w = 0U; + } + phost->ctrlparam.setup.b.wLength.w = length; + return usb_host_ctrlreq(pdev, phost, buff, length); +} + +/** + * @brief Issue command to the device to get the device discription. it parses + * the device descriptor and updates the status once getting the device + * description. + * @param [in] pdev device instance + * @param [in] phost host state set. + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + (uint8_t)(USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD), + USB_DESC_DEVICE, + pdev->host.Rx_Buffer, + (uint16_t)length); + if (status == HSTATUS_OK) { + /* Commands successfully sent and Response Received */ + usb_host_parsedevdesc(&phost->device_prop.devdesc, pdev->host.Rx_Buffer, (uint16_t)length); + } + return status; +} + +/** + * @brief Issue a command to get the configuration description from the device + * connected, parse the configuration descriptor and update the + * status once the response has been received. + * @param [in] pdev device instance + * @param [in] phost host state set. + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint16_t length) +{ + HOST_STATUS status; + + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_CONFIGURATION, + pdev->host.Rx_Buffer, + length); + if (status == HSTATUS_OK) { + usb_host_parsecfgdesc(&phost->device_prop.devcfgdesc, + phost->device_prop.devitfdesc, + phost->device_prop.devepdesc, + pdev->host.Rx_Buffer, + length); + } + return status; +} + +/** + * @brief Issues string Descriptor command to the device. Once the response + * received, it parses the string descriptor and updates the status. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] string_index the index for the string + * @param [in] buff buffer to save the the string descriptor + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t string_index, + uint8_t *buff, + uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_STRING | string_index, + pdev->host.Rx_Buffer, + length); + if (status == HSTATUS_OK) { + usb_host_parsestringdesc(pdev->host.Rx_Buffer, buff, length); + } + return status; +} + +/** + * @brief issue a command to set the address for the device that have connected. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] DeviceAddress Device address which would be set to the conected device + * @retval status + */ +HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t DeviceAddress) +{ + /* + Refer to table9-3 of 9.4 + */ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_ADDRESS; + phost->ctrlparam.setup.b.wValue.w = (uint16_t)DeviceAddress; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a command to set the configuration to the connected device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] cfg_idx value for the configuration setup + * @retval status + */ +HOST_STATUS usb_host_setconfig(usb_core_instance *pdev, + USBH_HOST *phost, + uint16_t cfg_idx) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; + phost->ctrlparam.setup.b.wValue.w = cfg_idx; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a command to set the Interface value to the connected device + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] ep_num the index of the endpoint + * @param [in] altSetting the value for the setup of set interface + * @retval status + */ +HOST_STATUS usb_host_setintf(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t ep_num, + uint8_t altSetting) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_INTERFACE; + phost->ctrlparam.setup.b.wValue.w = altSetting; + phost->ctrlparam.setup.b.wIndex.w = ep_num; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a comman to clear or disable a specific feature in the device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] ep_num index of the endpoint + * @param [in] hc_num host channel index + * @retval status + */ +HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t ep_num, + uint8_t hc_num) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | + USB_REQ_RECIPIENT_ENDPOINT | + USB_REQ_TYPE_STANDARD; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; + phost->ctrlparam.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; + phost->ctrlparam.setup.b.wIndex.w = ep_num; + phost->ctrlparam.setup.b.wLength.w = 0U; + + if ((ep_num & USB_REQ_DIR_MASK) == USB_D2H) { + pdev->host.hc[hc_num].in_toggle = 0U; + } else { + pdev->host.hc[hc_num].out_toggle = 0U; + } + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief parse the data frame of device descriptor + * @param [in] dev_desc the structure of the device descriptor + * @param [in] buf buffer where the source descriptor is save + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsedevdesc(usb_host_devdesc_typedef *dev_desc, + uint8_t *buf, + uint16_t length) +{ + dev_desc->bLength = *(uint8_t *)(buf + 0U); + dev_desc->bDescriptorType = *(uint8_t *)(buf + 1U); + dev_desc->bcdUSB = SMALL_END(buf + 2U); + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); + dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); + + if (length > (uint16_t)8) { + dev_desc->idVendor = SMALL_END(buf + 8U); + dev_desc->idProduct = SMALL_END(buf + 10U); + dev_desc->bcdDevice = SMALL_END(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/** + * @brief This function Parses the configuration descriptor from the received buffer + * @param [in] cfg_desc the structure of configuration descriptor + * @param [in] itf_desc the structure of interface descriptor + * @param [in] ep_desc the structure of endpoint descriptor + * @param [in] buf buffer where the source descriptor is save + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc, + usb_host_itfdesc_typedef *itf_desc, + USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length) +{ + usb_host_itfdesc_typedef *pif ; + usb_host_itfdesc_typedef temp_pif ; + USB_HOST_EPDesc_TypeDef *pep; + USB_HOST_DescHeader_TypeDef *pdesc = (USB_HOST_DescHeader_TypeDef *)buf; + uint16_t ptr; + int8_t if_ix; + int8_t ep_ix; + static uint16_t prev_ep_size = 0U; + static uint8_t prev_itf = 0U; + + /* Parse the configuration descriptor */ + cfg_desc->bLength = *(uint8_t *)(buf + 0U); + cfg_desc->bDescriptorType = *(uint8_t *)(buf + 1U); + cfg_desc->wTotalLength = SMALL_END(buf + 2U); + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); + + if (length > USB_CONFIGURATION_DESC_SIZE) { + ptr = USB_LEN_CFG_DESC; + + if (cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) { + + while (ptr < cfg_desc->wTotalLength) { + pdesc = usb_host_getnextdesc((uint8_t *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) { + if_ix = (int8_t) * (((uint8_t *)pdesc) + 2U); + pif = &itf_desc[if_ix]; + + if ((*((uint8_t *)pdesc + 3U)) < 3U) { + usb_host_parseitfdesc(&temp_pif, (uint8_t *)pdesc); + ep_ix = (int8_t)0; + + /* Parse Ep descriptors relative to the current interface */ + if (temp_pif.bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) { + while (ep_ix < (int8_t)temp_pif.bNumEndpoints) { + pdesc = usb_host_getnextdesc((void *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) { + pep = &ep_desc[if_ix][ep_ix]; + + if (prev_itf != (uint8_t)if_ix) { + prev_itf = (uint8_t)if_ix; + usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif); + } else { + if (prev_ep_size > SMALL_END((uint8_t *)pdesc + 4U)) { + break; + } else { + usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif); + } + } + usb_host_parseepdesc(pep, (uint8_t *)pdesc); + prev_ep_size = SMALL_END((uint8_t *)pdesc + 4U); + ep_ix++; + } + } + } + } + } + } + } + prev_ep_size = 0U; + prev_itf = 0U; + } +} + +/** + * @brief This function parses the interface descriptor from the received buffer. + * @param [in] if_descriptor structure of interface descriptor + * @param [in] buf buffer where the source descriptor is save + * @retval None + */ +void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf) +{ + if_descriptor->bLength = *(uint8_t *)(buf + 0U); + if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U); + if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2U); + if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3U); + if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4U); + if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5U); + if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6U); + if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7U); + if_descriptor->iInterface = *(uint8_t *)(buf + 8U); +} + +/** + * @brief This function parses the endpoint descriptor from the received buffer. + * @param [in] ep_descriptor the structure of endpoint descriptor. + * @param [in] buf buffer where the source descriptor is save + * @retval None + */ +void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf) +{ + ep_descriptor->bLength = *(uint8_t *)(buf + 0U); + ep_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U); + ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2U); + ep_descriptor->bmAttributes = *(uint8_t *)(buf + 3U); + ep_descriptor->wMaxPacketSize = SMALL_END(buf + 4U); + ep_descriptor->bInterval = *(uint8_t *)(buf + 6U); +} + +/** + * @brief This function parses the string descriptor from the received buffer. + * @param [in] psrc source data + * @param [in] pdest destination data + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length) +{ + uint16_t strlength; + uint16_t tmp_idx; + /* + The describ of String Desctipor refers to 9.6.8 + psrc[0] = bLength bLength = N+2 + psrc[1] = bDescriptorType STRING Descriptor Type + ... + */ + if (psrc[1] == USB_DESC_TYPE_STRING) { + strlength = ((((uint16_t)psrc[0]) - 2U) <= length) ? (((uint16_t)psrc[0]) - 2U) : length; + psrc += 2U; + for (tmp_idx = 0U; tmp_idx < strlength; tmp_idx += 2U) { + *pdest = psrc[tmp_idx]; + pdest++; + } + *pdest = 0U; + } +} + +/** + * @brief This function gets the header of next descriptor. + * @param [in] pbuf buffer where the configuration descriptor is contained. + * @param [in] ptr data popinter inside the cfg descriptor + * @retval header of next descriptor + */ +USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr) +{ + USB_HOST_DescHeader_TypeDef *pnext; + + *ptr += ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength; + pnext = (USB_HOST_DescHeader_TypeDef *)((uint8_t *)pbuf + ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength); + + return (pnext); +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h new file mode 100644 index 0000000000..8046d96a87 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h @@ -0,0 +1,107 @@ +/** + ******************************************************************************* + * @file usb_host_stdreq.h + * @brief Header file for usb_host_stdreq.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_STDREQ_H__ +#define __USB_HOST_STDREQ_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* USBH_STDREQ_Exported_Defines */ +/* Standard Feature Selector for clear feature command */ +#define FEATURE_SELECTOR_ENDPOINT (0x00U) +#define FEATURE_SELECTOR_DEVICE (0x01U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern HOST_STATUS usb_host_getdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length); + +extern HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev, USBH_HOST *phost, uint8_t length); + +HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t string_index, + uint8_t *buff, + uint16_t length); + +extern HOST_STATUS usb_host_setconfig(usb_core_instance *pdev, USBH_HOST *phost, uint16_t cfg_idx); + +extern HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); + +extern HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev, USBH_HOST *phost, uint8_t DeviceAddress); + +extern HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num); + +extern HOST_STATUS usb_host_setintf(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t altSetting); + +extern USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_STDREQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h new file mode 100644 index 0000000000..dc2a0cbc82 --- /dev/null +++ b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h @@ -0,0 +1,199 @@ +/** + ******************************************************************************* + * @file usb_lib.h + * @brief Header of the Core Layer Driver + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_LIB_H__ +#define __USB_LIB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usb.h" +#include "hc32_ll.h" + +/** + * @addtogroup LL_USB_LIB LL USB Lib + * @{ + */ + +/** + * @addtogroup LL_USB_LIB_DEF LL USB Lib Define + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MAX_DATA_LENGTH (0x200U) + + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* status of the host channel */ +typedef enum { + HOST_CH_IDLE = 0U, + HOST_CH_XFERCOMPL, + HOST_CH_CHHLTD, + HOST_CH_NAK, + HOST_CH_NYET, + HOST_CH_STALL, + HOST_CH_XACTERR, + HOST_CH_BBLERR, + HOST_CH_DATATGLERR, + HOST_CH_AHBERR, + HOST_CH_FRMOVRUN, + HOST_CH_BNAINTR, + HOST_CH_XCS_XACT_ERR, + HOST_CH_DESC_LST_ROLLINTR +} HOST_CH_STATUS; + +typedef enum { + HOST_CH_XFER_IDLE = 0U, + HOST_CH_XFER_DONE, + HOST_CH_XFER_UNREADY, + HOST_CH_XFER_ERROR, + HOST_CH_XFER_STALL +} HOST_CH_XFER_STATE; + +typedef enum { + CTRL_START = 0U, + CTRL_XFRC, + CTRL_HALTED, + CTRL_NAK, + CTRL_STALL, + CTRL_XACTERR, + CTRL_BBLERR, + CTRL_DATATGLERR, + CTRL_FAIL +} CTRL_HANDLE_STATUS; + +typedef struct { + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ; + +typedef struct { + uint8_t *(*get_dev_desc)(uint16_t *length); + uint8_t *(*get_dev_langiddesc)(uint16_t *length); + uint8_t *(*get_dev_manufacturerstr)(uint16_t *length); + uint8_t *(*get_dev_productstr)(uint16_t *length); + uint8_t *(*get_dev_serialstr)(uint16_t *length); + uint8_t *(*get_dev_configstr)(uint16_t *length); + uint8_t *(*get_dev_interfacestr)(uint16_t *length); +} usb_dev_desc_func; + +typedef struct { + void (*class_init)(void *pdev); + void (*class_deinit)(void *pdev); + uint8_t (*ep0_setup)(void *pdev, USB_SETUP_REQ *req); + void (*ep0_datain)(void *pdev); + void (*ep0_dataout)(void *pdev); + uint8_t *(*class_getconfigdesc)(uint16_t *length); + uint8_t (*class_sof)(void *pdev); + void (*class_datain)(void *pdev, uint8_t epnum); + void (*class_dataout)(void *pdev, uint8_t epnum); + void (*class_syn_in_incomplt)(void *pdev); + void (*class_syn_out_incomplt)(void *pdev); +} usb_dev_class_func; + +typedef struct { + void (*user_init)(void); + void (*user_devrst)(void); + void (*user_devconfig)(void); + void (*user_devsusp)(void); + void (*user_devresume)(void); + void (*user_devconn)(void); + void (*user_devdisconn)(void); +} usb_dev_user_func; + +typedef struct { + __IO uint8_t device_config; + __IO uint8_t device_address; + __IO uint8_t device_state; + __IO uint8_t device_old_status; + __IO uint8_t device_cur_status; + __IO uint8_t connection_status; + __IO uint8_t device_remote_wakeup; + __IO uint8_t test_mode; + USB_DEV_EP in_ep[USB_MAX_TX_FIFOS]; + USB_DEV_EP out_ep[USB_MAX_TX_FIFOS]; + uint8_t setup_pkt_buf[24]; + usb_dev_class_func *class_callback; + usb_dev_user_func *user_callback; + usb_dev_desc_func *desc_callback; +} USB_DEV_PARAM; + +typedef struct { + uint16_t channel[USB_MAX_TX_FIFOS]; + USB_HOST_CH hc[USB_MAX_TX_FIFOS]; + __IO uint32_t is_dev_connect; + uint8_t Rx_Buffer[MAX_DATA_LENGTH]; + __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_MAX_TX_FIFOS]; + __IO HOST_CH_STATUS HC_Status[USB_MAX_TX_FIFOS]; + __IO HOST_CH_XFER_STATE URB_State[USB_MAX_TX_FIFOS]; +} USB_HOST_PARAM; + +typedef struct { + USB_CORE_BASIC_CFGS basic_cfgs; + LL_USB_TypeDef regs; +#ifdef USE_DEVICE_MODE + USB_DEV_PARAM dev; +#endif +#ifdef USE_HOST_MODE + USB_HOST_PARAM host; +#endif +} usb_core_instance; + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_LIB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/tools/sdk_dist.py b/bsp/hc32/tools/sdk_dist.py new file mode 100644 index 0000000000..4bbeb45950 --- /dev/null +++ b/bsp/hc32/tools/sdk_dist.py @@ -0,0 +1,21 @@ +import os +import sys +import shutil + +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy hc32 bsp library") + library_dir = os.path.join(dist_dir, 'libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'hc32_drivers'), os.path.join(library_dir, 'hc32_drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) -- cgit v1.3.1