From 4b897fea3f667bcb80e5afbf1490f03ba44cac8f Mon Sep 17 00:00:00 2001 From: xiao xie <335266746@qq.com> Date: Mon, 19 Sep 2022 13:20:02 +0800 Subject: [imxrt1170-m7]Adjust pro dir structure (#6446) --- bsp/imxrt/imxrt1170-nxp-evk/.config | 751 ---------- bsp/imxrt/imxrt1170-nxp-evk/Kconfig | 16 - bsp/imxrt/imxrt1170-nxp-evk/SConscript | 14 - bsp/imxrt/imxrt1170-nxp-evk/SConstruct | 70 - .../imxrt1170-nxp-evk/applications/SConscript | 22 - bsp/imxrt/imxrt1170-nxp-evk/applications/main.c | 31 - bsp/imxrt/imxrt1170-nxp-evk/applications/mnt.c | 61 - bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig | 209 --- .../board/MCUX_Config/MCUX_Config.mex | 596 -------- .../board/MCUX_Config/clock_config.c | 884 ----------- .../board/MCUX_Config/clock_config.h | 203 --- .../imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.c | 127 -- .../imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.h | 52 - bsp/imxrt/imxrt1170-nxp-evk/board/SConscript | 18 - bsp/imxrt/imxrt1170-nxp-evk/board/board.c | 1366 ----------------- bsp/imxrt/imxrt1170-nxp-evk/board/board.h | 45 - bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c | 401 ----- bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h | 32 - .../evkmimxrt1170_flexspi_nor_sdram.ini | 377 ----- .../board/linker_scripts/link.icf | 98 -- .../board/linker_scripts/link.lds | 276 ---- .../board/linker_scripts/link.sct | 140 -- .../imxrt1170-nxp-evk/board/ports/flexspi_port.h | 32 - .../imxrt1170-nxp-evk/board/ports/sdram_port.h | 57 - bsp/imxrt/imxrt1170-nxp-evk/m7/.config | 751 ++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/Kconfig | 16 + bsp/imxrt/imxrt1170-nxp-evk/m7/SConscript | 14 + bsp/imxrt/imxrt1170-nxp-evk/m7/SConstruct | 70 + .../imxrt1170-nxp-evk/m7/applications/SConscript | 22 + bsp/imxrt/imxrt1170-nxp-evk/m7/applications/main.c | 31 + bsp/imxrt/imxrt1170-nxp-evk/m7/applications/mnt.c | 61 + bsp/imxrt/imxrt1170-nxp-evk/m7/board/Kconfig | 209 +++ .../m7/board/MCUX_Config/MCUX_Config.mex | 596 ++++++++ .../m7/board/MCUX_Config/clock_config.c | 884 +++++++++++ .../m7/board/MCUX_Config/clock_config.h | 203 +++ .../m7/board/MCUX_Config/pin_mux.c | 127 ++ .../m7/board/MCUX_Config/pin_mux.h | 52 + bsp/imxrt/imxrt1170-nxp-evk/m7/board/SConscript | 18 + bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.c | 1366 +++++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.h | 45 + bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.c | 401 +++++ bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.h | 32 + .../evkmimxrt1170_flexspi_nor_sdram.ini | 377 +++++ .../m7/board/linker_scripts/link.icf | 98 ++ .../m7/board/linker_scripts/link.lds | 276 ++++ .../m7/board/linker_scripts/link.sct | 140 ++ .../m7/board/ports/flexspi_port.h | 32 + .../imxrt1170-nxp-evk/m7/board/ports/sdram_port.h | 57 + bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd | 1546 ++++++++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp | 1323 +++++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/project.eww | 10 + bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvoptx | 189 +++ bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx | 882 +++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h | 213 +++ bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.py | 164 +++ bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewd | 1546 ++++++++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewp | 1074 ++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewt | 1426 ++++++++++++++++++ bsp/imxrt/imxrt1170-nxp-evk/m7/template.eww | 10 + bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvoptx | 189 +++ bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvprojx | 401 +++++ bsp/imxrt/imxrt1170-nxp-evk/m7/xip/SConscript | 20 + .../m7/xip/evkmimxrt1170_flexspi_nor_config.c | 53 + .../m7/xip/evkmimxrt1170_flexspi_nor_config.h | 268 ++++ .../m7/xip/fsl_flexspi_nor_boot.c | 49 + .../m7/xip/fsl_flexspi_nor_boot.h | 147 ++ bsp/imxrt/imxrt1170-nxp-evk/project.ewd | 1546 -------------------- bsp/imxrt/imxrt1170-nxp-evk/project.ewp | 1323 ----------------- bsp/imxrt/imxrt1170-nxp-evk/project.eww | 10 - bsp/imxrt/imxrt1170-nxp-evk/project.uvoptx | 189 --- bsp/imxrt/imxrt1170-nxp-evk/project.uvprojx | 882 ----------- bsp/imxrt/imxrt1170-nxp-evk/rtconfig.h | 213 --- bsp/imxrt/imxrt1170-nxp-evk/rtconfig.py | 164 --- bsp/imxrt/imxrt1170-nxp-evk/template.ewd | 1546 -------------------- bsp/imxrt/imxrt1170-nxp-evk/template.ewp | 1074 -------------- bsp/imxrt/imxrt1170-nxp-evk/template.ewt | 1426 ------------------ bsp/imxrt/imxrt1170-nxp-evk/template.eww | 10 - bsp/imxrt/imxrt1170-nxp-evk/template.uvoptx | 189 --- bsp/imxrt/imxrt1170-nxp-evk/template.uvprojx | 401 ----- bsp/imxrt/imxrt1170-nxp-evk/xip/SConscript | 20 - .../xip/evkmimxrt1170_flexspi_nor_config.c | 53 - .../xip/evkmimxrt1170_flexspi_nor_config.h | 268 ---- .../imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.c | 49 - .../imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.h | 147 -- 84 files changed, 15388 insertions(+), 15388 deletions(-) delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/.config delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/Kconfig delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/SConscript delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/SConstruct delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/applications/SConscript delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/applications/main.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/applications/mnt.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/MCUX_Config.mex delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/SConscript delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/board.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/board.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.icf delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.lds delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.sct delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/ports/flexspi_port.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/.config create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/Kconfig create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/SConscript create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/SConstruct create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/applications/SConscript create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/applications/main.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/applications/mnt.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/Kconfig create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/MCUX_Config.mex create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/SConscript create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.icf create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.lds create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.sct create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/flexspi_port.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/sdram_port.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/project.eww create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvoptx create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.py create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewd create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewp create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewt create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.eww create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvoptx create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvprojx create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/xip/SConscript create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.h create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.c create mode 100644 bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/project.ewd delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/project.ewp delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/project.eww delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/project.uvoptx delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/project.uvprojx delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/rtconfig.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/rtconfig.py delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.ewd delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.ewp delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.ewt delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.eww delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.uvoptx delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/template.uvprojx delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/xip/SConscript delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.h delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.c delete mode 100644 bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.h (limited to 'bsp') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/.config b/bsp/imxrt/imxrt1170-nxp-evk/.config deleted file mode 100644 index e620c5db30..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/.config +++ /dev/null @@ -1,751 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_SMALL_MEM is not set -# CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_MEMHEAP_FAST_MODE=y -# CONFIG_RT_MEMHEAP_BSET_MODE is not set -# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set -CONFIG_RT_USING_MEMHEAP_AS_HEAP=y -CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40101 -# CONFIG_RT_USING_CPU_FFS is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -CONFIG_RT_USING_CPUTIME=y -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PHY=y -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -CONFIG_RT_USING_NETDEV=y -CONFIG_NETDEV_USING_IFCONFIG=y -CONFIG_NETDEV_USING_PING=y -CONFIG_NETDEV_USING_NETSTAT=y -CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set -CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 -# CONFIG_NETDEV_IPV6_SCOPES is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set - -# -# RT-Thread Smart -# -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set - -# -# Hardware Drivers Config -# -CONFIG_BSP_USING_QSPIFLASH=y -CONFIG_SOC_MIMXRT1176DVMAA=y - -# -# On-chip Peripheral Drivers -# -# CONFIG_BSP_USING_DMA is not set -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_LPUART=y -CONFIG_BSP_USING_LPUART1=y -# CONFIG_BSP_LPUART1_RX_USING_DMA is not set -# CONFIG_BSP_LPUART1_TX_USING_DMA is not set -# CONFIG_BSP_USING_LPUART3 is not set - -# -# Onboard Peripheral Drivers -# -# CONFIG_BSP_USING_SDRAM is not set -# CONFIG_BSP_USING_ETH is not set - -# -# Board extended module Drivers -# diff --git a/bsp/imxrt/imxrt1170-nxp-evk/Kconfig b/bsp/imxrt/imxrt1170-nxp-evk/Kconfig deleted file mode 100644 index c9221717cb..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "../libraries/Kconfig" -source "board/Kconfig" diff --git a/bsp/imxrt/imxrt1170-nxp-evk/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/SConscript deleted file mode 100644 index c7ef7659ec..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/SConstruct b/bsp/imxrt/imxrt1170-nxp-evk/SConstruct deleted file mode 100644 index c950363404..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/SConstruct +++ /dev/null @@ -1,70 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT -DefaultEnvironment(tools=[]) -if rtconfig.PLATFORM == 'armcc': - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - # overwrite cflags, because cflags has '--C99' - CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') -else: - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') - -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') - -Export('RTT_ROOT') -Export('rtconfig') - -SDK_ROOT = os.path.abspath('./') -if os.path.exists(SDK_ROOT + '/libraries'): - libraries_path_prefix = SDK_ROOT + '/libraries' -else: - libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' - -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -imxrt_library = 'MIMXRT1170' -rtconfig.BSP_LIBRARY_TYPE = imxrt_library - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript'))) - -# include drivers -objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1170-nxp-evk/applications/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/applications/SConscript deleted file mode 100644 index 050054c59f..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/applications/SConscript +++ /dev/null @@ -1,22 +0,0 @@ -import rtconfig -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -# add for startup script -if rtconfig.PLATFORM in ['gcc']: - CPPDEFINES = ['__START=entry'] -else: - CPPDEFINES = [] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1170-nxp-evk/applications/main.c deleted file mode 100644 index e28f0df99a..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/applications/main.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-05-06 tyustli first version - * - */ - -#include -#include -#include -#include - -#define EXAMPLE_LED_GPIO GPIO9 -#define EXAMPLE_LED_GPIO_PIN (3U) -#define EXAMPLE_LED_GPIO_PORT (3U) -#define LED_PIN GET_PIN(EXAMPLE_LED_GPIO_PORT, EXAMPLE_LED_GPIO_PIN) -int main(void) -{ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); - while (1) - { - rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(500); - rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); - } -} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/applications/mnt.c b/bsp/imxrt/imxrt1170-nxp-evk/applications/mnt.c deleted file mode 100644 index 3b89810de7..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/applications/mnt.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2019, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-09-19 Gavin first version - * - */ - -#include -#ifdef RT_USING_DFS_RAMFS -#include - -extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); - -int mnt_init(void) -{ - rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8*1024*1024; - - pool = rt_malloc(size); - if (pool == RT_NULL) - return 0; - - if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) - rt_kprintf("RAM file system initializated!\n"); - else - rt_kprintf("RAM file system initializate failed!\n"); - - return 0; -} -INIT_ENV_EXPORT(mnt_init); -#endif - -#ifdef BSP_USING_SDCARD_FATFS -#include -#include -#define DBG_TAG "app.filesystem" -#define DBG_LVL DBG_INFO -#include -static int filesystem_mount(void) -{ - while(rt_device_find("sd0") == RT_NULL) - { - rt_thread_mdelay(1); - } - - int ret = dfs_mount("sd0", "/", "elm", 0, 0); - if (ret != 0) - { - rt_kprintf("ret: %d\n",ret); - LOG_E("sd0p0 mount to '/' failed!"); - return ret; - } - - return RT_EOK; -} -INIT_APP_EXPORT(filesystem_mount); -#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig deleted file mode 100644 index 8a4c96034c..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig +++ /dev/null @@ -1,209 +0,0 @@ -menu "Hardware Drivers Config" - -config BSP_USING_QSPIFLASH - bool - default n - -config SOC_MIMXRT1176DVMAA - bool - select SOC_MIMXRT1170_SERIES - select BSP_USING_QSPIFLASH - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -menu "On-chip Peripheral Drivers" - - config BSP_USING_DMA - bool "Enable DMA" - default n - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - config BSP_USING_RTC - bool "Enable RTC" - select RT_USING_RTC - default n - - config BSP_USING_SDIO - bool "Enable SDIO" - select RT_USING_SDIO - select RT_USING_DFS - default n - - menuconfig BSP_USING_LPUART - bool "Enable UART" - select RT_USING_SERIAL - default y - - if BSP_USING_LPUART - config BSP_USING_LPUART1 - bool "Enable LPUART1" - default y - - config BSP_LPUART1_RX_USING_DMA - bool "Enable LPUART1 RX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_RX_DMA_CHANNEL - depends on BSP_LPUART1_RX_USING_DMA - int "Set LPUART1 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART1_TX_USING_DMA - bool "Enable LPUART1 TX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_TX_DMA_CHANNEL - depends on BSP_LPUART1_TX_USING_DMA - int "Set LPUART1 TX DMA channel (0-32)" - default 1 - - config BSP_USING_LPUART3 - bool "Enable LPUART3" - default n - - config BSP_LPUART3_RX_USING_DMA - bool "Enable LPUART3 RX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_RX_DMA_CHANNEL - depends on BSP_LPUART3_RX_USING_DMA - int "Set LPUART3 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART3_TX_USING_DMA - bool "Enable LPUART3 TX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_TX_DMA_CHANNEL - depends on BSP_LPUART3_TX_USING_DMA - int "Set LPUART3 TX DMA channel (0-32)" - default 1 - endif - - menuconfig BSP_USING_CAN - bool "Enable CAN" - select RT_USING_CAN - default n - if BSP_USING_CAN - config BSP_USING_CAN3 - bool "Enable FLEXCAN3" - default n - endif - - menuconfig BSP_USING_FLEXSPI - bool "Enable FLEXSPI" - default n - if BSP_USING_FLEXSPI - config BSP_USING_FLEXSPI1 - bool "Enable FLEXCAN1" - default n - config BSP_USING_FLEXSPI2 - bool "Enable FLEXCAN2" - default n - endif -endmenu - -menu "Onboard Peripheral Drivers" - - config BSP_USING_SDRAM - bool "Enable SDRAM" - default n - - menuconfig BSP_USING_ETH - bool "Enable Ethernet" - select RT_USING_NETDEV - select RT_USING_LWIP - default n - - - if BSP_USING_ETH - config BSP_USING_PHY - select RT_USING_PHY - bool "Enable ethernet phy" - default y - - if BSP_USING_PHY - config PHY_USING_KSZ8081 - bool "i.MX RT1176EVK uses ksz8081 phy" - default y - - if PHY_USING_KSZ8081 - config PHY_KSZ8081_ADDRESS - int "Specify address of phy device" - default 2 - - config PHY_RESET_KSZ8081_PORT - int "indicate port of reset" - default 6 - - config PHY_RESET_KSZ8081_PIN - int "indicate pin of reset" - default 12 - - config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE - bool "Enable the PHY ksz8081 RMII50M mode" - depends on PHY_USING_KSZ8081 - default y - endif - endif - - if BSP_USING_PHY - config PHY_USING_RTL8211F - bool "i.MX RT1176EVK uses rtl8211f phy" - default y - - if PHY_USING_RTL8211F - config PHY_RTL8211F_ADDRESS - int "Specify address of phy device" - default 1 - - config PHY_RESET_RTL8211F_PORT - int "indicate port of reset" - default 5 - - config PHY_RESET_RTL8211F_PIN - int "indicate pin of reset" - default 14 - - endif - endif - endif - - menuconfig BSP_USING_FS - bool "Enable File System" - select RT_USING_DFS_DEVFS - select RT_USING_DFS - default n - - if BSP_USING_FS - config BSP_USING_SDCARD_FATFS - bool "Enable SDCARD (FATFS)" - select BSP_USING_SDIO - select RT_USING_DFS_ELMFAT - default n - endif - -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/MCUX_Config.mex b/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/MCUX_Config.mex deleted file mode 100644 index 85d03f1993..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/MCUX_Config.mex +++ /dev/null @@ -1,596 +0,0 @@ - - - - MIMXRT1176xxxxx - MIMXRT1176DVMAA - ksdk2_0 - - - - - - - - true - false - false - true - false - - - - - 12.0.0 - - - - - Configures pin routing and optionally pin electrical features. - - true - cm7 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12.0.0 - - - - - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - true - - - - - - 12.0.0 - c_array - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12.0.0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N/A - - - - \ No newline at end of file diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.c deleted file mode 100644 index 2ce144f774..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - * Copyright 2020-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v10.0 -processor: MIMXRT1176xxxxx -package_id: MIMXRT1176DVMAA -mcu_data: ksdk2_0 -processor_version: 12.0.0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" -#include "fsl_dcdc.h" -#include "fsl_pmu.h" -#include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) -/* This function should not run from SDRAM since it will change SEMC configuration. */ -AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void)); -void UpdateSemcClock(void) -{ - /* Enable self-refresh mode and update semc clock root to 200MHz. */ - SEMC->IPCMD = 0xA55A000D; - while ((SEMC->INTR & 0x3) == 0) - ; - SEMC->INTR = 0x3; - SEMC->DCCR = 0x0B; - /* - * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only - * need to change the SEMC clock root here. If customer is using their own DCD and - * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be - * adjusted here to fine tune the SDRAM performance - */ - CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602; -} -#endif -#endif - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ARM_PLL_CLK.outFreq, value: 996 MHz} -- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz} -- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz} -- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz} -- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz} -- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz} -- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz} -- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz} -- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz} -- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz} -- {id: M4_CLK_ROOT.outFreq, value: 240 MHz} -- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz} -- {id: M7_CLK_ROOT.outFreq, value: 996 MHz} -- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} -- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz} -- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz} -- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz} -- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz} -- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz} -- {id: MQS_MCLK.outFreq, value: 24 MHz} -- {id: OSC_24M.outFreq, value: 24 MHz} -- {id: OSC_32K.outFreq, value: 32.768 kHz} -- {id: OSC_RC_16M.outFreq, value: 16 MHz} -- {id: OSC_RC_400M.outFreq, value: 400 MHz} -- {id: OSC_RC_48M.outFreq, value: 48 MHz} -- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz} -- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI1_MCLK1.outFreq, value: 24 MHz} -- {id: SAI1_MCLK3.outFreq, value: 24 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI2_MCLK1.outFreq, value: 24 MHz} -- {id: SAI2_MCLK3.outFreq, value: 24 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI3_MCLK1.outFreq, value: 24 MHz} -- {id: SAI3_MCLK3.outFreq, value: 24 MHz} -- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI4_MCLK1.outFreq, value: 24 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz} -- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} -- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} -- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} -- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} -- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} -- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} -- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} -- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz} -- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz} -- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz} -- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz} -settings: -- {id: CoreBusClockRootsInitializationConfig, value: selectedCore} -- {id: SOCDomainVoltage, value: OD} -- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} -- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} -- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} -- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'} -- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'} -- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'} -- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M} -- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'} -- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} -- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} -- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} -- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true} -- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true} -- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} -- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} -- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled} -- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled} -- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled} -- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} -- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} -- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} -- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} -- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} -- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} -- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'} -- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} -- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'} -- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} -- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'} -- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} -- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'} -- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} -- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'} -- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK} -- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4', locked: true} -- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} -- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'} -- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK} -- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ - -#ifndef SKIP_POWER_ADJUSTMENT -#if __CORTEX_M == 7 -#define BYPASS_LDO_LPSR 1 -#define SKIP_LDO_ADJUSTMENT 1 -#elif __CORTEX_M == 4 -#define SKIP_DCDC_ADJUSTMENT 1 -#define SKIP_FBB_ENABLE 1 -#endif -#endif - -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ - .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ - }; - -const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = - { - .mfd = 268435455, /* Denominator of spread spectrum */ - .ss = NULL, /* Spread spectrum parameter */ - .ssEnable = false, /* Enable spread spectrum or not */ - }; - -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ - .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ - .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .ss = NULL, /* Spread spectrum parameter */ - .ssEnable = false, /* Enable spread spectrum or not */ - }; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - clock_root_config_t rootCfg = {0}; - - /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */ - DCDC_BootIntoDCM(DCDC); - -#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT) - if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU)) - { - DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); - } - else - { - /* Set 1.125V for production samples to align with data sheet requirement */ - DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V); - } -#endif - -#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) - /* Check if FBB need to be enabled in OverDrive(OD) mode */ - if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) - { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); - } - else - { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); - } -#endif - -#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR - PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); - PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); -#endif - -#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT) - pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; - pmu_static_lpsr_dig_config_t lpsrDigConfig; - - if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) - { - PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); - PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); - } - - if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) - { - PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); - lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; - PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); - } -#endif - - /* Config CLK_1M */ - CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); - - /* Init OSC RC 16M */ - ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; - - /* Init OSC RC 400M */ - CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(true); - - /* Init OSC RC 48M */ - CLOCK_OSC_EnableOsc48M(true); - CLOCK_OSC_EnableOsc48MDiv2(true); - - /* Config OSC 24M */ - ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); - /* Wait for 24M OSC to be stable. */ - while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != - (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) - { - } - - /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ -#if __CORTEX_M == 7 - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); - - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - -#if __CORTEX_M == 4 - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); - - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#endif - - /* - * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code. - */ - /* Init Arm Pll. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - - /* Bypass Sys Pll1. */ - CLOCK_SetPllBypass(kCLOCK_PllSys1, true); - - /* DeInit Sys Pll1. */ - CLOCK_DeinitSysPll1(); - - /* Init Sys Pll2. */ - CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); - - /* Init System Pll2 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); - - /* Init System Pll2 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); - - /* Init System Pll2 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); - - /* Init System Pll2 pfd3. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); - - /* Init Sys Pll3. */ - CLOCK_InitSysPll3(); - - /* Init System Pll3 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); - - /* Init System Pll3 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); - - /* Init System Pll3 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); - - /* Init System Pll3 pfd3. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); - - /* Bypass Audio Pll. */ - CLOCK_SetPllBypass(kCLOCK_PllAudio, true); - - /* DeInit Audio Pll. */ - CLOCK_DeinitAudioPll(); - - /* Init Video Pll. */ - CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN); - - /* Module clock root configurations. */ - /* Configure M7 using ARM_PLL_CLK */ -#if __CORTEX_M == 7 - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); -#endif - - /* Configure M4 using SYS_PLL3_CLK */ -#if __CORTEX_M == 4 - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); -#endif - - /* Configure BUS using SYS_PLL3_CLK */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); - - /* Configure BUS_LPSR using SYS_PLL3_CLK */ - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; - rootCfg.div = 3; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); - - /* Configure SEMC using SYS_PLL2_PFD1_CLK */ -#ifndef SKIP_SEMC_INIT - rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1; - rootCfg.div = 3; - CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - UpdateSemcClock(); -#endif -#endif - - /* Configure CSSYS using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); - - /* Configure CSTRACE using SYS_PLL2_CLK */ - rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; - rootCfg.div = 4; - CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); - - /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ -#if __CORTEX_M == 4 - rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); -#endif - - /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ -#if __CORTEX_M == 7 - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 240; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - - /* Configure ADC1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); - - /* Configure ADC2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); - - /* Configure ACMP using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); - - /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); - - /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); - - /* Configure GPT1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); - - /* Configure GPT2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); - - /* Configure GPT3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg); - - /* Configure GPT4 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg); - - /* Configure GPT5 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg); - - /* Configure GPT6 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg); - - /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE)) - rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); -#endif - - /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg); - - /* Configure CAN1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); - - /* Configure CAN2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); - - /* Configure CAN3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); - - /* Configure LPUART1 using SYS_PLL2_CLK */ - rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); - - /* Configure LPUART2 using SYS_PLL2_CLK */ - rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); - - /* Configure LPUART3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg); - - /* Configure LPUART4 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg); - - /* Configure LPUART5 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg); - - /* Configure LPUART6 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg); - - /* Configure LPUART7 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg); - - /* Configure LPUART8 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg); - - /* Configure LPUART9 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg); - - /* Configure LPUART10 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg); - - /* Configure LPUART11 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg); - - /* Configure LPUART12 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg); - - /* Configure LPI2C1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); - - /* Configure LPI2C2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg); - - /* Configure LPI2C3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg); - - /* Configure LPI2C4 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg); - - /* Configure LPI2C5 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); - - /* Configure LPI2C6 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg); - - /* Configure LPSPI1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); - - /* Configure LPSPI2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg); - - /* Configure LPSPI3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg); - - /* Configure LPSPI4 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg); - - /* Configure LPSPI5 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg); - - /* Configure LPSPI6 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg); - - /* Configure EMV1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg); - - /* Configure EMV2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg); - - /* Configure ENET1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); - - /* Configure ENET2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); - - /* Configure ENET_QOS using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg); - - /* Configure ENET_25M using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg); - - /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); - - /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg); - - /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg); - - /* Configure USDHC1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); - - /* Configure USDHC2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); - - /* Configure ASRC using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); - - /* Configure MQS using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg); - - /* Configure MIC using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); - - /* Configure SPDIF using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); - - /* Configure SAI1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); - - /* Configure SAI2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); - - /* Configure SAI3 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); - - /* Configure SAI4 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); - - /* Configure GC355 using PLL_VIDEO_CLK */ - rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg); - - /* Configure LCDIF using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); - - /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg); - - /* Configure MIPI_REF using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg); - - /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg); - - /* Configure CSI2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg); - - /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg); - - /* Configure CSI2_UI using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg); - - /* Configure CSI using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg); - - /* Configure CKO1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); - - /* Configure CKO2 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); - - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ - IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; - /* Set ENET_1G Tx clock source. */ - IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK); - /* Set ENET_1G Ref clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; - /* Set ENET_QOS Tx clock source. */ - IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK; - /* Set ENET_QOS Ref clock source. */ - IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK; - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK; - /* Set GPT3 High frequency reference clock source. */ - IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK; - /* Set GPT4 High frequency reference clock source. */ - IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK; - /* Set GPT5 High frequency reference clock source. */ - IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK; - /* Set GPT6 High frequency reference clock source. */ - IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK; - -#if __CORTEX_M == 7 - SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); -#else - SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4); -#endif -} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.h b/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.h deleted file mode 100644 index 26d3652314..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.h +++ /dev/null @@ -1,203 +0,0 @@ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if __CORTEX_M == 7 - #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ -#else - #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */ -#endif - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL -#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL -#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL -#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL -#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 240000000UL -#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL -#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL -#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL -#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL -#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL -#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL - - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.c b/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.c deleted file mode 100644 index 7008424305..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright 2020-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v9.0 -processor: MIMXRT1176xxxxx -package_id: MIMXRT1176DVMAA -mcu_data: ksdk2_0 -processor_version: 0.9.6 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) { - BOARD_InitPins(); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - - {pin_num: D6, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_DISP_B2_07, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ - - /* GPIO configuration on GPIO_AD_04 (pin M13) */ - gpio_pin_config_t gpio9_pinM13_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */ - GPIO_PinInit(GPIO9, 3U, &gpio9_pinM13_config); - - /* GPIO configuration on GPIO_AD_26 (pin L14) */ - gpio_pin_config_t gpio9_pinL14_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_AD_04 (pin L14) */ - GPIO_PinInit(GPIO9, 25U, &gpio9_pinL14_config); - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_26_GPIO9_IO25, /* GPIO_AD_04 is configured as GPIO9_IO03 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 is configured as ARM_TRACE_SWO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ -} - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.h b/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.h deleted file mode 100644 index 5341111961..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/pin_mux.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2020-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/board/SConscript deleted file mode 100644 index 6d2f0c49d3..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/SConscript +++ /dev/null @@ -1,18 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -# add the general drivers. -src = Split(""" -board.c -dcd.c -MCUX_Config/clock_config.c -MCUX_Config/pin_mux.c -""") - -CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1176DVMAA_cm7', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1','ARM_MATH_CM7','USE_SDRAM','SOC_IMXRT1170_SERIES'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/board.c b/bsp/imxrt/imxrt1170-nxp-evk/board/board.c deleted file mode 100644 index a9dc521eb4..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/board.c +++ /dev/null @@ -1,1366 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - * 2022-08-15 xjy198903 add sdram pin config - * 2022-08-17 xjy198903 add rgmii pins - * 2022-09-01 xjy198903 add can pins - * 2022-09-07 xjy198903 add sdio pins - * 2022-09-14 xjy198903 add flexspi pins - */ - -#include -#include -#include "board.h" -#include "pin_mux.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" - -#ifdef BSP_USING_DMA -#include "fsl_dmamux.h" -#include "fsl_edma.h" -#endif - -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -/* MPU configuration. */ -static void BOARD_ConfigMPU(void) -{ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$RW_m_ncache$$Base[]; - /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ - extern uint32_t Image$$RW_m_ncache_unused$$Base[]; - extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; - uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? - 0 : - ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); -#elif defined(__MCUXPRESSO) -#if defined(__USE_SHMEM) - extern uint32_t __base_rpmsg_sh_mem; - extern uint32_t __top_rpmsg_sh_mem; - uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem); - uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart; -#else - extern uint32_t __base_NCACHE_REGION; - extern uint32_t __top_NCACHE_REGION; - uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; -#endif -#elif defined(__ICCARM__) || defined(__GNUC__) - extern uint32_t __NCACHE_REGION_START[]; - extern uint32_t __NCACHE_REGION_SIZE[]; - uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; -#endif - volatile uint32_t i = 0; - -#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - /* Disable I cache and D cache */ - if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) - { - SCB_DisableICache(); - } -#endif -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) - { - SCB_DisableDCache(); - } -#endif - - /* Disable MPU */ - ARM_MPU_Disable(); - - /* MPU configure: - * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, - * SubRegionDisable, Size) - * API in mpu_armv7.h. - * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches - * disabled. - * param AccessPermission Data access permissions, allows you to configure read/write access for User and - * Privileged mode. - * Use MACROS defined in mpu_armv7.h: - * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO - * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache - * 0 x 0 0 Strongly Ordered shareable - * 0 x 0 1 Device shareable - * 0 0 1 0 Normal not shareable Outer and inner write - * through no write allocate - * 0 0 1 1 Normal not shareable Outer and inner write - * back no write allocate - * 0 1 1 0 Normal shareable Outer and inner write - * through no write allocate - * 0 1 1 1 Normal shareable Outer and inner write - * back no write allocate - * 1 0 0 0 Normal not shareable outer and inner - * noncache - * 1 1 0 0 Normal shareable outer and inner - * noncache - * 1 0 1 1 Normal not shareable outer and inner write - * back write/read acllocate - * 1 1 1 1 Normal shareable outer and inner write - * back write/read acllocate - * 2 x 0 0 Device not shareable - * Above are normal use settings, if your want to see more details or want to config different inner/outter cache - * policy. - * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide - * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. - * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in - * mpu_armv7.h. - */ - - /* Region 0 setting: Instruction access disabled, No data access permission. */ - MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); - - /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - - /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - - /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); - - /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); - -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) - /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ - MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); -#endif - -#ifdef USE_SDRAM - /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); -#endif - - while ((size >> i) > 0x1U) - { - i++; - } - - if (i != 0) - { - /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ - assert(!(nonCacheStart % size)); - assert(size == (uint32_t)(1 << i)); - assert(i >= 5); - - /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); - } - - /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); - - /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); - - /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); - - /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); - - /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); - - /* Enable MPU */ - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - /* Enable I cache and D cache */ -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - SCB_EnableDCache(); -#endif -#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - SCB_EnableICache(); -#endif -} - - -/* This is the timer interrupt service routine. */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - - -#ifdef BSP_USING_LPUART -void imxrt_uart_pins_init(void) -{ -#ifdef BSP_USING_LPUART1 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ -#endif -#ifdef BSP_USING_LPUART2 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_02_LPUART2_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_03_LPUART2_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_02_LPUART2_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_03_LPUART2_RX, - 0x10B0u); - -#endif -#ifdef BSP_USING_LPUART3 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_06_LPUART3_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_07_LPUART3_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_06_LPUART3_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_07_LPUART3_RX, - 0x10B0u); -#endif -#ifdef BSP_USING_LPUART4 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_00_LPUART4_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_01_LPUART4_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_00_LPUART4_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_01_LPUART4_RX, - 0x10B0u); -#endif -#ifdef BSP_USING_LPUART5 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_12_LPUART5_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_13_LPUART5_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_12_LPUART5_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_13_LPUART5_RX, - 0x10B0u); -#endif -#ifdef BSP_USING_LPUART6 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_02_LPUART6_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_03_LPUART6_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_02_LPUART6_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_03_LPUART6_RX, - 0x10B0u); -#endif -#ifdef BSP_USING_LPUART7 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_31_LPUART7_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_32_LPUART7_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_31_LPUART7_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_32_LPUART7_RX, - 0x10B0u); -#endif -#ifdef BSP_USING_LPUART8 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_10_LPUART8_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_11_LPUART8_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_10_LPUART8_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_11_LPUART8_RX, - 0x10B0u); -#endif -} -#endif /* BSP_USING_LPUART */ -#ifdef BSP_USING_SDIO -void imxrt_SDcard_pins_init(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_34_USDHC1_VSELECT, /* GPIO_AD_34 is configured as USDHC1_VSELECT */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_35_GPIO10_IO02, /* GPIO_AD_35 is configured as GPIO10_IO02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, /* GPIO_SD_B1_00 is configured as USDHC1_CMD */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_00 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, /* GPIO_SD_B1_01 is configured as USDHC1_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_01 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, /* GPIO_SD_B1_02 is configured as USDHC1_DATA0 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_02 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, /* GPIO_SD_B1_03 is configured as USDHC1_DATA1 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_03 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, /* GPIO_SD_B1_04 is configured as USDHC1_DATA2 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_04 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, /* GPIO_SD_B1_05 is configured as USDHC1_DATA3 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_05 */ - IOMUXC_GPR->GPR43 = ((IOMUXC_GPR->GPR43 & - (~(IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK))) /* Mask bits to zero which are setting */ - | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(0x8000U) /* GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function: 0x8000U */ - ); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, /* GPIO_SD_B1_00 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, /* GPIO_SD_B1_01 PAD functional properties : */ - 0x0CU); /* PDRV Field: high drive strength - Pull Down Pull Up Field: No Pull - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, /* GPIO_SD_B1_02 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, /* GPIO_SD_B1_03 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, /* GPIO_SD_B1_04 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, /* GPIO_SD_B1_05 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ -} -#endif -#ifdef BSP_USING_ETH -void imxrt_eth_pins_init(void) { -#ifdef PHY_USING_RTL8211F - CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, /* GPIO_DISP_B1_00 is configured as ENET_1G_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, /* GPIO_DISP_B1_01 is configured as ENET_1G_RX_CLK */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, /* GPIO_DISP_B1_02 is configured as ENET_1G_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, /* GPIO_DISP_B1_03 is configured as ENET_1G_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, /* GPIO_DISP_B1_04 is configured as ENET_1G_RX_DATA02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, /* GPIO_DISP_B1_05 is configured as ENET_1G_RX_DATA03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, /* GPIO_DISP_B1_06 is configured as ENET_1G_TX_DATA03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, /* GPIO_DISP_B1_07 is configured as ENET_1G_TX_DATA02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, /* GPIO_DISP_B1_08 is configured as ENET_1G_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, /* GPIO_DISP_B1_09 is configured as ENET_1G_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, /* GPIO_DISP_B1_10 is configured as ENET_1G_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, /* GPIO_DISP_B1_11 is configured as ENET_1G_TX_CLK_IO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13, /* GPIO_DISP_B2_12 is configured as GPIO_MUX5_IO13 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14, /* GPIO_DISP_B2_13 is configured as GPIO_MUX5_IO14 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, /* GPIO_EMC_B2_19 is configured as ENET_1G_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, /* GPIO_EMC_B2_20 is configured as ENET_1G_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ -#else - CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_12_GPIO9_IO11, /* GPIO_AD_12 is configured as GPIO9_IO11 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_32_ENET_MDC, /* GPIO_AD_32 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_33_ENET_MDIO, /* GPIO_AD_33 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, /* GPIO_DISP_B2_02 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, /* GPIO_DISP_B2_03 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, /* GPIO_DISP_B2_04 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, /* GPIO_DISP_B2_05 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_05 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, /* GPIO_DISP_B2_06 is configured as ENET_RX_DATA00 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_06 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, /* GPIO_DISP_B2_07 is configured as ENET_RX_DATA01 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_07 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, /* GPIO_DISP_B2_08 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, /* GPIO_DISP_B2_09 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_GPR->GPR4 = ((IOMUXC_GPR->GPR4 & - (~(IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK))) /* Mask bits to zero which are setting */ - | IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) /* ENET_REF_CLK direction control: 0x01U */ - ); - IOMUXC_SetPinMux( - IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12, /* GPIO_LPSR_12 is configured as GPIO12_IO12 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_12_GPIO9_IO11, /* GPIO_AD_12 PAD functional properties : */ - 0x06U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, /* GPIO_DISP_B2_02 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, /* GPIO_DISP_B2_03 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, /* GPIO_DISP_B2_04 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, /* GPIO_DISP_B2_05 PAD functional properties : */ - 0x03U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, /* GPIO_DISP_B2_06 PAD functional properties : */ - 0x06U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, /* GPIO_DISP_B2_07 PAD functional properties : */ - 0x06U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, /* GPIO_DISP_B2_08 PAD functional properties : */ - 0x06U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, /* GPIO_DISP_B2_09 PAD functional properties : */ - 0x06U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12, /* GPIO_LPSR_12 PAD functional properties : */ - 0x0EU); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain LPSR Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - -#endif -} -#endif - -#ifdef BSP_USING_SDRAM -void imxrt_sdram_pins_init(void) -{ - // SEMC - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 is configured as SEMC_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 is configured as SEMC_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 is configured as SEMC_DATA02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 is configured as SEMC_DATA03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 is configured as SEMC_DATA04 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 is configured as SEMC_DATA05 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 is configured as SEMC_DATA06 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 is configured as SEMC_DATA07 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 is configured as SEMC_DM00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 is configured as SEMC_ADDR00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 is configured as SEMC_ADDR01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 is configured as SEMC_ADDR02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 is configured as SEMC_ADDR03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 is configured as SEMC_ADDR04 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 is configured as SEMC_ADDR05 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 is configured as SEMC_ADDR06 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 is configured as SEMC_ADDR07 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 is configured as SEMC_ADDR08 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 is configured as SEMC_ADDR09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 is configured as SEMC_ADDR11 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 is configured as SEMC_ADDR12 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 is configured as SEMC_BA0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 is configured as SEMC_BA1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 is configured as SEMC_ADDR10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 is configured as SEMC_CAS */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 is configured as SEMC_RAS */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 is configured as SEMC_CLK */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 is configured as SEMC_CKE */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 is configured as SEMC_WE */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 is configured as SEMC_CS0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 is configured as SEMC_DATA08 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 is configured as SEMC_DATA09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 is configured as SEMC_DATA10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 is configured as SEMC_DATA11 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 is configured as SEMC_DATA12 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 is configured as SEMC_DATA13 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 is configured as SEMC_DATA14 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 is configured as SEMC_DATA15 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 is configured as SEMC_DM01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 is configured as SEMC_DQS */ - 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B1_39 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 is configured as SEMC_RDY */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 is configured as SEMC_CSX00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 is configured as SEMC_DATA16 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 is configured as SEMC_DATA17 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 is configured as SEMC_DATA18 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 is configured as SEMC_DATA19 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 is configured as SEMC_DATA20 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 is configured as SEMC_DATA21 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 is configured as SEMC_DATA22 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 is configured as SEMC_DATA23 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 is configured as SEMC_DM02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 is configured as SEMC_DATA24 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 is configured as SEMC_DATA25 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 is configured as SEMC_DATA26 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 is configured as SEMC_DATA27 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 is configured as SEMC_DATA28 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 is configured as SEMC_DATA29 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 is configured as SEMC_DATA30 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 is configured as SEMC_DATA31 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 is configured as SEMC_DM03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 is configured as SEMC_DQS4 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 PAD functional properties : */ - 0x04U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pullup resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 PAD functional properties : */ - 0x08U); /* PDRV Field: high drive strength - Pull Down Pull Up Field: Internal pulldown resistor enabled - Open Drain Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ -} -#endif - -#ifdef BSP_USING_CAN -void imxrt_can_pins_init(void) -{ -#ifdef BSP_USING_CAN3 - CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX, /* GPIO_LPSR_00 is configured as FLEXCAN3_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX, /* GPIO_LPSR_01 is configured as FLEXCAN3_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ -#endif -} -#endif - -#ifdef BSP_USING_FLEXSPI -void imxrt_flexspi_pins_init(void) -{ -#ifdef BSP_USING_FLEXSPI1 - CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03, /* GPIO_SD_B2_00 is configured as FLEXSPI1_B_DATA03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02, /* GPIO_SD_B2_01 is configured as FLEXSPI1_B_DATA02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01, /* GPIO_SD_B2_02 is configured as FLEXSPI1_B_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00, /* GPIO_SD_B2_03 is configured as FLEXSPI1_B_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, /* GPIO_SD_B2_05 is configured as FLEXSPI1_A_DQS */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, /* GPIO_SD_B2_06 is configured as FLEXSPI1_A_SS0_B */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, /* GPIO_SD_B2_07 is configured as FLEXSPI1_A_SCLK */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, /* GPIO_SD_B2_08 is configured as FLEXSPI1_A_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, /* GPIO_SD_B2_09 is configured as FLEXSPI1_A_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, /* GPIO_SD_B2_10 is configured as FLEXSPI1_A_DATA02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, /* GPIO_SD_B2_11 is configured as FLEXSPI1_A_DATA03 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - -#endif -} -#endif - -void rt_hw_board_init() -{ - BOARD_ConfigMPU(); - BOARD_InitPins(); - BOARD_BootClockRUN(); - - NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - -#ifdef BSP_USING_LPUART - imxrt_uart_pins_init(); -#endif - -#ifdef BSP_USING_SDRAM - imxrt_sdram_pins_init(); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef BSP_USING_SDIO - imxrt_SDcard_pins_init(); -#endif - -#ifdef BSP_USING_ETH - imxrt_eth_pins_init(); -#endif - -#ifdef BSP_USING_CAN - imxrt_can_pins_init(); -#endif - -#ifdef BSP_USING_FLEXSPI - imxrt_flexspi_pins_init(); -#endif -} - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/board.h b/bsp/imxrt/imxrt1170-nxp-evk/board/board.h deleted file mode 100644 index e49af960a1..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/board.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include "fsl_common.h" -#include "clock_config.h" - -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) -extern int Image$$RTT_HEAP$$ZI$$Base; -extern int Image$$RTT_HEAP$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) -#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) - -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -extern void __RTT_HEAP_END; -#define HEAP_END (&__RTT_HEAP_END) - -#else -extern int heap_start; -extern int heap_end; -#define HEAP_BEGIN (&heap_start) -#define HEAP_END (&heap_end) -#endif - -#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) - -/*! @brief The board flash size */ -#define BOARD_FLASH_SIZE (0x1000000U) - -void rt_hw_board_init(void); - -#endif - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c b/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c deleted file mode 100644 index b7e60a294b..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright 2020-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#include "dcd.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.dcd_data"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.dcd_data" -#endif - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: DCDx v3.0 -processor: MIMXRT1176xxxxx -package_id: MIMXRT1176DVMAA -mcu_data: ksdk2_0 -processor_version: 12.0.0 -output_format: c_array - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ -const uint8_t dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x05, 0x10, - /* Version */ - 0x41, - - /* COMMANDS */ - - /* group: 'Imported Commands' */ - /* #1.1-139, command header bytes for merged 'Write - value' command */ - 0xCC, 0x04, 0x5C, 0x04, - /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */ - 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02, - /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, - /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4 */ - 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, - /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, - /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, - /* #1.53, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, - /* #1.54, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, - /* #1.55, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, - /* #1.56, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, - /* #1.57, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, - /* #1.58, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, - /* #1.59, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, - /* #1.60, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, - /* #1.61, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, - /* #1.62, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, - /* #1.63, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x81, 0x04, 0x00, 0x00, 0x00, 0x00, - /* #1.64, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20, value: 0x00, size: 4 */ - 0x40, 0x0E, 0x81, 0x08, 0x00, 0x00, 0x00, 0x00, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, - /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, - /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, - /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, - /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, - /* #1.95, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, - /* #1.96, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, - /* #1.97, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, - /* #1.98, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, - /* #1.99, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, - /* #1.100, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, - /* #1.101, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, - /* #1.102, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, - /* #1.103, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, - /* #1.104, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, - /* #1.105, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xF4, 0x00, 0x00, 0x00, 0x08, - /* #1.106, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xF8, 0x00, 0x00, 0x00, 0x08, - /* #1.107, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, - /* #1.108, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, - /* #1.109, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, - /* #1.110, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, - /* #1.111, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, - /* #1.112, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, - /* #1.113, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, - /* #1.114, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, - /* #1.115, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, - /* #1.116, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, - /* #1.117, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, - /* #1.118, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, - /* #1.119, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, - /* #1.120, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, - /* #1.121, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, - /* #1.122, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, - /* #1.123, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, - /* #1.124, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x84, 0x00, 0x00, 0x00, 0x00, 0x08, - /* #1.125, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x84, 0x04, 0x00, 0x00, 0x00, 0x08, - /* #1.126, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x84, 0x08, 0x00, 0x00, 0x00, 0x08, - /* #1.127, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05, value: 0x08, size: 4 */ - 0x40, 0x0E, 0x84, 0x0C, 0x00, 0x00, 0x00, 0x08, - /* #1.128, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.129, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ - 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.130, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ - 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, - /* #1.131, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4 */ - 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, - /* #1.132, command: write_value, address: SEMC_SDRAMCR0, value: 0xF32, size: 4 */ - 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, - /* #1.133, command: write_value, address: SEMC_SDRAMCR1, value: 0x772A22, size: 4 */ - 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, - /* #1.134, command: write_value, address: SEMC_SDRAMCR2, value: 0x10A0D, size: 4 */ - 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, - /* #1.135, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */ - 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, - /* #1.136, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.137, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.138, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.139, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #3, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #4, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #5, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #6, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #7.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ - 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, - /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #8, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #9, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #10, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #11, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #12, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #13.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ - 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, - /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #14, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #15, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #16, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #17, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #18, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #19.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ - 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, - /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ - 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, - /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #20, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #21, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #22, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #23, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #24, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #25, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, - /* #26, command: nop */ - 0xC0, 0x00, 0x04, 0x00, - /* #27, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; -/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ - -#else -const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h b/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h deleted file mode 100644 index 77de9fa8b6..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef __DCD__ -#define __DCD__ - -#include - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/************************************* - * DCD Data - *************************************/ -#define DCD_TAG_HEADER (0xD2) -#define DCD_VERSION (0x41) -#define DCD_TAG_HEADER_SHIFT (24) -#define DCD_ARRAY_SIZE 1 - -#endif /* __DCD__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini b/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini deleted file mode 100644 index c39b5460c8..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2019-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -FUNC void restoreFlexRAM(void) -{ - unsigned int value; - - value = _RDWORD(0x400E4044); - value &= ~(0xFFFF); - value |= 0xFFAA; - _WDWORD(0x400E4044, value); - - value = _RDWORD(0x400E4048); - value &= ~(0xFFFF); - value |= 0xFFAA; - _WDWORD(0x400E4048, value); - - value = _RDWORD(0x400E4040); - value &= ~(0xFF << 8); - value |= 0x7 | (0xAA << 8); - _WDWORD(0x400E4040, value); -} - -FUNC void SDRAM_WaitIpCmdDone(void) -{ - unsigned long reg; - do - { - reg = _RDWORD(0x400D403C); - }while((reg & 0x3) == 0); - - _WDWORD(0x400D403C,0x00000003); // clear IPCMDERR and IPCMDDONE bits -} - -FUNC void EnableOSC400M(void) -{ - unsigned int reg; - // CTRL1: power down - reg = _RDWORD(0x40C84050); - reg &= ~0x1; - _WDWORD(0x40C84050,reg); - // CTRL2: enable clock - reg = _RDWORD(0x40C84060); - reg |= 0x1; - _WDWORD(0x40C84060,reg); -} - -FUNC void EnableOSC24M(void) -{ - unsigned int reg; - reg = _RDWORD(0x40C84020); - if(0 == (reg & 0x10)) - { - reg = 0x14; // OSC_EN and LP_EN - _WDWORD(0x40C84020,reg); - reg = _RDWORD(0x40C84020); - while (0 == (reg & 0x80000000)); - } -} - -FUNC void EnablePllLdo(void) -{ - unsigned int reg; - // CTRL_AI_CTRL - _WDWORD(0x40C84820,0x00000000); - // CTRL_AI_WDATA - _WDWORD(0x40C84830,0x00000105); - // PMU_LDO_PLL - reg = _RDWORD(0x40C84500); - reg |= 0x10000; - _WDWORD(0x40C84500,reg); - _Sleep_(100); - - // PMU_POWER_DETECT_CTRL - _WDWORD(0x40C84580,0x00000100); - _Sleep_(1); - // PMU_REF_CTRL - _WDWORD(0x40C84570,0x00000010); -} - -FUNC void InitSysPll2Pfd1(void) -{ - unsigned int reg; - unsigned int stable; - // ANADIG_PLL_PLL_528_PFD - reg = _RDWORD(0x40C84270); - if (((reg & 0x8000) != 0) || (((reg & 0x3F00) >> 8) != 16)) - { - stable = reg & 0x4000; - - reg |= 0x8000; - _WDWORD(0x40C84270,reg); - - reg = _RDWORD(0x40C84270); - reg &= ~0x3F00; - reg |= 16 << 8; - _WDWORD(0x40C84270,reg); - - reg = _RDWORD(0x40C84250); - reg ^= 0x4; - _WDWORD(0x40C84250,reg); - - reg = _RDWORD(0x40C84270); - reg &= ~0x8000; - _WDWORD(0x40C84270,reg); - do - { - reg = _RDWORD(0x40C84270) & 0x4000; - } while (reg == stable); - } - else - { - //syspll2 pfd1 has been initialized already - reg &= ~0x8000; - _WDWORD(0x40C84270,reg); - } -} - -FUNC void InitSysPll2(void) -{ - unsigned int reg; - - // ANADIG_PLL_PLL_528_CTRL - reg = _RDWORD(0x40C84240); - if (reg & 0x800000) - { - // SysPll2 has been initialized - reg &= ~0x40000000; - _WDWORD(0x40C84240, reg); - return; - } - - reg = _RDWORD(0x40C84270); - reg |= 0x80808080; - _WDWORD(0x40C84270, reg); - - reg = _RDWORD(0x40C84240); - reg &= ~(0x802000); - reg |= 0x40000000; - _WDWORD(0x40C84240, reg); - - // ANADIG_PLL_PLL_528_MFN - _WDWORD(0x40C84280, 0); - // ANADIG_PLL_PLL_528_MFI - _WDWORD(0x40C84290, 22); - // ANADIG_PLL_PLL_528_MFD - _WDWORD(0x40C842A0, 0x0FFFFFFF); - - // ANADIG_PLL_PLL_528_CTRL - _WDWORD(0x40C84240, 0x8 | 0x40000000); - _Sleep_(30); - - // ANADIG_PLL_PLL_528_CTRL - reg = _RDWORD(0x40C84240); - reg |= 0x800000 | 0x800; - _WDWORD(0x40C84240, reg); - _Sleep_(250); - - reg = _RDWORD(0x40C84240); - reg &= ~0x800; - _WDWORD(0x40C84240, reg); - - do - { - reg = _RDWORD(0x40C84240); - } while ((reg & 0x20000000) == 0); - - reg |= 0x2000; - _WDWORD(0x40C84240, reg); - - reg &= ~0x40000000; - _WDWORD(0x40C84240, reg); -} - -FUNC void SetSemcClock(void) -{ - //EnableOSC400M(); - EnablePllLdo(); - InitSysPll2(); - InitSysPll2Pfd1(); - - // Set SEMC root clock - // Use sys pll2 pfd1 divided by 3: 198Mhz - _WDWORD(0x40CC0200,0x00000602); -} - -FUNC void _clock_init(void) -{ - SetSemcClock(); -} - -FUNC void _sdr_Init(void) -{ - // Config IOMUX - _WDWORD(0x400E8010, 0x00000000); - _WDWORD(0x400E8014, 0x00000000); - _WDWORD(0x400E8018, 0x00000000); - _WDWORD(0x400E801C, 0x00000000); - _WDWORD(0x400E8020, 0x00000000); - _WDWORD(0x400E8024, 0x00000000); - _WDWORD(0x400E8028, 0x00000000); - _WDWORD(0x400E802C, 0x00000000); - _WDWORD(0x400E8030, 0x00000000); - _WDWORD(0x400E8034, 0x00000000); - _WDWORD(0x400E8038, 0x00000000); - _WDWORD(0x400E803C, 0x00000000); - _WDWORD(0x400E8040, 0x00000000); - _WDWORD(0x400E8044, 0x00000000); - _WDWORD(0x400E8048, 0x00000000); - _WDWORD(0x400E804C, 0x00000000); - _WDWORD(0x400E8050, 0x00000000); - _WDWORD(0x400E8054, 0x00000000); - _WDWORD(0x400E8058, 0x00000000); - _WDWORD(0x400E805C, 0x00000000); - _WDWORD(0x400E8060, 0x00000000); - _WDWORD(0x400E8064, 0x00000000); - _WDWORD(0x400E8068, 0x00000000); - _WDWORD(0x400E806C, 0x00000000); - _WDWORD(0x400E8070, 0x00000000); - _WDWORD(0x400E8074, 0x00000000); - _WDWORD(0x400E8078, 0x00000000); - _WDWORD(0x400E807C, 0x00000000); - _WDWORD(0x400E8080, 0x00000000); - _WDWORD(0x400E8084, 0x00000000); - _WDWORD(0x400E8088, 0x00000000); - _WDWORD(0x400E808C, 0x00000000); - _WDWORD(0x400E8090, 0x00000000); - _WDWORD(0x400E8094, 0x00000000); - _WDWORD(0x400E8098, 0x00000000); - _WDWORD(0x400E809C, 0x00000000); - _WDWORD(0x400E80A0, 0x00000000); - _WDWORD(0x400E80A4, 0x00000000); - _WDWORD(0x400E80A8, 0x00000000); - _WDWORD(0x400E80AC, 0x00000010); // EMC_39, DQS PIN, enable SION - _WDWORD(0x400E80B0, 0x00000000); - _WDWORD(0x400E80B4, 0x00000000); - _WDWORD(0x400E80B8, 0x00000000); - _WDWORD(0x400E80BC, 0x00000000); - _WDWORD(0x400E80C0, 0x00000000); - _WDWORD(0x400E80C4, 0x00000000); - _WDWORD(0x400E80C8, 0x00000000); - _WDWORD(0x400E80CC, 0x00000000); - _WDWORD(0x400E80D0, 0x00000000); - _WDWORD(0x400E80D4, 0x00000000); - _WDWORD(0x400E80D8, 0x00000000); - _WDWORD(0x400E80DC, 0x00000000); - _WDWORD(0x400E80E0, 0x00000000); - _WDWORD(0x400E80E4, 0x00000000); - _WDWORD(0x400E80E8, 0x00000000); - _WDWORD(0x400E80EC, 0x00000000); - _WDWORD(0x400E80F0, 0x00000000); - _WDWORD(0x400E80F4, 0x00000000); - _WDWORD(0x400E80F8, 0x00000000); - _WDWORD(0x400E80FC, 0x00000000); - _WDWORD(0x400E8100, 0x00000000); - _WDWORD(0x400E8104, 0x00000000); - _WDWORD(0x400E8108, 0x00000000); - - // PAD ctrl - // PDRV = 1b (normal); PULL = 10b (PD) - _WDWORD(0x400E8254, 0x00000008); - _WDWORD(0x400E8258, 0x00000008); - _WDWORD(0x400E825C, 0x00000008); - _WDWORD(0x400E8260, 0x00000008); - _WDWORD(0x400E8264, 0x00000008); - _WDWORD(0x400E8268, 0x00000008); - _WDWORD(0x400E826C, 0x00000008); - _WDWORD(0x400E8270, 0x00000008); - _WDWORD(0x400E8274, 0x00000008); - _WDWORD(0x400E8278, 0x00000008); - _WDWORD(0x400E827C, 0x00000008); - _WDWORD(0x400E8280, 0x00000008); - _WDWORD(0x400E8284, 0x00000008); - _WDWORD(0x400E8288, 0x00000008); - _WDWORD(0x400E828C, 0x00000008); - _WDWORD(0x400E8290, 0x00000008); - _WDWORD(0x400E8294, 0x00000008); - _WDWORD(0x400E8298, 0x00000008); - _WDWORD(0x400E829C, 0x00000008); - _WDWORD(0x400E82A0, 0x00000008); - _WDWORD(0x400E82A4, 0x00000008); - _WDWORD(0x400E82A8, 0x00000008); - _WDWORD(0x400E82AC, 0x00000008); - _WDWORD(0x400E82B0, 0x00000008); - _WDWORD(0x400E82B4, 0x00000008); - _WDWORD(0x400E82B8, 0x00000008); - _WDWORD(0x400E82BC, 0x00000008); - _WDWORD(0x400E82C0, 0x00000008); - _WDWORD(0x400E82C4, 0x00000008); - _WDWORD(0x400E82C8, 0x00000008); - _WDWORD(0x400E82CC, 0x00000008); - _WDWORD(0x400E82D0, 0x00000008); - _WDWORD(0x400E82D4, 0x00000008); - _WDWORD(0x400E82D8, 0x00000008); - _WDWORD(0x400E82DC, 0x00000008); - _WDWORD(0x400E82E0, 0x00000008); - _WDWORD(0x400E82E4, 0x00000008); - _WDWORD(0x400E82E8, 0x00000008); - _WDWORD(0x400E82EC, 0x00000008); - _WDWORD(0x400E82F0, 0x00000008); - _WDWORD(0x400E82F4, 0x00000008); - _WDWORD(0x400E82F8, 0x00000008); - _WDWORD(0x400E82FC, 0x00000008); - _WDWORD(0x400E8300, 0x00000008); - _WDWORD(0x400E8304, 0x00000008); - _WDWORD(0x400E8308, 0x00000008); - _WDWORD(0x400E830C, 0x00000008); - _WDWORD(0x400E8310, 0x00000008); - _WDWORD(0x400E8314, 0x00000008); - _WDWORD(0x400E8318, 0x00000008); - _WDWORD(0x400E831C, 0x00000008); - _WDWORD(0x400E8320, 0x00000008); - _WDWORD(0x400E8324, 0x00000008); - _WDWORD(0x400E8328, 0x00000008); - _WDWORD(0x400E832C, 0x00000008); - _WDWORD(0x400E8330, 0x00000008); - _WDWORD(0x400E8334, 0x00000008); - _WDWORD(0x400E8338, 0x00000008); - _WDWORD(0x400E833C, 0x00000008); - _WDWORD(0x400E8400, 0x00000008); - _WDWORD(0x400E8404, 0x00000008); - _WDWORD(0x400E8408, 0x00000008); - _WDWORD(0x400E840C, 0x00000008); - - // Config SDR Controller Registers/ - _WDWORD(0x400d4000,0x10000004); // MCR - _WDWORD(0x400d4008,0x00000081); // BMCR0 - _WDWORD(0x400d400C,0x00000081); // BMCR1 - _WDWORD(0x400d4010,0x8000001D); // BR0, 64MB - - _WDWORD(0x400d4040,0x00000F32); // SDRAMCR0, 32bit - _WDWORD(0x400d4044,0x00772A22); // SDRAMCR1 - _WDWORD(0x400d4048,0x00010A0D); // SDRAMCR2 - _WDWORD(0x400d404C,0x21210408); // SDRAMCR3 - - _WDWORD(0x400d4090,0x80000000); // IPCR0 - _WDWORD(0x400d4094,0x00000002); // IPCR1 - _WDWORD(0x400d4098,0x00000000); // IPCR2 - - - _WDWORD(0x400d409C,0xA55A000F); // IPCMD, SD_CC_IPREA - SDRAM_WaitIpCmdDone(); - _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF - SDRAM_WaitIpCmdDone(); - _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF - SDRAM_WaitIpCmdDone(); - _WDWORD(0x400d40A0,0x00000033); // IPTXDAT - _WDWORD(0x400d409C,0xA55A000A); // SD_CC_IMS - SDRAM_WaitIpCmdDone(); - _WDWORD(0x400d404C,0x21210409 ); // enable sdram self refresh again after initialization done. -} - -FUNC void Setup (void) { - SP = _RDWORD(0x30002000); // Setup Stack Pointer - PC = _RDWORD(0x30002004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x30002000); // Setup Vector Table Offset Register -} - -FUNC void OnResetExec (void) { // executes upon software RESET - _clock_init(); - _sdr_Init(); - Setup(); // Setup for Running -} - -restoreFlexRAM(); -_clock_init(); -_sdr_Init(); - -LOAD %L INCREMENTAL // Download - -Setup(); // Setup for Running - -// g, main diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.icf deleted file mode 100644 index f7053b54a9..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.icf +++ /dev/null @@ -1,98 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 1.0, 2018-09-21 -** Build: b180921 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x30002000; -define symbol m_interrupts_end = 0x300023FF; - -define symbol m_text_start = 0x30002400; -define symbol m_text_end = 0x30FBFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2003FFFF; - -define symbol m_data2_start = 0x202C0000; -define symbol m_data2_end = 0x2033FFFF; - -define exported symbol __NCACHE_REGION_START = m_data2_start; -define exported symbol __NCACHE_REGION_SIZE = 0x0; - -define exported symbol m_boot_hdr_conf_start = 0x30000400; -define symbol m_boot_hdr_ivt_start = 0x30001000; -define symbol m_boot_hdr_boot_data_start = 0x30001020; -define symbol m_boot_hdr_dcd_data_start = 0x30001030; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; -define exported symbol __RTT_HEAP_END = m_data2_end; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; - -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.lds deleted file mode 100644 index d21ddb6a79..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.lds +++ /dev/null @@ -1,276 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 - m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - - m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 - - m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 - - m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 - m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 -} - -/* Define output sections */ -SECTIONS -{ - .boot_data : - { - KEEP(*(.boot_hdr.conf)) - } > m_boot_data - - .image_vertor_table : - { - KEEP(*(.boot_hdr.ivt)) - KEEP(*(.boot_hdr.boot_data)) - KEEP(*(.boot_hdr.dcd_data)) - } > m_image_vertor_table - - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* __CTOR_LIST__ = .; */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* __CTOR_END__ = .; */ - PROVIDE(__ctors_end__ = .); - } > m_text - - .dtors : - { - PROVIDE(__dtors_start__ = .); - /* __DTOR_LIST__ = .; */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* __DTOR_END__ = .; */ - PROVIDE(__dtors_end__ = .); - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_dtcm - - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_nocache - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_nocache - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_dtcm - - .stack : - { - . = ALIGN(8); - stack_start = .; - . += STACK_SIZE; - stack_end = .; - __StackTop = .; - } > m_dtcm - - .RTT_HEAP : - { - heap_start = .; - . = ALIGN(8); - } > m_dtcm - - PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); - - .ARM.attributes 0 : { *(.ARM.attributes) } - -} - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.sct deleted file mode 100644 index 938f2a4a05..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/linker_scripts/link.sct +++ /dev/null @@ -1,140 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1176AVM8A_cm7 -** MIMXRT1176CVM8A_cm7 -** MIMXRT1176DVMAA_cm7 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1170RM, Rev E, 12/2019 -** Version: rev. 0.1, 2018-03-05 -** Build: b200828 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#define m_flash_config_start 0x30000400 -#define m_flash_config_size 0x00000C00 - -#define m_ivt_start 0x30001000 -#define m_ivt_size 0x00001000 - -#define m_interrupts_start 0x30002000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x30002400 -#define m_text_size 0x00FFDC00 - -#define m_interrupts_ram_start 0x80000000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x03000000 - m_interrupts_ram_size) - -#define m_ncache_start 0x83000000 -#define m_ncache_size 0x01000000 - -#define m_data2_start 0x20000000 -#define m_data2_size 0x00040000 - -#define m_data3_start 0x202C0000 -#define m_data3_size 0x00080000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif -#include "../../rtconfig.h" -#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region - RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address - * (.boot_hdr.conf, +FIRST) - } - - RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -#else -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region -#endif - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data2 m_data2_start m_data2_size { - * (RamFunction) - } -#if (defined(__heap_noncacheable__)) - RW_m_data m_data_start m_data_size-Stack_Size { ; RW data -#else - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data -#endif - .ANY (+RW +ZI) - *(*m_usb_dma_init_data) - *(*m_usb_dma_noninit_data) - } -#if (!defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } -#endif - ; ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - ; } - ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down - RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} -#if (defined(__heap_noncacheable__)) - RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data -#else - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data -#endif - * (NonCacheable.init) - * (*NonCacheable) - } -#if (defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration -#else - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration -#endif - } -} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/ports/flexspi_port.h b/bsp/imxrt/imxrt1170-nxp-evk/board/ports/flexspi_port.h deleted file mode 100644 index 60514484c9..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/ports/flexspi_port.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-08-15 xjy198903 The first version for rt1170 - */ - -#ifndef FLEXSPI_PORT_H__ -#define FLEXSPI_PORT_H__ - -/* parameters for flexpsi peripheral */ -#define FLEXSPI1_CONTROL_BASE FLEXSPI1 -#define FLEXSPI2_CONTROL_BASE FLEXSPI2 -#define FLEXSPI_ROOT_CLK (80000000U) /* serial root clk: 80MHz*/ -#define FLASH_SIZE (32 * 1024) /* device size 32*1024(KB) = 32MB */ -#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ -#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ -#define AWR_SEQ_NUMBER 1 /* Sequence number for AHB write command */ -#define AWR_SEQ_INDEX 1 /* Sequence ID for AHB write command */ -#define ARD_SEQ_CMD 0xBB /* cmd for read */ -#define AWR_SEQ_CMD 0xAA /* cmd for write */ -#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad -#define FLASH_PORT kFLEXSPI_PortA1 -#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M -#define CLOCK_DIV 5U -#define CUSTOM_LUT_LENGTH 64U -#define FLEXSPI1_AHB_DATA_ADDRESS (0x30000000U) -#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) -#endif /* FLEXSPI_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h deleted file mode 100644 index 9bdb3b617e..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-05 zylx The first version for STM32F4xx - * 2019-4-25 misonyo port to IMXRT - * 2022-08-15 xjy198903 add sdram config for rt1170 - */ - -#ifndef SDRAM_PORT_H__ -#define SDRAM_PORT_H__ - -/* parameters for sdram peripheral */ - -#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) -/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ -#define SDRAM_REGION kSEMC_SDRAM_CS0 -/* CS pin: kSEMC_MUXCSX0/1/2/3 */ -#define SDRAM_CS_PIN kSEMC_MUXCSX0 -/* size(kbyte):64MB = 2*32*1024*1KBytes */ -#if defined(SOC_IMXRT1170_SERIES) -#define SDRAM_SIZE ((uint32_t)(0x10000)) -/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize32Bit */ -#define SDRAM_DATA_WIDTH kSEMC_PortSize32Bit -#else -/* size(kbyte):32MB = 32*1024*1KBytes */ -#define SDRAM_SIZE ((uint32_t)0x8000) -/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ -#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit -#endif -/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ -#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit -/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ -#define SDRAM_CAS_LATENCY kSEMC_LatencyThree - -/* Timing configuration for W9825G6KH */ -/* TRP:precharge to active command time (ns) */ -#define SDRAM_TRP 18 -/* TRCD:active to read/write command delay time (ns) */ -#define SDRAM_TRCD 18 -/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ -#define SDRAM_REFRESH_RECOVERY 67 -/* TWR:write recovery time (ns). */ -#define SDRAM_TWR 12 -/* TRAS:active to precharge command time (ns). */ -#define SDRAM_TRAS 42 -/* TRC time (ns). */ -#define SDRAM_TRC 60 -/* active to active time (ns). */ -#define SDRAM_ACT2ACT 60 -/* refresh time (ns). 64ms */ -#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 - -#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/.config b/bsp/imxrt/imxrt1170-nxp-evk/m7/.config new file mode 100644 index 0000000000..e620c5db30 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/.config @@ -0,0 +1,751 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BSET_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40101 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CPUTIME=y +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PHY=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set +# CONFIG_PKG_USING_BSDIFF_LIB is not set +# CONFIG_PKG_USING_PRC_DIFF is not set + +# +# RT-Thread Smart +# +# CONFIG_PKG_USING_UKERNEL is not set +# CONFIG_PKG_USING_TRACE_AGENT is not set + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_QSPIFLASH=y +CONFIG_SOC_MIMXRT1176DVMAA=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set + +# +# Board extended module Drivers +# diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/Kconfig b/bsp/imxrt/imxrt1170-nxp-evk/m7/Kconfig new file mode 100644 index 0000000000..356193256c --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/Kconfig @@ -0,0 +1,16 @@ +mainmenu "RT-Thread Configuration" + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/m7/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/SConstruct b/bsp/imxrt/imxrt1170-nxp-evk/m7/SConstruct new file mode 100644 index 0000000000..9bd49dff8d --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/SConstruct @@ -0,0 +1,70 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/../libraries'): + libraries_path_prefix = SDK_ROOT + '/../libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1170' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/SConscript new file mode 100644 index 0000000000..050054c59f --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/main.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/main.c new file mode 100644 index 0000000000..e28f0df99a --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 tyustli first version + * + */ + +#include +#include +#include +#include + +#define EXAMPLE_LED_GPIO GPIO9 +#define EXAMPLE_LED_GPIO_PIN (3U) +#define EXAMPLE_LED_GPIO_PORT (3U) +#define LED_PIN GET_PIN(EXAMPLE_LED_GPIO_PORT, EXAMPLE_LED_GPIO_PIN) +int main(void) +{ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + while (1) + { + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + } +} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/mnt.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/mnt.c new file mode 100644 index 0000000000..3b89810de7 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/applications/mnt.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-09-19 Gavin first version + * + */ + +#include +#ifdef RT_USING_DFS_RAMFS +#include + +extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + +int mnt_init(void) +{ + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8*1024*1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + return 0; + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + rt_kprintf("RAM file system initializated!\n"); + else + rt_kprintf("RAM file system initializate failed!\n"); + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + +#ifdef BSP_USING_SDCARD_FATFS +#include +#include +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include +static int filesystem_mount(void) +{ + while(rt_device_find("sd0") == RT_NULL) + { + rt_thread_mdelay(1); + } + + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + rt_kprintf("ret: %d\n",ret); + LOG_E("sd0p0 mount to '/' failed!"); + return ret; + } + + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); +#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/Kconfig b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/Kconfig new file mode 100644 index 0000000000..8a4c96034c --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/Kconfig @@ -0,0 +1,209 @@ +menu "Hardware Drivers Config" + +config BSP_USING_QSPIFLASH + bool + default n + +config SOC_MIMXRT1176DVMAA + bool + select SOC_MIMXRT1170_SERIES + select BSP_USING_QSPIFLASH + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 1 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXCAN1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXCAN2" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1176EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 6 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 12 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + + if BSP_USING_PHY + config PHY_USING_RTL8211F + bool "i.MX RT1176EVK uses rtl8211f phy" + default y + + if PHY_USING_RTL8211F + config PHY_RTL8211F_ADDRESS + int "Specify address of phy device" + default 1 + + config PHY_RESET_RTL8211F_PORT + int "indicate port of reset" + default 5 + + config PHY_RESET_RTL8211F_PIN + int "indicate pin of reset" + default 14 + + endif + endif + endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/MCUX_Config.mex b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/MCUX_Config.mex new file mode 100644 index 0000000000..85d03f1993 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/MCUX_Config.mex @@ -0,0 +1,596 @@ + + + + MIMXRT1176xxxxx + MIMXRT1176DVMAA + ksdk2_0 + + + + + + + + true + false + false + true + false + + + + + 12.0.0 + + + + + Configures pin routing and optionally pin electrical features. + + true + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + 12.0.0 + c_array + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + \ No newline at end of file diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.c new file mode 100644 index 0000000000..2ce144f774 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.c @@ -0,0 +1,884 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v10.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 12.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +/* This function should not run from SDRAM since it will change SEMC configuration. */ +AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void)); +void UpdateSemcClock(void) +{ + /* Enable self-refresh mode and update semc clock root to 200MHz. */ + SEMC->IPCMD = 0xA55A000D; + while ((SEMC->INTR & 0x3) == 0) + ; + SEMC->INTR = 0x3; + SEMC->DCCR = 0x0B; + /* + * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only + * need to change the SEMC clock root here. If customer is using their own DCD and + * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be + * adjusted here to fine tune the SDRAM performance + */ + CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602; +} +#endif +#endif + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 996 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz} +- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz} +- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M4_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M7_CLK_ROOT.outFreq, value: 996 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MQS_MCLK.outFreq, value: 24 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_16M.outFreq, value: 16 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: OSC_RC_48M.outFreq, value: 48 MHz} +- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz} +- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI1_MCLK1.outFreq, value: 24 MHz} +- {id: SAI1_MCLK3.outFreq, value: 24 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI2_MCLK1.outFreq, value: 24 MHz} +- {id: SAI2_MCLK3.outFreq, value: 24 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI3_MCLK1.outFreq, value: 24 MHz} +- {id: SAI3_MCLK3.outFreq, value: 24 MHz} +- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI4_MCLK1.outFreq, value: 24 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz} +- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz} +settings: +- {id: CoreBusClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'} +- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'} +- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'} +- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ + +#ifndef SKIP_POWER_ADJUSTMENT +#if __CORTEX_M == 7 +#define BYPASS_LDO_LPSR 1 +#define SKIP_LDO_ADJUSTMENT 1 +#elif __CORTEX_M == 4 +#define SKIP_DCDC_ADJUSTMENT 1 +#define SKIP_FBB_ENABLE 1 +#endif +#endif + +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = + { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ + .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ + .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */ + DCDC_BootIntoDCM(DCDC); + +#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT) + if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU)) + { + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); + } + else + { + /* Set 1.125V for production samples to align with data sheet requirement */ + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V); + } +#endif + +#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) + /* Check if FBB need to be enabled in OverDrive(OD) mode */ + if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); + } + else + { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); + } +#endif + +#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR + PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); + PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); +#endif + +#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT) + pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; + pmu_static_lpsr_dig_config_t lpsrDigConfig; + + if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) + { + PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); + PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); + } + + if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) + { + PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); + lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; + PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); + } +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 16M */ + ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + CLOCK_OSC_GateOscRc400M(true); + + /* Init OSC RC 48M */ + CLOCK_OSC_EnableOsc48M(true); + CLOCK_OSC_EnableOsc48MDiv2(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ +#if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + +#if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* + * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code. + */ + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Bypass Sys Pll1. */ + CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + + /* DeInit Sys Pll1. */ + CLOCK_DeinitSysPll1(); + + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); + + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); + + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); + + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); + + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); + + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Init Video Pll. */ + CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M4 using SYS_PLL3_CLK */ +#if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + + /* Configure BUS using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); + + /* Configure BUS_LPSR using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); + + /* Configure SEMC using SYS_PLL2_PFD1_CLK */ +#ifndef SKIP_SEMC_INIT + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + UpdateSemcClock(); +#endif +#endif + + /* Configure CSSYS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); + + /* Configure CSTRACE using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); + + /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ +#if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ +#if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure ADC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure GPT1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure GPT3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg); + + /* Configure GPT4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg); + + /* Configure GPT5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg); + + /* Configure GPT6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg); + + /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE)) + rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); +#endif + + /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg); + + /* Configure CAN1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART1 using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); + + /* Configure LPUART2 using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); + + /* Configure LPUART3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg); + + /* Configure LPUART4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg); + + /* Configure LPUART5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg); + + /* Configure LPUART6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg); + + /* Configure LPUART7 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg); + + /* Configure LPUART8 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg); + + /* Configure LPUART9 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg); + + /* Configure LPUART10 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg); + + /* Configure LPUART11 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg); + + /* Configure LPUART12 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg); + + /* Configure LPI2C1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + + /* Configure LPI2C2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg); + + /* Configure LPI2C3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg); + + /* Configure LPI2C4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg); + + /* Configure LPI2C5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); + + /* Configure LPI2C6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg); + + /* Configure LPSPI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); + + /* Configure LPSPI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg); + + /* Configure LPSPI3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg); + + /* Configure LPSPI4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg); + + /* Configure LPSPI5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg); + + /* Configure LPSPI6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg); + + /* Configure EMV1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg); + + /* Configure EMV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg); + + /* Configure ENET1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); + + /* Configure ENET2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); + + /* Configure ENET_QOS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg); + + /* Configure ENET_25M using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg); + + /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); + + /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg); + + /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg); + + /* Configure USDHC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure ASRC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MQS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg); + + /* Configure MIC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure SPDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure SAI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure GC355 using PLL_VIDEO_CLK */ + rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg); + + /* Configure LCDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); + + /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg); + + /* Configure MIPI_REF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg); + + /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg); + + /* Configure CSI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg); + + /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg); + + /* Configure CSI2_UI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg); + + /* Configure CSI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg); + + /* Configure CKO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; + /* Set ENET_1G Tx clock source. */ + IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK); + /* Set ENET_1G Ref clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; + /* Set ENET_QOS Tx clock source. */ + IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK; + /* Set ENET_QOS Ref clock source. */ + IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK; + /* Set GPT3 High frequency reference clock source. */ + IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK; + /* Set GPT4 High frequency reference clock source. */ + IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK; + /* Set GPT5 High frequency reference clock source. */ + IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK; + /* Set GPT6 High frequency reference clock source. */ + IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK; + +#if __CORTEX_M == 7 + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4); +#endif +} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.h new file mode 100644 index 0000000000..26d3652314 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/clock_config.h @@ -0,0 +1,203 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL +#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 240000000UL +#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.c new file mode 100644 index 0000000000..7008424305 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.c @@ -0,0 +1,127 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 0.9.6 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, + open_drain: Disable, drive_strength: High, slew_rate: Slow} + - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, + open_drain: Disable, drive_strength: High, slew_rate: Slow} + - {pin_num: D6, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_DISP_B2_07, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, + open_drain: Disable, drive_strength: High, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ + + /* GPIO configuration on GPIO_AD_04 (pin M13) */ + gpio_pin_config_t gpio9_pinM13_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */ + GPIO_PinInit(GPIO9, 3U, &gpio9_pinM13_config); + + /* GPIO configuration on GPIO_AD_26 (pin L14) */ + gpio_pin_config_t gpio9_pinL14_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_04 (pin L14) */ + GPIO_PinInit(GPIO9, 25U, &gpio9_pinL14_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */ + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_26_GPIO9_IO25, /* GPIO_AD_04 is configured as GPIO9_IO03 */ + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 is configured as ARM_TRACE_SWO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.h new file mode 100644 index 0000000000..5341111961 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/MCUX_Config/pin_mux.h @@ -0,0 +1,52 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/SConscript new file mode 100644 index 0000000000..6d2f0c49d3 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +dcd.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1176DVMAA_cm7', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1','ARM_MATH_CM7','USE_SDRAM','SOC_IMXRT1170_SERIES'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.c new file mode 100644 index 0000000000..a9dc521eb4 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.c @@ -0,0 +1,1366 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2022-08-15 xjy198903 add sdram pin config + * 2022-08-17 xjy198903 add rgmii pins + * 2022-09-01 xjy198903 add can pins + * 2022-09-07 xjy198903 add sdio pins + * 2022-09-14 xjy198903 add flexspi pins + */ + +#include +#include +#include "board.h" +#include "pin_mux.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" + +#ifdef BSP_USING_DMA +#include "fsl_dmamux.h" +#include "fsl_edma.h" +#endif + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? + 0 : + ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); +#elif defined(__MCUXPRESSO) +#if defined(__USE_SHMEM) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem); + uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart; +#else + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#endif +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; +#endif + volatile uint32_t i = 0; + +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } +#endif +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + } +#endif + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); +#endif + +#ifdef USE_SDRAM + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif + + while ((size >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + SCB_EnableDCache(); +#endif +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + SCB_EnableICache(); +#endif +} + + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +#ifdef BSP_USING_LPUART +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +#endif +#ifdef BSP_USING_LPUART2 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0x10B0u); + +#endif +#ifdef BSP_USING_LPUART3 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART4 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART5 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART6 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART7 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART8 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0x10B0u); +#endif +} +#endif /* BSP_USING_LPUART */ +#ifdef BSP_USING_SDIO +void imxrt_SDcard_pins_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_34_USDHC1_VSELECT, /* GPIO_AD_34 is configured as USDHC1_VSELECT */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_35_GPIO10_IO02, /* GPIO_AD_35 is configured as GPIO10_IO02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, /* GPIO_SD_B1_00 is configured as USDHC1_CMD */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_00 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, /* GPIO_SD_B1_01 is configured as USDHC1_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_01 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, /* GPIO_SD_B1_02 is configured as USDHC1_DATA0 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_02 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, /* GPIO_SD_B1_03 is configured as USDHC1_DATA1 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_03 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, /* GPIO_SD_B1_04 is configured as USDHC1_DATA2 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_04 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, /* GPIO_SD_B1_05 is configured as USDHC1_DATA3 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_SD_B1_05 */ + IOMUXC_GPR->GPR43 = ((IOMUXC_GPR->GPR43 & + (~(IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK))) /* Mask bits to zero which are setting */ + | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(0x8000U) /* GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function: 0x8000U */ + ); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, /* GPIO_SD_B1_00 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, /* GPIO_SD_B1_01 PAD functional properties : */ + 0x0CU); /* PDRV Field: high drive strength + Pull Down Pull Up Field: No Pull + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, /* GPIO_SD_B1_02 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, /* GPIO_SD_B1_03 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, /* GPIO_SD_B1_04 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, /* GPIO_SD_B1_05 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} +#endif +#ifdef BSP_USING_ETH +void imxrt_eth_pins_init(void) { +#ifdef PHY_USING_RTL8211F + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, /* GPIO_DISP_B1_00 is configured as ENET_1G_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, /* GPIO_DISP_B1_01 is configured as ENET_1G_RX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, /* GPIO_DISP_B1_02 is configured as ENET_1G_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, /* GPIO_DISP_B1_03 is configured as ENET_1G_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, /* GPIO_DISP_B1_04 is configured as ENET_1G_RX_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, /* GPIO_DISP_B1_05 is configured as ENET_1G_RX_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, /* GPIO_DISP_B1_06 is configured as ENET_1G_TX_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, /* GPIO_DISP_B1_07 is configured as ENET_1G_TX_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, /* GPIO_DISP_B1_08 is configured as ENET_1G_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, /* GPIO_DISP_B1_09 is configured as ENET_1G_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, /* GPIO_DISP_B1_10 is configured as ENET_1G_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, /* GPIO_DISP_B1_11 is configured as ENET_1G_TX_CLK_IO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13, /* GPIO_DISP_B2_12 is configured as GPIO_MUX5_IO13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14, /* GPIO_DISP_B2_13 is configured as GPIO_MUX5_IO14 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, /* GPIO_EMC_B2_19 is configured as ENET_1G_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, /* GPIO_EMC_B2_20 is configured as ENET_1G_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +#else + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_12_GPIO9_IO11, /* GPIO_AD_12 is configured as GPIO9_IO11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_32_ENET_MDC, /* GPIO_AD_32 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_33_ENET_MDIO, /* GPIO_AD_33 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, /* GPIO_DISP_B2_02 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, /* GPIO_DISP_B2_03 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, /* GPIO_DISP_B2_04 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, /* GPIO_DISP_B2_05 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_05 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, /* GPIO_DISP_B2_06 is configured as ENET_RX_DATA00 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_06 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, /* GPIO_DISP_B2_07 is configured as ENET_RX_DATA01 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_DISP_B2_07 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, /* GPIO_DISP_B2_08 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, /* GPIO_DISP_B2_09 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPR->GPR4 = ((IOMUXC_GPR->GPR4 & + (~(IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK))) /* Mask bits to zero which are setting */ + | IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) /* ENET_REF_CLK direction control: 0x01U */ + ); + IOMUXC_SetPinMux( + IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12, /* GPIO_LPSR_12 is configured as GPIO12_IO12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_12_GPIO9_IO11, /* GPIO_AD_12 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, /* GPIO_DISP_B2_02 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, /* GPIO_DISP_B2_03 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, /* GPIO_DISP_B2_04 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, /* GPIO_DISP_B2_05 PAD functional properties : */ + 0x03U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, /* GPIO_DISP_B2_06 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, /* GPIO_DISP_B2_07 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, /* GPIO_DISP_B2_08 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, /* GPIO_DISP_B2_09 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12, /* GPIO_LPSR_12 PAD functional properties : */ + 0x0EU); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain LPSR Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + +#endif +} +#endif + +#ifdef BSP_USING_SDRAM +void imxrt_sdram_pins_init(void) +{ + // SEMC + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 is configured as SEMC_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 is configured as SEMC_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 is configured as SEMC_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 is configured as SEMC_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 is configured as SEMC_DATA04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 is configured as SEMC_DATA05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 is configured as SEMC_DATA06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 is configured as SEMC_DATA07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 is configured as SEMC_DM00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 is configured as SEMC_ADDR00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 is configured as SEMC_ADDR01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 is configured as SEMC_ADDR02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 is configured as SEMC_ADDR03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 is configured as SEMC_ADDR04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 is configured as SEMC_ADDR05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 is configured as SEMC_ADDR06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 is configured as SEMC_ADDR07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 is configured as SEMC_ADDR08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 is configured as SEMC_ADDR09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 is configured as SEMC_ADDR11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 is configured as SEMC_ADDR12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 is configured as SEMC_BA0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 is configured as SEMC_BA1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 is configured as SEMC_ADDR10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 is configured as SEMC_CAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 is configured as SEMC_RAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 is configured as SEMC_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 is configured as SEMC_CKE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 is configured as SEMC_WE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 is configured as SEMC_CS0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 is configured as SEMC_DATA08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 is configured as SEMC_DATA09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 is configured as SEMC_DATA10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 is configured as SEMC_DATA11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 is configured as SEMC_DATA12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 is configured as SEMC_DATA13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 is configured as SEMC_DATA14 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 is configured as SEMC_DATA15 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 is configured as SEMC_DM01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 is configured as SEMC_DQS */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B1_39 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 is configured as SEMC_RDY */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 is configured as SEMC_CSX00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 is configured as SEMC_DATA16 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 is configured as SEMC_DATA17 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 is configured as SEMC_DATA18 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 is configured as SEMC_DATA19 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 is configured as SEMC_DATA20 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 is configured as SEMC_DATA21 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 is configured as SEMC_DATA22 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 is configured as SEMC_DATA23 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 is configured as SEMC_DM02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 is configured as SEMC_DATA24 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 is configured as SEMC_DATA25 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 is configured as SEMC_DATA26 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 is configured as SEMC_DATA27 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 is configured as SEMC_DATA28 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 is configured as SEMC_DATA29 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 is configured as SEMC_DATA30 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 is configured as SEMC_DATA31 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 is configured as SEMC_DM03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 is configured as SEMC_DQS4 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00, /* GPIO_EMC_B1_00 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01, /* GPIO_EMC_B1_01 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02, /* GPIO_EMC_B1_02 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03, /* GPIO_EMC_B1_03 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04, /* GPIO_EMC_B1_04 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05, /* GPIO_EMC_B1_05 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06, /* GPIO_EMC_B1_06 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07, /* GPIO_EMC_B1_07 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00, /* GPIO_EMC_B1_08 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00, /* GPIO_EMC_B1_09 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01, /* GPIO_EMC_B1_10 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02, /* GPIO_EMC_B1_11 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03, /* GPIO_EMC_B1_12 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04, /* GPIO_EMC_B1_13 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05, /* GPIO_EMC_B1_14 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06, /* GPIO_EMC_B1_15 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07, /* GPIO_EMC_B1_16 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08, /* GPIO_EMC_B1_17 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09, /* GPIO_EMC_B1_18 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11, /* GPIO_EMC_B1_19 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12, /* GPIO_EMC_B1_20 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_21_SEMC_BA0, /* GPIO_EMC_B1_21 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_22_SEMC_BA1, /* GPIO_EMC_B1_22 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10, /* GPIO_EMC_B1_23 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_24_SEMC_CAS, /* GPIO_EMC_B1_24 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_25_SEMC_RAS, /* GPIO_EMC_B1_25 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_26_SEMC_CLK, /* GPIO_EMC_B1_26 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_27_SEMC_CKE, /* GPIO_EMC_B1_27 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_28_SEMC_WE, /* GPIO_EMC_B1_28 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_29_SEMC_CS0, /* GPIO_EMC_B1_29 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08, /* GPIO_EMC_B1_30 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09, /* GPIO_EMC_B1_31 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10, /* GPIO_EMC_B1_32 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11, /* GPIO_EMC_B1_33 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12, /* GPIO_EMC_B1_34 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13, /* GPIO_EMC_B1_35 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14, /* GPIO_EMC_B1_36 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15, /* GPIO_EMC_B1_37 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_38_SEMC_DM01, /* GPIO_EMC_B1_38 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_39_SEMC_DQS, /* GPIO_EMC_B1_39 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_40_SEMC_RDY, /* GPIO_EMC_B1_40 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00, /* GPIO_EMC_B1_41 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16, /* GPIO_EMC_B2_00 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17, /* GPIO_EMC_B2_01 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18, /* GPIO_EMC_B2_02 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19, /* GPIO_EMC_B2_03 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20, /* GPIO_EMC_B2_04 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21, /* GPIO_EMC_B2_05 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22, /* GPIO_EMC_B2_06 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23, /* GPIO_EMC_B2_07 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_08_SEMC_DM02, /* GPIO_EMC_B2_08 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24, /* GPIO_EMC_B2_09 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25, /* GPIO_EMC_B2_10 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26, /* GPIO_EMC_B2_11 PAD functional properties : */ + 0x04U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pullup resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27, /* GPIO_EMC_B2_12 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28, /* GPIO_EMC_B2_13 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29, /* GPIO_EMC_B2_14 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30, /* GPIO_EMC_B2_15 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31, /* GPIO_EMC_B2_16 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_17_SEMC_DM03, /* GPIO_EMC_B2_17 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4, /* GPIO_EMC_B2_18 PAD functional properties : */ + 0x08U); /* PDRV Field: high drive strength + Pull Down Pull Up Field: Internal pulldown resistor enabled + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} +#endif + +#ifdef BSP_USING_CAN +void imxrt_can_pins_init(void) +{ +#ifdef BSP_USING_CAN3 + CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX, /* GPIO_LPSR_00 is configured as FLEXCAN3_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX, /* GPIO_LPSR_01 is configured as FLEXCAN3_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +#endif +} +#endif + +#ifdef BSP_USING_FLEXSPI +void imxrt_flexspi_pins_init(void) +{ +#ifdef BSP_USING_FLEXSPI1 + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03, /* GPIO_SD_B2_00 is configured as FLEXSPI1_B_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02, /* GPIO_SD_B2_01 is configured as FLEXSPI1_B_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01, /* GPIO_SD_B2_02 is configured as FLEXSPI1_B_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00, /* GPIO_SD_B2_03 is configured as FLEXSPI1_B_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, /* GPIO_SD_B2_05 is configured as FLEXSPI1_A_DQS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, /* GPIO_SD_B2_06 is configured as FLEXSPI1_A_SS0_B */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, /* GPIO_SD_B2_07 is configured as FLEXSPI1_A_SCLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, /* GPIO_SD_B2_08 is configured as FLEXSPI1_A_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, /* GPIO_SD_B2_09 is configured as FLEXSPI1_A_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, /* GPIO_SD_B2_10 is configured as FLEXSPI1_A_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, /* GPIO_SD_B2_11 is configured as FLEXSPI1_A_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + +#endif +} +#endif + +void rt_hw_board_init() +{ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef BSP_USING_LPUART + imxrt_uart_pins_init(); +#endif + +#ifdef BSP_USING_SDRAM + imxrt_sdram_pins_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDIO + imxrt_SDcard_pins_init(); +#endif + +#ifdef BSP_USING_ETH + imxrt_eth_pins_init(); +#endif + +#ifdef BSP_USING_CAN + imxrt_can_pins_init(); +#endif + +#ifdef BSP_USING_FLEXSPI + imxrt_flexspi_pins_init(); +#endif +} + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.h new file mode 100644 index 0000000000..e49af960a1 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/board.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "fsl_common.h" +#include "clock_config.h" + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +/*! @brief The board flash size */ +#define BOARD_FLASH_SIZE (0x1000000U) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.c new file mode 100644 index 0000000000..b7e60a294b --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.c @@ -0,0 +1,401 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx v3.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 12.0.0 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x05, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-139, command header bytes for merged 'Write - value' command */ + 0xCC, 0x04, 0x5C, 0x04, + /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */ + 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02, + /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, + /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4 */ + 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, + /* #1.54, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, + /* #1.55, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, + /* #1.56, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, + /* #1.57, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, + /* #1.58, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, + /* #1.59, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, + /* #1.60, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, + /* #1.61, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, + /* #1.62, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, + /* #1.63, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x04, 0x00, 0x00, 0x00, 0x00, + /* #1.64, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x08, 0x00, 0x00, 0x00, 0x00, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, + /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, + /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, + /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, + /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, + /* #1.95, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, + /* #1.96, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, + /* #1.97, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, + /* #1.98, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, + /* #1.99, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, + /* #1.100, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, + /* #1.101, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, + /* #1.102, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, + /* #1.103, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, + /* #1.104, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, + /* #1.105, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF4, 0x00, 0x00, 0x00, 0x08, + /* #1.106, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF8, 0x00, 0x00, 0x00, 0x08, + /* #1.107, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, + /* #1.108, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.109, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.110, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.111, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.112, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, + /* #1.113, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, + /* #1.114, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, + /* #1.115, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, + /* #1.116, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, + /* #1.117, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, + /* #1.118, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, + /* #1.119, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, + /* #1.120, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, + /* #1.121, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, + /* #1.122, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, + /* #1.123, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, + /* #1.124, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.125, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.126, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.127, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.128, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.129, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.130, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.131, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4 */ + 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, + /* #1.132, command: write_value, address: SEMC_SDRAMCR0, value: 0xF32, size: 4 */ + 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, + /* #1.133, command: write_value, address: SEMC_SDRAMCR1, value: 0x772A22, size: 4 */ + 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, + /* #1.134, command: write_value, address: SEMC_SDRAMCR2, value: 0x10A0D, size: 4 */ + 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, + /* #1.135, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, + /* #1.136, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.137, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.138, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.139, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #3, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #4, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #5, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #6, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #9, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #10, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #11, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #12, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #13.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #14, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #15, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #16, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #17, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #18, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #19.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #20, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #21, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #22, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #23, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #24, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #25, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #26, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #27, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.h new file mode 100644 index 0000000000..77de9fa8b6 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini new file mode 100644 index 0000000000..c39b5460c8 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini @@ -0,0 +1,377 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void restoreFlexRAM(void) +{ + unsigned int value; + + value = _RDWORD(0x400E4044); + value &= ~(0xFFFF); + value |= 0xFFAA; + _WDWORD(0x400E4044, value); + + value = _RDWORD(0x400E4048); + value &= ~(0xFFFF); + value |= 0xFFAA; + _WDWORD(0x400E4048, value); + + value = _RDWORD(0x400E4040); + value &= ~(0xFF << 8); + value |= 0x7 | (0xAA << 8); + _WDWORD(0x400E4040, value); +} + +FUNC void SDRAM_WaitIpCmdDone(void) +{ + unsigned long reg; + do + { + reg = _RDWORD(0x400D403C); + }while((reg & 0x3) == 0); + + _WDWORD(0x400D403C,0x00000003); // clear IPCMDERR and IPCMDDONE bits +} + +FUNC void EnableOSC400M(void) +{ + unsigned int reg; + // CTRL1: power down + reg = _RDWORD(0x40C84050); + reg &= ~0x1; + _WDWORD(0x40C84050,reg); + // CTRL2: enable clock + reg = _RDWORD(0x40C84060); + reg |= 0x1; + _WDWORD(0x40C84060,reg); +} + +FUNC void EnableOSC24M(void) +{ + unsigned int reg; + reg = _RDWORD(0x40C84020); + if(0 == (reg & 0x10)) + { + reg = 0x14; // OSC_EN and LP_EN + _WDWORD(0x40C84020,reg); + reg = _RDWORD(0x40C84020); + while (0 == (reg & 0x80000000)); + } +} + +FUNC void EnablePllLdo(void) +{ + unsigned int reg; + // CTRL_AI_CTRL + _WDWORD(0x40C84820,0x00000000); + // CTRL_AI_WDATA + _WDWORD(0x40C84830,0x00000105); + // PMU_LDO_PLL + reg = _RDWORD(0x40C84500); + reg |= 0x10000; + _WDWORD(0x40C84500,reg); + _Sleep_(100); + + // PMU_POWER_DETECT_CTRL + _WDWORD(0x40C84580,0x00000100); + _Sleep_(1); + // PMU_REF_CTRL + _WDWORD(0x40C84570,0x00000010); +} + +FUNC void InitSysPll2Pfd1(void) +{ + unsigned int reg; + unsigned int stable; + // ANADIG_PLL_PLL_528_PFD + reg = _RDWORD(0x40C84270); + if (((reg & 0x8000) != 0) || (((reg & 0x3F00) >> 8) != 16)) + { + stable = reg & 0x4000; + + reg |= 0x8000; + _WDWORD(0x40C84270,reg); + + reg = _RDWORD(0x40C84270); + reg &= ~0x3F00; + reg |= 16 << 8; + _WDWORD(0x40C84270,reg); + + reg = _RDWORD(0x40C84250); + reg ^= 0x4; + _WDWORD(0x40C84250,reg); + + reg = _RDWORD(0x40C84270); + reg &= ~0x8000; + _WDWORD(0x40C84270,reg); + do + { + reg = _RDWORD(0x40C84270) & 0x4000; + } while (reg == stable); + } + else + { + //syspll2 pfd1 has been initialized already + reg &= ~0x8000; + _WDWORD(0x40C84270,reg); + } +} + +FUNC void InitSysPll2(void) +{ + unsigned int reg; + + // ANADIG_PLL_PLL_528_CTRL + reg = _RDWORD(0x40C84240); + if (reg & 0x800000) + { + // SysPll2 has been initialized + reg &= ~0x40000000; + _WDWORD(0x40C84240, reg); + return; + } + + reg = _RDWORD(0x40C84270); + reg |= 0x80808080; + _WDWORD(0x40C84270, reg); + + reg = _RDWORD(0x40C84240); + reg &= ~(0x802000); + reg |= 0x40000000; + _WDWORD(0x40C84240, reg); + + // ANADIG_PLL_PLL_528_MFN + _WDWORD(0x40C84280, 0); + // ANADIG_PLL_PLL_528_MFI + _WDWORD(0x40C84290, 22); + // ANADIG_PLL_PLL_528_MFD + _WDWORD(0x40C842A0, 0x0FFFFFFF); + + // ANADIG_PLL_PLL_528_CTRL + _WDWORD(0x40C84240, 0x8 | 0x40000000); + _Sleep_(30); + + // ANADIG_PLL_PLL_528_CTRL + reg = _RDWORD(0x40C84240); + reg |= 0x800000 | 0x800; + _WDWORD(0x40C84240, reg); + _Sleep_(250); + + reg = _RDWORD(0x40C84240); + reg &= ~0x800; + _WDWORD(0x40C84240, reg); + + do + { + reg = _RDWORD(0x40C84240); + } while ((reg & 0x20000000) == 0); + + reg |= 0x2000; + _WDWORD(0x40C84240, reg); + + reg &= ~0x40000000; + _WDWORD(0x40C84240, reg); +} + +FUNC void SetSemcClock(void) +{ + //EnableOSC400M(); + EnablePllLdo(); + InitSysPll2(); + InitSysPll2Pfd1(); + + // Set SEMC root clock + // Use sys pll2 pfd1 divided by 3: 198Mhz + _WDWORD(0x40CC0200,0x00000602); +} + +FUNC void _clock_init(void) +{ + SetSemcClock(); +} + +FUNC void _sdr_Init(void) +{ + // Config IOMUX + _WDWORD(0x400E8010, 0x00000000); + _WDWORD(0x400E8014, 0x00000000); + _WDWORD(0x400E8018, 0x00000000); + _WDWORD(0x400E801C, 0x00000000); + _WDWORD(0x400E8020, 0x00000000); + _WDWORD(0x400E8024, 0x00000000); + _WDWORD(0x400E8028, 0x00000000); + _WDWORD(0x400E802C, 0x00000000); + _WDWORD(0x400E8030, 0x00000000); + _WDWORD(0x400E8034, 0x00000000); + _WDWORD(0x400E8038, 0x00000000); + _WDWORD(0x400E803C, 0x00000000); + _WDWORD(0x400E8040, 0x00000000); + _WDWORD(0x400E8044, 0x00000000); + _WDWORD(0x400E8048, 0x00000000); + _WDWORD(0x400E804C, 0x00000000); + _WDWORD(0x400E8050, 0x00000000); + _WDWORD(0x400E8054, 0x00000000); + _WDWORD(0x400E8058, 0x00000000); + _WDWORD(0x400E805C, 0x00000000); + _WDWORD(0x400E8060, 0x00000000); + _WDWORD(0x400E8064, 0x00000000); + _WDWORD(0x400E8068, 0x00000000); + _WDWORD(0x400E806C, 0x00000000); + _WDWORD(0x400E8070, 0x00000000); + _WDWORD(0x400E8074, 0x00000000); + _WDWORD(0x400E8078, 0x00000000); + _WDWORD(0x400E807C, 0x00000000); + _WDWORD(0x400E8080, 0x00000000); + _WDWORD(0x400E8084, 0x00000000); + _WDWORD(0x400E8088, 0x00000000); + _WDWORD(0x400E808C, 0x00000000); + _WDWORD(0x400E8090, 0x00000000); + _WDWORD(0x400E8094, 0x00000000); + _WDWORD(0x400E8098, 0x00000000); + _WDWORD(0x400E809C, 0x00000000); + _WDWORD(0x400E80A0, 0x00000000); + _WDWORD(0x400E80A4, 0x00000000); + _WDWORD(0x400E80A8, 0x00000000); + _WDWORD(0x400E80AC, 0x00000010); // EMC_39, DQS PIN, enable SION + _WDWORD(0x400E80B0, 0x00000000); + _WDWORD(0x400E80B4, 0x00000000); + _WDWORD(0x400E80B8, 0x00000000); + _WDWORD(0x400E80BC, 0x00000000); + _WDWORD(0x400E80C0, 0x00000000); + _WDWORD(0x400E80C4, 0x00000000); + _WDWORD(0x400E80C8, 0x00000000); + _WDWORD(0x400E80CC, 0x00000000); + _WDWORD(0x400E80D0, 0x00000000); + _WDWORD(0x400E80D4, 0x00000000); + _WDWORD(0x400E80D8, 0x00000000); + _WDWORD(0x400E80DC, 0x00000000); + _WDWORD(0x400E80E0, 0x00000000); + _WDWORD(0x400E80E4, 0x00000000); + _WDWORD(0x400E80E8, 0x00000000); + _WDWORD(0x400E80EC, 0x00000000); + _WDWORD(0x400E80F0, 0x00000000); + _WDWORD(0x400E80F4, 0x00000000); + _WDWORD(0x400E80F8, 0x00000000); + _WDWORD(0x400E80FC, 0x00000000); + _WDWORD(0x400E8100, 0x00000000); + _WDWORD(0x400E8104, 0x00000000); + _WDWORD(0x400E8108, 0x00000000); + + // PAD ctrl + // PDRV = 1b (normal); PULL = 10b (PD) + _WDWORD(0x400E8254, 0x00000008); + _WDWORD(0x400E8258, 0x00000008); + _WDWORD(0x400E825C, 0x00000008); + _WDWORD(0x400E8260, 0x00000008); + _WDWORD(0x400E8264, 0x00000008); + _WDWORD(0x400E8268, 0x00000008); + _WDWORD(0x400E826C, 0x00000008); + _WDWORD(0x400E8270, 0x00000008); + _WDWORD(0x400E8274, 0x00000008); + _WDWORD(0x400E8278, 0x00000008); + _WDWORD(0x400E827C, 0x00000008); + _WDWORD(0x400E8280, 0x00000008); + _WDWORD(0x400E8284, 0x00000008); + _WDWORD(0x400E8288, 0x00000008); + _WDWORD(0x400E828C, 0x00000008); + _WDWORD(0x400E8290, 0x00000008); + _WDWORD(0x400E8294, 0x00000008); + _WDWORD(0x400E8298, 0x00000008); + _WDWORD(0x400E829C, 0x00000008); + _WDWORD(0x400E82A0, 0x00000008); + _WDWORD(0x400E82A4, 0x00000008); + _WDWORD(0x400E82A8, 0x00000008); + _WDWORD(0x400E82AC, 0x00000008); + _WDWORD(0x400E82B0, 0x00000008); + _WDWORD(0x400E82B4, 0x00000008); + _WDWORD(0x400E82B8, 0x00000008); + _WDWORD(0x400E82BC, 0x00000008); + _WDWORD(0x400E82C0, 0x00000008); + _WDWORD(0x400E82C4, 0x00000008); + _WDWORD(0x400E82C8, 0x00000008); + _WDWORD(0x400E82CC, 0x00000008); + _WDWORD(0x400E82D0, 0x00000008); + _WDWORD(0x400E82D4, 0x00000008); + _WDWORD(0x400E82D8, 0x00000008); + _WDWORD(0x400E82DC, 0x00000008); + _WDWORD(0x400E82E0, 0x00000008); + _WDWORD(0x400E82E4, 0x00000008); + _WDWORD(0x400E82E8, 0x00000008); + _WDWORD(0x400E82EC, 0x00000008); + _WDWORD(0x400E82F0, 0x00000008); + _WDWORD(0x400E82F4, 0x00000008); + _WDWORD(0x400E82F8, 0x00000008); + _WDWORD(0x400E82FC, 0x00000008); + _WDWORD(0x400E8300, 0x00000008); + _WDWORD(0x400E8304, 0x00000008); + _WDWORD(0x400E8308, 0x00000008); + _WDWORD(0x400E830C, 0x00000008); + _WDWORD(0x400E8310, 0x00000008); + _WDWORD(0x400E8314, 0x00000008); + _WDWORD(0x400E8318, 0x00000008); + _WDWORD(0x400E831C, 0x00000008); + _WDWORD(0x400E8320, 0x00000008); + _WDWORD(0x400E8324, 0x00000008); + _WDWORD(0x400E8328, 0x00000008); + _WDWORD(0x400E832C, 0x00000008); + _WDWORD(0x400E8330, 0x00000008); + _WDWORD(0x400E8334, 0x00000008); + _WDWORD(0x400E8338, 0x00000008); + _WDWORD(0x400E833C, 0x00000008); + _WDWORD(0x400E8400, 0x00000008); + _WDWORD(0x400E8404, 0x00000008); + _WDWORD(0x400E8408, 0x00000008); + _WDWORD(0x400E840C, 0x00000008); + + // Config SDR Controller Registers/ + _WDWORD(0x400d4000,0x10000004); // MCR + _WDWORD(0x400d4008,0x00000081); // BMCR0 + _WDWORD(0x400d400C,0x00000081); // BMCR1 + _WDWORD(0x400d4010,0x8000001D); // BR0, 64MB + + _WDWORD(0x400d4040,0x00000F32); // SDRAMCR0, 32bit + _WDWORD(0x400d4044,0x00772A22); // SDRAMCR1 + _WDWORD(0x400d4048,0x00010A0D); // SDRAMCR2 + _WDWORD(0x400d404C,0x21210408); // SDRAMCR3 + + _WDWORD(0x400d4090,0x80000000); // IPCR0 + _WDWORD(0x400d4094,0x00000002); // IPCR1 + _WDWORD(0x400d4098,0x00000000); // IPCR2 + + + _WDWORD(0x400d409C,0xA55A000F); // IPCMD, SD_CC_IPREA + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d40A0,0x00000033); // IPTXDAT + _WDWORD(0x400d409C,0xA55A000A); // SD_CC_IMS + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d404C,0x21210409 ); // enable sdram self refresh again after initialization done. +} + +FUNC void Setup (void) { + SP = _RDWORD(0x30002000); // Setup Stack Pointer + PC = _RDWORD(0x30002004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x30002000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + _clock_init(); + _sdr_Init(); + Setup(); // Setup for Running +} + +restoreFlexRAM(); +_clock_init(); +_sdr_Init(); + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.icf new file mode 100644 index 0000000000..f7053b54a9 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.icf @@ -0,0 +1,98 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x30002000; +define symbol m_interrupts_end = 0x300023FF; + +define symbol m_text_start = 0x30002400; +define symbol m_text_end = 0x30FBFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2003FFFF; + +define symbol m_data2_start = 0x202C0000; +define symbol m_data2_end = 0x2033FFFF; + +define exported symbol __NCACHE_REGION_START = m_data2_start; +define exported symbol __NCACHE_REGION_SIZE = 0x0; + +define exported symbol m_boot_hdr_conf_start = 0x30000400; +define symbol m_boot_hdr_ivt_start = 0x30001000; +define symbol m_boot_hdr_boot_data_start = 0x30001020; +define symbol m_boot_hdr_dcd_data_start = 0x30001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_data2_end; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.lds new file mode 100644 index 0000000000..d21ddb6a79 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.lds @@ -0,0 +1,276 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.sct new file mode 100644 index 0000000000..938f2a4a05 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/linker_scripts/link.sct @@ -0,0 +1,140 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1176AVM8A_cm7 +** MIMXRT1176CVM8A_cm7 +** MIMXRT1176DVMAA_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1170RM, Rev E, 12/2019 +** Version: rev. 0.1, 2018-03-05 +** Build: b200828 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_flash_config_start 0x30000400 +#define m_flash_config_size 0x00000C00 + +#define m_ivt_start 0x30001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x30002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x30002400 +#define m_text_size 0x00FFDC00 + +#define m_interrupts_ram_start 0x80000000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x03000000 - m_interrupts_ram_size) + +#define m_ncache_start 0x83000000 +#define m_ncache_size 0x01000000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00040000 + +#define m_data3_start 0x202C0000 +#define m_data3_size 0x00080000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif +#include "../../rtconfig.h" +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +#else +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region +#endif + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } +#if (defined(__ram_vector_table__)) + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +#else + VECTOR_RAM m_interrupts_start EMPTY 0 { + } +#endif + RW_m_data2 m_data2_start m_data2_size { + * (RamFunction) + } +#if (defined(__heap_noncacheable__)) + RW_m_data m_data_start m_data_size-Stack_Size { ; RW data +#else + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data +#endif + .ANY (+RW +ZI) + *(*m_usb_dma_init_data) + *(*m_usb_dma_noninit_data) + } +#if (!defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } +#endif + ; ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + ; } + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} +#if (defined(__heap_noncacheable__)) + RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data +#else + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data +#endif + * (NonCacheable.init) + * (*NonCacheable) + } +#if (defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration +#else + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration +#endif + } +} diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/flexspi_port.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/flexspi_port.h new file mode 100644 index 0000000000..60514484c9 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/flexspi_port.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-15 xjy198903 The first version for rt1170 + */ + +#ifndef FLEXSPI_PORT_H__ +#define FLEXSPI_PORT_H__ + +/* parameters for flexpsi peripheral */ +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI2_CONTROL_BASE FLEXSPI2 +#define FLEXSPI_ROOT_CLK (80000000U) /* serial root clk: 80MHz*/ +#define FLASH_SIZE (32 * 1024) /* device size 32*1024(KB) = 32MB */ +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 1 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 1 /* Sequence ID for AHB write command */ +#define ARD_SEQ_CMD 0xBB /* cmd for read */ +#define AWR_SEQ_CMD 0xAA /* cmd for write */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M +#define CLOCK_DIV 5U +#define CUSTOM_LUT_LENGTH 64U +#define FLEXSPI1_AHB_DATA_ADDRESS (0x30000000U) +#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) +#endif /* FLEXSPI_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/sdram_port.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/sdram_port.h new file mode 100644 index 0000000000..9bdb3b617e --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/board/ports/sdram_port.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + * 2022-08-15 xjy198903 add sdram config for rt1170 + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):64MB = 2*32*1024*1KBytes */ +#if defined(SOC_IMXRT1170_SERIES) +#define SDRAM_SIZE ((uint32_t)(0x10000)) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize32Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize32Bit +#else +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +#endif +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd new file mode 100644 index 0000000000..e0424639a2 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd @@ -0,0 +1,1546 @@ + + + 3 + + rtthread + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp new file mode 100644 index 0000000000..d73d08a449 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp @@ -0,0 +1,1323 @@ + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\mnt.c + + + $PROJ_DIR$\applications\main.c + + + + Compiler + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\phy\phy.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + + Drivers + + $PROJ_DIR$\board\MCUX_Config\clock_config.c + + + $PROJ_DIR$\board\MCUX_Config\pin_mux.c + + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\dcd.c + + + $PROJ_DIR$\..\libraries\drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\drivers\drv_uart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Libraries + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\iar\startup_MIMXRT1176_cm7.s + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c + + + $PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c + + + + POSIX + + + SAL + + $PROJ_DIR$\..\..\..\components\net\netdev\src\netdev.c + + + $PROJ_DIR$\..\..\..\components\net\netdev\src\netdev_ipaddr.c + + + + xip + + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + + + $PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.eww b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvoptx b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvoptx new file mode 100644 index 0000000000..0eb6e7b221 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + .\board\linker_scripts\evkmimxrt1170_flexspi_nor_sdram.ini + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC40000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + JL2CM3 + -U600103734 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx new file mode 100644 index 0000000000..38a3ae8a85 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx @@ -0,0 +1,882 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 1 + + + MIMXRT1176DVMAA:cm7 + NXP + NXP.MIMXRT1176_DFP.13.1.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x20000000,0x040000) IROM(0x00200000,0x040000) XRAM(0x1ffe0000,0x020000) XRAM2(0x00000000,0x040000) XRAM3(0x20240000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + 0 + $$Device:MIMXRT1176DVMAA$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1176DVMAA$MIMXRT1176_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x20000 + + + 0 + 0x0 + 0x40000 + + + 0 + 0x20240000 + 0x80000 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + CPU_MIMXRT1176DVMAA_cm7, USE_SDRAM, __STDC_LIMIT_MACROS, __RTTHREAD__, XIP_BOOT_HEADER_DCD_ENABLE=1, ARM_MATH_CM7, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, SOC_IMXRT1170_SERIES, XIP_BOOT_HEADER_ENABLE=1, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, XIP_EXTERNAL_FLASH=1, RT_USING_ARM_LIBC + + applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m7;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\MCUX_Config;board\ports;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MIMXRT1170\CMSIS\Include;..\libraries\MIMXRT1170\MIMXRT1176;..\libraries\MIMXRT1170\MIMXRT1176\drivers;..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;..\..\..\components\net\netdev\include;xip + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + --keep=*(.boot_hdr.ivt) --keep=*(.boot_hdr.boot_data) --keep=*(.boot_hdr.dcd_data) --keep=*(.boot_hdr.conf) --predefine="-DXIP_BOOT_HEADER_ENABLE=1" + + 6439,6314 + + + + + + Applications + + + mnt.c + 1 + applications\mnt.c + + + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdio.c + 1 + ..\..\..\components\libc\compilers\common\cstdio.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + + + + cpu_cache.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpu_cache.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + + + DeviceDrivers + + + cputime.c + 1 + ..\..\..\components\drivers\cputime\cputime.c + + + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + phy.c + 1 + ..\..\..\components\drivers\phy\phy.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + clock_config.c + 1 + board\MCUX_Config\clock_config.c + + + + + pin_mux.c + 1 + board\MCUX_Config\pin_mux.c + + + + + board.c + 1 + board\board.c + + + + + dcd.c + 1 + board\dcd.c + + + + + drv_gpio.c + 1 + ..\libraries\drivers\drv_gpio.c + + + + + drv_uart.c + 1 + ..\libraries\drivers\drv_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + fsl_pmu.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c + + + + + startup_MIMXRT1176_cm7.s + 2 + ..\libraries\MIMXRT1170\MIMXRT1176\arm\startup_MIMXRT1176_cm7.s + + + + + system_MIMXRT1176_cm7.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c + + + + + fsl_lpuart.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c + + + + + fsl_gpio.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c + + + + + fsl_anatop_ai.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c + + + + + fsl_dcdc.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c + + + + + fsl_cache.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c + + + + + fsl_common_arm.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c + + + + + fsl_common.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c + + + + + fsl_clock.c + 1 + ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c + + + + + SAL + + + netdev.c + 1 + ..\..\..\components\net\netdev\src\netdev.c + + + + + netdev_ipaddr.c + 1 + ..\..\..\components\net\netdev\src\netdev_ipaddr.c + + + + + xip + + + fsl_flexspi_nor_boot.c + 1 + xip\fsl_flexspi_nor_boot.c + + + + + evkmimxrt1170_flexspi_nor_config.c + 1 + xip\evkmimxrt1170_flexspi_nor_config.c + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h new file mode 100644 index 0000000000..778e5e18e3 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h @@ -0,0 +1,213 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40101 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CPUTIME +#define RT_USING_PHY +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + +/* RT-Thread Smart */ + + +/* Hardware Drivers Config */ + +#define BSP_USING_QSPIFLASH +#define SOC_MIMXRT1176DVMAA + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 + +/* Onboard Peripheral Drivers */ + + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.py b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.py new file mode 100644 index 0000000000..456c1f9267 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.py @@ -0,0 +1,164 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + AFLAGS += ' -D__STARTUP_CLEAR_BSS' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' + + CFLAGS += ' --diag_suppress=66,1296,186,6314' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + \ No newline at end of file diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewd b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewd new file mode 100644 index 0000000000..0d43f6d913 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewd @@ -0,0 +1,1546 @@ + + + 3 + + rtthread + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewp b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewp new file mode 100644 index 0000000000..e2ee9db5dd --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewp @@ -0,0 +1,1074 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 208 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewt b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewt new file mode 100644 index 0000000000..2909739da7 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.ewt @@ -0,0 +1,1426 @@ + + + 3 + + rtthread + + ARM + + 1 + + C-STAT + 516 + + 516 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + rtthread/C-STAT + + + 2.4.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + .\board\linker_scripts\evkmimxrt1170_flexspi_nor_sdram.ini + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC40000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + JL2CM3 + -U600103734 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvprojx b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvprojx new file mode 100644 index 0000000000..95a9d570eb --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 1 + + + MIMXRT1176DVMAA:cm7 + NXP + NXP.MIMXRT1176_DFP.13.1.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x20000000,0x040000) IROM(0x00200000,0x040000) XRAM(0x1ffe0000,0x020000) XRAM2(0x00000000,0x040000) XRAM3(0x20240000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + 0 + $$Device:MIMXRT1176DVMAA$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1176DVMAA$MIMXRT1176_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x20000 + + + 0 + 0x0 + 0x40000 + + + 0 + 0x20240000 + 0x80000 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + --legacyalign + + 6439,6314 + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/SConscript new file mode 100644 index 0000000000..84d2e8e4f8 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/SConscript @@ -0,0 +1,20 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BSP_USING_QSPIFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS = ' --keep=*(.boot_hdr.ivt)' + LINKFLAGS += ' --keep=*(.boot_hdr.boot_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.conf)' + LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' + else: + LINKFLAGS = '' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.c new file mode 100644 index 0000000000..ff2b4cce42 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.c @@ -0,0 +1,53 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1170_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0x00, DUMMY_SDR, FLEXSPI_4PAD, 0x04), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.h new file mode 100644 index 0000000000..aa3383d5ee --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/evkmimxrt1170_flexspi_nor_config.h @@ -0,0 +1,268 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..1a8307928d --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,49 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.ivt"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.boot_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + BOOT_IMAGE_BASE, /* boot start location */ + BOOT_IMAGE_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFFU /* empty - extra data word */ +}; +#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..e586d750e0 --- /dev/null +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,147 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "board.h" +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.4. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ +{ + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#elif defined(__MCUXPRESSO) +extern uint32_t ResetISR[]; +extern uint32_t __boot_hdr_start__[]; +extern uint32_t __boot_hdr_ivt_loadaddr__[]; +extern uint32_t __boot_hdr_boot_data_loadaddr__[]; +extern uint32_t __boot_hdr_dcd_loadaddr__[]; +extern uint32_t _boot_loadaddr[]; +extern uint32_t _boot_size[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) +#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr) +#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size) +#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__) +#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__) +#define DCD_DATA_ADDRESS ((uint32_t)__boot_hdr_dcd_loadaddr__) +#elif defined(__ICCARM__) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#elif defined(__GNUC__) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#endif +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) +#define DCD_ADDRESS DCD_DATA_ADDRESS +#else +#define DCD_ADDRESS 0 +#endif +#endif +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ +{ + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +} BOOT_DATA_T; + +#if __CORTEX_M == 7 +#define FLASH_BASE FlexSPI1_AMBA_BASE +#elif __CORTEX_M == 4 +#define FLASH_BASE FlexSPI1_ALIAS_BASE +#endif + +#if defined(BOARD_FLASH_SIZE) +#define FLASH_SIZE BOARD_FLASH_SIZE +#else +#error "Please define macro BOARD_FLASH_SIZE" +#endif +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) +extern const uint8_t dcd_data[]; +#endif + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/project.ewd b/bsp/imxrt/imxrt1170-nxp-evk/project.ewd deleted file mode 100644 index e0424639a2..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/project.ewd +++ /dev/null @@ -1,1546 +0,0 @@ - - - 3 - - rtthread - - ARM - - 1 - - C-SPY - 2 - - 32 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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1 - ..\..\..\components\drivers\ipc\workqueue.c - - - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - phy.c - 1 - ..\..\..\components\drivers\phy\phy.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - Drivers - - - clock_config.c - 1 - board\MCUX_Config\clock_config.c - - - - - pin_mux.c - 1 - board\MCUX_Config\pin_mux.c - - - - - board.c - 1 - board\board.c - - - - - dcd.c - 1 - board\dcd.c - - - - - drv_gpio.c - 1 - ..\libraries\drivers\drv_gpio.c - - - - - drv_uart.c - 1 - ..\libraries\drivers\drv_uart.c - - - - - Finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - memheap.c - 1 - ..\..\..\src\memheap.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - Libraries - - - fsl_pmu.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c - - - - - startup_MIMXRT1176_cm7.s - 2 - ..\libraries\MIMXRT1170\MIMXRT1176\arm\startup_MIMXRT1176_cm7.s - - - - - system_MIMXRT1176_cm7.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c - - - - - fsl_lpuart.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c - - - - - fsl_gpio.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c - - - - - fsl_anatop_ai.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c - - - - - fsl_dcdc.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c - - - - - fsl_cache.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c - - - - - fsl_common_arm.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c - - - - - fsl_common.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c - - - - - fsl_clock.c - 1 - ..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c - - - - - SAL - - - netdev.c - 1 - ..\..\..\components\net\netdev\src\netdev.c - - - - - netdev_ipaddr.c - 1 - ..\..\..\components\net\netdev\src\netdev_ipaddr.c - - - - - xip - - - fsl_flexspi_nor_boot.c - 1 - xip\fsl_flexspi_nor_boot.c - - - - - evkmimxrt1170_flexspi_nor_config.c - 1 - xip\evkmimxrt1170_flexspi_nor_config.c - - - - - - - - - - - - - - - <Project Info> - 0 - 1 - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.h deleted file mode 100644 index 778e5e18e3..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.h +++ /dev/null @@ -1,213 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_DEBUG -#define RT_DEBUG_COLOR - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_MEMHEAP -#define RT_MEMHEAP_FAST_MODE -#define RT_USING_MEMHEAP_AS_HEAP -#define RT_USING_MEMHEAP_AUTO_BINDING -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40101 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CPUTIME -#define RT_USING_PHY -#define RT_USING_PIN - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -#define RT_LIBC_DEFAULT_TIMEZONE 8 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - -#define RT_USING_NETDEV -#define NETDEV_USING_IFCONFIG -#define NETDEV_USING_PING -#define NETDEV_USING_NETSTAT -#define NETDEV_USING_AUTO_DEFAULT -#define NETDEV_IPV4 1 -#define NETDEV_IPV6 0 - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - - -/* RT-Thread Smart */ - - -/* Hardware Drivers Config */ - -#define BSP_USING_QSPIFLASH -#define SOC_MIMXRT1176DVMAA - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define BSP_USING_LPUART -#define BSP_USING_LPUART1 - -/* Onboard Peripheral Drivers */ - - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.py b/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.py deleted file mode 100644 index 456c1f9267..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/rtconfig.py +++ /dev/null @@ -1,164 +0,0 @@ -import os -import sys - -# toolchains options -ARCH='arm' -CPU='cortex-m7' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -#BUILD = 'debug' -BUILD = 'release' - -if PLATFORM == 'gcc': - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - STRIP = PREFIX + 'strip' - - DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' - AFLAGS += ' -D__STARTUP_CLEAR_BSS' - - if BUILD == 'debug': - CFLAGS += ' -gdwarf-2' - AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - else: - CFLAGS += ' -O2 -Os' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - - # module setting - CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' - M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' - M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' - M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ - ' -shared -fPIC -nostartfiles -static-libgcc' - M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu ' + CPU + '.fp.sp' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' - - CFLAGS += ' --diag_suppress=66,1296,186,6314' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' --c99' - - POST_ACTION = 'fromelf -z $TARGET' - # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D__FPU_PRESENT' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=' + CPU - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu ' + CPU - AFLAGS += ' --fpu None' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) - \ No newline at end of file diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.ewd b/bsp/imxrt/imxrt1170-nxp-evk/template.ewd deleted file mode 100644 index 0d43f6d913..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.ewd +++ /dev/null @@ -1,1546 +0,0 @@ - - - 3 - - rtthread - - ARM - - 1 - - C-SPY - 2 - - 32 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IJET_ID - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 3 - 1 - 1 - - - - - - - - - - - - - NULINK_ID - 2 - - 0 - 1 - 1 - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 1 - - - - - - - - STLINK_ID - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.ewp b/bsp/imxrt/imxrt1170-nxp-evk/template.ewp deleted file mode 100644 index e2ee9db5dd..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.ewp +++ /dev/null @@ -1,1074 +0,0 @@ - - - 3 - - rtthread - - ARM - - 1 - - General - 3 - - 35 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 37 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 208 - inputOutputBased - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 27 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.ewt b/bsp/imxrt/imxrt1170-nxp-evk/template.ewt deleted file mode 100644 index 2909739da7..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.ewt +++ /dev/null @@ -1,1426 +0,0 @@ - - - 3 - - rtthread - - ARM - - 1 - - C-STAT - 516 - - 516 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - rtthread/C-STAT - - - 2.4.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.eww b/bsp/imxrt/imxrt1170-nxp-evk/template.eww deleted file mode 100644 index bd036bb4c9..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\template.ewp - - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.uvoptx b/bsp/imxrt/imxrt1170-nxp-evk/template.uvoptx deleted file mode 100644 index 0eb6e7b221..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.uvoptx +++ /dev/null @@ -1,189 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rtthread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\List\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - .\board\linker_scripts\evkmimxrt1170_flexspi_nor_sdram.ini - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC40000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) - - - 0 - JL2CM3 - -U600103734 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 1 - 0 - 2 - 10000000 - - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/template.uvprojx b/bsp/imxrt/imxrt1170-nxp-evk/template.uvprojx deleted file mode 100644 index 95a9d570eb..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/template.uvprojx +++ /dev/null @@ -1,401 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rtthread - 0x4 - ARM-ADS - 6150000::V6.15::ARMCLANG - 1 - - - MIMXRT1176DVMAA:cm7 - NXP - NXP.MIMXRT1176_DFP.13.1.0 - https://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x020000) IRAM2(0x20000000,0x040000) IROM(0x00200000,0x040000) XRAM(0x1ffe0000,0x020000) XRAM2(0x00000000,0x040000) XRAM3(0x20240000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) - 0 - $$Device:MIMXRT1176DVMAA$fsl_device_registers.h - - - - - - - - - - $$Device:MIMXRT1176DVMAA$MIMXRT1176_cm7.xml - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rtthread - 1 - 0 - 0 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM7 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM7 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 0 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 0 - 0 - 0 - 1 - 1 - 1 - 0 - 3 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x200000 - 0x40000 - - - 1 - 0x1ffe0000 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x200000 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x1ffe0000 - 0x20000 - - - 0 - 0x0 - 0x40000 - - - 0 - 0x20240000 - 0x80000 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 5 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 3 - 0 - 0 - 1 - 0 - 0 - 3 - 3 - 1 - 1 - 0 - 0 - 0 - - -xc -std=gnu99 -mimplicit-float - RELOC_VECTOR - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x10000000 - - .\board\linker_scripts\link.sct - - - --legacyalign - - 6439,6314 - - - - - - - - - - - - - - - - <Project Info> - 0 - 1 - - - - - diff --git a/bsp/imxrt/imxrt1170-nxp-evk/xip/SConscript b/bsp/imxrt/imxrt1170-nxp-evk/xip/SConscript deleted file mode 100644 index 84d2e8e4f8..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/xip/SConscript +++ /dev/null @@ -1,20 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -if GetDepend('BSP_USING_QSPIFLASH'): - cwd = GetCurrentDir() - src = Glob('*.c') - CPPPATH = [cwd] - - if rtconfig.PLATFORM in ['armcc', 'armclang']: - LINKFLAGS = ' --keep=*(.boot_hdr.ivt)' - LINKFLAGS += ' --keep=*(.boot_hdr.boot_data)' - LINKFLAGS += ' --keep=*(.boot_hdr.dcd_data)' - LINKFLAGS += ' --keep=*(.boot_hdr.conf)' - LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' - else: - LINKFLAGS = '' - - group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) - Return('group') diff --git a/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.c b/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.c deleted file mode 100644 index ff2b4cce42..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "evkmimxrt1170_flexspi_nor_config.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const flexspi_nor_config_t qspiflash_config = { - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock - .controllerMiscOption = 0x10, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 16u * 1024u * 1024u, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0x00, DUMMY_SDR, FLEXSPI_4PAD, 0x04), - FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, 0, 0, 0), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = 0x1, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.h b/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.h deleted file mode 100644 index aa3383d5ee..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/xip/evkmimxrt1170_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.1. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_80MHz = 4, - kFlexSpiSerialClk_100MHz = 5, - kFlexSpiSerialClk_120MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.c deleted file mode 100644 index 1a8307928d..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2019-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexspi_nor_boot.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_device" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.ivt"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.ivt" -#endif -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.boot_data"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.boot_data" -#endif -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - BOOT_IMAGE_BASE, /* boot start location */ - BOOT_IMAGE_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFFU /* empty - extra data word */ -}; -#endif diff --git a/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.h deleted file mode 100644 index e586d750e0..0000000000 --- a/bsp/imxrt/imxrt1170-nxp-evk/xip/fsl_flexspi_nor_boot.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2019-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FLEXSPI_NOR_BOOT_H__ -#define __FLEXSPI_NOR_BOOT_H__ - -#include -#include "board.h" -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_DEVICE driver version 2.0.4. */ -#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ - -/************************************* - * IVT Data - *************************************/ -typedef struct _ivt_ -{ - /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields - * (see @ref data) - */ - uint32_t hdr; - /** Absolute address of the first instruction to execute from the - * image - */ - uint32_t entry; - /** Reserved in this version of HAB: should be NULL. */ - uint32_t reserved1; - /** Absolute address of the image DCD: may be NULL. */ - uint32_t dcd; - /** Absolute address of the Boot Data: may be NULL, but not interpreted - * any further by HAB - */ - uint32_t boot_data; - /** Absolute address of the IVT.*/ - uint32_t self; - /** Absolute address of the image CSF.*/ - uint32_t csf; - /** Reserved in this version of HAB: should be zero. */ - uint32_t reserved2; -} ivt; - -#define IVT_MAJOR_VERSION 0x4 -#define IVT_MAJOR_VERSION_SHIFT 0x4 -#define IVT_MAJOR_VERSION_MASK 0xF -#define IVT_MINOR_VERSION 0x1 -#define IVT_MINOR_VERSION_SHIFT 0x0 -#define IVT_MINOR_VERSION_MASK 0xF - -#define IVT_VERSION(major, minor) \ - ((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ - (((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) - -/* IVT header */ -#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ -#define IVT_SIZE 0x2000 -#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) -#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) - -/* Set resume entry */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) -extern uint32_t Reset_Handler[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) -#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) -#define BOOT_DATA_ADDRESS &boot_data -#define IVT_ADDRESS &image_vector_table -#define DCD_DATA_ADDRESS dcd_data -#elif defined(__MCUXPRESSO) -extern uint32_t ResetISR[]; -extern uint32_t __boot_hdr_start__[]; -extern uint32_t __boot_hdr_ivt_loadaddr__[]; -extern uint32_t __boot_hdr_boot_data_loadaddr__[]; -extern uint32_t __boot_hdr_dcd_loadaddr__[]; -extern uint32_t _boot_loadaddr[]; -extern uint32_t _boot_size[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) -#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr) -#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size) -#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__) -#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__) -#define DCD_DATA_ADDRESS ((uint32_t)__boot_hdr_dcd_loadaddr__) -#elif defined(__ICCARM__) -extern uint32_t Reset_Handler[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) -#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) -#define BOOT_DATA_ADDRESS &boot_data -#define IVT_ADDRESS &image_vector_table -#define DCD_DATA_ADDRESS dcd_data -#elif defined(__GNUC__) -extern uint32_t Reset_Handler[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) -#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) -#define BOOT_DATA_ADDRESS &boot_data -#define IVT_ADDRESS &image_vector_table -#define DCD_DATA_ADDRESS dcd_data -#endif -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) -#define DCD_ADDRESS DCD_DATA_ADDRESS -#else -#define DCD_ADDRESS 0 -#endif -#endif -#define CSF_ADDRESS 0 -#define IVT_RSVD (uint32_t)(0x00000000) - -/************************************* - * Boot Data - *************************************/ -typedef struct _boot_data_ -{ - uint32_t start; /* boot start location */ - uint32_t size; /* size */ - uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ -} BOOT_DATA_T; - -#if __CORTEX_M == 7 -#define FLASH_BASE FlexSPI1_AMBA_BASE -#elif __CORTEX_M == 4 -#define FLASH_BASE FlexSPI1_ALIAS_BASE -#endif - -#if defined(BOARD_FLASH_SIZE) -#define FLASH_SIZE BOARD_FLASH_SIZE -#else -#error "Please define macro BOARD_FLASH_SIZE" -#endif -#define PLUGIN_FLAG (uint32_t)0 - -/* External Variables */ -const BOOT_DATA_T boot_data; -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) -extern const uint8_t dcd_data[]; -#endif - -#endif /* __FLEXSPI_NOR_BOOT_H__ */ -- cgit v1.3.1