From 701df33436f2c88dc2c8b6912f377e978c6ab6d7 Mon Sep 17 00:00:00 2001 From: wuyangyong Date: Fri, 23 Dec 2011 01:36:10 +0000 Subject: remove libcpu/arm/lm3s libcpu/arm/lpc176x , update bsp lm3s lpc176x. git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1865 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- bsp/lm3s8962/Libraries/SConscript | 39 +- bsp/lm3s8962/Libraries/startup/arm/start_rvds.S | 253 ++++++++ bsp/lm3s8962/Libraries/startup/gcc/start_gcc.S | 164 +++++ bsp/lm3s8962/SConscript | 25 +- bsp/lm3s8962/SConstruct | 4 +- bsp/lm3s8962/application.c | 83 --- bsp/lm3s8962/applications/SConscript | 11 + bsp/lm3s8962/applications/application.c | 83 +++ bsp/lm3s8962/applications/startup.c | 156 +++++ bsp/lm3s8962/board.c | 132 ---- bsp/lm3s8962/board.h | 35 -- bsp/lm3s8962/drivers/SConscript | 21 + bsp/lm3s8962/drivers/board.c | 139 +++++ bsp/lm3s8962/drivers/board.h | 35 ++ bsp/lm3s8962/drivers/luminaryif.c | 489 +++++++++++++++ bsp/lm3s8962/drivers/luminaryif.h | 12 + bsp/lm3s8962/drivers/sdcard.c | 781 ++++++++++++++++++++++++ bsp/lm3s8962/drivers/serial.c | 362 +++++++++++ bsp/lm3s8962/luminaryif.c | 489 --------------- bsp/lm3s8962/luminaryif.h | 12 - bsp/lm3s8962/project.Uv2 | 236 ++++--- bsp/lm3s8962/rtconfig.py | 2 +- bsp/lm3s8962/sdcard.c | 781 ------------------------ bsp/lm3s8962/startup.c | 156 ----- bsp/lm3s8962/template.Uv2 | 4 +- bsp/lm3s9b9x/Libraries/SConscript | 39 +- bsp/lm3s9b9x/Libraries/startup/arm/start_rvds.S | 253 ++++++++ bsp/lm3s9b9x/Libraries/startup/gcc/start_gcc.S | 164 +++++ bsp/lm3s9b9x/SConscript | 25 +- bsp/lm3s9b9x/SConstruct | 5 +- bsp/lm3s9b9x/application.c | 83 --- bsp/lm3s9b9x/applications/SConscript | 11 + bsp/lm3s9b9x/applications/application.c | 83 +++ bsp/lm3s9b9x/applications/startup.c | 155 +++++ bsp/lm3s9b9x/board.c | 140 ----- bsp/lm3s9b9x/board.h | 47 -- bsp/lm3s9b9x/drivers/SConscript | 21 + bsp/lm3s9b9x/drivers/board.c | 140 +++++ bsp/lm3s9b9x/drivers/board.h | 47 ++ bsp/lm3s9b9x/drivers/luminaryif.c | 490 +++++++++++++++ bsp/lm3s9b9x/drivers/luminaryif.h | 12 + bsp/lm3s9b9x/drivers/sdcard.c | 781 ++++++++++++++++++++++++ bsp/lm3s9b9x/drivers/sdram.c | 256 ++++++++ bsp/lm3s9b9x/drivers/serial.c | 362 +++++++++++ bsp/lm3s9b9x/luminaryif.c | 490 --------------- bsp/lm3s9b9x/luminaryif.h | 12 - bsp/lm3s9b9x/project.Uv2 | 239 ++++---- bsp/lm3s9b9x/rtconfig.py | 2 +- bsp/lm3s9b9x/sdcard.c | 781 ------------------------ bsp/lm3s9b9x/sdram.c | 256 -------- bsp/lm3s9b9x/startup.c | 155 ----- bsp/lm3s9b9x/template.Uv2 | 4 +- bsp/lpc176x/project.Uv2 | 24 +- bsp/lpc176x/project.ewp | 371 +++-------- bsp/lpc176x/rtconfig.py | 2 +- bsp/lpc176x/template.ewp | 280 +++------ 56 files changed, 5734 insertions(+), 4500 deletions(-) create mode 100644 bsp/lm3s8962/Libraries/startup/arm/start_rvds.S create mode 100644 bsp/lm3s8962/Libraries/startup/gcc/start_gcc.S delete mode 100644 bsp/lm3s8962/application.c create mode 100644 bsp/lm3s8962/applications/SConscript create mode 100644 bsp/lm3s8962/applications/application.c create mode 100644 bsp/lm3s8962/applications/startup.c delete mode 100644 bsp/lm3s8962/board.c delete mode 100644 bsp/lm3s8962/board.h create mode 100644 bsp/lm3s8962/drivers/SConscript create mode 100644 bsp/lm3s8962/drivers/board.c create mode 100644 bsp/lm3s8962/drivers/board.h create mode 100644 bsp/lm3s8962/drivers/luminaryif.c create mode 100644 bsp/lm3s8962/drivers/luminaryif.h create mode 100644 bsp/lm3s8962/drivers/sdcard.c create mode 100644 bsp/lm3s8962/drivers/serial.c delete mode 100644 bsp/lm3s8962/luminaryif.c delete mode 100644 bsp/lm3s8962/luminaryif.h delete mode 100644 bsp/lm3s8962/sdcard.c delete mode 100644 bsp/lm3s8962/startup.c create mode 100644 bsp/lm3s9b9x/Libraries/startup/arm/start_rvds.S create mode 100644 bsp/lm3s9b9x/Libraries/startup/gcc/start_gcc.S delete mode 100644 bsp/lm3s9b9x/application.c create mode 100644 bsp/lm3s9b9x/applications/SConscript create mode 100644 bsp/lm3s9b9x/applications/application.c create mode 100644 bsp/lm3s9b9x/applications/startup.c delete mode 100644 bsp/lm3s9b9x/board.c delete mode 100644 bsp/lm3s9b9x/board.h create mode 100644 bsp/lm3s9b9x/drivers/SConscript create mode 100644 bsp/lm3s9b9x/drivers/board.c create mode 100644 bsp/lm3s9b9x/drivers/board.h create mode 100644 bsp/lm3s9b9x/drivers/luminaryif.c create mode 100644 bsp/lm3s9b9x/drivers/luminaryif.h create mode 100644 bsp/lm3s9b9x/drivers/sdcard.c create mode 100644 bsp/lm3s9b9x/drivers/sdram.c create mode 100644 bsp/lm3s9b9x/drivers/serial.c delete mode 100644 bsp/lm3s9b9x/luminaryif.c delete mode 100644 bsp/lm3s9b9x/luminaryif.h delete mode 100644 bsp/lm3s9b9x/sdcard.c delete mode 100644 bsp/lm3s9b9x/sdram.c delete mode 100644 bsp/lm3s9b9x/startup.c (limited to 'bsp') diff --git a/bsp/lm3s8962/Libraries/SConscript b/bsp/lm3s8962/Libraries/SConscript index 162fc442b8..ebf7b660c1 100644 --- a/bsp/lm3s8962/Libraries/SConscript +++ b/bsp/lm3s8962/Libraries/SConscript @@ -3,34 +3,19 @@ Import('rtconfig') from building import * # The set of source files associated with this SConscript file. -src = Split(""" - driverlib/adc.c - driverlib/can.c - driverlib/comp.c - driverlib/cpu.c - driverlib/epi.c - driverlib/ethernet.c - driverlib/flash.c - driverlib/gpio.c - driverlib/hibernate.c - driverlib/i2c.c - driverlib/i2s.c - driverlib/interrupt.c - driverlib/mpu.c - driverlib/pwm.c - driverlib/qei.c - driverlib/ssi.c - driverlib/sysctl.c - driverlib/systick.c - driverlib/timer.c - driverlib/uart.c - driverlib/udma.c - driverlib/usb.c - driverlib/watchdog.c -""") +cwd = GetCurrentDir() +src = Glob('driverlib/*.c') -CPPPATH = [RTT_ROOT + '/bsp/lm3s8962/Libraries/inc', RTT_ROOT + '/bsp/lm3s8962/Libraries', RTT_ROOT + '/bsp/lm3s8962/Libraries/driverlib'] +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += ['startup/gcc/startup_LPC17xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['startup/arm/start_rvds.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['startup/iar/start_iar.S'] -group = DefineGroup('library', src, depend = [''], CPPPATH = CPPPATH) +CPPPATH = [cwd] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/lm3s8962/Libraries/startup/arm/start_rvds.S b/bsp/lm3s8962/Libraries/startup/arm/start_rvds.S new file mode 100644 index 0000000000..cf564930bc --- /dev/null +++ b/bsp/lm3s8962/Libraries/startup/arm/start_rvds.S @@ -0,0 +1,253 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; Startup.s - Startup code for Stellaris. +; +; Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +; +; Software License Agreement +; +; Luminary Micro, Inc. (LMI) is supplying this software for use solely and +; exclusively on LMI's microcontroller products. +; +; The software is owned by LMI and/or its suppliers, and is protected under +; applicable copyright laws. All rights are reserved. You may not combine +; this software with "viral" open-source software in order to form a larger +; program. Any use in violation of the foregoing restrictions may subject +; the user to criminal sanctions under applicable laws, as well as to civil +; liability for the breach of the terms and conditions of this license. +; +; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2523 of the Stellaris Peripheral Driver Library. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000100 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + + IMPORT PendSV_Handler + IMPORT rt_hw_timer_handler + IMPORT rt_hw_uart_isr_1 + IMPORT rt_hw_eth_handler + IMPORT HardFault_Handler + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD IntDefaultHandler ; MPU Fault Handler + DCD IntDefaultHandler ; Bus Fault Handler + DCD IntDefaultHandler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall Handler + DCD IntDefaultHandler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD rt_hw_timer_handler ; SysTick Handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD rt_hw_uart_isr_1 ; UART0 + DCD IntDefaultHandler ; UART1 + DCD IntDefaultHandler ; SSI + DCD IntDefaultHandler ; I2C + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog + DCD IntDefaultHandler ; Timer 0A + DCD IntDefaultHandler ; Timer 0B + DCD IntDefaultHandler ; Timer 1A + DCD IntDefaultHandler ; Timer 1B + DCD IntDefaultHandler ; Timer 2A + DCD IntDefaultHandler ; Timer 2B + DCD IntDefaultHandler ; Comp 0 + DCD IntDefaultHandler ; Comp 1 + DCD IntDefaultHandler ; Comp 2 + DCD IntDefaultHandler ; System Control + DCD 0x881 ; Flash Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD IntDefaultHandler ; CAN2 + DCD rt_hw_eth_handler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/bsp/lm3s8962/Libraries/startup/gcc/start_gcc.S b/bsp/lm3s8962/Libraries/startup/gcc/start_gcc.S new file mode 100644 index 0000000000..1d1b8e558d --- /dev/null +++ b/bsp/lm3s8962/Libraries/startup/gcc/start_gcc.S @@ -0,0 +1,164 @@ +.section .bss.init +.equ Stack_Size, 0x00000200 +.space Stack_Size +Initial_spTop: + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + LDR r0, =Initial_spTop + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word Default_Handler //NMI_Handler + .word rt_hw_hard_fault + .word Default_Handler //MemManage_Handler + .word Default_Handler //BusFault_Handler + .word Default_Handler //UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word Default_Handler //SVC_Handler + .word Default_Handler //DebugMon_Handler + .word 0 + .word rt_hw_pend_sv + .word rt_hw_timer_handler + .word Default_Handler // GPIO Port A + .word Default_Handler // GPIO Port B + .word Default_Handler // GPIO Port C + .word Default_Handler // GPIO Port D + .word Default_Handler // GPIO Port E + .word rt_hw_uart_isr_1 // UART0 Rx and Tx + .word Default_Handler // UART1 Rx and Tx + .word Default_Handler // SSI Rx and Tx + .word Default_Handler // I2C Master and Slave + .word Default_Handler // PWM Fault + .word Default_Handler // PWM Generator 0 + .word Default_Handler // PWM Generator 1 + .word Default_Handler // PWM Generator 2 + .word Default_Handler // Quadrature Encoder + .word Default_Handler // ADC Sequence 0 + .word Default_Handler // ADC Sequence 1 + .word Default_Handler // ADC Sequence 2 + .word Default_Handler // ADC Sequence 3 + .word Default_Handler // Watchdog timer + .word Default_Handler // Timer 0 subtimer A + .word Default_Handler // Timer 0 subtimer B + .word Default_Handler // Timer 1 subtimer A + .word Default_Handler // Timer 1 subtimer B + .word Default_Handler // Timer 2 subtimer A + .word Default_Handler // Timer 2 subtimer B + .word Default_Handler // Analog Comparator 0 + .word Default_Handler // Analog Comparator 1 + .word Default_Handler // Analog Comparator 2 + .word Default_Handler // System Control (PLL, OSC, + .word Default_Handler // FLASH Control + .word Default_Handler // GPIO Port F + .word Default_Handler // GPIO Port G + .word Default_Handler // GPIO Port H + .word Default_Handler // UART2 Rx and Tx + .word Default_Handler // SSI1 Rx and Tx + .word Default_Handler // Timer 3 subtimer A + .word Default_Handler // Timer 3 subtimer B + .word Default_Handler // I2C1 Master and Slave + .word Default_Handler // Quadrature Encoder 1 + .word Default_Handler // CAN0 + .word Default_Handler // CAN1 + .word Default_Handler // CAN2 + .word luminaryif_isr // Ethernet + .word Default_Handler // Hibernate + .word Default_Handler // USB0 + .word Default_Handler // PWM Generator 3 + .word Default_Handler // uDMA Software Transfer + .word Default_Handler // uDMA Error diff --git a/bsp/lm3s8962/SConscript b/bsp/lm3s8962/SConscript index 41d350e427..a425264923 100644 --- a/bsp/lm3s8962/SConscript +++ b/bsp/lm3s8962/SConscript @@ -1,19 +1,14 @@ -import rtconfig +# for module compiling +import os Import('RTT_ROOT') -from building import * -src_bsp = ['application.c', 'startup.c', 'board.c'] +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) -src_drv = [] -if GetDepend('RT_USING_DFS'): - src_drv += ['sdcard.c'] +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) -if GetDepend('RT_USING_LWIP'): - - src_drv += ['luminaryif.c'] - -src = File(src_bsp + src_drv) -CPPPATH = [GetCurrentDir()] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') +Return('objs') diff --git a/bsp/lm3s8962/SConstruct b/bsp/lm3s8962/SConstruct index b8fd65c29f..12d70ecd16 100644 --- a/bsp/lm3s8962/SConstruct +++ b/bsp/lm3s8962/SConstruct @@ -19,9 +19,7 @@ Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -objs = objs + SConscript(('bsp/lm3s8962/Libraries/SConscript'), variant_dir='build/bsp/Libraries', duplicate=0) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) env.Program(TARGET, objs) diff --git a/bsp/lm3s8962/application.c b/bsp/lm3s8962/application.c deleted file mode 100644 index fded03279f..0000000000 --- a/bsp/lm3s8962/application.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -/** - * @addtogroup LM3S - */ -/*@{*/ - -#include -#include - -#ifdef RT_USING_DFS -/* dfs init */ -#include -/* dfs filesystem:ELM FatFs filesystem init */ -#include -/* dfs Filesystem APIs */ -#include -#endif - -#ifdef RT_USING_LWIP -#include -#include -#endif - -/* thread phase init */ -void rt_init_thread_entry(void *parameter) -{ -/* Filesystem Initialization */ -#ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); -#ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); - - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); -#endif - } -#endif - -/* LwIP Initialization */ -#ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } -#endif -} - -int rt_application_init() -{ - rt_thread_t init_thread; - - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 21, 20); - rt_thread_startup(init_thread); - - return 0; -} -/*@}*/ diff --git a/bsp/lm3s8962/applications/SConscript b/bsp/lm3s8962/applications/SConscript new file mode 100644 index 0000000000..591734409c --- /dev/null +++ b/bsp/lm3s8962/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lm3s8962/applications/application.c b/bsp/lm3s8962/applications/application.c new file mode 100644 index 0000000000..fded03279f --- /dev/null +++ b/bsp/lm3s8962/applications/application.c @@ -0,0 +1,83 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +/** + * @addtogroup LM3S + */ +/*@{*/ + +#include +#include + +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:ELM FatFs filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +#ifdef RT_USING_LWIP +#include +#include +#endif + +/* thread phase init */ +void rt_init_thread_entry(void *parameter) +{ +/* Filesystem Initialization */ +#ifdef RT_USING_DFS + { + /* init the device filesystem */ + dfs_init(); +#ifdef RT_USING_DFS_ELMFAT + /* init the elm chan FatFs filesystam*/ + elm_init(); + + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif + } +#endif + +/* LwIP Initialization */ +#ifdef RT_USING_LWIP + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } +#endif +} + +int rt_application_init() +{ + rt_thread_t init_thread; + + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 21, 20); + rt_thread_startup(init_thread); + + return 0; +} +/*@}*/ diff --git a/bsp/lm3s8962/applications/startup.c b/bsp/lm3s8962/applications/startup.c new file mode 100644 index 0000000000..b4c7e3e468 --- /dev/null +++ b/bsp/lm3s8962/applications/startup.c @@ -0,0 +1,156 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +#ifdef RT_USING_LWIP +#include +#include +#endif + +/** + * @addtogroup LM3S + */ + +extern void rt_hw_serial_init(void); + +/*@{*/ +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(char* device); +#endif + +extern int rt_application_init(void); +extern void rt_hw_sdcard_init(void); +extern int rt_hw_luminaryif_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); +#endif +#endif + +#ifdef RT_USING_MODULE + /* init module system */ + rt_system_module_init(); + + /* init scheduler system */ + rt_system_scheduler_init(); +#endif + +#ifdef RT_USING_LWIP + eth_system_device_init(); + + /* register ethernetif device */ + rt_hw_luminaryif_init(); +#endif + + /* init hardware serial device */ + rt_hw_serial_init(); +#ifdef RT_USING_DFS + /* init sd card device */ + rt_hw_sdcard_init(); +#endif + /* init all device */ + rt_device_init_all(); + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); +#ifdef RT_USING_DEVICE + finsh_set_device("uart1"); +#endif +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + rt_uint32_t level UNUSED; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/lm3s8962/board.c b/bsp/lm3s8962/board.c deleted file mode 100644 index 56fa83f89b..0000000000 --- a/bsp/lm3s8962/board.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-05-16 Bernard first implementation - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -static void rt_hw_console_init(void); - -/** - * @addtogroup LM3S - */ - -/*@{*/ - -extern void rt_hw_interrupt_thread_switch(void); -/** - * This is the timer interrupt service routine. - * - */ -void rt_hw_timer_handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); -} - -/** - * This is the ethernet interrupt service routine. - * - */ -void rt_hw_eth_handler(void) -{ -#ifdef RT_USING_LWIP - /* luminary ethernet interface */ - extern void luminaryif_isr(void); - luminaryif_isr(); -#endif -} - -/** - * This function will initial LM3S board. - */ -void rt_hw_board_init() -{ - /* set ldo */ - SysCtlLDOSet(SYSCTL_LDO_2_50V); - /* set clock */ - SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | - LM3S_XTAL_TYPE); - - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); - - /* enable ssio */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - - /* init console */ - rt_hw_console_init(); - - /* enable interrupt */ - IntMasterEnable(); -} - -/* init console to support rt_kprintf */ -static void rt_hw_console_init() -{ - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); -} - -/* write one character to serial, must not trigger interrupt */ -static void rt_hw_console_putc(const char c) -{ - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); -} - -/** - * This function is used by rt_kprintf to display a string on console. - * - * @param str the displayed string - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - rt_hw_console_putc (*str++); - } -} - -/*@}*/ diff --git a/bsp/lm3s8962/board.h b/bsp/lm3s8962/board.h deleted file mode 100644 index f33af86d26..0000000000 --- a/bsp/lm3s8962/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-10-08 Bernard add board.h to this bsp - * 2009-12-25 yi.qiu add LM3S configration - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#define LM3S_SRAM_SIZE 64 -#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) - -// For lm3s8962, it should be SYSCTL_XTAL_8MHZ -#define LM3S_XTAL_TYPE SYSCTL_XTAL_8MHZ - -void rt_hw_board_led_on(int n); -void rt_hw_board_led_off(int n); -void rt_hw_board_init(void); - -void rt_hw_usart_init(void); -void rt_hw_sdcard_init(void); - -#endif diff --git a/bsp/lm3s8962/drivers/SConscript b/bsp/lm3s8962/drivers/SConscript new file mode 100644 index 0000000000..36ce397c33 --- /dev/null +++ b/bsp/lm3s8962/drivers/SConscript @@ -0,0 +1,21 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import copy + +cwd = os.path.join(str(Dir('#')), 'drivers') +src = Glob('*.c') +CPPPATH = [cwd] + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + src_need_remove = ['luminaryif.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +if GetDepend('RT_USING_DFS') == False: + src_need_remove = ['sdcard.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lm3s8962/drivers/board.c b/bsp/lm3s8962/drivers/board.c new file mode 100644 index 0000000000..f7a75b0809 --- /dev/null +++ b/bsp/lm3s8962/drivers/board.c @@ -0,0 +1,139 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-05-16 Bernard first implementation + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +static void rt_hw_console_init(void); + +/** + * @addtogroup LM3S + */ + +/*@{*/ + +extern void rt_hw_interrupt_thread_switch(void); +/** + * This is the timer interrupt service routine. + * + */ +void rt_hw_timer_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} + +/** + * This is the ethernet interrupt service routine. + * + */ +void rt_hw_eth_handler(void) +{ +#ifdef RT_USING_LWIP + extern void luminaryif_isr(void); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* luminary ethernet interface */ + luminaryif_isr(); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +/** + * This function will initial LM3S board. + */ +void rt_hw_board_init() +{ + /* set ldo */ + SysCtlLDOSet(SYSCTL_LDO_2_50V); + /* set clock */ + SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | + LM3S_XTAL_TYPE); + + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); + + /* enable ssio */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + + /* init console */ + rt_hw_console_init(); + + /* enable interrupt */ + IntMasterEnable(); +} + +/* init console to support rt_kprintf */ +static void rt_hw_console_init() +{ + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); +} + +/* write one character to serial, must not trigger interrupt */ +static void rt_hw_console_putc(const char c) +{ + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_console_putc (*str++); + } +} + +/*@}*/ diff --git a/bsp/lm3s8962/drivers/board.h b/bsp/lm3s8962/drivers/board.h new file mode 100644 index 0000000000..f33af86d26 --- /dev/null +++ b/bsp/lm3s8962/drivers/board.h @@ -0,0 +1,35 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + * 2009-12-25 yi.qiu add LM3S configration + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#define LM3S_SRAM_SIZE 64 +#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) + +// For lm3s8962, it should be SYSCTL_XTAL_8MHZ +#define LM3S_XTAL_TYPE SYSCTL_XTAL_8MHZ + +void rt_hw_board_led_on(int n); +void rt_hw_board_led_off(int n); +void rt_hw_board_init(void); + +void rt_hw_usart_init(void); +void rt_hw_sdcard_init(void); + +#endif diff --git a/bsp/lm3s8962/drivers/luminaryif.c b/bsp/lm3s8962/drivers/luminaryif.c new file mode 100644 index 0000000000..6038059179 --- /dev/null +++ b/bsp/lm3s8962/drivers/luminaryif.c @@ -0,0 +1,489 @@ +//***************************************************************************** +// +// luminaryif.c - Ethernet Interface File for lwIP TCP/IP Stack +// +//***************************************************************************** + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "lwipopts.h" +#include "luminaryif.h" + +#define MAX_ADDR_LEN 6 + +struct net_device +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ +}; + +static struct net_device luminaryif_dev_entry; +static struct net_device *luminaryif_dev =&luminaryif_dev_entry; +static struct rt_semaphore tx_sem; + +//***************************************************************************** +// +// Sanity Check: This module will NOT work if the following defines +// are incorrect. +// +//***************************************************************************** +#if (PBUF_LINK_HLEN != 16) +#error "Incorrect PBUF_LINK_HLEN specified!" +#endif +#if (ETH_PAD_SIZE != 2) +#error "Incorrect ETH_PAD_SIZE specified!" +#endif +#if (PBUF_POOL_BUFSIZE % 4) +#error "PBUF_POOL_BUFSIZE must be modulo 4!" +#endif + +/* RT-Thread Device Interface */ + +/* initialize the interface */ +//***************************************************************************** +// +// Low-Level initialization function for the Ethernet Controller. +// +//***************************************************************************** +rt_err_t luminaryif_init(rt_device_t dev) +{ + unsigned long ulTemp; + + // + // Disable all Ethernet Interrupts. + // + EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX)); + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Initialize the Ethernet Controller. + // + EthernetInitExpClk(ETH_BASE, SysCtlClockGet()); + + // + // Configure the Ethernet Controller for normal operation. + // - Enable TX Duplex Mode + // - Enable TX Padding + // - Enable TX CRC Generation + // + EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | + ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN)); + + // + // Enable the Ethernet Controller transmitter and receiver. + // + EthernetEnable(ETH_BASE); + + // + // Enable the Ethernet Interrupt handler. + // + IntEnable(INT_ETH); + + // + // Enable Ethernet TX and RX Packet Interrupts. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX); + + return RT_EOK; +} + +void luminaryif_isr(void) +{ + unsigned long ulTemp; + + // + // Read and Clear the interrupt. + // + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Check to see if an RX Interrupt has occured. + // + if(ulTemp & ETH_INT_RX) + { + // + // Indicate that a packet has been received. + // + rt_err_t result; + + /* a frame has been received */ + result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent)); + + if(result != RT_EOK) rt_set_errno(-RT_ERROR); + + // + // Disable Ethernet RX Interrupt. + // + EthernetIntDisable(ETH_BASE, ETH_INT_RX); + } + if(ulTemp & ETH_INT_TX) + { + /* A frame has been transmitted. */ + rt_sem_release(&tx_sem); + } + +} + +/* control the interface */ +rt_err_t luminaryif_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, luminaryif_dev_entry.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* Open the ethernet interface */ +rt_err_t luminaryif_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +/* Close the interface */ +rt_err_t luminaryif_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* Read */ +rt_size_t luminaryif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* Write */ +rt_size_t luminaryif_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +//**************************************************************************** +// +// Low-Level transmit routine. Should do the actual transmission of the +// packet. The packet is contained in the pbuf that is passed to the function. +// This pbuf might be chained. +// +//**************************************************************************** +rt_err_t luminaryif_tx(rt_device_t dev, struct pbuf *p) +{ + int iBuf; + unsigned char *pucBuf; + unsigned long *pulBuf; + struct pbuf *q; + int iGather; + unsigned long ulGather; + unsigned char *pucGather; + unsigned long ulTemp; + + /* lock tx operation */ + rt_sem_take(&tx_sem, RT_WAITING_FOREVER); + + // + // Wait for space available in the TX FIFO. + // + while(!EthernetSpaceAvail(ETH_BASE)) + { + } + +// + // Fill in the first two bytes of the payload data (configured as padding + // with ETH_PAD_SIZE = 2) with the total length of the payload data + // (minus the Ethernet MAC layer header). + // + *((unsigned short *)(p->payload)) = p->tot_len - 16; + + // + // Initialize the gather register. + // + iGather = 0; + pucGather = (unsigned char *)&ulGather; + ulGather = 0; + + // + // Copy data from the pbuf(s) into the TX Fifo. + // + for(q = p; q != NULL; q = q->next) + { + // + // Intialize a char pointer and index to the pbuf payload data. + // + pucBuf = (unsigned char *)q->payload; + iBuf = 0; + + // + // If the gather buffer has leftover data from a previous pbuf + // in the chain, fill it up and write it to the Tx FIFO. + // + while((iBuf < q->len) && (iGather != 0)) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + + // + // If the gather index is 0 and the pbuf index is non-zero, + // we have a gather buffer to write into the Tx FIFO. + // + if((iGather == 0) && (iBuf != 0)) + { + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + ulGather = 0; + } + + // + // Copy words of pbuf data into the Tx FIFO, but don't go past + // the end of the pbuf. + // + if((iBuf % 4) != 0) + { + while((iBuf + 4) <= q->len) + { + ulTemp = (pucBuf[iBuf++] << 0); + ulTemp |= (pucBuf[iBuf++] << 8); + ulTemp |= (pucBuf[iBuf++] << 16); + ulTemp |= (pucBuf[iBuf++] << 24); + HWREG(ETH_BASE + MAC_O_DATA) = ulTemp; + } + } + else + { + // + // Initialze a long pointer into the pbuf for 32-bit access. + // + pulBuf = (unsigned long *)&pucBuf[iBuf]; + + while((iBuf + 4) <= q->len) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulBuf++; + iBuf += 4; + } + } + // + // Check if leftover data in the pbuf and save it in the gather + // buffer for the next time. + // + while(iBuf < q->len) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + } + + // + // Send any leftover data to the FIFO. + // + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + + // + // Wakeup the transmitter. + // + HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX; + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif + + return(ERR_OK); +} + +//***************************************************************************** +// +// Low-Level receive routine. Should allocate a pbuf and transfer the bytes +// of the incoming packet from the interface into the pbuf. +// +//***************************************************************************** +struct pbuf * luminaryif_rx(rt_device_t dev) +{ + struct pbuf *p, *q; + u16_t len; + unsigned long ulTemp; + int i; + unsigned long *ptr; + + if(!EthernetPacketAvail(ETH_BASE)) + { + // + // Enable Ethernet RX Interrupt. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return(NULL); + } + + // + // Obtain the size of the packet and put it into the "len" variable. + // Note: The length returned in the FIFO length position includes the + // two bytes for the length + the 4 bytes for the FCS. + // + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + len = ulTemp & 0xFFFF; + + // + // We allocate a pbuf chain of pbufs from the pool. + // + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + + if(p != NULL) + { + // + // Place the first word into the first pbuf location. + // + *(unsigned long *)p->payload = ulTemp; + p->payload = (char *)(p->payload) + 4; + p->len -= 4; + + // + // Process all but the last buffer in the pbuf chain. + // + q = p; + while(q != NULL) + { + // + // Setup a byte pointer into the payload section of the pbuf. + // + ptr = q->payload; + + // + // Read data from FIFO into the current pbuf + // (assume pbuf length is modulo 4) + // + for(i = 0; i < q->len; i += 4) + { + *ptr++ = HWREG(ETH_BASE + MAC_O_DATA); + } + + // + // Link in the next pbuf in the chain. + // + q = q->next; + } + + // + // Restore the first pbuf parameters to their original values. + // + p->payload = (char *)(p->payload) - 4; + p->len += 4; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif + } + else + { + // + // Just read all of the remaining data from the FIFO and dump it. + // + for(i = 4; i < len; i+=4) + { + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + } + +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + } + + return(p); +} + +int rt_hw_luminaryif_init(void) +{ + rt_err_t result; + unsigned long ulUser0, ulUser1; + + /* Enable and Reset the Ethernet Controller. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); + SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); + + /* + Enable Port F for Ethernet LEDs. + LED0 Bit 3 Output + LED1 Bit 2 Output + */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW); + GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, + GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + + FlashUserSet(0x12345678, 0x12345678); + /* Configure the hardware MAC address */ + FlashUserGet(&ulUser0, &ulUser1); + if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff)) + { + rt_kprintf("Fatal error in geting MAC address\n"); + } + + /* init rt-thread device interface */ + luminaryif_dev_entry.parent.parent.init = luminaryif_init; + luminaryif_dev_entry.parent.parent.open = luminaryif_open; + luminaryif_dev_entry.parent.parent.close = luminaryif_close; + luminaryif_dev_entry.parent.parent.read = luminaryif_read; + luminaryif_dev_entry.parent.parent.write = luminaryif_write; + luminaryif_dev_entry.parent.parent.control = luminaryif_control; + luminaryif_dev_entry.parent.eth_rx = luminaryif_rx; + luminaryif_dev_entry.parent.eth_tx = luminaryif_tx; + + /* + Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC + address needed to program the hardware registers, then program the MAC + address into the Ethernet Controller registers. + */ + luminaryif_dev_entry.dev_addr[0] = ((ulUser0 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[1] = ((ulUser0 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[2] = ((ulUser0 >> 16) & 0xff); + luminaryif_dev_entry.dev_addr[3] = ((ulUser1 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[4] = ((ulUser1 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the hardware with it's MAC address (for filtering). */ + EthernetMACAddrSet(ETH_BASE, luminaryif_dev_entry.dev_addr); + + rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); + + result = eth_device_init(&(luminaryif_dev->parent), "E0"); + + return result; +} + diff --git a/bsp/lm3s8962/drivers/luminaryif.h b/bsp/lm3s8962/drivers/luminaryif.h new file mode 100644 index 0000000000..e987daea5e --- /dev/null +++ b/bsp/lm3s8962/drivers/luminaryif.h @@ -0,0 +1,12 @@ +//***************************************************************************** +// +// luminaryif.h - Prototypes for the Luminary Micro Ethernet interface. +// +//***************************************************************************** + +#ifndef __LUMINARYIF_H__ +#define __LUMINARYIF_H__ + +int rt_hw_luminaryif_init(void); + +#endif // __LUMINARYIF_H__ diff --git a/bsp/lm3s8962/drivers/sdcard.c b/bsp/lm3s8962/drivers/sdcard.c new file mode 100644 index 0000000000..785f2eaf3e --- /dev/null +++ b/bsp/lm3s8962/drivers/sdcard.c @@ -0,0 +1,781 @@ +/*-----------------------------------------------------------------------*/ +/* MMC/SDC (in SPI mode) control module (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +/* + * This file was modified from a sample available from the FatFs + * web site. It was modified to work with a Luminary Micro + * EK-LM3S6965 evaluation board. + * + * Note that the SSI port is shared with the osram display. The code + * in this file does not attempt to share the SSI port with the osram, + * it assumes the osram is not being used. + */ +#include + +#include +#include +#include +#include +#include + +/* Status of Disk Functions */ +typedef rt_uint8_t DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Command code for disk_ioctrl() */ + +/* Generic command */ +#define CTRL_SYNC 0 /* Mandatory for write functions */ +#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ +#define GET_SECTOR_SIZE 2 /* Mandatory for multiple sector size cfg */ +#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +/* MMC/SDC command */ +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 +/* ATA/CF command */ +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +/* Peripheral definitions for EK-LM3S6965 board */ +// SSI port +#define SDC_SSI_BASE SSI0_BASE +#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0 + +// GPIO for SSI pins +#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE +#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA +#define SDC_SSI_CLK GPIO_PIN_2 +#define SDC_SSI_TX GPIO_PIN_5 +#define SDC_SSI_RX GPIO_PIN_4 +#define SDC_SSI_FSS GPIO_PIN_3 +#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK) + +// GPIO for card chip select +#define SDC_CS_GPIO_PORT_BASE GPIO_PORTG_BASE +#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOG +#define SDC_CS GPIO_PIN_0 + +// asserts the CS pin to the card +static +void SELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0); +} + +// de-asserts the CS pin to the card +static +void DESELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); +} + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +static volatile +rt_uint8_t Timer1, Timer2; /* 100Hz decrement timer */ + +static +rt_uint8_t CardType; /* b0:MMC, b1:SDC, b2:Block addressing */ + +static +rt_uint8_t PowerFlag = 0; /* indicates if "power" is on */ + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +void xmit_spi (rt_uint8_t dat) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, dat); /* Write the data to the tx fifo */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* flush data read during the write */ +} + + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t rcvr_spi (void) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, 0xFF); /* write dummy data */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */ + + return (rt_uint8_t)rcvdat; +} + + +static +void rcvr_spi_m (rt_uint8_t *dst) +{ + *dst = rcvr_spi(); +} + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t wait_ready (void) +{ + rt_uint8_t res; + + + Timer2 = 50; /* Wait for ready in timeout of 500ms */ + rcvr_spi(); + do + res = rcvr_spi(); + while ((res != 0xFF) && Timer2); + + return res; +} + +/*-----------------------------------------------------------------------*/ +/* Send 80 or so clock transitions with CS and DI held high. This is */ +/* required after card power up to get it into SPI mode */ +/*-----------------------------------------------------------------------*/ +static +void send_initial_clock_train(void) +{ + unsigned int i; + rt_uint32_t dat; + + /* Ensure CS is held high. */ + DESELECT(); + + /* Switch the SSI TX line to a GPIO and drive it high too. */ + GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX); + GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX); + + /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ + /* required number of times. */ + for(i = 0 ; i < 10 ; i++) + { + /* Write DUMMY data. SSIDataPut() waits until there is room in the */ + /* FIFO. */ + SSIDataPut(SDC_SSI_BASE, 0xFF); + + /* Flush data read during data write. */ + SSIDataGet(SDC_SSI_BASE, &dat); + } + + /* Revert to hardware control of the SSI TX line. */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX); +} + +/*-----------------------------------------------------------------------*/ +/* Power Control (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* When the target system does not support socket power control, there */ +/* is nothing to do in these functions and chk_power always returns 1. */ + +static +void power_on (void) +{ + /* + * This doesn't really turn the power on, but initializes the + * SSI port and pins needed to talk to the card. + */ + + /* Enable the peripherals used to drive the SDC on SSI, and the CS */ + SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH); + + /* Configure the appropriate pins to be SSI instead of GPIO */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS); + GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS); + GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + /* Deassert the SSI0 chip select */ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 400000, 8); + SSIEnable(SDC_SSI_BASE); + + /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ + /* to be able to accept a native command. */ + send_initial_clock_train(); + + PowerFlag = 1; +} + +// set the SSI speed to the max setting +static +void set_max_speed(void) +{ + unsigned long i; + + /* Disable the SSI */ + SSIDisable(SDC_SSI_BASE); + + /* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */ + i = SysCtlClockGet() / 2; + if(i > 12500000) + { + i = 12500000; + } + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, i, 8); + + /* Enable the SSI */ + SSIEnable(SDC_SSI_BASE); +} + +static +void power_off (void) +{ + PowerFlag = 0; +} + +static +int chk_power(void) /* Socket power state: 0=off, 1=on */ +{ + return PowerFlag; +} + + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_bool_t rcvr_datablock ( + rt_uint8_t *buff, /* Data buffer to store received data */ + unsigned int btr /* Byte count (must be even number) */ +) +{ + rt_uint8_t token; + + + Timer1 = 10; + do { /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ + + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 2); + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return RT_TRUE; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +static +rt_bool_t xmit_datablock ( + const rt_uint8_t *buff, /* 512 byte data block to be transmitted */ + rt_uint8_t token /* Data/Stop token */ +) +{ + rt_uint8_t resp, wc; + + + if (wait_ready() != 0xFF) return RT_FALSE; + + xmit_spi(token); /* Xmit data token */ + if (token != 0xFD) { /* Is data token */ + wc = 0; + do { /* Xmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Reveive data response */ + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return RT_FALSE; + } + + return RT_TRUE; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t send_cmd ( + rt_uint8_t cmd, /* Command byte */ + rt_uint32_t arg /* Argument */ +) +{ + rt_uint8_t n, res; + + + if (wait_ready() != 0xFF) return 0xFF; + + /* Send command packet */ + xmit_spi(cmd); /* Command */ + xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ + n = 0; + if (cmd == CMD0) n = 0x95; /* CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + res = rcvr_spi(); + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ +static +DSTATUS sdcard_initialize ( + rt_uint8_t drv /* Physical drive nmuber (0) */ +) +{ + rt_uint8_t n, ty, ocr[4]; + + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on */ + send_initial_clock_train(); + + SELECT(); /* CS = L */ + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 msec */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDC Ver2+ */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ + do { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0) break; /* ACMD41 with HCS bit */ + } while (Timer1); + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? 6 : 2; + } + } + } else { /* SDC Ver1 or MMC */ + ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */ + do { + if (ty == 2) { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break; /* ACMD41 */ + } else { + if (send_cmd(CMD1, 0) == 0) break; /* CMD1 */ + } + } while (Timer1); + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Select R/W block length */ + ty = 0; + } + } + CardType = ty; + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + if (ty) { /* Initialization succeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + set_max_speed(); + } else { /* Initialization failed */ + power_off(); + } + + return Stat; +} + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ +static +DRESULT sdcard_read ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t *buff, /* Pointer to the data buffer to store read data */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block read */ + if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ + && rcvr_datablock(buff, 512)) + count = 0; + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) break; + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +static +DRESULT sdcard_write ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + const rt_uint8_t *buff, /* Pointer to the data to be written */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block write */ + if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buff, 0xFE)) + count = 0; + } + else { /* Multiple block write */ + if (CardType & 2) { + send_cmd(CMD55, 0); send_cmd(CMD23, count); /* ACMD23 */ + } + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ +static +DRESULT sdcard_ioctl ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + rt_uint8_t n, csd[16], *ptr = buff; + rt_uint16_t csize; + + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (*ptr) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + if (chk_power()) + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code == 1 (POWER_ON) */ + power_on(); /* Power on */ + res = RES_OK; + break; + case 2: /* Sub control code == 2 (POWER_GET) */ + *(ptr+1) = (rt_uint8_t)chk_power(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) return RES_NOTRDY; + + SELECT(); /* CS = L */ + + switch (ctrl) { + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (rt_uint32_t) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ + csize = csd[9] + ((rt_uint16_t)csd[8] << 8) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << 10; + } else { /* MMC or SDC ver 1.XX */ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((rt_uint16_t)csd[7] << 2) + ((rt_uint16_t)(csd[6] & 3) << 10) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << (n - 9); + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get sectors on the disk (rt_uint16_t) */ + *(rt_uint16_t*)buff = 512; + res = RES_OK; + break; + + case CTRL_SYNC : /* Make sure that data has been written */ + if (wait_ready() == 0xFF) + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 0; n < 4; n++) + *ptr++ = rcvr_spi(); + res = RES_OK; + } + +// case MMC_GET_TYPE : /* Get card type flags (1 byte) */ +// *ptr = CardType; +// res = RES_OK; +// break; + + default: + res = RES_PARERR; + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + } + + return res; +} + +/* + * RT-Thread SD Card Driver + * 20090705 Yi.Qiu + */ +#include +#include + +struct rt_device sdcard_device; +struct dfs_partition part; + +/* RT-Thread Device Driver Interface */ +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + DRESULT status; + + status = sdcard_read(0, buffer, part.offset + pos, size); + if (status != RES_OK) + { + rt_kprintf("sd card read failed\n"); + return 0; + } + + return size; +} + +static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + DRESULT status; + + status = sdcard_write(0, buffer, part.offset + pos, size); + if (status != RES_OK) + { + rt_kprintf("sd card write failed\n"); + return 0; + } + + return size; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +void rt_hw_sdcard_init(void) +{ + if (sdcard_initialize(0) == RES_OK) + { + DRESULT status; + rt_uint8_t *sector; + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + status = sdcard_read(0, sector, 0, 1); + if (status == RES_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + { + /* there is no partition */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sdcard device */ + sdcard_device.type = RT_Device_Class_Block; + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; + + /* no private */ + sdcard_device.user_data = RT_NULL; + + rt_device_register(&sdcard_device, "sd0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + return; + } + rt_kprintf("sdcard init failed\n"); +} + diff --git a/bsp/lm3s8962/drivers/serial.c b/bsp/lm3s8962/drivers/serial.c new file mode 100644 index 0000000000..8572814925 --- /dev/null +++ b/bsp/lm3s8962/drivers/serial.c @@ -0,0 +1,362 @@ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-06-11 Bernard first version + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "board.h" + +extern void rt_hw_interrupt_thread_switch(void); + +#define RT_UART_RX_BUFFER_SIZE 64 + +/* LM3S serial device */ +struct rt_lm3s_serial +{ + /* inherit from device */ + struct rt_device parent; + + rt_uint32_t hw_base; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; + +#ifdef RT_USING_UART1 +struct rt_lm3s_serial serial1; +#endif +#ifdef RT_USING_UART2 +struct rt_lm3s_serial serial2; +#endif + +void rt_hw_serial_init(void); + +void rt_hw_uart_isr(struct rt_lm3s_serial* serial) +{ + rt_device_t device; + rt_uint32_t status; + + device = (struct rt_device*)serial; + status = UARTIntStatus(serial->hw_base, true); + + /* clear interrupt status */ + UARTIntClear(serial->hw_base, status); + + if (device->flag & RT_DEVICE_FLAG_INT_RX) + { + char ch; + rt_base_t level; + + while (UARTCharsAvail(serial->hw_base)) + { + ch = UARTCharGetNonBlocking(serial->hw_base); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + serial->rx_buffer[serial->save_index] = ch; + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if(device->rx_indicate != RT_NULL) + { + rt_int32_t length; + + length = serial->save_index - serial->read_index; + if (length < 0) length += RT_UART_RX_BUFFER_SIZE; + device->rx_indicate(device, length); + } + } +} + +#ifdef RT_USING_UART1 +void rt_hw_uart_isr_1(int irqno) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* get serial device */ + rt_hw_uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} +#endif + +#ifdef RT_USING_UART2 +void rt_hw_uart_isr_2(int irqno) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* get serial device */ + rt_hw_uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} +#endif + +/** + * @addtogroup LM3S + */ +/*@{*/ + +static rt_err_t rt_serial_init (rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; + + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + if (serial->hw_base == UART0_BASE) + IntEnable(INT_UART0); + else if (serial->hw_base == UART1_BASE) + IntEnable(INT_UART1); + + UARTIntEnable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; + + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size) + { + *ptr = UARTCharGetNonBlocking(serial->hw_base); + + ptr ++; size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + struct rt_lm3s_serial* serial; + char *ptr; + + serial = (struct rt_lm3s_serial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); + + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_hw_serial_init(void) +{ + struct rt_lm3s_serial* serial; + +#ifdef RT_USING_UART1 + serial = &serial1; + + serial->parent.type = RT_Device_Class_Char; + + serial->hw_base = UART0_BASE; + serial->baudrate = 115200; + + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; + + /* enable UART0 clock */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* set UART0 pinmux */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); + + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; + + rt_device_register(&serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + +#ifdef RT_USING_UART2 + serial = &serial2; + + serial->parent.type = RT_Device_Class_Char; + + serial->hw_base = 0xE0010000; + serial->baudrate = 115200; + + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; + + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; + + rt_device_register(&serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif +} + +/*@}*/ diff --git a/bsp/lm3s8962/luminaryif.c b/bsp/lm3s8962/luminaryif.c deleted file mode 100644 index 6038059179..0000000000 --- a/bsp/lm3s8962/luminaryif.c +++ /dev/null @@ -1,489 +0,0 @@ -//***************************************************************************** -// -// luminaryif.c - Ethernet Interface File for lwIP TCP/IP Stack -// -//***************************************************************************** - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "lwipopts.h" -#include "luminaryif.h" - -#define MAX_ADDR_LEN 6 - -struct net_device -{ - /* inherit from ethernet device */ - struct eth_device parent; - - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ -}; - -static struct net_device luminaryif_dev_entry; -static struct net_device *luminaryif_dev =&luminaryif_dev_entry; -static struct rt_semaphore tx_sem; - -//***************************************************************************** -// -// Sanity Check: This module will NOT work if the following defines -// are incorrect. -// -//***************************************************************************** -#if (PBUF_LINK_HLEN != 16) -#error "Incorrect PBUF_LINK_HLEN specified!" -#endif -#if (ETH_PAD_SIZE != 2) -#error "Incorrect ETH_PAD_SIZE specified!" -#endif -#if (PBUF_POOL_BUFSIZE % 4) -#error "PBUF_POOL_BUFSIZE must be modulo 4!" -#endif - -/* RT-Thread Device Interface */ - -/* initialize the interface */ -//***************************************************************************** -// -// Low-Level initialization function for the Ethernet Controller. -// -//***************************************************************************** -rt_err_t luminaryif_init(rt_device_t dev) -{ - unsigned long ulTemp; - - // - // Disable all Ethernet Interrupts. - // - EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | - ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | - ETH_INT_RX)); - ulTemp = EthernetIntStatus(ETH_BASE, false); - EthernetIntClear(ETH_BASE, ulTemp); - - // - // Initialize the Ethernet Controller. - // - EthernetInitExpClk(ETH_BASE, SysCtlClockGet()); - - // - // Configure the Ethernet Controller for normal operation. - // - Enable TX Duplex Mode - // - Enable TX Padding - // - Enable TX CRC Generation - // - EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | - ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN)); - - // - // Enable the Ethernet Controller transmitter and receiver. - // - EthernetEnable(ETH_BASE); - - // - // Enable the Ethernet Interrupt handler. - // - IntEnable(INT_ETH); - - // - // Enable Ethernet TX and RX Packet Interrupts. - // - EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX); - - return RT_EOK; -} - -void luminaryif_isr(void) -{ - unsigned long ulTemp; - - // - // Read and Clear the interrupt. - // - ulTemp = EthernetIntStatus(ETH_BASE, false); - EthernetIntClear(ETH_BASE, ulTemp); - - // - // Check to see if an RX Interrupt has occured. - // - if(ulTemp & ETH_INT_RX) - { - // - // Indicate that a packet has been received. - // - rt_err_t result; - - /* a frame has been received */ - result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent)); - - if(result != RT_EOK) rt_set_errno(-RT_ERROR); - - // - // Disable Ethernet RX Interrupt. - // - EthernetIntDisable(ETH_BASE, ETH_INT_RX); - } - if(ulTemp & ETH_INT_TX) - { - /* A frame has been transmitted. */ - rt_sem_release(&tx_sem); - } - -} - -/* control the interface */ -rt_err_t luminaryif_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, luminaryif_dev_entry.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -/* Open the ethernet interface */ -rt_err_t luminaryif_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -/* Close the interface */ -rt_err_t luminaryif_close(rt_device_t dev) -{ - return RT_EOK; -} - -/* Read */ -rt_size_t luminaryif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -/* Write */ -rt_size_t luminaryif_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -//**************************************************************************** -// -// Low-Level transmit routine. Should do the actual transmission of the -// packet. The packet is contained in the pbuf that is passed to the function. -// This pbuf might be chained. -// -//**************************************************************************** -rt_err_t luminaryif_tx(rt_device_t dev, struct pbuf *p) -{ - int iBuf; - unsigned char *pucBuf; - unsigned long *pulBuf; - struct pbuf *q; - int iGather; - unsigned long ulGather; - unsigned char *pucGather; - unsigned long ulTemp; - - /* lock tx operation */ - rt_sem_take(&tx_sem, RT_WAITING_FOREVER); - - // - // Wait for space available in the TX FIFO. - // - while(!EthernetSpaceAvail(ETH_BASE)) - { - } - -// - // Fill in the first two bytes of the payload data (configured as padding - // with ETH_PAD_SIZE = 2) with the total length of the payload data - // (minus the Ethernet MAC layer header). - // - *((unsigned short *)(p->payload)) = p->tot_len - 16; - - // - // Initialize the gather register. - // - iGather = 0; - pucGather = (unsigned char *)&ulGather; - ulGather = 0; - - // - // Copy data from the pbuf(s) into the TX Fifo. - // - for(q = p; q != NULL; q = q->next) - { - // - // Intialize a char pointer and index to the pbuf payload data. - // - pucBuf = (unsigned char *)q->payload; - iBuf = 0; - - // - // If the gather buffer has leftover data from a previous pbuf - // in the chain, fill it up and write it to the Tx FIFO. - // - while((iBuf < q->len) && (iGather != 0)) - { - // - // Copy a byte from the pbuf into the gather buffer. - // - pucGather[iGather] = pucBuf[iBuf++]; - - // - // Increment the gather buffer index modulo 4. - // - iGather = ((iGather + 1) % 4); - } - - // - // If the gather index is 0 and the pbuf index is non-zero, - // we have a gather buffer to write into the Tx FIFO. - // - if((iGather == 0) && (iBuf != 0)) - { - HWREG(ETH_BASE + MAC_O_DATA) = ulGather; - ulGather = 0; - } - - // - // Copy words of pbuf data into the Tx FIFO, but don't go past - // the end of the pbuf. - // - if((iBuf % 4) != 0) - { - while((iBuf + 4) <= q->len) - { - ulTemp = (pucBuf[iBuf++] << 0); - ulTemp |= (pucBuf[iBuf++] << 8); - ulTemp |= (pucBuf[iBuf++] << 16); - ulTemp |= (pucBuf[iBuf++] << 24); - HWREG(ETH_BASE + MAC_O_DATA) = ulTemp; - } - } - else - { - // - // Initialze a long pointer into the pbuf for 32-bit access. - // - pulBuf = (unsigned long *)&pucBuf[iBuf]; - - while((iBuf + 4) <= q->len) - { - HWREG(ETH_BASE + MAC_O_DATA) = *pulBuf++; - iBuf += 4; - } - } - // - // Check if leftover data in the pbuf and save it in the gather - // buffer for the next time. - // - while(iBuf < q->len) - { - // - // Copy a byte from the pbuf into the gather buffer. - // - pucGather[iGather] = pucBuf[iBuf++]; - - // - // Increment the gather buffer index modulo 4. - // - iGather = ((iGather + 1) % 4); - } - } - - // - // Send any leftover data to the FIFO. - // - HWREG(ETH_BASE + MAC_O_DATA) = ulGather; - - // - // Wakeup the transmitter. - // - HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX; - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif - - return(ERR_OK); -} - -//***************************************************************************** -// -// Low-Level receive routine. Should allocate a pbuf and transfer the bytes -// of the incoming packet from the interface into the pbuf. -// -//***************************************************************************** -struct pbuf * luminaryif_rx(rt_device_t dev) -{ - struct pbuf *p, *q; - u16_t len; - unsigned long ulTemp; - int i; - unsigned long *ptr; - - if(!EthernetPacketAvail(ETH_BASE)) - { - // - // Enable Ethernet RX Interrupt. - // - EthernetIntEnable(ETH_BASE, ETH_INT_RX); - - return(NULL); - } - - // - // Obtain the size of the packet and put it into the "len" variable. - // Note: The length returned in the FIFO length position includes the - // two bytes for the length + the 4 bytes for the FCS. - // - ulTemp = HWREG(ETH_BASE + MAC_O_DATA); - len = ulTemp & 0xFFFF; - - // - // We allocate a pbuf chain of pbufs from the pool. - // - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - - if(p != NULL) - { - // - // Place the first word into the first pbuf location. - // - *(unsigned long *)p->payload = ulTemp; - p->payload = (char *)(p->payload) + 4; - p->len -= 4; - - // - // Process all but the last buffer in the pbuf chain. - // - q = p; - while(q != NULL) - { - // - // Setup a byte pointer into the payload section of the pbuf. - // - ptr = q->payload; - - // - // Read data from FIFO into the current pbuf - // (assume pbuf length is modulo 4) - // - for(i = 0; i < q->len; i += 4) - { - *ptr++ = HWREG(ETH_BASE + MAC_O_DATA); - } - - // - // Link in the next pbuf in the chain. - // - q = q->next; - } - - // - // Restore the first pbuf parameters to their original values. - // - p->payload = (char *)(p->payload) - 4; - p->len += 4; - -#if LINK_STATS - lwip_stats.link.recv++; -#endif - } - else - { - // - // Just read all of the remaining data from the FIFO and dump it. - // - for(i = 4; i < len; i+=4) - { - ulTemp = HWREG(ETH_BASE + MAC_O_DATA); - } - -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif - } - - return(p); -} - -int rt_hw_luminaryif_init(void) -{ - rt_err_t result; - unsigned long ulUser0, ulUser1; - - /* Enable and Reset the Ethernet Controller. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); - SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); - - /* - Enable Port F for Ethernet LEDs. - LED0 Bit 3 Output - LED1 Bit 2 Output - */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); - GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW); - GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, - GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); - - FlashUserSet(0x12345678, 0x12345678); - /* Configure the hardware MAC address */ - FlashUserGet(&ulUser0, &ulUser1); - if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff)) - { - rt_kprintf("Fatal error in geting MAC address\n"); - } - - /* init rt-thread device interface */ - luminaryif_dev_entry.parent.parent.init = luminaryif_init; - luminaryif_dev_entry.parent.parent.open = luminaryif_open; - luminaryif_dev_entry.parent.parent.close = luminaryif_close; - luminaryif_dev_entry.parent.parent.read = luminaryif_read; - luminaryif_dev_entry.parent.parent.write = luminaryif_write; - luminaryif_dev_entry.parent.parent.control = luminaryif_control; - luminaryif_dev_entry.parent.eth_rx = luminaryif_rx; - luminaryif_dev_entry.parent.eth_tx = luminaryif_tx; - - /* - Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC - address needed to program the hardware registers, then program the MAC - address into the Ethernet Controller registers. - */ - luminaryif_dev_entry.dev_addr[0] = ((ulUser0 >> 0) & 0xff); - luminaryif_dev_entry.dev_addr[1] = ((ulUser0 >> 8) & 0xff); - luminaryif_dev_entry.dev_addr[2] = ((ulUser0 >> 16) & 0xff); - luminaryif_dev_entry.dev_addr[3] = ((ulUser1 >> 0) & 0xff); - luminaryif_dev_entry.dev_addr[4] = ((ulUser1 >> 8) & 0xff); - luminaryif_dev_entry.dev_addr[5] = ((ulUser1 >> 16) & 0xff); - - /* Program the hardware with it's MAC address (for filtering). */ - EthernetMACAddrSet(ETH_BASE, luminaryif_dev_entry.dev_addr); - - rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); - - result = eth_device_init(&(luminaryif_dev->parent), "E0"); - - return result; -} - diff --git a/bsp/lm3s8962/luminaryif.h b/bsp/lm3s8962/luminaryif.h deleted file mode 100644 index e987daea5e..0000000000 --- a/bsp/lm3s8962/luminaryif.h +++ /dev/null @@ -1,12 +0,0 @@ -//***************************************************************************** -// -// luminaryif.h - Prototypes for the Luminary Micro Ethernet interface. -// -//***************************************************************************** - -#ifndef __LUMINARYIF_H__ -#define __LUMINARYIF_H__ - -int rt_hw_luminaryif_init(void); - -#endif // __LUMINARYIF_H__ diff --git a/bsp/lm3s8962/project.Uv2 b/bsp/lm3s8962/project.Uv2 index 5ec5957925..16179a344b 100644 --- a/bsp/lm3s8962/project.Uv2 +++ b/bsp/lm3s8962/project.Uv2 @@ -3,130 +3,122 @@ Target (RT-Thread-lm3s), 0x0004 // Tools: 'ARM-ADS' -Group (Startup) +Group (Applications) +Group (Drivers) +Group (Libraries) Group (Kernel) -Group (LM3S) +Group (CORTEX-M3) Group (Filesystem) Group (finsh) Group (LwIP) -Group (library) - -File 1,1,<.\application.c> -File 1,1,<.\startup.c> -File 1,1,<.\board.c> -File 1,1,<.\sdcard.c> -File 1,1,<.\luminaryif.c> -File 2,1,<..\..\src\clock.c> -File 2,1,<..\..\src\device.c> -File 2,1,<..\..\src\idle.c> -File 2,1,<..\..\src\ipc.c> -File 2,1,<..\..\src\irq.c> -File 2,1,<..\..\src\kservice.c> -File 2,1,<..\..\src\mem.c> -File 2,1,<..\..\src\mempool.c> -File 2,1,<..\..\src\module.c> -File 2,1,<..\..\src\object.c> -File 2,1,<..\..\src\rtm.c> -File 2,1,<..\..\src\scheduler.c> -File 2,1,<..\..\src\slab.c> -File 2,1,<..\..\src\thread.c> -File 2,1,<..\..\src\timer.c> -File 3,1,<..\..\libcpu\arm\lm3s\cpu.c> -File 3,1,<..\..\libcpu\arm\lm3s\fault.c> -File 3,1,<..\..\libcpu\arm\lm3s\interrupt.c> -File 3,1,<..\..\libcpu\arm\lm3s\serial.c> -File 3,1,<..\..\libcpu\arm\lm3s\stack.c> -File 3,2,<..\..\libcpu\arm\lm3s\context_rvds.S> -File 3,2,<..\..\libcpu\arm\lm3s\fault_rvds.S> -File 3,2,<..\..\libcpu\arm\lm3s\start_rvds.S> -File 3,1,<..\..\libcpu\arm\common\backtrace.c> -File 3,1,<..\..\libcpu\arm\common\div0.c> -File 3,1,<..\..\libcpu\arm\common\showmem.c> -File 4,1,<..\..\components\dfs\src\dfs.c> -File 4,1,<..\..\components\dfs\src\dfs_fs.c> -File 4,1,<..\..\components\dfs\src\dfs_file.c> -File 4,1,<..\..\components\dfs\src\dfs_posix.c> -File 4,1,<..\..\components\dfs\filesystems\elmfat\dfs_elm.c> -File 4,1,<..\..\components\dfs\filesystems\elmfat\ff.c> -File 5,1,<..\..\components\finsh\cmd.c> -File 5,1,<..\..\components\finsh\finsh_compiler.c> -File 5,1,<..\..\components\finsh\finsh_error.c> -File 5,1,<..\..\components\finsh\finsh_heap.c> -File 5,1,<..\..\components\finsh\finsh_init.c> -File 5,1,<..\..\components\finsh\finsh_node.c> -File 5,1,<..\..\components\finsh\finsh_ops.c> -File 5,1,<..\..\components\finsh\finsh_parser.c> -File 5,1,<..\..\components\finsh\finsh_token.c> -File 5,1,<..\..\components\finsh\finsh_var.c> -File 5,1,<..\..\components\finsh\finsh_vm.c> -File 5,1,<..\..\components\finsh\shell.c> -File 5,1,<..\..\components\finsh\symbol.c> -File 6,1,<..\..\components\net\lwip\src\api\api_lib.c> -File 6,1,<..\..\components\net\lwip\src\api\api_msg.c> -File 6,1,<..\..\components\net\lwip\src\api\err.c> -File 6,1,<..\..\components\net\lwip\src\api\netbuf.c> -File 6,1,<..\..\components\net\lwip\src\api\netdb.c> -File 6,1,<..\..\components\net\lwip\src\api\netifapi.c> -File 6,1,<..\..\components\net\lwip\src\api\sockets.c> -File 6,1,<..\..\components\net\lwip\src\api\tcpip.c> -File 6,1,<..\..\components\net\lwip\src\arch\sys_arch.c> -File 6,1,<..\..\components\net\lwip\src\arch\sys_arch_init.c> -File 6,1,<..\..\components\net\lwip\src\core\dhcp.c> -File 6,1,<..\..\components\net\lwip\src\core\dns.c> -File 6,1,<..\..\components\net\lwip\src\core\init.c> -File 6,1,<..\..\components\net\lwip\src\core\memp.c> -File 6,1,<..\..\components\net\lwip\src\core\netif.c> -File 6,1,<..\..\components\net\lwip\src\core\pbuf.c> -File 6,1,<..\..\components\net\lwip\src\core\raw.c> -File 6,1,<..\..\components\net\lwip\src\core\stats.c> -File 6,1,<..\..\components\net\lwip\src\core\sys.c> -File 6,1,<..\..\components\net\lwip\src\core\tcp.c> -File 6,1,<..\..\components\net\lwip\src\core\tcp_in.c> -File 6,1,<..\..\components\net\lwip\src\core\tcp_out.c> -File 6,1,<..\..\components\net\lwip\src\core\udp.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\autoip.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\icmp.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\igmp.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\inet.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c> -File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c> -File 6,1,<..\..\components\net\lwip\src\netif\etharp.c> -File 6,1,<..\..\components\net\lwip\src\netif\ethernetif.c> -File 6,1,<..\..\components\net\lwip\src\netif\loopif.c> -File 6,1,<..\..\components\net\lwip\src\netif\slipif.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\mib2.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c> -File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c> -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, -File 7,1, - +File 1,1, +File 1,1, +File 2,1, +File 2,1, +File 2,1, +File 2,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,2, +File 4,1,<..\..\src\clock.c> +File 4,1,<..\..\src\device.c> +File 4,1,<..\..\src\idle.c> +File 4,1,<..\..\src\ipc.c> +File 4,1,<..\..\src\irq.c> +File 4,1,<..\..\src\kservice.c> +File 4,1,<..\..\src\mem.c> +File 4,1,<..\..\src\mempool.c> +File 4,1,<..\..\src\object.c> +File 4,1,<..\..\src\scheduler.c> +File 4,1,<..\..\src\thread.c> +File 4,1,<..\..\src\timer.c> +File 5,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> +File 5,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> +File 5,1,<..\..\libcpu\arm\common\backtrace.c> +File 5,1,<..\..\libcpu\arm\common\div0.c> +File 5,1,<..\..\libcpu\arm\common\showmem.c> +File 6,1,<..\..\components\dfs\src\dfs.c> +File 6,1,<..\..\components\dfs\src\dfs_fs.c> +File 6,1,<..\..\components\dfs\src\dfs_file.c> +File 6,1,<..\..\components\dfs\src\dfs_posix.c> +File 6,1,<..\..\components\dfs\filesystems\elmfat\dfs_elm.c> +File 6,1,<..\..\components\dfs\filesystems\elmfat\ff.c> +File 7,1,<..\..\components\finsh\cmd.c> +File 7,1,<..\..\components\finsh\finsh_compiler.c> +File 7,1,<..\..\components\finsh\finsh_error.c> +File 7,1,<..\..\components\finsh\finsh_heap.c> +File 7,1,<..\..\components\finsh\finsh_init.c> +File 7,1,<..\..\components\finsh\finsh_node.c> +File 7,1,<..\..\components\finsh\finsh_ops.c> +File 7,1,<..\..\components\finsh\finsh_parser.c> +File 7,1,<..\..\components\finsh\finsh_token.c> +File 7,1,<..\..\components\finsh\finsh_var.c> +File 7,1,<..\..\components\finsh\finsh_vm.c> +File 7,1,<..\..\components\finsh\shell.c> +File 7,1,<..\..\components\finsh\symbol.c> +File 8,1,<..\..\components\net\lwip\src\api\api_lib.c> +File 8,1,<..\..\components\net\lwip\src\api\api_msg.c> +File 8,1,<..\..\components\net\lwip\src\api\err.c> +File 8,1,<..\..\components\net\lwip\src\api\netbuf.c> +File 8,1,<..\..\components\net\lwip\src\api\netdb.c> +File 8,1,<..\..\components\net\lwip\src\api\netifapi.c> +File 8,1,<..\..\components\net\lwip\src\api\sockets.c> +File 8,1,<..\..\components\net\lwip\src\api\tcpip.c> +File 8,1,<..\..\components\net\lwip\src\arch\sys_arch.c> +File 8,1,<..\..\components\net\lwip\src\arch\sys_arch_init.c> +File 8,1,<..\..\components\net\lwip\src\core\dhcp.c> +File 8,1,<..\..\components\net\lwip\src\core\dns.c> +File 8,1,<..\..\components\net\lwip\src\core\init.c> +File 8,1,<..\..\components\net\lwip\src\core\memp.c> +File 8,1,<..\..\components\net\lwip\src\core\netif.c> +File 8,1,<..\..\components\net\lwip\src\core\pbuf.c> +File 8,1,<..\..\components\net\lwip\src\core\raw.c> +File 8,1,<..\..\components\net\lwip\src\core\stats.c> +File 8,1,<..\..\components\net\lwip\src\core\sys.c> +File 8,1,<..\..\components\net\lwip\src\core\tcp.c> +File 8,1,<..\..\components\net\lwip\src\core\tcp_in.c> +File 8,1,<..\..\components\net\lwip\src\core\tcp_out.c> +File 8,1,<..\..\components\net\lwip\src\core\udp.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\autoip.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\icmp.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\igmp.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\inet.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\ip.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c> +File 8,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c> +File 8,1,<..\..\components\net\lwip\src\netif\etharp.c> +File 8,1,<..\..\components\net\lwip\src\netif\ethernetif.c> +File 8,1,<..\..\components\net\lwip\src\netif\loopif.c> +File 8,1,<..\..\components\net\lwip\src\netif\slipif.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\mib2.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c> +File 8,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c> Options 1,0,0 // Target 'RT-Thread-lm3s' @@ -154,7 +146,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' EnvReg (Luminary\) OrgReg (Luminary\) TgStat=16 - OutDir (.\objs\) + OutDir (.\build\) OutName (rtthread-lm3s) GenApp=1 GenLib=0 @@ -176,7 +168,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ACPUTYP ("Cortex-M3") RVDEV () - ADSTFLGA { 0,12,0,0,160,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSTFLGA { 0,12,0,0,163,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } OCMADSIROM { 1,0,0,0,0,0,0,4,0 } @@ -187,7 +179,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' ADSCMISC () ADSCDEFN () ADSCUDEF () - ADSCINCD (Libraries\inc;..\..\include;..\..\libcpu\arm\lm3s;..\..\components\net\lwip\src\include;Libraries\driverlib;.;..\..\components\net\lwip\src\include\ipv4;..\..\components\dfs;Libraries;..\..\components\net\lwip\src\arch\include;..\..\components\dfs\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif) + ADSCINCD (..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\include;drivers;..\..\components\dfs;.;Libraries;applications;..\..\components\net\lwip\src\arch\include;..\..\libcpu\arm\cortex-m3;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif;..\..\components\dfs\include) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSAMISC () ADSADEFN () diff --git a/bsp/lm3s8962/rtconfig.py b/bsp/lm3s8962/rtconfig.py index 1fdb67c4bb..caef9a28a4 100644 --- a/bsp/lm3s8962/rtconfig.py +++ b/bsp/lm3s8962/rtconfig.py @@ -1,6 +1,6 @@ # toolchains options ARCH='arm' -CPU='lm3s' +CPU='cortex-m3' CROSS_TOOL = 'keil' if CROSS_TOOL == 'gcc': diff --git a/bsp/lm3s8962/sdcard.c b/bsp/lm3s8962/sdcard.c deleted file mode 100644 index 785f2eaf3e..0000000000 --- a/bsp/lm3s8962/sdcard.c +++ /dev/null @@ -1,781 +0,0 @@ -/*-----------------------------------------------------------------------*/ -/* MMC/SDC (in SPI mode) control module (C)ChaN, 2007 */ -/*-----------------------------------------------------------------------*/ -/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ -/* are platform dependent. */ -/*-----------------------------------------------------------------------*/ - -/* - * This file was modified from a sample available from the FatFs - * web site. It was modified to work with a Luminary Micro - * EK-LM3S6965 evaluation board. - * - * Note that the SSI port is shared with the osram display. The code - * in this file does not attempt to share the SSI port with the osram, - * it assumes the osram is not being used. - */ -#include - -#include -#include -#include -#include -#include - -/* Status of Disk Functions */ -typedef rt_uint8_t DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - -/* Disk Status Bits (DSTATUS) */ - -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - -/* Definitions for MMC/SDC command */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ - -/* Command code for disk_ioctrl() */ - -/* Generic command */ -#define CTRL_SYNC 0 /* Mandatory for write functions */ -#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ -#define GET_SECTOR_SIZE 2 /* Mandatory for multiple sector size cfg */ -#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ -#define CTRL_POWER 4 -#define CTRL_LOCK 5 -#define CTRL_EJECT 6 -/* MMC/SDC command */ -#define MMC_GET_TYPE 10 -#define MMC_GET_CSD 11 -#define MMC_GET_CID 12 -#define MMC_GET_OCR 13 -#define MMC_GET_SDSTAT 14 -/* ATA/CF command */ -#define ATA_GET_REV 20 -#define ATA_GET_MODEL 21 -#define ATA_GET_SN 22 - -/* Peripheral definitions for EK-LM3S6965 board */ -// SSI port -#define SDC_SSI_BASE SSI0_BASE -#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0 - -// GPIO for SSI pins -#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE -#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA -#define SDC_SSI_CLK GPIO_PIN_2 -#define SDC_SSI_TX GPIO_PIN_5 -#define SDC_SSI_RX GPIO_PIN_4 -#define SDC_SSI_FSS GPIO_PIN_3 -#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK) - -// GPIO for card chip select -#define SDC_CS_GPIO_PORT_BASE GPIO_PORTG_BASE -#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOG -#define SDC_CS GPIO_PIN_0 - -// asserts the CS pin to the card -static -void SELECT (void) -{ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0); -} - -// de-asserts the CS pin to the card -static -void DESELECT (void) -{ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); -} - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - -static volatile -DSTATUS Stat = STA_NOINIT; /* Disk status */ - -static volatile -rt_uint8_t Timer1, Timer2; /* 100Hz decrement timer */ - -static -rt_uint8_t CardType; /* b0:MMC, b1:SDC, b2:Block addressing */ - -static -rt_uint8_t PowerFlag = 0; /* indicates if "power" is on */ - -/*-----------------------------------------------------------------------*/ -/* Transmit a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -void xmit_spi (rt_uint8_t dat) -{ - rt_uint32_t rcvdat; - - SSIDataPut(SDC_SSI_BASE, dat); /* Write the data to the tx fifo */ - - SSIDataGet(SDC_SSI_BASE, &rcvdat); /* flush data read during the write */ -} - - -/*-----------------------------------------------------------------------*/ -/* Receive a byte from MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t rcvr_spi (void) -{ - rt_uint32_t rcvdat; - - SSIDataPut(SDC_SSI_BASE, 0xFF); /* write dummy data */ - - SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */ - - return (rt_uint8_t)rcvdat; -} - - -static -void rcvr_spi_m (rt_uint8_t *dst) -{ - *dst = rcvr_spi(); -} - -/*-----------------------------------------------------------------------*/ -/* Wait for card ready */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t wait_ready (void) -{ - rt_uint8_t res; - - - Timer2 = 50; /* Wait for ready in timeout of 500ms */ - rcvr_spi(); - do - res = rcvr_spi(); - while ((res != 0xFF) && Timer2); - - return res; -} - -/*-----------------------------------------------------------------------*/ -/* Send 80 or so clock transitions with CS and DI held high. This is */ -/* required after card power up to get it into SPI mode */ -/*-----------------------------------------------------------------------*/ -static -void send_initial_clock_train(void) -{ - unsigned int i; - rt_uint32_t dat; - - /* Ensure CS is held high. */ - DESELECT(); - - /* Switch the SSI TX line to a GPIO and drive it high too. */ - GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX); - GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX); - - /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ - /* required number of times. */ - for(i = 0 ; i < 10 ; i++) - { - /* Write DUMMY data. SSIDataPut() waits until there is room in the */ - /* FIFO. */ - SSIDataPut(SDC_SSI_BASE, 0xFF); - - /* Flush data read during data write. */ - SSIDataGet(SDC_SSI_BASE, &dat); - } - - /* Revert to hardware control of the SSI TX line. */ - GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX); -} - -/*-----------------------------------------------------------------------*/ -/* Power Control (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -/* When the target system does not support socket power control, there */ -/* is nothing to do in these functions and chk_power always returns 1. */ - -static -void power_on (void) -{ - /* - * This doesn't really turn the power on, but initializes the - * SSI port and pins needed to talk to the card. - */ - - /* Enable the peripherals used to drive the SDC on SSI, and the CS */ - SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH); - SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH); - SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH); - - /* Configure the appropriate pins to be SSI instead of GPIO */ - GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS); - GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS); - GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - /* Deassert the SSI0 chip select */ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); - - /* Configure the SSI0 port */ - SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, - SSI_MODE_MASTER, 400000, 8); - SSIEnable(SDC_SSI_BASE); - - /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ - /* to be able to accept a native command. */ - send_initial_clock_train(); - - PowerFlag = 1; -} - -// set the SSI speed to the max setting -static -void set_max_speed(void) -{ - unsigned long i; - - /* Disable the SSI */ - SSIDisable(SDC_SSI_BASE); - - /* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */ - i = SysCtlClockGet() / 2; - if(i > 12500000) - { - i = 12500000; - } - - /* Configure the SSI0 port */ - SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, - SSI_MODE_MASTER, i, 8); - - /* Enable the SSI */ - SSIEnable(SDC_SSI_BASE); -} - -static -void power_off (void) -{ - PowerFlag = 0; -} - -static -int chk_power(void) /* Socket power state: 0=off, 1=on */ -{ - return PowerFlag; -} - - - -/*-----------------------------------------------------------------------*/ -/* Receive a data packet from MMC */ -/*-----------------------------------------------------------------------*/ - -static -rt_bool_t rcvr_datablock ( - rt_uint8_t *buff, /* Data buffer to store received data */ - unsigned int btr /* Byte count (must be even number) */ -) -{ - rt_uint8_t token; - - - Timer1 = 10; - do { /* Wait for data packet in timeout of 100ms */ - token = rcvr_spi(); - } while ((token == 0xFF) && Timer1); - if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ - - do { /* Receive the data block into buffer */ - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - } while (btr -= 2); - rcvr_spi(); /* Discard CRC */ - rcvr_spi(); - - return RT_TRUE; /* Return with success */ -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a data packet to MMC */ -/*-----------------------------------------------------------------------*/ - -#if _READONLY == 0 -static -rt_bool_t xmit_datablock ( - const rt_uint8_t *buff, /* 512 byte data block to be transmitted */ - rt_uint8_t token /* Data/Stop token */ -) -{ - rt_uint8_t resp, wc; - - - if (wait_ready() != 0xFF) return RT_FALSE; - - xmit_spi(token); /* Xmit data token */ - if (token != 0xFD) { /* Is data token */ - wc = 0; - do { /* Xmit the 512 byte data block to MMC */ - xmit_spi(*buff++); - xmit_spi(*buff++); - } while (--wc); - xmit_spi(0xFF); /* CRC (Dummy) */ - xmit_spi(0xFF); - resp = rcvr_spi(); /* Reveive data response */ - if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - return RT_FALSE; - } - - return RT_TRUE; -} -#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Send a command packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t send_cmd ( - rt_uint8_t cmd, /* Command byte */ - rt_uint32_t arg /* Argument */ -) -{ - rt_uint8_t n, res; - - - if (wait_ready() != 0xFF) return 0xFF; - - /* Send command packet */ - xmit_spi(cmd); /* Command */ - xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ - xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ - xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ - xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ - n = 0; - if (cmd == CMD0) n = 0x95; /* CRC for CMD0(0) */ - if (cmd == CMD8) n = 0x87; /* CRC for CMD8(0x1AA) */ - xmit_spi(n); - - /* Receive command response */ - if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ - n = 10; /* Wait for a valid response in timeout of 10 attempts */ - do - res = rcvr_spi(); - while ((res & 0x80) && --n); - - return res; /* Return with the response value */ -} - - - -/*-------------------------------------------------------------------------- - - Public Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ -static -DSTATUS sdcard_initialize ( - rt_uint8_t drv /* Physical drive nmuber (0) */ -) -{ - rt_uint8_t n, ty, ocr[4]; - - - if (drv) return STA_NOINIT; /* Supports only single drive */ - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on */ - send_initial_clock_train(); - - SELECT(); /* CS = L */ - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 msec */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDC Ver2+ */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - do { - if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0) break; /* ACMD41 with HCS bit */ - } while (Timer1); - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? 6 : 2; - } - } - } else { /* SDC Ver1 or MMC */ - ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */ - do { - if (ty == 2) { - if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break; /* ACMD41 */ - } else { - if (send_cmd(CMD1, 0) == 0) break; /* CMD1 */ - } - } while (Timer1); - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Select R/W block length */ - ty = 0; - } - } - CardType = ty; - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - if (ty) { /* Initialization succeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - set_max_speed(); - } else { /* Initialization failed */ - power_off(); - } - - return Stat; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ -static -DRESULT sdcard_read ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - rt_uint8_t *buff, /* Pointer to the data buffer to store read data */ - rt_uint32_t sector, /* Start sector number (LBA) */ - rt_uint8_t count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - - if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ - - SELECT(); /* CS = L */ - - if (count == 1) { /* Single block read */ - if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ - && rcvr_datablock(buff, 512)) - count = 0; - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) break; - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - return count ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -#if _READONLY == 0 -static -DRESULT sdcard_write ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - const rt_uint8_t *buff, /* Pointer to the data to be written */ - rt_uint32_t sector, /* Start sector number (LBA) */ - rt_uint8_t count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - - if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ - - SELECT(); /* CS = L */ - - if (count == 1) { /* Single block write */ - if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ - && xmit_datablock(buff, 0xFE)) - count = 0; - } - else { /* Multiple block write */ - if (CardType & 2) { - send_cmd(CMD55, 0); send_cmd(CMD23, count); /* ACMD23 */ - } - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - return count ? RES_ERROR : RES_OK; -} -#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ -static -DRESULT sdcard_ioctl ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - rt_uint8_t ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - DRESULT res; - rt_uint8_t n, csd[16], *ptr = buff; - rt_uint16_t csize; - - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { - switch (*ptr) { - case 0: /* Sub control code == 0 (POWER_OFF) */ - if (chk_power()) - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code == 1 (POWER_ON) */ - power_on(); /* Power on */ - res = RES_OK; - break; - case 2: /* Sub control code == 2 (POWER_GET) */ - *(ptr+1) = (rt_uint8_t)chk_power(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - } - else { - if (Stat & STA_NOINIT) return RES_NOTRDY; - - SELECT(); /* CS = L */ - - switch (ctrl) { - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (rt_uint32_t) */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ - csize = csd[9] + ((rt_uint16_t)csd[8] << 8) + 1; - *(rt_uint32_t*)buff = (rt_uint32_t)csize << 10; - } else { /* MMC or SDC ver 1.XX */ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((rt_uint16_t)csd[7] << 2) + ((rt_uint16_t)(csd[6] & 3) << 10) + 1; - *(rt_uint32_t*)buff = (rt_uint32_t)csize << (n - 9); - } - res = RES_OK; - } - break; - - case GET_SECTOR_SIZE : /* Get sectors on the disk (rt_uint16_t) */ - *(rt_uint16_t*)buff = 512; - res = RES_OK; - break; - - case CTRL_SYNC : /* Make sure that data has been written */ - if (wait_ready() == 0xFF) - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 0; n < 4; n++) - *ptr++ = rcvr_spi(); - res = RES_OK; - } - -// case MMC_GET_TYPE : /* Get card type flags (1 byte) */ -// *ptr = CardType; -// res = RES_OK; -// break; - - default: - res = RES_PARERR; - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - } - - return res; -} - -/* - * RT-Thread SD Card Driver - * 20090705 Yi.Qiu - */ -#include -#include - -struct rt_device sdcard_device; -struct dfs_partition part; - -/* RT-Thread Device Driver Interface */ -static rt_err_t rt_sdcard_init(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) -{ - - return RT_EOK; -} - -static rt_err_t rt_sdcard_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - DRESULT status; - - status = sdcard_read(0, buffer, part.offset + pos, size); - if (status != RES_OK) - { - rt_kprintf("sd card read failed\n"); - return 0; - } - - return size; -} - -static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - DRESULT status; - - status = sdcard_write(0, buffer, part.offset + pos, size); - if (status != RES_OK) - { - rt_kprintf("sd card write failed\n"); - return 0; - } - - return size; -} - -static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - return RT_EOK; -} - -void rt_hw_sdcard_init(void) -{ - if (sdcard_initialize(0) == RES_OK) - { - DRESULT status; - rt_uint8_t *sector; - - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - return; - } - status = sdcard_read(0, sector, 0, 1); - if (status == RES_OK) - { - /* get the first partition */ - if (dfs_filesystem_get_partition(&part, sector, 0) != 0) - { - /* there is no partition */ - part.offset = 0; - part.size = 0; - } - } - else - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } - - /* release sector buffer */ - rt_free(sector); - - /* register sdcard device */ - sdcard_device.type = RT_Device_Class_Block; - sdcard_device.init = rt_sdcard_init; - sdcard_device.open = rt_sdcard_open; - sdcard_device.close = rt_sdcard_close; - sdcard_device.read = rt_sdcard_read; - sdcard_device.write = rt_sdcard_write; - sdcard_device.control = rt_sdcard_control; - - /* no private */ - sdcard_device.user_data = RT_NULL; - - rt_device_register(&sdcard_device, "sd0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - - return; - } - rt_kprintf("sdcard init failed\n"); -} - diff --git a/bsp/lm3s8962/startup.c b/bsp/lm3s8962/startup.c deleted file mode 100644 index a38733494f..0000000000 --- a/bsp/lm3s8962/startup.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -#ifdef RT_USING_LWIP -#include -#include -#endif - -/** - * @addtogroup LM3S - */ - -extern void rt_hw_serial_init(void); - -/*@{*/ -#ifdef RT_USING_FINSH -extern void finsh_system_init(void); -extern void finsh_set_device(char* device); -#endif - -extern int rt_application_init(void); -extern void rt_hw_sdcard_init(void); -extern int rt_hw_luminaryif_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -#ifdef DEBUG -/******************************************************************************* -* Function Name : assert_failed -* Description : Reports the name of the source file and the source line number -* where the assert error has occurred. -* Input : - file: pointer to the source file name -* - line: assert error line source number -* Output : None -* Return : None -*******************************************************************************/ -void assert_failed(u8* file, u32 line) -{ - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); - - while (1) ; -} -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP -#ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); -#elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); -#else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); -#endif -#endif - -#ifdef RT_USING_MODULE - /* init module system */ - rt_system_module_init(); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_LWIP - eth_system_device_init(); - - /* register ethernetif device */ - rt_hw_luminaryif_init(); -#endif - - /* init hardware serial device */ - rt_hw_serial_init(); -#ifdef RT_USING_DFS - /* init sd card device */ - rt_hw_sdcard_init(); -#endif - /* init all device */ - rt_device_init_all(); - - /* init application */ - rt_application_init(); - -#ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); -#ifdef RT_USING_DEVICE - finsh_set_device("uart1"); -#endif -#endif - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - rt_uint32_t level UNUSED; - - /* disable interrupt first */ - level = rt_hw_interrupt_disable(); - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/lm3s8962/template.Uv2 b/bsp/lm3s8962/template.Uv2 index a46bbe6f4c..c33acd19fb 100644 --- a/bsp/lm3s8962/template.Uv2 +++ b/bsp/lm3s8962/template.Uv2 @@ -31,14 +31,14 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' EnvReg (Luminary\) OrgReg (Luminary\) TgStat=16 - OutDir (.\objs\) + OutDir (.\build\) OutName (rtthread-lm3s) GenApp=1 GenLib=0 GenHex=0 Debug=1 Browse=1 - LstDir (.\objs\) + LstDir (.\build\) HexSel=1 MG32K=0 TGMORE=0 diff --git a/bsp/lm3s9b9x/Libraries/SConscript b/bsp/lm3s9b9x/Libraries/SConscript index ac6ad70115..27ff3b7105 100644 --- a/bsp/lm3s9b9x/Libraries/SConscript +++ b/bsp/lm3s9b9x/Libraries/SConscript @@ -3,34 +3,19 @@ Import('rtconfig') from building import * # The set of source files associated with this SConscript file. -src = Split(""" - driverlib/adc.c - driverlib/can.c - driverlib/comp.c - driverlib/cpu.c - driverlib/epi.c - driverlib/ethernet.c - driverlib/flash.c - driverlib/gpio.c - driverlib/hibernate.c - driverlib/i2c.c - driverlib/i2s.c - driverlib/interrupt.c - driverlib/mpu.c - driverlib/pwm.c - driverlib/qei.c - driverlib/ssi.c - driverlib/sysctl.c - driverlib/systick.c - driverlib/timer.c - driverlib/uart.c - driverlib/udma.c - driverlib/usb.c - driverlib/watchdog.c -""") +cwd = GetCurrentDir() +src = Glob('driverlib/*.c') -CPPPATH = [RTT_ROOT + '/bsp/lm3s9b9x/Libraries/inc', RTT_ROOT + '/bsp/lm3s9b9x/Libraries', RTT_ROOT + '/bsp/lm3s9b9x/Libraries/driverlib'] +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += ['startup/gcc/start_gcc.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['startup/arm/start_rvds.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['startup/iar/start_iar.S'] -group = DefineGroup('library', src, depend = [''], CPPPATH = CPPPATH) +CPPPATH = [cwd] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/lm3s9b9x/Libraries/startup/arm/start_rvds.S b/bsp/lm3s9b9x/Libraries/startup/arm/start_rvds.S new file mode 100644 index 0000000000..cf564930bc --- /dev/null +++ b/bsp/lm3s9b9x/Libraries/startup/arm/start_rvds.S @@ -0,0 +1,253 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; Startup.s - Startup code for Stellaris. +; +; Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +; +; Software License Agreement +; +; Luminary Micro, Inc. (LMI) is supplying this software for use solely and +; exclusively on LMI's microcontroller products. +; +; The software is owned by LMI and/or its suppliers, and is protected under +; applicable copyright laws. All rights are reserved. You may not combine +; this software with "viral" open-source software in order to form a larger +; program. Any use in violation of the foregoing restrictions may subject +; the user to criminal sanctions under applicable laws, as well as to civil +; liability for the breach of the terms and conditions of this license. +; +; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2523 of the Stellaris Peripheral Driver Library. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000100 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + + IMPORT PendSV_Handler + IMPORT rt_hw_timer_handler + IMPORT rt_hw_uart_isr_1 + IMPORT rt_hw_eth_handler + IMPORT HardFault_Handler + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD IntDefaultHandler ; MPU Fault Handler + DCD IntDefaultHandler ; Bus Fault Handler + DCD IntDefaultHandler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall Handler + DCD IntDefaultHandler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD rt_hw_timer_handler ; SysTick Handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD rt_hw_uart_isr_1 ; UART0 + DCD IntDefaultHandler ; UART1 + DCD IntDefaultHandler ; SSI + DCD IntDefaultHandler ; I2C + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog + DCD IntDefaultHandler ; Timer 0A + DCD IntDefaultHandler ; Timer 0B + DCD IntDefaultHandler ; Timer 1A + DCD IntDefaultHandler ; Timer 1B + DCD IntDefaultHandler ; Timer 2A + DCD IntDefaultHandler ; Timer 2B + DCD IntDefaultHandler ; Comp 0 + DCD IntDefaultHandler ; Comp 1 + DCD IntDefaultHandler ; Comp 2 + DCD IntDefaultHandler ; System Control + DCD 0x881 ; Flash Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD IntDefaultHandler ; CAN2 + DCD rt_hw_eth_handler ; Ethernet + DCD IntDefaultHandler ; Hibernate + DCD IntDefaultHandler ; USB0 + DCD IntDefaultHandler ; PWM Generator 3 + DCD IntDefaultHandler ; uDMA Software Transfer + DCD IntDefaultHandler ; uDMA Error + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/bsp/lm3s9b9x/Libraries/startup/gcc/start_gcc.S b/bsp/lm3s9b9x/Libraries/startup/gcc/start_gcc.S new file mode 100644 index 0000000000..1d1b8e558d --- /dev/null +++ b/bsp/lm3s9b9x/Libraries/startup/gcc/start_gcc.S @@ -0,0 +1,164 @@ +.section .bss.init +.equ Stack_Size, 0x00000200 +.space Stack_Size +Initial_spTop: + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + LDR r0, =Initial_spTop + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word Default_Handler //NMI_Handler + .word rt_hw_hard_fault + .word Default_Handler //MemManage_Handler + .word Default_Handler //BusFault_Handler + .word Default_Handler //UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word Default_Handler //SVC_Handler + .word Default_Handler //DebugMon_Handler + .word 0 + .word rt_hw_pend_sv + .word rt_hw_timer_handler + .word Default_Handler // GPIO Port A + .word Default_Handler // GPIO Port B + .word Default_Handler // GPIO Port C + .word Default_Handler // GPIO Port D + .word Default_Handler // GPIO Port E + .word rt_hw_uart_isr_1 // UART0 Rx and Tx + .word Default_Handler // UART1 Rx and Tx + .word Default_Handler // SSI Rx and Tx + .word Default_Handler // I2C Master and Slave + .word Default_Handler // PWM Fault + .word Default_Handler // PWM Generator 0 + .word Default_Handler // PWM Generator 1 + .word Default_Handler // PWM Generator 2 + .word Default_Handler // Quadrature Encoder + .word Default_Handler // ADC Sequence 0 + .word Default_Handler // ADC Sequence 1 + .word Default_Handler // ADC Sequence 2 + .word Default_Handler // ADC Sequence 3 + .word Default_Handler // Watchdog timer + .word Default_Handler // Timer 0 subtimer A + .word Default_Handler // Timer 0 subtimer B + .word Default_Handler // Timer 1 subtimer A + .word Default_Handler // Timer 1 subtimer B + .word Default_Handler // Timer 2 subtimer A + .word Default_Handler // Timer 2 subtimer B + .word Default_Handler // Analog Comparator 0 + .word Default_Handler // Analog Comparator 1 + .word Default_Handler // Analog Comparator 2 + .word Default_Handler // System Control (PLL, OSC, + .word Default_Handler // FLASH Control + .word Default_Handler // GPIO Port F + .word Default_Handler // GPIO Port G + .word Default_Handler // GPIO Port H + .word Default_Handler // UART2 Rx and Tx + .word Default_Handler // SSI1 Rx and Tx + .word Default_Handler // Timer 3 subtimer A + .word Default_Handler // Timer 3 subtimer B + .word Default_Handler // I2C1 Master and Slave + .word Default_Handler // Quadrature Encoder 1 + .word Default_Handler // CAN0 + .word Default_Handler // CAN1 + .word Default_Handler // CAN2 + .word luminaryif_isr // Ethernet + .word Default_Handler // Hibernate + .word Default_Handler // USB0 + .word Default_Handler // PWM Generator 3 + .word Default_Handler // uDMA Software Transfer + .word Default_Handler // uDMA Error diff --git a/bsp/lm3s9b9x/SConscript b/bsp/lm3s9b9x/SConscript index c5d7d76b02..a425264923 100644 --- a/bsp/lm3s9b9x/SConscript +++ b/bsp/lm3s9b9x/SConscript @@ -1,19 +1,14 @@ -import rtconfig +# for module compiling +import os Import('RTT_ROOT') -from building import * -src_bsp = ['application.c', 'startup.c', 'sdram.c', 'board.c'] +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) -src_drv = [] -if GetDepend('RT_USING_DFS'): - src_drv += ['sdcard.c'] +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) -if GetDepend('RT_USING_LWIP'): - - src_drv += ['luminaryif.c'] - -src = File(src_bsp + src_drv) -CPPPATH = [GetCurrentDir()] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') +Return('objs') diff --git a/bsp/lm3s9b9x/SConstruct b/bsp/lm3s9b9x/SConstruct index 19c806f8ec..5439cdbb57 100644 --- a/bsp/lm3s9b9x/SConstruct +++ b/bsp/lm3s9b9x/SConstruct @@ -19,10 +19,9 @@ Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -objs = objs + SConscript(('bsp/lm3s9b9x/Libraries/SConscript'), variant_dir='build/bsp/Libraries', duplicate=0) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +# build program env.Program(TARGET, objs) # end building diff --git a/bsp/lm3s9b9x/application.c b/bsp/lm3s9b9x/application.c deleted file mode 100644 index fded03279f..0000000000 --- a/bsp/lm3s9b9x/application.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -/** - * @addtogroup LM3S - */ -/*@{*/ - -#include -#include - -#ifdef RT_USING_DFS -/* dfs init */ -#include -/* dfs filesystem:ELM FatFs filesystem init */ -#include -/* dfs Filesystem APIs */ -#include -#endif - -#ifdef RT_USING_LWIP -#include -#include -#endif - -/* thread phase init */ -void rt_init_thread_entry(void *parameter) -{ -/* Filesystem Initialization */ -#ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); -#ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); - - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); -#endif - } -#endif - -/* LwIP Initialization */ -#ifdef RT_USING_LWIP - { - extern void lwip_sys_init(void); - - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } -#endif -} - -int rt_application_init() -{ - rt_thread_t init_thread; - - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 1024, 21, 20); - rt_thread_startup(init_thread); - - return 0; -} -/*@}*/ diff --git a/bsp/lm3s9b9x/applications/SConscript b/bsp/lm3s9b9x/applications/SConscript new file mode 100644 index 0000000000..591734409c --- /dev/null +++ b/bsp/lm3s9b9x/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lm3s9b9x/applications/application.c b/bsp/lm3s9b9x/applications/application.c new file mode 100644 index 0000000000..fded03279f --- /dev/null +++ b/bsp/lm3s9b9x/applications/application.c @@ -0,0 +1,83 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +/** + * @addtogroup LM3S + */ +/*@{*/ + +#include +#include + +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:ELM FatFs filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +#ifdef RT_USING_LWIP +#include +#include +#endif + +/* thread phase init */ +void rt_init_thread_entry(void *parameter) +{ +/* Filesystem Initialization */ +#ifdef RT_USING_DFS + { + /* init the device filesystem */ + dfs_init(); +#ifdef RT_USING_DFS_ELMFAT + /* init the elm chan FatFs filesystam*/ + elm_init(); + + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif + } +#endif + +/* LwIP Initialization */ +#ifdef RT_USING_LWIP + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + } +#endif +} + +int rt_application_init() +{ + rt_thread_t init_thread; + + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 1024, 21, 20); + rt_thread_startup(init_thread); + + return 0; +} +/*@}*/ diff --git a/bsp/lm3s9b9x/applications/startup.c b/bsp/lm3s9b9x/applications/startup.c new file mode 100644 index 0000000000..942ac439aa --- /dev/null +++ b/bsp/lm3s9b9x/applications/startup.c @@ -0,0 +1,155 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +#ifdef RT_USING_LWIP +#include +#include +#endif + +/** + * @addtogroup LM3S + */ + +extern void rt_hw_serial_init(void); + +/*@{*/ +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(char* device); +#endif + +extern int rt_application_init(void); +extern void rt_hw_sdcard_init(void); +extern int rt_hw_luminaryif_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void __error__(char* file, unsigned long line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#if LM3S_EXT_SRAM == 1 + /* init sdram */ + rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); +#else +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); +#endif +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_LWIP + eth_system_device_init(); + + /* register ethernetif device */ + rt_hw_luminaryif_init(); +#endif + + /* init hardware serial device */ + rt_hw_serial_init(); +#ifdef RT_USING_DFS + /* init sd card device */ + rt_hw_sdcard_init(); +#endif + /* init all device */ + rt_device_init_all(); + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); +#ifdef RT_USING_DEVICE + finsh_set_device("uart1"); +#endif +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/lm3s9b9x/board.c b/bsp/lm3s9b9x/board.c deleted file mode 100644 index 1b6ee22678..0000000000 --- a/bsp/lm3s9b9x/board.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-05-16 Bernard first implementation - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -static void rt_hw_console_init(void); - -/** - * @addtogroup LM3S - */ - -/*@{*/ - -extern void rt_hw_interrupt_thread_switch(void); -/** - * This is the timer interrupt service routine. - * - */ -void rt_hw_timer_handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); - rt_hw_interrupt_thread_switch(); -} - -/** - * This is the ethernet interrupt service routine. - * - */ -void rt_hw_eth_handler(void) -{ -#ifdef RT_USING_LWIP - extern void luminaryif_isr(void); - - /* enter interrupt */ - rt_interrupt_enter(); - - /* luminary ethernet interface */ - luminaryif_isr(); - - /* leave interrupt */ - rt_interrupt_leave(); -#endif -} - -/** - * This function will initial LM3S board. - */ -void rt_hw_board_init() -{ - // set sysclock to 80M - SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); - - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); - - /* enable ssio */ - //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); - -#if LM3S_EXT_SRAM == 1 - /* init SDRAM */ - rt_hw_sdram_init(); -#endif - /* init console */ - rt_hw_console_init(); - - /* enable interrupt */ - IntMasterEnable(); -} - -/* init console to support rt_kprintf */ -static void rt_hw_console_init() -{ - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); -} - -/* write one character to serial, must not trigger interrupt */ -static void rt_hw_console_putc(const char c) -{ - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); -} - -/** - * This function is used by rt_kprintf to display a string on console. - * - * @param str the displayed string - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - rt_hw_console_putc (*str++); - } -} - -/*@}*/ diff --git a/bsp/lm3s9b9x/board.h b/bsp/lm3s9b9x/board.h deleted file mode 100644 index 862b889e6c..0000000000 --- a/bsp/lm3s9b9x/board.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-10-08 Bernard add board.h to this bsp - * 2009-12-25 yi.qiu add LM3S configration - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -/* whether use board external SRAM memory */ -// Use external SRAM memory on the board -// Enable External SRAM memory -#define LM3S_EXT_SRAM 0 -// Begin Address of External SRAM -// Default: 0x60000000 -#define LM3S_EXT_SRAM_BEGIN 0x60000000 /* the begining address of external SRAM */ -// End Address of External SRAM -// Default: 0x60000000 -#define LM3S_EXT_SRAM_END 0x607FFFFF /* the end address of external SRAM */ -// - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#define LM3S_SRAM_SIZE 96 -#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) - -// For lm3s8962, it should be SYSCTL_XTAL_8MHZ -#define LM3S_XTAL_TYPE SYSCTL_XTAL_8MHZ - -void rt_hw_board_led_on(int n); -void rt_hw_board_led_off(int n); -void rt_hw_board_init(void); - -void rt_hw_usart_init(void); -void rt_hw_sdcard_init(void); - -#endif diff --git a/bsp/lm3s9b9x/drivers/SConscript b/bsp/lm3s9b9x/drivers/SConscript new file mode 100644 index 0000000000..36ce397c33 --- /dev/null +++ b/bsp/lm3s9b9x/drivers/SConscript @@ -0,0 +1,21 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import copy + +cwd = os.path.join(str(Dir('#')), 'drivers') +src = Glob('*.c') +CPPPATH = [cwd] + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + src_need_remove = ['luminaryif.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +if GetDepend('RT_USING_DFS') == False: + src_need_remove = ['sdcard.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lm3s9b9x/drivers/board.c b/bsp/lm3s9b9x/drivers/board.c new file mode 100644 index 0000000000..1b6ee22678 --- /dev/null +++ b/bsp/lm3s9b9x/drivers/board.c @@ -0,0 +1,140 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-05-16 Bernard first implementation + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +static void rt_hw_console_init(void); + +/** + * @addtogroup LM3S + */ + +/*@{*/ + +extern void rt_hw_interrupt_thread_switch(void); +/** + * This is the timer interrupt service routine. + * + */ +void rt_hw_timer_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} + +/** + * This is the ethernet interrupt service routine. + * + */ +void rt_hw_eth_handler(void) +{ +#ifdef RT_USING_LWIP + extern void luminaryif_isr(void); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* luminary ethernet interface */ + luminaryif_isr(); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +/** + * This function will initial LM3S board. + */ +void rt_hw_board_init() +{ + // set sysclock to 80M + SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); + + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); + + /* enable ssio */ + //SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + +#if LM3S_EXT_SRAM == 1 + /* init SDRAM */ + rt_hw_sdram_init(); +#endif + /* init console */ + rt_hw_console_init(); + + /* enable interrupt */ + IntMasterEnable(); +} + +/* init console to support rt_kprintf */ +static void rt_hw_console_init() +{ + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); +} + +/* write one character to serial, must not trigger interrupt */ +static void rt_hw_console_putc(const char c) +{ + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_console_putc (*str++); + } +} + +/*@}*/ diff --git a/bsp/lm3s9b9x/drivers/board.h b/bsp/lm3s9b9x/drivers/board.h new file mode 100644 index 0000000000..6d50535c3f --- /dev/null +++ b/bsp/lm3s9b9x/drivers/board.h @@ -0,0 +1,47 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + * 2009-12-25 yi.qiu add LM3S configration + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +/* whether use board external SRAM memory */ +// Use external SRAM memory on the board +// Enable External SRAM memory +#define LM3S_EXT_SRAM 1 +// Begin Address of External SRAM +// Default: 0x60000000 +#define LM3S_EXT_SRAM_BEGIN 0x60000000 /* the begining address of external SRAM */ +// End Address of External SRAM +// Default: 0x60000000 +#define LM3S_EXT_SRAM_END 0x607FFFFF /* the end address of external SRAM */ +// + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#define LM3S_SRAM_SIZE 96 +#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024) + +// For lm3s9b9x, it should be SYSCTL_XTAL_16MHZ +#define LM3S_XTAL_TYPE SYSCTL_XTAL_168MHZ + +void rt_hw_board_led_on(int n); +void rt_hw_board_led_off(int n); +void rt_hw_board_init(void); + +void rt_hw_usart_init(void); +void rt_hw_sdcard_init(void); + +#endif diff --git a/bsp/lm3s9b9x/drivers/luminaryif.c b/bsp/lm3s9b9x/drivers/luminaryif.c new file mode 100644 index 0000000000..0e20c6dd50 --- /dev/null +++ b/bsp/lm3s9b9x/drivers/luminaryif.c @@ -0,0 +1,490 @@ +//***************************************************************************** +// +// luminaryif.c - Ethernet Interface File for lwIP TCP/IP Stack +// +//***************************************************************************** + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "lwipopts.h" +#include "luminaryif.h" + +#define MAX_ADDR_LEN 6 + +struct net_device +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ +}; + +static struct net_device luminaryif_dev_entry; +static struct net_device *luminaryif_dev =&luminaryif_dev_entry; +static struct rt_semaphore tx_sem; + +//***************************************************************************** +// +// Sanity Check: This module will NOT work if the following defines +// are incorrect. +// +//***************************************************************************** +#if (PBUF_LINK_HLEN != 16) +#error "Incorrect PBUF_LINK_HLEN specified!" +#endif +#if (ETH_PAD_SIZE != 2) +#error "Incorrect ETH_PAD_SIZE specified!" +#endif +#if (PBUF_POOL_BUFSIZE % 4) +#error "PBUF_POOL_BUFSIZE must be modulo 4!" +#endif + +/* RT-Thread Device Interface */ + +/* initialize the interface */ +//***************************************************************************** +// +// Low-Level initialization function for the Ethernet Controller. +// +//***************************************************************************** +rt_err_t luminaryif_init(rt_device_t dev) +{ + unsigned long ulTemp; + + // + // Disable all Ethernet Interrupts. + // + EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX)); + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Initialize the Ethernet Controller. + // + EthernetInitExpClk(ETH_BASE, SysCtlClockGet()); + + // + // Configure the Ethernet Controller for normal operation. + // - Enable TX Duplex Mode + // - Enable TX Padding + // - Enable TX CRC Generation + // + EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | + ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN)); + + // + // Enable the Ethernet Controller transmitter and receiver. + // + EthernetEnable(ETH_BASE); + + // + // Enable the Ethernet Interrupt handler. + // + IntEnable(INT_ETH); + + // + // Enable Ethernet TX and RX Packet Interrupts. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX); + + return RT_EOK; +} + +void luminaryif_isr(void) +{ + unsigned long ulTemp; + + // + // Read and Clear the interrupt. + // + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Check to see if an RX Interrupt has occured. + // + if(ulTemp & ETH_INT_RX) + { + // + // Indicate that a packet has been received. + // + rt_err_t result; + + /* a frame has been received */ + result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent)); + + if(result != RT_EOK) rt_set_errno(-RT_ERROR); + + // + // Disable Ethernet RX Interrupt. + // + EthernetIntDisable(ETH_BASE, ETH_INT_RX); + } + if(ulTemp & ETH_INT_TX) + { + /* A frame has been transmitted. */ + rt_sem_release(&tx_sem); + } + +} + +/* control the interface */ +rt_err_t luminaryif_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, luminaryif_dev_entry.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* Open the ethernet interface */ +rt_err_t luminaryif_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +/* Close the interface */ +rt_err_t luminaryif_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* Read */ +rt_size_t luminaryif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* Write */ +rt_size_t luminaryif_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +//**************************************************************************** +// +// Low-Level transmit routine. Should do the actual transmission of the +// packet. The packet is contained in the pbuf that is passed to the function. +// This pbuf might be chained. +// +//**************************************************************************** +rt_err_t luminaryif_tx(rt_device_t dev, struct pbuf *p) +{ + int iBuf; + unsigned char *pucBuf; + unsigned long *pulBuf; + struct pbuf *q; + int iGather; + unsigned long ulGather; + unsigned char *pucGather; + unsigned long ulTemp; + + /* lock tx operation */ + rt_sem_take(&tx_sem, RT_WAITING_FOREVER); + + // + // Wait for space available in the TX FIFO. + // + while(!EthernetSpaceAvail(ETH_BASE)) + { + } + +// + // Fill in the first two bytes of the payload data (configured as padding + // with ETH_PAD_SIZE = 2) with the total length of the payload data + // (minus the Ethernet MAC layer header). + // + *((unsigned short *)(p->payload)) = p->tot_len - 16; + + // + // Initialize the gather register. + // + iGather = 0; + pucGather = (unsigned char *)&ulGather; + ulGather = 0; + + // + // Copy data from the pbuf(s) into the TX Fifo. + // + for(q = p; q != NULL; q = q->next) + { + // + // Intialize a char pointer and index to the pbuf payload data. + // + pucBuf = (unsigned char *)q->payload; + iBuf = 0; + + // + // If the gather buffer has leftover data from a previous pbuf + // in the chain, fill it up and write it to the Tx FIFO. + // + while((iBuf < q->len) && (iGather != 0)) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + + // + // If the gather index is 0 and the pbuf index is non-zero, + // we have a gather buffer to write into the Tx FIFO. + // + if((iGather == 0) && (iBuf != 0)) + { + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + ulGather = 0; + } + + // + // Copy words of pbuf data into the Tx FIFO, but don't go past + // the end of the pbuf. + // + if((iBuf % 4) != 0) + { + while((iBuf + 4) <= q->len) + { + ulTemp = (pucBuf[iBuf++] << 0); + ulTemp |= (pucBuf[iBuf++] << 8); + ulTemp |= (pucBuf[iBuf++] << 16); + ulTemp |= (pucBuf[iBuf++] << 24); + HWREG(ETH_BASE + MAC_O_DATA) = ulTemp; + } + } + else + { + // + // Initialze a long pointer into the pbuf for 32-bit access. + // + pulBuf = (unsigned long *)&pucBuf[iBuf]; + + while((iBuf + 4) <= q->len) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulBuf++; + iBuf += 4; + } + } + // + // Check if leftover data in the pbuf and save it in the gather + // buffer for the next time. + // + while(iBuf < q->len) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + } + + // + // Send any leftover data to the FIFO. + // + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + + // + // Wakeup the transmitter. + // + HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX; + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif + + return(ERR_OK); +} + +//***************************************************************************** +// +// Low-Level receive routine. Should allocate a pbuf and transfer the bytes +// of the incoming packet from the interface into the pbuf. +// +//***************************************************************************** +struct pbuf * luminaryif_rx(rt_device_t dev) +{ + struct pbuf *p, *q; + u16_t len; + unsigned long ulTemp; + int i; + unsigned long *ptr; + + if(!EthernetPacketAvail(ETH_BASE)) + { + // + // Enable Ethernet RX Interrupt. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return(NULL); + } + + // + // Obtain the size of the packet and put it into the "len" variable. + // Note: The length returned in the FIFO length position includes the + // two bytes for the length + the 4 bytes for the FCS. + // + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + len = ulTemp & 0xFFFF; + + // + // We allocate a pbuf chain of pbufs from the pool. + // + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + + if(p != NULL) + { + // + // Place the first word into the first pbuf location. + // + *(unsigned long *)p->payload = ulTemp; + p->payload = (char *)(p->payload) + 4; + p->len -= 4; + + // + // Process all but the last buffer in the pbuf chain. + // + q = p; + while(q != NULL) + { + // + // Setup a byte pointer into the payload section of the pbuf. + // + ptr = q->payload; + + // + // Read data from FIFO into the current pbuf + // (assume pbuf length is modulo 4) + // + for(i = 0; i < q->len; i += 4) + { + *ptr++ = HWREG(ETH_BASE + MAC_O_DATA); + } + + // + // Link in the next pbuf in the chain. + // + q = q->next; + } + + // + // Restore the first pbuf parameters to their original values. + // + p->payload = (char *)(p->payload) - 4; + p->len += 4; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif + } + else + { + // + // Just read all of the remaining data from the FIFO and dump it. + // + for(i = 4; i < len; i+=4) + { + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + } + +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + } + + return(p); +} + +int rt_hw_luminaryif_init(void) +{ + rt_err_t result; + unsigned long ulUser0, ulUser1; + + /* Enable and Reset the Ethernet Controller. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); + SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); + + /* + Enable Port F for Ethernet LEDs. + LED0 Bit 3 Output + LED1 Bit 2 Output + */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + /* GPIODirModeSet and GPIOPadConfigSet */ + GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3); + GPIOPinConfigure(GPIO_PF2_LED1); + GPIOPinConfigure(GPIO_PF3_LED0); + + FlashUserSet(0x00371200, 0x00563412); /* OUI:00-12-37 (hex) Texas Instruments, only for test */ + /* Configure the hardware MAC address */ + FlashUserGet(&ulUser0, &ulUser1); + if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff)) + { + rt_kprintf("Fatal error in geting MAC address\n"); + } + + /* init rt-thread device interface */ + luminaryif_dev_entry.parent.parent.init = luminaryif_init; + luminaryif_dev_entry.parent.parent.open = luminaryif_open; + luminaryif_dev_entry.parent.parent.close = luminaryif_close; + luminaryif_dev_entry.parent.parent.read = luminaryif_read; + luminaryif_dev_entry.parent.parent.write = luminaryif_write; + luminaryif_dev_entry.parent.parent.control = luminaryif_control; + luminaryif_dev_entry.parent.eth_rx = luminaryif_rx; + luminaryif_dev_entry.parent.eth_tx = luminaryif_tx; + + /* + Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC + address needed to program the hardware registers, then program the MAC + address into the Ethernet Controller registers. + */ + luminaryif_dev_entry.dev_addr[0] = ((ulUser0 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[1] = ((ulUser0 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[2] = ((ulUser0 >> 16) & 0xff); + luminaryif_dev_entry.dev_addr[3] = ((ulUser1 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[4] = ((ulUser1 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the hardware with it's MAC address (for filtering). */ + EthernetMACAddrSet(ETH_BASE, luminaryif_dev_entry.dev_addr); + + rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); + + result = eth_device_init(&(luminaryif_dev->parent), "E0"); + + return result; +} + diff --git a/bsp/lm3s9b9x/drivers/luminaryif.h b/bsp/lm3s9b9x/drivers/luminaryif.h new file mode 100644 index 0000000000..e987daea5e --- /dev/null +++ b/bsp/lm3s9b9x/drivers/luminaryif.h @@ -0,0 +1,12 @@ +//***************************************************************************** +// +// luminaryif.h - Prototypes for the Luminary Micro Ethernet interface. +// +//***************************************************************************** + +#ifndef __LUMINARYIF_H__ +#define __LUMINARYIF_H__ + +int rt_hw_luminaryif_init(void); + +#endif // __LUMINARYIF_H__ diff --git a/bsp/lm3s9b9x/drivers/sdcard.c b/bsp/lm3s9b9x/drivers/sdcard.c new file mode 100644 index 0000000000..785f2eaf3e --- /dev/null +++ b/bsp/lm3s9b9x/drivers/sdcard.c @@ -0,0 +1,781 @@ +/*-----------------------------------------------------------------------*/ +/* MMC/SDC (in SPI mode) control module (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +/* + * This file was modified from a sample available from the FatFs + * web site. It was modified to work with a Luminary Micro + * EK-LM3S6965 evaluation board. + * + * Note that the SSI port is shared with the osram display. The code + * in this file does not attempt to share the SSI port with the osram, + * it assumes the osram is not being used. + */ +#include + +#include +#include +#include +#include +#include + +/* Status of Disk Functions */ +typedef rt_uint8_t DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Command code for disk_ioctrl() */ + +/* Generic command */ +#define CTRL_SYNC 0 /* Mandatory for write functions */ +#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ +#define GET_SECTOR_SIZE 2 /* Mandatory for multiple sector size cfg */ +#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +/* MMC/SDC command */ +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 +/* ATA/CF command */ +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +/* Peripheral definitions for EK-LM3S6965 board */ +// SSI port +#define SDC_SSI_BASE SSI0_BASE +#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0 + +// GPIO for SSI pins +#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE +#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA +#define SDC_SSI_CLK GPIO_PIN_2 +#define SDC_SSI_TX GPIO_PIN_5 +#define SDC_SSI_RX GPIO_PIN_4 +#define SDC_SSI_FSS GPIO_PIN_3 +#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK) + +// GPIO for card chip select +#define SDC_CS_GPIO_PORT_BASE GPIO_PORTG_BASE +#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOG +#define SDC_CS GPIO_PIN_0 + +// asserts the CS pin to the card +static +void SELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0); +} + +// de-asserts the CS pin to the card +static +void DESELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); +} + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +static volatile +rt_uint8_t Timer1, Timer2; /* 100Hz decrement timer */ + +static +rt_uint8_t CardType; /* b0:MMC, b1:SDC, b2:Block addressing */ + +static +rt_uint8_t PowerFlag = 0; /* indicates if "power" is on */ + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +void xmit_spi (rt_uint8_t dat) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, dat); /* Write the data to the tx fifo */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* flush data read during the write */ +} + + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t rcvr_spi (void) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, 0xFF); /* write dummy data */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */ + + return (rt_uint8_t)rcvdat; +} + + +static +void rcvr_spi_m (rt_uint8_t *dst) +{ + *dst = rcvr_spi(); +} + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t wait_ready (void) +{ + rt_uint8_t res; + + + Timer2 = 50; /* Wait for ready in timeout of 500ms */ + rcvr_spi(); + do + res = rcvr_spi(); + while ((res != 0xFF) && Timer2); + + return res; +} + +/*-----------------------------------------------------------------------*/ +/* Send 80 or so clock transitions with CS and DI held high. This is */ +/* required after card power up to get it into SPI mode */ +/*-----------------------------------------------------------------------*/ +static +void send_initial_clock_train(void) +{ + unsigned int i; + rt_uint32_t dat; + + /* Ensure CS is held high. */ + DESELECT(); + + /* Switch the SSI TX line to a GPIO and drive it high too. */ + GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX); + GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX); + + /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ + /* required number of times. */ + for(i = 0 ; i < 10 ; i++) + { + /* Write DUMMY data. SSIDataPut() waits until there is room in the */ + /* FIFO. */ + SSIDataPut(SDC_SSI_BASE, 0xFF); + + /* Flush data read during data write. */ + SSIDataGet(SDC_SSI_BASE, &dat); + } + + /* Revert to hardware control of the SSI TX line. */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX); +} + +/*-----------------------------------------------------------------------*/ +/* Power Control (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* When the target system does not support socket power control, there */ +/* is nothing to do in these functions and chk_power always returns 1. */ + +static +void power_on (void) +{ + /* + * This doesn't really turn the power on, but initializes the + * SSI port and pins needed to talk to the card. + */ + + /* Enable the peripherals used to drive the SDC on SSI, and the CS */ + SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH); + + /* Configure the appropriate pins to be SSI instead of GPIO */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS); + GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS); + GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + /* Deassert the SSI0 chip select */ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 400000, 8); + SSIEnable(SDC_SSI_BASE); + + /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ + /* to be able to accept a native command. */ + send_initial_clock_train(); + + PowerFlag = 1; +} + +// set the SSI speed to the max setting +static +void set_max_speed(void) +{ + unsigned long i; + + /* Disable the SSI */ + SSIDisable(SDC_SSI_BASE); + + /* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */ + i = SysCtlClockGet() / 2; + if(i > 12500000) + { + i = 12500000; + } + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, i, 8); + + /* Enable the SSI */ + SSIEnable(SDC_SSI_BASE); +} + +static +void power_off (void) +{ + PowerFlag = 0; +} + +static +int chk_power(void) /* Socket power state: 0=off, 1=on */ +{ + return PowerFlag; +} + + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_bool_t rcvr_datablock ( + rt_uint8_t *buff, /* Data buffer to store received data */ + unsigned int btr /* Byte count (must be even number) */ +) +{ + rt_uint8_t token; + + + Timer1 = 10; + do { /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ + + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 2); + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return RT_TRUE; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +static +rt_bool_t xmit_datablock ( + const rt_uint8_t *buff, /* 512 byte data block to be transmitted */ + rt_uint8_t token /* Data/Stop token */ +) +{ + rt_uint8_t resp, wc; + + + if (wait_ready() != 0xFF) return RT_FALSE; + + xmit_spi(token); /* Xmit data token */ + if (token != 0xFD) { /* Is data token */ + wc = 0; + do { /* Xmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Reveive data response */ + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return RT_FALSE; + } + + return RT_TRUE; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t send_cmd ( + rt_uint8_t cmd, /* Command byte */ + rt_uint32_t arg /* Argument */ +) +{ + rt_uint8_t n, res; + + + if (wait_ready() != 0xFF) return 0xFF; + + /* Send command packet */ + xmit_spi(cmd); /* Command */ + xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ + n = 0; + if (cmd == CMD0) n = 0x95; /* CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + res = rcvr_spi(); + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ +static +DSTATUS sdcard_initialize ( + rt_uint8_t drv /* Physical drive nmuber (0) */ +) +{ + rt_uint8_t n, ty, ocr[4]; + + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on */ + send_initial_clock_train(); + + SELECT(); /* CS = L */ + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 msec */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDC Ver2+ */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ + do { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0) break; /* ACMD41 with HCS bit */ + } while (Timer1); + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? 6 : 2; + } + } + } else { /* SDC Ver1 or MMC */ + ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */ + do { + if (ty == 2) { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break; /* ACMD41 */ + } else { + if (send_cmd(CMD1, 0) == 0) break; /* CMD1 */ + } + } while (Timer1); + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Select R/W block length */ + ty = 0; + } + } + CardType = ty; + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + if (ty) { /* Initialization succeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + set_max_speed(); + } else { /* Initialization failed */ + power_off(); + } + + return Stat; +} + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ +static +DRESULT sdcard_read ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t *buff, /* Pointer to the data buffer to store read data */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block read */ + if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ + && rcvr_datablock(buff, 512)) + count = 0; + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) break; + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +static +DRESULT sdcard_write ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + const rt_uint8_t *buff, /* Pointer to the data to be written */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block write */ + if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buff, 0xFE)) + count = 0; + } + else { /* Multiple block write */ + if (CardType & 2) { + send_cmd(CMD55, 0); send_cmd(CMD23, count); /* ACMD23 */ + } + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ +static +DRESULT sdcard_ioctl ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + rt_uint8_t n, csd[16], *ptr = buff; + rt_uint16_t csize; + + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (*ptr) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + if (chk_power()) + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code == 1 (POWER_ON) */ + power_on(); /* Power on */ + res = RES_OK; + break; + case 2: /* Sub control code == 2 (POWER_GET) */ + *(ptr+1) = (rt_uint8_t)chk_power(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) return RES_NOTRDY; + + SELECT(); /* CS = L */ + + switch (ctrl) { + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (rt_uint32_t) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ + csize = csd[9] + ((rt_uint16_t)csd[8] << 8) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << 10; + } else { /* MMC or SDC ver 1.XX */ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((rt_uint16_t)csd[7] << 2) + ((rt_uint16_t)(csd[6] & 3) << 10) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << (n - 9); + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get sectors on the disk (rt_uint16_t) */ + *(rt_uint16_t*)buff = 512; + res = RES_OK; + break; + + case CTRL_SYNC : /* Make sure that data has been written */ + if (wait_ready() == 0xFF) + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 0; n < 4; n++) + *ptr++ = rcvr_spi(); + res = RES_OK; + } + +// case MMC_GET_TYPE : /* Get card type flags (1 byte) */ +// *ptr = CardType; +// res = RES_OK; +// break; + + default: + res = RES_PARERR; + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + } + + return res; +} + +/* + * RT-Thread SD Card Driver + * 20090705 Yi.Qiu + */ +#include +#include + +struct rt_device sdcard_device; +struct dfs_partition part; + +/* RT-Thread Device Driver Interface */ +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + DRESULT status; + + status = sdcard_read(0, buffer, part.offset + pos, size); + if (status != RES_OK) + { + rt_kprintf("sd card read failed\n"); + return 0; + } + + return size; +} + +static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + DRESULT status; + + status = sdcard_write(0, buffer, part.offset + pos, size); + if (status != RES_OK) + { + rt_kprintf("sd card write failed\n"); + return 0; + } + + return size; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +void rt_hw_sdcard_init(void) +{ + if (sdcard_initialize(0) == RES_OK) + { + DRESULT status; + rt_uint8_t *sector; + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + status = sdcard_read(0, sector, 0, 1); + if (status == RES_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + { + /* there is no partition */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sdcard device */ + sdcard_device.type = RT_Device_Class_Block; + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; + + /* no private */ + sdcard_device.user_data = RT_NULL; + + rt_device_register(&sdcard_device, "sd0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + return; + } + rt_kprintf("sdcard init failed\n"); +} + diff --git a/bsp/lm3s9b9x/drivers/sdram.c b/bsp/lm3s9b9x/drivers/sdram.c new file mode 100644 index 0000000000..62798659a9 --- /dev/null +++ b/bsp/lm3s9b9x/drivers/sdram.c @@ -0,0 +1,256 @@ +//***************************************************************************** +// +// sdram.c - Example demonstrating how to configure the EPI bus in SDRAM +// mode. +// +// Copyright (c) 2010 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 5961 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#include +#include +#include + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_epi.h" +#include "inc/hw_gpio.h" +#include "driverlib/epi.h" +#include "driverlib/gpio.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +//! \addtogroup epi_examples_list +//!

EPI SDRAM Mode (sdram)

+//! +//! This example shows how to configure the EPI bus in SDRAM mode. This +//! example has been written to be compatible with the Texas Instruments 8MB +//! SDRAM expansion card for the DK-LM3S9B96. +//! +//! For the EPI SDRAM mode, the pinout is as follows: +//! Address11:0 - EPI0S11:0 +//! Bank1:0 - EPI0S14:13 +//! Data15:0 - EPI0S15:0 +//! DQML - EPI0S16 +//! DQMH - EPI0S17 +//! /CAS - EPI0S18 +//! /RAS - EPI0S19 +//! /WE - EPI0S28 +//! /CS - EPI0S29 +//! SDCKE - EPI0S30 +//! SDCLK - EPI0S31 +//! +//! This example uses the following peripherals and I/O signals. You must +//! review these and change as needed for your own board: +//! - EPI0 peripheral +//! - GPIO Port C peripheral (for EPI0 pins) +//! - GPIO Port E peripheral (for EPI0 pins) +//! - GPIO Port F peripheral (for EPI0 pins) +//! - GPIO Port G peripheral (for EPI0 pins) +//! - GPIO Port H peripheral (for EPI0 pins) +//! - GPIO Port J peripheral (for EPI0 pins) +//! - EPI0S0 - PH3 +//! - EPI0S1 - PH2 +//! - EPI0S2 - PC4 +//! - EPI0S3 - PC5 +//! - EPI0S4 - PC6 +//! - EPI0S5 - PC7 +//! - EPI0S6 - PH0 +//! - EPI0S7 - PH1 +//! - EPI0S8 - PE0 +//! - EPI0S9 - PE1 +//! - EPI0S10 - PH4 +//! - EPI0S11 - PH5 +//! - EPI0S12 - PF4 +//! - EPI0S13 - PG0 +//! - EPI0S14 - PG1 +//! - EPI0S15 - PF5 +//! - EPI0S16 - PJ0 +//! - EPI0S17 - PJ1 +//! - EPI0S18 - PJ2 +//! - EPI0S19 - PJ3 +//! - EPI0S28 - PJ4 +//! - EPI0S29 - PJ5 +//! - EPI0S30 - PJ6 +//! - EPI0S31 - PG7 +//! +//! The following UART signals are configured only for displaying console +//! messages for this example. These are not required for operation of EPI0. +//! - UART0 peripheral +//! - GPIO Port A peripheral (for UART0 pins) +//! - UART0RX - PA0 +//! - UART0TX - PA1 +//! +//! This example uses the following interrupt handlers. To use this example +//! in your own application you must add these interrupt handlers to your +//! vector table. +//! - None. +//! +// +//***************************************************************************** + +//***************************************************************************** +// +// Use the following to specify the GPIO pins used by the SDRAM EPI bus. +// +//***************************************************************************** +#define EPI_PORTC_PINS (GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4) +#define EPI_PORTE_PINS (GPIO_PIN_1 | GPIO_PIN_0) +#define EPI_PORTF_PINS (GPIO_PIN_5 | GPIO_PIN_4) +#define EPI_PORTG_PINS (GPIO_PIN_7 | GPIO_PIN_1 | GPIO_PIN_0) +#define EPI_PORTH_PINS (GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2 | \ + GPIO_PIN_1 | GPIO_PIN_0) +#define EPI_PORTJ_PINS (GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | \ + GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0) + +//***************************************************************************** +// +// The starting and ending address for the 8MB SDRAM chip (4Meg x 16bits) on +// the SDRAM daughter board. +// +//***************************************************************************** +#define SDRAM_START_ADDRESS 0x000000 +#define SDRAM_END_ADDRESS 0x3FFFFF + +//***************************************************************************** +// + +//***************************************************************************** +// +// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a +// simple C array. This example shows how to read and write to an SDRAM card +// using the EPI bus in SDRAM mode. +// +//***************************************************************************** +void rt_hw_sdram_init(void) +{ + // + // The EPI0 peripheral must be enabled for use. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0); + + // + // For this example EPI0 is used with multiple pins on PortC, E, F, G, H, + // and J. The actual port and pins used may be different on your part, + // consult the data sheet for more information. + // TODO: change this to whichever GPIO port you are using. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); + + // + // This step configures the internal pin muxes to set the EPI pins for use + // with EPI. This step is only required because the default function of + // these pins may not be to function in EPI mode. Please reference the + // datasheet for more information about pin muxing. Note that EPI0S27:20 + // are not used for the EPI SDRAM implementation. + // TODO: change this to select the port/pin you are using. + // + GPIOPinConfigure(GPIO_PH3_EPI0S0); + GPIOPinConfigure(GPIO_PH2_EPI0S1); + GPIOPinConfigure(GPIO_PC4_EPI0S2); + GPIOPinConfigure(GPIO_PC5_EPI0S3); + GPIOPinConfigure(GPIO_PC6_EPI0S4); + GPIOPinConfigure(GPIO_PC7_EPI0S5); + GPIOPinConfigure(GPIO_PH0_EPI0S6); + GPIOPinConfigure(GPIO_PH1_EPI0S7); + GPIOPinConfigure(GPIO_PE0_EPI0S8); + GPIOPinConfigure(GPIO_PE1_EPI0S9); + GPIOPinConfigure(GPIO_PH4_EPI0S10); + GPIOPinConfigure(GPIO_PH5_EPI0S11); + GPIOPinConfigure(GPIO_PF4_EPI0S12); + GPIOPinConfigure(GPIO_PG0_EPI0S13); + GPIOPinConfigure(GPIO_PG1_EPI0S14); + GPIOPinConfigure(GPIO_PF5_EPI0S15); + GPIOPinConfigure(GPIO_PJ0_EPI0S16); + GPIOPinConfigure(GPIO_PJ1_EPI0S17); + GPIOPinConfigure(GPIO_PJ2_EPI0S18); + GPIOPinConfigure(GPIO_PJ3_EPI0S19); + GPIOPinConfigure(GPIO_PJ4_EPI0S28); + GPIOPinConfigure(GPIO_PJ5_EPI0S29); + GPIOPinConfigure(GPIO_PJ6_EPI0S30); + GPIOPinConfigure(GPIO_PG7_EPI0S31); + + // + // Configure the GPIO pins for EPI mode. All the EPI pins require 8mA + // drive strength in push-pull operation. This step also gives control of + // pins to the EPI module. + // TODO: change this to select the port/pin you are using. + // + GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS); + GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS); + GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS); + GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS); + GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS); + GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS); + + // + // Sets the clock divider for the EPI module. In this case set the + // divider to 0, making the EPIClock = SysClk. + // + EPIDividerSet(EPI0_BASE, 1); + + // + // Sets the usage mode of the EPI module. For this example we will use + // the SDRAM mode to talk to the external 8MB SDRAM daughter card. + // + EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM); + + // + // Configure the SDRAM mode. We configure the SDRAM according to our core + // clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz + // range (i.e 16Mhz crystal). We will use the normal (or full power) + // operating state which means we will not use the low power self-refresh + // state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of + // 1024 clock ticks. + // TODO: change this to select the proper clock frequency and SDRAM + // refresh counter. + // + EPIConfigSDRAMSet(EPI0_BASE, EPI_SDRAM_CORE_FREQ_15_30 | + EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024); + + // + // Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF. + // For this example, we will start from a base address of 0x60000000 with + // a size of 16MB. We use 16MB so we have the ability to access the + // entire 8MB SDRAM daughter card. Since there is no 8MB option, so we + // use the next closest one. If you attempt to access an address higher + // than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of + // of addresses by 16-bits of data) a fault will not occur since we + // configured the EPI for 16MB addressability. In the case that you do + // access an address higher than 0x3FFFFF, the MSb of the address gets + // ignored. + // + EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6); + + // + // Wait for the SDRAM wake-up to complete by polling the SDRAM + // initialization sequence bit. This bit is true when the SDRAM interface + // is going through the initialization and false when the SDRAM interface + // it is not in a wake-up period. + // + while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ) + { + } +} diff --git a/bsp/lm3s9b9x/drivers/serial.c b/bsp/lm3s9b9x/drivers/serial.c new file mode 100644 index 0000000000..8572814925 --- /dev/null +++ b/bsp/lm3s9b9x/drivers/serial.c @@ -0,0 +1,362 @@ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-06-11 Bernard first version + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "board.h" + +extern void rt_hw_interrupt_thread_switch(void); + +#define RT_UART_RX_BUFFER_SIZE 64 + +/* LM3S serial device */ +struct rt_lm3s_serial +{ + /* inherit from device */ + struct rt_device parent; + + rt_uint32_t hw_base; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; + +#ifdef RT_USING_UART1 +struct rt_lm3s_serial serial1; +#endif +#ifdef RT_USING_UART2 +struct rt_lm3s_serial serial2; +#endif + +void rt_hw_serial_init(void); + +void rt_hw_uart_isr(struct rt_lm3s_serial* serial) +{ + rt_device_t device; + rt_uint32_t status; + + device = (struct rt_device*)serial; + status = UARTIntStatus(serial->hw_base, true); + + /* clear interrupt status */ + UARTIntClear(serial->hw_base, status); + + if (device->flag & RT_DEVICE_FLAG_INT_RX) + { + char ch; + rt_base_t level; + + while (UARTCharsAvail(serial->hw_base)) + { + ch = UARTCharGetNonBlocking(serial->hw_base); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + serial->rx_buffer[serial->save_index] = ch; + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if(device->rx_indicate != RT_NULL) + { + rt_int32_t length; + + length = serial->save_index - serial->read_index; + if (length < 0) length += RT_UART_RX_BUFFER_SIZE; + device->rx_indicate(device, length); + } + } +} + +#ifdef RT_USING_UART1 +void rt_hw_uart_isr_1(int irqno) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* get serial device */ + rt_hw_uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} +#endif + +#ifdef RT_USING_UART2 +void rt_hw_uart_isr_2(int irqno) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* get serial device */ + rt_hw_uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} +#endif + +/** + * @addtogroup LM3S + */ +/*@{*/ + +static rt_err_t rt_serial_init (rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; + + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + if (serial->hw_base == UART0_BASE) + IntEnable(INT_UART0); + else if (serial->hw_base == UART1_BASE) + IntEnable(INT_UART1); + + UARTIntEnable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_lm3s_serial* serial; + serial = (struct rt_lm3s_serial*) dev; + + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UARTIntDisable(serial->hw_base, UART_INT_RX | UART_INT_RT); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_lm3s_serial *serial = (struct rt_lm3s_serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + while (size) + { + *ptr = UARTCharGetNonBlocking(serial->hw_base); + + ptr ++; size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + struct rt_lm3s_serial* serial; + char *ptr; + + serial = (struct rt_lm3s_serial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + while (UARTCharPutNonBlocking(serial->hw_base, '\r') == false); + + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (UARTCharPutNonBlocking(serial->hw_base, *ptr) == false); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_hw_serial_init(void) +{ + struct rt_lm3s_serial* serial; + +#ifdef RT_USING_UART1 + serial = &serial1; + + serial->parent.type = RT_Device_Class_Char; + + serial->hw_base = UART0_BASE; + serial->baudrate = 115200; + + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; + + /* enable UART0 clock */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* set UART0 pinmux */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial->baudrate, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); + + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; + + rt_device_register(&serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + +#ifdef RT_USING_UART2 + serial = &serial2; + + serial->parent.type = RT_Device_Class_Char; + + serial->hw_base = 0xE0010000; + serial->baudrate = 115200; + + rt_memset(serial->rx_buffer, 0, sizeof(serial->rx_buffer)); + serial->read_index = serial->save_index = 0; + + serial->parent.init = rt_serial_init; + serial->parent.open = rt_serial_open; + serial->parent.close = rt_serial_close; + serial->parent.read = rt_serial_read; + serial->parent.write = rt_serial_write; + serial->parent.control = rt_serial_control; + serial->parent.user_data = RT_NULL; + + rt_device_register(&serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif +} + +/*@}*/ diff --git a/bsp/lm3s9b9x/luminaryif.c b/bsp/lm3s9b9x/luminaryif.c deleted file mode 100644 index 0e20c6dd50..0000000000 --- a/bsp/lm3s9b9x/luminaryif.c +++ /dev/null @@ -1,490 +0,0 @@ -//***************************************************************************** -// -// luminaryif.c - Ethernet Interface File for lwIP TCP/IP Stack -// -//***************************************************************************** - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "lwipopts.h" -#include "luminaryif.h" - -#define MAX_ADDR_LEN 6 - -struct net_device -{ - /* inherit from ethernet device */ - struct eth_device parent; - - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ -}; - -static struct net_device luminaryif_dev_entry; -static struct net_device *luminaryif_dev =&luminaryif_dev_entry; -static struct rt_semaphore tx_sem; - -//***************************************************************************** -// -// Sanity Check: This module will NOT work if the following defines -// are incorrect. -// -//***************************************************************************** -#if (PBUF_LINK_HLEN != 16) -#error "Incorrect PBUF_LINK_HLEN specified!" -#endif -#if (ETH_PAD_SIZE != 2) -#error "Incorrect ETH_PAD_SIZE specified!" -#endif -#if (PBUF_POOL_BUFSIZE % 4) -#error "PBUF_POOL_BUFSIZE must be modulo 4!" -#endif - -/* RT-Thread Device Interface */ - -/* initialize the interface */ -//***************************************************************************** -// -// Low-Level initialization function for the Ethernet Controller. -// -//***************************************************************************** -rt_err_t luminaryif_init(rt_device_t dev) -{ - unsigned long ulTemp; - - // - // Disable all Ethernet Interrupts. - // - EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | - ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | - ETH_INT_RX)); - ulTemp = EthernetIntStatus(ETH_BASE, false); - EthernetIntClear(ETH_BASE, ulTemp); - - // - // Initialize the Ethernet Controller. - // - EthernetInitExpClk(ETH_BASE, SysCtlClockGet()); - - // - // Configure the Ethernet Controller for normal operation. - // - Enable TX Duplex Mode - // - Enable TX Padding - // - Enable TX CRC Generation - // - EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | - ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN)); - - // - // Enable the Ethernet Controller transmitter and receiver. - // - EthernetEnable(ETH_BASE); - - // - // Enable the Ethernet Interrupt handler. - // - IntEnable(INT_ETH); - - // - // Enable Ethernet TX and RX Packet Interrupts. - // - EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX); - - return RT_EOK; -} - -void luminaryif_isr(void) -{ - unsigned long ulTemp; - - // - // Read and Clear the interrupt. - // - ulTemp = EthernetIntStatus(ETH_BASE, false); - EthernetIntClear(ETH_BASE, ulTemp); - - // - // Check to see if an RX Interrupt has occured. - // - if(ulTemp & ETH_INT_RX) - { - // - // Indicate that a packet has been received. - // - rt_err_t result; - - /* a frame has been received */ - result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent)); - - if(result != RT_EOK) rt_set_errno(-RT_ERROR); - - // - // Disable Ethernet RX Interrupt. - // - EthernetIntDisable(ETH_BASE, ETH_INT_RX); - } - if(ulTemp & ETH_INT_TX) - { - /* A frame has been transmitted. */ - rt_sem_release(&tx_sem); - } - -} - -/* control the interface */ -rt_err_t luminaryif_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, luminaryif_dev_entry.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -/* Open the ethernet interface */ -rt_err_t luminaryif_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -/* Close the interface */ -rt_err_t luminaryif_close(rt_device_t dev) -{ - return RT_EOK; -} - -/* Read */ -rt_size_t luminaryif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -/* Write */ -rt_size_t luminaryif_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -//**************************************************************************** -// -// Low-Level transmit routine. Should do the actual transmission of the -// packet. The packet is contained in the pbuf that is passed to the function. -// This pbuf might be chained. -// -//**************************************************************************** -rt_err_t luminaryif_tx(rt_device_t dev, struct pbuf *p) -{ - int iBuf; - unsigned char *pucBuf; - unsigned long *pulBuf; - struct pbuf *q; - int iGather; - unsigned long ulGather; - unsigned char *pucGather; - unsigned long ulTemp; - - /* lock tx operation */ - rt_sem_take(&tx_sem, RT_WAITING_FOREVER); - - // - // Wait for space available in the TX FIFO. - // - while(!EthernetSpaceAvail(ETH_BASE)) - { - } - -// - // Fill in the first two bytes of the payload data (configured as padding - // with ETH_PAD_SIZE = 2) with the total length of the payload data - // (minus the Ethernet MAC layer header). - // - *((unsigned short *)(p->payload)) = p->tot_len - 16; - - // - // Initialize the gather register. - // - iGather = 0; - pucGather = (unsigned char *)&ulGather; - ulGather = 0; - - // - // Copy data from the pbuf(s) into the TX Fifo. - // - for(q = p; q != NULL; q = q->next) - { - // - // Intialize a char pointer and index to the pbuf payload data. - // - pucBuf = (unsigned char *)q->payload; - iBuf = 0; - - // - // If the gather buffer has leftover data from a previous pbuf - // in the chain, fill it up and write it to the Tx FIFO. - // - while((iBuf < q->len) && (iGather != 0)) - { - // - // Copy a byte from the pbuf into the gather buffer. - // - pucGather[iGather] = pucBuf[iBuf++]; - - // - // Increment the gather buffer index modulo 4. - // - iGather = ((iGather + 1) % 4); - } - - // - // If the gather index is 0 and the pbuf index is non-zero, - // we have a gather buffer to write into the Tx FIFO. - // - if((iGather == 0) && (iBuf != 0)) - { - HWREG(ETH_BASE + MAC_O_DATA) = ulGather; - ulGather = 0; - } - - // - // Copy words of pbuf data into the Tx FIFO, but don't go past - // the end of the pbuf. - // - if((iBuf % 4) != 0) - { - while((iBuf + 4) <= q->len) - { - ulTemp = (pucBuf[iBuf++] << 0); - ulTemp |= (pucBuf[iBuf++] << 8); - ulTemp |= (pucBuf[iBuf++] << 16); - ulTemp |= (pucBuf[iBuf++] << 24); - HWREG(ETH_BASE + MAC_O_DATA) = ulTemp; - } - } - else - { - // - // Initialze a long pointer into the pbuf for 32-bit access. - // - pulBuf = (unsigned long *)&pucBuf[iBuf]; - - while((iBuf + 4) <= q->len) - { - HWREG(ETH_BASE + MAC_O_DATA) = *pulBuf++; - iBuf += 4; - } - } - // - // Check if leftover data in the pbuf and save it in the gather - // buffer for the next time. - // - while(iBuf < q->len) - { - // - // Copy a byte from the pbuf into the gather buffer. - // - pucGather[iGather] = pucBuf[iBuf++]; - - // - // Increment the gather buffer index modulo 4. - // - iGather = ((iGather + 1) % 4); - } - } - - // - // Send any leftover data to the FIFO. - // - HWREG(ETH_BASE + MAC_O_DATA) = ulGather; - - // - // Wakeup the transmitter. - // - HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX; - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif - - return(ERR_OK); -} - -//***************************************************************************** -// -// Low-Level receive routine. Should allocate a pbuf and transfer the bytes -// of the incoming packet from the interface into the pbuf. -// -//***************************************************************************** -struct pbuf * luminaryif_rx(rt_device_t dev) -{ - struct pbuf *p, *q; - u16_t len; - unsigned long ulTemp; - int i; - unsigned long *ptr; - - if(!EthernetPacketAvail(ETH_BASE)) - { - // - // Enable Ethernet RX Interrupt. - // - EthernetIntEnable(ETH_BASE, ETH_INT_RX); - - return(NULL); - } - - // - // Obtain the size of the packet and put it into the "len" variable. - // Note: The length returned in the FIFO length position includes the - // two bytes for the length + the 4 bytes for the FCS. - // - ulTemp = HWREG(ETH_BASE + MAC_O_DATA); - len = ulTemp & 0xFFFF; - - // - // We allocate a pbuf chain of pbufs from the pool. - // - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - - if(p != NULL) - { - // - // Place the first word into the first pbuf location. - // - *(unsigned long *)p->payload = ulTemp; - p->payload = (char *)(p->payload) + 4; - p->len -= 4; - - // - // Process all but the last buffer in the pbuf chain. - // - q = p; - while(q != NULL) - { - // - // Setup a byte pointer into the payload section of the pbuf. - // - ptr = q->payload; - - // - // Read data from FIFO into the current pbuf - // (assume pbuf length is modulo 4) - // - for(i = 0; i < q->len; i += 4) - { - *ptr++ = HWREG(ETH_BASE + MAC_O_DATA); - } - - // - // Link in the next pbuf in the chain. - // - q = q->next; - } - - // - // Restore the first pbuf parameters to their original values. - // - p->payload = (char *)(p->payload) - 4; - p->len += 4; - -#if LINK_STATS - lwip_stats.link.recv++; -#endif - } - else - { - // - // Just read all of the remaining data from the FIFO and dump it. - // - for(i = 4; i < len; i+=4) - { - ulTemp = HWREG(ETH_BASE + MAC_O_DATA); - } - -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif - } - - return(p); -} - -int rt_hw_luminaryif_init(void) -{ - rt_err_t result; - unsigned long ulUser0, ulUser1; - - /* Enable and Reset the Ethernet Controller. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); - SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); - - /* - Enable Port F for Ethernet LEDs. - LED0 Bit 3 Output - LED1 Bit 2 Output - */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); - /* GPIODirModeSet and GPIOPadConfigSet */ - GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3); - GPIOPinConfigure(GPIO_PF2_LED1); - GPIOPinConfigure(GPIO_PF3_LED0); - - FlashUserSet(0x00371200, 0x00563412); /* OUI:00-12-37 (hex) Texas Instruments, only for test */ - /* Configure the hardware MAC address */ - FlashUserGet(&ulUser0, &ulUser1); - if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff)) - { - rt_kprintf("Fatal error in geting MAC address\n"); - } - - /* init rt-thread device interface */ - luminaryif_dev_entry.parent.parent.init = luminaryif_init; - luminaryif_dev_entry.parent.parent.open = luminaryif_open; - luminaryif_dev_entry.parent.parent.close = luminaryif_close; - luminaryif_dev_entry.parent.parent.read = luminaryif_read; - luminaryif_dev_entry.parent.parent.write = luminaryif_write; - luminaryif_dev_entry.parent.parent.control = luminaryif_control; - luminaryif_dev_entry.parent.eth_rx = luminaryif_rx; - luminaryif_dev_entry.parent.eth_tx = luminaryif_tx; - - /* - Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC - address needed to program the hardware registers, then program the MAC - address into the Ethernet Controller registers. - */ - luminaryif_dev_entry.dev_addr[0] = ((ulUser0 >> 0) & 0xff); - luminaryif_dev_entry.dev_addr[1] = ((ulUser0 >> 8) & 0xff); - luminaryif_dev_entry.dev_addr[2] = ((ulUser0 >> 16) & 0xff); - luminaryif_dev_entry.dev_addr[3] = ((ulUser1 >> 0) & 0xff); - luminaryif_dev_entry.dev_addr[4] = ((ulUser1 >> 8) & 0xff); - luminaryif_dev_entry.dev_addr[5] = ((ulUser1 >> 16) & 0xff); - - /* Program the hardware with it's MAC address (for filtering). */ - EthernetMACAddrSet(ETH_BASE, luminaryif_dev_entry.dev_addr); - - rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); - - result = eth_device_init(&(luminaryif_dev->parent), "E0"); - - return result; -} - diff --git a/bsp/lm3s9b9x/luminaryif.h b/bsp/lm3s9b9x/luminaryif.h deleted file mode 100644 index e987daea5e..0000000000 --- a/bsp/lm3s9b9x/luminaryif.h +++ /dev/null @@ -1,12 +0,0 @@ -//***************************************************************************** -// -// luminaryif.h - Prototypes for the Luminary Micro Ethernet interface. -// -//***************************************************************************** - -#ifndef __LUMINARYIF_H__ -#define __LUMINARYIF_H__ - -int rt_hw_luminaryif_init(void); - -#endif // __LUMINARYIF_H__ diff --git a/bsp/lm3s9b9x/project.Uv2 b/bsp/lm3s9b9x/project.Uv2 index ff5c69bc01..874832b584 100644 --- a/bsp/lm3s9b9x/project.Uv2 +++ b/bsp/lm3s9b9x/project.Uv2 @@ -3,121 +3,115 @@ Target (RT-Thread-lm3s), 0x0004 // Tools: 'ARM-ADS' -Group (Startup) +Group (Applications) +Group (Drivers) +Group (Libraries) Group (Kernel) -Group (LM3S) +Group (CORTEX-M3) Group (finsh) Group (LwIP) -Group (library) -File 1,1,<.\application.c> -File 1,1,<.\startup.c> -File 1,1,<.\board.c> -File 1,1,<.\sdram.c> -File 1,1,<.\luminaryif.c> -File 2,1,<..\..\src\clock.c> -File 2,1,<..\..\src\device.c> -File 2,1,<..\..\src\idle.c> -File 2,1,<..\..\src\ipc.c> -File 2,1,<..\..\src\irq.c> -File 2,1,<..\..\src\kservice.c> -File 2,1,<..\..\src\mem.c> -File 2,1,<..\..\src\mempool.c> -File 2,1,<..\..\src\module.c> -File 2,1,<..\..\src\object.c> -File 2,1,<..\..\src\rtm.c> -File 2,1,<..\..\src\scheduler.c> -File 2,1,<..\..\src\slab.c> -File 2,1,<..\..\src\thread.c> -File 2,1,<..\..\src\timer.c> -File 3,1,<..\..\libcpu\arm\lm3s\cpu.c> -File 3,1,<..\..\libcpu\arm\lm3s\fault.c> -File 3,1,<..\..\libcpu\arm\lm3s\interrupt.c> -File 3,1,<..\..\libcpu\arm\lm3s\serial.c> -File 3,1,<..\..\libcpu\arm\lm3s\stack.c> -File 3,2,<..\..\libcpu\arm\lm3s\context_rvds.S> -File 3,2,<..\..\libcpu\arm\lm3s\fault_rvds.S> -File 3,2,<..\..\libcpu\arm\lm3s\start_rvds.S> -File 3,1,<..\..\libcpu\arm\common\backtrace.c> -File 3,1,<..\..\libcpu\arm\common\div0.c> -File 3,1,<..\..\libcpu\arm\common\showmem.c> -File 4,1,<..\..\components\finsh\cmd.c> -File 4,1,<..\..\components\finsh\finsh_compiler.c> -File 4,1,<..\..\components\finsh\finsh_error.c> -File 4,1,<..\..\components\finsh\finsh_heap.c> -File 4,1,<..\..\components\finsh\finsh_init.c> -File 4,1,<..\..\components\finsh\finsh_node.c> -File 4,1,<..\..\components\finsh\finsh_ops.c> -File 4,1,<..\..\components\finsh\finsh_parser.c> -File 4,1,<..\..\components\finsh\finsh_token.c> -File 4,1,<..\..\components\finsh\finsh_var.c> -File 4,1,<..\..\components\finsh\finsh_vm.c> -File 4,1,<..\..\components\finsh\shell.c> -File 4,1,<..\..\components\finsh\symbol.c> -File 5,1,<..\..\components\net\lwip\src\api\api_lib.c> -File 5,1,<..\..\components\net\lwip\src\api\api_msg.c> -File 5,1,<..\..\components\net\lwip\src\api\err.c> -File 5,1,<..\..\components\net\lwip\src\api\netbuf.c> -File 5,1,<..\..\components\net\lwip\src\api\netdb.c> -File 5,1,<..\..\components\net\lwip\src\api\netifapi.c> -File 5,1,<..\..\components\net\lwip\src\api\sockets.c> -File 5,1,<..\..\components\net\lwip\src\api\tcpip.c> -File 5,1,<..\..\components\net\lwip\src\arch\sys_arch.c> -File 5,1,<..\..\components\net\lwip\src\arch\sys_arch_init.c> -File 5,1,<..\..\components\net\lwip\src\core\dhcp.c> -File 5,1,<..\..\components\net\lwip\src\core\dns.c> -File 5,1,<..\..\components\net\lwip\src\core\init.c> -File 5,1,<..\..\components\net\lwip\src\core\memp.c> -File 5,1,<..\..\components\net\lwip\src\core\netif.c> -File 5,1,<..\..\components\net\lwip\src\core\pbuf.c> -File 5,1,<..\..\components\net\lwip\src\core\raw.c> -File 5,1,<..\..\components\net\lwip\src\core\stats.c> -File 5,1,<..\..\components\net\lwip\src\core\sys.c> -File 5,1,<..\..\components\net\lwip\src\core\tcp.c> -File 5,1,<..\..\components\net\lwip\src\core\tcp_in.c> -File 5,1,<..\..\components\net\lwip\src\core\tcp_out.c> -File 5,1,<..\..\components\net\lwip\src\core\udp.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\autoip.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\icmp.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\igmp.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\inet.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\ip.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c> -File 5,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c> -File 5,1,<..\..\components\net\lwip\src\netif\etharp.c> -File 5,1,<..\..\components\net\lwip\src\netif\ethernetif.c> -File 5,1,<..\..\components\net\lwip\src\netif\loopif.c> -File 5,1,<..\..\components\net\lwip\src\netif\slipif.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\mib2.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c> -File 5,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c> -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, -File 6,1, +File 1,1, +File 1,1, +File 2,1, +File 2,1, +File 2,1, +File 2,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 3,2, +File 4,1,<..\..\src\clock.c> +File 4,1,<..\..\src\device.c> +File 4,1,<..\..\src\idle.c> +File 4,1,<..\..\src\ipc.c> +File 4,1,<..\..\src\irq.c> +File 4,1,<..\..\src\kservice.c> +File 4,1,<..\..\src\mem.c> +File 4,1,<..\..\src\mempool.c> +File 4,1,<..\..\src\object.c> +File 4,1,<..\..\src\scheduler.c> +File 4,1,<..\..\src\thread.c> +File 4,1,<..\..\src\timer.c> +File 5,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> +File 5,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> +File 5,1,<..\..\libcpu\arm\common\backtrace.c> +File 5,1,<..\..\libcpu\arm\common\div0.c> +File 5,1,<..\..\libcpu\arm\common\showmem.c> +File 6,1,<..\..\components\finsh\cmd.c> +File 6,1,<..\..\components\finsh\finsh_compiler.c> +File 6,1,<..\..\components\finsh\finsh_error.c> +File 6,1,<..\..\components\finsh\finsh_heap.c> +File 6,1,<..\..\components\finsh\finsh_init.c> +File 6,1,<..\..\components\finsh\finsh_node.c> +File 6,1,<..\..\components\finsh\finsh_ops.c> +File 6,1,<..\..\components\finsh\finsh_parser.c> +File 6,1,<..\..\components\finsh\finsh_token.c> +File 6,1,<..\..\components\finsh\finsh_var.c> +File 6,1,<..\..\components\finsh\finsh_vm.c> +File 6,1,<..\..\components\finsh\shell.c> +File 6,1,<..\..\components\finsh\symbol.c> +File 7,1,<..\..\components\net\lwip\src\api\api_lib.c> +File 7,1,<..\..\components\net\lwip\src\api\api_msg.c> +File 7,1,<..\..\components\net\lwip\src\api\err.c> +File 7,1,<..\..\components\net\lwip\src\api\netbuf.c> +File 7,1,<..\..\components\net\lwip\src\api\netdb.c> +File 7,1,<..\..\components\net\lwip\src\api\netifapi.c> +File 7,1,<..\..\components\net\lwip\src\api\sockets.c> +File 7,1,<..\..\components\net\lwip\src\api\tcpip.c> +File 7,1,<..\..\components\net\lwip\src\arch\sys_arch.c> +File 7,1,<..\..\components\net\lwip\src\arch\sys_arch_init.c> +File 7,1,<..\..\components\net\lwip\src\core\dhcp.c> +File 7,1,<..\..\components\net\lwip\src\core\dns.c> +File 7,1,<..\..\components\net\lwip\src\core\init.c> +File 7,1,<..\..\components\net\lwip\src\core\memp.c> +File 7,1,<..\..\components\net\lwip\src\core\netif.c> +File 7,1,<..\..\components\net\lwip\src\core\pbuf.c> +File 7,1,<..\..\components\net\lwip\src\core\raw.c> +File 7,1,<..\..\components\net\lwip\src\core\stats.c> +File 7,1,<..\..\components\net\lwip\src\core\sys.c> +File 7,1,<..\..\components\net\lwip\src\core\tcp.c> +File 7,1,<..\..\components\net\lwip\src\core\tcp_in.c> +File 7,1,<..\..\components\net\lwip\src\core\tcp_out.c> +File 7,1,<..\..\components\net\lwip\src\core\udp.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\autoip.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\icmp.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\igmp.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\inet.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\ip.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c> +File 7,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c> +File 7,1,<..\..\components\net\lwip\src\netif\etharp.c> +File 7,1,<..\..\components\net\lwip\src\netif\ethernetif.c> +File 7,1,<..\..\components\net\lwip\src\netif\loopif.c> +File 7,1,<..\..\components\net\lwip\src\netif\slipif.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\mib2.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c> +File 7,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c> Options 1,0,0 // Target 'RT-Thread-lm3s' @@ -145,7 +139,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' EnvReg (Luminary\) OrgReg (Luminary\) TgStat=16 - OutDir (.\objs\) + OutDir (.\build\) OutName (rtthread-lm3s) GenApp=1 GenLib=0 @@ -167,7 +161,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ACPUTYP ("Cortex-M3") RVDEV () - ADSTFLGA { 0,12,0,2,163,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSTFLGA { 0,12,0,0,163,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } OCMADSIRAM { 0,0,0,0,32,0,128,1,0 } OCMADSIROM { 1,0,0,0,0,0,0,4,0 } @@ -178,7 +172,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' ADSCMISC () ADSCDEFN () ADSCUDEF () - ADSCINCD (Libraries\inc;..\..\libcpu\arm\lm3s;..\..\components\net\lwip\src\include;Libraries\driverlib;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;Libraries;..\..\components\net\lwip\src\arch\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif) + ADSCINCD (..\..\components\net\lwip\src\include\ipv4;..\..\include;drivers;..\..\components\net\lwip\src\include;.;Libraries;applications;..\..\components\net\lwip\src\arch\include;..\..\libcpu\arm\cortex-m3;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSAMISC () ADSADEFN () @@ -210,20 +204,3 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' FLASH4 () EndOpt -Options 1,1,1 // File 'application.c' - PropFld { 2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=2 - AlwaysBuild=2 - GenAsm=2 - AsmAsm=2 - PublicsOnly=2 - StopCode=11 - CustArgs () - LibMods () - ADSCCFLG { 6,84,85,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSCMISC () - ADSCDEFN () - ADSCUDEF () - ADSCINCD () -EndOpt - diff --git a/bsp/lm3s9b9x/rtconfig.py b/bsp/lm3s9b9x/rtconfig.py index 1fdb67c4bb..caef9a28a4 100644 --- a/bsp/lm3s9b9x/rtconfig.py +++ b/bsp/lm3s9b9x/rtconfig.py @@ -1,6 +1,6 @@ # toolchains options ARCH='arm' -CPU='lm3s' +CPU='cortex-m3' CROSS_TOOL = 'keil' if CROSS_TOOL == 'gcc': diff --git a/bsp/lm3s9b9x/sdcard.c b/bsp/lm3s9b9x/sdcard.c deleted file mode 100644 index 785f2eaf3e..0000000000 --- a/bsp/lm3s9b9x/sdcard.c +++ /dev/null @@ -1,781 +0,0 @@ -/*-----------------------------------------------------------------------*/ -/* MMC/SDC (in SPI mode) control module (C)ChaN, 2007 */ -/*-----------------------------------------------------------------------*/ -/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ -/* are platform dependent. */ -/*-----------------------------------------------------------------------*/ - -/* - * This file was modified from a sample available from the FatFs - * web site. It was modified to work with a Luminary Micro - * EK-LM3S6965 evaluation board. - * - * Note that the SSI port is shared with the osram display. The code - * in this file does not attempt to share the SSI port with the osram, - * it assumes the osram is not being used. - */ -#include - -#include -#include -#include -#include -#include - -/* Status of Disk Functions */ -typedef rt_uint8_t DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - -/* Disk Status Bits (DSTATUS) */ - -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - -/* Definitions for MMC/SDC command */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ - -/* Command code for disk_ioctrl() */ - -/* Generic command */ -#define CTRL_SYNC 0 /* Mandatory for write functions */ -#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ -#define GET_SECTOR_SIZE 2 /* Mandatory for multiple sector size cfg */ -#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ -#define CTRL_POWER 4 -#define CTRL_LOCK 5 -#define CTRL_EJECT 6 -/* MMC/SDC command */ -#define MMC_GET_TYPE 10 -#define MMC_GET_CSD 11 -#define MMC_GET_CID 12 -#define MMC_GET_OCR 13 -#define MMC_GET_SDSTAT 14 -/* ATA/CF command */ -#define ATA_GET_REV 20 -#define ATA_GET_MODEL 21 -#define ATA_GET_SN 22 - -/* Peripheral definitions for EK-LM3S6965 board */ -// SSI port -#define SDC_SSI_BASE SSI0_BASE -#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0 - -// GPIO for SSI pins -#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE -#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA -#define SDC_SSI_CLK GPIO_PIN_2 -#define SDC_SSI_TX GPIO_PIN_5 -#define SDC_SSI_RX GPIO_PIN_4 -#define SDC_SSI_FSS GPIO_PIN_3 -#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK) - -// GPIO for card chip select -#define SDC_CS_GPIO_PORT_BASE GPIO_PORTG_BASE -#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOG -#define SDC_CS GPIO_PIN_0 - -// asserts the CS pin to the card -static -void SELECT (void) -{ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0); -} - -// de-asserts the CS pin to the card -static -void DESELECT (void) -{ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); -} - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - -static volatile -DSTATUS Stat = STA_NOINIT; /* Disk status */ - -static volatile -rt_uint8_t Timer1, Timer2; /* 100Hz decrement timer */ - -static -rt_uint8_t CardType; /* b0:MMC, b1:SDC, b2:Block addressing */ - -static -rt_uint8_t PowerFlag = 0; /* indicates if "power" is on */ - -/*-----------------------------------------------------------------------*/ -/* Transmit a byte to MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -void xmit_spi (rt_uint8_t dat) -{ - rt_uint32_t rcvdat; - - SSIDataPut(SDC_SSI_BASE, dat); /* Write the data to the tx fifo */ - - SSIDataGet(SDC_SSI_BASE, &rcvdat); /* flush data read during the write */ -} - - -/*-----------------------------------------------------------------------*/ -/* Receive a byte from MMC via SPI (Platform dependent) */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t rcvr_spi (void) -{ - rt_uint32_t rcvdat; - - SSIDataPut(SDC_SSI_BASE, 0xFF); /* write dummy data */ - - SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */ - - return (rt_uint8_t)rcvdat; -} - - -static -void rcvr_spi_m (rt_uint8_t *dst) -{ - *dst = rcvr_spi(); -} - -/*-----------------------------------------------------------------------*/ -/* Wait for card ready */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t wait_ready (void) -{ - rt_uint8_t res; - - - Timer2 = 50; /* Wait for ready in timeout of 500ms */ - rcvr_spi(); - do - res = rcvr_spi(); - while ((res != 0xFF) && Timer2); - - return res; -} - -/*-----------------------------------------------------------------------*/ -/* Send 80 or so clock transitions with CS and DI held high. This is */ -/* required after card power up to get it into SPI mode */ -/*-----------------------------------------------------------------------*/ -static -void send_initial_clock_train(void) -{ - unsigned int i; - rt_uint32_t dat; - - /* Ensure CS is held high. */ - DESELECT(); - - /* Switch the SSI TX line to a GPIO and drive it high too. */ - GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX); - GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX); - - /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ - /* required number of times. */ - for(i = 0 ; i < 10 ; i++) - { - /* Write DUMMY data. SSIDataPut() waits until there is room in the */ - /* FIFO. */ - SSIDataPut(SDC_SSI_BASE, 0xFF); - - /* Flush data read during data write. */ - SSIDataGet(SDC_SSI_BASE, &dat); - } - - /* Revert to hardware control of the SSI TX line. */ - GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX); -} - -/*-----------------------------------------------------------------------*/ -/* Power Control (Platform dependent) */ -/*-----------------------------------------------------------------------*/ -/* When the target system does not support socket power control, there */ -/* is nothing to do in these functions and chk_power always returns 1. */ - -static -void power_on (void) -{ - /* - * This doesn't really turn the power on, but initializes the - * SSI port and pins needed to talk to the card. - */ - - /* Enable the peripherals used to drive the SDC on SSI, and the CS */ - SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH); - SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH); - SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH); - - /* Configure the appropriate pins to be SSI instead of GPIO */ - GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS); - GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS); - GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - /* Deassert the SSI0 chip select */ - GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); - - /* Configure the SSI0 port */ - SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, - SSI_MODE_MASTER, 400000, 8); - SSIEnable(SDC_SSI_BASE); - - /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ - /* to be able to accept a native command. */ - send_initial_clock_train(); - - PowerFlag = 1; -} - -// set the SSI speed to the max setting -static -void set_max_speed(void) -{ - unsigned long i; - - /* Disable the SSI */ - SSIDisable(SDC_SSI_BASE); - - /* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */ - i = SysCtlClockGet() / 2; - if(i > 12500000) - { - i = 12500000; - } - - /* Configure the SSI0 port */ - SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, - SSI_MODE_MASTER, i, 8); - - /* Enable the SSI */ - SSIEnable(SDC_SSI_BASE); -} - -static -void power_off (void) -{ - PowerFlag = 0; -} - -static -int chk_power(void) /* Socket power state: 0=off, 1=on */ -{ - return PowerFlag; -} - - - -/*-----------------------------------------------------------------------*/ -/* Receive a data packet from MMC */ -/*-----------------------------------------------------------------------*/ - -static -rt_bool_t rcvr_datablock ( - rt_uint8_t *buff, /* Data buffer to store received data */ - unsigned int btr /* Byte count (must be even number) */ -) -{ - rt_uint8_t token; - - - Timer1 = 10; - do { /* Wait for data packet in timeout of 100ms */ - token = rcvr_spi(); - } while ((token == 0xFF) && Timer1); - if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ - - do { /* Receive the data block into buffer */ - rcvr_spi_m(buff++); - rcvr_spi_m(buff++); - } while (btr -= 2); - rcvr_spi(); /* Discard CRC */ - rcvr_spi(); - - return RT_TRUE; /* Return with success */ -} - - - -/*-----------------------------------------------------------------------*/ -/* Send a data packet to MMC */ -/*-----------------------------------------------------------------------*/ - -#if _READONLY == 0 -static -rt_bool_t xmit_datablock ( - const rt_uint8_t *buff, /* 512 byte data block to be transmitted */ - rt_uint8_t token /* Data/Stop token */ -) -{ - rt_uint8_t resp, wc; - - - if (wait_ready() != 0xFF) return RT_FALSE; - - xmit_spi(token); /* Xmit data token */ - if (token != 0xFD) { /* Is data token */ - wc = 0; - do { /* Xmit the 512 byte data block to MMC */ - xmit_spi(*buff++); - xmit_spi(*buff++); - } while (--wc); - xmit_spi(0xFF); /* CRC (Dummy) */ - xmit_spi(0xFF); - resp = rcvr_spi(); /* Reveive data response */ - if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - return RT_FALSE; - } - - return RT_TRUE; -} -#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Send a command packet to MMC */ -/*-----------------------------------------------------------------------*/ - -static -rt_uint8_t send_cmd ( - rt_uint8_t cmd, /* Command byte */ - rt_uint32_t arg /* Argument */ -) -{ - rt_uint8_t n, res; - - - if (wait_ready() != 0xFF) return 0xFF; - - /* Send command packet */ - xmit_spi(cmd); /* Command */ - xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ - xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ - xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ - xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ - n = 0; - if (cmd == CMD0) n = 0x95; /* CRC for CMD0(0) */ - if (cmd == CMD8) n = 0x87; /* CRC for CMD8(0x1AA) */ - xmit_spi(n); - - /* Receive command response */ - if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ - n = 10; /* Wait for a valid response in timeout of 10 attempts */ - do - res = rcvr_spi(); - while ((res & 0x80) && --n); - - return res; /* Return with the response value */ -} - - - -/*-------------------------------------------------------------------------- - - Public Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ -static -DSTATUS sdcard_initialize ( - rt_uint8_t drv /* Physical drive nmuber (0) */ -) -{ - rt_uint8_t n, ty, ocr[4]; - - - if (drv) return STA_NOINIT; /* Supports only single drive */ - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - - power_on(); /* Force socket power on */ - send_initial_clock_train(); - - SELECT(); /* CS = L */ - ty = 0; - if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - Timer1 = 100; /* Initialization timeout of 1000 msec */ - if (send_cmd(CMD8, 0x1AA) == 1) { /* SDC Ver2+ */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - do { - if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0) break; /* ACMD41 with HCS bit */ - } while (Timer1); - if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit */ - for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); - ty = (ocr[0] & 0x40) ? 6 : 2; - } - } - } else { /* SDC Ver1 or MMC */ - ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */ - do { - if (ty == 2) { - if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break; /* ACMD41 */ - } else { - if (send_cmd(CMD1, 0) == 0) break; /* CMD1 */ - } - } while (Timer1); - if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Select R/W block length */ - ty = 0; - } - } - CardType = ty; - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - if (ty) { /* Initialization succeded */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - set_max_speed(); - } else { /* Initialization failed */ - power_off(); - } - - return Stat; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ -static -DRESULT sdcard_read ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - rt_uint8_t *buff, /* Pointer to the data buffer to store read data */ - rt_uint32_t sector, /* Start sector number (LBA) */ - rt_uint8_t count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - - if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ - - SELECT(); /* CS = L */ - - if (count == 1) { /* Single block read */ - if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ - && rcvr_datablock(buff, 512)) - count = 0; - } - else { /* Multiple block read */ - if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - do { - if (!rcvr_datablock(buff, 512)) break; - buff += 512; - } while (--count); - send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - } - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - return count ? RES_ERROR : RES_OK; -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -#if _READONLY == 0 -static -DRESULT sdcard_write ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - const rt_uint8_t *buff, /* Pointer to the data to be written */ - rt_uint32_t sector, /* Start sector number (LBA) */ - rt_uint8_t count /* Sector count (1..255) */ -) -{ - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - - if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ - - SELECT(); /* CS = L */ - - if (count == 1) { /* Single block write */ - if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ - && xmit_datablock(buff, 0xFE)) - count = 0; - } - else { /* Multiple block write */ - if (CardType & 2) { - send_cmd(CMD55, 0); send_cmd(CMD23, count); /* ACMD23 */ - } - if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - do { - if (!xmit_datablock(buff, 0xFC)) break; - buff += 512; - } while (--count); - if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - count = 1; - } - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - - return count ? RES_ERROR : RES_OK; -} -#endif /* _READONLY */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ -static -DRESULT sdcard_ioctl ( - rt_uint8_t drv, /* Physical drive nmuber (0) */ - rt_uint8_t ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - DRESULT res; - rt_uint8_t n, csd[16], *ptr = buff; - rt_uint16_t csize; - - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { - switch (*ptr) { - case 0: /* Sub control code == 0 (POWER_OFF) */ - if (chk_power()) - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code == 1 (POWER_ON) */ - power_on(); /* Power on */ - res = RES_OK; - break; - case 2: /* Sub control code == 2 (POWER_GET) */ - *(ptr+1) = (rt_uint8_t)chk_power(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - } - else { - if (Stat & STA_NOINIT) return RES_NOTRDY; - - SELECT(); /* CS = L */ - - switch (ctrl) { - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (rt_uint32_t) */ - if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ - csize = csd[9] + ((rt_uint16_t)csd[8] << 8) + 1; - *(rt_uint32_t*)buff = (rt_uint32_t)csize << 10; - } else { /* MMC or SDC ver 1.XX */ - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - csize = (csd[8] >> 6) + ((rt_uint16_t)csd[7] << 2) + ((rt_uint16_t)(csd[6] & 3) << 10) + 1; - *(rt_uint32_t*)buff = (rt_uint32_t)csize << (n - 9); - } - res = RES_OK; - } - break; - - case GET_SECTOR_SIZE : /* Get sectors on the disk (rt_uint16_t) */ - *(rt_uint16_t*)buff = 512; - res = RES_OK; - break; - - case CTRL_SYNC : /* Make sure that data has been written */ - if (wait_ready() == 0xFF) - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 0; n < 4; n++) - *ptr++ = rcvr_spi(); - res = RES_OK; - } - -// case MMC_GET_TYPE : /* Get card type flags (1 byte) */ -// *ptr = CardType; -// res = RES_OK; -// break; - - default: - res = RES_PARERR; - } - - DESELECT(); /* CS = H */ - rcvr_spi(); /* Idle (Release DO) */ - } - - return res; -} - -/* - * RT-Thread SD Card Driver - * 20090705 Yi.Qiu - */ -#include -#include - -struct rt_device sdcard_device; -struct dfs_partition part; - -/* RT-Thread Device Driver Interface */ -static rt_err_t rt_sdcard_init(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) -{ - - return RT_EOK; -} - -static rt_err_t rt_sdcard_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - DRESULT status; - - status = sdcard_read(0, buffer, part.offset + pos, size); - if (status != RES_OK) - { - rt_kprintf("sd card read failed\n"); - return 0; - } - - return size; -} - -static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - DRESULT status; - - status = sdcard_write(0, buffer, part.offset + pos, size); - if (status != RES_OK) - { - rt_kprintf("sd card write failed\n"); - return 0; - } - - return size; -} - -static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - return RT_EOK; -} - -void rt_hw_sdcard_init(void) -{ - if (sdcard_initialize(0) == RES_OK) - { - DRESULT status; - rt_uint8_t *sector; - - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - return; - } - status = sdcard_read(0, sector, 0, 1); - if (status == RES_OK) - { - /* get the first partition */ - if (dfs_filesystem_get_partition(&part, sector, 0) != 0) - { - /* there is no partition */ - part.offset = 0; - part.size = 0; - } - } - else - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } - - /* release sector buffer */ - rt_free(sector); - - /* register sdcard device */ - sdcard_device.type = RT_Device_Class_Block; - sdcard_device.init = rt_sdcard_init; - sdcard_device.open = rt_sdcard_open; - sdcard_device.close = rt_sdcard_close; - sdcard_device.read = rt_sdcard_read; - sdcard_device.write = rt_sdcard_write; - sdcard_device.control = rt_sdcard_control; - - /* no private */ - sdcard_device.user_data = RT_NULL; - - rt_device_register(&sdcard_device, "sd0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - - return; - } - rt_kprintf("sdcard init failed\n"); -} - diff --git a/bsp/lm3s9b9x/sdram.c b/bsp/lm3s9b9x/sdram.c deleted file mode 100644 index 62798659a9..0000000000 --- a/bsp/lm3s9b9x/sdram.c +++ /dev/null @@ -1,256 +0,0 @@ -//***************************************************************************** -// -// sdram.c - Example demonstrating how to configure the EPI bus in SDRAM -// mode. -// -// Copyright (c) 2010 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 5961 of the Stellaris Firmware Development Package. -// -//***************************************************************************** - -#include -#include -#include - -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_epi.h" -#include "inc/hw_gpio.h" -#include "driverlib/epi.h" -#include "driverlib/gpio.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -//! \addtogroup epi_examples_list -//!

EPI SDRAM Mode (sdram)

-//! -//! This example shows how to configure the EPI bus in SDRAM mode. This -//! example has been written to be compatible with the Texas Instruments 8MB -//! SDRAM expansion card for the DK-LM3S9B96. -//! -//! For the EPI SDRAM mode, the pinout is as follows: -//! Address11:0 - EPI0S11:0 -//! Bank1:0 - EPI0S14:13 -//! Data15:0 - EPI0S15:0 -//! DQML - EPI0S16 -//! DQMH - EPI0S17 -//! /CAS - EPI0S18 -//! /RAS - EPI0S19 -//! /WE - EPI0S28 -//! /CS - EPI0S29 -//! SDCKE - EPI0S30 -//! SDCLK - EPI0S31 -//! -//! This example uses the following peripherals and I/O signals. You must -//! review these and change as needed for your own board: -//! - EPI0 peripheral -//! - GPIO Port C peripheral (for EPI0 pins) -//! - GPIO Port E peripheral (for EPI0 pins) -//! - GPIO Port F peripheral (for EPI0 pins) -//! - GPIO Port G peripheral (for EPI0 pins) -//! - GPIO Port H peripheral (for EPI0 pins) -//! - GPIO Port J peripheral (for EPI0 pins) -//! - EPI0S0 - PH3 -//! - EPI0S1 - PH2 -//! - EPI0S2 - PC4 -//! - EPI0S3 - PC5 -//! - EPI0S4 - PC6 -//! - EPI0S5 - PC7 -//! - EPI0S6 - PH0 -//! - EPI0S7 - PH1 -//! - EPI0S8 - PE0 -//! - EPI0S9 - PE1 -//! - EPI0S10 - PH4 -//! - EPI0S11 - PH5 -//! - EPI0S12 - PF4 -//! - EPI0S13 - PG0 -//! - EPI0S14 - PG1 -//! - EPI0S15 - PF5 -//! - EPI0S16 - PJ0 -//! - EPI0S17 - PJ1 -//! - EPI0S18 - PJ2 -//! - EPI0S19 - PJ3 -//! - EPI0S28 - PJ4 -//! - EPI0S29 - PJ5 -//! - EPI0S30 - PJ6 -//! - EPI0S31 - PG7 -//! -//! The following UART signals are configured only for displaying console -//! messages for this example. These are not required for operation of EPI0. -//! - UART0 peripheral -//! - GPIO Port A peripheral (for UART0 pins) -//! - UART0RX - PA0 -//! - UART0TX - PA1 -//! -//! This example uses the following interrupt handlers. To use this example -//! in your own application you must add these interrupt handlers to your -//! vector table. -//! - None. -//! -// -//***************************************************************************** - -//***************************************************************************** -// -// Use the following to specify the GPIO pins used by the SDRAM EPI bus. -// -//***************************************************************************** -#define EPI_PORTC_PINS (GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4) -#define EPI_PORTE_PINS (GPIO_PIN_1 | GPIO_PIN_0) -#define EPI_PORTF_PINS (GPIO_PIN_5 | GPIO_PIN_4) -#define EPI_PORTG_PINS (GPIO_PIN_7 | GPIO_PIN_1 | GPIO_PIN_0) -#define EPI_PORTH_PINS (GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2 | \ - GPIO_PIN_1 | GPIO_PIN_0) -#define EPI_PORTJ_PINS (GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | \ - GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0) - -//***************************************************************************** -// -// The starting and ending address for the 8MB SDRAM chip (4Meg x 16bits) on -// the SDRAM daughter board. -// -//***************************************************************************** -#define SDRAM_START_ADDRESS 0x000000 -#define SDRAM_END_ADDRESS 0x3FFFFF - -//***************************************************************************** -// - -//***************************************************************************** -// -// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a -// simple C array. This example shows how to read and write to an SDRAM card -// using the EPI bus in SDRAM mode. -// -//***************************************************************************** -void rt_hw_sdram_init(void) -{ - // - // The EPI0 peripheral must be enabled for use. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0); - - // - // For this example EPI0 is used with multiple pins on PortC, E, F, G, H, - // and J. The actual port and pins used may be different on your part, - // consult the data sheet for more information. - // TODO: change this to whichever GPIO port you are using. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); - - // - // This step configures the internal pin muxes to set the EPI pins for use - // with EPI. This step is only required because the default function of - // these pins may not be to function in EPI mode. Please reference the - // datasheet for more information about pin muxing. Note that EPI0S27:20 - // are not used for the EPI SDRAM implementation. - // TODO: change this to select the port/pin you are using. - // - GPIOPinConfigure(GPIO_PH3_EPI0S0); - GPIOPinConfigure(GPIO_PH2_EPI0S1); - GPIOPinConfigure(GPIO_PC4_EPI0S2); - GPIOPinConfigure(GPIO_PC5_EPI0S3); - GPIOPinConfigure(GPIO_PC6_EPI0S4); - GPIOPinConfigure(GPIO_PC7_EPI0S5); - GPIOPinConfigure(GPIO_PH0_EPI0S6); - GPIOPinConfigure(GPIO_PH1_EPI0S7); - GPIOPinConfigure(GPIO_PE0_EPI0S8); - GPIOPinConfigure(GPIO_PE1_EPI0S9); - GPIOPinConfigure(GPIO_PH4_EPI0S10); - GPIOPinConfigure(GPIO_PH5_EPI0S11); - GPIOPinConfigure(GPIO_PF4_EPI0S12); - GPIOPinConfigure(GPIO_PG0_EPI0S13); - GPIOPinConfigure(GPIO_PG1_EPI0S14); - GPIOPinConfigure(GPIO_PF5_EPI0S15); - GPIOPinConfigure(GPIO_PJ0_EPI0S16); - GPIOPinConfigure(GPIO_PJ1_EPI0S17); - GPIOPinConfigure(GPIO_PJ2_EPI0S18); - GPIOPinConfigure(GPIO_PJ3_EPI0S19); - GPIOPinConfigure(GPIO_PJ4_EPI0S28); - GPIOPinConfigure(GPIO_PJ5_EPI0S29); - GPIOPinConfigure(GPIO_PJ6_EPI0S30); - GPIOPinConfigure(GPIO_PG7_EPI0S31); - - // - // Configure the GPIO pins for EPI mode. All the EPI pins require 8mA - // drive strength in push-pull operation. This step also gives control of - // pins to the EPI module. - // TODO: change this to select the port/pin you are using. - // - GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS); - GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS); - GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS); - GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS); - GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS); - GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS); - - // - // Sets the clock divider for the EPI module. In this case set the - // divider to 0, making the EPIClock = SysClk. - // - EPIDividerSet(EPI0_BASE, 1); - - // - // Sets the usage mode of the EPI module. For this example we will use - // the SDRAM mode to talk to the external 8MB SDRAM daughter card. - // - EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM); - - // - // Configure the SDRAM mode. We configure the SDRAM according to our core - // clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz - // range (i.e 16Mhz crystal). We will use the normal (or full power) - // operating state which means we will not use the low power self-refresh - // state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of - // 1024 clock ticks. - // TODO: change this to select the proper clock frequency and SDRAM - // refresh counter. - // - EPIConfigSDRAMSet(EPI0_BASE, EPI_SDRAM_CORE_FREQ_15_30 | - EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024); - - // - // Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF. - // For this example, we will start from a base address of 0x60000000 with - // a size of 16MB. We use 16MB so we have the ability to access the - // entire 8MB SDRAM daughter card. Since there is no 8MB option, so we - // use the next closest one. If you attempt to access an address higher - // than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of - // of addresses by 16-bits of data) a fault will not occur since we - // configured the EPI for 16MB addressability. In the case that you do - // access an address higher than 0x3FFFFF, the MSb of the address gets - // ignored. - // - EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6); - - // - // Wait for the SDRAM wake-up to complete by polling the SDRAM - // initialization sequence bit. This bit is true when the SDRAM interface - // is going through the initialization and false when the SDRAM interface - // it is not in a wake-up period. - // - while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ) - { - } -} diff --git a/bsp/lm3s9b9x/startup.c b/bsp/lm3s9b9x/startup.c deleted file mode 100644 index 942ac439aa..0000000000 --- a/bsp/lm3s9b9x/startup.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -#ifdef RT_USING_LWIP -#include -#include -#endif - -/** - * @addtogroup LM3S - */ - -extern void rt_hw_serial_init(void); - -/*@{*/ -#ifdef RT_USING_FINSH -extern void finsh_system_init(void); -extern void finsh_set_device(char* device); -#endif - -extern int rt_application_init(void); -extern void rt_hw_sdcard_init(void); -extern int rt_hw_luminaryif_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -#ifdef DEBUG -/******************************************************************************* -* Function Name : assert_failed -* Description : Reports the name of the source file and the source line number -* where the assert error has occurred. -* Input : - file: pointer to the source file name -* - line: assert error line source number -* Output : None -* Return : None -*******************************************************************************/ -void __error__(char* file, unsigned long line) -{ - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); - - while (1) ; -} -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP -#if LM3S_EXT_SRAM == 1 - /* init sdram */ - rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END); -#else -#ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END); -#elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)LM3S_SRAM_END); -#else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END); -#endif -#endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_LWIP - eth_system_device_init(); - - /* register ethernetif device */ - rt_hw_luminaryif_init(); -#endif - - /* init hardware serial device */ - rt_hw_serial_init(); -#ifdef RT_USING_DFS - /* init sd card device */ - rt_hw_sdcard_init(); -#endif - /* init all device */ - rt_device_init_all(); - - /* init application */ - rt_application_init(); - -#ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); -#ifdef RT_USING_DEVICE - finsh_set_device("uart1"); -#endif -#endif - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/lm3s9b9x/template.Uv2 b/bsp/lm3s9b9x/template.Uv2 index 8b67ec8a52..d557f53836 100644 --- a/bsp/lm3s9b9x/template.Uv2 +++ b/bsp/lm3s9b9x/template.Uv2 @@ -31,14 +31,14 @@ Options 1,0,0 // Target 'RT-Thread-lm3s' EnvReg (Luminary\) OrgReg (Luminary\) TgStat=16 - OutDir (.\objs\) + OutDir (.\build\) OutName (rtthread-lm3s) GenApp=1 GenLib=0 GenHex=0 Debug=1 Browse=1 - LstDir (.\objs\) + LstDir (.\build\) HexSel=1 MG32K=0 TGMORE=0 diff --git a/bsp/lpc176x/project.Uv2 b/bsp/lpc176x/project.Uv2 index 576f998fa6..01510dfaff 100644 --- a/bsp/lpc176x/project.Uv2 +++ b/bsp/lpc176x/project.Uv2 @@ -5,7 +5,7 @@ Target (RT-Thread LPC17xx), 0x0004 // Tools: 'ARM-ADS' Group (Startup) Group (Kernel) -Group (LPC17XX) +Group (CORTEX-M3) Group (finsh) Group (LwIP) Group (CMSIS) @@ -16,20 +16,20 @@ File 1,1,<.\board.c> File 1,1,<.\uart.c> File 1,1,<.\led.c> File 1,1,<.\emac.c> +File 2,1,<..\..\src\clock.c> File 2,1,<..\..\src\device.c> -File 2,1,<..\..\src\thread.c> -File 2,1,<..\..\src\scheduler.c> -File 2,1,<..\..\src\timer.c> +File 2,1,<..\..\src\idle.c> +File 2,1,<..\..\src\ipc.c> File 2,1,<..\..\src\irq.c> File 2,1,<..\..\src\kservice.c> -File 2,1,<..\..\src\clock.c> -File 2,1,<..\..\src\object.c> -File 2,1,<..\..\src\mempool.c> -File 2,1,<..\..\src\ipc.c> -File 2,1,<..\..\src\idle.c> File 2,1,<..\..\src\mem.c> -File 3,1,<..\..\libcpu\arm\lpc17xx\cpuport.c> -File 3,2,<..\..\libcpu\arm\lpc17xx\context_rvds.S> +File 2,1,<..\..\src\mempool.c> +File 2,1,<..\..\src\object.c> +File 2,1,<..\..\src\scheduler.c> +File 2,1,<..\..\src\thread.c> +File 2,1,<..\..\src\timer.c> +File 3,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> +File 3,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> File 3,1,<..\..\libcpu\arm\common\backtrace.c> File 3,1,<..\..\libcpu\arm\common\div0.c> File 3,1,<..\..\libcpu\arm\common\showmem.c> @@ -144,7 +144,7 @@ Options 1,0,0 // Target 'RT-Thread LPC17xx' ADSCMISC () ADSCDEFN () ADSCUDEF () - ADSCINCD (..\..\components\net\lwip\src\include\ipv4;..\..\components\net\lwip\src\arch\include;CMSIS\CM3\DeviceSupport\NXP\LPC17xx;..\..\components\net\lwip\src\include;.;..\..\libcpu\arm\lpc17xx;..\..\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;CMSIS\CM3\CoreSupport;..\..\components\finsh;..\..\components\net\lwip\src\include\netif) + ADSCINCD (..\..\components\net\lwip\src\arch\include;CMSIS\CM3\DeviceSupport\NXP\LPC17xx;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\components\net\lwip\src;..\..\libcpu\arm\common;CMSIS\CM3\CoreSupport;..\..\components\finsh;..\..\components\net\lwip\src\include\netif) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSAMISC () ADSADEFN () diff --git a/bsp/lpc176x/project.ewp b/bsp/lpc176x/project.ewp index 588b9355c0..dcdc5f164f 100644 --- a/bsp/lpc176x/project.ewp +++ b/bsp/lpc176x/project.ewp @@ -10,7 +10,7 @@ General 3 - 18 + 17 1 1 + - ICCARM 2 - 26 + 21 1 1 + + - - - - - - - - - - - - AARM 2 - 8 + 7 1 1 + @@ -880,7 +810,7 @@ General 3 - 18 + 17 1 0 + - ICCARM 2 - 26 + 21 1 0 + + - - - - - - - - - - - - AARM 2 - 8 + 7 1 0 + @@ -1757,21 +1617,9 @@ $PROJ_DIR$\.\led.c - - $PROJ_DIR$\.\sd.c - - - $PROJ_DIR$\.\spi.c - $PROJ_DIR$\.\emac.c - - $PROJ_DIR$\CMSIS\CM3\CoreSupport\core_cm3.c - - - $PROJ_DIR$\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c - Kernel @@ -1799,21 +1647,12 @@ $PROJ_DIR$\..\..\src\mempool.c - - $PROJ_DIR$\..\..\src\module.c - $PROJ_DIR$\..\..\src\object.c - - $PROJ_DIR$\..\..\src\rtm.c - $PROJ_DIR$\..\..\src\scheduler.c - - $PROJ_DIR$\..\..\src\slab.c - $PROJ_DIR$\..\..\src\thread.c @@ -1822,27 +1661,12 @@ - LPC17XX - - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\cpu.c - - - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\fault.c - + CORTEX-M3 - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\interrupt.c + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\stack.c - - - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\context_iar.S - - - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\fault_iar.S - - - $PROJ_DIR$\..\..\libcpu\arm\lpc17xx\start_iar.S + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c @@ -1854,27 +1678,6 @@ $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c - - Filesystem - - $PROJ_DIR$\..\..\components\dfs\src\dfs.c - - - $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c - - - $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c - - - $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c - - - $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c - - finsh @@ -2025,4 +1828,16 @@ $PROJ_DIR$\..\..\components\net\lwip\src\netif\slipif.c + + CMSIS + + $PROJ_DIR$\CMSIS\CM3\CoreSupport\core_cm3.c + + + $PROJ_DIR$\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c + + + $PROJ_DIR$\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\iar\startup_LPC17xx.s + + diff --git a/bsp/lpc176x/rtconfig.py b/bsp/lpc176x/rtconfig.py index 678522f928..11c425ff93 100644 --- a/bsp/lpc176x/rtconfig.py +++ b/bsp/lpc176x/rtconfig.py @@ -1,6 +1,6 @@ # toolchains options ARCH='arm' -CPU='lpc17xx' +CPU='cortex-m3' CROSS_TOOL='keil' if CROSS_TOOL == 'gcc': diff --git a/bsp/lpc176x/template.ewp b/bsp/lpc176x/template.ewp index 6c0a5e60e8..3f66c77438 100644 --- a/bsp/lpc176x/template.ewp +++ b/bsp/lpc176x/template.ewp @@ -12,7 +12,7 @@ General 3 - 18 + 17 1 1 + - ICCARM 2 - 26 + 21 1 1 + + - - - - - - - - - - - - AARM 2 - 8 + 7 1 1 + @@ -868,7 +800,7 @@ General 3 - 18 + 17 1 0 + - ICCARM 2 - 26 + 21 1 0 + + - - - - - - - - - - - - AARM 2 - 8 + 7 1 0 + -- cgit v1.3.1